[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / suspend_64.c

/*
 * Suspend support specific for i386.
 *
 * Distribute under GPLv2
 *
 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
 */

#include <linux/smp.h>
#include <linux/suspend.h>
#include <asm/proto.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mtrr.h>

/* References to section boundaries */
extern const void __nosave_begin, __nosave_end;

struct saved_context saved_context;

unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
unsigned long saved_context_eflags;

void __save_processor_state(struct saved_context *ctxt)
{
	kernel_fpu_begin();

	/*
	 * descriptor tables
	 */
	asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
	asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
	asm volatile ("str %0"  : "=m" (ctxt->tr));

	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
	/*
	 * segment registers
	 */
	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));

	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	mtrr_save_fixed_ranges(NULL);

	/*
	 * control registers 
	 */
	rdmsrl(MSR_EFER, ctxt->efer);
	ctxt->cr0 = read_cr0();
	ctxt->cr2 = read_cr2();
	ctxt->cr3 = read_cr3();
	ctxt->cr4 = read_cr4();
	ctxt->cr8 = read_cr8();
}

void save_processor_state(void)
{
	__save_processor_state(&saved_context);
}

static void do_fpu_end(void)
{
	/*
	 * Restore FPU regs if necessary
	 */
	kernel_fpu_end();
}

void __restore_processor_state(struct saved_context *ctxt)
{
	/*
	 * control registers
	 */
	wrmsrl(MSR_EFER, ctxt->efer);
	write_cr8(ctxt->cr8);
	write_cr4(ctxt->cr4);
	write_cr3(ctxt->cr3);
	write_cr2(ctxt->cr2);
	write_cr0(ctxt->cr0);

	/*
	 * now restore the descriptor tables to their proper values
	 * ltr is done i fix_processor_context().
	 */
	asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
	asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));

	/*
	 * segment registers
	 */
	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	load_gs_index(ctxt->gs);
	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));

	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);

	fix_processor_context();

	do_fpu_end();
	mtrr_ap_init();
}

void restore_processor_state(void)
{
	__restore_processor_state(&saved_context);
}

void fix_processor_context(void)
{
	int cpu = smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);

	set_tss_desc(cpu,t);	/* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */

	cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;

	syscall_init();                         /* This sets MSR_*STAR and related */
	load_TR_desc();				/* This does ltr */
	load_LDT(&current->active_mm->context);	/* This does lldt */

	/*
	 * Now maybe reload the debug registers
	 */
	if (current->thread.debugreg7){
                loaddebug(&current->thread, 0);
                loaddebug(&current->thread, 1);
                loaddebug(&current->thread, 2);
                loaddebug(&current->thread, 3);
                /* no 4 and 5 */
                loaddebug(&current->thread, 6);
                loaddebug(&current->thread, 7);
	}

}

#ifdef CONFIG_HIBERNATION
/* Defined in arch/x86_64/kernel/suspend_asm.S */
extern int restore_image(void);

/*
 * Address to jump to in the last phase of restore in order to get to the image
 * kernel's text (this value is passed in the image header).
 */
unsigned long restore_jump_address;

/*
 * Value of the cr3 register from before the hibernation (this value is passed
 * in the image header).
 */
unsigned long restore_cr3;

pgd_t *temp_level4_pgt;

void *relocated_restore_code;

static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
{
	long i, j;

	i = pud_index(address);
	pud = pud + i;
	for (; i < PTRS_PER_PUD; pud++, i++) {
		unsigned long paddr;
		pmd_t *pmd;

		paddr = address + i*PUD_SIZE;
		if (paddr >= end)
			break;

		pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
		if (!pmd)
			return -ENOMEM;
		set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
		for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
			unsigned long pe;

			if (paddr >= end)
				break;
			pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
			pe &= __supported_pte_mask;
			set_pmd(pmd, __pmd(pe));
		}
	}
	return 0;
}

static int res_kernel_text_pud_init(pud_t *pud, unsigned long start)
{
	pmd_t *pmd;
	unsigned long paddr;

	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	if (!pmd)
		return -ENOMEM;
	set_pud(pud + pud_index(start), __pud(__pa(pmd) | _KERNPG_TABLE));
	for (paddr = 0; paddr < KERNEL_TEXT_SIZE; pmd++, paddr += PMD_SIZE) {
		unsigned long pe;

		pe = __PAGE_KERNEL_LARGE_EXEC | _PAGE_GLOBAL | paddr;
		pe &= __supported_pte_mask;
		set_pmd(pmd, __pmd(pe));
	}

	return 0;
}

static int set_up_temporary_mappings(void)
{
	unsigned long start, end, next;
	pud_t *pud;
	int error;

	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	if (!temp_level4_pgt)
		return -ENOMEM;

	/* Set up the direct mapping from scratch */
	start = (unsigned long)pfn_to_kaddr(0);
	end = (unsigned long)pfn_to_kaddr(end_pfn);

	for (; start < end; start = next) {
		pud = (pud_t *)get_safe_page(GFP_ATOMIC);
		if (!pud)
			return -ENOMEM;
		next = start + PGDIR_SIZE;
		if (next > end)
			next = end;
		if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
			return error;
		set_pgd(temp_level4_pgt + pgd_index(start),
			mk_kernel_pgd(__pa(pud)));
	}

	/* Set up the kernel text mapping from scratch */
	pud = (pud_t *)get_safe_page(GFP_ATOMIC);
	if (!pud)
		return -ENOMEM;
	error = res_kernel_text_pud_init(pud, __START_KERNEL_map);
	if (!error)
		set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
			__pgd(__pa(pud) | _PAGE_TABLE));

	return error;
}

int swsusp_arch_resume(void)
{
	int error;

	/* We have got enough memory and from now on we cannot recover */
	if ((error = set_up_temporary_mappings()))
		return error;

	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	if (!relocated_restore_code)
		return -ENOMEM;
	memcpy(relocated_restore_code, &core_restore_code,
	       &restore_registers - &core_restore_code);

	restore_image();
	return 0;
}

/*
 *	pfn_is_nosave - check if given pfn is in the 'nosave' section
 */

int pfn_is_nosave(unsigned long pfn)
{
	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
}

struct restore_data_record {
	unsigned long jump_address;
	unsigned long cr3;
	unsigned long magic;
};

#define RESTORE_MAGIC	0x0123456789ABCDEFUL

/**
 *	arch_hibernation_header_save - populate the architecture specific part
 *		of a hibernation image header
 *	@addr: address to save the data at
 */
int arch_hibernation_header_save(void *addr, unsigned int max_size)
{
	struct restore_data_record *rdr = addr;

	if (max_size < sizeof(struct restore_data_record))
		return -EOVERFLOW;
	rdr->jump_address = restore_jump_address;
	rdr->cr3 = restore_cr3;
	rdr->magic = RESTORE_MAGIC;
	return 0;
}

/**
 *	arch_hibernation_header_restore - read the architecture specific data
 *		from the hibernation image header
 *	@addr: address to read the data from
 */
int arch_hibernation_header_restore(void *addr)
{
	struct restore_data_record *rdr = addr;

	restore_jump_address = rdr->jump_address;
	restore_cr3 = rdr->cr3;
	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
}
#endif /* CONFIG_HIBERNATION */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Suspend support specific for i386.
	3	*
	4	* Distribute under GPLv2
	5	*
	6	* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
	7	* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
	8	*/
	9
55679edb	10	#include <linux/smp.h>
1da177e4	11	#include <linux/suspend.h>
1da177e4	12	#include <asm/proto.h>
3dd08325 RW	13	#include <asm/page.h>
3dd08325 RW	14	#include <asm/pgtable.h>
3ebad590	15	#include <asm/mtrr.h>
1da177e4	16
49c3df6a VG	17	/* References to section boundaries */
	18	extern const void __nosave_begin, __nosave_end;
	19
1da177e4 LT	20	struct saved_context saved_context;
	21
	22	unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx;
	23	unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi;
	24	unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11;
	25	unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15;
	26	unsigned long saved_context_eflags;
	27
	28	void __save_processor_state(struct saved_context *ctxt)
	29	{
	30	kernel_fpu_begin();
	31
	32	/*
	33	* descriptor tables
	34	*/
	35	asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
	36	asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
1da177e4 LT	37	asm volatile ("str %0" : "=m" (ctxt->tr));
	38
	39	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
1da177e4 LT	40	/*
	41	* segment registers
	42	*/
	43	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
	44	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
	45	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
	46	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
	47	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
	48
	49	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
	50	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
	51	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
3ebad590	52	mtrr_save_fixed_ranges(NULL);
1da177e4 LT	53
	54	/*
	55	* control registers
	56	*/
3c321bce	57	rdmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	58	ctxt->cr0 = read_cr0();
	59	ctxt->cr2 = read_cr2();
	60	ctxt->cr3 = read_cr3();
	61	ctxt->cr4 = read_cr4();
	62	ctxt->cr8 = read_cr8();
1da177e4 LT	63	}
	64
	65	void save_processor_state(void)
	66	{
	67	__save_processor_state(&saved_context);
	68	}
	69
08967f94	70	static void do_fpu_end(void)
1da177e4	71	{
08967f94 SL	72	/*
	73	* Restore FPU regs if necessary
	74	*/
	75	kernel_fpu_end();
1da177e4 LT	76	}
	77
	78	void __restore_processor_state(struct saved_context *ctxt)
	79	{
	80	/*
	81	* control registers
	82	*/
3c321bce	83	wrmsrl(MSR_EFER, ctxt->efer);
f51c9452 GOC	84	write_cr8(ctxt->cr8);
	85	write_cr4(ctxt->cr4);
	86	write_cr3(ctxt->cr3);
	87	write_cr2(ctxt->cr2);
	88	write_cr0(ctxt->cr0);
1da177e4	89
8d783b3e PM	90	/*
	91	* now restore the descriptor tables to their proper values
	92	* ltr is done i fix_processor_context().
	93	*/
	94	asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
	95	asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
	96
1da177e4 LT	97	/*
	98	* segment registers
	99	*/
	100	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
	101	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
	102	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
	103	load_gs_index(ctxt->gs);
	104	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
	105
	106	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
	107	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
	108	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
	109
1da177e4 LT	110	fix_processor_context();
	111
	112	do_fpu_end();
3b520b23	113	mtrr_ap_init();
1da177e4 LT	114	}
	115
	116	void restore_processor_state(void)
	117	{
	118	__restore_processor_state(&saved_context);
	119	}
	120
	121	void fix_processor_context(void)
	122	{
	123	int cpu = smp_processor_id();
	124	struct tss_struct *t = &per_cpu(init_tss, cpu);
	125
3a4fa0a2	126	set_tss_desc(cpu,t); /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
1da177e4	127
c11efdf9	128	cpu_gdt(cpu)[GDT_ENTRY_TSS].type = 9;
1da177e4 LT	129
	130	syscall_init(); /* This sets MSR_STAR and related /
	131	load_TR_desc(); /* This does ltr */
	132	load_LDT(&current->active_mm->context); /* This does lldt */
	133
	134	/*
	135	* Now maybe reload the debug registers
	136	*/
	137	if (current->thread.debugreg7){
	138	loaddebug(&current->thread, 0);
	139	loaddebug(&current->thread, 1);
	140	loaddebug(&current->thread, 2);
	141	loaddebug(&current->thread, 3);
	142	/* no 4 and 5 */
	143	loaddebug(&current->thread, 6);
	144	loaddebug(&current->thread, 7);
	145	}
	146
	147	}
	148
b0cb1a19	149	#ifdef CONFIG_HIBERNATION
3dd08325 RW	150	/* Defined in arch/x86_64/kernel/suspend_asm.S */
3dd08325 RW	151	extern int restore_image(void);
1da177e4	152
d158cbdf RW	153	/*
	154	* Address to jump to in the last phase of restore in order to get to the image
	155	* kernel's text (this value is passed in the image header).
	156	*/
	157	unsigned long restore_jump_address;
	158
c30bb68c RW	159	/*
	160	* Value of the cr3 register from before the hibernation (this value is passed
	161	* in the image header).
	162	*/
	163	unsigned long restore_cr3;
	164
3dd08325 RW	165	pgd_t *temp_level4_pgt;
3dd08325 RW	166
d158cbdf RW	167	void *relocated_restore_code;
d158cbdf RW	168
2c1b4a5c	169	static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
3dd08325 RW	170	{
	171	long i, j;
	172
	173	i = pud_index(address);
	174	pud = pud + i;
	175	for (; i < PTRS_PER_PUD; pud++, i++) {
	176	unsigned long paddr;
	177	pmd_t *pmd;
	178
	179	paddr = address + i*PUD_SIZE;
	180	if (paddr >= end)
	181	break;
	182
2c1b4a5c RW	183	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	184	if (!pmd)
	185	return -ENOMEM;
3dd08325 RW	186	set_pud(pud, __pud(__pa(pmd) \| _KERNPG_TABLE));
	187	for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
	188	unsigned long pe;
	189
	190	if (paddr >= end)
	191	break;
d158cbdf	192	pe = __PAGE_KERNEL_LARGE_EXEC \| paddr;
3dd08325 RW	193	pe &= __supported_pte_mask;
	194	set_pmd(pmd, __pmd(pe));
	195	}
	196	}
2c1b4a5c	197	return 0;
3dd08325 RW	198	}
3dd08325 RW	199
efa4d2fb RW	200	static int res_kernel_text_pud_init(pud_t *pud, unsigned long start)
	201	{
	202	pmd_t *pmd;
	203	unsigned long paddr;
	204
	205	pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
	206	if (!pmd)
	207	return -ENOMEM;
	208	set_pud(pud + pud_index(start), __pud(__pa(pmd) \| _KERNPG_TABLE));
	209	for (paddr = 0; paddr < KERNEL_TEXT_SIZE; pmd++, paddr += PMD_SIZE) {
	210	unsigned long pe;
	211
	212	pe = __PAGE_KERNEL_LARGE_EXEC \| _PAGE_GLOBAL \| paddr;
	213	pe &= __supported_pte_mask;
	214	set_pmd(pmd, __pmd(pe));
	215	}
	216
	217	return 0;
	218	}
	219
2c1b4a5c	220	static int set_up_temporary_mappings(void)
3dd08325 RW	221	{
3dd08325 RW	222	unsigned long start, end, next;
efa4d2fb	223	pud_t *pud;
2c1b4a5c	224	int error;
3dd08325	225
2c1b4a5c RW	226	temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
	227	if (!temp_level4_pgt)
	228	return -ENOMEM;
3dd08325	229
3dd08325 RW	230	/* Set up the direct mapping from scratch */
	231	start = (unsigned long)pfn_to_kaddr(0);
	232	end = (unsigned long)pfn_to_kaddr(end_pfn);
	233
	234	for (; start < end; start = next) {
efa4d2fb	235	pud = (pud_t *)get_safe_page(GFP_ATOMIC);
2c1b4a5c RW	236	if (!pud)
2c1b4a5c RW	237	return -ENOMEM;
3dd08325 RW	238	next = start + PGDIR_SIZE;
	239	if (next > end)
	240	next = end;
2c1b4a5c RW	241	if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
2c1b4a5c RW	242	return error;
3dd08325 RW	243	set_pgd(temp_level4_pgt + pgd_index(start),
	244	mk_kernel_pgd(__pa(pud)));
	245	}
efa4d2fb RW	246
	247	/* Set up the kernel text mapping from scratch */
	248	pud = (pud_t *)get_safe_page(GFP_ATOMIC);
	249	if (!pud)
	250	return -ENOMEM;
	251	error = res_kernel_text_pud_init(pud, __START_KERNEL_map);
	252	if (!error)
	253	set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
	254	__pgd(__pa(pud) \| _PAGE_TABLE));
	255
	256	return error;
3dd08325 RW	257	}
	258
	259	int swsusp_arch_resume(void)
	260	{
2c1b4a5c	261	int error;
3dd08325	262
3dd08325	263	/* We have got enough memory and from now on we cannot recover */
2c1b4a5c RW	264	if ((error = set_up_temporary_mappings()))
2c1b4a5c RW	265	return error;
d158cbdf RW	266
	267	relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
	268	if (!relocated_restore_code)
	269	return -ENOMEM;
	270	memcpy(relocated_restore_code, &core_restore_code,
	271	&restore_registers - &core_restore_code);
	272
3dd08325 RW	273	restore_image();
	274	return 0;
	275	}
49c3df6a VG	276
	277	/*
	278	* pfn_is_nosave - check if given pfn is in the 'nosave' section
	279	*/
	280
	281	int pfn_is_nosave(unsigned long pfn)
	282	{
	283	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
	284	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
	285	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
	286	}
d158cbdf RW	287
	288	struct restore_data_record {
	289	unsigned long jump_address;
c30bb68c RW	290	unsigned long cr3;
c30bb68c RW	291	unsigned long magic;
d158cbdf RW	292	};
	293
	294	#define RESTORE_MAGIC 0x0123456789ABCDEFUL
	295
	296	/**
	297	* arch_hibernation_header_save - populate the architecture specific part
	298	* of a hibernation image header
	299	* @addr: address to save the data at
	300	*/
	301	int arch_hibernation_header_save(void *addr, unsigned int max_size)
	302	{
	303	struct restore_data_record *rdr = addr;
	304
	305	if (max_size < sizeof(struct restore_data_record))
	306	return -EOVERFLOW;
	307	rdr->jump_address = restore_jump_address;
c30bb68c RW	308	rdr->cr3 = restore_cr3;
c30bb68c RW	309	rdr->magic = RESTORE_MAGIC;
d158cbdf RW	310	return 0;
	311	}
	312
	313	/**
	314	* arch_hibernation_header_restore - read the architecture specific data
	315	* from the hibernation image header
	316	* @addr: address to read the data from
	317	*/
	318	int arch_hibernation_header_restore(void *addr)
	319	{
	320	struct restore_data_record *rdr = addr;
	321
	322	restore_jump_address = rdr->jump_address;
c30bb68c RW	323	restore_cr3 = rdr->cr3;
c30bb68c RW	324	return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
d158cbdf	325	}
b0cb1a19	326	#endif /* CONFIG_HIBERNATION */