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Commit | Line | Data |
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1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
4 | * (c) 2008 Cliff Wickman <cpw@sgi.com>, SGI. | |
5 | * | |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b CW |
10 | #include <linux/proc_fs.h> |
11 | #include <linux/kernel.h> | |
12 | ||
1812924b | 13 | #include <asm/mmu_context.h> |
bdbcdd48 | 14 | #include <asm/uv/uv.h> |
1812924b | 15 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 16 | #include <asm/uv/uv_hub.h> |
1812924b | 17 | #include <asm/uv/uv_bau.h> |
b4c286e6 IM |
18 | #include <asm/genapic.h> |
19 | #include <asm/idle.h> | |
b194b120 | 20 | #include <asm/tsc.h> |
99dd8713 | 21 | #include <asm/irq_vectors.h> |
1812924b | 22 | |
1dcdd3d1 | 23 | #include <asm/genapic.h> |
b194b120 | 24 | |
b4c286e6 IM |
25 | static struct bau_control **uv_bau_table_bases __read_mostly; |
26 | static int uv_bau_retry_limit __read_mostly; | |
27 | ||
28 | /* position of pnode (which is nasid>>1): */ | |
29 | static int uv_nshift __read_mostly; | |
30 | ||
31 | static unsigned long uv_mmask __read_mostly; | |
1812924b | 32 | |
dc163a41 IM |
33 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
34 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
1812924b CW |
35 | |
36 | /* | |
37 | * Free a software acknowledge hardware resource by clearing its Pending | |
38 | * bit. This will return a reply to the sender. | |
39 | * If the message has timed out, a reply has already been sent by the | |
40 | * hardware but the resource has not been released. In that case our | |
41 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
42 | * be sent (the hardware will only do one reply per message). | |
43 | */ | |
b194b120 | 44 | static void uv_reply_to_message(int resource, |
b4c286e6 IM |
45 | struct bau_payload_queue_entry *msg, |
46 | struct bau_msg_status *msp) | |
1812924b | 47 | { |
b194b120 | 48 | unsigned long dw; |
1812924b | 49 | |
b194b120 | 50 | dw = (1 << (resource + UV_SW_ACK_NPENDING)) | (1 << resource); |
1812924b CW |
51 | msg->replied_to = 1; |
52 | msg->sw_ack_vector = 0; | |
53 | if (msp) | |
54 | msp->seen_by.bits = 0; | |
b194b120 | 55 | uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw); |
1812924b CW |
56 | } |
57 | ||
58 | /* | |
59 | * Do all the things a cpu should do for a TLB shootdown message. | |
60 | * Other cpu's may come here at the same time for this message. | |
61 | */ | |
b194b120 | 62 | static void uv_bau_process_message(struct bau_payload_queue_entry *msg, |
b4c286e6 | 63 | int msg_slot, int sw_ack_slot) |
1812924b | 64 | { |
1812924b CW |
65 | unsigned long this_cpu_mask; |
66 | struct bau_msg_status *msp; | |
b4c286e6 | 67 | int cpu; |
1812924b CW |
68 | |
69 | msp = __get_cpu_var(bau_control).msg_statuses + msg_slot; | |
70 | cpu = uv_blade_processor_id(); | |
71 | msg->number_of_cpus = | |
72 | uv_blade_nr_online_cpus(uv_node_to_blade_id(numa_node_id())); | |
dc163a41 | 73 | this_cpu_mask = 1UL << cpu; |
1812924b CW |
74 | if (msp->seen_by.bits & this_cpu_mask) |
75 | return; | |
76 | atomic_or_long(&msp->seen_by.bits, this_cpu_mask); | |
77 | ||
78 | if (msg->replied_to == 1) | |
79 | return; | |
80 | ||
81 | if (msg->address == TLB_FLUSH_ALL) { | |
82 | local_flush_tlb(); | |
83 | __get_cpu_var(ptcstats).alltlb++; | |
84 | } else { | |
85 | __flush_tlb_one(msg->address); | |
86 | __get_cpu_var(ptcstats).onetlb++; | |
87 | } | |
88 | ||
89 | __get_cpu_var(ptcstats).requestee++; | |
90 | ||
91 | atomic_inc_short(&msg->acknowledge_count); | |
92 | if (msg->number_of_cpus == msg->acknowledge_count) | |
93 | uv_reply_to_message(sw_ack_slot, msg, msp); | |
1812924b CW |
94 | } |
95 | ||
96 | /* | |
dc163a41 | 97 | * Examine the payload queue on one distribution node to see |
1812924b CW |
98 | * which messages have not been seen, and which cpu(s) have not seen them. |
99 | * | |
100 | * Returns the number of cpu's that have not responded. | |
101 | */ | |
dc163a41 | 102 | static int uv_examine_destination(struct bau_control *bau_tablesp, int sender) |
1812924b | 103 | { |
1812924b CW |
104 | struct bau_payload_queue_entry *msg; |
105 | struct bau_msg_status *msp; | |
b4c286e6 IM |
106 | int count = 0; |
107 | int i; | |
108 | int j; | |
1812924b | 109 | |
dc163a41 IM |
110 | for (msg = bau_tablesp->va_queue_first, i = 0; i < DEST_Q_SIZE; |
111 | msg++, i++) { | |
112 | if ((msg->sending_cpu == sender) && (!msg->replied_to)) { | |
113 | msp = bau_tablesp->msg_statuses + i; | |
114 | printk(KERN_DEBUG | |
115 | "blade %d: address:%#lx %d of %d, not cpu(s): ", | |
116 | i, msg->address, msg->acknowledge_count, | |
117 | msg->number_of_cpus); | |
118 | for (j = 0; j < msg->number_of_cpus; j++) { | |
b4c286e6 | 119 | if (!((1L << j) & msp->seen_by.bits)) { |
dc163a41 IM |
120 | count++; |
121 | printk("%d ", j); | |
122 | } | |
123 | } | |
124 | printk("\n"); | |
125 | } | |
126 | } | |
127 | return count; | |
128 | } | |
129 | ||
130 | /* | |
131 | * Examine the payload queue on all the distribution nodes to see | |
132 | * which messages have not been seen, and which cpu(s) have not seen them. | |
133 | * | |
134 | * Returns the number of cpu's that have not responded. | |
135 | */ | |
136 | static int uv_examine_destinations(struct bau_target_nodemask *distribution) | |
137 | { | |
138 | int sender; | |
139 | int i; | |
140 | int count = 0; | |
141 | ||
1812924b | 142 | sender = smp_processor_id(); |
b4c286e6 | 143 | for (i = 0; i < sizeof(struct bau_target_nodemask) * BITSPERBYTE; i++) { |
b194b120 CW |
144 | if (!bau_node_isset(i, distribution)) |
145 | continue; | |
dc163a41 | 146 | count += uv_examine_destination(uv_bau_table_bases[i], sender); |
1812924b CW |
147 | } |
148 | return count; | |
149 | } | |
150 | ||
b194b120 CW |
151 | /* |
152 | * wait for completion of a broadcast message | |
153 | * | |
154 | * return COMPLETE, RETRY or GIVEUP | |
155 | */ | |
dc163a41 | 156 | static int uv_wait_completion(struct bau_desc *bau_desc, |
b194b120 CW |
157 | unsigned long mmr_offset, int right_shift) |
158 | { | |
159 | int exams = 0; | |
160 | long destination_timeouts = 0; | |
161 | long source_timeouts = 0; | |
162 | unsigned long descriptor_status; | |
163 | ||
164 | while ((descriptor_status = (((unsigned long) | |
165 | uv_read_local_mmr(mmr_offset) >> | |
166 | right_shift) & UV_ACT_STATUS_MASK)) != | |
167 | DESC_STATUS_IDLE) { | |
168 | if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) { | |
169 | source_timeouts++; | |
170 | if (source_timeouts > SOURCE_TIMEOUT_LIMIT) | |
171 | source_timeouts = 0; | |
172 | __get_cpu_var(ptcstats).s_retry++; | |
173 | return FLUSH_RETRY; | |
174 | } | |
175 | /* | |
176 | * spin here looking for progress at the destinations | |
177 | */ | |
178 | if (descriptor_status == DESC_STATUS_DESTINATION_TIMEOUT) { | |
179 | destination_timeouts++; | |
180 | if (destination_timeouts > DESTINATION_TIMEOUT_LIMIT) { | |
181 | /* | |
182 | * returns number of cpus not responding | |
183 | */ | |
184 | if (uv_examine_destinations | |
185 | (&bau_desc->distribution) == 0) { | |
186 | __get_cpu_var(ptcstats).d_retry++; | |
187 | return FLUSH_RETRY; | |
188 | } | |
189 | exams++; | |
190 | if (exams >= uv_bau_retry_limit) { | |
191 | printk(KERN_DEBUG | |
192 | "uv_flush_tlb_others"); | |
193 | printk("giving up on cpu %d\n", | |
194 | smp_processor_id()); | |
195 | return FLUSH_GIVEUP; | |
196 | } | |
197 | /* | |
198 | * delays can hang the simulator | |
199 | udelay(1000); | |
200 | */ | |
201 | destination_timeouts = 0; | |
202 | } | |
203 | } | |
18c07cf5 | 204 | cpu_relax(); |
b194b120 CW |
205 | } |
206 | return FLUSH_COMPLETE; | |
207 | } | |
208 | ||
209 | /** | |
210 | * uv_flush_send_and_wait | |
211 | * | |
212 | * Send a broadcast and wait for a broadcast message to complete. | |
213 | * | |
bdbcdd48 | 214 | * The flush_mask contains the cpus the broadcast was sent to. |
b194b120 | 215 | * |
bdbcdd48 TH |
216 | * Returns NULL if all remote flushing was done. The mask is zeroed. |
217 | * Returns @flush_mask if some remote flushing remains to be done. The | |
218 | * mask will have some bits still set. | |
b194b120 | 219 | */ |
bdbcdd48 TH |
220 | const struct cpumask *uv_flush_send_and_wait(int cpu, int this_blade, |
221 | struct bau_desc *bau_desc, | |
222 | struct cpumask *flush_mask) | |
b194b120 CW |
223 | { |
224 | int completion_status = 0; | |
225 | int right_shift; | |
b194b120 | 226 | int tries = 0; |
b4c286e6 IM |
227 | int blade; |
228 | int bit; | |
b194b120 | 229 | unsigned long mmr_offset; |
b4c286e6 | 230 | unsigned long index; |
b194b120 CW |
231 | cycles_t time1; |
232 | cycles_t time2; | |
233 | ||
234 | if (cpu < UV_CPUS_PER_ACT_STATUS) { | |
235 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
236 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
237 | } else { | |
238 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
239 | right_shift = | |
240 | ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE); | |
241 | } | |
242 | time1 = get_cycles(); | |
243 | do { | |
244 | tries++; | |
dc163a41 IM |
245 | index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) | |
246 | cpu; | |
b194b120 CW |
247 | uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); |
248 | completion_status = uv_wait_completion(bau_desc, mmr_offset, | |
249 | right_shift); | |
250 | } while (completion_status == FLUSH_RETRY); | |
251 | time2 = get_cycles(); | |
252 | __get_cpu_var(ptcstats).sflush += (time2 - time1); | |
253 | if (tries > 1) | |
254 | __get_cpu_var(ptcstats).retriesok++; | |
255 | ||
256 | if (completion_status == FLUSH_GIVEUP) { | |
257 | /* | |
258 | * Cause the caller to do an IPI-style TLB shootdown on | |
259 | * the cpu's, all of which are still in the mask. | |
260 | */ | |
261 | __get_cpu_var(ptcstats).ptc_i++; | |
2749ebe3 | 262 | return flush_mask; |
b194b120 CW |
263 | } |
264 | ||
265 | /* | |
266 | * Success, so clear the remote cpu's from the mask so we don't | |
267 | * use the IPI method of shootdown on them. | |
268 | */ | |
bdbcdd48 | 269 | for_each_cpu(bit, flush_mask) { |
b194b120 CW |
270 | blade = uv_cpu_to_blade_id(bit); |
271 | if (blade == this_blade) | |
272 | continue; | |
bdbcdd48 | 273 | cpumask_clear_cpu(bit, flush_mask); |
b194b120 | 274 | } |
bdbcdd48 TH |
275 | if (!cpumask_empty(flush_mask)) |
276 | return flush_mask; | |
277 | return NULL; | |
b194b120 CW |
278 | } |
279 | ||
1812924b CW |
280 | /** |
281 | * uv_flush_tlb_others - globally purge translation cache of a virtual | |
282 | * address or all TLB's | |
bdbcdd48 | 283 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b CW |
284 | * @mm: mm_struct containing virtual address range |
285 | * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) | |
bdbcdd48 | 286 | * @cpu: the current cpu |
1812924b CW |
287 | * |
288 | * This is the entry point for initiating any UV global TLB shootdown. | |
289 | * | |
290 | * Purges the translation caches of all specified processors of the given | |
291 | * virtual address, or purges all TLB's on specified processors. | |
292 | * | |
bdbcdd48 TH |
293 | * The caller has derived the cpumask from the mm_struct. This function |
294 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 295 | * |
bdbcdd48 | 296 | * The cpumask is converted into a nodemask of the nodes containing |
1812924b | 297 | * the cpus. |
b194b120 | 298 | * |
bdbcdd48 TH |
299 | * Note that this function should be called with preemption disabled. |
300 | * | |
301 | * Returns NULL if all remote flushing was done. | |
302 | * Returns pointer to cpumask if some remote flushing remains to be | |
303 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 304 | */ |
bdbcdd48 TH |
305 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
306 | struct mm_struct *mm, | |
307 | unsigned long va, unsigned int cpu) | |
1812924b | 308 | { |
bdbcdd48 TH |
309 | static DEFINE_PER_CPU(cpumask_t, flush_tlb_mask); |
310 | struct cpumask *flush_mask = &__get_cpu_var(flush_tlb_mask); | |
1812924b | 311 | int i; |
b194b120 | 312 | int bit; |
1812924b | 313 | int blade; |
bdbcdd48 | 314 | int uv_cpu; |
1812924b | 315 | int this_blade; |
b194b120 | 316 | int locals = 0; |
dc163a41 | 317 | struct bau_desc *bau_desc; |
1812924b | 318 | |
bdbcdd48 TH |
319 | WARN_ON(!in_atomic()); |
320 | ||
321 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); | |
322 | ||
323 | uv_cpu = uv_blade_processor_id(); | |
1812924b CW |
324 | this_blade = uv_numa_blade_id(); |
325 | bau_desc = __get_cpu_var(bau_control).descriptor_base; | |
bdbcdd48 | 326 | bau_desc += UV_ITEMS_PER_DESCRIPTOR * uv_cpu; |
1812924b CW |
327 | |
328 | bau_nodes_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); | |
329 | ||
330 | i = 0; | |
bdbcdd48 | 331 | for_each_cpu(bit, flush_mask) { |
1812924b | 332 | blade = uv_cpu_to_blade_id(bit); |
dc163a41 | 333 | BUG_ON(blade > (UV_DISTRIBUTION_SIZE - 1)); |
b194b120 CW |
334 | if (blade == this_blade) { |
335 | locals++; | |
1812924b | 336 | continue; |
b194b120 | 337 | } |
1812924b | 338 | bau_node_set(blade, &bau_desc->distribution); |
1812924b CW |
339 | i++; |
340 | } | |
b194b120 CW |
341 | if (i == 0) { |
342 | /* | |
343 | * no off_node flushing; return status for local node | |
344 | */ | |
345 | if (locals) | |
bdbcdd48 | 346 | return flush_mask; |
b194b120 | 347 | else |
bdbcdd48 | 348 | return NULL; |
b194b120 | 349 | } |
1812924b CW |
350 | __get_cpu_var(ptcstats).requestor++; |
351 | __get_cpu_var(ptcstats).ntargeted += i; | |
352 | ||
353 | bau_desc->payload.address = va; | |
bdbcdd48 | 354 | bau_desc->payload.sending_cpu = cpu; |
1812924b | 355 | |
bdbcdd48 | 356 | return uv_flush_send_and_wait(uv_cpu, this_blade, bau_desc, flush_mask); |
1812924b CW |
357 | } |
358 | ||
359 | /* | |
360 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
361 | * See entry_64.S | |
362 | * | |
363 | * We received a broadcast assist message. | |
364 | * | |
365 | * Interrupts may have been disabled; this interrupt could represent | |
366 | * the receipt of several messages. | |
367 | * | |
368 | * All cores/threads on this node get this interrupt. | |
369 | * The last one to see it does the s/w ack. | |
370 | * (the resource will not be freed until noninterruptable cpus see this | |
371 | * interrupt; hardware will timeout the s/w ack and reply ERROR) | |
372 | */ | |
b194b120 | 373 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 374 | { |
dc163a41 IM |
375 | struct bau_payload_queue_entry *va_queue_first; |
376 | struct bau_payload_queue_entry *va_queue_last; | |
b4c286e6 | 377 | struct bau_payload_queue_entry *msg; |
1812924b | 378 | struct pt_regs *old_regs = set_irq_regs(regs); |
b4c286e6 IM |
379 | cycles_t time1; |
380 | cycles_t time2; | |
1812924b CW |
381 | int msg_slot; |
382 | int sw_ack_slot; | |
383 | int fw; | |
384 | int count = 0; | |
385 | unsigned long local_pnode; | |
386 | ||
387 | ack_APIC_irq(); | |
388 | exit_idle(); | |
389 | irq_enter(); | |
390 | ||
b194b120 | 391 | time1 = get_cycles(); |
1812924b CW |
392 | |
393 | local_pnode = uv_blade_to_pnode(uv_numa_blade_id()); | |
394 | ||
b4c286e6 | 395 | va_queue_first = __get_cpu_var(bau_control).va_queue_first; |
dc163a41 | 396 | va_queue_last = __get_cpu_var(bau_control).va_queue_last; |
b4c286e6 | 397 | |
1812924b CW |
398 | msg = __get_cpu_var(bau_control).bau_msg_head; |
399 | while (msg->sw_ack_vector) { | |
400 | count++; | |
401 | fw = msg->sw_ack_vector; | |
b4c286e6 | 402 | msg_slot = msg - va_queue_first; |
1812924b CW |
403 | sw_ack_slot = ffs(fw) - 1; |
404 | ||
405 | uv_bau_process_message(msg, msg_slot, sw_ack_slot); | |
406 | ||
407 | msg++; | |
dc163a41 IM |
408 | if (msg > va_queue_last) |
409 | msg = va_queue_first; | |
1812924b CW |
410 | __get_cpu_var(bau_control).bau_msg_head = msg; |
411 | } | |
412 | if (!count) | |
413 | __get_cpu_var(ptcstats).nomsg++; | |
414 | else if (count > 1) | |
415 | __get_cpu_var(ptcstats).multmsg++; | |
416 | ||
b194b120 CW |
417 | time2 = get_cycles(); |
418 | __get_cpu_var(ptcstats).dflush += (time2 - time1); | |
1812924b CW |
419 | |
420 | irq_exit(); | |
421 | set_irq_regs(old_regs); | |
1812924b CW |
422 | } |
423 | ||
b194b120 | 424 | static void uv_enable_timeouts(void) |
1812924b CW |
425 | { |
426 | int i; | |
427 | int blade; | |
428 | int last_blade; | |
429 | int pnode; | |
430 | int cur_cpu = 0; | |
431 | unsigned long apicid; | |
432 | ||
1812924b CW |
433 | last_blade = -1; |
434 | for_each_online_node(i) { | |
435 | blade = uv_node_to_blade_id(i); | |
436 | if (blade == last_blade) | |
437 | continue; | |
438 | last_blade = blade; | |
439 | apicid = per_cpu(x86_cpu_to_apicid, cur_cpu); | |
440 | pnode = uv_blade_to_pnode(blade); | |
441 | cur_cpu += uv_blade_nr_possible_cpus(i); | |
442 | } | |
1812924b CW |
443 | } |
444 | ||
b194b120 | 445 | static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
446 | { |
447 | if (*offset < num_possible_cpus()) | |
448 | return offset; | |
449 | return NULL; | |
450 | } | |
451 | ||
b194b120 | 452 | static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
453 | { |
454 | (*offset)++; | |
455 | if (*offset < num_possible_cpus()) | |
456 | return offset; | |
457 | return NULL; | |
458 | } | |
459 | ||
b194b120 | 460 | static void uv_ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
461 | { |
462 | } | |
463 | ||
464 | /* | |
465 | * Display the statistics thru /proc | |
466 | * data points to the cpu number | |
467 | */ | |
b194b120 | 468 | static int uv_ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
469 | { |
470 | struct ptc_stats *stat; | |
471 | int cpu; | |
472 | ||
473 | cpu = *(loff_t *)data; | |
474 | ||
475 | if (!cpu) { | |
476 | seq_printf(file, | |
477 | "# cpu requestor requestee one all sretry dretry ptc_i "); | |
478 | seq_printf(file, | |
b194b120 | 479 | "sw_ack sflush dflush sok dnomsg dmult starget\n"); |
1812924b CW |
480 | } |
481 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
482 | stat = &per_cpu(ptcstats, cpu); | |
483 | seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld ", | |
484 | cpu, stat->requestor, | |
485 | stat->requestee, stat->onetlb, stat->alltlb, | |
486 | stat->s_retry, stat->d_retry, stat->ptc_i); | |
487 | seq_printf(file, "%lx %ld %ld %ld %ld %ld %ld\n", | |
488 | uv_read_global_mmr64(uv_blade_to_pnode | |
489 | (uv_cpu_to_blade_id(cpu)), | |
490 | UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE), | |
b194b120 | 491 | stat->sflush, stat->dflush, |
1812924b CW |
492 | stat->retriesok, stat->nomsg, |
493 | stat->multmsg, stat->ntargeted); | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | /* | |
500 | * 0: display meaning of the statistics | |
501 | * >0: retry limit | |
502 | */ | |
b194b120 | 503 | static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user, |
b4c286e6 | 504 | size_t count, loff_t *data) |
1812924b CW |
505 | { |
506 | long newmode; | |
507 | char optstr[64]; | |
508 | ||
e7eb8726 | 509 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 510 | return -EINVAL; |
1812924b CW |
511 | if (copy_from_user(optstr, user, count)) |
512 | return -EFAULT; | |
513 | optstr[count - 1] = '\0'; | |
514 | if (strict_strtoul(optstr, 10, &newmode) < 0) { | |
515 | printk(KERN_DEBUG "%s is invalid\n", optstr); | |
516 | return -EINVAL; | |
517 | } | |
518 | ||
519 | if (newmode == 0) { | |
520 | printk(KERN_DEBUG "# cpu: cpu number\n"); | |
521 | printk(KERN_DEBUG | |
522 | "requestor: times this cpu was the flush requestor\n"); | |
523 | printk(KERN_DEBUG | |
524 | "requestee: times this cpu was requested to flush its TLBs\n"); | |
525 | printk(KERN_DEBUG | |
526 | "one: times requested to flush a single address\n"); | |
527 | printk(KERN_DEBUG | |
528 | "all: times requested to flush all TLB's\n"); | |
529 | printk(KERN_DEBUG | |
530 | "sretry: number of retries of source-side timeouts\n"); | |
531 | printk(KERN_DEBUG | |
532 | "dretry: number of retries of destination-side timeouts\n"); | |
533 | printk(KERN_DEBUG | |
534 | "ptc_i: times UV fell through to IPI-style flushes\n"); | |
535 | printk(KERN_DEBUG | |
536 | "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n"); | |
537 | printk(KERN_DEBUG | |
b194b120 | 538 | "sflush_us: cycles spent in uv_flush_tlb_others()\n"); |
1812924b | 539 | printk(KERN_DEBUG |
b194b120 | 540 | "dflush_us: cycles spent in handling flush requests\n"); |
1812924b CW |
541 | printk(KERN_DEBUG "sok: successes on retry\n"); |
542 | printk(KERN_DEBUG "dnomsg: interrupts with no message\n"); | |
543 | printk(KERN_DEBUG | |
544 | "dmult: interrupts with multiple messages\n"); | |
545 | printk(KERN_DEBUG "starget: nodes targeted\n"); | |
546 | } else { | |
547 | uv_bau_retry_limit = newmode; | |
548 | printk(KERN_DEBUG "timeout retry limit:%d\n", | |
549 | uv_bau_retry_limit); | |
550 | } | |
551 | ||
552 | return count; | |
553 | } | |
554 | ||
555 | static const struct seq_operations uv_ptc_seq_ops = { | |
dc163a41 IM |
556 | .start = uv_ptc_seq_start, |
557 | .next = uv_ptc_seq_next, | |
558 | .stop = uv_ptc_seq_stop, | |
559 | .show = uv_ptc_seq_show | |
1812924b CW |
560 | }; |
561 | ||
b194b120 | 562 | static int uv_ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
563 | { |
564 | return seq_open(file, &uv_ptc_seq_ops); | |
565 | } | |
566 | ||
567 | static const struct file_operations proc_uv_ptc_operations = { | |
b194b120 CW |
568 | .open = uv_ptc_proc_open, |
569 | .read = seq_read, | |
570 | .write = uv_ptc_proc_write, | |
571 | .llseek = seq_lseek, | |
572 | .release = seq_release, | |
1812924b CW |
573 | }; |
574 | ||
b194b120 | 575 | static int __init uv_ptc_init(void) |
1812924b | 576 | { |
b194b120 | 577 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
578 | |
579 | if (!is_uv_system()) | |
580 | return 0; | |
581 | ||
1812924b CW |
582 | proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL); |
583 | if (!proc_uv_ptc) { | |
584 | printk(KERN_ERR "unable to create %s proc entry\n", | |
585 | UV_PTC_BASENAME); | |
586 | return -EINVAL; | |
587 | } | |
588 | proc_uv_ptc->proc_fops = &proc_uv_ptc_operations; | |
589 | return 0; | |
590 | } | |
591 | ||
b194b120 CW |
592 | /* |
593 | * begin the initialization of the per-blade control structures | |
594 | */ | |
595 | static struct bau_control * __init uv_table_bases_init(int blade, int node) | |
1812924b | 596 | { |
b194b120 | 597 | int i; |
b194b120 | 598 | struct bau_msg_status *msp; |
dc163a41 | 599 | struct bau_control *bau_tabp; |
b194b120 | 600 | |
dc163a41 | 601 | bau_tabp = |
b194b120 | 602 | kmalloc_node(sizeof(struct bau_control), GFP_KERNEL, node); |
dc163a41 | 603 | BUG_ON(!bau_tabp); |
b4c286e6 | 604 | |
dc163a41 | 605 | bau_tabp->msg_statuses = |
b194b120 | 606 | kmalloc_node(sizeof(struct bau_msg_status) * |
dc163a41 IM |
607 | DEST_Q_SIZE, GFP_KERNEL, node); |
608 | BUG_ON(!bau_tabp->msg_statuses); | |
b4c286e6 | 609 | |
dc163a41 | 610 | for (i = 0, msp = bau_tabp->msg_statuses; i < DEST_Q_SIZE; i++, msp++) |
b194b120 CW |
611 | bau_cpubits_clear(&msp->seen_by, (int) |
612 | uv_blade_nr_possible_cpus(blade)); | |
b4c286e6 | 613 | |
dc163a41 | 614 | uv_bau_table_bases[blade] = bau_tabp; |
b4c286e6 | 615 | |
d400524a | 616 | return bau_tabp; |
1812924b CW |
617 | } |
618 | ||
b194b120 CW |
619 | /* |
620 | * finish the initialization of the per-blade control structures | |
621 | */ | |
b4c286e6 IM |
622 | static void __init |
623 | uv_table_bases_finish(int blade, int node, int cur_cpu, | |
624 | struct bau_control *bau_tablesp, | |
625 | struct bau_desc *adp) | |
b194b120 | 626 | { |
b194b120 | 627 | struct bau_control *bcp; |
b4c286e6 | 628 | int i; |
b194b120 | 629 | |
b4c286e6 | 630 | for (i = cur_cpu; i < cur_cpu + uv_blade_nr_possible_cpus(blade); i++) { |
b194b120 | 631 | bcp = (struct bau_control *)&per_cpu(bau_control, i); |
b4c286e6 IM |
632 | |
633 | bcp->bau_msg_head = bau_tablesp->va_queue_first; | |
634 | bcp->va_queue_first = bau_tablesp->va_queue_first; | |
635 | bcp->va_queue_last = bau_tablesp->va_queue_last; | |
b4c286e6 IM |
636 | bcp->msg_statuses = bau_tablesp->msg_statuses; |
637 | bcp->descriptor_base = adp; | |
b194b120 CW |
638 | } |
639 | } | |
1812924b CW |
640 | |
641 | /* | |
b194b120 | 642 | * initialize the sending side's sending buffers |
1812924b | 643 | */ |
dc163a41 | 644 | static struct bau_desc * __init |
b194b120 | 645 | uv_activation_descriptor_init(int node, int pnode) |
1812924b CW |
646 | { |
647 | int i; | |
1812924b | 648 | unsigned long pa; |
1812924b | 649 | unsigned long m; |
b194b120 | 650 | unsigned long n; |
1812924b | 651 | unsigned long mmr_image; |
dc163a41 IM |
652 | struct bau_desc *adp; |
653 | struct bau_desc *ad2; | |
b194b120 | 654 | |
dc163a41 | 655 | adp = (struct bau_desc *) |
b194b120 | 656 | kmalloc_node(16384, GFP_KERNEL, node); |
dc163a41 | 657 | BUG_ON(!adp); |
b4c286e6 | 658 | |
b194b120 CW |
659 | pa = __pa((unsigned long)adp); |
660 | n = pa >> uv_nshift; | |
661 | m = pa & uv_mmask; | |
b4c286e6 | 662 | |
b194b120 | 663 | mmr_image = uv_read_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE); |
b4c286e6 | 664 | if (mmr_image) { |
b194b120 CW |
665 | uv_write_global_mmr64(pnode, (unsigned long) |
666 | UVH_LB_BAU_SB_DESCRIPTOR_BASE, | |
667 | (n << UV_DESC_BASE_PNODE_SHIFT | m)); | |
b4c286e6 IM |
668 | } |
669 | ||
b194b120 | 670 | for (i = 0, ad2 = adp; i < UV_ACTIVATION_DESCRIPTOR_SIZE; i++, ad2++) { |
dc163a41 | 671 | memset(ad2, 0, sizeof(struct bau_desc)); |
b194b120 CW |
672 | ad2->header.sw_ack_flag = 1; |
673 | ad2->header.base_dest_nodeid = | |
674 | uv_blade_to_pnode(uv_cpu_to_blade_id(0)); | |
675 | ad2->header.command = UV_NET_ENDPOINT_INTD; | |
676 | ad2->header.int_both = 1; | |
677 | /* | |
678 | * all others need to be set to zero: | |
679 | * fairness chaining multilevel count replied_to | |
680 | */ | |
681 | } | |
682 | return adp; | |
683 | } | |
684 | ||
685 | /* | |
686 | * initialize the destination side's receiving buffers | |
687 | */ | |
b4c286e6 IM |
688 | static struct bau_payload_queue_entry * __init |
689 | uv_payload_queue_init(int node, int pnode, struct bau_control *bau_tablesp) | |
b194b120 | 690 | { |
1812924b | 691 | struct bau_payload_queue_entry *pqp; |
b4c286e6 | 692 | char *cp; |
1812924b | 693 | |
dc163a41 IM |
694 | pqp = (struct bau_payload_queue_entry *) kmalloc_node( |
695 | (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry), | |
696 | GFP_KERNEL, node); | |
697 | BUG_ON(!pqp); | |
b4c286e6 | 698 | |
b194b120 CW |
699 | cp = (char *)pqp + 31; |
700 | pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5); | |
701 | bau_tablesp->va_queue_first = pqp; | |
702 | uv_write_global_mmr64(pnode, | |
703 | UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, | |
704 | ((unsigned long)pnode << | |
705 | UV_PAYLOADQ_PNODE_SHIFT) | | |
706 | uv_physnodeaddr(pqp)); | |
707 | uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, | |
708 | uv_physnodeaddr(pqp)); | |
dc163a41 | 709 | bau_tablesp->va_queue_last = pqp + (DEST_Q_SIZE - 1); |
b194b120 CW |
710 | uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, |
711 | (unsigned long) | |
712 | uv_physnodeaddr(bau_tablesp->va_queue_last)); | |
dc163a41 | 713 | memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE); |
b4c286e6 | 714 | |
b194b120 CW |
715 | return pqp; |
716 | } | |
1812924b | 717 | |
b194b120 CW |
718 | /* |
719 | * Initialization of each UV blade's structures | |
720 | */ | |
721 | static int __init uv_init_blade(int blade, int node, int cur_cpu) | |
722 | { | |
723 | int pnode; | |
724 | unsigned long pa; | |
725 | unsigned long apicid; | |
dc163a41 | 726 | struct bau_desc *adp; |
b194b120 CW |
727 | struct bau_payload_queue_entry *pqp; |
728 | struct bau_control *bau_tablesp; | |
1812924b | 729 | |
b194b120 CW |
730 | bau_tablesp = uv_table_bases_init(blade, node); |
731 | pnode = uv_blade_to_pnode(blade); | |
732 | adp = uv_activation_descriptor_init(node, pnode); | |
733 | pqp = uv_payload_queue_init(node, pnode, bau_tablesp); | |
734 | uv_table_bases_finish(blade, node, cur_cpu, bau_tablesp, adp); | |
735 | /* | |
736 | * the below initialization can't be in firmware because the | |
737 | * messaging IRQ will be determined by the OS | |
738 | */ | |
739 | apicid = per_cpu(x86_cpu_to_apicid, cur_cpu); | |
740 | pa = uv_read_global_mmr64(pnode, UVH_BAU_DATA_CONFIG); | |
741 | if ((pa & 0xff) != UV_BAU_MESSAGE) { | |
742 | uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, | |
743 | ((apicid << 32) | UV_BAU_MESSAGE)); | |
1812924b | 744 | } |
b194b120 CW |
745 | return 0; |
746 | } | |
747 | ||
748 | /* | |
749 | * Initialization of BAU-related structures | |
750 | */ | |
751 | static int __init uv_bau_init(void) | |
752 | { | |
753 | int blade; | |
754 | int node; | |
755 | int nblades; | |
756 | int last_blade; | |
757 | int cur_cpu = 0; | |
758 | ||
759 | if (!is_uv_system()) | |
760 | return 0; | |
1812924b | 761 | |
b194b120 | 762 | uv_bau_retry_limit = 1; |
1812924b | 763 | uv_nshift = uv_hub_info->n_val; |
dc163a41 | 764 | uv_mmask = (1UL << uv_hub_info->n_val) - 1; |
1812924b CW |
765 | nblades = 0; |
766 | last_blade = -1; | |
b194b120 CW |
767 | for_each_online_node(node) { |
768 | blade = uv_node_to_blade_id(node); | |
1812924b CW |
769 | if (blade == last_blade) |
770 | continue; | |
771 | last_blade = blade; | |
772 | nblades++; | |
773 | } | |
1812924b CW |
774 | uv_bau_table_bases = (struct bau_control **) |
775 | kmalloc(nblades * sizeof(struct bau_control *), GFP_KERNEL); | |
dc163a41 | 776 | BUG_ON(!uv_bau_table_bases); |
b4c286e6 | 777 | |
1812924b | 778 | last_blade = -1; |
b194b120 CW |
779 | for_each_online_node(node) { |
780 | blade = uv_node_to_blade_id(node); | |
1812924b CW |
781 | if (blade == last_blade) |
782 | continue; | |
783 | last_blade = blade; | |
b194b120 CW |
784 | uv_init_blade(blade, node, cur_cpu); |
785 | cur_cpu += uv_blade_nr_possible_cpus(blade); | |
1812924b | 786 | } |
99dd8713 | 787 | alloc_intr_gate(UV_BAU_MESSAGE, uv_bau_message_intr1); |
1812924b | 788 | uv_enable_timeouts(); |
b4c286e6 | 789 | |
1812924b CW |
790 | return 0; |
791 | } | |
1812924b | 792 | __initcall(uv_bau_init); |
b194b120 | 793 | __initcall(uv_ptc_init); |