]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
b5964405 IM |
15 | #include <linux/interrupt.h> |
16 | #include <linux/kallsyms.h> | |
17 | #include <linux/spinlock.h> | |
b5964405 IM |
18 | #include <linux/kprobes.h> |
19 | #include <linux/uaccess.h> | |
b5964405 | 20 | #include <linux/kdebug.h> |
f503b5ae | 21 | #include <linux/kgdb.h> |
1da177e4 | 22 | #include <linux/kernel.h> |
b5964405 IM |
23 | #include <linux/module.h> |
24 | #include <linux/ptrace.h> | |
1da177e4 | 25 | #include <linux/string.h> |
b5964405 | 26 | #include <linux/delay.h> |
1da177e4 | 27 | #include <linux/errno.h> |
b5964405 IM |
28 | #include <linux/kexec.h> |
29 | #include <linux/sched.h> | |
1da177e4 | 30 | #include <linux/timer.h> |
1da177e4 | 31 | #include <linux/init.h> |
91768d6c | 32 | #include <linux/bug.h> |
b5964405 IM |
33 | #include <linux/nmi.h> |
34 | #include <linux/mm.h> | |
c1d518c8 AH |
35 | #include <linux/smp.h> |
36 | #include <linux/io.h> | |
1da177e4 LT |
37 | |
38 | #ifdef CONFIG_EISA | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/eisa.h> | |
41 | #endif | |
42 | ||
c0d12172 DJ |
43 | #if defined(CONFIG_EDAC) |
44 | #include <linux/edac.h> | |
45 | #endif | |
46 | ||
f8561296 | 47 | #include <asm/kmemcheck.h> |
b5964405 | 48 | #include <asm/stacktrace.h> |
1da177e4 | 49 | #include <asm/processor.h> |
1da177e4 | 50 | #include <asm/debugreg.h> |
60063497 | 51 | #include <linux/atomic.h> |
08d636b6 | 52 | #include <asm/ftrace.h> |
c1d518c8 | 53 | #include <asm/traps.h> |
1da177e4 LT |
54 | #include <asm/desc.h> |
55 | #include <asm/i387.h> | |
1361b83a | 56 | #include <asm/fpu-internal.h> |
9e55e44e | 57 | #include <asm/mce.h> |
c1d518c8 | 58 | |
1164dd00 | 59 | #include <asm/mach_traps.h> |
c1d518c8 | 60 | |
081f75bb | 61 | #ifdef CONFIG_X86_64 |
428cf902 | 62 | #include <asm/x86_init.h> |
081f75bb AH |
63 | #include <asm/pgalloc.h> |
64 | #include <asm/proto.h> | |
081f75bb | 65 | #else |
c1d518c8 | 66 | #include <asm/processor-flags.h> |
8e6dafd6 | 67 | #include <asm/setup.h> |
1da177e4 | 68 | |
1da177e4 LT |
69 | asmlinkage int system_call(void); |
70 | ||
1da177e4 | 71 | /* Do we ignore FPU interrupts ? */ |
b5964405 | 72 | char ignore_fpu_irq; |
1da177e4 LT |
73 | |
74 | /* | |
75 | * The IDT has to be page-aligned to simplify the Pentium | |
07e81d61 | 76 | * F0 0F bug workaround. |
1da177e4 | 77 | */ |
07e81d61 | 78 | gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, }; |
081f75bb | 79 | #endif |
1da177e4 | 80 | |
b77b881f YL |
81 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
82 | EXPORT_SYMBOL_GPL(used_vectors); | |
83 | ||
762db434 AH |
84 | static inline void conditional_sti(struct pt_regs *regs) |
85 | { | |
86 | if (regs->flags & X86_EFLAGS_IF) | |
87 | local_irq_enable(); | |
88 | } | |
89 | ||
3d2a71a5 AH |
90 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
91 | { | |
92 | inc_preempt_count(); | |
93 | if (regs->flags & X86_EFLAGS_IF) | |
94 | local_irq_enable(); | |
95 | } | |
96 | ||
be716615 TG |
97 | static inline void conditional_cli(struct pt_regs *regs) |
98 | { | |
99 | if (regs->flags & X86_EFLAGS_IF) | |
100 | local_irq_disable(); | |
101 | } | |
102 | ||
3d2a71a5 AH |
103 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
104 | { | |
105 | if (regs->flags & X86_EFLAGS_IF) | |
106 | local_irq_disable(); | |
107 | dec_preempt_count(); | |
108 | } | |
109 | ||
b5964405 | 110 | static void __kprobes |
3c1326f8 | 111 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
b5964405 | 112 | long error_code, siginfo_t *info) |
1da177e4 | 113 | { |
4f339ecb | 114 | struct task_struct *tsk = current; |
4f339ecb | 115 | |
081f75bb | 116 | #ifdef CONFIG_X86_32 |
6b6891f9 | 117 | if (regs->flags & X86_VM_MASK) { |
3c1326f8 AH |
118 | /* |
119 | * traps 0, 1, 3, 4, and 5 should be forwarded to vm86. | |
120 | * On nmi (interrupt 2), do_trap should not be called. | |
121 | */ | |
c9408265 | 122 | if (trapnr < X86_TRAP_UD) |
1da177e4 LT |
123 | goto vm86_trap; |
124 | goto trap_signal; | |
125 | } | |
081f75bb | 126 | #endif |
1da177e4 | 127 | |
717b594a | 128 | if (!user_mode(regs)) |
1da177e4 LT |
129 | goto kernel_trap; |
130 | ||
081f75bb | 131 | #ifdef CONFIG_X86_32 |
b5964405 | 132 | trap_signal: |
081f75bb | 133 | #endif |
b5964405 | 134 | /* |
51e7dc70 | 135 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
136 | * kernelspace faults which result in die(), but not |
137 | * kernelspace faults which are fixed up. die() gives the | |
138 | * process no chance to handle the signal and notice the | |
139 | * kernel fault information, so that won't result in polluting | |
140 | * the information about previously queued, but not yet | |
141 | * delivered, faults. See also do_general_protection below. | |
142 | */ | |
143 | tsk->thread.error_code = error_code; | |
51e7dc70 | 144 | tsk->thread.trap_nr = trapnr; |
d1895183 | 145 | |
081f75bb AH |
146 | #ifdef CONFIG_X86_64 |
147 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
148 | printk_ratelimit()) { | |
c767a54b JP |
149 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
150 | tsk->comm, tsk->pid, str, | |
151 | regs->ip, regs->sp, error_code); | |
081f75bb | 152 | print_vma_addr(" in ", regs->ip); |
c767a54b | 153 | pr_cont("\n"); |
081f75bb AH |
154 | } |
155 | #endif | |
156 | ||
b5964405 IM |
157 | if (info) |
158 | force_sig_info(signr, info, tsk); | |
159 | else | |
160 | force_sig(signr, tsk); | |
161 | return; | |
1da177e4 | 162 | |
b5964405 IM |
163 | kernel_trap: |
164 | if (!fixup_exception(regs)) { | |
165 | tsk->thread.error_code = error_code; | |
51e7dc70 | 166 | tsk->thread.trap_nr = trapnr; |
b5964405 | 167 | die(str, regs, error_code); |
1da177e4 | 168 | } |
b5964405 | 169 | return; |
1da177e4 | 170 | |
081f75bb | 171 | #ifdef CONFIG_X86_32 |
b5964405 IM |
172 | vm86_trap: |
173 | if (handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
174 | error_code, trapnr)) | |
175 | goto trap_signal; | |
176 | return; | |
081f75bb | 177 | #endif |
1da177e4 LT |
178 | } |
179 | ||
b5964405 | 180 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 181 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
182 | { \ |
183 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ | |
a8c1be9d | 184 | == NOTIFY_STOP) \ |
b5964405 | 185 | return; \ |
61aef7d2 | 186 | conditional_sti(regs); \ |
3c1326f8 | 187 | do_trap(trapnr, signr, str, regs, error_code, NULL); \ |
1da177e4 LT |
188 | } |
189 | ||
3c1326f8 | 190 | #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \ |
e407d620 | 191 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
192 | { \ |
193 | siginfo_t info; \ | |
194 | info.si_signo = signr; \ | |
195 | info.si_errno = 0; \ | |
196 | info.si_code = sicode; \ | |
197 | info.si_addr = (void __user *)siaddr; \ | |
b5964405 | 198 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ |
a8c1be9d | 199 | == NOTIFY_STOP) \ |
b5964405 | 200 | return; \ |
61aef7d2 | 201 | conditional_sti(regs); \ |
3c1326f8 | 202 | do_trap(trapnr, signr, str, regs, error_code, &info); \ |
1da177e4 LT |
203 | } |
204 | ||
c9408265 KC |
205 | DO_ERROR_INFO(X86_TRAP_DE, SIGFPE, "divide error", divide_error, FPE_INTDIV, |
206 | regs->ip) | |
207 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
208 | DO_ERROR(X86_TRAP_BR, SIGSEGV, "bounds", bounds) | |
209 | DO_ERROR_INFO(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, | |
210 | regs->ip) | |
211 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun", | |
212 | coprocessor_segment_overrun) | |
213 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
214 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
081f75bb | 215 | #ifdef CONFIG_X86_32 |
c9408265 | 216 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
081f75bb | 217 | #endif |
c9408265 KC |
218 | DO_ERROR_INFO(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check, |
219 | BUS_ADRALN, 0) | |
1da177e4 | 220 | |
081f75bb AH |
221 | #ifdef CONFIG_X86_64 |
222 | /* Runs on IST stack */ | |
223 | dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code) | |
224 | { | |
225 | if (notify_die(DIE_TRAP, "stack segment", regs, error_code, | |
c9408265 | 226 | X86_TRAP_SS, SIGBUS) == NOTIFY_STOP) |
081f75bb AH |
227 | return; |
228 | preempt_conditional_sti(regs); | |
c9408265 | 229 | do_trap(X86_TRAP_SS, SIGBUS, "stack segment", regs, error_code, NULL); |
081f75bb AH |
230 | preempt_conditional_cli(regs); |
231 | } | |
232 | ||
233 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) | |
234 | { | |
235 | static const char str[] = "double fault"; | |
236 | struct task_struct *tsk = current; | |
237 | ||
238 | /* Return not checked because double check cannot be ignored */ | |
c9408265 | 239 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
240 | |
241 | tsk->thread.error_code = error_code; | |
51e7dc70 | 242 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 243 | |
bd8b96df IM |
244 | /* |
245 | * This is always a kernel trap and never fixable (and thus must | |
246 | * never return). | |
247 | */ | |
081f75bb AH |
248 | for (;;) |
249 | die(str, regs, error_code); | |
250 | } | |
251 | #endif | |
252 | ||
e407d620 | 253 | dotraplinkage void __kprobes |
13485ab5 | 254 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 255 | { |
13485ab5 | 256 | struct task_struct *tsk; |
b5964405 | 257 | |
c6df0d71 AH |
258 | conditional_sti(regs); |
259 | ||
081f75bb | 260 | #ifdef CONFIG_X86_32 |
6b6891f9 | 261 | if (regs->flags & X86_VM_MASK) |
1da177e4 | 262 | goto gp_in_vm86; |
081f75bb | 263 | #endif |
1da177e4 | 264 | |
13485ab5 | 265 | tsk = current; |
717b594a | 266 | if (!user_mode(regs)) |
1da177e4 LT |
267 | goto gp_in_kernel; |
268 | ||
13485ab5 | 269 | tsk->thread.error_code = error_code; |
51e7dc70 | 270 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 271 | |
13485ab5 AH |
272 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
273 | printk_ratelimit()) { | |
c767a54b | 274 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
275 | tsk->comm, task_pid_nr(tsk), |
276 | regs->ip, regs->sp, error_code); | |
03252919 | 277 | print_vma_addr(" in ", regs->ip); |
c767a54b | 278 | pr_cont("\n"); |
03252919 | 279 | } |
abd4f750 | 280 | |
13485ab5 | 281 | force_sig(SIGSEGV, tsk); |
1da177e4 LT |
282 | return; |
283 | ||
081f75bb | 284 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
285 | gp_in_vm86: |
286 | local_irq_enable(); | |
287 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
288 | return; | |
081f75bb | 289 | #endif |
1da177e4 LT |
290 | |
291 | gp_in_kernel: | |
13485ab5 AH |
292 | if (fixup_exception(regs)) |
293 | return; | |
294 | ||
295 | tsk->thread.error_code = error_code; | |
51e7dc70 | 296 | tsk->thread.trap_nr = X86_TRAP_GP; |
c9408265 KC |
297 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
298 | X86_TRAP_GP, SIGSEGV) == NOTIFY_STOP) | |
13485ab5 AH |
299 | return; |
300 | die("general protection fault", regs, error_code); | |
1da177e4 LT |
301 | } |
302 | ||
c1d518c8 | 303 | /* May run on IST stack. */ |
08d636b6 | 304 | dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 305 | { |
08d636b6 | 306 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
307 | /* |
308 | * ftrace must be first, everything else may cause a recursive crash. | |
309 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
310 | */ | |
311 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
312 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
313 | return; |
314 | #endif | |
f503b5ae | 315 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
316 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
317 | SIGTRAP) == NOTIFY_STOP) | |
f503b5ae JW |
318 | return; |
319 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
cc3a1bf5 | 320 | |
c9408265 KC |
321 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
322 | SIGTRAP) == NOTIFY_STOP) | |
48c88211 | 323 | return; |
b5964405 | 324 | |
42181186 SR |
325 | /* |
326 | * Let others (NMI) know that the debug stack is in use | |
327 | * as we may switch to the interrupt stack. | |
328 | */ | |
329 | debug_stack_usage_inc(); | |
4915a35e | 330 | preempt_conditional_sti(regs); |
c9408265 | 331 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 332 | preempt_conditional_cli(regs); |
42181186 | 333 | debug_stack_usage_dec(); |
1da177e4 | 334 | } |
1da177e4 | 335 | |
081f75bb | 336 | #ifdef CONFIG_X86_64 |
bd8b96df IM |
337 | /* |
338 | * Help handler running on IST stack to switch back to user stack | |
339 | * for scheduling or signal handling. The actual stack switch is done in | |
340 | * entry.S | |
341 | */ | |
081f75bb AH |
342 | asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs) |
343 | { | |
344 | struct pt_regs *regs = eregs; | |
345 | /* Did already sync */ | |
346 | if (eregs == (struct pt_regs *)eregs->sp) | |
347 | ; | |
348 | /* Exception from user space */ | |
349 | else if (user_mode(eregs)) | |
350 | regs = task_pt_regs(current); | |
bd8b96df IM |
351 | /* |
352 | * Exception from kernel and interrupts are enabled. Move to | |
353 | * kernel process stack. | |
354 | */ | |
081f75bb AH |
355 | else if (eregs->flags & X86_EFLAGS_IF) |
356 | regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs)); | |
357 | if (eregs != regs) | |
358 | *regs = *eregs; | |
359 | return regs; | |
360 | } | |
361 | #endif | |
362 | ||
1da177e4 LT |
363 | /* |
364 | * Our handling of the processor debug registers is non-trivial. | |
365 | * We do not clear them on entry and exit from the kernel. Therefore | |
366 | * it is possible to get a watchpoint trap here from inside the kernel. | |
367 | * However, the code in ./ptrace.c has ensured that the user can | |
368 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
369 | * watchpoint trap can only occur in code which is reading/writing | |
370 | * from user space. Such code must not hold kernel locks (since it | |
371 | * can equally take a page fault), therefore it is safe to call | |
372 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 373 | * |
1da177e4 LT |
374 | * Code in ./signal.c ensures that the debug control register |
375 | * is restored before we deliver any signal, and therefore that | |
376 | * user code runs with the correct debug control register even though | |
377 | * we clear it here. | |
378 | * | |
379 | * Being careful here means that we don't have to be as careful in a | |
380 | * lot of more complicated places (task switching can be a bit lazy | |
381 | * about restoring all the debug state, and ptrace doesn't have to | |
382 | * find every occurrence of the TF bit that could be saved away even | |
383 | * by user code) | |
c1d518c8 AH |
384 | * |
385 | * May run on IST stack. | |
1da177e4 | 386 | */ |
e407d620 | 387 | dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 388 | { |
1da177e4 | 389 | struct task_struct *tsk = current; |
a1e80faf | 390 | int user_icebp = 0; |
08d68323 | 391 | unsigned long dr6; |
da654b74 | 392 | int si_code; |
1da177e4 | 393 | |
08d68323 | 394 | get_debugreg(dr6, 6); |
1da177e4 | 395 | |
40f9249a P |
396 | /* Filter out all the reserved bits which are preset to 1 */ |
397 | dr6 &= ~DR6_RESERVED; | |
398 | ||
a1e80faf FW |
399 | /* |
400 | * If dr6 has no reason to give us about the origin of this trap, | |
401 | * then it's very likely the result of an icebp/int01 trap. | |
402 | * User wants a sigtrap for that. | |
403 | */ | |
404 | if (!dr6 && user_mode(regs)) | |
405 | user_icebp = 1; | |
406 | ||
f8561296 | 407 | /* Catch kmemcheck conditions first of all! */ |
eadb8a09 | 408 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
f8561296 VN |
409 | return; |
410 | ||
08d68323 P |
411 | /* DR6 may or may not be cleared by the CPU */ |
412 | set_debugreg(0, 6); | |
10faa81e | 413 | |
ea8e61b7 PZ |
414 | /* |
415 | * The processor cleared BTF, so don't mark that we need it set. | |
416 | */ | |
417 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
418 | ||
08d68323 P |
419 | /* Store the virtualized DR6 value */ |
420 | tsk->thread.debugreg6 = dr6; | |
421 | ||
62edab90 P |
422 | if (notify_die(DIE_DEBUG, "debug", regs, PTR_ERR(&dr6), error_code, |
423 | SIGTRAP) == NOTIFY_STOP) | |
1da177e4 | 424 | return; |
3d2a71a5 | 425 | |
42181186 SR |
426 | /* |
427 | * Let others (NMI) know that the debug stack is in use | |
428 | * as we may switch to the interrupt stack. | |
429 | */ | |
430 | debug_stack_usage_inc(); | |
431 | ||
1da177e4 | 432 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 433 | preempt_conditional_sti(regs); |
1da177e4 | 434 | |
08d68323 | 435 | if (regs->flags & X86_VM_MASK) { |
c9408265 KC |
436 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
437 | X86_TRAP_DB); | |
6554287b | 438 | preempt_conditional_cli(regs); |
42181186 | 439 | debug_stack_usage_dec(); |
08d68323 | 440 | return; |
1da177e4 LT |
441 | } |
442 | ||
1da177e4 | 443 | /* |
08d68323 P |
444 | * Single-stepping through system calls: ignore any exceptions in |
445 | * kernel space, but re-enable TF when returning to user mode. | |
446 | * | |
447 | * We already checked v86 mode above, so we can check for kernel mode | |
448 | * by just checking the CPL of CS. | |
1da177e4 | 449 | */ |
08d68323 P |
450 | if ((dr6 & DR_STEP) && !user_mode(regs)) { |
451 | tsk->thread.debugreg6 &= ~DR_STEP; | |
452 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
453 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 454 | } |
08d68323 | 455 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 456 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 457 | send_sigtrap(tsk, regs, error_code, si_code); |
3d2a71a5 | 458 | preempt_conditional_cli(regs); |
42181186 | 459 | debug_stack_usage_dec(); |
1da177e4 | 460 | |
1da177e4 LT |
461 | return; |
462 | } | |
463 | ||
464 | /* | |
465 | * Note that we play around with the 'TS' bit in an attempt to get | |
466 | * the correct behaviour even in the presence of the asynchronous | |
467 | * IRQ13 behaviour | |
468 | */ | |
9b6dba9e | 469 | void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 470 | { |
e2e75c91 | 471 | struct task_struct *task = current; |
1da177e4 | 472 | siginfo_t info; |
9b6dba9e | 473 | unsigned short err; |
c9408265 KC |
474 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
475 | "simd exception"; | |
e2e75c91 BG |
476 | |
477 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
478 | return; | |
479 | conditional_sti(regs); | |
480 | ||
481 | if (!user_mode_vm(regs)) | |
482 | { | |
483 | if (!fixup_exception(regs)) { | |
484 | task->thread.error_code = error_code; | |
51e7dc70 | 485 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
486 | die(str, regs, error_code); |
487 | } | |
488 | return; | |
489 | } | |
1da177e4 LT |
490 | |
491 | /* | |
492 | * Save the info for the exception handler and clear the error. | |
493 | */ | |
1da177e4 | 494 | save_init_fpu(task); |
51e7dc70 | 495 | task->thread.trap_nr = trapnr; |
9b6dba9e | 496 | task->thread.error_code = error_code; |
1da177e4 LT |
497 | info.si_signo = SIGFPE; |
498 | info.si_errno = 0; | |
9b6dba9e | 499 | info.si_addr = (void __user *)regs->ip; |
c9408265 | 500 | if (trapnr == X86_TRAP_MF) { |
9b6dba9e BG |
501 | unsigned short cwd, swd; |
502 | /* | |
503 | * (~cwd & swd) will mask out exceptions that are not set to unmasked | |
504 | * status. 0x3f is the exception bits in these regs, 0x200 is the | |
505 | * C1 reg you need in case of a stack fault, 0x040 is the stack | |
506 | * fault bit. We should only be taking one exception at a time, | |
507 | * so if this combination doesn't produce any single exception, | |
508 | * then we have a bad program that isn't synchronizing its FPU usage | |
509 | * and it will suffer the consequences since we won't be able to | |
510 | * fully reproduce the context of the exception | |
511 | */ | |
512 | cwd = get_fpu_cwd(task); | |
513 | swd = get_fpu_swd(task); | |
adf77bac | 514 | |
9b6dba9e BG |
515 | err = swd & ~cwd; |
516 | } else { | |
517 | /* | |
518 | * The SIMD FPU exceptions are handled a little differently, as there | |
519 | * is only a single status/control register. Thus, to determine which | |
520 | * unmasked exception was caught we must mask the exception mask bits | |
521 | * at 0x1f80, and then use these to mask the exception bits at 0x3f. | |
522 | */ | |
523 | unsigned short mxcsr = get_fpu_mxcsr(task); | |
524 | err = ~(mxcsr >> 7) & mxcsr; | |
525 | } | |
adf77bac PA |
526 | |
527 | if (err & 0x001) { /* Invalid op */ | |
b5964405 IM |
528 | /* |
529 | * swd & 0x240 == 0x040: Stack Underflow | |
530 | * swd & 0x240 == 0x240: Stack Overflow | |
531 | * User must clear the SF bit (0x40) if set | |
532 | */ | |
533 | info.si_code = FPE_FLTINV; | |
adf77bac | 534 | } else if (err & 0x004) { /* Divide by Zero */ |
b5964405 | 535 | info.si_code = FPE_FLTDIV; |
adf77bac | 536 | } else if (err & 0x008) { /* Overflow */ |
b5964405 | 537 | info.si_code = FPE_FLTOVF; |
adf77bac PA |
538 | } else if (err & 0x012) { /* Denormal, Underflow */ |
539 | info.si_code = FPE_FLTUND; | |
540 | } else if (err & 0x020) { /* Precision */ | |
b5964405 | 541 | info.si_code = FPE_FLTRES; |
adf77bac | 542 | } else { |
bd8b96df | 543 | /* |
c9408265 KC |
544 | * If we're using IRQ 13, or supposedly even some trap |
545 | * X86_TRAP_MF implementations, it's possible | |
546 | * we get a spurious trap, which is not an error. | |
bd8b96df | 547 | */ |
c9408265 | 548 | return; |
1da177e4 LT |
549 | } |
550 | force_sig_info(SIGFPE, &info, task); | |
551 | } | |
552 | ||
e407d620 | 553 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 554 | { |
081f75bb | 555 | #ifdef CONFIG_X86_32 |
1da177e4 | 556 | ignore_fpu_irq = 1; |
081f75bb AH |
557 | #endif |
558 | ||
c9408265 | 559 | math_error(regs, error_code, X86_TRAP_MF); |
1da177e4 LT |
560 | } |
561 | ||
e407d620 AH |
562 | dotraplinkage void |
563 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 564 | { |
c9408265 | 565 | math_error(regs, error_code, X86_TRAP_XF); |
1da177e4 LT |
566 | } |
567 | ||
e407d620 AH |
568 | dotraplinkage void |
569 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 570 | { |
cf81978d | 571 | conditional_sti(regs); |
1da177e4 LT |
572 | #if 0 |
573 | /* No need to warn about this any longer. */ | |
c767a54b | 574 | pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
575 | #endif |
576 | } | |
577 | ||
081f75bb | 578 | asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void) |
1da177e4 | 579 | { |
1da177e4 | 580 | } |
4efc0670 | 581 | |
7856f6cc | 582 | asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void) |
081f75bb AH |
583 | { |
584 | } | |
585 | ||
1da177e4 | 586 | /* |
b5964405 | 587 | * 'math_state_restore()' saves the current math information in the |
1da177e4 LT |
588 | * old math state array, and gets the new ones from the current task |
589 | * | |
590 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
591 | * Don't touch unless you *really* know how it works. | |
592 | * | |
be98c2cd LT |
593 | * Must be called with kernel preemption disabled (eg with local |
594 | * local interrupts as in the case of do_device_not_available). | |
1da177e4 | 595 | */ |
be98c2cd | 596 | void math_state_restore(void) |
1da177e4 | 597 | { |
f94edacf | 598 | struct task_struct *tsk = current; |
1da177e4 | 599 | |
aa283f49 SS |
600 | if (!tsk_used_math(tsk)) { |
601 | local_irq_enable(); | |
602 | /* | |
603 | * does a slab alloc which can sleep | |
604 | */ | |
605 | if (init_fpu(tsk)) { | |
606 | /* | |
607 | * ran out of memory! | |
608 | */ | |
609 | do_group_exit(SIGKILL); | |
610 | return; | |
611 | } | |
612 | local_irq_disable(); | |
613 | } | |
614 | ||
f94edacf | 615 | __thread_fpu_begin(tsk); |
80ab6f1e LT |
616 | /* |
617 | * Paranoid restore. send a SIGSEGV if we fail to restore the state. | |
618 | */ | |
619 | if (unlikely(restore_fpu_checking(tsk))) { | |
620 | __thread_fpu_end(tsk); | |
621 | force_sig(SIGSEGV, tsk); | |
622 | return; | |
623 | } | |
b3b0870e LT |
624 | |
625 | tsk->fpu_counter++; | |
1da177e4 | 626 | } |
5992b6da | 627 | EXPORT_SYMBOL_GPL(math_state_restore); |
1da177e4 | 628 | |
e407d620 | 629 | dotraplinkage void __kprobes |
aa78bcfa | 630 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 631 | { |
a334fe43 | 632 | #ifdef CONFIG_MATH_EMULATION |
7643e9b9 | 633 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
634 | struct math_emu_info info = { }; |
635 | ||
7643e9b9 | 636 | conditional_sti(regs); |
d315760f | 637 | |
aa78bcfa | 638 | info.regs = regs; |
d315760f | 639 | math_emulate(&info); |
a334fe43 | 640 | return; |
7643e9b9 | 641 | } |
a334fe43 BG |
642 | #endif |
643 | math_state_restore(); /* interrupts still off */ | |
644 | #ifdef CONFIG_X86_32 | |
645 | conditional_sti(regs); | |
081f75bb | 646 | #endif |
7643e9b9 AH |
647 | } |
648 | ||
081f75bb | 649 | #ifdef CONFIG_X86_32 |
e407d620 | 650 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
651 | { |
652 | siginfo_t info; | |
653 | local_irq_enable(); | |
654 | ||
655 | info.si_signo = SIGILL; | |
656 | info.si_errno = 0; | |
657 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 658 | info.si_addr = NULL; |
c9408265 KC |
659 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
660 | X86_TRAP_IRET, SIGILL) == NOTIFY_STOP) | |
f8e0870f | 661 | return; |
c9408265 KC |
662 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, |
663 | &info); | |
f8e0870f | 664 | } |
081f75bb | 665 | #endif |
f8e0870f | 666 | |
29c84391 JK |
667 | /* Set of traps needed for early debugging. */ |
668 | void __init early_trap_init(void) | |
669 | { | |
c9408265 | 670 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); |
29c84391 | 671 | /* int3 can be called from all */ |
c9408265 KC |
672 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); |
673 | set_intr_gate(X86_TRAP_PF, &page_fault); | |
29c84391 JK |
674 | load_idt(&idt_descr); |
675 | } | |
676 | ||
1da177e4 LT |
677 | void __init trap_init(void) |
678 | { | |
dbeb2be2 RR |
679 | int i; |
680 | ||
1da177e4 | 681 | #ifdef CONFIG_EISA |
927222b1 | 682 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
683 | |
684 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 685 | EISA_bus = 1; |
927222b1 | 686 | early_iounmap(p, 4); |
1da177e4 LT |
687 | #endif |
688 | ||
c9408265 KC |
689 | set_intr_gate(X86_TRAP_DE, ÷_error); |
690 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); | |
699d2937 | 691 | /* int4 can be called from all */ |
c9408265 KC |
692 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
693 | set_intr_gate(X86_TRAP_BR, &bounds); | |
694 | set_intr_gate(X86_TRAP_UD, &invalid_op); | |
695 | set_intr_gate(X86_TRAP_NM, &device_not_available); | |
081f75bb | 696 | #ifdef CONFIG_X86_32 |
c9408265 | 697 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 698 | #else |
c9408265 | 699 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 700 | #endif |
c9408265 KC |
701 | set_intr_gate(X86_TRAP_OLD_MF, &coprocessor_segment_overrun); |
702 | set_intr_gate(X86_TRAP_TS, &invalid_TSS); | |
703 | set_intr_gate(X86_TRAP_NP, &segment_not_present); | |
704 | set_intr_gate_ist(X86_TRAP_SS, &stack_segment, STACKFAULT_STACK); | |
705 | set_intr_gate(X86_TRAP_GP, &general_protection); | |
706 | set_intr_gate(X86_TRAP_SPURIOUS, &spurious_interrupt_bug); | |
707 | set_intr_gate(X86_TRAP_MF, &coprocessor_error); | |
708 | set_intr_gate(X86_TRAP_AC, &alignment_check); | |
1da177e4 | 709 | #ifdef CONFIG_X86_MCE |
c9408265 | 710 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 711 | #endif |
c9408265 | 712 | set_intr_gate(X86_TRAP_XF, &simd_coprocessor_error); |
1da177e4 | 713 | |
bb3f0b59 YL |
714 | /* Reserve all the builtin and the syscall vector: */ |
715 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
716 | set_bit(i, used_vectors); | |
717 | ||
081f75bb AH |
718 | #ifdef CONFIG_IA32_EMULATION |
719 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
bb3f0b59 | 720 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
721 | #endif |
722 | ||
723 | #ifdef CONFIG_X86_32 | |
699d2937 | 724 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
dbeb2be2 | 725 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 726 | #endif |
bb3f0b59 | 727 | |
1da177e4 | 728 | /* |
b5964405 | 729 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
730 | */ |
731 | cpu_init(); | |
732 | ||
428cf902 | 733 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
734 | |
735 | #ifdef CONFIG_X86_64 | |
736 | memcpy(&nmi_idt_table, &idt_table, IDT_ENTRIES * 16); | |
c9408265 KC |
737 | set_nmi_gate(X86_TRAP_DB, &debug); |
738 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 739 | #endif |
1da177e4 | 740 | } |