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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
b5964405 IM |
24 | #include <linux/module.h> |
25 | #include <linux/ptrace.h> | |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
1da177e4 | 32 | #include <linux/timer.h> |
1da177e4 | 33 | #include <linux/init.h> |
91768d6c | 34 | #include <linux/bug.h> |
b5964405 IM |
35 | #include <linux/nmi.h> |
36 | #include <linux/mm.h> | |
c1d518c8 AH |
37 | #include <linux/smp.h> |
38 | #include <linux/io.h> | |
1da177e4 LT |
39 | |
40 | #ifdef CONFIG_EISA | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/eisa.h> | |
43 | #endif | |
44 | ||
c0d12172 DJ |
45 | #if defined(CONFIG_EDAC) |
46 | #include <linux/edac.h> | |
47 | #endif | |
48 | ||
f8561296 | 49 | #include <asm/kmemcheck.h> |
b5964405 | 50 | #include <asm/stacktrace.h> |
1da177e4 | 51 | #include <asm/processor.h> |
1da177e4 | 52 | #include <asm/debugreg.h> |
60063497 | 53 | #include <linux/atomic.h> |
08d636b6 | 54 | #include <asm/ftrace.h> |
c1d518c8 | 55 | #include <asm/traps.h> |
1da177e4 | 56 | #include <asm/desc.h> |
78f7f1e5 | 57 | #include <asm/fpu/internal.h> |
9e55e44e | 58 | #include <asm/mce.h> |
4eefbe79 | 59 | #include <asm/fixmap.h> |
1164dd00 | 60 | #include <asm/mach_traps.h> |
17f41571 | 61 | #include <asm/alternative.h> |
a84eeaa9 | 62 | #include <asm/fpu/xstate.h> |
e7126cf5 | 63 | #include <asm/trace/mpx.h> |
fe3d197f | 64 | #include <asm/mpx.h> |
c1d518c8 | 65 | |
081f75bb | 66 | #ifdef CONFIG_X86_64 |
428cf902 | 67 | #include <asm/x86_init.h> |
081f75bb AH |
68 | #include <asm/pgalloc.h> |
69 | #include <asm/proto.h> | |
4df05f36 KC |
70 | |
71 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
72 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 73 | #else |
c1d518c8 | 74 | #include <asm/processor-flags.h> |
8e6dafd6 | 75 | #include <asm/setup.h> |
b2502b41 | 76 | #include <asm/proto.h> |
081f75bb | 77 | #endif |
1da177e4 | 78 | |
4df05f36 KC |
79 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
80 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
81 | ||
b77b881f YL |
82 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
83 | EXPORT_SYMBOL_GPL(used_vectors); | |
84 | ||
762db434 AH |
85 | static inline void conditional_sti(struct pt_regs *regs) |
86 | { | |
87 | if (regs->flags & X86_EFLAGS_IF) | |
88 | local_irq_enable(); | |
89 | } | |
90 | ||
3d2a71a5 AH |
91 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
92 | { | |
bdb43806 | 93 | preempt_count_inc(); |
3d2a71a5 AH |
94 | if (regs->flags & X86_EFLAGS_IF) |
95 | local_irq_enable(); | |
96 | } | |
97 | ||
be716615 TG |
98 | static inline void conditional_cli(struct pt_regs *regs) |
99 | { | |
100 | if (regs->flags & X86_EFLAGS_IF) | |
101 | local_irq_disable(); | |
102 | } | |
103 | ||
3d2a71a5 AH |
104 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
105 | { | |
106 | if (regs->flags & X86_EFLAGS_IF) | |
107 | local_irq_disable(); | |
bdb43806 | 108 | preempt_count_dec(); |
3d2a71a5 AH |
109 | } |
110 | ||
8c84014f | 111 | void ist_enter(struct pt_regs *regs) |
95927475 | 112 | { |
f39b6f0e | 113 | if (user_mode(regs)) { |
8c84014f | 114 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
95927475 AL |
115 | } else { |
116 | /* | |
117 | * We might have interrupted pretty much anything. In | |
118 | * fact, if we're a machine check, we can even interrupt | |
119 | * NMI processing. We don't want in_nmi() to return true, | |
120 | * but we need to notify RCU. | |
121 | */ | |
122 | rcu_nmi_enter(); | |
95927475 | 123 | } |
b926e6f6 AL |
124 | |
125 | /* | |
8c84014f AL |
126 | * We are atomic because we're on the IST stack; or we're on |
127 | * x86_32, in which case we still shouldn't schedule; or we're | |
128 | * on x86_64 and entered from user mode, in which case we're | |
129 | * still atomic unless ist_begin_non_atomic is called. | |
b926e6f6 AL |
130 | */ |
131 | preempt_count_add(HARDIRQ_OFFSET); | |
132 | ||
133 | /* This code is a bit fragile. Test it. */ | |
134 | rcu_lockdep_assert(rcu_is_watching(), "ist_enter didn't work"); | |
95927475 AL |
135 | } |
136 | ||
8c84014f | 137 | void ist_exit(struct pt_regs *regs) |
95927475 AL |
138 | { |
139 | preempt_count_sub(HARDIRQ_OFFSET); | |
140 | ||
8c84014f | 141 | if (!user_mode(regs)) |
95927475 AL |
142 | rcu_nmi_exit(); |
143 | } | |
144 | ||
bced35b6 AL |
145 | /** |
146 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
147 | * @regs: regs passed to the IST exception handler | |
148 | * | |
149 | * IST exception handlers normally cannot schedule. As a special | |
150 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 151 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
152 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
153 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
154 | * Callers are responsible for enabling interrupts themselves inside | |
8c84014f | 155 | * the non-atomic section, and callers must call ist_end_non_atomic() |
bced35b6 AL |
156 | * before ist_exit(). |
157 | */ | |
158 | void ist_begin_non_atomic(struct pt_regs *regs) | |
159 | { | |
f39b6f0e | 160 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
161 | |
162 | /* | |
163 | * Sanity check: we need to be on the normal thread stack. This | |
164 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
165 | * from double_fault. | |
166 | */ | |
a7fcf28d AL |
167 | BUG_ON((unsigned long)(current_top_of_stack() - |
168 | current_stack_pointer()) >= THREAD_SIZE); | |
bced35b6 AL |
169 | |
170 | preempt_count_sub(HARDIRQ_OFFSET); | |
171 | } | |
172 | ||
173 | /** | |
174 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
175 | * | |
176 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
177 | */ | |
178 | void ist_end_non_atomic(void) | |
179 | { | |
180 | preempt_count_add(HARDIRQ_OFFSET); | |
181 | } | |
182 | ||
9326638c | 183 | static nokprobe_inline int |
c416ddf5 FW |
184 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
185 | struct pt_regs *regs, long error_code) | |
1da177e4 | 186 | { |
d74ef111 | 187 | if (v8086_mode(regs)) { |
3c1326f8 | 188 | /* |
c416ddf5 | 189 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
190 | * On nmi (interrupt 2), do_trap should not be called. |
191 | */ | |
c416ddf5 FW |
192 | if (trapnr < X86_TRAP_UD) { |
193 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
194 | error_code, trapnr)) | |
195 | return 0; | |
196 | } | |
197 | return -1; | |
1da177e4 | 198 | } |
d74ef111 | 199 | |
55474c48 | 200 | if (!user_mode(regs)) { |
c416ddf5 FW |
201 | if (!fixup_exception(regs)) { |
202 | tsk->thread.error_code = error_code; | |
203 | tsk->thread.trap_nr = trapnr; | |
204 | die(str, regs, error_code); | |
205 | } | |
206 | return 0; | |
207 | } | |
1da177e4 | 208 | |
c416ddf5 FW |
209 | return -1; |
210 | } | |
1da177e4 | 211 | |
1c326c4d ON |
212 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
213 | siginfo_t *info) | |
958d3d72 ON |
214 | { |
215 | unsigned long siaddr; | |
216 | int sicode; | |
217 | ||
218 | switch (trapnr) { | |
1c326c4d ON |
219 | default: |
220 | return SEND_SIG_PRIV; | |
221 | ||
958d3d72 ON |
222 | case X86_TRAP_DE: |
223 | sicode = FPE_INTDIV; | |
b02ef20a | 224 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
225 | break; |
226 | case X86_TRAP_UD: | |
227 | sicode = ILL_ILLOPN; | |
b02ef20a | 228 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
229 | break; |
230 | case X86_TRAP_AC: | |
231 | sicode = BUS_ADRALN; | |
232 | siaddr = 0; | |
233 | break; | |
234 | } | |
235 | ||
236 | info->si_signo = signr; | |
237 | info->si_errno = 0; | |
238 | info->si_code = sicode; | |
239 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 240 | return info; |
958d3d72 ON |
241 | } |
242 | ||
9326638c | 243 | static void |
c416ddf5 FW |
244 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
245 | long error_code, siginfo_t *info) | |
246 | { | |
247 | struct task_struct *tsk = current; | |
248 | ||
249 | ||
250 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
251 | return; | |
b5964405 | 252 | /* |
51e7dc70 | 253 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
254 | * kernelspace faults which result in die(), but not |
255 | * kernelspace faults which are fixed up. die() gives the | |
256 | * process no chance to handle the signal and notice the | |
257 | * kernel fault information, so that won't result in polluting | |
258 | * the information about previously queued, but not yet | |
259 | * delivered, faults. See also do_general_protection below. | |
260 | */ | |
261 | tsk->thread.error_code = error_code; | |
51e7dc70 | 262 | tsk->thread.trap_nr = trapnr; |
d1895183 | 263 | |
081f75bb AH |
264 | #ifdef CONFIG_X86_64 |
265 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
266 | printk_ratelimit()) { | |
c767a54b JP |
267 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
268 | tsk->comm, tsk->pid, str, | |
269 | regs->ip, regs->sp, error_code); | |
081f75bb | 270 | print_vma_addr(" in ", regs->ip); |
c767a54b | 271 | pr_cont("\n"); |
081f75bb AH |
272 | } |
273 | #endif | |
274 | ||
38cad57b | 275 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 276 | } |
9326638c | 277 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 278 | |
dff0796e | 279 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 280 | unsigned long trapnr, int signr) |
dff0796e | 281 | { |
1c326c4d | 282 | siginfo_t info; |
dff0796e | 283 | |
02fdcd5e AL |
284 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
285 | ||
dff0796e ON |
286 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != |
287 | NOTIFY_STOP) { | |
288 | conditional_sti(regs); | |
1c326c4d ON |
289 | do_trap(trapnr, signr, str, regs, error_code, |
290 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e | 291 | } |
dff0796e ON |
292 | } |
293 | ||
b5964405 | 294 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 295 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 296 | { \ |
1c326c4d | 297 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
298 | } |
299 | ||
0eb14833 ON |
300 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
301 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
302 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
303 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
304 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
305 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 306 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 307 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 308 | |
081f75bb AH |
309 | #ifdef CONFIG_X86_64 |
310 | /* Runs on IST stack */ | |
081f75bb AH |
311 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
312 | { | |
313 | static const char str[] = "double fault"; | |
314 | struct task_struct *tsk = current; | |
315 | ||
af726f21 AL |
316 | #ifdef CONFIG_X86_ESPFIX64 |
317 | extern unsigned char native_irq_return_iret[]; | |
318 | ||
319 | /* | |
320 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
321 | * end up promoting it to a doublefault. In that case, modify | |
322 | * the stack to make it look like we just entered the #GP | |
323 | * handler from user space, similar to bad_iret. | |
95927475 AL |
324 | * |
325 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
326 | */ |
327 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
328 | regs->cs == __KERNEL_CS && | |
329 | regs->ip == (unsigned long)native_irq_return_iret) | |
330 | { | |
331 | struct pt_regs *normal_regs = task_pt_regs(current); | |
332 | ||
333 | /* Fake a #GP(0) from userspace. */ | |
334 | memmove(&normal_regs->ip, (void *)regs->sp, 5*8); | |
335 | normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
336 | regs->ip = (unsigned long)general_protection; | |
337 | regs->sp = (unsigned long)&normal_regs->orig_ax; | |
95927475 | 338 | |
af726f21 AL |
339 | return; |
340 | } | |
341 | #endif | |
342 | ||
8c84014f | 343 | ist_enter(regs); |
c9408265 | 344 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
345 | |
346 | tsk->thread.error_code = error_code; | |
51e7dc70 | 347 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 348 | |
4d067d8e BP |
349 | #ifdef CONFIG_DOUBLEFAULT |
350 | df_debug(regs, error_code); | |
351 | #endif | |
bd8b96df IM |
352 | /* |
353 | * This is always a kernel trap and never fixable (and thus must | |
354 | * never return). | |
355 | */ | |
081f75bb AH |
356 | for (;;) |
357 | die(str, regs, error_code); | |
358 | } | |
359 | #endif | |
360 | ||
fe3d197f DH |
361 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
362 | { | |
a84eeaa9 | 363 | const struct bndcsr *bndcsr; |
fe3d197f DH |
364 | siginfo_t *info; |
365 | ||
02fdcd5e | 366 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
fe3d197f DH |
367 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, |
368 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
8c84014f | 369 | return; |
fe3d197f DH |
370 | conditional_sti(regs); |
371 | ||
f39b6f0e | 372 | if (!user_mode(regs)) |
fe3d197f DH |
373 | die("bounds", regs, error_code); |
374 | ||
375 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
376 | /* The exception is not from Intel MPX */ | |
377 | goto exit_trap; | |
378 | } | |
379 | ||
380 | /* | |
381 | * We need to look at BNDSTATUS to resolve this exception. | |
a84eeaa9 DH |
382 | * A NULL here might mean that it is in its 'init state', |
383 | * which is all zeros which indicates MPX was not | |
384 | * responsible for the exception. | |
fe3d197f | 385 | */ |
a84eeaa9 | 386 | bndcsr = get_xsave_field_ptr(XSTATE_BNDCSR); |
fe3d197f DH |
387 | if (!bndcsr) |
388 | goto exit_trap; | |
389 | ||
e7126cf5 | 390 | trace_bounds_exception_mpx(bndcsr); |
fe3d197f DH |
391 | /* |
392 | * The error code field of the BNDSTATUS register communicates status | |
393 | * information of a bound range exception #BR or operation involving | |
394 | * bound directory. | |
395 | */ | |
396 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
397 | case 2: /* Bound directory has invalid entry. */ | |
46a6e0cf | 398 | if (mpx_handle_bd_fault()) |
fe3d197f DH |
399 | goto exit_trap; |
400 | break; /* Success, it was handled */ | |
401 | case 1: /* Bound violation. */ | |
46a6e0cf | 402 | info = mpx_generate_siginfo(regs); |
e10abb2f | 403 | if (IS_ERR(info)) { |
fe3d197f DH |
404 | /* |
405 | * We failed to decode the MPX instruction. Act as if | |
406 | * the exception was not caused by MPX. | |
407 | */ | |
408 | goto exit_trap; | |
409 | } | |
410 | /* | |
411 | * Success, we decoded the instruction and retrieved | |
412 | * an 'info' containing the address being accessed | |
413 | * which caused the exception. This information | |
414 | * allows and application to possibly handle the | |
415 | * #BR exception itself. | |
416 | */ | |
417 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
418 | kfree(info); | |
419 | break; | |
420 | case 0: /* No exception caused by Intel MPX operations. */ | |
421 | goto exit_trap; | |
422 | default: | |
423 | die("bounds", regs, error_code); | |
424 | } | |
425 | ||
fe3d197f | 426 | return; |
8c84014f | 427 | |
fe3d197f DH |
428 | exit_trap: |
429 | /* | |
430 | * This path out is for all the cases where we could not | |
431 | * handle the exception in some way (like allocating a | |
432 | * table or telling userspace about it. We will also end | |
433 | * up here if the kernel has MPX turned off at compile | |
434 | * time.. | |
435 | */ | |
436 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
fe3d197f DH |
437 | } |
438 | ||
9326638c | 439 | dotraplinkage void |
13485ab5 | 440 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 441 | { |
13485ab5 | 442 | struct task_struct *tsk; |
b5964405 | 443 | |
02fdcd5e | 444 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
c6df0d71 AH |
445 | conditional_sti(regs); |
446 | ||
d74ef111 | 447 | if (v8086_mode(regs)) { |
ef3f6288 FW |
448 | local_irq_enable(); |
449 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
8c84014f | 450 | return; |
ef3f6288 | 451 | } |
1da177e4 | 452 | |
13485ab5 | 453 | tsk = current; |
55474c48 | 454 | if (!user_mode(regs)) { |
ef3f6288 | 455 | if (fixup_exception(regs)) |
8c84014f | 456 | return; |
ef3f6288 FW |
457 | |
458 | tsk->thread.error_code = error_code; | |
459 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
460 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
461 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 462 | die("general protection fault", regs, error_code); |
8c84014f | 463 | return; |
ef3f6288 | 464 | } |
1da177e4 | 465 | |
13485ab5 | 466 | tsk->thread.error_code = error_code; |
51e7dc70 | 467 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 468 | |
13485ab5 AH |
469 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
470 | printk_ratelimit()) { | |
c767a54b | 471 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
472 | tsk->comm, task_pid_nr(tsk), |
473 | regs->ip, regs->sp, error_code); | |
03252919 | 474 | print_vma_addr(" in ", regs->ip); |
c767a54b | 475 | pr_cont("\n"); |
03252919 | 476 | } |
abd4f750 | 477 | |
38cad57b | 478 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
1da177e4 | 479 | } |
9326638c | 480 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 481 | |
c1d518c8 | 482 | /* May run on IST stack. */ |
9326638c | 483 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 484 | { |
08d636b6 | 485 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
486 | /* |
487 | * ftrace must be first, everything else may cause a recursive crash. | |
488 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
489 | */ | |
490 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
491 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
492 | return; |
493 | #endif | |
17f41571 JK |
494 | if (poke_int3_handler(regs)) |
495 | return; | |
496 | ||
8c84014f | 497 | ist_enter(regs); |
02fdcd5e | 498 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
f503b5ae | 499 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
500 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
501 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 502 | goto exit; |
f503b5ae | 503 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 504 | |
6f6343f5 MH |
505 | #ifdef CONFIG_KPROBES |
506 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 507 | goto exit; |
6f6343f5 MH |
508 | #endif |
509 | ||
c9408265 KC |
510 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
511 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 512 | goto exit; |
b5964405 | 513 | |
42181186 SR |
514 | /* |
515 | * Let others (NMI) know that the debug stack is in use | |
516 | * as we may switch to the interrupt stack. | |
517 | */ | |
518 | debug_stack_usage_inc(); | |
4915a35e | 519 | preempt_conditional_sti(regs); |
c9408265 | 520 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 521 | preempt_conditional_cli(regs); |
42181186 | 522 | debug_stack_usage_dec(); |
6ba3c97a | 523 | exit: |
8c84014f | 524 | ist_exit(regs); |
1da177e4 | 525 | } |
9326638c | 526 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 527 | |
081f75bb | 528 | #ifdef CONFIG_X86_64 |
bd8b96df | 529 | /* |
48e08d0f AL |
530 | * Help handler running on IST stack to switch off the IST stack if the |
531 | * interrupted code was in user mode. The actual stack switch is done in | |
532 | * entry_64.S | |
bd8b96df | 533 | */ |
7ddc6a21 | 534 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 535 | { |
48e08d0f AL |
536 | struct pt_regs *regs = task_pt_regs(current); |
537 | *regs = *eregs; | |
081f75bb AH |
538 | return regs; |
539 | } | |
9326638c | 540 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
541 | |
542 | struct bad_iret_stack { | |
543 | void *error_entry_ret; | |
544 | struct pt_regs regs; | |
545 | }; | |
546 | ||
7ddc6a21 | 547 | asmlinkage __visible notrace |
b645af2d AL |
548 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
549 | { | |
550 | /* | |
551 | * This is called from entry_64.S early in handling a fault | |
552 | * caused by a bad iret to user mode. To handle the fault | |
553 | * correctly, we want move our stack frame to task_pt_regs | |
554 | * and we want to pretend that the exception came from the | |
555 | * iret target. | |
556 | */ | |
557 | struct bad_iret_stack *new_stack = | |
558 | container_of(task_pt_regs(current), | |
559 | struct bad_iret_stack, regs); | |
560 | ||
561 | /* Copy the IRET target to the new stack. */ | |
562 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
563 | ||
564 | /* Copy the remainder of the stack from the current stack. */ | |
565 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
566 | ||
f39b6f0e | 567 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
568 | return new_stack; |
569 | } | |
7ddc6a21 | 570 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
571 | #endif |
572 | ||
1da177e4 LT |
573 | /* |
574 | * Our handling of the processor debug registers is non-trivial. | |
575 | * We do not clear them on entry and exit from the kernel. Therefore | |
576 | * it is possible to get a watchpoint trap here from inside the kernel. | |
577 | * However, the code in ./ptrace.c has ensured that the user can | |
578 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
579 | * watchpoint trap can only occur in code which is reading/writing | |
580 | * from user space. Such code must not hold kernel locks (since it | |
581 | * can equally take a page fault), therefore it is safe to call | |
582 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 583 | * |
1da177e4 LT |
584 | * Code in ./signal.c ensures that the debug control register |
585 | * is restored before we deliver any signal, and therefore that | |
586 | * user code runs with the correct debug control register even though | |
587 | * we clear it here. | |
588 | * | |
589 | * Being careful here means that we don't have to be as careful in a | |
590 | * lot of more complicated places (task switching can be a bit lazy | |
591 | * about restoring all the debug state, and ptrace doesn't have to | |
592 | * find every occurrence of the TF bit that could be saved away even | |
593 | * by user code) | |
c1d518c8 AH |
594 | * |
595 | * May run on IST stack. | |
1da177e4 | 596 | */ |
9326638c | 597 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 598 | { |
1da177e4 | 599 | struct task_struct *tsk = current; |
a1e80faf | 600 | int user_icebp = 0; |
08d68323 | 601 | unsigned long dr6; |
da654b74 | 602 | int si_code; |
1da177e4 | 603 | |
8c84014f | 604 | ist_enter(regs); |
4cdf77a8 | 605 | |
08d68323 | 606 | get_debugreg(dr6, 6); |
1da177e4 | 607 | |
40f9249a P |
608 | /* Filter out all the reserved bits which are preset to 1 */ |
609 | dr6 &= ~DR6_RESERVED; | |
610 | ||
a1e80faf FW |
611 | /* |
612 | * If dr6 has no reason to give us about the origin of this trap, | |
613 | * then it's very likely the result of an icebp/int01 trap. | |
614 | * User wants a sigtrap for that. | |
615 | */ | |
f39b6f0e | 616 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
617 | user_icebp = 1; |
618 | ||
f8561296 | 619 | /* Catch kmemcheck conditions first of all! */ |
eadb8a09 | 620 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 621 | goto exit; |
f8561296 | 622 | |
08d68323 P |
623 | /* DR6 may or may not be cleared by the CPU */ |
624 | set_debugreg(0, 6); | |
10faa81e | 625 | |
ea8e61b7 PZ |
626 | /* |
627 | * The processor cleared BTF, so don't mark that we need it set. | |
628 | */ | |
629 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
630 | ||
08d68323 P |
631 | /* Store the virtualized DR6 value */ |
632 | tsk->thread.debugreg6 = dr6; | |
633 | ||
6f6343f5 MH |
634 | #ifdef CONFIG_KPROBES |
635 | if (kprobe_debug_handler(regs)) | |
636 | goto exit; | |
637 | #endif | |
638 | ||
5a802e15 | 639 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 640 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 641 | goto exit; |
3d2a71a5 | 642 | |
42181186 SR |
643 | /* |
644 | * Let others (NMI) know that the debug stack is in use | |
645 | * as we may switch to the interrupt stack. | |
646 | */ | |
647 | debug_stack_usage_inc(); | |
648 | ||
1da177e4 | 649 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 650 | preempt_conditional_sti(regs); |
1da177e4 | 651 | |
d74ef111 | 652 | if (v8086_mode(regs)) { |
c9408265 KC |
653 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
654 | X86_TRAP_DB); | |
6554287b | 655 | preempt_conditional_cli(regs); |
42181186 | 656 | debug_stack_usage_dec(); |
6ba3c97a | 657 | goto exit; |
1da177e4 LT |
658 | } |
659 | ||
1da177e4 | 660 | /* |
08d68323 P |
661 | * Single-stepping through system calls: ignore any exceptions in |
662 | * kernel space, but re-enable TF when returning to user mode. | |
663 | * | |
664 | * We already checked v86 mode above, so we can check for kernel mode | |
665 | * by just checking the CPL of CS. | |
1da177e4 | 666 | */ |
55474c48 | 667 | if ((dr6 & DR_STEP) && !user_mode(regs)) { |
08d68323 P |
668 | tsk->thread.debugreg6 &= ~DR_STEP; |
669 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
670 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 671 | } |
08d68323 | 672 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 673 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 674 | send_sigtrap(tsk, regs, error_code, si_code); |
3d2a71a5 | 675 | preempt_conditional_cli(regs); |
42181186 | 676 | debug_stack_usage_dec(); |
1da177e4 | 677 | |
6ba3c97a | 678 | exit: |
8c84014f | 679 | ist_exit(regs); |
1da177e4 | 680 | } |
9326638c | 681 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
682 | |
683 | /* | |
684 | * Note that we play around with the 'TS' bit in an attempt to get | |
685 | * the correct behaviour even in the presence of the asynchronous | |
686 | * IRQ13 behaviour | |
687 | */ | |
5e1b05be | 688 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 689 | { |
e2e75c91 | 690 | struct task_struct *task = current; |
e1cebad4 | 691 | struct fpu *fpu = &task->thread.fpu; |
1da177e4 | 692 | siginfo_t info; |
c9408265 KC |
693 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
694 | "simd exception"; | |
e2e75c91 BG |
695 | |
696 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
697 | return; | |
698 | conditional_sti(regs); | |
699 | ||
e1cebad4 | 700 | if (!user_mode(regs)) { |
e2e75c91 BG |
701 | if (!fixup_exception(regs)) { |
702 | task->thread.error_code = error_code; | |
51e7dc70 | 703 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
704 | die(str, regs, error_code); |
705 | } | |
706 | return; | |
707 | } | |
1da177e4 LT |
708 | |
709 | /* | |
710 | * Save the info for the exception handler and clear the error. | |
711 | */ | |
e1cebad4 IM |
712 | fpu__save(fpu); |
713 | ||
714 | task->thread.trap_nr = trapnr; | |
9b6dba9e | 715 | task->thread.error_code = error_code; |
e1cebad4 IM |
716 | info.si_signo = SIGFPE; |
717 | info.si_errno = 0; | |
718 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); | |
adf77bac | 719 | |
e1cebad4 | 720 | info.si_code = fpu__exception_code(fpu, trapnr); |
adf77bac | 721 | |
e1cebad4 IM |
722 | /* Retry when we get spurious exceptions: */ |
723 | if (!info.si_code) | |
c9408265 | 724 | return; |
e1cebad4 | 725 | |
1da177e4 LT |
726 | force_sig_info(SIGFPE, &info, task); |
727 | } | |
728 | ||
e407d620 | 729 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 730 | { |
02fdcd5e | 731 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
c9408265 | 732 | math_error(regs, error_code, X86_TRAP_MF); |
1da177e4 LT |
733 | } |
734 | ||
e407d620 AH |
735 | dotraplinkage void |
736 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 737 | { |
02fdcd5e | 738 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
c9408265 | 739 | math_error(regs, error_code, X86_TRAP_XF); |
1da177e4 LT |
740 | } |
741 | ||
e407d620 AH |
742 | dotraplinkage void |
743 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 744 | { |
cf81978d | 745 | conditional_sti(regs); |
081f75bb AH |
746 | } |
747 | ||
9326638c | 748 | dotraplinkage void |
aa78bcfa | 749 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 750 | { |
02fdcd5e | 751 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
5d2bd700 | 752 | BUG_ON(use_eager_fpu()); |
304bceda | 753 | |
a334fe43 | 754 | #ifdef CONFIG_MATH_EMULATION |
7643e9b9 | 755 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
756 | struct math_emu_info info = { }; |
757 | ||
7643e9b9 | 758 | conditional_sti(regs); |
d315760f | 759 | |
aa78bcfa | 760 | info.regs = regs; |
d315760f | 761 | math_emulate(&info); |
a334fe43 | 762 | return; |
7643e9b9 | 763 | } |
a334fe43 | 764 | #endif |
e1884d69 | 765 | fpu__restore(¤t->thread.fpu); /* interrupts still off */ |
a334fe43 BG |
766 | #ifdef CONFIG_X86_32 |
767 | conditional_sti(regs); | |
081f75bb | 768 | #endif |
7643e9b9 | 769 | } |
9326638c | 770 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 771 | |
081f75bb | 772 | #ifdef CONFIG_X86_32 |
e407d620 | 773 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
774 | { |
775 | siginfo_t info; | |
6ba3c97a | 776 | |
02fdcd5e | 777 | CT_WARN_ON(ct_state() != CONTEXT_KERNEL); |
f8e0870f AH |
778 | local_irq_enable(); |
779 | ||
780 | info.si_signo = SIGILL; | |
781 | info.si_errno = 0; | |
782 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 783 | info.si_addr = NULL; |
c9408265 | 784 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
785 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
786 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
787 | &info); | |
788 | } | |
f8e0870f | 789 | } |
081f75bb | 790 | #endif |
f8e0870f | 791 | |
29c84391 JK |
792 | /* Set of traps needed for early debugging. */ |
793 | void __init early_trap_init(void) | |
794 | { | |
b4d83270 | 795 | /* |
5eca7453 WN |
796 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
797 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
798 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
799 | * stack. Using the original stack works well enough at this | |
800 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 801 | * trap_init(). |
5eca7453 WN |
802 | * |
803 | * We don't need to set trace_idt_table like set_intr_gate(), | |
804 | * since we don't have trace_debug and it will be reset to | |
805 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 806 | */ |
5eca7453 | 807 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 808 | /* int3 can be called from all */ |
5eca7453 | 809 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 810 | #ifdef CONFIG_X86_32 |
25c74b10 | 811 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 812 | #endif |
29c84391 JK |
813 | load_idt(&idt_descr); |
814 | } | |
815 | ||
8170e6be PA |
816 | void __init early_trap_pf_init(void) |
817 | { | |
818 | #ifdef CONFIG_X86_64 | |
25c74b10 | 819 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
820 | #endif |
821 | } | |
822 | ||
1da177e4 LT |
823 | void __init trap_init(void) |
824 | { | |
dbeb2be2 RR |
825 | int i; |
826 | ||
1da177e4 | 827 | #ifdef CONFIG_EISA |
927222b1 | 828 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
829 | |
830 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 831 | EISA_bus = 1; |
927222b1 | 832 | early_iounmap(p, 4); |
1da177e4 LT |
833 | #endif |
834 | ||
25c74b10 | 835 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 836 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 837 | /* int4 can be called from all */ |
c9408265 | 838 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
839 | set_intr_gate(X86_TRAP_BR, bounds); |
840 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
841 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 842 | #ifdef CONFIG_X86_32 |
c9408265 | 843 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 844 | #else |
c9408265 | 845 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 846 | #endif |
25c74b10 SA |
847 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
848 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
849 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 850 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
851 | set_intr_gate(X86_TRAP_GP, general_protection); |
852 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
853 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
854 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 855 | #ifdef CONFIG_X86_MCE |
c9408265 | 856 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 857 | #endif |
25c74b10 | 858 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 859 | |
bb3f0b59 YL |
860 | /* Reserve all the builtin and the syscall vector: */ |
861 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
862 | set_bit(i, used_vectors); | |
863 | ||
081f75bb | 864 | #ifdef CONFIG_IA32_EMULATION |
2cd23553 | 865 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_compat); |
bb3f0b59 | 866 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
867 | #endif |
868 | ||
869 | #ifdef CONFIG_X86_32 | |
b2502b41 | 870 | set_system_trap_gate(IA32_SYSCALL_VECTOR, entry_INT80_32); |
51bb9284 | 871 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb | 872 | #endif |
bb3f0b59 | 873 | |
4eefbe79 KC |
874 | /* |
875 | * Set the IDT descriptor to a fixed read-only location, so that the | |
876 | * "sidt" instruction will not leak the location of the kernel, and | |
877 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
878 | * It will be reloaded in cpu_init() */ | |
879 | __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO); | |
880 | idt_descr.address = fix_to_virt(FIX_RO_IDT); | |
881 | ||
1da177e4 | 882 | /* |
b5964405 | 883 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
884 | */ |
885 | cpu_init(); | |
886 | ||
b4d83270 WN |
887 | /* |
888 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 889 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
890 | * cpu_init() loads TSS. See comments in early_trap_init(). |
891 | */ | |
892 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
893 | /* int3 can be called from all */ | |
894 | set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK); | |
895 | ||
428cf902 | 896 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
897 | |
898 | #ifdef CONFIG_X86_64 | |
629f4f9d | 899 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 KC |
900 | set_nmi_gate(X86_TRAP_DB, &debug); |
901 | set_nmi_gate(X86_TRAP_BP, &int3); | |
228bdaa9 | 902 | #endif |
1da177e4 | 903 | } |