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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 | 4 | #include <linux/sched.h> |
e6017571 | 5 | #include <linux/sched/clock.h> |
0ef95533 | 6 | #include <linux/init.h> |
186f4360 | 7 | #include <linux/export.h> |
0ef95533 | 8 | #include <linux/timer.h> |
bfc0f594 | 9 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 10 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
11 | #include <linux/delay.h> |
12 | #include <linux/clocksource.h> | |
13 | #include <linux/percpu.h> | |
08604bd9 | 14 | #include <linux/timex.h> |
10b033d4 | 15 | #include <linux/static_key.h> |
bfc0f594 AK |
16 | |
17 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
18 | #include <asm/timer.h> |
19 | #include <asm/vgtod.h> | |
20 | #include <asm/time.h> | |
21 | #include <asm/delay.h> | |
88b094fb | 22 | #include <asm/hypervisor.h> |
08047c4f | 23 | #include <asm/nmi.h> |
2d826404 | 24 | #include <asm/x86_init.h> |
03da3ff1 | 25 | #include <asm/geode.h> |
6731b0d6 | 26 | #include <asm/apic.h> |
655e52d2 | 27 | #include <asm/intel-family.h> |
30c7e5b1 | 28 | #include <asm/i8259.h> |
0ef95533 | 29 | |
f24ade3a | 30 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 31 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
32 | |
33 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
34 | EXPORT_SYMBOL(tsc_khz); |
35 | ||
36 | /* | |
37 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
38 | */ | |
f24ade3a | 39 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
40 | |
41 | /* native_sched_clock() is called before tsc_init(), so | |
42 | we must start with the TSC soft disabled to prevent | |
59e21e3d | 43 | erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */ |
f24ade3a | 44 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 45 | |
3bbfafb7 | 46 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 47 | |
28a00184 | 48 | int tsc_clocksource_reliable; |
57c67da2 | 49 | |
f9677e0f CH |
50 | static u32 art_to_tsc_numerator; |
51 | static u32 art_to_tsc_denominator; | |
52 | static u64 art_to_tsc_offset; | |
53 | struct clocksource *art_related_clocksource; | |
54 | ||
20d1c86a | 55 | struct cyc2ns { |
59eaef78 PZ |
56 | struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ |
57 | seqcount_t seq; /* 32 + 4 = 36 */ | |
20d1c86a | 58 | |
59eaef78 | 59 | }; /* fits one cacheline */ |
20d1c86a | 60 | |
59eaef78 | 61 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); |
20d1c86a | 62 | |
59eaef78 | 63 | void cyc2ns_read_begin(struct cyc2ns_data *data) |
20d1c86a | 64 | { |
59eaef78 | 65 | int seq, idx; |
20d1c86a | 66 | |
59eaef78 | 67 | preempt_disable_notrace(); |
20d1c86a | 68 | |
59eaef78 PZ |
69 | do { |
70 | seq = this_cpu_read(cyc2ns.seq.sequence); | |
71 | idx = seq & 1; | |
20d1c86a | 72 | |
59eaef78 PZ |
73 | data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); |
74 | data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); | |
75 | data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); | |
20d1c86a | 76 | |
59eaef78 | 77 | } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); |
20d1c86a PZ |
78 | } |
79 | ||
59eaef78 | 80 | void cyc2ns_read_end(void) |
20d1c86a | 81 | { |
59eaef78 | 82 | preempt_enable_notrace(); |
20d1c86a PZ |
83 | } |
84 | ||
85 | /* | |
86 | * Accelerators for sched_clock() | |
57c67da2 PZ |
87 | * convert from cycles(64bits) => nanoseconds (64bits) |
88 | * basic equation: | |
89 | * ns = cycles / (freq / ns_per_sec) | |
90 | * ns = cycles * (ns_per_sec / freq) | |
91 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
92 | * ns = cycles * (10^6 / cpu_khz) | |
93 | * | |
94 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
95 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
96 | * ns = cycles * cyc2ns_scale / SC | |
97 | * | |
98 | * And since SC is a constant power of two, we can convert the div | |
b20112ed AH |
99 | * into a shift. The larger SC is, the more accurate the conversion, but |
100 | * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication | |
101 | * (64-bit result) can be used. | |
57c67da2 | 102 | * |
b20112ed | 103 | * We can use khz divisor instead of mhz to keep a better precision. |
57c67da2 PZ |
104 | * (mathieu.desnoyers@polymtl.ca) |
105 | * | |
106 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
107 | */ | |
108 | ||
20d1c86a PZ |
109 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
110 | { | |
5e3c1afd | 111 | data->cyc2ns_mul = 0; |
b20112ed | 112 | data->cyc2ns_shift = 0; |
20d1c86a | 113 | data->cyc2ns_offset = 0; |
20d1c86a PZ |
114 | } |
115 | ||
120fc3fb | 116 | static void __init cyc2ns_init(int cpu) |
20d1c86a PZ |
117 | { |
118 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
119 | ||
120 | cyc2ns_data_init(&c2n->data[0]); | |
121 | cyc2ns_data_init(&c2n->data[1]); | |
122 | ||
59eaef78 | 123 | seqcount_init(&c2n->seq); |
20d1c86a PZ |
124 | } |
125 | ||
57c67da2 PZ |
126 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
127 | { | |
59eaef78 | 128 | struct cyc2ns_data data; |
20d1c86a PZ |
129 | unsigned long long ns; |
130 | ||
59eaef78 | 131 | cyc2ns_read_begin(&data); |
20d1c86a | 132 | |
59eaef78 PZ |
133 | ns = data.cyc2ns_offset; |
134 | ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); | |
20d1c86a | 135 | |
59eaef78 | 136 | cyc2ns_read_end(); |
20d1c86a | 137 | |
57c67da2 PZ |
138 | return ns; |
139 | } | |
140 | ||
5c3c2ea6 | 141 | static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) |
57c67da2 | 142 | { |
615cd033 | 143 | unsigned long long ns_now; |
59eaef78 PZ |
144 | struct cyc2ns_data data; |
145 | struct cyc2ns *c2n; | |
20d1c86a | 146 | unsigned long flags; |
57c67da2 PZ |
147 | |
148 | local_irq_save(flags); | |
149 | sched_clock_idle_sleep_event(); | |
150 | ||
aa297292 | 151 | if (!khz) |
20d1c86a PZ |
152 | goto done; |
153 | ||
57c67da2 PZ |
154 | ns_now = cycles_2_ns(tsc_now); |
155 | ||
20d1c86a PZ |
156 | /* |
157 | * Compute a new multiplier as per the above comment and ensure our | |
158 | * time function is continuous; see the comment near struct | |
159 | * cyc2ns_data. | |
160 | */ | |
59eaef78 | 161 | clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, |
b20112ed AH |
162 | NSEC_PER_MSEC, 0); |
163 | ||
b9511cd7 AH |
164 | /* |
165 | * cyc2ns_shift is exported via arch_perf_update_userpage() where it is | |
166 | * not expected to be greater than 31 due to the original published | |
167 | * conversion algorithm shifting a 32-bit value (now specifies a 64-bit | |
168 | * value) - refer perf_event_mmap_page documentation in perf_event.h. | |
169 | */ | |
59eaef78 PZ |
170 | if (data.cyc2ns_shift == 32) { |
171 | data.cyc2ns_shift = 31; | |
172 | data.cyc2ns_mul >>= 1; | |
b9511cd7 AH |
173 | } |
174 | ||
59eaef78 PZ |
175 | data.cyc2ns_offset = ns_now - |
176 | mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); | |
177 | ||
178 | c2n = per_cpu_ptr(&cyc2ns, cpu); | |
20d1c86a | 179 | |
59eaef78 PZ |
180 | raw_write_seqcount_latch(&c2n->seq); |
181 | c2n->data[0] = data; | |
182 | raw_write_seqcount_latch(&c2n->seq); | |
183 | c2n->data[1] = data; | |
57c67da2 | 184 | |
20d1c86a | 185 | done: |
ac1e843f | 186 | sched_clock_idle_wakeup_event(); |
57c67da2 PZ |
187 | local_irq_restore(flags); |
188 | } | |
615cd033 | 189 | |
0ef95533 AK |
190 | /* |
191 | * Scheduler clock - returns current time in nanosec units. | |
192 | */ | |
193 | u64 native_sched_clock(void) | |
194 | { | |
3bbfafb7 PZ |
195 | if (static_branch_likely(&__use_tsc)) { |
196 | u64 tsc_now = rdtsc(); | |
197 | ||
198 | /* return the value in ns */ | |
199 | return cycles_2_ns(tsc_now); | |
200 | } | |
0ef95533 AK |
201 | |
202 | /* | |
203 | * Fall back to jiffies if there's no TSC available: | |
204 | * ( But note that we still use it if the TSC is marked | |
205 | * unstable. We do this because unlike Time Of Day, | |
206 | * the scheduler clock tolerates small errors and it's | |
207 | * very important for it to be as fast as the platform | |
3ad2f3fb | 208 | * can achieve it. ) |
0ef95533 | 209 | */ |
0ef95533 | 210 | |
3bbfafb7 PZ |
211 | /* No locking but a rare wrong value is not a big deal: */ |
212 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
213 | } |
214 | ||
a94cab23 AK |
215 | /* |
216 | * Generate a sched_clock if you already have a TSC value. | |
217 | */ | |
218 | u64 native_sched_clock_from_tsc(u64 tsc) | |
219 | { | |
220 | return cycles_2_ns(tsc); | |
221 | } | |
222 | ||
0ef95533 AK |
223 | /* We need to define a real function for sched_clock, to override the |
224 | weak default version */ | |
225 | #ifdef CONFIG_PARAVIRT | |
226 | unsigned long long sched_clock(void) | |
227 | { | |
228 | return paravirt_sched_clock(); | |
229 | } | |
f94c8d11 | 230 | |
698eff63 | 231 | bool using_native_sched_clock(void) |
f94c8d11 PZ |
232 | { |
233 | return pv_time_ops.sched_clock == native_sched_clock; | |
234 | } | |
0ef95533 AK |
235 | #else |
236 | unsigned long long | |
237 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
f94c8d11 | 238 | |
698eff63 | 239 | bool using_native_sched_clock(void) { return true; } |
0ef95533 AK |
240 | #endif |
241 | ||
242 | int check_tsc_unstable(void) | |
243 | { | |
244 | return tsc_unstable; | |
245 | } | |
246 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
247 | ||
248 | #ifdef CONFIG_X86_TSC | |
249 | int __init notsc_setup(char *str) | |
250 | { | |
c767a54b | 251 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
252 | tsc_disabled = 1; |
253 | return 1; | |
254 | } | |
255 | #else | |
256 | /* | |
257 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
258 | * in cpu/common.c | |
259 | */ | |
260 | int __init notsc_setup(char *str) | |
261 | { | |
262 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
263 | return 1; | |
264 | } | |
265 | #endif | |
266 | ||
267 | __setup("notsc", notsc_setup); | |
bfc0f594 | 268 | |
e82b8e4e VP |
269 | static int no_sched_irq_time; |
270 | ||
395628ef AK |
271 | static int __init tsc_setup(char *str) |
272 | { | |
273 | if (!strcmp(str, "reliable")) | |
274 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
275 | if (!strncmp(str, "noirqtime", 9)) |
276 | no_sched_irq_time = 1; | |
8309f86c PZ |
277 | if (!strcmp(str, "unstable")) |
278 | mark_tsc_unstable("boot parameter"); | |
395628ef AK |
279 | return 1; |
280 | } | |
281 | ||
282 | __setup("tsc=", tsc_setup); | |
283 | ||
bfc0f594 AK |
284 | #define MAX_RETRIES 5 |
285 | #define SMI_TRESHOLD 50000 | |
286 | ||
287 | /* | |
288 | * Read TSC and the reference counters. Take care of SMI disturbance | |
289 | */ | |
827014be | 290 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
291 | { |
292 | u64 t1, t2; | |
293 | int i; | |
294 | ||
295 | for (i = 0; i < MAX_RETRIES; i++) { | |
296 | t1 = get_cycles(); | |
297 | if (hpet) | |
827014be | 298 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 299 | else |
827014be | 300 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
301 | t2 = get_cycles(); |
302 | if ((t2 - t1) < SMI_TRESHOLD) | |
303 | return t2; | |
304 | } | |
305 | return ULLONG_MAX; | |
306 | } | |
307 | ||
d683ef7a TG |
308 | /* |
309 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 310 | */ |
d683ef7a | 311 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 312 | { |
d683ef7a | 313 | u64 tmp; |
bfc0f594 | 314 | |
d683ef7a TG |
315 | if (hpet2 < hpet1) |
316 | hpet2 += 0x100000000ULL; | |
317 | hpet2 -= hpet1; | |
318 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
319 | do_div(tmp, 1000000); | |
d3878e16 | 320 | deltatsc = div64_u64(deltatsc, tmp); |
d683ef7a TG |
321 | |
322 | return (unsigned long) deltatsc; | |
323 | } | |
324 | ||
325 | /* | |
326 | * Calculate the TSC frequency from PMTimer reference | |
327 | */ | |
328 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
329 | { | |
330 | u64 tmp; | |
bfc0f594 | 331 | |
d683ef7a TG |
332 | if (!pm1 && !pm2) |
333 | return ULONG_MAX; | |
334 | ||
335 | if (pm2 < pm1) | |
336 | pm2 += (u64)ACPI_PM_OVRRUN; | |
337 | pm2 -= pm1; | |
338 | tmp = pm2 * 1000000000LL; | |
339 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
340 | do_div(deltatsc, tmp); | |
341 | ||
342 | return (unsigned long) deltatsc; | |
343 | } | |
344 | ||
a977c400 | 345 | #define CAL_MS 10 |
b7743970 | 346 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
347 | #define CAL_PIT_LOOPS 1000 |
348 | ||
349 | #define CAL2_MS 50 | |
b7743970 | 350 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
351 | #define CAL2_PIT_LOOPS 5000 |
352 | ||
cce3e057 | 353 | |
ec0c15af LT |
354 | /* |
355 | * Try to calibrate the TSC against the Programmable | |
356 | * Interrupt Timer and return the frequency of the TSC | |
357 | * in kHz. | |
358 | * | |
359 | * Return ULONG_MAX on failure to calibrate. | |
360 | */ | |
a977c400 | 361 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
362 | { |
363 | u64 tsc, t1, t2, delta; | |
364 | unsigned long tscmin, tscmax; | |
365 | int pitcnt; | |
366 | ||
30c7e5b1 PZ |
367 | if (!has_legacy_pic()) { |
368 | /* | |
369 | * Relies on tsc_early_delay_calibrate() to have given us semi | |
370 | * usable udelay(), wait for the same 50ms we would have with | |
371 | * the PIT loop below. | |
372 | */ | |
373 | udelay(10 * USEC_PER_MSEC); | |
374 | udelay(10 * USEC_PER_MSEC); | |
375 | udelay(10 * USEC_PER_MSEC); | |
376 | udelay(10 * USEC_PER_MSEC); | |
377 | udelay(10 * USEC_PER_MSEC); | |
378 | return ULONG_MAX; | |
379 | } | |
380 | ||
ec0c15af LT |
381 | /* Set the Gate high, disable speaker */ |
382 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
383 | ||
384 | /* | |
385 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
386 | * count mode), binary count. Set the latch register to 50ms | |
387 | * (LSB then MSB) to begin countdown. | |
388 | */ | |
389 | outb(0xb0, 0x43); | |
a977c400 TG |
390 | outb(latch & 0xff, 0x42); |
391 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
392 | |
393 | tsc = t1 = t2 = get_cycles(); | |
394 | ||
395 | pitcnt = 0; | |
396 | tscmax = 0; | |
397 | tscmin = ULONG_MAX; | |
398 | while ((inb(0x61) & 0x20) == 0) { | |
399 | t2 = get_cycles(); | |
400 | delta = t2 - tsc; | |
401 | tsc = t2; | |
402 | if ((unsigned long) delta < tscmin) | |
403 | tscmin = (unsigned int) delta; | |
404 | if ((unsigned long) delta > tscmax) | |
405 | tscmax = (unsigned int) delta; | |
406 | pitcnt++; | |
407 | } | |
408 | ||
409 | /* | |
410 | * Sanity checks: | |
411 | * | |
a977c400 | 412 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
413 | * times, then we have been hit by a massive SMI |
414 | * | |
415 | * If the maximum is 10 times larger than the minimum, | |
416 | * then we got hit by an SMI as well. | |
417 | */ | |
a977c400 | 418 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
419 | return ULONG_MAX; |
420 | ||
421 | /* Calculate the PIT value */ | |
422 | delta = t2 - t1; | |
a977c400 | 423 | do_div(delta, ms); |
ec0c15af LT |
424 | return delta; |
425 | } | |
426 | ||
6ac40ed0 LT |
427 | /* |
428 | * This reads the current MSB of the PIT counter, and | |
429 | * checks if we are running on sufficiently fast and | |
430 | * non-virtualized hardware. | |
431 | * | |
432 | * Our expectations are: | |
433 | * | |
434 | * - the PIT is running at roughly 1.19MHz | |
435 | * | |
436 | * - each IO is going to take about 1us on real hardware, | |
437 | * but we allow it to be much faster (by a factor of 10) or | |
438 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
439 | * update - anything else implies a unacceptably slow CPU | |
440 | * or PIT for the fast calibration to work. | |
441 | * | |
442 | * - with 256 PIT ticks to read the value, we have 214us to | |
443 | * see the same MSB (and overhead like doing a single TSC | |
444 | * read per MSB value etc). | |
445 | * | |
446 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
447 | * them each to take about a microsecond on real hardware. | |
448 | * So we expect a count value of around 100. But we'll be | |
449 | * generous, and accept anything over 50. | |
450 | * | |
451 | * - if the PIT is stuck, and we see *many* more reads, we | |
452 | * return early (and the next caller of pit_expect_msb() | |
453 | * then consider it a failure when they don't see the | |
454 | * next expected value). | |
455 | * | |
456 | * These expectations mean that we know that we have seen the | |
457 | * transition from one expected value to another with a fairly | |
458 | * high accuracy, and we didn't miss any events. We can thus | |
459 | * use the TSC value at the transitions to calculate a pretty | |
460 | * good value for the TSC frequencty. | |
461 | */ | |
b6e61eef LT |
462 | static inline int pit_verify_msb(unsigned char val) |
463 | { | |
464 | /* Ignore LSB */ | |
465 | inb(0x42); | |
466 | return inb(0x42) == val; | |
467 | } | |
468 | ||
9e8912e0 | 469 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 470 | { |
9e8912e0 | 471 | int count; |
68f30fbe | 472 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 473 | |
6ac40ed0 | 474 | for (count = 0; count < 50000; count++) { |
b6e61eef | 475 | if (!pit_verify_msb(val)) |
6ac40ed0 | 476 | break; |
68f30fbe | 477 | prev_tsc = tsc; |
9e8912e0 | 478 | tsc = get_cycles(); |
6ac40ed0 | 479 | } |
68f30fbe | 480 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
481 | *tscp = tsc; |
482 | ||
483 | /* | |
484 | * We require _some_ success, but the quality control | |
485 | * will be based on the error terms on the TSC values. | |
486 | */ | |
487 | return count > 5; | |
6ac40ed0 LT |
488 | } |
489 | ||
490 | /* | |
9e8912e0 LT |
491 | * How many MSB values do we want to see? We aim for |
492 | * a maximum error rate of 500ppm (in practice the | |
493 | * real error is much smaller), but refuse to spend | |
68f30fbe | 494 | * more than 50ms on it. |
6ac40ed0 | 495 | */ |
68f30fbe | 496 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 497 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 498 | |
6ac40ed0 LT |
499 | static unsigned long quick_pit_calibrate(void) |
500 | { | |
9e8912e0 LT |
501 | int i; |
502 | u64 tsc, delta; | |
503 | unsigned long d1, d2; | |
504 | ||
30c7e5b1 PZ |
505 | if (!has_legacy_pic()) |
506 | return 0; | |
507 | ||
6ac40ed0 | 508 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
509 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
510 | ||
6ac40ed0 LT |
511 | /* |
512 | * Counter 2, mode 0 (one-shot), binary count | |
513 | * | |
514 | * NOTE! Mode 2 decrements by two (and then the | |
515 | * output is flipped each time, giving the same | |
516 | * final output frequency as a decrement-by-one), | |
517 | * so mode 0 is much better when looking at the | |
518 | * individual counts. | |
519 | */ | |
bfc0f594 | 520 | outb(0xb0, 0x43); |
bfc0f594 | 521 | |
6ac40ed0 LT |
522 | /* Start at 0xffff */ |
523 | outb(0xff, 0x42); | |
524 | outb(0xff, 0x42); | |
525 | ||
a6a80e1d LT |
526 | /* |
527 | * The PIT starts counting at the next edge, so we | |
528 | * need to delay for a microsecond. The easiest way | |
529 | * to do that is to just read back the 16-bit counter | |
530 | * once from the PIT. | |
531 | */ | |
b6e61eef | 532 | pit_verify_msb(0); |
a6a80e1d | 533 | |
9e8912e0 LT |
534 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
535 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
536 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
537 | break; | |
538 | ||
5aac644a AH |
539 | delta -= tsc; |
540 | ||
541 | /* | |
542 | * Extrapolate the error and fail fast if the error will | |
543 | * never be below 500 ppm. | |
544 | */ | |
545 | if (i == 1 && | |
546 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
547 | return 0; | |
548 | ||
9e8912e0 LT |
549 | /* |
550 | * Iterate until the error is less than 500 ppm | |
551 | */ | |
b6e61eef LT |
552 | if (d1+d2 >= delta >> 11) |
553 | continue; | |
554 | ||
555 | /* | |
556 | * Check the PIT one more time to verify that | |
557 | * all TSC reads were stable wrt the PIT. | |
558 | * | |
559 | * This also guarantees serialization of the | |
560 | * last cycle read ('d2') in pit_expect_msb. | |
561 | */ | |
562 | if (!pit_verify_msb(0xfe - i)) | |
563 | break; | |
564 | goto success; | |
6ac40ed0 | 565 | } |
6ac40ed0 | 566 | } |
52045217 | 567 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 568 | return 0; |
9e8912e0 LT |
569 | |
570 | success: | |
571 | /* | |
572 | * Ok, if we get here, then we've seen the | |
573 | * MSB of the PIT decrement 'i' times, and the | |
574 | * error has shrunk to less than 500 ppm. | |
575 | * | |
576 | * As a result, we can depend on there not being | |
577 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 578 | * reliable (within the error). |
9e8912e0 LT |
579 | * |
580 | * kHz = ticks / time-in-seconds / 1000; | |
581 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
582 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
583 | */ | |
9e8912e0 LT |
584 | delta *= PIT_TICK_RATE; |
585 | do_div(delta, i*256*1000); | |
c767a54b | 586 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 587 | return delta; |
6ac40ed0 | 588 | } |
ec0c15af | 589 | |
bfc0f594 | 590 | /** |
aa297292 LB |
591 | * native_calibrate_tsc |
592 | * Determine TSC frequency via CPUID, else return 0. | |
bfc0f594 | 593 | */ |
e93ef949 | 594 | unsigned long native_calibrate_tsc(void) |
aa297292 LB |
595 | { |
596 | unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; | |
597 | unsigned int crystal_khz; | |
598 | ||
599 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
600 | return 0; | |
601 | ||
602 | if (boot_cpu_data.cpuid_level < 0x15) | |
603 | return 0; | |
604 | ||
605 | eax_denominator = ebx_numerator = ecx_hz = edx = 0; | |
606 | ||
607 | /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ | |
608 | cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); | |
609 | ||
610 | if (ebx_numerator == 0 || eax_denominator == 0) | |
611 | return 0; | |
612 | ||
613 | crystal_khz = ecx_hz / 1000; | |
614 | ||
615 | if (crystal_khz == 0) { | |
616 | switch (boot_cpu_data.x86_model) { | |
655e52d2 PB |
617 | case INTEL_FAM6_SKYLAKE_MOBILE: |
618 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
6baf3d61 PB |
619 | case INTEL_FAM6_KABYLAKE_MOBILE: |
620 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
ff4c8663 LB |
621 | crystal_khz = 24000; /* 24.0 MHz */ |
622 | break; | |
695085b4 | 623 | case INTEL_FAM6_ATOM_DENVERTON: |
6baf3d61 PB |
624 | crystal_khz = 25000; /* 25.0 MHz */ |
625 | break; | |
655e52d2 | 626 | case INTEL_FAM6_ATOM_GOLDMONT: |
ff4c8663 LB |
627 | crystal_khz = 19200; /* 19.2 MHz */ |
628 | break; | |
aa297292 LB |
629 | } |
630 | } | |
631 | ||
da4ae6c4 LB |
632 | if (crystal_khz == 0) |
633 | return 0; | |
4ca4df0b BG |
634 | /* |
635 | * TSC frequency determined by CPUID is a "hardware reported" | |
636 | * frequency and is the most accurate one so far we have. This | |
637 | * is considered a known frequency. | |
638 | */ | |
639 | setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); | |
640 | ||
4635fdc6 BG |
641 | /* |
642 | * For Atom SoCs TSC is the only reliable clocksource. | |
643 | * Mark TSC reliable so no watchdog on it. | |
644 | */ | |
645 | if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) | |
646 | setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); | |
647 | ||
aa297292 LB |
648 | return crystal_khz * ebx_numerator / eax_denominator; |
649 | } | |
650 | ||
651 | static unsigned long cpu_khz_from_cpuid(void) | |
652 | { | |
653 | unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; | |
654 | ||
655 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
656 | return 0; | |
657 | ||
658 | if (boot_cpu_data.cpuid_level < 0x16) | |
659 | return 0; | |
660 | ||
661 | eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; | |
662 | ||
663 | cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); | |
664 | ||
665 | return eax_base_mhz * 1000; | |
666 | } | |
667 | ||
668 | /** | |
669 | * native_calibrate_cpu - calibrate the cpu on boot | |
670 | */ | |
671 | unsigned long native_calibrate_cpu(void) | |
bfc0f594 | 672 | { |
827014be | 673 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 674 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 675 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 676 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 677 | |
aa297292 LB |
678 | fast_calibrate = cpu_khz_from_cpuid(); |
679 | if (fast_calibrate) | |
680 | return fast_calibrate; | |
681 | ||
02c0cd2d | 682 | fast_calibrate = cpu_khz_from_msr(); |
5f0e0309 | 683 | if (fast_calibrate) |
7da7c156 | 684 | return fast_calibrate; |
7da7c156 | 685 | |
6ac40ed0 LT |
686 | local_irq_save(flags); |
687 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 688 | local_irq_restore(flags); |
6ac40ed0 LT |
689 | if (fast_calibrate) |
690 | return fast_calibrate; | |
bfc0f594 | 691 | |
fbb16e24 TG |
692 | /* |
693 | * Run 5 calibration loops to get the lowest frequency value | |
694 | * (the best estimate). We use two different calibration modes | |
695 | * here: | |
696 | * | |
697 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
698 | * load a timeout of 50ms. We read the time right after we | |
699 | * started the timer and wait until the PIT count down reaches | |
700 | * zero. In each wait loop iteration we read the TSC and check | |
701 | * the delta to the previous read. We keep track of the min | |
702 | * and max values of that delta. The delta is mostly defined | |
703 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 704 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
705 | * maximum time is significantly larger than the minimum time, |
706 | * then we discard the result and have another try. | |
707 | * | |
708 | * 2) Reference counter. If available we use the HPET or the | |
709 | * PMTIMER as a reference to check the sanity of that value. | |
710 | * We use separate TSC readouts and check inside of the | |
711 | * reference read for a SMI/SMM disturbance. We dicard | |
712 | * disturbed values here as well. We do that around the PIT | |
713 | * calibration delay loop as we have to wait for a certain | |
714 | * amount of time anyway. | |
715 | */ | |
a977c400 TG |
716 | |
717 | /* Preset PIT loop values */ | |
718 | latch = CAL_LATCH; | |
719 | ms = CAL_MS; | |
720 | loopmin = CAL_PIT_LOOPS; | |
721 | ||
722 | for (i = 0; i < 3; i++) { | |
ec0c15af | 723 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
724 | |
725 | /* | |
726 | * Read the start value and the reference count of | |
ec0c15af LT |
727 | * hpet/pmtimer when available. Then do the PIT |
728 | * calibration, which will take at least 50ms, and | |
729 | * read the end value. | |
fbb16e24 | 730 | */ |
ec0c15af | 731 | local_irq_save(flags); |
827014be | 732 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 733 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 734 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
735 | local_irq_restore(flags); |
736 | ||
ec0c15af LT |
737 | /* Pick the lowest PIT TSC calibration so far */ |
738 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
739 | |
740 | /* hpet or pmtimer available ? */ | |
62627bec | 741 | if (ref1 == ref2) |
fbb16e24 TG |
742 | continue; |
743 | ||
744 | /* Check, whether the sampling was disturbed by an SMI */ | |
745 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
746 | continue; | |
747 | ||
748 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 749 | if (hpet) |
827014be | 750 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 751 | else |
827014be | 752 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 753 | |
fbb16e24 | 754 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
755 | |
756 | /* Check the reference deviation */ | |
757 | delta = ((u64) tsc_pit_min) * 100; | |
758 | do_div(delta, tsc_ref_min); | |
759 | ||
760 | /* | |
761 | * If both calibration results are inside a 10% window | |
762 | * then we can be sure, that the calibration | |
763 | * succeeded. We break out of the loop right away. We | |
764 | * use the reference value, as it is more precise. | |
765 | */ | |
766 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
767 | pr_info("PIT calibration matches %s. %d loops\n", |
768 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 769 | return tsc_ref_min; |
fbb16e24 TG |
770 | } |
771 | ||
a977c400 TG |
772 | /* |
773 | * Check whether PIT failed more than once. This | |
774 | * happens in virtualized environments. We need to | |
775 | * give the virtual PC a slightly longer timeframe for | |
776 | * the HPET/PMTIMER to make the result precise. | |
777 | */ | |
778 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
779 | latch = CAL2_LATCH; | |
780 | ms = CAL2_MS; | |
781 | loopmin = CAL2_PIT_LOOPS; | |
782 | } | |
fbb16e24 | 783 | } |
bfc0f594 AK |
784 | |
785 | /* | |
fbb16e24 | 786 | * Now check the results. |
bfc0f594 | 787 | */ |
fbb16e24 TG |
788 | if (tsc_pit_min == ULONG_MAX) { |
789 | /* PIT gave no useful value */ | |
c767a54b | 790 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
791 | |
792 | /* We don't have an alternative source, disable TSC */ | |
827014be | 793 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 794 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
795 | return 0; |
796 | } | |
797 | ||
798 | /* The alternative source failed as well, disable TSC */ | |
799 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 800 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
801 | return 0; |
802 | } | |
803 | ||
804 | /* Use the alternative source */ | |
c767a54b JP |
805 | pr_info("using %s reference calibration\n", |
806 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
807 | |
808 | return tsc_ref_min; | |
809 | } | |
bfc0f594 | 810 | |
fbb16e24 | 811 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 812 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 813 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 814 | return tsc_pit_min; |
bfc0f594 AK |
815 | } |
816 | ||
fbb16e24 TG |
817 | /* The alternative source failed, use the PIT calibration value */ |
818 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 819 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 820 | return tsc_pit_min; |
bfc0f594 AK |
821 | } |
822 | ||
fbb16e24 TG |
823 | /* |
824 | * The calibration values differ too much. In doubt, we use | |
825 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 826 | * running at double speed. At least we let the user know: |
fbb16e24 | 827 | */ |
c767a54b JP |
828 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
829 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
830 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 831 | return tsc_pit_min; |
bfc0f594 AK |
832 | } |
833 | ||
af576850 | 834 | void recalibrate_cpu_khz(void) |
bfc0f594 AK |
835 | { |
836 | #ifndef CONFIG_SMP | |
837 | unsigned long cpu_khz_old = cpu_khz; | |
838 | ||
eff4677e | 839 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
af576850 | 840 | return; |
eff4677e | 841 | |
aa297292 | 842 | cpu_khz = x86_platform.calibrate_cpu(); |
eff4677e | 843 | tsc_khz = x86_platform.calibrate_tsc(); |
aa297292 LB |
844 | if (tsc_khz == 0) |
845 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
846 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
847 | cpu_khz = tsc_khz; | |
eff4677e BP |
848 | cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, |
849 | cpu_khz_old, cpu_khz); | |
bfc0f594 AK |
850 | #endif |
851 | } | |
852 | ||
853 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
854 | ||
2dbe06fa | 855 | |
cd7240c0 SS |
856 | static unsigned long long cyc2ns_suspend; |
857 | ||
b74f05d6 | 858 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 859 | { |
35af99e6 | 860 | if (!sched_clock_stable()) |
cd7240c0 SS |
861 | return; |
862 | ||
863 | cyc2ns_suspend = sched_clock(); | |
864 | } | |
865 | ||
866 | /* | |
867 | * Even on processors with invariant TSC, TSC gets reset in some the | |
868 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
869 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
870 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
871 | * that sched_clock() continues from the point where it was left off during | |
872 | * suspend. | |
873 | */ | |
b74f05d6 | 874 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
875 | { |
876 | unsigned long long offset; | |
877 | unsigned long flags; | |
878 | int cpu; | |
879 | ||
35af99e6 | 880 | if (!sched_clock_stable()) |
cd7240c0 SS |
881 | return; |
882 | ||
883 | local_irq_save(flags); | |
884 | ||
20d1c86a | 885 | /* |
6a6256f9 | 886 | * We're coming out of suspend, there's no concurrency yet; don't |
20d1c86a PZ |
887 | * bother being nice about the RCU stuff, just write to both |
888 | * data fields. | |
889 | */ | |
890 | ||
891 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
892 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
893 | ||
cd7240c0 SS |
894 | offset = cyc2ns_suspend - sched_clock(); |
895 | ||
20d1c86a PZ |
896 | for_each_possible_cpu(cpu) { |
897 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
898 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
899 | } | |
cd7240c0 SS |
900 | |
901 | local_irq_restore(flags); | |
902 | } | |
903 | ||
2dbe06fa | 904 | #ifdef CONFIG_CPU_FREQ |
2dbe06fa AK |
905 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency |
906 | * changes. | |
907 | * | |
908 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
909 | * not that important because current Opteron setups do not support | |
910 | * scaling on SMP anyroads. | |
911 | * | |
912 | * Should fix up last_tsc too. Currently gettimeofday in the | |
913 | * first tick after the change will be slightly wrong. | |
914 | */ | |
915 | ||
916 | static unsigned int ref_freq; | |
917 | static unsigned long loops_per_jiffy_ref; | |
918 | static unsigned long tsc_khz_ref; | |
919 | ||
920 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
921 | void *data) | |
922 | { | |
923 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 924 | unsigned long *lpj; |
2dbe06fa | 925 | |
931db6a3 | 926 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 927 | #ifdef CONFIG_SMP |
931db6a3 | 928 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 929 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
930 | #endif |
931 | ||
932 | if (!ref_freq) { | |
933 | ref_freq = freq->old; | |
934 | loops_per_jiffy_ref = *lpj; | |
935 | tsc_khz_ref = tsc_khz; | |
936 | } | |
937 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 938 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 939 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
940 | |
941 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
942 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
943 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 944 | |
5c3c2ea6 | 945 | set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc()); |
3896c329 | 946 | } |
2dbe06fa AK |
947 | |
948 | return 0; | |
949 | } | |
950 | ||
951 | static struct notifier_block time_cpufreq_notifier_block = { | |
952 | .notifier_call = time_cpufreq_notifier | |
953 | }; | |
954 | ||
a841cca7 | 955 | static int __init cpufreq_register_tsc_scaling(void) |
2dbe06fa | 956 | { |
59e21e3d | 957 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
060700b5 LT |
958 | return 0; |
959 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
960 | return 0; | |
2dbe06fa AK |
961 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
962 | CPUFREQ_TRANSITION_NOTIFIER); | |
963 | return 0; | |
964 | } | |
965 | ||
a841cca7 | 966 | core_initcall(cpufreq_register_tsc_scaling); |
2dbe06fa AK |
967 | |
968 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 | 969 | |
f9677e0f CH |
970 | #define ART_CPUID_LEAF (0x15) |
971 | #define ART_MIN_DENOMINATOR (1) | |
972 | ||
973 | ||
974 | /* | |
975 | * If ART is present detect the numerator:denominator to convert to TSC | |
976 | */ | |
120fc3fb | 977 | static void __init detect_art(void) |
f9677e0f CH |
978 | { |
979 | unsigned int unused[2]; | |
980 | ||
981 | if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) | |
982 | return; | |
983 | ||
6c66350d | 984 | /* |
985 | * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, | |
986 | * and the TSC counter resets must not occur asynchronously. | |
987 | */ | |
f9677e0f CH |
988 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || |
989 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || | |
6c66350d | 990 | !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || |
991 | tsc_async_resets) | |
f9677e0f CH |
992 | return; |
993 | ||
7b3d2f6e TG |
994 | cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, |
995 | &art_to_tsc_numerator, unused, unused+1); | |
996 | ||
997 | if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) | |
f9677e0f CH |
998 | return; |
999 | ||
7b3d2f6e TG |
1000 | rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); |
1001 | ||
f9677e0f CH |
1002 | /* Make this sticky over multiple CPU init calls */ |
1003 | setup_force_cpu_cap(X86_FEATURE_ART); | |
1004 | } | |
1005 | ||
1006 | ||
8fbbc4b4 AK |
1007 | /* clocksource code */ |
1008 | ||
6a369583 TG |
1009 | static void tsc_resume(struct clocksource *cs) |
1010 | { | |
1011 | tsc_verify_tsc_adjust(true); | |
1012 | } | |
1013 | ||
8fbbc4b4 | 1014 | /* |
09ec5442 | 1015 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
1016 | * structure to avoid a nasty time-warp. This can be observed in a |
1017 | * very small window right after one CPU updated cycle_last under | |
1018 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
1019 | * is smaller than the cycle_last reference value due to a TSC which | |
1020 | * is slighty behind. This delta is nowhere else observable, but in | |
1021 | * that case it results in a forward time jump in the range of hours | |
1022 | * due to the unsigned delta calculation of the time keeping core | |
1023 | * code, which is necessary to support wrapping clocksources like pm | |
1024 | * timer. | |
09ec5442 TG |
1025 | * |
1026 | * This sanity check is now done in the core timekeeping code. | |
1027 | * checking the result of read_tsc() - cycle_last for being negative. | |
1028 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 1029 | */ |
a5a1d1c2 | 1030 | static u64 read_tsc(struct clocksource *cs) |
8fbbc4b4 | 1031 | { |
a5a1d1c2 | 1032 | return (u64)rdtsc_ordered(); |
1be39679 MS |
1033 | } |
1034 | ||
12907fbb TG |
1035 | static void tsc_cs_mark_unstable(struct clocksource *cs) |
1036 | { | |
1037 | if (tsc_unstable) | |
1038 | return; | |
f94c8d11 | 1039 | |
12907fbb | 1040 | tsc_unstable = 1; |
f94c8d11 PZ |
1041 | if (using_native_sched_clock()) |
1042 | clear_sched_clock_stable(); | |
12907fbb TG |
1043 | disable_sched_clock_irqtime(); |
1044 | pr_info("Marking TSC unstable due to clocksource watchdog\n"); | |
1045 | } | |
1046 | ||
b421b22b PZ |
1047 | static void tsc_cs_tick_stable(struct clocksource *cs) |
1048 | { | |
1049 | if (tsc_unstable) | |
1050 | return; | |
1051 | ||
1052 | if (using_native_sched_clock()) | |
1053 | sched_clock_tick_stable(); | |
1054 | } | |
1055 | ||
09ec5442 TG |
1056 | /* |
1057 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
1058 | */ | |
aa83c457 PZ |
1059 | static struct clocksource clocksource_tsc_early = { |
1060 | .name = "tsc-early", | |
1061 | .rating = 299, | |
1062 | .read = read_tsc, | |
1063 | .mask = CLOCKSOURCE_MASK(64), | |
1064 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | | |
1065 | CLOCK_SOURCE_MUST_VERIFY, | |
1066 | .archdata = { .vclock_mode = VCLOCK_TSC }, | |
1067 | .resume = tsc_resume, | |
1068 | .mark_unstable = tsc_cs_mark_unstable, | |
1069 | .tick_stable = tsc_cs_tick_stable, | |
e3b4f790 | 1070 | .list = LIST_HEAD_INIT(clocksource_tsc_early.list), |
aa83c457 PZ |
1071 | }; |
1072 | ||
1073 | /* | |
1074 | * Must mark VALID_FOR_HRES early such that when we unregister tsc_early | |
1075 | * this one will immediately take over. We will only register if TSC has | |
1076 | * been found good. | |
1077 | */ | |
8fbbc4b4 AK |
1078 | static struct clocksource clocksource_tsc = { |
1079 | .name = "tsc", | |
1080 | .rating = 300, | |
1081 | .read = read_tsc, | |
1082 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 | 1083 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
aa83c457 | 1084 | CLOCK_SOURCE_VALID_FOR_HRES | |
8fbbc4b4 | 1085 | CLOCK_SOURCE_MUST_VERIFY, |
98d0ac38 | 1086 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
6a369583 | 1087 | .resume = tsc_resume, |
12907fbb | 1088 | .mark_unstable = tsc_cs_mark_unstable, |
b421b22b | 1089 | .tick_stable = tsc_cs_tick_stable, |
e3b4f790 | 1090 | .list = LIST_HEAD_INIT(clocksource_tsc.list), |
8fbbc4b4 AK |
1091 | }; |
1092 | ||
1093 | void mark_tsc_unstable(char *reason) | |
1094 | { | |
f94c8d11 PZ |
1095 | if (tsc_unstable) |
1096 | return; | |
1097 | ||
1098 | tsc_unstable = 1; | |
1099 | if (using_native_sched_clock()) | |
35af99e6 | 1100 | clear_sched_clock_stable(); |
f94c8d11 PZ |
1101 | disable_sched_clock_irqtime(); |
1102 | pr_info("Marking TSC unstable due to %s\n", reason); | |
e3b4f790 PZ |
1103 | |
1104 | clocksource_mark_unstable(&clocksource_tsc_early); | |
1105 | clocksource_mark_unstable(&clocksource_tsc); | |
8fbbc4b4 AK |
1106 | } |
1107 | ||
1108 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1109 | ||
395628ef AK |
1110 | static void __init check_system_tsc_reliable(void) |
1111 | { | |
03da3ff1 DW |
1112 | #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) |
1113 | if (is_geode_lx()) { | |
1114 | /* RTSC counts during suspend */ | |
8fbbc4b4 | 1115 | #define RTSC_SUSP 0x100 |
03da3ff1 | 1116 | unsigned long res_low, res_high; |
8fbbc4b4 | 1117 | |
03da3ff1 DW |
1118 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); |
1119 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ | |
1120 | if (res_low & RTSC_SUSP) | |
1121 | tsc_clocksource_reliable = 1; | |
1122 | } | |
8fbbc4b4 | 1123 | #endif |
395628ef AK |
1124 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1125 | tsc_clocksource_reliable = 1; | |
1126 | } | |
8fbbc4b4 AK |
1127 | |
1128 | /* | |
1129 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1130 | * over all CPUs. | |
1131 | */ | |
148f9bb8 | 1132 | int unsynchronized_tsc(void) |
8fbbc4b4 | 1133 | { |
59e21e3d | 1134 | if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) |
8fbbc4b4 AK |
1135 | return 1; |
1136 | ||
3e5095d1 | 1137 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1138 | if (apic_is_clustered_box()) |
1139 | return 1; | |
1140 | #endif | |
1141 | ||
1142 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1143 | return 0; | |
d3b8f889 JS |
1144 | |
1145 | if (tsc_clocksource_reliable) | |
1146 | return 0; | |
8fbbc4b4 AK |
1147 | /* |
1148 | * Intel systems are normally all synchronized. | |
1149 | * Exceptions must mark TSC as unstable: | |
1150 | */ | |
1151 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1152 | /* assume multi socket systems are not synchronized: */ | |
1153 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1154 | return 1; |
8fbbc4b4 AK |
1155 | } |
1156 | ||
d3b8f889 | 1157 | return 0; |
8fbbc4b4 AK |
1158 | } |
1159 | ||
f9677e0f CH |
1160 | /* |
1161 | * Convert ART to TSC given numerator/denominator found in detect_art() | |
1162 | */ | |
a5a1d1c2 | 1163 | struct system_counterval_t convert_art_to_tsc(u64 art) |
f9677e0f CH |
1164 | { |
1165 | u64 tmp, res, rem; | |
1166 | ||
1167 | rem = do_div(art, art_to_tsc_denominator); | |
1168 | ||
1169 | res = art * art_to_tsc_numerator; | |
1170 | tmp = rem * art_to_tsc_numerator; | |
1171 | ||
1172 | do_div(tmp, art_to_tsc_denominator); | |
1173 | res += tmp + art_to_tsc_offset; | |
1174 | ||
1175 | return (struct system_counterval_t) {.cs = art_related_clocksource, | |
1176 | .cycles = res}; | |
1177 | } | |
1178 | EXPORT_SYMBOL(convert_art_to_tsc); | |
08ec0c58 | 1179 | |
fc804f65 RJ |
1180 | /** |
1181 | * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. | |
1182 | * @art_ns: ART (Always Running Timer) in unit of nanoseconds | |
1183 | * | |
1184 | * PTM requires all timestamps to be in units of nanoseconds. When user | |
1185 | * software requests a cross-timestamp, this function converts system timestamp | |
1186 | * to TSC. | |
1187 | * | |
1188 | * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set | |
1189 | * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check | |
1190 | * that this flag is set before conversion to TSC is attempted. | |
1191 | * | |
1192 | * Return: | |
1193 | * struct system_counterval_t - system counter value with the pointer to the | |
1194 | * corresponding clocksource | |
1195 | * @cycles: System counter value | |
1196 | * @cs: Clocksource corresponding to system counter value. Used | |
1197 | * by timekeeping code to verify comparibility of two cycle | |
1198 | * values. | |
1199 | */ | |
1200 | ||
1201 | struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) | |
1202 | { | |
1203 | u64 tmp, res, rem; | |
1204 | ||
1205 | rem = do_div(art_ns, USEC_PER_SEC); | |
1206 | ||
1207 | res = art_ns * tsc_khz; | |
1208 | tmp = rem * tsc_khz; | |
1209 | ||
1210 | do_div(tmp, USEC_PER_SEC); | |
1211 | res += tmp; | |
1212 | ||
1213 | return (struct system_counterval_t) { .cs = art_related_clocksource, | |
1214 | .cycles = res}; | |
1215 | } | |
1216 | EXPORT_SYMBOL(convert_art_ns_to_tsc); | |
1217 | ||
1218 | ||
08ec0c58 JS |
1219 | static void tsc_refine_calibration_work(struct work_struct *work); |
1220 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1221 | /** | |
1222 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1223 | * @work - ignored. | |
1224 | * | |
1225 | * This functions uses delayed work over a period of a | |
1226 | * second to further refine the TSC freq value. Since this is | |
1227 | * timer based, instead of loop based, we don't block the boot | |
1228 | * process while this longer calibration is done. | |
1229 | * | |
0d2eb44f | 1230 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1231 | * or the refined calibration is off by 1% of the fast early |
1232 | * calibration, we throw out the new calibration and use the | |
1233 | * early calibration. | |
1234 | */ | |
1235 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1236 | { | |
1237 | static u64 tsc_start = -1, ref_start; | |
1238 | static int hpet; | |
1239 | u64 tsc_stop, ref_stop, delta; | |
1240 | unsigned long freq; | |
aa7b630e | 1241 | int cpu; |
08ec0c58 JS |
1242 | |
1243 | /* Don't bother refining TSC on unstable systems */ | |
aa83c457 | 1244 | if (tsc_unstable) |
e9088add | 1245 | goto unreg; |
08ec0c58 JS |
1246 | |
1247 | /* | |
1248 | * Since the work is started early in boot, we may be | |
1249 | * delayed the first time we expire. So set the workqueue | |
1250 | * again once we know timers are working. | |
1251 | */ | |
1252 | if (tsc_start == -1) { | |
1253 | /* | |
1254 | * Only set hpet once, to avoid mixing hardware | |
1255 | * if the hpet becomes enabled later. | |
1256 | */ | |
1257 | hpet = is_hpet_enabled(); | |
1258 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1259 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1260 | return; | |
1261 | } | |
1262 | ||
1263 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1264 | ||
1265 | /* hpet or pmtimer available ? */ | |
62627bec | 1266 | if (ref_start == ref_stop) |
08ec0c58 JS |
1267 | goto out; |
1268 | ||
1269 | /* Check, whether the sampling was disturbed by an SMI */ | |
1270 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1271 | goto out; | |
1272 | ||
1273 | delta = tsc_stop - tsc_start; | |
1274 | delta *= 1000000LL; | |
1275 | if (hpet) | |
1276 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1277 | else | |
1278 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1279 | ||
1280 | /* Make sure we're within 1% */ | |
1281 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1282 | goto out; | |
1283 | ||
1284 | tsc_khz = freq; | |
c767a54b JP |
1285 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1286 | (unsigned long)tsc_khz / 1000, | |
1287 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 | 1288 | |
6731b0d6 NS |
1289 | /* Inform the TSC deadline clockevent devices about the recalibration */ |
1290 | lapic_update_tsc_freq(); | |
1291 | ||
aa7b630e PZ |
1292 | /* Update the sched_clock() rate to match the clocksource one */ |
1293 | for_each_possible_cpu(cpu) | |
5c3c2ea6 | 1294 | set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); |
aa7b630e | 1295 | |
08ec0c58 | 1296 | out: |
aa83c457 | 1297 | if (tsc_unstable) |
e9088add | 1298 | goto unreg; |
aa83c457 | 1299 | |
f9677e0f CH |
1300 | if (boot_cpu_has(X86_FEATURE_ART)) |
1301 | art_related_clocksource = &clocksource_tsc; | |
08ec0c58 | 1302 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
e9088add | 1303 | unreg: |
aa83c457 | 1304 | clocksource_unregister(&clocksource_tsc_early); |
08ec0c58 JS |
1305 | } |
1306 | ||
1307 | ||
1308 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1309 | { |
59e21e3d | 1310 | if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
1311 | return 0; |
1312 | ||
e9088add PZ |
1313 | if (tsc_unstable) |
1314 | goto unreg; | |
aa83c457 | 1315 | |
395628ef AK |
1316 | if (tsc_clocksource_reliable) |
1317 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
57779dc2 | 1318 | |
82f9c080 FT |
1319 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1320 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1321 | ||
57779dc2 | 1322 | /* |
47c95a46 BG |
1323 | * When TSC frequency is known (retrieved via MSR or CPUID), we skip |
1324 | * the refined calibration and directly register it as a clocksource. | |
57779dc2 | 1325 | */ |
984feceb | 1326 | if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { |
44fee88c PZ |
1327 | if (boot_cpu_has(X86_FEATURE_ART)) |
1328 | art_related_clocksource = &clocksource_tsc; | |
57779dc2 | 1329 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
e9088add | 1330 | unreg: |
aa83c457 | 1331 | clocksource_unregister(&clocksource_tsc_early); |
57779dc2 AK |
1332 | return 0; |
1333 | } | |
1334 | ||
08ec0c58 JS |
1335 | schedule_delayed_work(&tsc_irqwork, 0); |
1336 | return 0; | |
8fbbc4b4 | 1337 | } |
08ec0c58 JS |
1338 | /* |
1339 | * We use device_initcall here, to ensure we run after the hpet | |
1340 | * is fully initialized, which may occur at fs_initcall time. | |
1341 | */ | |
1342 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 | 1343 | |
eb496063 DL |
1344 | void __init tsc_early_delay_calibrate(void) |
1345 | { | |
1346 | unsigned long lpj; | |
1347 | ||
1348 | if (!boot_cpu_has(X86_FEATURE_TSC)) | |
1349 | return; | |
1350 | ||
1351 | cpu_khz = x86_platform.calibrate_cpu(); | |
1352 | tsc_khz = x86_platform.calibrate_tsc(); | |
1353 | ||
1354 | tsc_khz = tsc_khz ? : cpu_khz; | |
1355 | if (!tsc_khz) | |
1356 | return; | |
1357 | ||
1358 | lpj = tsc_khz * 1000; | |
1359 | do_div(lpj, HZ); | |
1360 | loops_per_jiffy = lpj; | |
1361 | } | |
1362 | ||
8fbbc4b4 AK |
1363 | void __init tsc_init(void) |
1364 | { | |
615cd033 | 1365 | u64 lpj, cyc; |
8fbbc4b4 AK |
1366 | int cpu; |
1367 | ||
59e21e3d | 1368 | if (!boot_cpu_has(X86_FEATURE_TSC)) { |
b47dcbdc | 1369 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 | 1370 | return; |
b47dcbdc | 1371 | } |
8fbbc4b4 | 1372 | |
aa297292 | 1373 | cpu_khz = x86_platform.calibrate_cpu(); |
2d826404 | 1374 | tsc_khz = x86_platform.calibrate_tsc(); |
ff4c8663 LB |
1375 | |
1376 | /* | |
1377 | * Trust non-zero tsc_khz as authorative, | |
1378 | * and use it to sanity check cpu_khz, | |
1379 | * which will be off if system timer is off. | |
1380 | */ | |
aa297292 LB |
1381 | if (tsc_khz == 0) |
1382 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
1383 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
1384 | cpu_khz = tsc_khz; | |
8fbbc4b4 | 1385 | |
e93ef949 | 1386 | if (!tsc_khz) { |
8fbbc4b4 | 1387 | mark_tsc_unstable("could not calculate TSC khz"); |
b47dcbdc | 1388 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 AK |
1389 | return; |
1390 | } | |
1391 | ||
c767a54b JP |
1392 | pr_info("Detected %lu.%03lu MHz processor\n", |
1393 | (unsigned long)cpu_khz / 1000, | |
1394 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 | 1395 | |
4b5b2127 LB |
1396 | if (cpu_khz != tsc_khz) { |
1397 | pr_info("Detected %lu.%03lu MHz TSC", | |
1398 | (unsigned long)tsc_khz / 1000, | |
1399 | (unsigned long)tsc_khz % 1000); | |
1400 | } | |
1401 | ||
f2e04214 TG |
1402 | /* Sanitize TSC ADJUST before cyc2ns gets initialized */ |
1403 | tsc_store_and_check_tsc_adjust(true); | |
1404 | ||
8fbbc4b4 AK |
1405 | /* |
1406 | * Secondary CPUs do not run through tsc_init(), so set up | |
1407 | * all the scale factors for all CPUs, assuming the same | |
1408 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1409 | * up if their speed diverges) | |
1410 | */ | |
615cd033 | 1411 | cyc = rdtsc(); |
20d1c86a PZ |
1412 | for_each_possible_cpu(cpu) { |
1413 | cyc2ns_init(cpu); | |
5c3c2ea6 | 1414 | set_cyc2ns_scale(tsc_khz, cpu, cyc); |
20d1c86a | 1415 | } |
8fbbc4b4 AK |
1416 | |
1417 | if (tsc_disabled > 0) | |
1418 | return; | |
1419 | ||
1420 | /* now allow native_sched_clock() to use rdtsc */ | |
10b033d4 | 1421 | |
8fbbc4b4 | 1422 | tsc_disabled = 0; |
3bbfafb7 | 1423 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1424 | |
e82b8e4e VP |
1425 | if (!no_sched_irq_time) |
1426 | enable_sched_clock_irqtime(); | |
1427 | ||
70de9a97 AK |
1428 | lpj = ((u64)tsc_khz * 1000); |
1429 | do_div(lpj, HZ); | |
1430 | lpj_fine = lpj; | |
1431 | ||
8fbbc4b4 | 1432 | use_tsc_delay(); |
8fbbc4b4 | 1433 | |
a1272dd5 ZD |
1434 | check_system_tsc_reliable(); |
1435 | ||
aa83c457 | 1436 | if (unsynchronized_tsc()) { |
8fbbc4b4 | 1437 | mark_tsc_unstable("TSCs unsynchronized"); |
aa83c457 PZ |
1438 | return; |
1439 | } | |
8fbbc4b4 | 1440 | |
aa83c457 | 1441 | clocksource_register_khz(&clocksource_tsc_early, tsc_khz); |
f9677e0f | 1442 | detect_art(); |
8fbbc4b4 AK |
1443 | } |
1444 | ||
b565201c JS |
1445 | #ifdef CONFIG_SMP |
1446 | /* | |
1447 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1448 | * we can skip clock calibration if another cpu in the same socket has already | |
1449 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1450 | * cpus in the socket - this should be a safe assumption. | |
1451 | */ | |
148f9bb8 | 1452 | unsigned long calibrate_delay_is_known(void) |
b565201c | 1453 | { |
c25323c0 | 1454 | int sibling, cpu = smp_processor_id(); |
76ce7cfe PT |
1455 | int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC); |
1456 | const struct cpumask *mask = topology_core_cpumask(cpu); | |
b565201c | 1457 | |
76ce7cfe | 1458 | if (tsc_disabled || !constant_tsc || !mask) |
f508a5ba TG |
1459 | return 0; |
1460 | ||
1461 | sibling = cpumask_any_but(mask, cpu); | |
c25323c0 TG |
1462 | if (sibling < nr_cpu_ids) |
1463 | return cpu_data(sibling).loops_per_jiffy; | |
b565201c JS |
1464 | return 0; |
1465 | } | |
1466 | #endif |