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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 AK |
4 | #include <linux/sched.h> |
5 | #include <linux/init.h> | |
6 | #include <linux/module.h> | |
7 | #include <linux/timer.h> | |
bfc0f594 | 8 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 9 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
10 | #include <linux/delay.h> |
11 | #include <linux/clocksource.h> | |
12 | #include <linux/percpu.h> | |
08604bd9 | 13 | #include <linux/timex.h> |
10b033d4 | 14 | #include <linux/static_key.h> |
bfc0f594 AK |
15 | |
16 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
17 | #include <asm/timer.h> |
18 | #include <asm/vgtod.h> | |
19 | #include <asm/time.h> | |
20 | #include <asm/delay.h> | |
88b094fb | 21 | #include <asm/hypervisor.h> |
08047c4f | 22 | #include <asm/nmi.h> |
2d826404 | 23 | #include <asm/x86_init.h> |
03da3ff1 | 24 | #include <asm/geode.h> |
0ef95533 | 25 | |
f24ade3a | 26 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 27 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
28 | |
29 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
30 | EXPORT_SYMBOL(tsc_khz); |
31 | ||
32 | /* | |
33 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
34 | */ | |
f24ade3a | 35 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
36 | |
37 | /* native_sched_clock() is called before tsc_init(), so | |
38 | we must start with the TSC soft disabled to prevent | |
39 | erroneous rdtsc usage on !cpu_has_tsc processors */ | |
f24ade3a | 40 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 41 | |
3bbfafb7 | 42 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 43 | |
28a00184 | 44 | int tsc_clocksource_reliable; |
57c67da2 | 45 | |
20d1c86a PZ |
46 | /* |
47 | * Use a ring-buffer like data structure, where a writer advances the head by | |
48 | * writing a new data entry and a reader advances the tail when it observes a | |
49 | * new entry. | |
50 | * | |
51 | * Writers are made to wait on readers until there's space to write a new | |
52 | * entry. | |
53 | * | |
54 | * This means that we can always use an {offset, mul} pair to compute a ns | |
55 | * value that is 'roughly' in the right direction, even if we're writing a new | |
56 | * {offset, mul} pair during the clock read. | |
57 | * | |
58 | * The down-side is that we can no longer guarantee strict monotonicity anymore | |
59 | * (assuming the TSC was that to begin with), because while we compute the | |
60 | * intersection point of the two clock slopes and make sure the time is | |
61 | * continuous at the point of switching; we can no longer guarantee a reader is | |
62 | * strictly before or after the switch point. | |
63 | * | |
64 | * It does mean a reader no longer needs to disable IRQs in order to avoid | |
65 | * CPU-Freq updates messing with his times, and similarly an NMI reader will | |
66 | * no longer run the risk of hitting half-written state. | |
67 | */ | |
68 | ||
69 | struct cyc2ns { | |
70 | struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */ | |
71 | struct cyc2ns_data *head; /* 48 + 8 = 56 */ | |
72 | struct cyc2ns_data *tail; /* 56 + 8 = 64 */ | |
73 | }; /* exactly fits one cacheline */ | |
74 | ||
75 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); | |
76 | ||
77 | struct cyc2ns_data *cyc2ns_read_begin(void) | |
78 | { | |
79 | struct cyc2ns_data *head; | |
80 | ||
81 | preempt_disable(); | |
82 | ||
83 | head = this_cpu_read(cyc2ns.head); | |
84 | /* | |
85 | * Ensure we observe the entry when we observe the pointer to it. | |
86 | * matches the wmb from cyc2ns_write_end(). | |
87 | */ | |
88 | smp_read_barrier_depends(); | |
89 | head->__count++; | |
90 | barrier(); | |
91 | ||
92 | return head; | |
93 | } | |
94 | ||
95 | void cyc2ns_read_end(struct cyc2ns_data *head) | |
96 | { | |
97 | barrier(); | |
98 | /* | |
99 | * If we're the outer most nested read; update the tail pointer | |
100 | * when we're done. This notifies possible pending writers | |
101 | * that we've observed the head pointer and that the other | |
102 | * entry is now free. | |
103 | */ | |
104 | if (!--head->__count) { | |
105 | /* | |
106 | * x86-TSO does not reorder writes with older reads; | |
107 | * therefore once this write becomes visible to another | |
108 | * cpu, we must be finished reading the cyc2ns_data. | |
109 | * | |
110 | * matches with cyc2ns_write_begin(). | |
111 | */ | |
112 | this_cpu_write(cyc2ns.tail, head); | |
113 | } | |
114 | preempt_enable(); | |
115 | } | |
116 | ||
117 | /* | |
118 | * Begin writing a new @data entry for @cpu. | |
119 | * | |
120 | * Assumes some sort of write side lock; currently 'provided' by the assumption | |
121 | * that cpufreq will call its notifiers sequentially. | |
122 | */ | |
123 | static struct cyc2ns_data *cyc2ns_write_begin(int cpu) | |
124 | { | |
125 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
126 | struct cyc2ns_data *data = c2n->data; | |
127 | ||
128 | if (data == c2n->head) | |
129 | data++; | |
130 | ||
131 | /* XXX send an IPI to @cpu in order to guarantee a read? */ | |
132 | ||
133 | /* | |
134 | * When we observe the tail write from cyc2ns_read_end(), | |
135 | * the cpu must be done with that entry and its safe | |
136 | * to start writing to it. | |
137 | */ | |
138 | while (c2n->tail == data) | |
139 | cpu_relax(); | |
140 | ||
141 | return data; | |
142 | } | |
143 | ||
144 | static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data) | |
145 | { | |
146 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
147 | ||
148 | /* | |
149 | * Ensure the @data writes are visible before we publish the | |
150 | * entry. Matches the data-depencency in cyc2ns_read_begin(). | |
151 | */ | |
152 | smp_wmb(); | |
153 | ||
154 | ACCESS_ONCE(c2n->head) = data; | |
155 | } | |
156 | ||
157 | /* | |
158 | * Accelerators for sched_clock() | |
57c67da2 PZ |
159 | * convert from cycles(64bits) => nanoseconds (64bits) |
160 | * basic equation: | |
161 | * ns = cycles / (freq / ns_per_sec) | |
162 | * ns = cycles * (ns_per_sec / freq) | |
163 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
164 | * ns = cycles * (10^6 / cpu_khz) | |
165 | * | |
166 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
167 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
168 | * ns = cycles * cyc2ns_scale / SC | |
169 | * | |
170 | * And since SC is a constant power of two, we can convert the div | |
b20112ed AH |
171 | * into a shift. The larger SC is, the more accurate the conversion, but |
172 | * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication | |
173 | * (64-bit result) can be used. | |
57c67da2 | 174 | * |
b20112ed | 175 | * We can use khz divisor instead of mhz to keep a better precision. |
57c67da2 PZ |
176 | * (mathieu.desnoyers@polymtl.ca) |
177 | * | |
178 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
179 | */ | |
180 | ||
20d1c86a PZ |
181 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
182 | { | |
5e3c1afd | 183 | data->cyc2ns_mul = 0; |
b20112ed | 184 | data->cyc2ns_shift = 0; |
20d1c86a PZ |
185 | data->cyc2ns_offset = 0; |
186 | data->__count = 0; | |
187 | } | |
188 | ||
189 | static void cyc2ns_init(int cpu) | |
190 | { | |
191 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
192 | ||
193 | cyc2ns_data_init(&c2n->data[0]); | |
194 | cyc2ns_data_init(&c2n->data[1]); | |
195 | ||
196 | c2n->head = c2n->data; | |
197 | c2n->tail = c2n->data; | |
198 | } | |
199 | ||
57c67da2 PZ |
200 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
201 | { | |
20d1c86a PZ |
202 | struct cyc2ns_data *data, *tail; |
203 | unsigned long long ns; | |
204 | ||
205 | /* | |
206 | * See cyc2ns_read_*() for details; replicated in order to avoid | |
207 | * an extra few instructions that came with the abstraction. | |
208 | * Notable, it allows us to only do the __count and tail update | |
209 | * dance when its actually needed. | |
210 | */ | |
211 | ||
569d6557 | 212 | preempt_disable_notrace(); |
20d1c86a PZ |
213 | data = this_cpu_read(cyc2ns.head); |
214 | tail = this_cpu_read(cyc2ns.tail); | |
215 | ||
216 | if (likely(data == tail)) { | |
217 | ns = data->cyc2ns_offset; | |
b20112ed | 218 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
219 | } else { |
220 | data->__count++; | |
221 | ||
222 | barrier(); | |
223 | ||
224 | ns = data->cyc2ns_offset; | |
b20112ed | 225 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
226 | |
227 | barrier(); | |
228 | ||
229 | if (!--data->__count) | |
230 | this_cpu_write(cyc2ns.tail, data); | |
231 | } | |
569d6557 | 232 | preempt_enable_notrace(); |
20d1c86a | 233 | |
57c67da2 PZ |
234 | return ns; |
235 | } | |
236 | ||
237 | static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) | |
238 | { | |
20d1c86a PZ |
239 | unsigned long long tsc_now, ns_now; |
240 | struct cyc2ns_data *data; | |
241 | unsigned long flags; | |
57c67da2 PZ |
242 | |
243 | local_irq_save(flags); | |
244 | sched_clock_idle_sleep_event(); | |
245 | ||
20d1c86a PZ |
246 | if (!cpu_khz) |
247 | goto done; | |
248 | ||
249 | data = cyc2ns_write_begin(cpu); | |
57c67da2 | 250 | |
4ea1636b | 251 | tsc_now = rdtsc(); |
57c67da2 PZ |
252 | ns_now = cycles_2_ns(tsc_now); |
253 | ||
20d1c86a PZ |
254 | /* |
255 | * Compute a new multiplier as per the above comment and ensure our | |
256 | * time function is continuous; see the comment near struct | |
257 | * cyc2ns_data. | |
258 | */ | |
b20112ed AH |
259 | clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz, |
260 | NSEC_PER_MSEC, 0); | |
261 | ||
b9511cd7 AH |
262 | /* |
263 | * cyc2ns_shift is exported via arch_perf_update_userpage() where it is | |
264 | * not expected to be greater than 31 due to the original published | |
265 | * conversion algorithm shifting a 32-bit value (now specifies a 64-bit | |
266 | * value) - refer perf_event_mmap_page documentation in perf_event.h. | |
267 | */ | |
268 | if (data->cyc2ns_shift == 32) { | |
269 | data->cyc2ns_shift = 31; | |
270 | data->cyc2ns_mul >>= 1; | |
271 | } | |
272 | ||
20d1c86a | 273 | data->cyc2ns_offset = ns_now - |
b20112ed | 274 | mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
275 | |
276 | cyc2ns_write_end(cpu, data); | |
57c67da2 | 277 | |
20d1c86a | 278 | done: |
57c67da2 PZ |
279 | sched_clock_idle_wakeup_event(0); |
280 | local_irq_restore(flags); | |
281 | } | |
0ef95533 AK |
282 | /* |
283 | * Scheduler clock - returns current time in nanosec units. | |
284 | */ | |
285 | u64 native_sched_clock(void) | |
286 | { | |
3bbfafb7 PZ |
287 | if (static_branch_likely(&__use_tsc)) { |
288 | u64 tsc_now = rdtsc(); | |
289 | ||
290 | /* return the value in ns */ | |
291 | return cycles_2_ns(tsc_now); | |
292 | } | |
0ef95533 AK |
293 | |
294 | /* | |
295 | * Fall back to jiffies if there's no TSC available: | |
296 | * ( But note that we still use it if the TSC is marked | |
297 | * unstable. We do this because unlike Time Of Day, | |
298 | * the scheduler clock tolerates small errors and it's | |
299 | * very important for it to be as fast as the platform | |
3ad2f3fb | 300 | * can achieve it. ) |
0ef95533 | 301 | */ |
0ef95533 | 302 | |
3bbfafb7 PZ |
303 | /* No locking but a rare wrong value is not a big deal: */ |
304 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
305 | } |
306 | ||
a94cab23 AK |
307 | /* |
308 | * Generate a sched_clock if you already have a TSC value. | |
309 | */ | |
310 | u64 native_sched_clock_from_tsc(u64 tsc) | |
311 | { | |
312 | return cycles_2_ns(tsc); | |
313 | } | |
314 | ||
0ef95533 AK |
315 | /* We need to define a real function for sched_clock, to override the |
316 | weak default version */ | |
317 | #ifdef CONFIG_PARAVIRT | |
318 | unsigned long long sched_clock(void) | |
319 | { | |
320 | return paravirt_sched_clock(); | |
321 | } | |
322 | #else | |
323 | unsigned long long | |
324 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
325 | #endif | |
326 | ||
327 | int check_tsc_unstable(void) | |
328 | { | |
329 | return tsc_unstable; | |
330 | } | |
331 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
332 | ||
c73deb6a AH |
333 | int check_tsc_disabled(void) |
334 | { | |
335 | return tsc_disabled; | |
336 | } | |
337 | EXPORT_SYMBOL_GPL(check_tsc_disabled); | |
338 | ||
0ef95533 AK |
339 | #ifdef CONFIG_X86_TSC |
340 | int __init notsc_setup(char *str) | |
341 | { | |
c767a54b | 342 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
343 | tsc_disabled = 1; |
344 | return 1; | |
345 | } | |
346 | #else | |
347 | /* | |
348 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
349 | * in cpu/common.c | |
350 | */ | |
351 | int __init notsc_setup(char *str) | |
352 | { | |
353 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
354 | return 1; | |
355 | } | |
356 | #endif | |
357 | ||
358 | __setup("notsc", notsc_setup); | |
bfc0f594 | 359 | |
e82b8e4e VP |
360 | static int no_sched_irq_time; |
361 | ||
395628ef AK |
362 | static int __init tsc_setup(char *str) |
363 | { | |
364 | if (!strcmp(str, "reliable")) | |
365 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
366 | if (!strncmp(str, "noirqtime", 9)) |
367 | no_sched_irq_time = 1; | |
395628ef AK |
368 | return 1; |
369 | } | |
370 | ||
371 | __setup("tsc=", tsc_setup); | |
372 | ||
bfc0f594 AK |
373 | #define MAX_RETRIES 5 |
374 | #define SMI_TRESHOLD 50000 | |
375 | ||
376 | /* | |
377 | * Read TSC and the reference counters. Take care of SMI disturbance | |
378 | */ | |
827014be | 379 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
380 | { |
381 | u64 t1, t2; | |
382 | int i; | |
383 | ||
384 | for (i = 0; i < MAX_RETRIES; i++) { | |
385 | t1 = get_cycles(); | |
386 | if (hpet) | |
827014be | 387 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 388 | else |
827014be | 389 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
390 | t2 = get_cycles(); |
391 | if ((t2 - t1) < SMI_TRESHOLD) | |
392 | return t2; | |
393 | } | |
394 | return ULLONG_MAX; | |
395 | } | |
396 | ||
d683ef7a TG |
397 | /* |
398 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 399 | */ |
d683ef7a | 400 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 401 | { |
d683ef7a | 402 | u64 tmp; |
bfc0f594 | 403 | |
d683ef7a TG |
404 | if (hpet2 < hpet1) |
405 | hpet2 += 0x100000000ULL; | |
406 | hpet2 -= hpet1; | |
407 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
408 | do_div(tmp, 1000000); | |
409 | do_div(deltatsc, tmp); | |
410 | ||
411 | return (unsigned long) deltatsc; | |
412 | } | |
413 | ||
414 | /* | |
415 | * Calculate the TSC frequency from PMTimer reference | |
416 | */ | |
417 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
418 | { | |
419 | u64 tmp; | |
bfc0f594 | 420 | |
d683ef7a TG |
421 | if (!pm1 && !pm2) |
422 | return ULONG_MAX; | |
423 | ||
424 | if (pm2 < pm1) | |
425 | pm2 += (u64)ACPI_PM_OVRRUN; | |
426 | pm2 -= pm1; | |
427 | tmp = pm2 * 1000000000LL; | |
428 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
429 | do_div(deltatsc, tmp); | |
430 | ||
431 | return (unsigned long) deltatsc; | |
432 | } | |
433 | ||
a977c400 | 434 | #define CAL_MS 10 |
b7743970 | 435 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
436 | #define CAL_PIT_LOOPS 1000 |
437 | ||
438 | #define CAL2_MS 50 | |
b7743970 | 439 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
440 | #define CAL2_PIT_LOOPS 5000 |
441 | ||
cce3e057 | 442 | |
ec0c15af LT |
443 | /* |
444 | * Try to calibrate the TSC against the Programmable | |
445 | * Interrupt Timer and return the frequency of the TSC | |
446 | * in kHz. | |
447 | * | |
448 | * Return ULONG_MAX on failure to calibrate. | |
449 | */ | |
a977c400 | 450 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
451 | { |
452 | u64 tsc, t1, t2, delta; | |
453 | unsigned long tscmin, tscmax; | |
454 | int pitcnt; | |
455 | ||
456 | /* Set the Gate high, disable speaker */ | |
457 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
458 | ||
459 | /* | |
460 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
461 | * count mode), binary count. Set the latch register to 50ms | |
462 | * (LSB then MSB) to begin countdown. | |
463 | */ | |
464 | outb(0xb0, 0x43); | |
a977c400 TG |
465 | outb(latch & 0xff, 0x42); |
466 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
467 | |
468 | tsc = t1 = t2 = get_cycles(); | |
469 | ||
470 | pitcnt = 0; | |
471 | tscmax = 0; | |
472 | tscmin = ULONG_MAX; | |
473 | while ((inb(0x61) & 0x20) == 0) { | |
474 | t2 = get_cycles(); | |
475 | delta = t2 - tsc; | |
476 | tsc = t2; | |
477 | if ((unsigned long) delta < tscmin) | |
478 | tscmin = (unsigned int) delta; | |
479 | if ((unsigned long) delta > tscmax) | |
480 | tscmax = (unsigned int) delta; | |
481 | pitcnt++; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Sanity checks: | |
486 | * | |
a977c400 | 487 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
488 | * times, then we have been hit by a massive SMI |
489 | * | |
490 | * If the maximum is 10 times larger than the minimum, | |
491 | * then we got hit by an SMI as well. | |
492 | */ | |
a977c400 | 493 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
494 | return ULONG_MAX; |
495 | ||
496 | /* Calculate the PIT value */ | |
497 | delta = t2 - t1; | |
a977c400 | 498 | do_div(delta, ms); |
ec0c15af LT |
499 | return delta; |
500 | } | |
501 | ||
6ac40ed0 LT |
502 | /* |
503 | * This reads the current MSB of the PIT counter, and | |
504 | * checks if we are running on sufficiently fast and | |
505 | * non-virtualized hardware. | |
506 | * | |
507 | * Our expectations are: | |
508 | * | |
509 | * - the PIT is running at roughly 1.19MHz | |
510 | * | |
511 | * - each IO is going to take about 1us on real hardware, | |
512 | * but we allow it to be much faster (by a factor of 10) or | |
513 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
514 | * update - anything else implies a unacceptably slow CPU | |
515 | * or PIT for the fast calibration to work. | |
516 | * | |
517 | * - with 256 PIT ticks to read the value, we have 214us to | |
518 | * see the same MSB (and overhead like doing a single TSC | |
519 | * read per MSB value etc). | |
520 | * | |
521 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
522 | * them each to take about a microsecond on real hardware. | |
523 | * So we expect a count value of around 100. But we'll be | |
524 | * generous, and accept anything over 50. | |
525 | * | |
526 | * - if the PIT is stuck, and we see *many* more reads, we | |
527 | * return early (and the next caller of pit_expect_msb() | |
528 | * then consider it a failure when they don't see the | |
529 | * next expected value). | |
530 | * | |
531 | * These expectations mean that we know that we have seen the | |
532 | * transition from one expected value to another with a fairly | |
533 | * high accuracy, and we didn't miss any events. We can thus | |
534 | * use the TSC value at the transitions to calculate a pretty | |
535 | * good value for the TSC frequencty. | |
536 | */ | |
b6e61eef LT |
537 | static inline int pit_verify_msb(unsigned char val) |
538 | { | |
539 | /* Ignore LSB */ | |
540 | inb(0x42); | |
541 | return inb(0x42) == val; | |
542 | } | |
543 | ||
9e8912e0 | 544 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 545 | { |
9e8912e0 | 546 | int count; |
68f30fbe | 547 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 548 | |
6ac40ed0 | 549 | for (count = 0; count < 50000; count++) { |
b6e61eef | 550 | if (!pit_verify_msb(val)) |
6ac40ed0 | 551 | break; |
68f30fbe | 552 | prev_tsc = tsc; |
9e8912e0 | 553 | tsc = get_cycles(); |
6ac40ed0 | 554 | } |
68f30fbe | 555 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
556 | *tscp = tsc; |
557 | ||
558 | /* | |
559 | * We require _some_ success, but the quality control | |
560 | * will be based on the error terms on the TSC values. | |
561 | */ | |
562 | return count > 5; | |
6ac40ed0 LT |
563 | } |
564 | ||
565 | /* | |
9e8912e0 LT |
566 | * How many MSB values do we want to see? We aim for |
567 | * a maximum error rate of 500ppm (in practice the | |
568 | * real error is much smaller), but refuse to spend | |
68f30fbe | 569 | * more than 50ms on it. |
6ac40ed0 | 570 | */ |
68f30fbe | 571 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 572 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 573 | |
6ac40ed0 LT |
574 | static unsigned long quick_pit_calibrate(void) |
575 | { | |
9e8912e0 LT |
576 | int i; |
577 | u64 tsc, delta; | |
578 | unsigned long d1, d2; | |
579 | ||
6ac40ed0 | 580 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
581 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
582 | ||
6ac40ed0 LT |
583 | /* |
584 | * Counter 2, mode 0 (one-shot), binary count | |
585 | * | |
586 | * NOTE! Mode 2 decrements by two (and then the | |
587 | * output is flipped each time, giving the same | |
588 | * final output frequency as a decrement-by-one), | |
589 | * so mode 0 is much better when looking at the | |
590 | * individual counts. | |
591 | */ | |
bfc0f594 | 592 | outb(0xb0, 0x43); |
bfc0f594 | 593 | |
6ac40ed0 LT |
594 | /* Start at 0xffff */ |
595 | outb(0xff, 0x42); | |
596 | outb(0xff, 0x42); | |
597 | ||
a6a80e1d LT |
598 | /* |
599 | * The PIT starts counting at the next edge, so we | |
600 | * need to delay for a microsecond. The easiest way | |
601 | * to do that is to just read back the 16-bit counter | |
602 | * once from the PIT. | |
603 | */ | |
b6e61eef | 604 | pit_verify_msb(0); |
a6a80e1d | 605 | |
9e8912e0 LT |
606 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
607 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
608 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
609 | break; | |
610 | ||
5aac644a AH |
611 | delta -= tsc; |
612 | ||
613 | /* | |
614 | * Extrapolate the error and fail fast if the error will | |
615 | * never be below 500 ppm. | |
616 | */ | |
617 | if (i == 1 && | |
618 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
619 | return 0; | |
620 | ||
9e8912e0 LT |
621 | /* |
622 | * Iterate until the error is less than 500 ppm | |
623 | */ | |
b6e61eef LT |
624 | if (d1+d2 >= delta >> 11) |
625 | continue; | |
626 | ||
627 | /* | |
628 | * Check the PIT one more time to verify that | |
629 | * all TSC reads were stable wrt the PIT. | |
630 | * | |
631 | * This also guarantees serialization of the | |
632 | * last cycle read ('d2') in pit_expect_msb. | |
633 | */ | |
634 | if (!pit_verify_msb(0xfe - i)) | |
635 | break; | |
636 | goto success; | |
6ac40ed0 | 637 | } |
6ac40ed0 | 638 | } |
52045217 | 639 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 640 | return 0; |
9e8912e0 LT |
641 | |
642 | success: | |
643 | /* | |
644 | * Ok, if we get here, then we've seen the | |
645 | * MSB of the PIT decrement 'i' times, and the | |
646 | * error has shrunk to less than 500 ppm. | |
647 | * | |
648 | * As a result, we can depend on there not being | |
649 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 650 | * reliable (within the error). |
9e8912e0 LT |
651 | * |
652 | * kHz = ticks / time-in-seconds / 1000; | |
653 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
654 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
655 | */ | |
9e8912e0 LT |
656 | delta *= PIT_TICK_RATE; |
657 | do_div(delta, i*256*1000); | |
c767a54b | 658 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 659 | return delta; |
6ac40ed0 | 660 | } |
ec0c15af | 661 | |
bfc0f594 | 662 | /** |
e93ef949 | 663 | * native_calibrate_tsc - calibrate the tsc on boot |
bfc0f594 | 664 | */ |
e93ef949 | 665 | unsigned long native_calibrate_tsc(void) |
bfc0f594 | 666 | { |
827014be | 667 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 668 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 669 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 670 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 671 | |
7da7c156 BG |
672 | /* Calibrate TSC using MSR for Intel Atom SoCs */ |
673 | local_irq_save(flags); | |
5f0e0309 | 674 | fast_calibrate = try_msr_calibrate_tsc(); |
7da7c156 | 675 | local_irq_restore(flags); |
5f0e0309 | 676 | if (fast_calibrate) |
7da7c156 | 677 | return fast_calibrate; |
7da7c156 | 678 | |
6ac40ed0 LT |
679 | local_irq_save(flags); |
680 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 681 | local_irq_restore(flags); |
6ac40ed0 LT |
682 | if (fast_calibrate) |
683 | return fast_calibrate; | |
bfc0f594 | 684 | |
fbb16e24 TG |
685 | /* |
686 | * Run 5 calibration loops to get the lowest frequency value | |
687 | * (the best estimate). We use two different calibration modes | |
688 | * here: | |
689 | * | |
690 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
691 | * load a timeout of 50ms. We read the time right after we | |
692 | * started the timer and wait until the PIT count down reaches | |
693 | * zero. In each wait loop iteration we read the TSC and check | |
694 | * the delta to the previous read. We keep track of the min | |
695 | * and max values of that delta. The delta is mostly defined | |
696 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 697 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
698 | * maximum time is significantly larger than the minimum time, |
699 | * then we discard the result and have another try. | |
700 | * | |
701 | * 2) Reference counter. If available we use the HPET or the | |
702 | * PMTIMER as a reference to check the sanity of that value. | |
703 | * We use separate TSC readouts and check inside of the | |
704 | * reference read for a SMI/SMM disturbance. We dicard | |
705 | * disturbed values here as well. We do that around the PIT | |
706 | * calibration delay loop as we have to wait for a certain | |
707 | * amount of time anyway. | |
708 | */ | |
a977c400 TG |
709 | |
710 | /* Preset PIT loop values */ | |
711 | latch = CAL_LATCH; | |
712 | ms = CAL_MS; | |
713 | loopmin = CAL_PIT_LOOPS; | |
714 | ||
715 | for (i = 0; i < 3; i++) { | |
ec0c15af | 716 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
717 | |
718 | /* | |
719 | * Read the start value and the reference count of | |
ec0c15af LT |
720 | * hpet/pmtimer when available. Then do the PIT |
721 | * calibration, which will take at least 50ms, and | |
722 | * read the end value. | |
fbb16e24 | 723 | */ |
ec0c15af | 724 | local_irq_save(flags); |
827014be | 725 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 726 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 727 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
728 | local_irq_restore(flags); |
729 | ||
ec0c15af LT |
730 | /* Pick the lowest PIT TSC calibration so far */ |
731 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
732 | |
733 | /* hpet or pmtimer available ? */ | |
62627bec | 734 | if (ref1 == ref2) |
fbb16e24 TG |
735 | continue; |
736 | ||
737 | /* Check, whether the sampling was disturbed by an SMI */ | |
738 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
739 | continue; | |
740 | ||
741 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 742 | if (hpet) |
827014be | 743 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 744 | else |
827014be | 745 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 746 | |
fbb16e24 | 747 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
748 | |
749 | /* Check the reference deviation */ | |
750 | delta = ((u64) tsc_pit_min) * 100; | |
751 | do_div(delta, tsc_ref_min); | |
752 | ||
753 | /* | |
754 | * If both calibration results are inside a 10% window | |
755 | * then we can be sure, that the calibration | |
756 | * succeeded. We break out of the loop right away. We | |
757 | * use the reference value, as it is more precise. | |
758 | */ | |
759 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
760 | pr_info("PIT calibration matches %s. %d loops\n", |
761 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 762 | return tsc_ref_min; |
fbb16e24 TG |
763 | } |
764 | ||
a977c400 TG |
765 | /* |
766 | * Check whether PIT failed more than once. This | |
767 | * happens in virtualized environments. We need to | |
768 | * give the virtual PC a slightly longer timeframe for | |
769 | * the HPET/PMTIMER to make the result precise. | |
770 | */ | |
771 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
772 | latch = CAL2_LATCH; | |
773 | ms = CAL2_MS; | |
774 | loopmin = CAL2_PIT_LOOPS; | |
775 | } | |
fbb16e24 | 776 | } |
bfc0f594 AK |
777 | |
778 | /* | |
fbb16e24 | 779 | * Now check the results. |
bfc0f594 | 780 | */ |
fbb16e24 TG |
781 | if (tsc_pit_min == ULONG_MAX) { |
782 | /* PIT gave no useful value */ | |
c767a54b | 783 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
784 | |
785 | /* We don't have an alternative source, disable TSC */ | |
827014be | 786 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 787 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
788 | return 0; |
789 | } | |
790 | ||
791 | /* The alternative source failed as well, disable TSC */ | |
792 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 793 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
794 | return 0; |
795 | } | |
796 | ||
797 | /* Use the alternative source */ | |
c767a54b JP |
798 | pr_info("using %s reference calibration\n", |
799 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
800 | |
801 | return tsc_ref_min; | |
802 | } | |
bfc0f594 | 803 | |
fbb16e24 | 804 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 805 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 806 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 807 | return tsc_pit_min; |
bfc0f594 AK |
808 | } |
809 | ||
fbb16e24 TG |
810 | /* The alternative source failed, use the PIT calibration value */ |
811 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 812 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 813 | return tsc_pit_min; |
bfc0f594 AK |
814 | } |
815 | ||
fbb16e24 TG |
816 | /* |
817 | * The calibration values differ too much. In doubt, we use | |
818 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 819 | * running at double speed. At least we let the user know: |
fbb16e24 | 820 | */ |
c767a54b JP |
821 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
822 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
823 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 824 | return tsc_pit_min; |
bfc0f594 AK |
825 | } |
826 | ||
bfc0f594 AK |
827 | int recalibrate_cpu_khz(void) |
828 | { | |
829 | #ifndef CONFIG_SMP | |
830 | unsigned long cpu_khz_old = cpu_khz; | |
831 | ||
832 | if (cpu_has_tsc) { | |
2d826404 | 833 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 834 | cpu_khz = tsc_khz; |
bfc0f594 AK |
835 | cpu_data(0).loops_per_jiffy = |
836 | cpufreq_scale(cpu_data(0).loops_per_jiffy, | |
837 | cpu_khz_old, cpu_khz); | |
838 | return 0; | |
839 | } else | |
840 | return -ENODEV; | |
841 | #else | |
842 | return -ENODEV; | |
843 | #endif | |
844 | } | |
845 | ||
846 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
847 | ||
2dbe06fa | 848 | |
cd7240c0 SS |
849 | static unsigned long long cyc2ns_suspend; |
850 | ||
b74f05d6 | 851 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 852 | { |
35af99e6 | 853 | if (!sched_clock_stable()) |
cd7240c0 SS |
854 | return; |
855 | ||
856 | cyc2ns_suspend = sched_clock(); | |
857 | } | |
858 | ||
859 | /* | |
860 | * Even on processors with invariant TSC, TSC gets reset in some the | |
861 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
862 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
863 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
864 | * that sched_clock() continues from the point where it was left off during | |
865 | * suspend. | |
866 | */ | |
b74f05d6 | 867 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
868 | { |
869 | unsigned long long offset; | |
870 | unsigned long flags; | |
871 | int cpu; | |
872 | ||
35af99e6 | 873 | if (!sched_clock_stable()) |
cd7240c0 SS |
874 | return; |
875 | ||
876 | local_irq_save(flags); | |
877 | ||
20d1c86a PZ |
878 | /* |
879 | * We're comming out of suspend, there's no concurrency yet; don't | |
880 | * bother being nice about the RCU stuff, just write to both | |
881 | * data fields. | |
882 | */ | |
883 | ||
884 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
885 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
886 | ||
cd7240c0 SS |
887 | offset = cyc2ns_suspend - sched_clock(); |
888 | ||
20d1c86a PZ |
889 | for_each_possible_cpu(cpu) { |
890 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
891 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
892 | } | |
cd7240c0 SS |
893 | |
894 | local_irq_restore(flags); | |
895 | } | |
896 | ||
2dbe06fa AK |
897 | #ifdef CONFIG_CPU_FREQ |
898 | ||
899 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
900 | * changes. | |
901 | * | |
902 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
903 | * not that important because current Opteron setups do not support | |
904 | * scaling on SMP anyroads. | |
905 | * | |
906 | * Should fix up last_tsc too. Currently gettimeofday in the | |
907 | * first tick after the change will be slightly wrong. | |
908 | */ | |
909 | ||
910 | static unsigned int ref_freq; | |
911 | static unsigned long loops_per_jiffy_ref; | |
912 | static unsigned long tsc_khz_ref; | |
913 | ||
914 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
915 | void *data) | |
916 | { | |
917 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 918 | unsigned long *lpj; |
2dbe06fa AK |
919 | |
920 | if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) | |
921 | return 0; | |
922 | ||
931db6a3 | 923 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 924 | #ifdef CONFIG_SMP |
931db6a3 | 925 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 926 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
927 | #endif |
928 | ||
929 | if (!ref_freq) { | |
930 | ref_freq = freq->old; | |
931 | loops_per_jiffy_ref = *lpj; | |
932 | tsc_khz_ref = tsc_khz; | |
933 | } | |
934 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 935 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 936 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
937 | |
938 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
939 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
940 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 941 | |
3896c329 PZ |
942 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
943 | } | |
2dbe06fa AK |
944 | |
945 | return 0; | |
946 | } | |
947 | ||
948 | static struct notifier_block time_cpufreq_notifier_block = { | |
949 | .notifier_call = time_cpufreq_notifier | |
950 | }; | |
951 | ||
952 | static int __init cpufreq_tsc(void) | |
953 | { | |
060700b5 LT |
954 | if (!cpu_has_tsc) |
955 | return 0; | |
956 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
957 | return 0; | |
2dbe06fa AK |
958 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
959 | CPUFREQ_TRANSITION_NOTIFIER); | |
960 | return 0; | |
961 | } | |
962 | ||
963 | core_initcall(cpufreq_tsc); | |
964 | ||
965 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 AK |
966 | |
967 | /* clocksource code */ | |
968 | ||
969 | static struct clocksource clocksource_tsc; | |
970 | ||
971 | /* | |
09ec5442 | 972 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
973 | * structure to avoid a nasty time-warp. This can be observed in a |
974 | * very small window right after one CPU updated cycle_last under | |
975 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
976 | * is smaller than the cycle_last reference value due to a TSC which | |
977 | * is slighty behind. This delta is nowhere else observable, but in | |
978 | * that case it results in a forward time jump in the range of hours | |
979 | * due to the unsigned delta calculation of the time keeping core | |
980 | * code, which is necessary to support wrapping clocksources like pm | |
981 | * timer. | |
09ec5442 TG |
982 | * |
983 | * This sanity check is now done in the core timekeeping code. | |
984 | * checking the result of read_tsc() - cycle_last for being negative. | |
985 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 986 | */ |
8e19608e | 987 | static cycle_t read_tsc(struct clocksource *cs) |
8fbbc4b4 | 988 | { |
27c63405 | 989 | return (cycle_t)rdtsc_ordered(); |
1be39679 MS |
990 | } |
991 | ||
09ec5442 TG |
992 | /* |
993 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
994 | */ | |
8fbbc4b4 AK |
995 | static struct clocksource clocksource_tsc = { |
996 | .name = "tsc", | |
997 | .rating = 300, | |
998 | .read = read_tsc, | |
999 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 AK |
1000 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
1001 | CLOCK_SOURCE_MUST_VERIFY, | |
98d0ac38 | 1002 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
8fbbc4b4 AK |
1003 | }; |
1004 | ||
1005 | void mark_tsc_unstable(char *reason) | |
1006 | { | |
1007 | if (!tsc_unstable) { | |
1008 | tsc_unstable = 1; | |
35af99e6 | 1009 | clear_sched_clock_stable(); |
e82b8e4e | 1010 | disable_sched_clock_irqtime(); |
c767a54b | 1011 | pr_info("Marking TSC unstable due to %s\n", reason); |
8fbbc4b4 AK |
1012 | /* Change only the rating, when not registered */ |
1013 | if (clocksource_tsc.mult) | |
7285dd7f TG |
1014 | clocksource_mark_unstable(&clocksource_tsc); |
1015 | else { | |
1016 | clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; | |
8fbbc4b4 | 1017 | clocksource_tsc.rating = 0; |
7285dd7f | 1018 | } |
8fbbc4b4 AK |
1019 | } |
1020 | } | |
1021 | ||
1022 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1023 | ||
395628ef AK |
1024 | static void __init check_system_tsc_reliable(void) |
1025 | { | |
03da3ff1 DW |
1026 | #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) |
1027 | if (is_geode_lx()) { | |
1028 | /* RTSC counts during suspend */ | |
8fbbc4b4 | 1029 | #define RTSC_SUSP 0x100 |
03da3ff1 | 1030 | unsigned long res_low, res_high; |
8fbbc4b4 | 1031 | |
03da3ff1 DW |
1032 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); |
1033 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ | |
1034 | if (res_low & RTSC_SUSP) | |
1035 | tsc_clocksource_reliable = 1; | |
1036 | } | |
8fbbc4b4 | 1037 | #endif |
395628ef AK |
1038 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1039 | tsc_clocksource_reliable = 1; | |
1040 | } | |
8fbbc4b4 AK |
1041 | |
1042 | /* | |
1043 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1044 | * over all CPUs. | |
1045 | */ | |
148f9bb8 | 1046 | int unsynchronized_tsc(void) |
8fbbc4b4 AK |
1047 | { |
1048 | if (!cpu_has_tsc || tsc_unstable) | |
1049 | return 1; | |
1050 | ||
3e5095d1 | 1051 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1052 | if (apic_is_clustered_box()) |
1053 | return 1; | |
1054 | #endif | |
1055 | ||
1056 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1057 | return 0; | |
d3b8f889 JS |
1058 | |
1059 | if (tsc_clocksource_reliable) | |
1060 | return 0; | |
8fbbc4b4 AK |
1061 | /* |
1062 | * Intel systems are normally all synchronized. | |
1063 | * Exceptions must mark TSC as unstable: | |
1064 | */ | |
1065 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1066 | /* assume multi socket systems are not synchronized: */ | |
1067 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1068 | return 1; |
8fbbc4b4 AK |
1069 | } |
1070 | ||
d3b8f889 | 1071 | return 0; |
8fbbc4b4 AK |
1072 | } |
1073 | ||
08ec0c58 JS |
1074 | |
1075 | static void tsc_refine_calibration_work(struct work_struct *work); | |
1076 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1077 | /** | |
1078 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1079 | * @work - ignored. | |
1080 | * | |
1081 | * This functions uses delayed work over a period of a | |
1082 | * second to further refine the TSC freq value. Since this is | |
1083 | * timer based, instead of loop based, we don't block the boot | |
1084 | * process while this longer calibration is done. | |
1085 | * | |
0d2eb44f | 1086 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1087 | * or the refined calibration is off by 1% of the fast early |
1088 | * calibration, we throw out the new calibration and use the | |
1089 | * early calibration. | |
1090 | */ | |
1091 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1092 | { | |
1093 | static u64 tsc_start = -1, ref_start; | |
1094 | static int hpet; | |
1095 | u64 tsc_stop, ref_stop, delta; | |
1096 | unsigned long freq; | |
1097 | ||
1098 | /* Don't bother refining TSC on unstable systems */ | |
1099 | if (check_tsc_unstable()) | |
1100 | goto out; | |
1101 | ||
1102 | /* | |
1103 | * Since the work is started early in boot, we may be | |
1104 | * delayed the first time we expire. So set the workqueue | |
1105 | * again once we know timers are working. | |
1106 | */ | |
1107 | if (tsc_start == -1) { | |
1108 | /* | |
1109 | * Only set hpet once, to avoid mixing hardware | |
1110 | * if the hpet becomes enabled later. | |
1111 | */ | |
1112 | hpet = is_hpet_enabled(); | |
1113 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1114 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1119 | ||
1120 | /* hpet or pmtimer available ? */ | |
62627bec | 1121 | if (ref_start == ref_stop) |
08ec0c58 JS |
1122 | goto out; |
1123 | ||
1124 | /* Check, whether the sampling was disturbed by an SMI */ | |
1125 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1126 | goto out; | |
1127 | ||
1128 | delta = tsc_stop - tsc_start; | |
1129 | delta *= 1000000LL; | |
1130 | if (hpet) | |
1131 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1132 | else | |
1133 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1134 | ||
1135 | /* Make sure we're within 1% */ | |
1136 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1137 | goto out; | |
1138 | ||
1139 | tsc_khz = freq; | |
c767a54b JP |
1140 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1141 | (unsigned long)tsc_khz / 1000, | |
1142 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 JS |
1143 | |
1144 | out: | |
1145 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
1146 | } | |
1147 | ||
1148 | ||
1149 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1150 | { |
29fe359c | 1151 | if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
1152 | return 0; |
1153 | ||
395628ef AK |
1154 | if (tsc_clocksource_reliable) |
1155 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
1156 | /* lower the rating if we already know its unstable: */ |
1157 | if (check_tsc_unstable()) { | |
1158 | clocksource_tsc.rating = 0; | |
1159 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
1160 | } | |
57779dc2 | 1161 | |
82f9c080 FT |
1162 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1163 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1164 | ||
57779dc2 AK |
1165 | /* |
1166 | * Trust the results of the earlier calibration on systems | |
1167 | * exporting a reliable TSC. | |
1168 | */ | |
1169 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { | |
1170 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
1171 | return 0; | |
1172 | } | |
1173 | ||
08ec0c58 JS |
1174 | schedule_delayed_work(&tsc_irqwork, 0); |
1175 | return 0; | |
8fbbc4b4 | 1176 | } |
08ec0c58 JS |
1177 | /* |
1178 | * We use device_initcall here, to ensure we run after the hpet | |
1179 | * is fully initialized, which may occur at fs_initcall time. | |
1180 | */ | |
1181 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 AK |
1182 | |
1183 | void __init tsc_init(void) | |
1184 | { | |
1185 | u64 lpj; | |
1186 | int cpu; | |
1187 | ||
845b3944 TG |
1188 | x86_init.timers.tsc_pre_init(); |
1189 | ||
b47dcbdc AL |
1190 | if (!cpu_has_tsc) { |
1191 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
8fbbc4b4 | 1192 | return; |
b47dcbdc | 1193 | } |
8fbbc4b4 | 1194 | |
2d826404 | 1195 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 1196 | cpu_khz = tsc_khz; |
8fbbc4b4 | 1197 | |
e93ef949 | 1198 | if (!tsc_khz) { |
8fbbc4b4 | 1199 | mark_tsc_unstable("could not calculate TSC khz"); |
b47dcbdc | 1200 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 AK |
1201 | return; |
1202 | } | |
1203 | ||
c767a54b JP |
1204 | pr_info("Detected %lu.%03lu MHz processor\n", |
1205 | (unsigned long)cpu_khz / 1000, | |
1206 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 AK |
1207 | |
1208 | /* | |
1209 | * Secondary CPUs do not run through tsc_init(), so set up | |
1210 | * all the scale factors for all CPUs, assuming the same | |
1211 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1212 | * up if their speed diverges) | |
1213 | */ | |
20d1c86a PZ |
1214 | for_each_possible_cpu(cpu) { |
1215 | cyc2ns_init(cpu); | |
8fbbc4b4 | 1216 | set_cyc2ns_scale(cpu_khz, cpu); |
20d1c86a | 1217 | } |
8fbbc4b4 AK |
1218 | |
1219 | if (tsc_disabled > 0) | |
1220 | return; | |
1221 | ||
1222 | /* now allow native_sched_clock() to use rdtsc */ | |
10b033d4 | 1223 | |
8fbbc4b4 | 1224 | tsc_disabled = 0; |
3bbfafb7 | 1225 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1226 | |
e82b8e4e VP |
1227 | if (!no_sched_irq_time) |
1228 | enable_sched_clock_irqtime(); | |
1229 | ||
70de9a97 AK |
1230 | lpj = ((u64)tsc_khz * 1000); |
1231 | do_div(lpj, HZ); | |
1232 | lpj_fine = lpj; | |
1233 | ||
8fbbc4b4 | 1234 | use_tsc_delay(); |
8fbbc4b4 AK |
1235 | |
1236 | if (unsynchronized_tsc()) | |
1237 | mark_tsc_unstable("TSCs unsynchronized"); | |
1238 | ||
395628ef | 1239 | check_system_tsc_reliable(); |
8fbbc4b4 AK |
1240 | } |
1241 | ||
b565201c JS |
1242 | #ifdef CONFIG_SMP |
1243 | /* | |
1244 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1245 | * we can skip clock calibration if another cpu in the same socket has already | |
1246 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1247 | * cpus in the socket - this should be a safe assumption. | |
1248 | */ | |
148f9bb8 | 1249 | unsigned long calibrate_delay_is_known(void) |
b565201c JS |
1250 | { |
1251 | int i, cpu = smp_processor_id(); | |
1252 | ||
1253 | if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC)) | |
1254 | return 0; | |
1255 | ||
1256 | for_each_online_cpu(i) | |
1257 | if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id) | |
1258 | return cpu_data(i).loops_per_jiffy; | |
1259 | return 0; | |
1260 | } | |
1261 | #endif |