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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 AK |
4 | #include <linux/sched.h> |
5 | #include <linux/init.h> | |
6 | #include <linux/module.h> | |
7 | #include <linux/timer.h> | |
bfc0f594 | 8 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 9 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
10 | #include <linux/delay.h> |
11 | #include <linux/clocksource.h> | |
12 | #include <linux/percpu.h> | |
08604bd9 | 13 | #include <linux/timex.h> |
10b033d4 | 14 | #include <linux/static_key.h> |
bfc0f594 AK |
15 | |
16 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
17 | #include <asm/timer.h> |
18 | #include <asm/vgtod.h> | |
19 | #include <asm/time.h> | |
20 | #include <asm/delay.h> | |
88b094fb | 21 | #include <asm/hypervisor.h> |
08047c4f | 22 | #include <asm/nmi.h> |
2d826404 | 23 | #include <asm/x86_init.h> |
03da3ff1 | 24 | #include <asm/geode.h> |
0ef95533 | 25 | |
f24ade3a | 26 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 27 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
28 | |
29 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
30 | EXPORT_SYMBOL(tsc_khz); |
31 | ||
32 | /* | |
33 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
34 | */ | |
f24ade3a | 35 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
36 | |
37 | /* native_sched_clock() is called before tsc_init(), so | |
38 | we must start with the TSC soft disabled to prevent | |
39 | erroneous rdtsc usage on !cpu_has_tsc processors */ | |
f24ade3a | 40 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 41 | |
3bbfafb7 | 42 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 43 | |
28a00184 | 44 | int tsc_clocksource_reliable; |
57c67da2 | 45 | |
f9677e0f CH |
46 | static u32 art_to_tsc_numerator; |
47 | static u32 art_to_tsc_denominator; | |
48 | static u64 art_to_tsc_offset; | |
49 | struct clocksource *art_related_clocksource; | |
50 | ||
20d1c86a PZ |
51 | /* |
52 | * Use a ring-buffer like data structure, where a writer advances the head by | |
53 | * writing a new data entry and a reader advances the tail when it observes a | |
54 | * new entry. | |
55 | * | |
56 | * Writers are made to wait on readers until there's space to write a new | |
57 | * entry. | |
58 | * | |
59 | * This means that we can always use an {offset, mul} pair to compute a ns | |
60 | * value that is 'roughly' in the right direction, even if we're writing a new | |
61 | * {offset, mul} pair during the clock read. | |
62 | * | |
63 | * The down-side is that we can no longer guarantee strict monotonicity anymore | |
64 | * (assuming the TSC was that to begin with), because while we compute the | |
65 | * intersection point of the two clock slopes and make sure the time is | |
66 | * continuous at the point of switching; we can no longer guarantee a reader is | |
67 | * strictly before or after the switch point. | |
68 | * | |
69 | * It does mean a reader no longer needs to disable IRQs in order to avoid | |
70 | * CPU-Freq updates messing with his times, and similarly an NMI reader will | |
71 | * no longer run the risk of hitting half-written state. | |
72 | */ | |
73 | ||
74 | struct cyc2ns { | |
75 | struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */ | |
76 | struct cyc2ns_data *head; /* 48 + 8 = 56 */ | |
77 | struct cyc2ns_data *tail; /* 56 + 8 = 64 */ | |
78 | }; /* exactly fits one cacheline */ | |
79 | ||
80 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); | |
81 | ||
82 | struct cyc2ns_data *cyc2ns_read_begin(void) | |
83 | { | |
84 | struct cyc2ns_data *head; | |
85 | ||
86 | preempt_disable(); | |
87 | ||
88 | head = this_cpu_read(cyc2ns.head); | |
89 | /* | |
90 | * Ensure we observe the entry when we observe the pointer to it. | |
91 | * matches the wmb from cyc2ns_write_end(). | |
92 | */ | |
93 | smp_read_barrier_depends(); | |
94 | head->__count++; | |
95 | barrier(); | |
96 | ||
97 | return head; | |
98 | } | |
99 | ||
100 | void cyc2ns_read_end(struct cyc2ns_data *head) | |
101 | { | |
102 | barrier(); | |
103 | /* | |
104 | * If we're the outer most nested read; update the tail pointer | |
105 | * when we're done. This notifies possible pending writers | |
106 | * that we've observed the head pointer and that the other | |
107 | * entry is now free. | |
108 | */ | |
109 | if (!--head->__count) { | |
110 | /* | |
111 | * x86-TSO does not reorder writes with older reads; | |
112 | * therefore once this write becomes visible to another | |
113 | * cpu, we must be finished reading the cyc2ns_data. | |
114 | * | |
115 | * matches with cyc2ns_write_begin(). | |
116 | */ | |
117 | this_cpu_write(cyc2ns.tail, head); | |
118 | } | |
119 | preempt_enable(); | |
120 | } | |
121 | ||
122 | /* | |
123 | * Begin writing a new @data entry for @cpu. | |
124 | * | |
125 | * Assumes some sort of write side lock; currently 'provided' by the assumption | |
126 | * that cpufreq will call its notifiers sequentially. | |
127 | */ | |
128 | static struct cyc2ns_data *cyc2ns_write_begin(int cpu) | |
129 | { | |
130 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
131 | struct cyc2ns_data *data = c2n->data; | |
132 | ||
133 | if (data == c2n->head) | |
134 | data++; | |
135 | ||
136 | /* XXX send an IPI to @cpu in order to guarantee a read? */ | |
137 | ||
138 | /* | |
139 | * When we observe the tail write from cyc2ns_read_end(), | |
140 | * the cpu must be done with that entry and its safe | |
141 | * to start writing to it. | |
142 | */ | |
143 | while (c2n->tail == data) | |
144 | cpu_relax(); | |
145 | ||
146 | return data; | |
147 | } | |
148 | ||
149 | static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data) | |
150 | { | |
151 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
152 | ||
153 | /* | |
154 | * Ensure the @data writes are visible before we publish the | |
155 | * entry. Matches the data-depencency in cyc2ns_read_begin(). | |
156 | */ | |
157 | smp_wmb(); | |
158 | ||
159 | ACCESS_ONCE(c2n->head) = data; | |
160 | } | |
161 | ||
162 | /* | |
163 | * Accelerators for sched_clock() | |
57c67da2 PZ |
164 | * convert from cycles(64bits) => nanoseconds (64bits) |
165 | * basic equation: | |
166 | * ns = cycles / (freq / ns_per_sec) | |
167 | * ns = cycles * (ns_per_sec / freq) | |
168 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
169 | * ns = cycles * (10^6 / cpu_khz) | |
170 | * | |
171 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
172 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
173 | * ns = cycles * cyc2ns_scale / SC | |
174 | * | |
175 | * And since SC is a constant power of two, we can convert the div | |
b20112ed AH |
176 | * into a shift. The larger SC is, the more accurate the conversion, but |
177 | * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication | |
178 | * (64-bit result) can be used. | |
57c67da2 | 179 | * |
b20112ed | 180 | * We can use khz divisor instead of mhz to keep a better precision. |
57c67da2 PZ |
181 | * (mathieu.desnoyers@polymtl.ca) |
182 | * | |
183 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
184 | */ | |
185 | ||
20d1c86a PZ |
186 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
187 | { | |
5e3c1afd | 188 | data->cyc2ns_mul = 0; |
b20112ed | 189 | data->cyc2ns_shift = 0; |
20d1c86a PZ |
190 | data->cyc2ns_offset = 0; |
191 | data->__count = 0; | |
192 | } | |
193 | ||
194 | static void cyc2ns_init(int cpu) | |
195 | { | |
196 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
197 | ||
198 | cyc2ns_data_init(&c2n->data[0]); | |
199 | cyc2ns_data_init(&c2n->data[1]); | |
200 | ||
201 | c2n->head = c2n->data; | |
202 | c2n->tail = c2n->data; | |
203 | } | |
204 | ||
57c67da2 PZ |
205 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
206 | { | |
20d1c86a PZ |
207 | struct cyc2ns_data *data, *tail; |
208 | unsigned long long ns; | |
209 | ||
210 | /* | |
211 | * See cyc2ns_read_*() for details; replicated in order to avoid | |
212 | * an extra few instructions that came with the abstraction. | |
213 | * Notable, it allows us to only do the __count and tail update | |
214 | * dance when its actually needed. | |
215 | */ | |
216 | ||
569d6557 | 217 | preempt_disable_notrace(); |
20d1c86a PZ |
218 | data = this_cpu_read(cyc2ns.head); |
219 | tail = this_cpu_read(cyc2ns.tail); | |
220 | ||
221 | if (likely(data == tail)) { | |
222 | ns = data->cyc2ns_offset; | |
b20112ed | 223 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
224 | } else { |
225 | data->__count++; | |
226 | ||
227 | barrier(); | |
228 | ||
229 | ns = data->cyc2ns_offset; | |
b20112ed | 230 | ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
231 | |
232 | barrier(); | |
233 | ||
234 | if (!--data->__count) | |
235 | this_cpu_write(cyc2ns.tail, data); | |
236 | } | |
569d6557 | 237 | preempt_enable_notrace(); |
20d1c86a | 238 | |
57c67da2 PZ |
239 | return ns; |
240 | } | |
241 | ||
242 | static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) | |
243 | { | |
20d1c86a PZ |
244 | unsigned long long tsc_now, ns_now; |
245 | struct cyc2ns_data *data; | |
246 | unsigned long flags; | |
57c67da2 PZ |
247 | |
248 | local_irq_save(flags); | |
249 | sched_clock_idle_sleep_event(); | |
250 | ||
20d1c86a PZ |
251 | if (!cpu_khz) |
252 | goto done; | |
253 | ||
254 | data = cyc2ns_write_begin(cpu); | |
57c67da2 | 255 | |
4ea1636b | 256 | tsc_now = rdtsc(); |
57c67da2 PZ |
257 | ns_now = cycles_2_ns(tsc_now); |
258 | ||
20d1c86a PZ |
259 | /* |
260 | * Compute a new multiplier as per the above comment and ensure our | |
261 | * time function is continuous; see the comment near struct | |
262 | * cyc2ns_data. | |
263 | */ | |
b20112ed AH |
264 | clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz, |
265 | NSEC_PER_MSEC, 0); | |
266 | ||
b9511cd7 AH |
267 | /* |
268 | * cyc2ns_shift is exported via arch_perf_update_userpage() where it is | |
269 | * not expected to be greater than 31 due to the original published | |
270 | * conversion algorithm shifting a 32-bit value (now specifies a 64-bit | |
271 | * value) - refer perf_event_mmap_page documentation in perf_event.h. | |
272 | */ | |
273 | if (data->cyc2ns_shift == 32) { | |
274 | data->cyc2ns_shift = 31; | |
275 | data->cyc2ns_mul >>= 1; | |
276 | } | |
277 | ||
20d1c86a | 278 | data->cyc2ns_offset = ns_now - |
b20112ed | 279 | mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift); |
20d1c86a PZ |
280 | |
281 | cyc2ns_write_end(cpu, data); | |
57c67da2 | 282 | |
20d1c86a | 283 | done: |
57c67da2 PZ |
284 | sched_clock_idle_wakeup_event(0); |
285 | local_irq_restore(flags); | |
286 | } | |
0ef95533 AK |
287 | /* |
288 | * Scheduler clock - returns current time in nanosec units. | |
289 | */ | |
290 | u64 native_sched_clock(void) | |
291 | { | |
3bbfafb7 PZ |
292 | if (static_branch_likely(&__use_tsc)) { |
293 | u64 tsc_now = rdtsc(); | |
294 | ||
295 | /* return the value in ns */ | |
296 | return cycles_2_ns(tsc_now); | |
297 | } | |
0ef95533 AK |
298 | |
299 | /* | |
300 | * Fall back to jiffies if there's no TSC available: | |
301 | * ( But note that we still use it if the TSC is marked | |
302 | * unstable. We do this because unlike Time Of Day, | |
303 | * the scheduler clock tolerates small errors and it's | |
304 | * very important for it to be as fast as the platform | |
3ad2f3fb | 305 | * can achieve it. ) |
0ef95533 | 306 | */ |
0ef95533 | 307 | |
3bbfafb7 PZ |
308 | /* No locking but a rare wrong value is not a big deal: */ |
309 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
310 | } |
311 | ||
a94cab23 AK |
312 | /* |
313 | * Generate a sched_clock if you already have a TSC value. | |
314 | */ | |
315 | u64 native_sched_clock_from_tsc(u64 tsc) | |
316 | { | |
317 | return cycles_2_ns(tsc); | |
318 | } | |
319 | ||
0ef95533 AK |
320 | /* We need to define a real function for sched_clock, to override the |
321 | weak default version */ | |
322 | #ifdef CONFIG_PARAVIRT | |
323 | unsigned long long sched_clock(void) | |
324 | { | |
325 | return paravirt_sched_clock(); | |
326 | } | |
327 | #else | |
328 | unsigned long long | |
329 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
330 | #endif | |
331 | ||
332 | int check_tsc_unstable(void) | |
333 | { | |
334 | return tsc_unstable; | |
335 | } | |
336 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
337 | ||
c73deb6a AH |
338 | int check_tsc_disabled(void) |
339 | { | |
340 | return tsc_disabled; | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(check_tsc_disabled); | |
343 | ||
0ef95533 AK |
344 | #ifdef CONFIG_X86_TSC |
345 | int __init notsc_setup(char *str) | |
346 | { | |
c767a54b | 347 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
348 | tsc_disabled = 1; |
349 | return 1; | |
350 | } | |
351 | #else | |
352 | /* | |
353 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
354 | * in cpu/common.c | |
355 | */ | |
356 | int __init notsc_setup(char *str) | |
357 | { | |
358 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
359 | return 1; | |
360 | } | |
361 | #endif | |
362 | ||
363 | __setup("notsc", notsc_setup); | |
bfc0f594 | 364 | |
e82b8e4e VP |
365 | static int no_sched_irq_time; |
366 | ||
395628ef AK |
367 | static int __init tsc_setup(char *str) |
368 | { | |
369 | if (!strcmp(str, "reliable")) | |
370 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
371 | if (!strncmp(str, "noirqtime", 9)) |
372 | no_sched_irq_time = 1; | |
395628ef AK |
373 | return 1; |
374 | } | |
375 | ||
376 | __setup("tsc=", tsc_setup); | |
377 | ||
bfc0f594 AK |
378 | #define MAX_RETRIES 5 |
379 | #define SMI_TRESHOLD 50000 | |
380 | ||
381 | /* | |
382 | * Read TSC and the reference counters. Take care of SMI disturbance | |
383 | */ | |
827014be | 384 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
385 | { |
386 | u64 t1, t2; | |
387 | int i; | |
388 | ||
389 | for (i = 0; i < MAX_RETRIES; i++) { | |
390 | t1 = get_cycles(); | |
391 | if (hpet) | |
827014be | 392 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 393 | else |
827014be | 394 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
395 | t2 = get_cycles(); |
396 | if ((t2 - t1) < SMI_TRESHOLD) | |
397 | return t2; | |
398 | } | |
399 | return ULLONG_MAX; | |
400 | } | |
401 | ||
d683ef7a TG |
402 | /* |
403 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 404 | */ |
d683ef7a | 405 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 406 | { |
d683ef7a | 407 | u64 tmp; |
bfc0f594 | 408 | |
d683ef7a TG |
409 | if (hpet2 < hpet1) |
410 | hpet2 += 0x100000000ULL; | |
411 | hpet2 -= hpet1; | |
412 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
413 | do_div(tmp, 1000000); | |
414 | do_div(deltatsc, tmp); | |
415 | ||
416 | return (unsigned long) deltatsc; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Calculate the TSC frequency from PMTimer reference | |
421 | */ | |
422 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
423 | { | |
424 | u64 tmp; | |
bfc0f594 | 425 | |
d683ef7a TG |
426 | if (!pm1 && !pm2) |
427 | return ULONG_MAX; | |
428 | ||
429 | if (pm2 < pm1) | |
430 | pm2 += (u64)ACPI_PM_OVRRUN; | |
431 | pm2 -= pm1; | |
432 | tmp = pm2 * 1000000000LL; | |
433 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
434 | do_div(deltatsc, tmp); | |
435 | ||
436 | return (unsigned long) deltatsc; | |
437 | } | |
438 | ||
a977c400 | 439 | #define CAL_MS 10 |
b7743970 | 440 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
441 | #define CAL_PIT_LOOPS 1000 |
442 | ||
443 | #define CAL2_MS 50 | |
b7743970 | 444 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
445 | #define CAL2_PIT_LOOPS 5000 |
446 | ||
cce3e057 | 447 | |
ec0c15af LT |
448 | /* |
449 | * Try to calibrate the TSC against the Programmable | |
450 | * Interrupt Timer and return the frequency of the TSC | |
451 | * in kHz. | |
452 | * | |
453 | * Return ULONG_MAX on failure to calibrate. | |
454 | */ | |
a977c400 | 455 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
456 | { |
457 | u64 tsc, t1, t2, delta; | |
458 | unsigned long tscmin, tscmax; | |
459 | int pitcnt; | |
460 | ||
461 | /* Set the Gate high, disable speaker */ | |
462 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
463 | ||
464 | /* | |
465 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
466 | * count mode), binary count. Set the latch register to 50ms | |
467 | * (LSB then MSB) to begin countdown. | |
468 | */ | |
469 | outb(0xb0, 0x43); | |
a977c400 TG |
470 | outb(latch & 0xff, 0x42); |
471 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
472 | |
473 | tsc = t1 = t2 = get_cycles(); | |
474 | ||
475 | pitcnt = 0; | |
476 | tscmax = 0; | |
477 | tscmin = ULONG_MAX; | |
478 | while ((inb(0x61) & 0x20) == 0) { | |
479 | t2 = get_cycles(); | |
480 | delta = t2 - tsc; | |
481 | tsc = t2; | |
482 | if ((unsigned long) delta < tscmin) | |
483 | tscmin = (unsigned int) delta; | |
484 | if ((unsigned long) delta > tscmax) | |
485 | tscmax = (unsigned int) delta; | |
486 | pitcnt++; | |
487 | } | |
488 | ||
489 | /* | |
490 | * Sanity checks: | |
491 | * | |
a977c400 | 492 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
493 | * times, then we have been hit by a massive SMI |
494 | * | |
495 | * If the maximum is 10 times larger than the minimum, | |
496 | * then we got hit by an SMI as well. | |
497 | */ | |
a977c400 | 498 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
499 | return ULONG_MAX; |
500 | ||
501 | /* Calculate the PIT value */ | |
502 | delta = t2 - t1; | |
a977c400 | 503 | do_div(delta, ms); |
ec0c15af LT |
504 | return delta; |
505 | } | |
506 | ||
6ac40ed0 LT |
507 | /* |
508 | * This reads the current MSB of the PIT counter, and | |
509 | * checks if we are running on sufficiently fast and | |
510 | * non-virtualized hardware. | |
511 | * | |
512 | * Our expectations are: | |
513 | * | |
514 | * - the PIT is running at roughly 1.19MHz | |
515 | * | |
516 | * - each IO is going to take about 1us on real hardware, | |
517 | * but we allow it to be much faster (by a factor of 10) or | |
518 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
519 | * update - anything else implies a unacceptably slow CPU | |
520 | * or PIT for the fast calibration to work. | |
521 | * | |
522 | * - with 256 PIT ticks to read the value, we have 214us to | |
523 | * see the same MSB (and overhead like doing a single TSC | |
524 | * read per MSB value etc). | |
525 | * | |
526 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
527 | * them each to take about a microsecond on real hardware. | |
528 | * So we expect a count value of around 100. But we'll be | |
529 | * generous, and accept anything over 50. | |
530 | * | |
531 | * - if the PIT is stuck, and we see *many* more reads, we | |
532 | * return early (and the next caller of pit_expect_msb() | |
533 | * then consider it a failure when they don't see the | |
534 | * next expected value). | |
535 | * | |
536 | * These expectations mean that we know that we have seen the | |
537 | * transition from one expected value to another with a fairly | |
538 | * high accuracy, and we didn't miss any events. We can thus | |
539 | * use the TSC value at the transitions to calculate a pretty | |
540 | * good value for the TSC frequencty. | |
541 | */ | |
b6e61eef LT |
542 | static inline int pit_verify_msb(unsigned char val) |
543 | { | |
544 | /* Ignore LSB */ | |
545 | inb(0x42); | |
546 | return inb(0x42) == val; | |
547 | } | |
548 | ||
9e8912e0 | 549 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 550 | { |
9e8912e0 | 551 | int count; |
68f30fbe | 552 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 553 | |
6ac40ed0 | 554 | for (count = 0; count < 50000; count++) { |
b6e61eef | 555 | if (!pit_verify_msb(val)) |
6ac40ed0 | 556 | break; |
68f30fbe | 557 | prev_tsc = tsc; |
9e8912e0 | 558 | tsc = get_cycles(); |
6ac40ed0 | 559 | } |
68f30fbe | 560 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
561 | *tscp = tsc; |
562 | ||
563 | /* | |
564 | * We require _some_ success, but the quality control | |
565 | * will be based on the error terms on the TSC values. | |
566 | */ | |
567 | return count > 5; | |
6ac40ed0 LT |
568 | } |
569 | ||
570 | /* | |
9e8912e0 LT |
571 | * How many MSB values do we want to see? We aim for |
572 | * a maximum error rate of 500ppm (in practice the | |
573 | * real error is much smaller), but refuse to spend | |
68f30fbe | 574 | * more than 50ms on it. |
6ac40ed0 | 575 | */ |
68f30fbe | 576 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 577 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 578 | |
6ac40ed0 LT |
579 | static unsigned long quick_pit_calibrate(void) |
580 | { | |
9e8912e0 LT |
581 | int i; |
582 | u64 tsc, delta; | |
583 | unsigned long d1, d2; | |
584 | ||
6ac40ed0 | 585 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
586 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
587 | ||
6ac40ed0 LT |
588 | /* |
589 | * Counter 2, mode 0 (one-shot), binary count | |
590 | * | |
591 | * NOTE! Mode 2 decrements by two (and then the | |
592 | * output is flipped each time, giving the same | |
593 | * final output frequency as a decrement-by-one), | |
594 | * so mode 0 is much better when looking at the | |
595 | * individual counts. | |
596 | */ | |
bfc0f594 | 597 | outb(0xb0, 0x43); |
bfc0f594 | 598 | |
6ac40ed0 LT |
599 | /* Start at 0xffff */ |
600 | outb(0xff, 0x42); | |
601 | outb(0xff, 0x42); | |
602 | ||
a6a80e1d LT |
603 | /* |
604 | * The PIT starts counting at the next edge, so we | |
605 | * need to delay for a microsecond. The easiest way | |
606 | * to do that is to just read back the 16-bit counter | |
607 | * once from the PIT. | |
608 | */ | |
b6e61eef | 609 | pit_verify_msb(0); |
a6a80e1d | 610 | |
9e8912e0 LT |
611 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
612 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
613 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
614 | break; | |
615 | ||
5aac644a AH |
616 | delta -= tsc; |
617 | ||
618 | /* | |
619 | * Extrapolate the error and fail fast if the error will | |
620 | * never be below 500 ppm. | |
621 | */ | |
622 | if (i == 1 && | |
623 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
624 | return 0; | |
625 | ||
9e8912e0 LT |
626 | /* |
627 | * Iterate until the error is less than 500 ppm | |
628 | */ | |
b6e61eef LT |
629 | if (d1+d2 >= delta >> 11) |
630 | continue; | |
631 | ||
632 | /* | |
633 | * Check the PIT one more time to verify that | |
634 | * all TSC reads were stable wrt the PIT. | |
635 | * | |
636 | * This also guarantees serialization of the | |
637 | * last cycle read ('d2') in pit_expect_msb. | |
638 | */ | |
639 | if (!pit_verify_msb(0xfe - i)) | |
640 | break; | |
641 | goto success; | |
6ac40ed0 | 642 | } |
6ac40ed0 | 643 | } |
52045217 | 644 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 645 | return 0; |
9e8912e0 LT |
646 | |
647 | success: | |
648 | /* | |
649 | * Ok, if we get here, then we've seen the | |
650 | * MSB of the PIT decrement 'i' times, and the | |
651 | * error has shrunk to less than 500 ppm. | |
652 | * | |
653 | * As a result, we can depend on there not being | |
654 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 655 | * reliable (within the error). |
9e8912e0 LT |
656 | * |
657 | * kHz = ticks / time-in-seconds / 1000; | |
658 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
659 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
660 | */ | |
9e8912e0 LT |
661 | delta *= PIT_TICK_RATE; |
662 | do_div(delta, i*256*1000); | |
c767a54b | 663 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 664 | return delta; |
6ac40ed0 | 665 | } |
ec0c15af | 666 | |
bfc0f594 | 667 | /** |
e93ef949 | 668 | * native_calibrate_tsc - calibrate the tsc on boot |
bfc0f594 | 669 | */ |
e93ef949 | 670 | unsigned long native_calibrate_tsc(void) |
bfc0f594 | 671 | { |
827014be | 672 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 673 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 674 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 675 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 676 | |
7da7c156 BG |
677 | /* Calibrate TSC using MSR for Intel Atom SoCs */ |
678 | local_irq_save(flags); | |
5f0e0309 | 679 | fast_calibrate = try_msr_calibrate_tsc(); |
7da7c156 | 680 | local_irq_restore(flags); |
5f0e0309 | 681 | if (fast_calibrate) |
7da7c156 | 682 | return fast_calibrate; |
7da7c156 | 683 | |
6ac40ed0 LT |
684 | local_irq_save(flags); |
685 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 686 | local_irq_restore(flags); |
6ac40ed0 LT |
687 | if (fast_calibrate) |
688 | return fast_calibrate; | |
bfc0f594 | 689 | |
fbb16e24 TG |
690 | /* |
691 | * Run 5 calibration loops to get the lowest frequency value | |
692 | * (the best estimate). We use two different calibration modes | |
693 | * here: | |
694 | * | |
695 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
696 | * load a timeout of 50ms. We read the time right after we | |
697 | * started the timer and wait until the PIT count down reaches | |
698 | * zero. In each wait loop iteration we read the TSC and check | |
699 | * the delta to the previous read. We keep track of the min | |
700 | * and max values of that delta. The delta is mostly defined | |
701 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 702 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
703 | * maximum time is significantly larger than the minimum time, |
704 | * then we discard the result and have another try. | |
705 | * | |
706 | * 2) Reference counter. If available we use the HPET or the | |
707 | * PMTIMER as a reference to check the sanity of that value. | |
708 | * We use separate TSC readouts and check inside of the | |
709 | * reference read for a SMI/SMM disturbance. We dicard | |
710 | * disturbed values here as well. We do that around the PIT | |
711 | * calibration delay loop as we have to wait for a certain | |
712 | * amount of time anyway. | |
713 | */ | |
a977c400 TG |
714 | |
715 | /* Preset PIT loop values */ | |
716 | latch = CAL_LATCH; | |
717 | ms = CAL_MS; | |
718 | loopmin = CAL_PIT_LOOPS; | |
719 | ||
720 | for (i = 0; i < 3; i++) { | |
ec0c15af | 721 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
722 | |
723 | /* | |
724 | * Read the start value and the reference count of | |
ec0c15af LT |
725 | * hpet/pmtimer when available. Then do the PIT |
726 | * calibration, which will take at least 50ms, and | |
727 | * read the end value. | |
fbb16e24 | 728 | */ |
ec0c15af | 729 | local_irq_save(flags); |
827014be | 730 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 731 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 732 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
733 | local_irq_restore(flags); |
734 | ||
ec0c15af LT |
735 | /* Pick the lowest PIT TSC calibration so far */ |
736 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
737 | |
738 | /* hpet or pmtimer available ? */ | |
62627bec | 739 | if (ref1 == ref2) |
fbb16e24 TG |
740 | continue; |
741 | ||
742 | /* Check, whether the sampling was disturbed by an SMI */ | |
743 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
744 | continue; | |
745 | ||
746 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 747 | if (hpet) |
827014be | 748 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 749 | else |
827014be | 750 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 751 | |
fbb16e24 | 752 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
753 | |
754 | /* Check the reference deviation */ | |
755 | delta = ((u64) tsc_pit_min) * 100; | |
756 | do_div(delta, tsc_ref_min); | |
757 | ||
758 | /* | |
759 | * If both calibration results are inside a 10% window | |
760 | * then we can be sure, that the calibration | |
761 | * succeeded. We break out of the loop right away. We | |
762 | * use the reference value, as it is more precise. | |
763 | */ | |
764 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
765 | pr_info("PIT calibration matches %s. %d loops\n", |
766 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 767 | return tsc_ref_min; |
fbb16e24 TG |
768 | } |
769 | ||
a977c400 TG |
770 | /* |
771 | * Check whether PIT failed more than once. This | |
772 | * happens in virtualized environments. We need to | |
773 | * give the virtual PC a slightly longer timeframe for | |
774 | * the HPET/PMTIMER to make the result precise. | |
775 | */ | |
776 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
777 | latch = CAL2_LATCH; | |
778 | ms = CAL2_MS; | |
779 | loopmin = CAL2_PIT_LOOPS; | |
780 | } | |
fbb16e24 | 781 | } |
bfc0f594 AK |
782 | |
783 | /* | |
fbb16e24 | 784 | * Now check the results. |
bfc0f594 | 785 | */ |
fbb16e24 TG |
786 | if (tsc_pit_min == ULONG_MAX) { |
787 | /* PIT gave no useful value */ | |
c767a54b | 788 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
789 | |
790 | /* We don't have an alternative source, disable TSC */ | |
827014be | 791 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 792 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
793 | return 0; |
794 | } | |
795 | ||
796 | /* The alternative source failed as well, disable TSC */ | |
797 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 798 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
799 | return 0; |
800 | } | |
801 | ||
802 | /* Use the alternative source */ | |
c767a54b JP |
803 | pr_info("using %s reference calibration\n", |
804 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
805 | |
806 | return tsc_ref_min; | |
807 | } | |
bfc0f594 | 808 | |
fbb16e24 | 809 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 810 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 811 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 812 | return tsc_pit_min; |
bfc0f594 AK |
813 | } |
814 | ||
fbb16e24 TG |
815 | /* The alternative source failed, use the PIT calibration value */ |
816 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 817 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 818 | return tsc_pit_min; |
bfc0f594 AK |
819 | } |
820 | ||
fbb16e24 TG |
821 | /* |
822 | * The calibration values differ too much. In doubt, we use | |
823 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 824 | * running at double speed. At least we let the user know: |
fbb16e24 | 825 | */ |
c767a54b JP |
826 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
827 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
828 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 829 | return tsc_pit_min; |
bfc0f594 AK |
830 | } |
831 | ||
bfc0f594 AK |
832 | int recalibrate_cpu_khz(void) |
833 | { | |
834 | #ifndef CONFIG_SMP | |
835 | unsigned long cpu_khz_old = cpu_khz; | |
836 | ||
837 | if (cpu_has_tsc) { | |
2d826404 | 838 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 839 | cpu_khz = tsc_khz; |
bfc0f594 AK |
840 | cpu_data(0).loops_per_jiffy = |
841 | cpufreq_scale(cpu_data(0).loops_per_jiffy, | |
842 | cpu_khz_old, cpu_khz); | |
843 | return 0; | |
844 | } else | |
845 | return -ENODEV; | |
846 | #else | |
847 | return -ENODEV; | |
848 | #endif | |
849 | } | |
850 | ||
851 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
852 | ||
2dbe06fa | 853 | |
cd7240c0 SS |
854 | static unsigned long long cyc2ns_suspend; |
855 | ||
b74f05d6 | 856 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 857 | { |
35af99e6 | 858 | if (!sched_clock_stable()) |
cd7240c0 SS |
859 | return; |
860 | ||
861 | cyc2ns_suspend = sched_clock(); | |
862 | } | |
863 | ||
864 | /* | |
865 | * Even on processors with invariant TSC, TSC gets reset in some the | |
866 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
867 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
868 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
869 | * that sched_clock() continues from the point where it was left off during | |
870 | * suspend. | |
871 | */ | |
b74f05d6 | 872 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
873 | { |
874 | unsigned long long offset; | |
875 | unsigned long flags; | |
876 | int cpu; | |
877 | ||
35af99e6 | 878 | if (!sched_clock_stable()) |
cd7240c0 SS |
879 | return; |
880 | ||
881 | local_irq_save(flags); | |
882 | ||
20d1c86a | 883 | /* |
6a6256f9 | 884 | * We're coming out of suspend, there's no concurrency yet; don't |
20d1c86a PZ |
885 | * bother being nice about the RCU stuff, just write to both |
886 | * data fields. | |
887 | */ | |
888 | ||
889 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
890 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
891 | ||
cd7240c0 SS |
892 | offset = cyc2ns_suspend - sched_clock(); |
893 | ||
20d1c86a PZ |
894 | for_each_possible_cpu(cpu) { |
895 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
896 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
897 | } | |
cd7240c0 SS |
898 | |
899 | local_irq_restore(flags); | |
900 | } | |
901 | ||
2dbe06fa AK |
902 | #ifdef CONFIG_CPU_FREQ |
903 | ||
904 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
905 | * changes. | |
906 | * | |
907 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
908 | * not that important because current Opteron setups do not support | |
909 | * scaling on SMP anyroads. | |
910 | * | |
911 | * Should fix up last_tsc too. Currently gettimeofday in the | |
912 | * first tick after the change will be slightly wrong. | |
913 | */ | |
914 | ||
915 | static unsigned int ref_freq; | |
916 | static unsigned long loops_per_jiffy_ref; | |
917 | static unsigned long tsc_khz_ref; | |
918 | ||
919 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
920 | void *data) | |
921 | { | |
922 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 923 | unsigned long *lpj; |
2dbe06fa AK |
924 | |
925 | if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) | |
926 | return 0; | |
927 | ||
931db6a3 | 928 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 929 | #ifdef CONFIG_SMP |
931db6a3 | 930 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 931 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
932 | #endif |
933 | ||
934 | if (!ref_freq) { | |
935 | ref_freq = freq->old; | |
936 | loops_per_jiffy_ref = *lpj; | |
937 | tsc_khz_ref = tsc_khz; | |
938 | } | |
939 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 940 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 941 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
942 | |
943 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
944 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
945 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 946 | |
3896c329 PZ |
947 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
948 | } | |
2dbe06fa AK |
949 | |
950 | return 0; | |
951 | } | |
952 | ||
953 | static struct notifier_block time_cpufreq_notifier_block = { | |
954 | .notifier_call = time_cpufreq_notifier | |
955 | }; | |
956 | ||
957 | static int __init cpufreq_tsc(void) | |
958 | { | |
060700b5 LT |
959 | if (!cpu_has_tsc) |
960 | return 0; | |
961 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
962 | return 0; | |
2dbe06fa AK |
963 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
964 | CPUFREQ_TRANSITION_NOTIFIER); | |
965 | return 0; | |
966 | } | |
967 | ||
968 | core_initcall(cpufreq_tsc); | |
969 | ||
970 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 | 971 | |
f9677e0f CH |
972 | #define ART_CPUID_LEAF (0x15) |
973 | #define ART_MIN_DENOMINATOR (1) | |
974 | ||
975 | ||
976 | /* | |
977 | * If ART is present detect the numerator:denominator to convert to TSC | |
978 | */ | |
979 | static void detect_art(void) | |
980 | { | |
981 | unsigned int unused[2]; | |
982 | ||
983 | if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) | |
984 | return; | |
985 | ||
986 | cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, | |
987 | &art_to_tsc_numerator, unused, unused+1); | |
988 | ||
989 | /* Don't enable ART in a VM, non-stop TSC required */ | |
990 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || | |
991 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || | |
992 | art_to_tsc_denominator < ART_MIN_DENOMINATOR) | |
993 | return; | |
994 | ||
995 | if (rdmsrl_safe(MSR_IA32_TSC_ADJUST, &art_to_tsc_offset)) | |
996 | return; | |
997 | ||
998 | /* Make this sticky over multiple CPU init calls */ | |
999 | setup_force_cpu_cap(X86_FEATURE_ART); | |
1000 | } | |
1001 | ||
1002 | ||
8fbbc4b4 AK |
1003 | /* clocksource code */ |
1004 | ||
1005 | static struct clocksource clocksource_tsc; | |
1006 | ||
1007 | /* | |
09ec5442 | 1008 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
1009 | * structure to avoid a nasty time-warp. This can be observed in a |
1010 | * very small window right after one CPU updated cycle_last under | |
1011 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
1012 | * is smaller than the cycle_last reference value due to a TSC which | |
1013 | * is slighty behind. This delta is nowhere else observable, but in | |
1014 | * that case it results in a forward time jump in the range of hours | |
1015 | * due to the unsigned delta calculation of the time keeping core | |
1016 | * code, which is necessary to support wrapping clocksources like pm | |
1017 | * timer. | |
09ec5442 TG |
1018 | * |
1019 | * This sanity check is now done in the core timekeeping code. | |
1020 | * checking the result of read_tsc() - cycle_last for being negative. | |
1021 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 1022 | */ |
8e19608e | 1023 | static cycle_t read_tsc(struct clocksource *cs) |
8fbbc4b4 | 1024 | { |
27c63405 | 1025 | return (cycle_t)rdtsc_ordered(); |
1be39679 MS |
1026 | } |
1027 | ||
09ec5442 TG |
1028 | /* |
1029 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
1030 | */ | |
8fbbc4b4 AK |
1031 | static struct clocksource clocksource_tsc = { |
1032 | .name = "tsc", | |
1033 | .rating = 300, | |
1034 | .read = read_tsc, | |
1035 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 AK |
1036 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
1037 | CLOCK_SOURCE_MUST_VERIFY, | |
98d0ac38 | 1038 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
8fbbc4b4 AK |
1039 | }; |
1040 | ||
1041 | void mark_tsc_unstable(char *reason) | |
1042 | { | |
1043 | if (!tsc_unstable) { | |
1044 | tsc_unstable = 1; | |
35af99e6 | 1045 | clear_sched_clock_stable(); |
e82b8e4e | 1046 | disable_sched_clock_irqtime(); |
c767a54b | 1047 | pr_info("Marking TSC unstable due to %s\n", reason); |
8fbbc4b4 AK |
1048 | /* Change only the rating, when not registered */ |
1049 | if (clocksource_tsc.mult) | |
7285dd7f TG |
1050 | clocksource_mark_unstable(&clocksource_tsc); |
1051 | else { | |
1052 | clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; | |
8fbbc4b4 | 1053 | clocksource_tsc.rating = 0; |
7285dd7f | 1054 | } |
8fbbc4b4 AK |
1055 | } |
1056 | } | |
1057 | ||
1058 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1059 | ||
395628ef AK |
1060 | static void __init check_system_tsc_reliable(void) |
1061 | { | |
03da3ff1 DW |
1062 | #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) |
1063 | if (is_geode_lx()) { | |
1064 | /* RTSC counts during suspend */ | |
8fbbc4b4 | 1065 | #define RTSC_SUSP 0x100 |
03da3ff1 | 1066 | unsigned long res_low, res_high; |
8fbbc4b4 | 1067 | |
03da3ff1 DW |
1068 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); |
1069 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ | |
1070 | if (res_low & RTSC_SUSP) | |
1071 | tsc_clocksource_reliable = 1; | |
1072 | } | |
8fbbc4b4 | 1073 | #endif |
395628ef AK |
1074 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1075 | tsc_clocksource_reliable = 1; | |
1076 | } | |
8fbbc4b4 AK |
1077 | |
1078 | /* | |
1079 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1080 | * over all CPUs. | |
1081 | */ | |
148f9bb8 | 1082 | int unsynchronized_tsc(void) |
8fbbc4b4 AK |
1083 | { |
1084 | if (!cpu_has_tsc || tsc_unstable) | |
1085 | return 1; | |
1086 | ||
3e5095d1 | 1087 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1088 | if (apic_is_clustered_box()) |
1089 | return 1; | |
1090 | #endif | |
1091 | ||
1092 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1093 | return 0; | |
d3b8f889 | 1094 | |
1095 | if (tsc_clocksource_reliable) | |
1096 | return 0; | |
8fbbc4b4 AK |
1097 | /* |
1098 | * Intel systems are normally all synchronized. | |
1099 | * Exceptions must mark TSC as unstable: | |
1100 | */ | |
1101 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1102 | /* assume multi socket systems are not synchronized: */ | |
1103 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1104 | return 1; |
8fbbc4b4 AK |
1105 | } |
1106 | ||
d3b8f889 | 1107 | return 0; |
8fbbc4b4 AK |
1108 | } |
1109 | ||
f9677e0f CH |
1110 | /* |
1111 | * Convert ART to TSC given numerator/denominator found in detect_art() | |
1112 | */ | |
1113 | struct system_counterval_t convert_art_to_tsc(cycle_t art) | |
1114 | { | |
1115 | u64 tmp, res, rem; | |
1116 | ||
1117 | rem = do_div(art, art_to_tsc_denominator); | |
1118 | ||
1119 | res = art * art_to_tsc_numerator; | |
1120 | tmp = rem * art_to_tsc_numerator; | |
1121 | ||
1122 | do_div(tmp, art_to_tsc_denominator); | |
1123 | res += tmp + art_to_tsc_offset; | |
1124 | ||
1125 | return (struct system_counterval_t) {.cs = art_related_clocksource, | |
1126 | .cycles = res}; | |
1127 | } | |
1128 | EXPORT_SYMBOL(convert_art_to_tsc); | |
08ec0c58 JS |
1129 | |
1130 | static void tsc_refine_calibration_work(struct work_struct *work); | |
1131 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1132 | /** | |
1133 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1134 | * @work - ignored. | |
1135 | * | |
1136 | * This functions uses delayed work over a period of a | |
1137 | * second to further refine the TSC freq value. Since this is | |
1138 | * timer based, instead of loop based, we don't block the boot | |
1139 | * process while this longer calibration is done. | |
1140 | * | |
0d2eb44f | 1141 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1142 | * or the refined calibration is off by 1% of the fast early |
1143 | * calibration, we throw out the new calibration and use the | |
1144 | * early calibration. | |
1145 | */ | |
1146 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1147 | { | |
1148 | static u64 tsc_start = -1, ref_start; | |
1149 | static int hpet; | |
1150 | u64 tsc_stop, ref_stop, delta; | |
1151 | unsigned long freq; | |
1152 | ||
1153 | /* Don't bother refining TSC on unstable systems */ | |
1154 | if (check_tsc_unstable()) | |
1155 | goto out; | |
1156 | ||
1157 | /* | |
1158 | * Since the work is started early in boot, we may be | |
1159 | * delayed the first time we expire. So set the workqueue | |
1160 | * again once we know timers are working. | |
1161 | */ | |
1162 | if (tsc_start == -1) { | |
1163 | /* | |
1164 | * Only set hpet once, to avoid mixing hardware | |
1165 | * if the hpet becomes enabled later. | |
1166 | */ | |
1167 | hpet = is_hpet_enabled(); | |
1168 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1169 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1170 | return; | |
1171 | } | |
1172 | ||
1173 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1174 | ||
1175 | /* hpet or pmtimer available ? */ | |
62627bec | 1176 | if (ref_start == ref_stop) |
08ec0c58 JS |
1177 | goto out; |
1178 | ||
1179 | /* Check, whether the sampling was disturbed by an SMI */ | |
1180 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1181 | goto out; | |
1182 | ||
1183 | delta = tsc_stop - tsc_start; | |
1184 | delta *= 1000000LL; | |
1185 | if (hpet) | |
1186 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1187 | else | |
1188 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1189 | ||
1190 | /* Make sure we're within 1% */ | |
1191 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1192 | goto out; | |
1193 | ||
1194 | tsc_khz = freq; | |
c767a54b JP |
1195 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1196 | (unsigned long)tsc_khz / 1000, | |
1197 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 JS |
1198 | |
1199 | out: | |
f9677e0f CH |
1200 | if (boot_cpu_has(X86_FEATURE_ART)) |
1201 | art_related_clocksource = &clocksource_tsc; | |
08ec0c58 JS |
1202 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
1203 | } | |
1204 | ||
1205 | ||
1206 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1207 | { |
29fe359c | 1208 | if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
1209 | return 0; |
1210 | ||
395628ef AK |
1211 | if (tsc_clocksource_reliable) |
1212 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
1213 | /* lower the rating if we already know its unstable: */ |
1214 | if (check_tsc_unstable()) { | |
1215 | clocksource_tsc.rating = 0; | |
1216 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
1217 | } | |
57779dc2 | 1218 | |
82f9c080 FT |
1219 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1220 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1221 | ||
57779dc2 AK |
1222 | /* |
1223 | * Trust the results of the earlier calibration on systems | |
1224 | * exporting a reliable TSC. | |
1225 | */ | |
1226 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) { | |
1227 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | |
1228 | return 0; | |
1229 | } | |
1230 | ||
08ec0c58 JS |
1231 | schedule_delayed_work(&tsc_irqwork, 0); |
1232 | return 0; | |
8fbbc4b4 | 1233 | } |
08ec0c58 JS |
1234 | /* |
1235 | * We use device_initcall here, to ensure we run after the hpet | |
1236 | * is fully initialized, which may occur at fs_initcall time. | |
1237 | */ | |
1238 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 AK |
1239 | |
1240 | void __init tsc_init(void) | |
1241 | { | |
1242 | u64 lpj; | |
1243 | int cpu; | |
1244 | ||
b47dcbdc AL |
1245 | if (!cpu_has_tsc) { |
1246 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
8fbbc4b4 | 1247 | return; |
b47dcbdc | 1248 | } |
8fbbc4b4 | 1249 | |
2d826404 | 1250 | tsc_khz = x86_platform.calibrate_tsc(); |
e93ef949 | 1251 | cpu_khz = tsc_khz; |
8fbbc4b4 | 1252 | |
e93ef949 | 1253 | if (!tsc_khz) { |
8fbbc4b4 | 1254 | mark_tsc_unstable("could not calculate TSC khz"); |
b47dcbdc | 1255 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 AK |
1256 | return; |
1257 | } | |
1258 | ||
c767a54b JP |
1259 | pr_info("Detected %lu.%03lu MHz processor\n", |
1260 | (unsigned long)cpu_khz / 1000, | |
1261 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 AK |
1262 | |
1263 | /* | |
1264 | * Secondary CPUs do not run through tsc_init(), so set up | |
1265 | * all the scale factors for all CPUs, assuming the same | |
1266 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1267 | * up if their speed diverges) | |
1268 | */ | |
20d1c86a PZ |
1269 | for_each_possible_cpu(cpu) { |
1270 | cyc2ns_init(cpu); | |
8fbbc4b4 | 1271 | set_cyc2ns_scale(cpu_khz, cpu); |
20d1c86a | 1272 | } |
8fbbc4b4 AK |
1273 | |
1274 | if (tsc_disabled > 0) | |
1275 | return; | |
1276 | ||
1277 | /* now allow native_sched_clock() to use rdtsc */ | |
10b033d4 | 1278 | |
8fbbc4b4 | 1279 | tsc_disabled = 0; |
3bbfafb7 | 1280 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1281 | |
e82b8e4e VP |
1282 | if (!no_sched_irq_time) |
1283 | enable_sched_clock_irqtime(); | |
1284 | ||
70de9a97 AK |
1285 | lpj = ((u64)tsc_khz * 1000); |
1286 | do_div(lpj, HZ); | |
1287 | lpj_fine = lpj; | |
1288 | ||
8fbbc4b4 | 1289 | use_tsc_delay(); |
8fbbc4b4 AK |
1290 | |
1291 | if (unsynchronized_tsc()) | |
1292 | mark_tsc_unstable("TSCs unsynchronized"); | |
1293 | ||
395628ef | 1294 | check_system_tsc_reliable(); |
f9677e0f CH |
1295 | |
1296 | detect_art(); | |
8fbbc4b4 AK |
1297 | } |
1298 | ||
b565201c JS |
1299 | #ifdef CONFIG_SMP |
1300 | /* | |
1301 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1302 | * we can skip clock calibration if another cpu in the same socket has already | |
1303 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1304 | * cpus in the socket - this should be a safe assumption. | |
1305 | */ | |
148f9bb8 | 1306 | unsigned long calibrate_delay_is_known(void) |
b565201c | 1307 | { |
c25323c0 | 1308 | int sibling, cpu = smp_processor_id(); |
f508a5ba | 1309 | struct cpumask *mask = topology_core_cpumask(cpu); |
b565201c JS |
1310 | |
1311 | if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC)) | |
1312 | return 0; | |
1313 | ||
f508a5ba TG |
1314 | if (!mask) |
1315 | return 0; | |
1316 | ||
1317 | sibling = cpumask_any_but(mask, cpu); | |
c25323c0 TG |
1318 | if (sibling < nr_cpu_ids) |
1319 | return cpu_data(sibling).loops_per_jiffy; | |
b565201c JS |
1320 | return 0; |
1321 | } | |
1322 | #endif |