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Commit | Line | Data |
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c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
bfc0f594 | 3 | #include <linux/kernel.h> |
0ef95533 | 4 | #include <linux/sched.h> |
e6017571 | 5 | #include <linux/sched/clock.h> |
0ef95533 | 6 | #include <linux/init.h> |
186f4360 | 7 | #include <linux/export.h> |
0ef95533 | 8 | #include <linux/timer.h> |
bfc0f594 | 9 | #include <linux/acpi_pmtmr.h> |
2dbe06fa | 10 | #include <linux/cpufreq.h> |
8fbbc4b4 AK |
11 | #include <linux/delay.h> |
12 | #include <linux/clocksource.h> | |
13 | #include <linux/percpu.h> | |
08604bd9 | 14 | #include <linux/timex.h> |
10b033d4 | 15 | #include <linux/static_key.h> |
bfc0f594 AK |
16 | |
17 | #include <asm/hpet.h> | |
8fbbc4b4 AK |
18 | #include <asm/timer.h> |
19 | #include <asm/vgtod.h> | |
20 | #include <asm/time.h> | |
21 | #include <asm/delay.h> | |
88b094fb | 22 | #include <asm/hypervisor.h> |
08047c4f | 23 | #include <asm/nmi.h> |
2d826404 | 24 | #include <asm/x86_init.h> |
03da3ff1 | 25 | #include <asm/geode.h> |
6731b0d6 | 26 | #include <asm/apic.h> |
655e52d2 | 27 | #include <asm/intel-family.h> |
0ef95533 | 28 | |
f24ade3a | 29 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
0ef95533 | 30 | EXPORT_SYMBOL(cpu_khz); |
f24ade3a IM |
31 | |
32 | unsigned int __read_mostly tsc_khz; | |
0ef95533 AK |
33 | EXPORT_SYMBOL(tsc_khz); |
34 | ||
35 | /* | |
36 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | |
37 | */ | |
f24ade3a | 38 | static int __read_mostly tsc_unstable; |
0ef95533 AK |
39 | |
40 | /* native_sched_clock() is called before tsc_init(), so | |
41 | we must start with the TSC soft disabled to prevent | |
59e21e3d | 42 | erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */ |
f24ade3a | 43 | static int __read_mostly tsc_disabled = -1; |
0ef95533 | 44 | |
3bbfafb7 | 45 | static DEFINE_STATIC_KEY_FALSE(__use_tsc); |
10b033d4 | 46 | |
28a00184 | 47 | int tsc_clocksource_reliable; |
57c67da2 | 48 | |
f9677e0f CH |
49 | static u32 art_to_tsc_numerator; |
50 | static u32 art_to_tsc_denominator; | |
51 | static u64 art_to_tsc_offset; | |
52 | struct clocksource *art_related_clocksource; | |
53 | ||
20d1c86a | 54 | struct cyc2ns { |
59eaef78 PZ |
55 | struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ |
56 | seqcount_t seq; /* 32 + 4 = 36 */ | |
20d1c86a | 57 | |
59eaef78 | 58 | }; /* fits one cacheline */ |
20d1c86a | 59 | |
59eaef78 | 60 | static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); |
20d1c86a | 61 | |
59eaef78 | 62 | void cyc2ns_read_begin(struct cyc2ns_data *data) |
20d1c86a | 63 | { |
59eaef78 | 64 | int seq, idx; |
20d1c86a | 65 | |
59eaef78 | 66 | preempt_disable_notrace(); |
20d1c86a | 67 | |
59eaef78 PZ |
68 | do { |
69 | seq = this_cpu_read(cyc2ns.seq.sequence); | |
70 | idx = seq & 1; | |
20d1c86a | 71 | |
59eaef78 PZ |
72 | data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); |
73 | data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); | |
74 | data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); | |
20d1c86a | 75 | |
59eaef78 | 76 | } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); |
20d1c86a PZ |
77 | } |
78 | ||
59eaef78 | 79 | void cyc2ns_read_end(void) |
20d1c86a | 80 | { |
59eaef78 | 81 | preempt_enable_notrace(); |
20d1c86a PZ |
82 | } |
83 | ||
84 | /* | |
85 | * Accelerators for sched_clock() | |
57c67da2 PZ |
86 | * convert from cycles(64bits) => nanoseconds (64bits) |
87 | * basic equation: | |
88 | * ns = cycles / (freq / ns_per_sec) | |
89 | * ns = cycles * (ns_per_sec / freq) | |
90 | * ns = cycles * (10^9 / (cpu_khz * 10^3)) | |
91 | * ns = cycles * (10^6 / cpu_khz) | |
92 | * | |
93 | * Then we use scaling math (suggested by george@mvista.com) to get: | |
94 | * ns = cycles * (10^6 * SC / cpu_khz) / SC | |
95 | * ns = cycles * cyc2ns_scale / SC | |
96 | * | |
97 | * And since SC is a constant power of two, we can convert the div | |
b20112ed AH |
98 | * into a shift. The larger SC is, the more accurate the conversion, but |
99 | * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication | |
100 | * (64-bit result) can be used. | |
57c67da2 | 101 | * |
b20112ed | 102 | * We can use khz divisor instead of mhz to keep a better precision. |
57c67da2 PZ |
103 | * (mathieu.desnoyers@polymtl.ca) |
104 | * | |
105 | * -johnstul@us.ibm.com "math is hard, lets go shopping!" | |
106 | */ | |
107 | ||
20d1c86a PZ |
108 | static void cyc2ns_data_init(struct cyc2ns_data *data) |
109 | { | |
5e3c1afd | 110 | data->cyc2ns_mul = 0; |
b20112ed | 111 | data->cyc2ns_shift = 0; |
20d1c86a | 112 | data->cyc2ns_offset = 0; |
20d1c86a PZ |
113 | } |
114 | ||
115 | static void cyc2ns_init(int cpu) | |
116 | { | |
117 | struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu); | |
118 | ||
119 | cyc2ns_data_init(&c2n->data[0]); | |
120 | cyc2ns_data_init(&c2n->data[1]); | |
121 | ||
59eaef78 | 122 | seqcount_init(&c2n->seq); |
20d1c86a PZ |
123 | } |
124 | ||
57c67da2 PZ |
125 | static inline unsigned long long cycles_2_ns(unsigned long long cyc) |
126 | { | |
59eaef78 | 127 | struct cyc2ns_data data; |
20d1c86a PZ |
128 | unsigned long long ns; |
129 | ||
59eaef78 | 130 | cyc2ns_read_begin(&data); |
20d1c86a | 131 | |
59eaef78 PZ |
132 | ns = data.cyc2ns_offset; |
133 | ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); | |
20d1c86a | 134 | |
59eaef78 | 135 | cyc2ns_read_end(); |
20d1c86a | 136 | |
57c67da2 PZ |
137 | return ns; |
138 | } | |
139 | ||
615cd033 | 140 | static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) |
57c67da2 | 141 | { |
615cd033 | 142 | unsigned long long ns_now; |
59eaef78 PZ |
143 | struct cyc2ns_data data; |
144 | struct cyc2ns *c2n; | |
20d1c86a | 145 | unsigned long flags; |
57c67da2 PZ |
146 | |
147 | local_irq_save(flags); | |
148 | sched_clock_idle_sleep_event(); | |
149 | ||
aa297292 | 150 | if (!khz) |
20d1c86a PZ |
151 | goto done; |
152 | ||
57c67da2 PZ |
153 | ns_now = cycles_2_ns(tsc_now); |
154 | ||
20d1c86a PZ |
155 | /* |
156 | * Compute a new multiplier as per the above comment and ensure our | |
157 | * time function is continuous; see the comment near struct | |
158 | * cyc2ns_data. | |
159 | */ | |
59eaef78 | 160 | clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, |
b20112ed AH |
161 | NSEC_PER_MSEC, 0); |
162 | ||
b9511cd7 AH |
163 | /* |
164 | * cyc2ns_shift is exported via arch_perf_update_userpage() where it is | |
165 | * not expected to be greater than 31 due to the original published | |
166 | * conversion algorithm shifting a 32-bit value (now specifies a 64-bit | |
167 | * value) - refer perf_event_mmap_page documentation in perf_event.h. | |
168 | */ | |
59eaef78 PZ |
169 | if (data.cyc2ns_shift == 32) { |
170 | data.cyc2ns_shift = 31; | |
171 | data.cyc2ns_mul >>= 1; | |
b9511cd7 AH |
172 | } |
173 | ||
59eaef78 PZ |
174 | data.cyc2ns_offset = ns_now - |
175 | mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); | |
176 | ||
177 | c2n = per_cpu_ptr(&cyc2ns, cpu); | |
20d1c86a | 178 | |
59eaef78 PZ |
179 | raw_write_seqcount_latch(&c2n->seq); |
180 | c2n->data[0] = data; | |
181 | raw_write_seqcount_latch(&c2n->seq); | |
182 | c2n->data[1] = data; | |
57c67da2 | 183 | |
20d1c86a | 184 | done: |
57c67da2 PZ |
185 | sched_clock_idle_wakeup_event(0); |
186 | local_irq_restore(flags); | |
187 | } | |
615cd033 PZ |
188 | |
189 | static void set_cyc2ns_scale(unsigned long khz, int cpu) | |
190 | { | |
191 | __set_cyc2ns_scale(khz, cpu, rdtsc()); | |
192 | } | |
193 | ||
0ef95533 AK |
194 | /* |
195 | * Scheduler clock - returns current time in nanosec units. | |
196 | */ | |
197 | u64 native_sched_clock(void) | |
198 | { | |
3bbfafb7 PZ |
199 | if (static_branch_likely(&__use_tsc)) { |
200 | u64 tsc_now = rdtsc(); | |
201 | ||
202 | /* return the value in ns */ | |
203 | return cycles_2_ns(tsc_now); | |
204 | } | |
0ef95533 AK |
205 | |
206 | /* | |
207 | * Fall back to jiffies if there's no TSC available: | |
208 | * ( But note that we still use it if the TSC is marked | |
209 | * unstable. We do this because unlike Time Of Day, | |
210 | * the scheduler clock tolerates small errors and it's | |
211 | * very important for it to be as fast as the platform | |
3ad2f3fb | 212 | * can achieve it. ) |
0ef95533 | 213 | */ |
0ef95533 | 214 | |
3bbfafb7 PZ |
215 | /* No locking but a rare wrong value is not a big deal: */ |
216 | return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); | |
0ef95533 AK |
217 | } |
218 | ||
a94cab23 AK |
219 | /* |
220 | * Generate a sched_clock if you already have a TSC value. | |
221 | */ | |
222 | u64 native_sched_clock_from_tsc(u64 tsc) | |
223 | { | |
224 | return cycles_2_ns(tsc); | |
225 | } | |
226 | ||
0ef95533 AK |
227 | /* We need to define a real function for sched_clock, to override the |
228 | weak default version */ | |
229 | #ifdef CONFIG_PARAVIRT | |
230 | unsigned long long sched_clock(void) | |
231 | { | |
232 | return paravirt_sched_clock(); | |
233 | } | |
f94c8d11 | 234 | |
698eff63 | 235 | bool using_native_sched_clock(void) |
f94c8d11 PZ |
236 | { |
237 | return pv_time_ops.sched_clock == native_sched_clock; | |
238 | } | |
0ef95533 AK |
239 | #else |
240 | unsigned long long | |
241 | sched_clock(void) __attribute__((alias("native_sched_clock"))); | |
f94c8d11 | 242 | |
698eff63 | 243 | bool using_native_sched_clock(void) { return true; } |
0ef95533 AK |
244 | #endif |
245 | ||
246 | int check_tsc_unstable(void) | |
247 | { | |
248 | return tsc_unstable; | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(check_tsc_unstable); | |
251 | ||
252 | #ifdef CONFIG_X86_TSC | |
253 | int __init notsc_setup(char *str) | |
254 | { | |
c767a54b | 255 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
0ef95533 AK |
256 | tsc_disabled = 1; |
257 | return 1; | |
258 | } | |
259 | #else | |
260 | /* | |
261 | * disable flag for tsc. Takes effect by clearing the TSC cpu flag | |
262 | * in cpu/common.c | |
263 | */ | |
264 | int __init notsc_setup(char *str) | |
265 | { | |
266 | setup_clear_cpu_cap(X86_FEATURE_TSC); | |
267 | return 1; | |
268 | } | |
269 | #endif | |
270 | ||
271 | __setup("notsc", notsc_setup); | |
bfc0f594 | 272 | |
e82b8e4e VP |
273 | static int no_sched_irq_time; |
274 | ||
395628ef AK |
275 | static int __init tsc_setup(char *str) |
276 | { | |
277 | if (!strcmp(str, "reliable")) | |
278 | tsc_clocksource_reliable = 1; | |
e82b8e4e VP |
279 | if (!strncmp(str, "noirqtime", 9)) |
280 | no_sched_irq_time = 1; | |
8309f86c PZ |
281 | if (!strcmp(str, "unstable")) |
282 | mark_tsc_unstable("boot parameter"); | |
395628ef AK |
283 | return 1; |
284 | } | |
285 | ||
286 | __setup("tsc=", tsc_setup); | |
287 | ||
bfc0f594 AK |
288 | #define MAX_RETRIES 5 |
289 | #define SMI_TRESHOLD 50000 | |
290 | ||
291 | /* | |
292 | * Read TSC and the reference counters. Take care of SMI disturbance | |
293 | */ | |
827014be | 294 | static u64 tsc_read_refs(u64 *p, int hpet) |
bfc0f594 AK |
295 | { |
296 | u64 t1, t2; | |
297 | int i; | |
298 | ||
299 | for (i = 0; i < MAX_RETRIES; i++) { | |
300 | t1 = get_cycles(); | |
301 | if (hpet) | |
827014be | 302 | *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; |
bfc0f594 | 303 | else |
827014be | 304 | *p = acpi_pm_read_early(); |
bfc0f594 AK |
305 | t2 = get_cycles(); |
306 | if ((t2 - t1) < SMI_TRESHOLD) | |
307 | return t2; | |
308 | } | |
309 | return ULLONG_MAX; | |
310 | } | |
311 | ||
d683ef7a TG |
312 | /* |
313 | * Calculate the TSC frequency from HPET reference | |
bfc0f594 | 314 | */ |
d683ef7a | 315 | static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) |
bfc0f594 | 316 | { |
d683ef7a | 317 | u64 tmp; |
bfc0f594 | 318 | |
d683ef7a TG |
319 | if (hpet2 < hpet1) |
320 | hpet2 += 0x100000000ULL; | |
321 | hpet2 -= hpet1; | |
322 | tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); | |
323 | do_div(tmp, 1000000); | |
324 | do_div(deltatsc, tmp); | |
325 | ||
326 | return (unsigned long) deltatsc; | |
327 | } | |
328 | ||
329 | /* | |
330 | * Calculate the TSC frequency from PMTimer reference | |
331 | */ | |
332 | static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) | |
333 | { | |
334 | u64 tmp; | |
bfc0f594 | 335 | |
d683ef7a TG |
336 | if (!pm1 && !pm2) |
337 | return ULONG_MAX; | |
338 | ||
339 | if (pm2 < pm1) | |
340 | pm2 += (u64)ACPI_PM_OVRRUN; | |
341 | pm2 -= pm1; | |
342 | tmp = pm2 * 1000000000LL; | |
343 | do_div(tmp, PMTMR_TICKS_PER_SEC); | |
344 | do_div(deltatsc, tmp); | |
345 | ||
346 | return (unsigned long) deltatsc; | |
347 | } | |
348 | ||
a977c400 | 349 | #define CAL_MS 10 |
b7743970 | 350 | #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) |
a977c400 TG |
351 | #define CAL_PIT_LOOPS 1000 |
352 | ||
353 | #define CAL2_MS 50 | |
b7743970 | 354 | #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) |
a977c400 TG |
355 | #define CAL2_PIT_LOOPS 5000 |
356 | ||
cce3e057 | 357 | |
ec0c15af LT |
358 | /* |
359 | * Try to calibrate the TSC against the Programmable | |
360 | * Interrupt Timer and return the frequency of the TSC | |
361 | * in kHz. | |
362 | * | |
363 | * Return ULONG_MAX on failure to calibrate. | |
364 | */ | |
a977c400 | 365 | static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) |
ec0c15af LT |
366 | { |
367 | u64 tsc, t1, t2, delta; | |
368 | unsigned long tscmin, tscmax; | |
369 | int pitcnt; | |
370 | ||
371 | /* Set the Gate high, disable speaker */ | |
372 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | |
373 | ||
374 | /* | |
375 | * Setup CTC channel 2* for mode 0, (interrupt on terminal | |
376 | * count mode), binary count. Set the latch register to 50ms | |
377 | * (LSB then MSB) to begin countdown. | |
378 | */ | |
379 | outb(0xb0, 0x43); | |
a977c400 TG |
380 | outb(latch & 0xff, 0x42); |
381 | outb(latch >> 8, 0x42); | |
ec0c15af LT |
382 | |
383 | tsc = t1 = t2 = get_cycles(); | |
384 | ||
385 | pitcnt = 0; | |
386 | tscmax = 0; | |
387 | tscmin = ULONG_MAX; | |
388 | while ((inb(0x61) & 0x20) == 0) { | |
389 | t2 = get_cycles(); | |
390 | delta = t2 - tsc; | |
391 | tsc = t2; | |
392 | if ((unsigned long) delta < tscmin) | |
393 | tscmin = (unsigned int) delta; | |
394 | if ((unsigned long) delta > tscmax) | |
395 | tscmax = (unsigned int) delta; | |
396 | pitcnt++; | |
397 | } | |
398 | ||
399 | /* | |
400 | * Sanity checks: | |
401 | * | |
a977c400 | 402 | * If we were not able to read the PIT more than loopmin |
ec0c15af LT |
403 | * times, then we have been hit by a massive SMI |
404 | * | |
405 | * If the maximum is 10 times larger than the minimum, | |
406 | * then we got hit by an SMI as well. | |
407 | */ | |
a977c400 | 408 | if (pitcnt < loopmin || tscmax > 10 * tscmin) |
ec0c15af LT |
409 | return ULONG_MAX; |
410 | ||
411 | /* Calculate the PIT value */ | |
412 | delta = t2 - t1; | |
a977c400 | 413 | do_div(delta, ms); |
ec0c15af LT |
414 | return delta; |
415 | } | |
416 | ||
6ac40ed0 LT |
417 | /* |
418 | * This reads the current MSB of the PIT counter, and | |
419 | * checks if we are running on sufficiently fast and | |
420 | * non-virtualized hardware. | |
421 | * | |
422 | * Our expectations are: | |
423 | * | |
424 | * - the PIT is running at roughly 1.19MHz | |
425 | * | |
426 | * - each IO is going to take about 1us on real hardware, | |
427 | * but we allow it to be much faster (by a factor of 10) or | |
428 | * _slightly_ slower (ie we allow up to a 2us read+counter | |
429 | * update - anything else implies a unacceptably slow CPU | |
430 | * or PIT for the fast calibration to work. | |
431 | * | |
432 | * - with 256 PIT ticks to read the value, we have 214us to | |
433 | * see the same MSB (and overhead like doing a single TSC | |
434 | * read per MSB value etc). | |
435 | * | |
436 | * - We're doing 2 reads per loop (LSB, MSB), and we expect | |
437 | * them each to take about a microsecond on real hardware. | |
438 | * So we expect a count value of around 100. But we'll be | |
439 | * generous, and accept anything over 50. | |
440 | * | |
441 | * - if the PIT is stuck, and we see *many* more reads, we | |
442 | * return early (and the next caller of pit_expect_msb() | |
443 | * then consider it a failure when they don't see the | |
444 | * next expected value). | |
445 | * | |
446 | * These expectations mean that we know that we have seen the | |
447 | * transition from one expected value to another with a fairly | |
448 | * high accuracy, and we didn't miss any events. We can thus | |
449 | * use the TSC value at the transitions to calculate a pretty | |
450 | * good value for the TSC frequencty. | |
451 | */ | |
b6e61eef LT |
452 | static inline int pit_verify_msb(unsigned char val) |
453 | { | |
454 | /* Ignore LSB */ | |
455 | inb(0x42); | |
456 | return inb(0x42) == val; | |
457 | } | |
458 | ||
9e8912e0 | 459 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
6ac40ed0 | 460 | { |
9e8912e0 | 461 | int count; |
68f30fbe | 462 | u64 tsc = 0, prev_tsc = 0; |
bfc0f594 | 463 | |
6ac40ed0 | 464 | for (count = 0; count < 50000; count++) { |
b6e61eef | 465 | if (!pit_verify_msb(val)) |
6ac40ed0 | 466 | break; |
68f30fbe | 467 | prev_tsc = tsc; |
9e8912e0 | 468 | tsc = get_cycles(); |
6ac40ed0 | 469 | } |
68f30fbe | 470 | *deltap = get_cycles() - prev_tsc; |
9e8912e0 LT |
471 | *tscp = tsc; |
472 | ||
473 | /* | |
474 | * We require _some_ success, but the quality control | |
475 | * will be based on the error terms on the TSC values. | |
476 | */ | |
477 | return count > 5; | |
6ac40ed0 LT |
478 | } |
479 | ||
480 | /* | |
9e8912e0 LT |
481 | * How many MSB values do we want to see? We aim for |
482 | * a maximum error rate of 500ppm (in practice the | |
483 | * real error is much smaller), but refuse to spend | |
68f30fbe | 484 | * more than 50ms on it. |
6ac40ed0 | 485 | */ |
68f30fbe | 486 | #define MAX_QUICK_PIT_MS 50 |
9e8912e0 | 487 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
bfc0f594 | 488 | |
6ac40ed0 LT |
489 | static unsigned long quick_pit_calibrate(void) |
490 | { | |
9e8912e0 LT |
491 | int i; |
492 | u64 tsc, delta; | |
493 | unsigned long d1, d2; | |
494 | ||
6ac40ed0 | 495 | /* Set the Gate high, disable speaker */ |
bfc0f594 AK |
496 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
497 | ||
6ac40ed0 LT |
498 | /* |
499 | * Counter 2, mode 0 (one-shot), binary count | |
500 | * | |
501 | * NOTE! Mode 2 decrements by two (and then the | |
502 | * output is flipped each time, giving the same | |
503 | * final output frequency as a decrement-by-one), | |
504 | * so mode 0 is much better when looking at the | |
505 | * individual counts. | |
506 | */ | |
bfc0f594 | 507 | outb(0xb0, 0x43); |
bfc0f594 | 508 | |
6ac40ed0 LT |
509 | /* Start at 0xffff */ |
510 | outb(0xff, 0x42); | |
511 | outb(0xff, 0x42); | |
512 | ||
a6a80e1d LT |
513 | /* |
514 | * The PIT starts counting at the next edge, so we | |
515 | * need to delay for a microsecond. The easiest way | |
516 | * to do that is to just read back the 16-bit counter | |
517 | * once from the PIT. | |
518 | */ | |
b6e61eef | 519 | pit_verify_msb(0); |
a6a80e1d | 520 | |
9e8912e0 LT |
521 | if (pit_expect_msb(0xff, &tsc, &d1)) { |
522 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | |
523 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | |
524 | break; | |
525 | ||
5aac644a AH |
526 | delta -= tsc; |
527 | ||
528 | /* | |
529 | * Extrapolate the error and fail fast if the error will | |
530 | * never be below 500 ppm. | |
531 | */ | |
532 | if (i == 1 && | |
533 | d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) | |
534 | return 0; | |
535 | ||
9e8912e0 LT |
536 | /* |
537 | * Iterate until the error is less than 500 ppm | |
538 | */ | |
b6e61eef LT |
539 | if (d1+d2 >= delta >> 11) |
540 | continue; | |
541 | ||
542 | /* | |
543 | * Check the PIT one more time to verify that | |
544 | * all TSC reads were stable wrt the PIT. | |
545 | * | |
546 | * This also guarantees serialization of the | |
547 | * last cycle read ('d2') in pit_expect_msb. | |
548 | */ | |
549 | if (!pit_verify_msb(0xfe - i)) | |
550 | break; | |
551 | goto success; | |
6ac40ed0 | 552 | } |
6ac40ed0 | 553 | } |
52045217 | 554 | pr_info("Fast TSC calibration failed\n"); |
6ac40ed0 | 555 | return 0; |
9e8912e0 LT |
556 | |
557 | success: | |
558 | /* | |
559 | * Ok, if we get here, then we've seen the | |
560 | * MSB of the PIT decrement 'i' times, and the | |
561 | * error has shrunk to less than 500 ppm. | |
562 | * | |
563 | * As a result, we can depend on there not being | |
564 | * any odd delays anywhere, and the TSC reads are | |
68f30fbe | 565 | * reliable (within the error). |
9e8912e0 LT |
566 | * |
567 | * kHz = ticks / time-in-seconds / 1000; | |
568 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | |
569 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | |
570 | */ | |
9e8912e0 LT |
571 | delta *= PIT_TICK_RATE; |
572 | do_div(delta, i*256*1000); | |
c767a54b | 573 | pr_info("Fast TSC calibration using PIT\n"); |
9e8912e0 | 574 | return delta; |
6ac40ed0 | 575 | } |
ec0c15af | 576 | |
bfc0f594 | 577 | /** |
aa297292 LB |
578 | * native_calibrate_tsc |
579 | * Determine TSC frequency via CPUID, else return 0. | |
bfc0f594 | 580 | */ |
e93ef949 | 581 | unsigned long native_calibrate_tsc(void) |
aa297292 LB |
582 | { |
583 | unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; | |
584 | unsigned int crystal_khz; | |
585 | ||
586 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
587 | return 0; | |
588 | ||
589 | if (boot_cpu_data.cpuid_level < 0x15) | |
590 | return 0; | |
591 | ||
592 | eax_denominator = ebx_numerator = ecx_hz = edx = 0; | |
593 | ||
594 | /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ | |
595 | cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); | |
596 | ||
597 | if (ebx_numerator == 0 || eax_denominator == 0) | |
598 | return 0; | |
599 | ||
600 | crystal_khz = ecx_hz / 1000; | |
601 | ||
602 | if (crystal_khz == 0) { | |
603 | switch (boot_cpu_data.x86_model) { | |
655e52d2 PB |
604 | case INTEL_FAM6_SKYLAKE_MOBILE: |
605 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
6baf3d61 PB |
606 | case INTEL_FAM6_KABYLAKE_MOBILE: |
607 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
ff4c8663 LB |
608 | crystal_khz = 24000; /* 24.0 MHz */ |
609 | break; | |
6baf3d61 | 610 | case INTEL_FAM6_SKYLAKE_X: |
695085b4 | 611 | case INTEL_FAM6_ATOM_DENVERTON: |
6baf3d61 PB |
612 | crystal_khz = 25000; /* 25.0 MHz */ |
613 | break; | |
655e52d2 | 614 | case INTEL_FAM6_ATOM_GOLDMONT: |
ff4c8663 LB |
615 | crystal_khz = 19200; /* 19.2 MHz */ |
616 | break; | |
aa297292 LB |
617 | } |
618 | } | |
619 | ||
4ca4df0b BG |
620 | /* |
621 | * TSC frequency determined by CPUID is a "hardware reported" | |
622 | * frequency and is the most accurate one so far we have. This | |
623 | * is considered a known frequency. | |
624 | */ | |
625 | setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); | |
626 | ||
4635fdc6 BG |
627 | /* |
628 | * For Atom SoCs TSC is the only reliable clocksource. | |
629 | * Mark TSC reliable so no watchdog on it. | |
630 | */ | |
631 | if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) | |
632 | setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); | |
633 | ||
aa297292 LB |
634 | return crystal_khz * ebx_numerator / eax_denominator; |
635 | } | |
636 | ||
637 | static unsigned long cpu_khz_from_cpuid(void) | |
638 | { | |
639 | unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; | |
640 | ||
641 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
642 | return 0; | |
643 | ||
644 | if (boot_cpu_data.cpuid_level < 0x16) | |
645 | return 0; | |
646 | ||
647 | eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; | |
648 | ||
649 | cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); | |
650 | ||
651 | return eax_base_mhz * 1000; | |
652 | } | |
653 | ||
654 | /** | |
655 | * native_calibrate_cpu - calibrate the cpu on boot | |
656 | */ | |
657 | unsigned long native_calibrate_cpu(void) | |
bfc0f594 | 658 | { |
827014be | 659 | u64 tsc1, tsc2, delta, ref1, ref2; |
fbb16e24 | 660 | unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; |
2d826404 | 661 | unsigned long flags, latch, ms, fast_calibrate; |
a977c400 | 662 | int hpet = is_hpet_enabled(), i, loopmin; |
bfc0f594 | 663 | |
aa297292 LB |
664 | fast_calibrate = cpu_khz_from_cpuid(); |
665 | if (fast_calibrate) | |
666 | return fast_calibrate; | |
667 | ||
02c0cd2d | 668 | fast_calibrate = cpu_khz_from_msr(); |
5f0e0309 | 669 | if (fast_calibrate) |
7da7c156 | 670 | return fast_calibrate; |
7da7c156 | 671 | |
6ac40ed0 LT |
672 | local_irq_save(flags); |
673 | fast_calibrate = quick_pit_calibrate(); | |
bfc0f594 | 674 | local_irq_restore(flags); |
6ac40ed0 LT |
675 | if (fast_calibrate) |
676 | return fast_calibrate; | |
bfc0f594 | 677 | |
fbb16e24 TG |
678 | /* |
679 | * Run 5 calibration loops to get the lowest frequency value | |
680 | * (the best estimate). We use two different calibration modes | |
681 | * here: | |
682 | * | |
683 | * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and | |
684 | * load a timeout of 50ms. We read the time right after we | |
685 | * started the timer and wait until the PIT count down reaches | |
686 | * zero. In each wait loop iteration we read the TSC and check | |
687 | * the delta to the previous read. We keep track of the min | |
688 | * and max values of that delta. The delta is mostly defined | |
689 | * by the IO time of the PIT access, so we can detect when a | |
0d2eb44f | 690 | * SMI/SMM disturbance happened between the two reads. If the |
fbb16e24 TG |
691 | * maximum time is significantly larger than the minimum time, |
692 | * then we discard the result and have another try. | |
693 | * | |
694 | * 2) Reference counter. If available we use the HPET or the | |
695 | * PMTIMER as a reference to check the sanity of that value. | |
696 | * We use separate TSC readouts and check inside of the | |
697 | * reference read for a SMI/SMM disturbance. We dicard | |
698 | * disturbed values here as well. We do that around the PIT | |
699 | * calibration delay loop as we have to wait for a certain | |
700 | * amount of time anyway. | |
701 | */ | |
a977c400 TG |
702 | |
703 | /* Preset PIT loop values */ | |
704 | latch = CAL_LATCH; | |
705 | ms = CAL_MS; | |
706 | loopmin = CAL_PIT_LOOPS; | |
707 | ||
708 | for (i = 0; i < 3; i++) { | |
ec0c15af | 709 | unsigned long tsc_pit_khz; |
fbb16e24 TG |
710 | |
711 | /* | |
712 | * Read the start value and the reference count of | |
ec0c15af LT |
713 | * hpet/pmtimer when available. Then do the PIT |
714 | * calibration, which will take at least 50ms, and | |
715 | * read the end value. | |
fbb16e24 | 716 | */ |
ec0c15af | 717 | local_irq_save(flags); |
827014be | 718 | tsc1 = tsc_read_refs(&ref1, hpet); |
a977c400 | 719 | tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); |
827014be | 720 | tsc2 = tsc_read_refs(&ref2, hpet); |
fbb16e24 TG |
721 | local_irq_restore(flags); |
722 | ||
ec0c15af LT |
723 | /* Pick the lowest PIT TSC calibration so far */ |
724 | tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); | |
fbb16e24 TG |
725 | |
726 | /* hpet or pmtimer available ? */ | |
62627bec | 727 | if (ref1 == ref2) |
fbb16e24 TG |
728 | continue; |
729 | ||
730 | /* Check, whether the sampling was disturbed by an SMI */ | |
731 | if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) | |
732 | continue; | |
733 | ||
734 | tsc2 = (tsc2 - tsc1) * 1000000LL; | |
d683ef7a | 735 | if (hpet) |
827014be | 736 | tsc2 = calc_hpet_ref(tsc2, ref1, ref2); |
d683ef7a | 737 | else |
827014be | 738 | tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); |
fbb16e24 | 739 | |
fbb16e24 | 740 | tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); |
a977c400 TG |
741 | |
742 | /* Check the reference deviation */ | |
743 | delta = ((u64) tsc_pit_min) * 100; | |
744 | do_div(delta, tsc_ref_min); | |
745 | ||
746 | /* | |
747 | * If both calibration results are inside a 10% window | |
748 | * then we can be sure, that the calibration | |
749 | * succeeded. We break out of the loop right away. We | |
750 | * use the reference value, as it is more precise. | |
751 | */ | |
752 | if (delta >= 90 && delta <= 110) { | |
c767a54b JP |
753 | pr_info("PIT calibration matches %s. %d loops\n", |
754 | hpet ? "HPET" : "PMTIMER", i + 1); | |
a977c400 | 755 | return tsc_ref_min; |
fbb16e24 TG |
756 | } |
757 | ||
a977c400 TG |
758 | /* |
759 | * Check whether PIT failed more than once. This | |
760 | * happens in virtualized environments. We need to | |
761 | * give the virtual PC a slightly longer timeframe for | |
762 | * the HPET/PMTIMER to make the result precise. | |
763 | */ | |
764 | if (i == 1 && tsc_pit_min == ULONG_MAX) { | |
765 | latch = CAL2_LATCH; | |
766 | ms = CAL2_MS; | |
767 | loopmin = CAL2_PIT_LOOPS; | |
768 | } | |
fbb16e24 | 769 | } |
bfc0f594 AK |
770 | |
771 | /* | |
fbb16e24 | 772 | * Now check the results. |
bfc0f594 | 773 | */ |
fbb16e24 TG |
774 | if (tsc_pit_min == ULONG_MAX) { |
775 | /* PIT gave no useful value */ | |
c767a54b | 776 | pr_warn("Unable to calibrate against PIT\n"); |
fbb16e24 TG |
777 | |
778 | /* We don't have an alternative source, disable TSC */ | |
827014be | 779 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 780 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
fbb16e24 TG |
781 | return 0; |
782 | } | |
783 | ||
784 | /* The alternative source failed as well, disable TSC */ | |
785 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 786 | pr_warn("HPET/PMTIMER calibration failed\n"); |
fbb16e24 TG |
787 | return 0; |
788 | } | |
789 | ||
790 | /* Use the alternative source */ | |
c767a54b JP |
791 | pr_info("using %s reference calibration\n", |
792 | hpet ? "HPET" : "PMTIMER"); | |
fbb16e24 TG |
793 | |
794 | return tsc_ref_min; | |
795 | } | |
bfc0f594 | 796 | |
fbb16e24 | 797 | /* We don't have an alternative source, use the PIT calibration value */ |
827014be | 798 | if (!hpet && !ref1 && !ref2) { |
c767a54b | 799 | pr_info("Using PIT calibration value\n"); |
fbb16e24 | 800 | return tsc_pit_min; |
bfc0f594 AK |
801 | } |
802 | ||
fbb16e24 TG |
803 | /* The alternative source failed, use the PIT calibration value */ |
804 | if (tsc_ref_min == ULONG_MAX) { | |
c767a54b | 805 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
fbb16e24 | 806 | return tsc_pit_min; |
bfc0f594 AK |
807 | } |
808 | ||
fbb16e24 TG |
809 | /* |
810 | * The calibration values differ too much. In doubt, we use | |
811 | * the PIT value as we know that there are PMTIMERs around | |
a977c400 | 812 | * running at double speed. At least we let the user know: |
fbb16e24 | 813 | */ |
c767a54b JP |
814 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
815 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | |
816 | pr_info("Using PIT calibration value\n"); | |
fbb16e24 | 817 | return tsc_pit_min; |
bfc0f594 AK |
818 | } |
819 | ||
bfc0f594 AK |
820 | int recalibrate_cpu_khz(void) |
821 | { | |
822 | #ifndef CONFIG_SMP | |
823 | unsigned long cpu_khz_old = cpu_khz; | |
824 | ||
eff4677e | 825 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
bfc0f594 | 826 | return -ENODEV; |
eff4677e | 827 | |
aa297292 | 828 | cpu_khz = x86_platform.calibrate_cpu(); |
eff4677e | 829 | tsc_khz = x86_platform.calibrate_tsc(); |
aa297292 LB |
830 | if (tsc_khz == 0) |
831 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
832 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
833 | cpu_khz = tsc_khz; | |
eff4677e BP |
834 | cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, |
835 | cpu_khz_old, cpu_khz); | |
836 | ||
837 | return 0; | |
bfc0f594 AK |
838 | #else |
839 | return -ENODEV; | |
840 | #endif | |
841 | } | |
842 | ||
843 | EXPORT_SYMBOL(recalibrate_cpu_khz); | |
844 | ||
2dbe06fa | 845 | |
cd7240c0 SS |
846 | static unsigned long long cyc2ns_suspend; |
847 | ||
b74f05d6 | 848 | void tsc_save_sched_clock_state(void) |
cd7240c0 | 849 | { |
35af99e6 | 850 | if (!sched_clock_stable()) |
cd7240c0 SS |
851 | return; |
852 | ||
853 | cyc2ns_suspend = sched_clock(); | |
854 | } | |
855 | ||
856 | /* | |
857 | * Even on processors with invariant TSC, TSC gets reset in some the | |
858 | * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to | |
859 | * arbitrary value (still sync'd across cpu's) during resume from such sleep | |
860 | * states. To cope up with this, recompute the cyc2ns_offset for each cpu so | |
861 | * that sched_clock() continues from the point where it was left off during | |
862 | * suspend. | |
863 | */ | |
b74f05d6 | 864 | void tsc_restore_sched_clock_state(void) |
cd7240c0 SS |
865 | { |
866 | unsigned long long offset; | |
867 | unsigned long flags; | |
868 | int cpu; | |
869 | ||
35af99e6 | 870 | if (!sched_clock_stable()) |
cd7240c0 SS |
871 | return; |
872 | ||
873 | local_irq_save(flags); | |
874 | ||
20d1c86a | 875 | /* |
6a6256f9 | 876 | * We're coming out of suspend, there's no concurrency yet; don't |
20d1c86a PZ |
877 | * bother being nice about the RCU stuff, just write to both |
878 | * data fields. | |
879 | */ | |
880 | ||
881 | this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); | |
882 | this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); | |
883 | ||
cd7240c0 SS |
884 | offset = cyc2ns_suspend - sched_clock(); |
885 | ||
20d1c86a PZ |
886 | for_each_possible_cpu(cpu) { |
887 | per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; | |
888 | per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; | |
889 | } | |
cd7240c0 SS |
890 | |
891 | local_irq_restore(flags); | |
892 | } | |
893 | ||
2dbe06fa AK |
894 | #ifdef CONFIG_CPU_FREQ |
895 | ||
896 | /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency | |
897 | * changes. | |
898 | * | |
899 | * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's | |
900 | * not that important because current Opteron setups do not support | |
901 | * scaling on SMP anyroads. | |
902 | * | |
903 | * Should fix up last_tsc too. Currently gettimeofday in the | |
904 | * first tick after the change will be slightly wrong. | |
905 | */ | |
906 | ||
907 | static unsigned int ref_freq; | |
908 | static unsigned long loops_per_jiffy_ref; | |
909 | static unsigned long tsc_khz_ref; | |
910 | ||
911 | static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
912 | void *data) | |
913 | { | |
914 | struct cpufreq_freqs *freq = data; | |
931db6a3 | 915 | unsigned long *lpj; |
2dbe06fa | 916 | |
931db6a3 | 917 | lpj = &boot_cpu_data.loops_per_jiffy; |
2dbe06fa | 918 | #ifdef CONFIG_SMP |
931db6a3 | 919 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) |
2dbe06fa | 920 | lpj = &cpu_data(freq->cpu).loops_per_jiffy; |
2dbe06fa AK |
921 | #endif |
922 | ||
923 | if (!ref_freq) { | |
924 | ref_freq = freq->old; | |
925 | loops_per_jiffy_ref = *lpj; | |
926 | tsc_khz_ref = tsc_khz; | |
927 | } | |
928 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 929 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
878f4f53 | 930 | *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); |
2dbe06fa AK |
931 | |
932 | tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
933 | if (!(freq->flags & CPUFREQ_CONST_LOOPS)) | |
934 | mark_tsc_unstable("cpufreq changes"); | |
2dbe06fa | 935 | |
3896c329 PZ |
936 | set_cyc2ns_scale(tsc_khz, freq->cpu); |
937 | } | |
2dbe06fa AK |
938 | |
939 | return 0; | |
940 | } | |
941 | ||
942 | static struct notifier_block time_cpufreq_notifier_block = { | |
943 | .notifier_call = time_cpufreq_notifier | |
944 | }; | |
945 | ||
a841cca7 | 946 | static int __init cpufreq_register_tsc_scaling(void) |
2dbe06fa | 947 | { |
59e21e3d | 948 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
060700b5 LT |
949 | return 0; |
950 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
951 | return 0; | |
2dbe06fa AK |
952 | cpufreq_register_notifier(&time_cpufreq_notifier_block, |
953 | CPUFREQ_TRANSITION_NOTIFIER); | |
954 | return 0; | |
955 | } | |
956 | ||
a841cca7 | 957 | core_initcall(cpufreq_register_tsc_scaling); |
2dbe06fa AK |
958 | |
959 | #endif /* CONFIG_CPU_FREQ */ | |
8fbbc4b4 | 960 | |
f9677e0f CH |
961 | #define ART_CPUID_LEAF (0x15) |
962 | #define ART_MIN_DENOMINATOR (1) | |
963 | ||
964 | ||
965 | /* | |
966 | * If ART is present detect the numerator:denominator to convert to TSC | |
967 | */ | |
968 | static void detect_art(void) | |
969 | { | |
970 | unsigned int unused[2]; | |
971 | ||
972 | if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) | |
973 | return; | |
974 | ||
7b3d2f6e | 975 | /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */ |
f9677e0f CH |
976 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || |
977 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || | |
7b3d2f6e | 978 | !boot_cpu_has(X86_FEATURE_TSC_ADJUST)) |
f9677e0f CH |
979 | return; |
980 | ||
7b3d2f6e TG |
981 | cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, |
982 | &art_to_tsc_numerator, unused, unused+1); | |
983 | ||
984 | if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) | |
f9677e0f CH |
985 | return; |
986 | ||
7b3d2f6e TG |
987 | rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); |
988 | ||
f9677e0f CH |
989 | /* Make this sticky over multiple CPU init calls */ |
990 | setup_force_cpu_cap(X86_FEATURE_ART); | |
991 | } | |
992 | ||
993 | ||
8fbbc4b4 AK |
994 | /* clocksource code */ |
995 | ||
996 | static struct clocksource clocksource_tsc; | |
997 | ||
6a369583 TG |
998 | static void tsc_resume(struct clocksource *cs) |
999 | { | |
1000 | tsc_verify_tsc_adjust(true); | |
1001 | } | |
1002 | ||
8fbbc4b4 | 1003 | /* |
09ec5442 | 1004 | * We used to compare the TSC to the cycle_last value in the clocksource |
8fbbc4b4 AK |
1005 | * structure to avoid a nasty time-warp. This can be observed in a |
1006 | * very small window right after one CPU updated cycle_last under | |
1007 | * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which | |
1008 | * is smaller than the cycle_last reference value due to a TSC which | |
1009 | * is slighty behind. This delta is nowhere else observable, but in | |
1010 | * that case it results in a forward time jump in the range of hours | |
1011 | * due to the unsigned delta calculation of the time keeping core | |
1012 | * code, which is necessary to support wrapping clocksources like pm | |
1013 | * timer. | |
09ec5442 TG |
1014 | * |
1015 | * This sanity check is now done in the core timekeeping code. | |
1016 | * checking the result of read_tsc() - cycle_last for being negative. | |
1017 | * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. | |
8fbbc4b4 | 1018 | */ |
a5a1d1c2 | 1019 | static u64 read_tsc(struct clocksource *cs) |
8fbbc4b4 | 1020 | { |
a5a1d1c2 | 1021 | return (u64)rdtsc_ordered(); |
1be39679 MS |
1022 | } |
1023 | ||
12907fbb TG |
1024 | static void tsc_cs_mark_unstable(struct clocksource *cs) |
1025 | { | |
1026 | if (tsc_unstable) | |
1027 | return; | |
f94c8d11 | 1028 | |
12907fbb | 1029 | tsc_unstable = 1; |
f94c8d11 PZ |
1030 | if (using_native_sched_clock()) |
1031 | clear_sched_clock_stable(); | |
12907fbb TG |
1032 | disable_sched_clock_irqtime(); |
1033 | pr_info("Marking TSC unstable due to clocksource watchdog\n"); | |
1034 | } | |
1035 | ||
09ec5442 TG |
1036 | /* |
1037 | * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() | |
1038 | */ | |
8fbbc4b4 AK |
1039 | static struct clocksource clocksource_tsc = { |
1040 | .name = "tsc", | |
1041 | .rating = 300, | |
1042 | .read = read_tsc, | |
1043 | .mask = CLOCKSOURCE_MASK(64), | |
8fbbc4b4 AK |
1044 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | |
1045 | CLOCK_SOURCE_MUST_VERIFY, | |
98d0ac38 | 1046 | .archdata = { .vclock_mode = VCLOCK_TSC }, |
6a369583 | 1047 | .resume = tsc_resume, |
12907fbb | 1048 | .mark_unstable = tsc_cs_mark_unstable, |
8fbbc4b4 AK |
1049 | }; |
1050 | ||
1051 | void mark_tsc_unstable(char *reason) | |
1052 | { | |
f94c8d11 PZ |
1053 | if (tsc_unstable) |
1054 | return; | |
1055 | ||
1056 | tsc_unstable = 1; | |
1057 | if (using_native_sched_clock()) | |
35af99e6 | 1058 | clear_sched_clock_stable(); |
f94c8d11 PZ |
1059 | disable_sched_clock_irqtime(); |
1060 | pr_info("Marking TSC unstable due to %s\n", reason); | |
1061 | /* Change only the rating, when not registered */ | |
1062 | if (clocksource_tsc.mult) { | |
1063 | clocksource_mark_unstable(&clocksource_tsc); | |
1064 | } else { | |
1065 | clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE; | |
1066 | clocksource_tsc.rating = 0; | |
8fbbc4b4 AK |
1067 | } |
1068 | } | |
1069 | ||
1070 | EXPORT_SYMBOL_GPL(mark_tsc_unstable); | |
1071 | ||
395628ef AK |
1072 | static void __init check_system_tsc_reliable(void) |
1073 | { | |
03da3ff1 DW |
1074 | #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) |
1075 | if (is_geode_lx()) { | |
1076 | /* RTSC counts during suspend */ | |
8fbbc4b4 | 1077 | #define RTSC_SUSP 0x100 |
03da3ff1 | 1078 | unsigned long res_low, res_high; |
8fbbc4b4 | 1079 | |
03da3ff1 DW |
1080 | rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); |
1081 | /* Geode_LX - the OLPC CPU has a very reliable TSC */ | |
1082 | if (res_low & RTSC_SUSP) | |
1083 | tsc_clocksource_reliable = 1; | |
1084 | } | |
8fbbc4b4 | 1085 | #endif |
395628ef AK |
1086 | if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) |
1087 | tsc_clocksource_reliable = 1; | |
1088 | } | |
8fbbc4b4 AK |
1089 | |
1090 | /* | |
1091 | * Make an educated guess if the TSC is trustworthy and synchronized | |
1092 | * over all CPUs. | |
1093 | */ | |
148f9bb8 | 1094 | int unsynchronized_tsc(void) |
8fbbc4b4 | 1095 | { |
59e21e3d | 1096 | if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) |
8fbbc4b4 AK |
1097 | return 1; |
1098 | ||
3e5095d1 | 1099 | #ifdef CONFIG_SMP |
8fbbc4b4 AK |
1100 | if (apic_is_clustered_box()) |
1101 | return 1; | |
1102 | #endif | |
1103 | ||
1104 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1105 | return 0; | |
d3b8f889 JS |
1106 | |
1107 | if (tsc_clocksource_reliable) | |
1108 | return 0; | |
8fbbc4b4 AK |
1109 | /* |
1110 | * Intel systems are normally all synchronized. | |
1111 | * Exceptions must mark TSC as unstable: | |
1112 | */ | |
1113 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { | |
1114 | /* assume multi socket systems are not synchronized: */ | |
1115 | if (num_possible_cpus() > 1) | |
d3b8f889 | 1116 | return 1; |
8fbbc4b4 AK |
1117 | } |
1118 | ||
d3b8f889 | 1119 | return 0; |
8fbbc4b4 AK |
1120 | } |
1121 | ||
f9677e0f CH |
1122 | /* |
1123 | * Convert ART to TSC given numerator/denominator found in detect_art() | |
1124 | */ | |
a5a1d1c2 | 1125 | struct system_counterval_t convert_art_to_tsc(u64 art) |
f9677e0f CH |
1126 | { |
1127 | u64 tmp, res, rem; | |
1128 | ||
1129 | rem = do_div(art, art_to_tsc_denominator); | |
1130 | ||
1131 | res = art * art_to_tsc_numerator; | |
1132 | tmp = rem * art_to_tsc_numerator; | |
1133 | ||
1134 | do_div(tmp, art_to_tsc_denominator); | |
1135 | res += tmp + art_to_tsc_offset; | |
1136 | ||
1137 | return (struct system_counterval_t) {.cs = art_related_clocksource, | |
1138 | .cycles = res}; | |
1139 | } | |
1140 | EXPORT_SYMBOL(convert_art_to_tsc); | |
08ec0c58 JS |
1141 | |
1142 | static void tsc_refine_calibration_work(struct work_struct *work); | |
1143 | static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); | |
1144 | /** | |
1145 | * tsc_refine_calibration_work - Further refine tsc freq calibration | |
1146 | * @work - ignored. | |
1147 | * | |
1148 | * This functions uses delayed work over a period of a | |
1149 | * second to further refine the TSC freq value. Since this is | |
1150 | * timer based, instead of loop based, we don't block the boot | |
1151 | * process while this longer calibration is done. | |
1152 | * | |
0d2eb44f | 1153 | * If there are any calibration anomalies (too many SMIs, etc), |
08ec0c58 JS |
1154 | * or the refined calibration is off by 1% of the fast early |
1155 | * calibration, we throw out the new calibration and use the | |
1156 | * early calibration. | |
1157 | */ | |
1158 | static void tsc_refine_calibration_work(struct work_struct *work) | |
1159 | { | |
1160 | static u64 tsc_start = -1, ref_start; | |
1161 | static int hpet; | |
1162 | u64 tsc_stop, ref_stop, delta; | |
1163 | unsigned long freq; | |
aa7b630e | 1164 | int cpu; |
08ec0c58 JS |
1165 | |
1166 | /* Don't bother refining TSC on unstable systems */ | |
1167 | if (check_tsc_unstable()) | |
1168 | goto out; | |
1169 | ||
1170 | /* | |
1171 | * Since the work is started early in boot, we may be | |
1172 | * delayed the first time we expire. So set the workqueue | |
1173 | * again once we know timers are working. | |
1174 | */ | |
1175 | if (tsc_start == -1) { | |
1176 | /* | |
1177 | * Only set hpet once, to avoid mixing hardware | |
1178 | * if the hpet becomes enabled later. | |
1179 | */ | |
1180 | hpet = is_hpet_enabled(); | |
1181 | schedule_delayed_work(&tsc_irqwork, HZ); | |
1182 | tsc_start = tsc_read_refs(&ref_start, hpet); | |
1183 | return; | |
1184 | } | |
1185 | ||
1186 | tsc_stop = tsc_read_refs(&ref_stop, hpet); | |
1187 | ||
1188 | /* hpet or pmtimer available ? */ | |
62627bec | 1189 | if (ref_start == ref_stop) |
08ec0c58 JS |
1190 | goto out; |
1191 | ||
1192 | /* Check, whether the sampling was disturbed by an SMI */ | |
1193 | if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) | |
1194 | goto out; | |
1195 | ||
1196 | delta = tsc_stop - tsc_start; | |
1197 | delta *= 1000000LL; | |
1198 | if (hpet) | |
1199 | freq = calc_hpet_ref(delta, ref_start, ref_stop); | |
1200 | else | |
1201 | freq = calc_pmtimer_ref(delta, ref_start, ref_stop); | |
1202 | ||
1203 | /* Make sure we're within 1% */ | |
1204 | if (abs(tsc_khz - freq) > tsc_khz/100) | |
1205 | goto out; | |
1206 | ||
1207 | tsc_khz = freq; | |
c767a54b JP |
1208 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
1209 | (unsigned long)tsc_khz / 1000, | |
1210 | (unsigned long)tsc_khz % 1000); | |
08ec0c58 | 1211 | |
6731b0d6 NS |
1212 | /* Inform the TSC deadline clockevent devices about the recalibration */ |
1213 | lapic_update_tsc_freq(); | |
1214 | ||
aa7b630e PZ |
1215 | /* Update the sched_clock() rate to match the clocksource one */ |
1216 | for_each_possible_cpu(cpu) | |
1217 | __set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); | |
1218 | ||
08ec0c58 | 1219 | out: |
f9677e0f CH |
1220 | if (boot_cpu_has(X86_FEATURE_ART)) |
1221 | art_related_clocksource = &clocksource_tsc; | |
08ec0c58 JS |
1222 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
1223 | } | |
1224 | ||
1225 | ||
1226 | static int __init init_tsc_clocksource(void) | |
8fbbc4b4 | 1227 | { |
59e21e3d | 1228 | if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz) |
a8760eca TG |
1229 | return 0; |
1230 | ||
395628ef AK |
1231 | if (tsc_clocksource_reliable) |
1232 | clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; | |
8fbbc4b4 AK |
1233 | /* lower the rating if we already know its unstable: */ |
1234 | if (check_tsc_unstable()) { | |
1235 | clocksource_tsc.rating = 0; | |
1236 | clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; | |
1237 | } | |
57779dc2 | 1238 | |
82f9c080 FT |
1239 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) |
1240 | clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; | |
1241 | ||
57779dc2 | 1242 | /* |
47c95a46 BG |
1243 | * When TSC frequency is known (retrieved via MSR or CPUID), we skip |
1244 | * the refined calibration and directly register it as a clocksource. | |
57779dc2 | 1245 | */ |
984feceb | 1246 | if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { |
44fee88c PZ |
1247 | if (boot_cpu_has(X86_FEATURE_ART)) |
1248 | art_related_clocksource = &clocksource_tsc; | |
57779dc2 AK |
1249 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
1250 | return 0; | |
1251 | } | |
1252 | ||
08ec0c58 JS |
1253 | schedule_delayed_work(&tsc_irqwork, 0); |
1254 | return 0; | |
8fbbc4b4 | 1255 | } |
08ec0c58 JS |
1256 | /* |
1257 | * We use device_initcall here, to ensure we run after the hpet | |
1258 | * is fully initialized, which may occur at fs_initcall time. | |
1259 | */ | |
1260 | device_initcall(init_tsc_clocksource); | |
8fbbc4b4 AK |
1261 | |
1262 | void __init tsc_init(void) | |
1263 | { | |
615cd033 | 1264 | u64 lpj, cyc; |
8fbbc4b4 AK |
1265 | int cpu; |
1266 | ||
59e21e3d | 1267 | if (!boot_cpu_has(X86_FEATURE_TSC)) { |
b47dcbdc | 1268 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 | 1269 | return; |
b47dcbdc | 1270 | } |
8fbbc4b4 | 1271 | |
aa297292 | 1272 | cpu_khz = x86_platform.calibrate_cpu(); |
2d826404 | 1273 | tsc_khz = x86_platform.calibrate_tsc(); |
ff4c8663 LB |
1274 | |
1275 | /* | |
1276 | * Trust non-zero tsc_khz as authorative, | |
1277 | * and use it to sanity check cpu_khz, | |
1278 | * which will be off if system timer is off. | |
1279 | */ | |
aa297292 LB |
1280 | if (tsc_khz == 0) |
1281 | tsc_khz = cpu_khz; | |
ff4c8663 LB |
1282 | else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) |
1283 | cpu_khz = tsc_khz; | |
8fbbc4b4 | 1284 | |
e93ef949 | 1285 | if (!tsc_khz) { |
8fbbc4b4 | 1286 | mark_tsc_unstable("could not calculate TSC khz"); |
b47dcbdc | 1287 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
8fbbc4b4 AK |
1288 | return; |
1289 | } | |
1290 | ||
c767a54b JP |
1291 | pr_info("Detected %lu.%03lu MHz processor\n", |
1292 | (unsigned long)cpu_khz / 1000, | |
1293 | (unsigned long)cpu_khz % 1000); | |
8fbbc4b4 | 1294 | |
f2e04214 TG |
1295 | /* Sanitize TSC ADJUST before cyc2ns gets initialized */ |
1296 | tsc_store_and_check_tsc_adjust(true); | |
1297 | ||
8fbbc4b4 AK |
1298 | /* |
1299 | * Secondary CPUs do not run through tsc_init(), so set up | |
1300 | * all the scale factors for all CPUs, assuming the same | |
1301 | * speed as the bootup CPU. (cpufreq notifiers will fix this | |
1302 | * up if their speed diverges) | |
1303 | */ | |
615cd033 | 1304 | cyc = rdtsc(); |
20d1c86a PZ |
1305 | for_each_possible_cpu(cpu) { |
1306 | cyc2ns_init(cpu); | |
615cd033 | 1307 | __set_cyc2ns_scale(tsc_khz, cpu, cyc); |
20d1c86a | 1308 | } |
8fbbc4b4 AK |
1309 | |
1310 | if (tsc_disabled > 0) | |
1311 | return; | |
1312 | ||
1313 | /* now allow native_sched_clock() to use rdtsc */ | |
10b033d4 | 1314 | |
8fbbc4b4 | 1315 | tsc_disabled = 0; |
3bbfafb7 | 1316 | static_branch_enable(&__use_tsc); |
8fbbc4b4 | 1317 | |
e82b8e4e VP |
1318 | if (!no_sched_irq_time) |
1319 | enable_sched_clock_irqtime(); | |
1320 | ||
70de9a97 AK |
1321 | lpj = ((u64)tsc_khz * 1000); |
1322 | do_div(lpj, HZ); | |
1323 | lpj_fine = lpj; | |
1324 | ||
8fbbc4b4 | 1325 | use_tsc_delay(); |
8fbbc4b4 AK |
1326 | |
1327 | if (unsynchronized_tsc()) | |
1328 | mark_tsc_unstable("TSCs unsynchronized"); | |
1329 | ||
395628ef | 1330 | check_system_tsc_reliable(); |
f9677e0f CH |
1331 | |
1332 | detect_art(); | |
8fbbc4b4 AK |
1333 | } |
1334 | ||
b565201c JS |
1335 | #ifdef CONFIG_SMP |
1336 | /* | |
1337 | * If we have a constant TSC and are using the TSC for the delay loop, | |
1338 | * we can skip clock calibration if another cpu in the same socket has already | |
1339 | * been calibrated. This assumes that CONSTANT_TSC applies to all | |
1340 | * cpus in the socket - this should be a safe assumption. | |
1341 | */ | |
148f9bb8 | 1342 | unsigned long calibrate_delay_is_known(void) |
b565201c | 1343 | { |
c25323c0 | 1344 | int sibling, cpu = smp_processor_id(); |
f508a5ba | 1345 | struct cpumask *mask = topology_core_cpumask(cpu); |
b565201c JS |
1346 | |
1347 | if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC)) | |
1348 | return 0; | |
1349 | ||
f508a5ba TG |
1350 | if (!mask) |
1351 | return 0; | |
1352 | ||
1353 | sibling = cpumask_any_but(mask, cpu); | |
c25323c0 TG |
1354 | if (sibling < nr_cpu_ids) |
1355 | return cpu_data(sibling).loops_per_jiffy; | |
b565201c JS |
1356 | return 0; |
1357 | } | |
1358 | #endif |