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2b144498 | 1 | /* |
7b2d81d4 | 2 | * User-space Probes (UProbes) for x86 |
2b144498 SD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * Copyright (C) IBM Corporation, 2008-2011 | |
19 | * Authors: | |
20 | * Srikar Dronamraju | |
21 | * Jim Keniston | |
22 | */ | |
2b144498 SD |
23 | #include <linux/kernel.h> |
24 | #include <linux/sched.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/uprobes.h> | |
0326f5a9 | 27 | #include <linux/uaccess.h> |
2b144498 SD |
28 | |
29 | #include <linux/kdebug.h> | |
0326f5a9 | 30 | #include <asm/processor.h> |
2b144498 SD |
31 | #include <asm/insn.h> |
32 | ||
33 | /* Post-execution fixups. */ | |
34 | ||
2b144498 | 35 | /* Adjust IP back to vicinity of actual insn */ |
900771a4 | 36 | #define UPROBE_FIX_IP 0x1 |
0326f5a9 | 37 | |
2b144498 | 38 | /* Adjust the return address of a call insn */ |
900771a4 | 39 | #define UPROBE_FIX_CALL 0x2 |
2b144498 | 40 | |
bdc1e472 SAS |
41 | /* Instruction will modify TF, don't change it */ |
42 | #define UPROBE_FIX_SETF 0x4 | |
43 | ||
900771a4 SD |
44 | #define UPROBE_FIX_RIP_AX 0x8000 |
45 | #define UPROBE_FIX_RIP_CX 0x4000 | |
2b144498 | 46 | |
0326f5a9 SD |
47 | #define UPROBE_TRAP_NR UINT_MAX |
48 | ||
2b144498 | 49 | /* Adaptations for mhiramat x86 decoder v14. */ |
7b2d81d4 IM |
50 | #define OPCODE1(insn) ((insn)->opcode.bytes[0]) |
51 | #define OPCODE2(insn) ((insn)->opcode.bytes[1]) | |
52 | #define OPCODE3(insn) ((insn)->opcode.bytes[2]) | |
ddb69f27 | 53 | #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) |
2b144498 SD |
54 | |
55 | #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ | |
56 | (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ | |
57 | (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ | |
58 | (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ | |
59 | (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ | |
60 | << (row % 32)) | |
61 | ||
04a3d984 SD |
62 | /* |
63 | * Good-instruction tables for 32-bit apps. This is non-const and volatile | |
64 | * to keep gcc from statically optimizing it out, as variable_test_bit makes | |
65 | * some versions of gcc to think only *(unsigned long*) is used. | |
66 | */ | |
67 | static volatile u32 good_insns_32[256 / 32] = { | |
2b144498 SD |
68 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
69 | /* ---------------------------------------------- */ | |
70 | W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */ | |
71 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ | |
72 | W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */ | |
73 | W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */ | |
74 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
75 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
76 | W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ | |
77 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ | |
78 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
79 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
80 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ | |
81 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
82 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ | |
83 | W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
84 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ | |
85 | W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ | |
86 | /* ---------------------------------------------- */ | |
87 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
88 | }; | |
89 | ||
90 | /* Using this for both 64-bit and 32-bit apps */ | |
04a3d984 | 91 | static volatile u32 good_2byte_insns[256 / 32] = { |
2b144498 SD |
92 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
93 | /* ---------------------------------------------- */ | |
94 | W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */ | |
95 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ | |
96 | W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ | |
97 | W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */ | |
98 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
99 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
100 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ | |
101 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */ | |
102 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
103 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
104 | W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ | |
105 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
106 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ | |
107 | W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
108 | W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ | |
109 | W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */ | |
110 | /* ---------------------------------------------- */ | |
111 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
112 | }; | |
113 | ||
04a3d984 SD |
114 | /* Good-instruction tables for 64-bit apps */ |
115 | static volatile u32 good_insns_64[256 / 32] = { | |
116 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
117 | /* ---------------------------------------------- */ | |
118 | W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */ | |
119 | W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ | |
120 | W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */ | |
121 | W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */ | |
122 | W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */ | |
123 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
124 | W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ | |
125 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ | |
126 | W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
127 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
128 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ | |
129 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
130 | W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ | |
131 | W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
132 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ | |
133 | W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ | |
134 | /* ---------------------------------------------- */ | |
135 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
136 | }; | |
2b144498 SD |
137 | #undef W |
138 | ||
139 | /* | |
140 | * opcodes we'll probably never support: | |
7b2d81d4 IM |
141 | * |
142 | * 6c-6d, e4-e5, ec-ed - in | |
143 | * 6e-6f, e6-e7, ee-ef - out | |
144 | * cc, cd - int3, int | |
145 | * cf - iret | |
146 | * d6 - illegal instruction | |
147 | * f1 - int1/icebp | |
148 | * f4 - hlt | |
149 | * fa, fb - cli, sti | |
150 | * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2 | |
2b144498 SD |
151 | * |
152 | * invalid opcodes in 64-bit mode: | |
2b144498 | 153 | * |
7b2d81d4 IM |
154 | * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5 |
155 | * 63 - we support this opcode in x86_64 but not in i386. | |
2b144498 SD |
156 | * |
157 | * opcodes we may need to refine support for: | |
7b2d81d4 IM |
158 | * |
159 | * 0f - 2-byte instructions: For many of these instructions, the validity | |
160 | * depends on the prefix and/or the reg field. On such instructions, we | |
161 | * just consider the opcode combination valid if it corresponds to any | |
162 | * valid instruction. | |
163 | * | |
164 | * 8f - Group 1 - only reg = 0 is OK | |
165 | * c6-c7 - Group 11 - only reg = 0 is OK | |
166 | * d9-df - fpu insns with some illegal encodings | |
167 | * f2, f3 - repnz, repz prefixes. These are also the first byte for | |
168 | * certain floating-point instructions, such as addsd. | |
169 | * | |
170 | * fe - Group 4 - only reg = 0 or 1 is OK | |
171 | * ff - Group 5 - only reg = 0-6 is OK | |
2b144498 SD |
172 | * |
173 | * others -- Do we need to support these? | |
7b2d81d4 IM |
174 | * |
175 | * 0f - (floating-point?) prefetch instructions | |
176 | * 07, 17, 1f - pop es, pop ss, pop ds | |
177 | * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- | |
2b144498 | 178 | * but 64 and 65 (fs: and gs:) seem to be used, so we support them |
7b2d81d4 IM |
179 | * 67 - addr16 prefix |
180 | * ce - into | |
181 | * f0 - lock prefix | |
2b144498 SD |
182 | */ |
183 | ||
184 | /* | |
185 | * TODO: | |
186 | * - Where necessary, examine the modrm byte and allow only valid instructions | |
187 | * in the different Groups and fpu instructions. | |
188 | */ | |
189 | ||
190 | static bool is_prefix_bad(struct insn *insn) | |
191 | { | |
192 | int i; | |
193 | ||
194 | for (i = 0; i < insn->prefixes.nbytes; i++) { | |
195 | switch (insn->prefixes.bytes[i]) { | |
7b2d81d4 IM |
196 | case 0x26: /* INAT_PFX_ES */ |
197 | case 0x2E: /* INAT_PFX_CS */ | |
198 | case 0x36: /* INAT_PFX_DS */ | |
199 | case 0x3E: /* INAT_PFX_SS */ | |
200 | case 0xF0: /* INAT_PFX_LOCK */ | |
2b144498 SD |
201 | return true; |
202 | } | |
203 | } | |
204 | return false; | |
205 | } | |
206 | ||
73175d0d | 207 | static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) |
2b144498 | 208 | { |
73175d0d ON |
209 | u32 volatile *good_insns; |
210 | ||
211 | insn_init(insn, auprobe->insn, x86_64); | |
2b144498 | 212 | |
2b144498 SD |
213 | insn_get_opcode(insn); |
214 | if (is_prefix_bad(insn)) | |
215 | return -ENOTSUPP; | |
7b2d81d4 | 216 | |
73175d0d ON |
217 | if (x86_64) |
218 | good_insns = good_insns_64; | |
219 | else | |
220 | good_insns = good_insns_32; | |
221 | ||
222 | if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) | |
2b144498 | 223 | return 0; |
7b2d81d4 | 224 | |
2b144498 SD |
225 | if (insn->opcode.nbytes == 2) { |
226 | if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) | |
227 | return 0; | |
228 | } | |
7b2d81d4 | 229 | |
2b144498 SD |
230 | return -ENOTSUPP; |
231 | } | |
232 | ||
2b144498 | 233 | #ifdef CONFIG_X86_64 |
2ae1f49a ON |
234 | static inline bool is_64bit_mm(struct mm_struct *mm) |
235 | { | |
236 | return !config_enabled(CONFIG_IA32_EMULATION) || | |
237 | !mm->context.ia32_compat; | |
238 | } | |
2b144498 | 239 | /* |
3ff54efd | 240 | * If arch_uprobe->insn doesn't use rip-relative addressing, return |
2b144498 SD |
241 | * immediately. Otherwise, rewrite the instruction so that it accesses |
242 | * its memory operand indirectly through a scratch register. Set | |
3ff54efd | 243 | * arch_uprobe->fixups and arch_uprobe->rip_rela_target_address |
2b144498 SD |
244 | * accordingly. (The contents of the scratch register will be saved |
245 | * before we single-step the modified instruction, and restored | |
246 | * afterward.) | |
247 | * | |
248 | * We do this because a rip-relative instruction can access only a | |
249 | * relatively small area (+/- 2 GB from the instruction), and the XOL | |
250 | * area typically lies beyond that area. At least for instructions | |
251 | * that store to memory, we can't execute the original instruction | |
252 | * and "fix things up" later, because the misdirected store could be | |
253 | * disastrous. | |
254 | * | |
255 | * Some useful facts about rip-relative instructions: | |
7b2d81d4 IM |
256 | * |
257 | * - There's always a modrm byte. | |
258 | * - There's never a SIB byte. | |
259 | * - The displacement is always 4 bytes. | |
2b144498 | 260 | */ |
e3343e6a | 261 | static void |
59078d4b | 262 | handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 SD |
263 | { |
264 | u8 *cursor; | |
265 | u8 reg; | |
266 | ||
2b144498 SD |
267 | if (!insn_rip_relative(insn)) |
268 | return; | |
269 | ||
270 | /* | |
271 | * insn_rip_relative() would have decoded rex_prefix, modrm. | |
272 | * Clear REX.b bit (extension of MODRM.rm field): | |
273 | * we want to encode rax/rcx, not r8/r9. | |
274 | */ | |
275 | if (insn->rex_prefix.nbytes) { | |
3ff54efd | 276 | cursor = auprobe->insn + insn_offset_rex_prefix(insn); |
2b144498 SD |
277 | *cursor &= 0xfe; /* Clearing REX.B bit */ |
278 | } | |
279 | ||
280 | /* | |
281 | * Point cursor at the modrm byte. The next 4 bytes are the | |
282 | * displacement. Beyond the displacement, for some instructions, | |
283 | * is the immediate operand. | |
284 | */ | |
3ff54efd | 285 | cursor = auprobe->insn + insn_offset_modrm(insn); |
2b144498 SD |
286 | insn_get_length(insn); |
287 | ||
288 | /* | |
289 | * Convert from rip-relative addressing to indirect addressing | |
290 | * via a scratch register. Change the r/m field from 0x5 (%rip) | |
291 | * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field. | |
292 | */ | |
293 | reg = MODRM_REG(insn); | |
294 | if (reg == 0) { | |
295 | /* | |
296 | * The register operand (if any) is either the A register | |
297 | * (%rax, %eax, etc.) or (if the 0x4 bit is set in the | |
298 | * REX prefix) %r8. In any case, we know the C register | |
299 | * is NOT the register operand, so we use %rcx (register | |
300 | * #1) for the scratch register. | |
301 | */ | |
900771a4 | 302 | auprobe->fixups = UPROBE_FIX_RIP_CX; |
2b144498 SD |
303 | /* Change modrm from 00 000 101 to 00 000 001. */ |
304 | *cursor = 0x1; | |
305 | } else { | |
306 | /* Use %rax (register #0) for the scratch register. */ | |
900771a4 | 307 | auprobe->fixups = UPROBE_FIX_RIP_AX; |
2b144498 SD |
308 | /* Change modrm from 00 xxx 101 to 00 xxx 000 */ |
309 | *cursor = (reg << 3); | |
310 | } | |
311 | ||
312 | /* Target address = address of next instruction + (signed) offset */ | |
3ff54efd | 313 | auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value; |
7b2d81d4 | 314 | |
2b144498 SD |
315 | /* Displacement field is gone; slide immediate field (if any) over. */ |
316 | if (insn->immediate.nbytes) { | |
317 | cursor++; | |
7b2d81d4 | 318 | memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes); |
2b144498 | 319 | } |
2b144498 SD |
320 | } |
321 | ||
d20737c0 ON |
322 | /* |
323 | * If we're emulating a rip-relative instruction, save the contents | |
324 | * of the scratch register and store the target address in that register. | |
325 | */ | |
326 | static void | |
327 | pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
328 | struct arch_uprobe_task *autask) | |
329 | { | |
330 | if (auprobe->fixups & UPROBE_FIX_RIP_AX) { | |
331 | autask->saved_scratch_register = regs->ax; | |
332 | regs->ax = current->utask->vaddr; | |
333 | regs->ax += auprobe->rip_rela_target_address; | |
334 | } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) { | |
335 | autask->saved_scratch_register = regs->cx; | |
336 | regs->cx = current->utask->vaddr; | |
337 | regs->cx += auprobe->rip_rela_target_address; | |
338 | } | |
339 | } | |
340 | ||
341 | static void | |
342 | handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) | |
343 | { | |
344 | if (auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) { | |
345 | struct arch_uprobe_task *autask; | |
346 | ||
347 | autask = ¤t->utask->autask; | |
348 | if (auprobe->fixups & UPROBE_FIX_RIP_AX) | |
349 | regs->ax = autask->saved_scratch_register; | |
350 | else | |
351 | regs->cx = autask->saved_scratch_register; | |
352 | ||
353 | /* | |
354 | * The original instruction includes a displacement, and so | |
355 | * is 4 bytes longer than what we've just single-stepped. | |
356 | * Caller may need to apply other fixups to handle stuff | |
357 | * like "jmpq *...(%rip)" and "callq *...(%rip)". | |
358 | */ | |
359 | if (correction) | |
360 | *correction += 4; | |
361 | } | |
362 | } | |
2ae1f49a ON |
363 | #else /* 32-bit: */ |
364 | static inline bool is_64bit_mm(struct mm_struct *mm) | |
2b144498 | 365 | { |
2ae1f49a | 366 | return false; |
2b144498 | 367 | } |
d20737c0 ON |
368 | /* |
369 | * No RIP-relative addressing on 32-bit | |
370 | */ | |
59078d4b | 371 | static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 | 372 | { |
d20737c0 ON |
373 | } |
374 | static void pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
375 | struct arch_uprobe_task *autask) | |
376 | { | |
377 | } | |
378 | static void handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
379 | long *correction) | |
380 | { | |
2b144498 | 381 | } |
2b144498 SD |
382 | #endif /* CONFIG_X86_64 */ |
383 | ||
8ad8e9d3 ON |
384 | struct uprobe_xol_ops { |
385 | bool (*emulate)(struct arch_uprobe *, struct pt_regs *); | |
386 | int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); | |
387 | int (*post_xol)(struct arch_uprobe *, struct pt_regs *); | |
388 | }; | |
389 | ||
8faaed1b ON |
390 | static inline int sizeof_long(void) |
391 | { | |
392 | return is_ia32_task() ? 4 : 8; | |
393 | } | |
394 | ||
8ad8e9d3 ON |
395 | static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
396 | { | |
397 | pre_xol_rip_insn(auprobe, regs, ¤t->utask->autask); | |
398 | return 0; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Adjust the return address pushed by a call insn executed out of line. | |
403 | */ | |
404 | static int adjust_ret_addr(unsigned long sp, long correction) | |
405 | { | |
8faaed1b ON |
406 | int rasize = sizeof_long(); |
407 | long ra; | |
8ad8e9d3 | 408 | |
8faaed1b | 409 | if (copy_from_user(&ra, (void __user *)sp, rasize)) |
8ad8e9d3 ON |
410 | return -EFAULT; |
411 | ||
412 | ra += correction; | |
8faaed1b | 413 | if (copy_to_user((void __user *)sp, &ra, rasize)) |
8ad8e9d3 ON |
414 | return -EFAULT; |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
420 | { | |
421 | struct uprobe_task *utask = current->utask; | |
422 | long correction = (long)(utask->vaddr - utask->xol_vaddr); | |
8ad8e9d3 ON |
423 | |
424 | handle_riprel_post_xol(auprobe, regs, &correction); | |
425 | if (auprobe->fixups & UPROBE_FIX_IP) | |
426 | regs->ip += correction; | |
427 | ||
75f9ef0b ON |
428 | if (auprobe->fixups & UPROBE_FIX_CALL) { |
429 | if (adjust_ret_addr(regs->sp, correction)) { | |
8faaed1b | 430 | regs->sp += sizeof_long(); |
75f9ef0b ON |
431 | return -ERESTART; |
432 | } | |
433 | } | |
8ad8e9d3 | 434 | |
75f9ef0b | 435 | return 0; |
8ad8e9d3 ON |
436 | } |
437 | ||
438 | static struct uprobe_xol_ops default_xol_ops = { | |
439 | .pre_xol = default_pre_xol_op, | |
440 | .post_xol = default_post_xol_op, | |
441 | }; | |
442 | ||
8e89c0be ON |
443 | static bool branch_is_call(struct arch_uprobe *auprobe) |
444 | { | |
445 | return auprobe->branch.opc1 == 0xe8; | |
446 | } | |
447 | ||
8f95505b ON |
448 | #define CASE_COND \ |
449 | COND(70, 71, XF(OF)) \ | |
450 | COND(72, 73, XF(CF)) \ | |
451 | COND(74, 75, XF(ZF)) \ | |
452 | COND(78, 79, XF(SF)) \ | |
453 | COND(7a, 7b, XF(PF)) \ | |
454 | COND(76, 77, XF(CF) || XF(ZF)) \ | |
455 | COND(7c, 7d, XF(SF) != XF(OF)) \ | |
456 | COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) | |
457 | ||
458 | #define COND(op_y, op_n, expr) \ | |
459 | case 0x ## op_y: DO((expr) != 0) \ | |
460 | case 0x ## op_n: DO((expr) == 0) | |
461 | ||
462 | #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) | |
463 | ||
464 | static bool is_cond_jmp_opcode(u8 opcode) | |
465 | { | |
466 | switch (opcode) { | |
467 | #define DO(expr) \ | |
468 | return true; | |
469 | CASE_COND | |
470 | #undef DO | |
471 | ||
472 | default: | |
473 | return false; | |
474 | } | |
475 | } | |
476 | ||
477 | static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
478 | { | |
479 | unsigned long flags = regs->flags; | |
480 | ||
481 | switch (auprobe->branch.opc1) { | |
482 | #define DO(expr) \ | |
483 | return expr; | |
484 | CASE_COND | |
485 | #undef DO | |
486 | ||
487 | default: /* not a conditional jmp */ | |
488 | return true; | |
489 | } | |
490 | } | |
491 | ||
492 | #undef XF | |
493 | #undef COND | |
494 | #undef CASE_COND | |
495 | ||
7ba6db2d ON |
496 | static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
497 | { | |
8e89c0be | 498 | unsigned long new_ip = regs->ip += auprobe->branch.ilen; |
8f95505b | 499 | unsigned long offs = (long)auprobe->branch.offs; |
8e89c0be ON |
500 | |
501 | if (branch_is_call(auprobe)) { | |
502 | unsigned long new_sp = regs->sp - sizeof_long(); | |
503 | /* | |
504 | * If it fails we execute this (mangled, see the comment in | |
505 | * branch_clear_offset) insn out-of-line. In the likely case | |
506 | * this should trigger the trap, and the probed application | |
507 | * should die or restart the same insn after it handles the | |
508 | * signal, arch_uprobe_post_xol() won't be even called. | |
509 | * | |
510 | * But there is corner case, see the comment in ->post_xol(). | |
511 | */ | |
512 | if (copy_to_user((void __user *)new_sp, &new_ip, sizeof_long())) | |
513 | return false; | |
514 | regs->sp = new_sp; | |
8f95505b ON |
515 | } else if (!check_jmp_cond(auprobe, regs)) { |
516 | offs = 0; | |
8e89c0be ON |
517 | } |
518 | ||
8f95505b | 519 | regs->ip = new_ip + offs; |
7ba6db2d ON |
520 | return true; |
521 | } | |
522 | ||
8e89c0be ON |
523 | static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) |
524 | { | |
525 | BUG_ON(!branch_is_call(auprobe)); | |
526 | /* | |
527 | * We can only get here if branch_emulate_op() failed to push the ret | |
528 | * address _and_ another thread expanded our stack before the (mangled) | |
529 | * "call" insn was executed out-of-line. Just restore ->sp and restart. | |
530 | * We could also restore ->ip and try to call branch_emulate_op() again. | |
531 | */ | |
532 | regs->sp += sizeof_long(); | |
533 | return -ERESTART; | |
534 | } | |
535 | ||
536 | static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) | |
537 | { | |
538 | /* | |
539 | * Turn this insn into "call 1f; 1:", this is what we will execute | |
540 | * out-of-line if ->emulate() fails. We only need this to generate | |
541 | * a trap, so that the probed task receives the correct signal with | |
542 | * the properly filled siginfo. | |
543 | * | |
544 | * But see the comment in ->post_xol(), in the unlikely case it can | |
545 | * succeed. So we need to ensure that the new ->ip can not fall into | |
546 | * the non-canonical area and trigger #GP. | |
547 | * | |
548 | * We could turn it into (say) "pushf", but then we would need to | |
549 | * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte | |
550 | * of ->insn[] for set_orig_insn(). | |
551 | */ | |
552 | memset(auprobe->insn + insn_offset_immediate(insn), | |
553 | 0, insn->immediate.nbytes); | |
554 | } | |
555 | ||
7ba6db2d ON |
556 | static struct uprobe_xol_ops branch_xol_ops = { |
557 | .emulate = branch_emulate_op, | |
8e89c0be | 558 | .post_xol = branch_post_xol_op, |
7ba6db2d ON |
559 | }; |
560 | ||
561 | /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ | |
562 | static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) | |
563 | { | |
8e89c0be | 564 | u8 opc1 = OPCODE1(insn); |
250bbd12 | 565 | int i; |
8e89c0be ON |
566 | |
567 | /* has the side-effect of processing the entire instruction */ | |
568 | insn_get_length(insn); | |
569 | if (WARN_ON_ONCE(!insn_complete(insn))) | |
570 | return -ENOEXEC; | |
7ba6db2d | 571 | |
8e89c0be | 572 | switch (opc1) { |
7ba6db2d ON |
573 | case 0xeb: /* jmp 8 */ |
574 | case 0xe9: /* jmp 32 */ | |
d2410063 | 575 | case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ |
7ba6db2d | 576 | break; |
8e89c0be ON |
577 | |
578 | case 0xe8: /* call relative */ | |
579 | branch_clear_offset(auprobe, insn); | |
580 | break; | |
8f95505b | 581 | |
6cc5e7ff ON |
582 | case 0x0f: |
583 | if (insn->opcode.nbytes != 2) | |
584 | return -ENOSYS; | |
585 | /* | |
586 | * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches | |
587 | * OPCODE1() of the "short" jmp which checks the same condition. | |
588 | */ | |
589 | opc1 = OPCODE2(insn) - 0x10; | |
7ba6db2d | 590 | default: |
8f95505b ON |
591 | if (!is_cond_jmp_opcode(opc1)) |
592 | return -ENOSYS; | |
7ba6db2d ON |
593 | } |
594 | ||
250bbd12 DV |
595 | /* |
596 | * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported. | |
597 | * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix. | |
598 | * No one uses these insns, reject any branch insns with such prefix. | |
599 | */ | |
600 | for (i = 0; i < insn->prefixes.nbytes; i++) { | |
601 | if (insn->prefixes.bytes[i] == 0x66) | |
602 | return -ENOTSUPP; | |
603 | } | |
604 | ||
8e89c0be | 605 | auprobe->branch.opc1 = opc1; |
7ba6db2d ON |
606 | auprobe->branch.ilen = insn->length; |
607 | auprobe->branch.offs = insn->immediate.value; | |
608 | ||
609 | auprobe->ops = &branch_xol_ops; | |
610 | return 0; | |
611 | } | |
612 | ||
2b144498 | 613 | /** |
0326f5a9 | 614 | * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. |
2b144498 | 615 | * @mm: the probed address space. |
3ff54efd | 616 | * @arch_uprobe: the probepoint information. |
7eb9ba5e | 617 | * @addr: virtual address at which to install the probepoint |
2b144498 SD |
618 | * Return 0 on success or a -ve number on error. |
619 | */ | |
7eb9ba5e | 620 | int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) |
2b144498 | 621 | { |
2b144498 | 622 | struct insn insn; |
ddb69f27 ON |
623 | bool fix_ip = true, fix_call = false; |
624 | int ret; | |
2b144498 | 625 | |
2ae1f49a | 626 | ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm)); |
ddb69f27 | 627 | if (ret) |
2b144498 | 628 | return ret; |
7b2d81d4 | 629 | |
7ba6db2d ON |
630 | ret = branch_setup_xol_ops(auprobe, &insn); |
631 | if (ret != -ENOSYS) | |
632 | return ret; | |
633 | ||
ddb69f27 ON |
634 | /* |
635 | * Figure out which fixups arch_uprobe_post_xol() will need to perform, | |
636 | * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups | |
637 | * is either zero or it reflects rip-related fixups. | |
638 | */ | |
ddb69f27 ON |
639 | switch (OPCODE1(&insn)) { |
640 | case 0x9d: /* popf */ | |
641 | auprobe->fixups |= UPROBE_FIX_SETF; | |
642 | break; | |
643 | case 0xc3: /* ret or lret -- ip is correct */ | |
644 | case 0xcb: | |
645 | case 0xc2: | |
646 | case 0xca: | |
647 | fix_ip = false; | |
648 | break; | |
ddb69f27 ON |
649 | case 0x9a: /* call absolute - Fix return addr, not ip */ |
650 | fix_call = true; | |
651 | fix_ip = false; | |
652 | break; | |
653 | case 0xea: /* jmp absolute -- ip is correct */ | |
654 | fix_ip = false; | |
655 | break; | |
656 | case 0xff: | |
657 | insn_get_modrm(&insn); | |
658 | switch (MODRM_REG(&insn)) { | |
659 | case 2: case 3: /* call or lcall, indirect */ | |
660 | fix_call = true; | |
661 | case 4: case 5: /* jmp or ljmp, indirect */ | |
662 | fix_ip = false; | |
663 | } | |
e55848a4 | 664 | /* fall through */ |
ddb69f27 | 665 | default: |
e55848a4 | 666 | handle_riprel_insn(auprobe, &insn); |
ddb69f27 ON |
667 | } |
668 | ||
669 | if (fix_ip) | |
670 | auprobe->fixups |= UPROBE_FIX_IP; | |
671 | if (fix_call) | |
672 | auprobe->fixups |= UPROBE_FIX_CALL; | |
7b2d81d4 | 673 | |
8ad8e9d3 | 674 | auprobe->ops = &default_xol_ops; |
2b144498 SD |
675 | return 0; |
676 | } | |
0326f5a9 | 677 | |
0326f5a9 SD |
678 | /* |
679 | * arch_uprobe_pre_xol - prepare to execute out of line. | |
680 | * @auprobe: the probepoint information. | |
681 | * @regs: reflects the saved user state of current task. | |
682 | */ | |
683 | int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
684 | { | |
34e7317d | 685 | struct uprobe_task *utask = current->utask; |
0326f5a9 | 686 | |
34e7317d ON |
687 | regs->ip = utask->xol_vaddr; |
688 | utask->autask.saved_trap_nr = current->thread.trap_nr; | |
0326f5a9 | 689 | current->thread.trap_nr = UPROBE_TRAP_NR; |
0326f5a9 | 690 | |
34e7317d | 691 | utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); |
4dc316c6 ON |
692 | regs->flags |= X86_EFLAGS_TF; |
693 | if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) | |
694 | set_task_blockstep(current, false); | |
695 | ||
8ad8e9d3 ON |
696 | if (auprobe->ops->pre_xol) |
697 | return auprobe->ops->pre_xol(auprobe, regs); | |
0326f5a9 SD |
698 | return 0; |
699 | } | |
700 | ||
0326f5a9 SD |
701 | /* |
702 | * If xol insn itself traps and generates a signal(Say, | |
703 | * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped | |
704 | * instruction jumps back to its own address. It is assumed that anything | |
705 | * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. | |
706 | * | |
707 | * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, | |
708 | * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to | |
709 | * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). | |
710 | */ | |
711 | bool arch_uprobe_xol_was_trapped(struct task_struct *t) | |
712 | { | |
713 | if (t->thread.trap_nr != UPROBE_TRAP_NR) | |
714 | return true; | |
715 | ||
716 | return false; | |
717 | } | |
718 | ||
719 | /* | |
720 | * Called after single-stepping. To avoid the SMP problems that can | |
721 | * occur when we temporarily put back the original opcode to | |
722 | * single-step, we single-stepped a copy of the instruction. | |
723 | * | |
724 | * This function prepares to resume execution after the single-step. | |
725 | * We have to fix things up as follows: | |
726 | * | |
727 | * Typically, the new ip is relative to the copied instruction. We need | |
728 | * to make it relative to the original instruction (FIX_IP). Exceptions | |
729 | * are return instructions and absolute or indirect jump or call instructions. | |
730 | * | |
731 | * If the single-stepped instruction was a call, the return address that | |
732 | * is atop the stack is the address following the copied instruction. We | |
733 | * need to make it the address following the original instruction (FIX_CALL). | |
734 | * | |
735 | * If the original instruction was a rip-relative instruction such as | |
736 | * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent | |
737 | * instruction using a scratch register -- e.g., "movl %edx,(%rax)". | |
738 | * We need to restore the contents of the scratch register and adjust | |
739 | * the ip, keeping in mind that the instruction we executed is 4 bytes | |
740 | * shorter than the original instruction (since we squeezed out the offset | |
741 | * field). (FIX_RIP_AX or FIX_RIP_CX) | |
742 | */ | |
743 | int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
744 | { | |
34e7317d | 745 | struct uprobe_task *utask = current->utask; |
0326f5a9 SD |
746 | |
747 | WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); | |
014940ba ON |
748 | |
749 | if (auprobe->ops->post_xol) { | |
750 | int err = auprobe->ops->post_xol(auprobe, regs); | |
751 | if (err) { | |
752 | arch_uprobe_abort_xol(auprobe, regs); | |
75f9ef0b ON |
753 | /* |
754 | * Restart the probed insn. ->post_xol() must ensure | |
755 | * this is really possible if it returns -ERESTART. | |
756 | */ | |
757 | if (err == -ERESTART) | |
758 | return 0; | |
014940ba ON |
759 | return err; |
760 | } | |
761 | } | |
762 | ||
0326f5a9 | 763 | current->thread.trap_nr = utask->autask.saved_trap_nr; |
4dc316c6 ON |
764 | /* |
765 | * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP | |
766 | * so we can get an extra SIGTRAP if we do not clear TF. We need | |
767 | * to examine the opcode to make it right. | |
768 | */ | |
769 | if (utask->autask.saved_tf) | |
770 | send_sig(SIGTRAP, current, 0); | |
771 | else if (!(auprobe->fixups & UPROBE_FIX_SETF)) | |
772 | regs->flags &= ~X86_EFLAGS_TF; | |
773 | ||
8ad8e9d3 | 774 | return 0; |
0326f5a9 SD |
775 | } |
776 | ||
777 | /* callback routine for handling exceptions. */ | |
778 | int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) | |
779 | { | |
780 | struct die_args *args = data; | |
781 | struct pt_regs *regs = args->regs; | |
782 | int ret = NOTIFY_DONE; | |
783 | ||
784 | /* We are only interested in userspace traps */ | |
785 | if (regs && !user_mode_vm(regs)) | |
786 | return NOTIFY_DONE; | |
787 | ||
788 | switch (val) { | |
789 | case DIE_INT3: | |
790 | if (uprobe_pre_sstep_notifier(regs)) | |
791 | ret = NOTIFY_STOP; | |
792 | ||
793 | break; | |
794 | ||
795 | case DIE_DEBUG: | |
796 | if (uprobe_post_sstep_notifier(regs)) | |
797 | ret = NOTIFY_STOP; | |
798 | ||
799 | default: | |
800 | break; | |
801 | } | |
802 | ||
803 | return ret; | |
804 | } | |
805 | ||
806 | /* | |
807 | * This function gets called when XOL instruction either gets trapped or | |
014940ba ON |
808 | * the thread has a fatal signal, or if arch_uprobe_post_xol() failed. |
809 | * Reset the instruction pointer to its probed address for the potential | |
810 | * restart or for post mortem analysis. | |
0326f5a9 SD |
811 | */ |
812 | void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
813 | { | |
814 | struct uprobe_task *utask = current->utask; | |
815 | ||
816 | current->thread.trap_nr = utask->autask.saved_trap_nr; | |
817 | handle_riprel_post_xol(auprobe, regs, NULL); | |
818 | instruction_pointer_set(regs, utask->vaddr); | |
4dc316c6 ON |
819 | |
820 | /* clear TF if it was set by us in arch_uprobe_pre_xol() */ | |
821 | if (!utask->autask.saved_tf) | |
822 | regs->flags &= ~X86_EFLAGS_TF; | |
0326f5a9 SD |
823 | } |
824 | ||
3a4664aa | 825 | static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
0326f5a9 | 826 | { |
8ad8e9d3 ON |
827 | if (auprobe->ops->emulate) |
828 | return auprobe->ops->emulate(auprobe, regs); | |
0326f5a9 SD |
829 | return false; |
830 | } | |
bdc1e472 | 831 | |
3a4664aa ON |
832 | bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
833 | { | |
834 | bool ret = __skip_sstep(auprobe, regs); | |
835 | if (ret && (regs->flags & X86_EFLAGS_TF)) | |
836 | send_sig(SIGTRAP, current, 0); | |
837 | return ret; | |
838 | } | |
791eca10 AA |
839 | |
840 | unsigned long | |
841 | arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) | |
842 | { | |
8faaed1b | 843 | int rasize = sizeof_long(), nleft; |
791eca10 AA |
844 | unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ |
845 | ||
8faaed1b | 846 | if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) |
791eca10 AA |
847 | return -1; |
848 | ||
849 | /* check whether address has been already hijacked */ | |
850 | if (orig_ret_vaddr == trampoline_vaddr) | |
851 | return orig_ret_vaddr; | |
852 | ||
8faaed1b ON |
853 | nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); |
854 | if (likely(!nleft)) | |
791eca10 AA |
855 | return orig_ret_vaddr; |
856 | ||
8faaed1b | 857 | if (nleft != rasize) { |
791eca10 AA |
858 | pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, " |
859 | "%%ip=%#lx\n", current->pid, regs->sp, regs->ip); | |
860 | ||
861 | force_sig_info(SIGSEGV, SEND_SIG_FORCED, current); | |
862 | } | |
863 | ||
864 | return -1; | |
865 | } |