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2b144498 | 1 | /* |
7b2d81d4 | 2 | * User-space Probes (UProbes) for x86 |
2b144498 SD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * Copyright (C) IBM Corporation, 2008-2011 | |
19 | * Authors: | |
20 | * Srikar Dronamraju | |
21 | * Jim Keniston | |
22 | */ | |
2b144498 SD |
23 | #include <linux/kernel.h> |
24 | #include <linux/sched.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/uprobes.h> | |
0326f5a9 | 27 | #include <linux/uaccess.h> |
2b144498 SD |
28 | |
29 | #include <linux/kdebug.h> | |
0326f5a9 | 30 | #include <asm/processor.h> |
2b144498 SD |
31 | #include <asm/insn.h> |
32 | ||
33 | /* Post-execution fixups. */ | |
34 | ||
35 | /* No fixup needed */ | |
0326f5a9 SD |
36 | #define UPROBE_FIX_NONE 0x0 |
37 | ||
2b144498 | 38 | /* Adjust IP back to vicinity of actual insn */ |
900771a4 | 39 | #define UPROBE_FIX_IP 0x1 |
0326f5a9 | 40 | |
2b144498 | 41 | /* Adjust the return address of a call insn */ |
900771a4 | 42 | #define UPROBE_FIX_CALL 0x2 |
2b144498 | 43 | |
bdc1e472 SAS |
44 | /* Instruction will modify TF, don't change it */ |
45 | #define UPROBE_FIX_SETF 0x4 | |
46 | ||
900771a4 SD |
47 | #define UPROBE_FIX_RIP_AX 0x8000 |
48 | #define UPROBE_FIX_RIP_CX 0x4000 | |
2b144498 | 49 | |
0326f5a9 SD |
50 | #define UPROBE_TRAP_NR UINT_MAX |
51 | ||
2b144498 | 52 | /* Adaptations for mhiramat x86 decoder v14. */ |
7b2d81d4 IM |
53 | #define OPCODE1(insn) ((insn)->opcode.bytes[0]) |
54 | #define OPCODE2(insn) ((insn)->opcode.bytes[1]) | |
55 | #define OPCODE3(insn) ((insn)->opcode.bytes[2]) | |
ddb69f27 | 56 | #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) |
2b144498 SD |
57 | |
58 | #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ | |
59 | (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ | |
60 | (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ | |
61 | (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ | |
62 | (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ | |
63 | << (row % 32)) | |
64 | ||
04a3d984 SD |
65 | /* |
66 | * Good-instruction tables for 32-bit apps. This is non-const and volatile | |
67 | * to keep gcc from statically optimizing it out, as variable_test_bit makes | |
68 | * some versions of gcc to think only *(unsigned long*) is used. | |
69 | */ | |
70 | static volatile u32 good_insns_32[256 / 32] = { | |
2b144498 SD |
71 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
72 | /* ---------------------------------------------- */ | |
73 | W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */ | |
74 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ | |
75 | W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */ | |
76 | W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */ | |
77 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
78 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
79 | W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ | |
80 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ | |
81 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
82 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
83 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ | |
84 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
85 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ | |
86 | W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
87 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ | |
88 | W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ | |
89 | /* ---------------------------------------------- */ | |
90 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
91 | }; | |
92 | ||
93 | /* Using this for both 64-bit and 32-bit apps */ | |
04a3d984 | 94 | static volatile u32 good_2byte_insns[256 / 32] = { |
2b144498 SD |
95 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
96 | /* ---------------------------------------------- */ | |
97 | W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */ | |
98 | W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ | |
99 | W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ | |
100 | W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */ | |
101 | W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ | |
102 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
103 | W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ | |
104 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */ | |
105 | W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
106 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
107 | W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ | |
108 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
109 | W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ | |
110 | W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
111 | W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ | |
112 | W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */ | |
113 | /* ---------------------------------------------- */ | |
114 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
115 | }; | |
116 | ||
04a3d984 SD |
117 | #ifdef CONFIG_X86_64 |
118 | /* Good-instruction tables for 64-bit apps */ | |
119 | static volatile u32 good_insns_64[256 / 32] = { | |
120 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
121 | /* ---------------------------------------------- */ | |
122 | W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */ | |
123 | W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ | |
124 | W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */ | |
125 | W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */ | |
126 | W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */ | |
127 | W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ | |
128 | W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ | |
129 | W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ | |
130 | W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ | |
131 | W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ | |
132 | W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ | |
133 | W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ | |
134 | W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ | |
135 | W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ | |
136 | W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ | |
137 | W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ | |
138 | /* ---------------------------------------------- */ | |
139 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
140 | }; | |
141 | #endif | |
2b144498 SD |
142 | #undef W |
143 | ||
144 | /* | |
145 | * opcodes we'll probably never support: | |
7b2d81d4 IM |
146 | * |
147 | * 6c-6d, e4-e5, ec-ed - in | |
148 | * 6e-6f, e6-e7, ee-ef - out | |
149 | * cc, cd - int3, int | |
150 | * cf - iret | |
151 | * d6 - illegal instruction | |
152 | * f1 - int1/icebp | |
153 | * f4 - hlt | |
154 | * fa, fb - cli, sti | |
155 | * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2 | |
2b144498 SD |
156 | * |
157 | * invalid opcodes in 64-bit mode: | |
2b144498 | 158 | * |
7b2d81d4 IM |
159 | * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5 |
160 | * 63 - we support this opcode in x86_64 but not in i386. | |
2b144498 SD |
161 | * |
162 | * opcodes we may need to refine support for: | |
7b2d81d4 IM |
163 | * |
164 | * 0f - 2-byte instructions: For many of these instructions, the validity | |
165 | * depends on the prefix and/or the reg field. On such instructions, we | |
166 | * just consider the opcode combination valid if it corresponds to any | |
167 | * valid instruction. | |
168 | * | |
169 | * 8f - Group 1 - only reg = 0 is OK | |
170 | * c6-c7 - Group 11 - only reg = 0 is OK | |
171 | * d9-df - fpu insns with some illegal encodings | |
172 | * f2, f3 - repnz, repz prefixes. These are also the first byte for | |
173 | * certain floating-point instructions, such as addsd. | |
174 | * | |
175 | * fe - Group 4 - only reg = 0 or 1 is OK | |
176 | * ff - Group 5 - only reg = 0-6 is OK | |
2b144498 SD |
177 | * |
178 | * others -- Do we need to support these? | |
7b2d81d4 IM |
179 | * |
180 | * 0f - (floating-point?) prefetch instructions | |
181 | * 07, 17, 1f - pop es, pop ss, pop ds | |
182 | * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- | |
2b144498 | 183 | * but 64 and 65 (fs: and gs:) seem to be used, so we support them |
7b2d81d4 IM |
184 | * 67 - addr16 prefix |
185 | * ce - into | |
186 | * f0 - lock prefix | |
2b144498 SD |
187 | */ |
188 | ||
189 | /* | |
190 | * TODO: | |
191 | * - Where necessary, examine the modrm byte and allow only valid instructions | |
192 | * in the different Groups and fpu instructions. | |
193 | */ | |
194 | ||
195 | static bool is_prefix_bad(struct insn *insn) | |
196 | { | |
197 | int i; | |
198 | ||
199 | for (i = 0; i < insn->prefixes.nbytes; i++) { | |
200 | switch (insn->prefixes.bytes[i]) { | |
7b2d81d4 IM |
201 | case 0x26: /* INAT_PFX_ES */ |
202 | case 0x2E: /* INAT_PFX_CS */ | |
203 | case 0x36: /* INAT_PFX_DS */ | |
204 | case 0x3E: /* INAT_PFX_SS */ | |
205 | case 0xF0: /* INAT_PFX_LOCK */ | |
2b144498 SD |
206 | return true; |
207 | } | |
208 | } | |
209 | return false; | |
210 | } | |
211 | ||
3ff54efd | 212 | static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 | 213 | { |
3ff54efd | 214 | insn_init(insn, auprobe->insn, false); |
2b144498 SD |
215 | |
216 | /* Skip good instruction prefixes; reject "bad" ones. */ | |
217 | insn_get_opcode(insn); | |
218 | if (is_prefix_bad(insn)) | |
219 | return -ENOTSUPP; | |
7b2d81d4 | 220 | |
2b144498 SD |
221 | if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32)) |
222 | return 0; | |
7b2d81d4 | 223 | |
2b144498 SD |
224 | if (insn->opcode.nbytes == 2) { |
225 | if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) | |
226 | return 0; | |
227 | } | |
7b2d81d4 | 228 | |
2b144498 SD |
229 | return -ENOTSUPP; |
230 | } | |
231 | ||
2b144498 SD |
232 | #ifdef CONFIG_X86_64 |
233 | /* | |
3ff54efd | 234 | * If arch_uprobe->insn doesn't use rip-relative addressing, return |
2b144498 SD |
235 | * immediately. Otherwise, rewrite the instruction so that it accesses |
236 | * its memory operand indirectly through a scratch register. Set | |
3ff54efd | 237 | * arch_uprobe->fixups and arch_uprobe->rip_rela_target_address |
2b144498 SD |
238 | * accordingly. (The contents of the scratch register will be saved |
239 | * before we single-step the modified instruction, and restored | |
240 | * afterward.) | |
241 | * | |
242 | * We do this because a rip-relative instruction can access only a | |
243 | * relatively small area (+/- 2 GB from the instruction), and the XOL | |
244 | * area typically lies beyond that area. At least for instructions | |
245 | * that store to memory, we can't execute the original instruction | |
246 | * and "fix things up" later, because the misdirected store could be | |
247 | * disastrous. | |
248 | * | |
249 | * Some useful facts about rip-relative instructions: | |
7b2d81d4 IM |
250 | * |
251 | * - There's always a modrm byte. | |
252 | * - There's never a SIB byte. | |
253 | * - The displacement is always 4 bytes. | |
2b144498 | 254 | */ |
e3343e6a | 255 | static void |
59078d4b | 256 | handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 SD |
257 | { |
258 | u8 *cursor; | |
259 | u8 reg; | |
260 | ||
2b144498 SD |
261 | if (!insn_rip_relative(insn)) |
262 | return; | |
263 | ||
264 | /* | |
265 | * insn_rip_relative() would have decoded rex_prefix, modrm. | |
266 | * Clear REX.b bit (extension of MODRM.rm field): | |
267 | * we want to encode rax/rcx, not r8/r9. | |
268 | */ | |
269 | if (insn->rex_prefix.nbytes) { | |
3ff54efd | 270 | cursor = auprobe->insn + insn_offset_rex_prefix(insn); |
2b144498 SD |
271 | *cursor &= 0xfe; /* Clearing REX.B bit */ |
272 | } | |
273 | ||
274 | /* | |
275 | * Point cursor at the modrm byte. The next 4 bytes are the | |
276 | * displacement. Beyond the displacement, for some instructions, | |
277 | * is the immediate operand. | |
278 | */ | |
3ff54efd | 279 | cursor = auprobe->insn + insn_offset_modrm(insn); |
2b144498 SD |
280 | insn_get_length(insn); |
281 | ||
282 | /* | |
283 | * Convert from rip-relative addressing to indirect addressing | |
284 | * via a scratch register. Change the r/m field from 0x5 (%rip) | |
285 | * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field. | |
286 | */ | |
287 | reg = MODRM_REG(insn); | |
288 | if (reg == 0) { | |
289 | /* | |
290 | * The register operand (if any) is either the A register | |
291 | * (%rax, %eax, etc.) or (if the 0x4 bit is set in the | |
292 | * REX prefix) %r8. In any case, we know the C register | |
293 | * is NOT the register operand, so we use %rcx (register | |
294 | * #1) for the scratch register. | |
295 | */ | |
900771a4 | 296 | auprobe->fixups = UPROBE_FIX_RIP_CX; |
2b144498 SD |
297 | /* Change modrm from 00 000 101 to 00 000 001. */ |
298 | *cursor = 0x1; | |
299 | } else { | |
300 | /* Use %rax (register #0) for the scratch register. */ | |
900771a4 | 301 | auprobe->fixups = UPROBE_FIX_RIP_AX; |
2b144498 SD |
302 | /* Change modrm from 00 xxx 101 to 00 xxx 000 */ |
303 | *cursor = (reg << 3); | |
304 | } | |
305 | ||
306 | /* Target address = address of next instruction + (signed) offset */ | |
3ff54efd | 307 | auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value; |
7b2d81d4 | 308 | |
2b144498 SD |
309 | /* Displacement field is gone; slide immediate field (if any) over. */ |
310 | if (insn->immediate.nbytes) { | |
311 | cursor++; | |
7b2d81d4 | 312 | memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes); |
2b144498 | 313 | } |
2b144498 SD |
314 | } |
315 | ||
d20737c0 ON |
316 | /* |
317 | * If we're emulating a rip-relative instruction, save the contents | |
318 | * of the scratch register and store the target address in that register. | |
319 | */ | |
320 | static void | |
321 | pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
322 | struct arch_uprobe_task *autask) | |
323 | { | |
324 | if (auprobe->fixups & UPROBE_FIX_RIP_AX) { | |
325 | autask->saved_scratch_register = regs->ax; | |
326 | regs->ax = current->utask->vaddr; | |
327 | regs->ax += auprobe->rip_rela_target_address; | |
328 | } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) { | |
329 | autask->saved_scratch_register = regs->cx; | |
330 | regs->cx = current->utask->vaddr; | |
331 | regs->cx += auprobe->rip_rela_target_address; | |
332 | } | |
333 | } | |
334 | ||
335 | static void | |
336 | handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) | |
337 | { | |
338 | if (auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) { | |
339 | struct arch_uprobe_task *autask; | |
340 | ||
341 | autask = ¤t->utask->autask; | |
342 | if (auprobe->fixups & UPROBE_FIX_RIP_AX) | |
343 | regs->ax = autask->saved_scratch_register; | |
344 | else | |
345 | regs->cx = autask->saved_scratch_register; | |
346 | ||
347 | /* | |
348 | * The original instruction includes a displacement, and so | |
349 | * is 4 bytes longer than what we've just single-stepped. | |
350 | * Caller may need to apply other fixups to handle stuff | |
351 | * like "jmpq *...(%rip)" and "callq *...(%rip)". | |
352 | */ | |
353 | if (correction) | |
354 | *correction += 4; | |
355 | } | |
356 | } | |
357 | ||
3ff54efd | 358 | static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 | 359 | { |
3ff54efd | 360 | insn_init(insn, auprobe->insn, true); |
2b144498 SD |
361 | |
362 | /* Skip good instruction prefixes; reject "bad" ones. */ | |
363 | insn_get_opcode(insn); | |
364 | if (is_prefix_bad(insn)) | |
365 | return -ENOTSUPP; | |
7b2d81d4 | 366 | |
2b144498 SD |
367 | if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64)) |
368 | return 0; | |
7b2d81d4 | 369 | |
2b144498 SD |
370 | if (insn->opcode.nbytes == 2) { |
371 | if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) | |
372 | return 0; | |
373 | } | |
374 | return -ENOTSUPP; | |
375 | } | |
376 | ||
e3343e6a | 377 | static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) |
2b144498 SD |
378 | { |
379 | if (mm->context.ia32_compat) | |
3ff54efd SD |
380 | return validate_insn_32bits(auprobe, insn); |
381 | return validate_insn_64bits(auprobe, insn); | |
2b144498 | 382 | } |
7b2d81d4 | 383 | #else /* 32-bit: */ |
d20737c0 ON |
384 | /* |
385 | * No RIP-relative addressing on 32-bit | |
386 | */ | |
59078d4b | 387 | static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) |
2b144498 | 388 | { |
d20737c0 ON |
389 | } |
390 | static void pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
391 | struct arch_uprobe_task *autask) | |
392 | { | |
393 | } | |
394 | static void handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, | |
395 | long *correction) | |
396 | { | |
2b144498 SD |
397 | } |
398 | ||
e3343e6a | 399 | static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) |
2b144498 | 400 | { |
3ff54efd | 401 | return validate_insn_32bits(auprobe, insn); |
2b144498 SD |
402 | } |
403 | #endif /* CONFIG_X86_64 */ | |
404 | ||
405 | /** | |
0326f5a9 | 406 | * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. |
2b144498 | 407 | * @mm: the probed address space. |
3ff54efd | 408 | * @arch_uprobe: the probepoint information. |
7eb9ba5e | 409 | * @addr: virtual address at which to install the probepoint |
2b144498 SD |
410 | * Return 0 on success or a -ve number on error. |
411 | */ | |
7eb9ba5e | 412 | int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) |
2b144498 | 413 | { |
2b144498 | 414 | struct insn insn; |
ddb69f27 ON |
415 | bool fix_ip = true, fix_call = false; |
416 | int ret; | |
2b144498 | 417 | |
e3343e6a | 418 | ret = validate_insn_bits(auprobe, mm, &insn); |
ddb69f27 | 419 | if (ret) |
2b144498 | 420 | return ret; |
7b2d81d4 | 421 | |
ddb69f27 ON |
422 | /* |
423 | * Figure out which fixups arch_uprobe_post_xol() will need to perform, | |
424 | * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups | |
425 | * is either zero or it reflects rip-related fixups. | |
426 | */ | |
59078d4b | 427 | handle_riprel_insn(auprobe, &insn); |
ddb69f27 ON |
428 | |
429 | switch (OPCODE1(&insn)) { | |
430 | case 0x9d: /* popf */ | |
431 | auprobe->fixups |= UPROBE_FIX_SETF; | |
432 | break; | |
433 | case 0xc3: /* ret or lret -- ip is correct */ | |
434 | case 0xcb: | |
435 | case 0xc2: | |
436 | case 0xca: | |
437 | fix_ip = false; | |
438 | break; | |
439 | case 0xe8: /* call relative - Fix return addr */ | |
440 | fix_call = true; | |
441 | break; | |
442 | case 0x9a: /* call absolute - Fix return addr, not ip */ | |
443 | fix_call = true; | |
444 | fix_ip = false; | |
445 | break; | |
446 | case 0xea: /* jmp absolute -- ip is correct */ | |
447 | fix_ip = false; | |
448 | break; | |
449 | case 0xff: | |
450 | insn_get_modrm(&insn); | |
451 | switch (MODRM_REG(&insn)) { | |
452 | case 2: case 3: /* call or lcall, indirect */ | |
453 | fix_call = true; | |
454 | case 4: case 5: /* jmp or ljmp, indirect */ | |
455 | fix_ip = false; | |
456 | } | |
457 | break; | |
458 | default: | |
459 | break; | |
460 | } | |
461 | ||
462 | if (fix_ip) | |
463 | auprobe->fixups |= UPROBE_FIX_IP; | |
464 | if (fix_call) | |
465 | auprobe->fixups |= UPROBE_FIX_CALL; | |
7b2d81d4 | 466 | |
2b144498 SD |
467 | return 0; |
468 | } | |
0326f5a9 | 469 | |
0326f5a9 SD |
470 | /* |
471 | * arch_uprobe_pre_xol - prepare to execute out of line. | |
472 | * @auprobe: the probepoint information. | |
473 | * @regs: reflects the saved user state of current task. | |
474 | */ | |
475 | int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
476 | { | |
477 | struct arch_uprobe_task *autask; | |
478 | ||
479 | autask = ¤t->utask->autask; | |
480 | autask->saved_trap_nr = current->thread.trap_nr; | |
481 | current->thread.trap_nr = UPROBE_TRAP_NR; | |
482 | regs->ip = current->utask->xol_vaddr; | |
483 | pre_xol_rip_insn(auprobe, regs, autask); | |
484 | ||
4dc316c6 ON |
485 | autask->saved_tf = !!(regs->flags & X86_EFLAGS_TF); |
486 | regs->flags |= X86_EFLAGS_TF; | |
487 | if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) | |
488 | set_task_blockstep(current, false); | |
489 | ||
0326f5a9 SD |
490 | return 0; |
491 | } | |
492 | ||
493 | /* | |
494 | * This function is called by arch_uprobe_post_xol() to adjust the return | |
495 | * address pushed by a call instruction executed out of line. | |
496 | */ | |
497 | static int adjust_ret_addr(unsigned long sp, long correction) | |
498 | { | |
499 | int rasize, ncopied; | |
500 | long ra = 0; | |
501 | ||
502 | if (is_ia32_task()) | |
503 | rasize = 4; | |
504 | else | |
505 | rasize = 8; | |
506 | ||
507 | ncopied = copy_from_user(&ra, (void __user *)sp, rasize); | |
508 | if (unlikely(ncopied)) | |
509 | return -EFAULT; | |
510 | ||
511 | ra += correction; | |
512 | ncopied = copy_to_user((void __user *)sp, &ra, rasize); | |
513 | if (unlikely(ncopied)) | |
514 | return -EFAULT; | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
0326f5a9 SD |
519 | /* |
520 | * If xol insn itself traps and generates a signal(Say, | |
521 | * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped | |
522 | * instruction jumps back to its own address. It is assumed that anything | |
523 | * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. | |
524 | * | |
525 | * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, | |
526 | * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to | |
527 | * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). | |
528 | */ | |
529 | bool arch_uprobe_xol_was_trapped(struct task_struct *t) | |
530 | { | |
531 | if (t->thread.trap_nr != UPROBE_TRAP_NR) | |
532 | return true; | |
533 | ||
534 | return false; | |
535 | } | |
536 | ||
537 | /* | |
538 | * Called after single-stepping. To avoid the SMP problems that can | |
539 | * occur when we temporarily put back the original opcode to | |
540 | * single-step, we single-stepped a copy of the instruction. | |
541 | * | |
542 | * This function prepares to resume execution after the single-step. | |
543 | * We have to fix things up as follows: | |
544 | * | |
545 | * Typically, the new ip is relative to the copied instruction. We need | |
546 | * to make it relative to the original instruction (FIX_IP). Exceptions | |
547 | * are return instructions and absolute or indirect jump or call instructions. | |
548 | * | |
549 | * If the single-stepped instruction was a call, the return address that | |
550 | * is atop the stack is the address following the copied instruction. We | |
551 | * need to make it the address following the original instruction (FIX_CALL). | |
552 | * | |
553 | * If the original instruction was a rip-relative instruction such as | |
554 | * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent | |
555 | * instruction using a scratch register -- e.g., "movl %edx,(%rax)". | |
556 | * We need to restore the contents of the scratch register and adjust | |
557 | * the ip, keeping in mind that the instruction we executed is 4 bytes | |
558 | * shorter than the original instruction (since we squeezed out the offset | |
559 | * field). (FIX_RIP_AX or FIX_RIP_CX) | |
560 | */ | |
561 | int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
562 | { | |
563 | struct uprobe_task *utask; | |
564 | long correction; | |
565 | int result = 0; | |
566 | ||
567 | WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); | |
568 | ||
569 | utask = current->utask; | |
570 | current->thread.trap_nr = utask->autask.saved_trap_nr; | |
571 | correction = (long)(utask->vaddr - utask->xol_vaddr); | |
572 | handle_riprel_post_xol(auprobe, regs, &correction); | |
573 | if (auprobe->fixups & UPROBE_FIX_IP) | |
574 | regs->ip += correction; | |
575 | ||
576 | if (auprobe->fixups & UPROBE_FIX_CALL) | |
577 | result = adjust_ret_addr(regs->sp, correction); | |
578 | ||
4dc316c6 ON |
579 | /* |
580 | * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP | |
581 | * so we can get an extra SIGTRAP if we do not clear TF. We need | |
582 | * to examine the opcode to make it right. | |
583 | */ | |
584 | if (utask->autask.saved_tf) | |
585 | send_sig(SIGTRAP, current, 0); | |
586 | else if (!(auprobe->fixups & UPROBE_FIX_SETF)) | |
587 | regs->flags &= ~X86_EFLAGS_TF; | |
588 | ||
0326f5a9 SD |
589 | return result; |
590 | } | |
591 | ||
592 | /* callback routine for handling exceptions. */ | |
593 | int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) | |
594 | { | |
595 | struct die_args *args = data; | |
596 | struct pt_regs *regs = args->regs; | |
597 | int ret = NOTIFY_DONE; | |
598 | ||
599 | /* We are only interested in userspace traps */ | |
600 | if (regs && !user_mode_vm(regs)) | |
601 | return NOTIFY_DONE; | |
602 | ||
603 | switch (val) { | |
604 | case DIE_INT3: | |
605 | if (uprobe_pre_sstep_notifier(regs)) | |
606 | ret = NOTIFY_STOP; | |
607 | ||
608 | break; | |
609 | ||
610 | case DIE_DEBUG: | |
611 | if (uprobe_post_sstep_notifier(regs)) | |
612 | ret = NOTIFY_STOP; | |
613 | ||
614 | default: | |
615 | break; | |
616 | } | |
617 | ||
618 | return ret; | |
619 | } | |
620 | ||
621 | /* | |
622 | * This function gets called when XOL instruction either gets trapped or | |
623 | * the thread has a fatal signal, so reset the instruction pointer to its | |
624 | * probed address. | |
625 | */ | |
626 | void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) | |
627 | { | |
628 | struct uprobe_task *utask = current->utask; | |
629 | ||
630 | current->thread.trap_nr = utask->autask.saved_trap_nr; | |
631 | handle_riprel_post_xol(auprobe, regs, NULL); | |
632 | instruction_pointer_set(regs, utask->vaddr); | |
4dc316c6 ON |
633 | |
634 | /* clear TF if it was set by us in arch_uprobe_pre_xol() */ | |
635 | if (!utask->autask.saved_tf) | |
636 | regs->flags &= ~X86_EFLAGS_TF; | |
0326f5a9 SD |
637 | } |
638 | ||
639 | /* | |
640 | * Skip these instructions as per the currently known x86 ISA. | |
b64b9c93 | 641 | * rep=0x66*; nop=0x90 |
0326f5a9 | 642 | */ |
3a4664aa | 643 | static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
0326f5a9 SD |
644 | { |
645 | int i; | |
646 | ||
647 | for (i = 0; i < MAX_UINSN_BYTES; i++) { | |
b64b9c93 | 648 | if (auprobe->insn[i] == 0x66) |
0326f5a9 SD |
649 | continue; |
650 | ||
cf31ec3f | 651 | if (auprobe->insn[i] == 0x90) { |
cf31ec3f | 652 | regs->ip += i + 1; |
0326f5a9 | 653 | return true; |
cf31ec3f | 654 | } |
0326f5a9 | 655 | |
0326f5a9 SD |
656 | break; |
657 | } | |
658 | return false; | |
659 | } | |
bdc1e472 | 660 | |
3a4664aa ON |
661 | bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) |
662 | { | |
663 | bool ret = __skip_sstep(auprobe, regs); | |
664 | if (ret && (regs->flags & X86_EFLAGS_TF)) | |
665 | send_sig(SIGTRAP, current, 0); | |
666 | return ret; | |
667 | } | |
791eca10 AA |
668 | |
669 | unsigned long | |
670 | arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) | |
671 | { | |
672 | int rasize, ncopied; | |
673 | unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ | |
674 | ||
675 | rasize = is_ia32_task() ? 4 : 8; | |
676 | ncopied = copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize); | |
677 | if (unlikely(ncopied)) | |
678 | return -1; | |
679 | ||
680 | /* check whether address has been already hijacked */ | |
681 | if (orig_ret_vaddr == trampoline_vaddr) | |
682 | return orig_ret_vaddr; | |
683 | ||
684 | ncopied = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); | |
685 | if (likely(!ncopied)) | |
686 | return orig_ret_vaddr; | |
687 | ||
688 | if (ncopied != rasize) { | |
689 | pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, " | |
690 | "%%ip=%#lx\n", current->pid, regs->sp, regs->ip); | |
691 | ||
692 | force_sig_info(SIGSEGV, SEND_SIG_FORCED, current); | |
693 | } | |
694 | ||
695 | return -1; | |
696 | } |