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65253636 | 1 | /* |
26dd9fcf IM |
2 | * SGI Visual Workstation support and quirks, unmaintained. |
3 | * | |
65253636 | 4 | * Split out from setup.c by davej@suse.de |
26dd9fcf IM |
5 | * |
6 | * Copyright (C) 1999 Bent Hagemark, Ingo Molnar | |
7 | * | |
8 | * SGI Visual Workstation interrupt controller | |
9 | * | |
10 | * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC | |
11 | * which serves as the main interrupt controller in the system. Non-legacy | |
12 | * hardware in the system uses this controller directly. Legacy devices | |
13 | * are connected to the PIIX4 which in turn has its 8259(s) connected to | |
14 | * a of the Cobalt APIC entry. | |
15 | * | |
16 | * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com | |
17 | * | |
18 | * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru> | |
65253636 | 19 | */ |
65253636 IM |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/smp.h> | |
24 | ||
25 | #include <asm/visws/cobalt.h> | |
26 | #include <asm/visws/piix4.h> | |
27 | #include <asm/arch_hooks.h> | |
28 | #include <asm/fixmap.h> | |
29 | #include <asm/reboot.h> | |
30 | #include <asm/setup.h> | |
31 | #include <asm/e820.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/io.h> | |
34 | ||
35 | #include <mach_ipi.h> | |
36 | ||
37 | #include "mach_apic.h" | |
38 | ||
39 | #include <linux/init.h> | |
40 | #include <linux/smp.h> | |
41 | ||
26dd9fcf IM |
42 | #include <linux/kernel_stat.h> |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/init.h> | |
45 | ||
46 | #include <asm/io.h> | |
47 | #include <asm/apic.h> | |
48 | #include <asm/i8259.h> | |
49 | #include <asm/irq_vectors.h> | |
50 | #include <asm/visws/cobalt.h> | |
51 | #include <asm/visws/lithium.h> | |
52 | #include <asm/visws/piix4.h> | |
53 | ||
54 | #include <linux/sched.h> | |
55 | #include <linux/kernel.h> | |
56 | #include <linux/init.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/pci_ids.h> | |
59 | ||
f78cb9b1 IM |
60 | extern int no_broadcast; |
61 | ||
26dd9fcf IM |
62 | #include <asm/io.h> |
63 | #include <asm/apic.h> | |
64 | #include <asm/arch_hooks.h> | |
65 | #include <asm/visws/cobalt.h> | |
66 | #include <asm/visws/lithium.h> | |
67 | ||
65253636 IM |
68 | char visws_board_type = -1; |
69 | char visws_board_rev = -1; | |
70 | ||
71 | int is_visws_box(void) | |
72 | { | |
73 | return visws_board_type >= 0; | |
74 | } | |
75 | ||
76 | static int __init visws_time_init_quirk(void) | |
77 | { | |
78 | printk(KERN_INFO "Starting Cobalt Timer system clock\n"); | |
79 | ||
80 | /* Set the countdown value */ | |
81 | co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); | |
82 | ||
83 | /* Start the timer */ | |
84 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); | |
85 | ||
86 | /* Enable (unmask) the timer interrupt */ | |
87 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); | |
88 | ||
89 | /* | |
90 | * Zero return means the generic timer setup code will set up | |
91 | * the standard vector: | |
92 | */ | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int __init visws_pre_intr_init_quirk(void) | |
97 | { | |
98 | init_VISWS_APIC_irqs(); | |
99 | ||
100 | /* | |
101 | * We dont want ISA irqs to be set up by the generic code: | |
102 | */ | |
103 | return 1; | |
104 | } | |
105 | ||
106 | /* Quirk for machine specific memory setup. */ | |
107 | ||
108 | #define MB (1024 * 1024) | |
109 | ||
110 | unsigned long sgivwfb_mem_phys; | |
111 | unsigned long sgivwfb_mem_size; | |
112 | EXPORT_SYMBOL(sgivwfb_mem_phys); | |
113 | EXPORT_SYMBOL(sgivwfb_mem_size); | |
114 | ||
115 | long long mem_size __initdata = 0; | |
116 | ||
117 | static char * __init visws_memory_setup_quirk(void) | |
118 | { | |
119 | long long gfx_mem_size = 8 * MB; | |
120 | ||
121 | mem_size = boot_params.alt_mem_k; | |
122 | ||
123 | if (!mem_size) { | |
124 | printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n"); | |
125 | mem_size = 128 * MB; | |
126 | } | |
127 | ||
128 | /* | |
129 | * this hardcodes the graphics memory to 8 MB | |
130 | * it really should be sized dynamically (or at least | |
131 | * set as a boot param) | |
132 | */ | |
133 | if (!sgivwfb_mem_size) { | |
134 | printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n"); | |
135 | sgivwfb_mem_size = 8 * MB; | |
136 | } | |
137 | ||
138 | /* | |
139 | * Trim to nearest MB | |
140 | */ | |
141 | sgivwfb_mem_size &= ~((1 << 20) - 1); | |
142 | sgivwfb_mem_phys = mem_size - gfx_mem_size; | |
143 | ||
144 | e820_add_region(0, LOWMEMSIZE(), E820_RAM); | |
145 | e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM); | |
146 | e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED); | |
147 | ||
148 | return "PROM"; | |
149 | } | |
150 | ||
151 | static void visws_machine_emergency_restart(void) | |
152 | { | |
153 | /* | |
154 | * Visual Workstations restart after this | |
155 | * register is poked on the PIIX4 | |
156 | */ | |
157 | outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT); | |
158 | } | |
159 | ||
160 | static void visws_machine_power_off(void) | |
161 | { | |
162 | unsigned short pm_status; | |
163 | /* extern unsigned int pci_bus0; */ | |
164 | ||
165 | while ((pm_status = inw(PMSTS_PORT)) & 0x100) | |
166 | outw(pm_status, PMSTS_PORT); | |
167 | ||
168 | outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT); | |
169 | ||
170 | mdelay(10); | |
171 | ||
172 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ | |
173 | (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) | |
174 | ||
175 | /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */ | |
176 | outl(PIIX_SPECIAL_STOP, 0xCFC); | |
177 | } | |
178 | ||
179 | static int __init visws_get_smp_config_quirk(unsigned int early) | |
180 | { | |
181 | /* | |
182 | * Prevent MP-table parsing by the generic code: | |
183 | */ | |
184 | return 1; | |
185 | } | |
186 | ||
187 | extern unsigned int __cpuinitdata maxcpus; | |
188 | ||
189 | /* | |
190 | * The Visual Workstation is Intel MP compliant in the hardware | |
191 | * sense, but it doesn't have a BIOS(-configuration table). | |
192 | * No problem for Linux. | |
193 | */ | |
194 | ||
195 | static void __init MP_processor_info (struct mpc_config_processor *m) | |
196 | { | |
197 | int ver, logical_apicid; | |
198 | physid_mask_t apic_cpus; | |
199 | ||
200 | if (!(m->mpc_cpuflag & CPU_ENABLED)) | |
201 | return; | |
202 | ||
203 | logical_apicid = m->mpc_apicid; | |
204 | printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n", | |
205 | m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "", | |
206 | m->mpc_apicid, | |
207 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, | |
208 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, | |
209 | m->mpc_apicver); | |
210 | ||
211 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) | |
212 | boot_cpu_physical_apicid = m->mpc_apicid; | |
213 | ||
214 | ver = m->mpc_apicver; | |
215 | if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) { | |
216 | printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n", | |
217 | m->mpc_apicid, MAX_APICS); | |
218 | return; | |
219 | } | |
220 | ||
221 | apic_cpus = apicid_to_cpu_present(m->mpc_apicid); | |
222 | physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus); | |
223 | /* | |
224 | * Validate version | |
225 | */ | |
226 | if (ver == 0x0) { | |
227 | printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! " | |
228 | "fixing up to 0x10. (tell your hw vendor)\n", | |
229 | m->mpc_apicid); | |
230 | ver = 0x10; | |
231 | } | |
232 | apic_version[m->mpc_apicid] = ver; | |
233 | } | |
234 | ||
235 | int __init visws_find_smp_config_quirk(unsigned int reserve) | |
236 | { | |
237 | struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS); | |
238 | unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS)); | |
239 | ||
240 | if (ncpus > CO_CPU_MAX) { | |
241 | printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n", | |
242 | ncpus, mp); | |
243 | ||
244 | ncpus = CO_CPU_MAX; | |
245 | } | |
246 | ||
247 | if (ncpus > maxcpus) | |
248 | ncpus = maxcpus; | |
249 | ||
250 | #ifdef CONFIG_X86_LOCAL_APIC | |
251 | smp_found_config = 1; | |
252 | #endif | |
253 | while (ncpus--) | |
254 | MP_processor_info(mp++); | |
255 | ||
256 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
257 | ||
258 | return 1; | |
259 | } | |
260 | ||
261 | extern int visws_trap_init_quirk(void); | |
262 | ||
263 | void __init visws_early_detect(void) | |
264 | { | |
265 | int raw; | |
266 | ||
267 | visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) | |
268 | >> PIIX_GPI_BD_SHIFT; | |
269 | ||
270 | if (visws_board_type < 0) | |
271 | return; | |
272 | ||
273 | /* | |
274 | * Install special quirks for timer, interrupt and memory setup: | |
275 | */ | |
276 | arch_time_init_quirk = visws_time_init_quirk; | |
277 | arch_pre_intr_init_quirk = visws_pre_intr_init_quirk; | |
278 | arch_memory_setup_quirk = visws_memory_setup_quirk; | |
279 | ||
280 | /* | |
281 | * Fall back to generic behavior for traps: | |
282 | */ | |
283 | arch_intr_init_quirk = NULL; | |
284 | arch_trap_init_quirk = visws_trap_init_quirk; | |
285 | ||
286 | /* | |
287 | * Install reboot quirks: | |
288 | */ | |
289 | pm_power_off = visws_machine_power_off; | |
290 | machine_ops.emergency_restart = visws_machine_emergency_restart; | |
291 | ||
292 | /* | |
293 | * Do not use broadcast IPIs: | |
294 | */ | |
295 | no_broadcast = 0; | |
296 | ||
297 | /* | |
298 | * Override generic MP-table parsing: | |
299 | */ | |
300 | mach_get_smp_config_quirk = visws_get_smp_config_quirk; | |
301 | mach_find_smp_config_quirk = visws_find_smp_config_quirk; | |
302 | ||
54ce7f99 IM |
303 | #ifdef CONFIG_X86_IO_APIC |
304 | /* | |
305 | * Turn off IO-APIC detection and initialization: | |
306 | */ | |
307 | skip_ioapic_setup = 1; | |
308 | #endif | |
309 | ||
65253636 IM |
310 | /* |
311 | * Get Board rev. | |
312 | * First, we have to initialize the 307 part to allow us access | |
313 | * to the GPIO registers. Let's map them at 0x0fc0 which is right | |
314 | * after the PIIX4 PM section. | |
315 | */ | |
316 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
317 | outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
318 | ||
319 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
320 | outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ | |
321 | ||
322 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
323 | outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ | |
324 | ||
325 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
326 | outb_p(1, SIO_DATA); /* Enable GPIO registers. */ | |
327 | ||
328 | /* | |
329 | * Now, we have to map the power management section to write | |
330 | * a bit which enables access to the GPIO registers. | |
331 | * What lunatic came up with this shit? | |
332 | */ | |
333 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
334 | outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
335 | ||
336 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
337 | outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ | |
338 | ||
339 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
340 | outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ | |
341 | ||
342 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
343 | outb_p(1, SIO_DATA); /* Enable PM registers. */ | |
344 | ||
345 | /* | |
346 | * Now, write the PM register which enables the GPIO registers. | |
347 | */ | |
348 | outb_p(SIO_PM_FER2, SIO_PM_INDEX); | |
349 | outb_p(SIO_PM_GP_EN, SIO_PM_DATA); | |
350 | ||
351 | /* | |
352 | * Now, initialize the GPIO registers. | |
353 | * We want them all to be inputs which is the | |
354 | * power on default, so let's leave them alone. | |
355 | * So, let's just read the board rev! | |
356 | */ | |
357 | raw = inb_p(SIO_GP_DATA1); | |
358 | raw &= 0x7f; /* 7 bits of valid board revision ID. */ | |
359 | ||
360 | if (visws_board_type == VISWS_320) { | |
361 | if (raw < 0x6) { | |
362 | visws_board_rev = 4; | |
363 | } else if (raw < 0xc) { | |
364 | visws_board_rev = 5; | |
365 | } else { | |
366 | visws_board_rev = 6; | |
367 | } | |
368 | } else if (visws_board_type == VISWS_540) { | |
369 | visws_board_rev = 2; | |
370 | } else { | |
371 | visws_board_rev = raw; | |
372 | } | |
373 | ||
374 | printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n", | |
375 | (visws_board_type == VISWS_320 ? "320" : | |
376 | (visws_board_type == VISWS_540 ? "540" : | |
377 | "unknown")), visws_board_rev); | |
378 | } | |
26dd9fcf IM |
379 | |
380 | #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4) | |
381 | #define BCD (LI_INTB | LI_INTC | LI_INTD) | |
382 | #define ALLDEVS (A01234 | BCD) | |
383 | ||
384 | static __init void lithium_init(void) | |
385 | { | |
386 | set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS); | |
387 | set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS); | |
388 | ||
389 | if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
390 | (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
391 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A'); | |
392 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
393 | } | |
394 | ||
395 | if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
396 | (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
397 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B'); | |
398 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
399 | } | |
400 | ||
401 | li_pcia_write16(LI_PCI_INTEN, ALLDEVS); | |
402 | li_pcib_write16(LI_PCI_INTEN, ALLDEVS); | |
403 | } | |
404 | ||
405 | static __init void cobalt_init(void) | |
406 | { | |
407 | /* | |
408 | * On normal SMP PC this is used only with SMP, but we have to | |
409 | * use it and set it up here to start the Cobalt clock | |
410 | */ | |
411 | set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); | |
412 | setup_local_APIC(); | |
413 | printk(KERN_INFO "Local APIC Version %#x, ID %#x\n", | |
414 | (unsigned int)apic_read(APIC_LVR), | |
415 | (unsigned int)apic_read(APIC_ID)); | |
416 | ||
417 | set_fixmap(FIX_CO_CPU, CO_CPU_PHYS); | |
418 | set_fixmap(FIX_CO_APIC, CO_APIC_PHYS); | |
419 | printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n", | |
420 | co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID)); | |
421 | ||
422 | /* Enable Cobalt APIC being careful to NOT change the ID! */ | |
423 | co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE); | |
424 | ||
425 | printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n", | |
426 | co_apic_read(CO_APIC_ID)); | |
427 | } | |
428 | ||
429 | int __init visws_trap_init_quirk(void) | |
430 | { | |
431 | lithium_init(); | |
432 | cobalt_init(); | |
433 | ||
434 | return 1; | |
435 | } | |
436 | ||
437 | /* | |
438 | * IRQ controller / APIC support: | |
439 | */ | |
440 | ||
441 | static DEFINE_SPINLOCK(cobalt_lock); | |
442 | ||
443 | /* | |
444 | * Set the given Cobalt APIC Redirection Table entry to point | |
445 | * to the given IDT vector/index. | |
446 | */ | |
447 | static inline void co_apic_set(int entry, int irq) | |
448 | { | |
449 | co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR)); | |
450 | co_apic_write(CO_APIC_HI(entry), 0); | |
451 | } | |
452 | ||
453 | /* | |
454 | * Cobalt (IO)-APIC functions to handle PCI devices. | |
455 | */ | |
456 | static inline int co_apic_ide0_hack(void) | |
457 | { | |
458 | extern char visws_board_type; | |
459 | extern char visws_board_rev; | |
460 | ||
461 | if (visws_board_type == VISWS_320 && visws_board_rev == 5) | |
462 | return 5; | |
463 | return CO_APIC_IDE0; | |
464 | } | |
465 | ||
466 | static int is_co_apic(unsigned int irq) | |
467 | { | |
468 | if (IS_CO_APIC(irq)) | |
469 | return CO_APIC(irq); | |
470 | ||
471 | switch (irq) { | |
472 | case 0: return CO_APIC_CPU; | |
473 | case CO_IRQ_IDE0: return co_apic_ide0_hack(); | |
474 | case CO_IRQ_IDE1: return CO_APIC_IDE1; | |
475 | default: return -1; | |
476 | } | |
477 | } | |
478 | ||
479 | ||
480 | /* | |
481 | * This is the SGI Cobalt (IO-)APIC: | |
482 | */ | |
483 | ||
484 | static void enable_cobalt_irq(unsigned int irq) | |
485 | { | |
486 | co_apic_set(is_co_apic(irq), irq); | |
487 | } | |
488 | ||
489 | static void disable_cobalt_irq(unsigned int irq) | |
490 | { | |
491 | int entry = is_co_apic(irq); | |
492 | ||
493 | co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK); | |
494 | co_apic_read(CO_APIC_LO(entry)); | |
495 | } | |
496 | ||
497 | /* | |
498 | * "irq" really just serves to identify the device. Here is where we | |
499 | * map this to the Cobalt APIC entry where it's physically wired. | |
500 | * This is called via request_irq -> setup_irq -> irq_desc->startup() | |
501 | */ | |
502 | static unsigned int startup_cobalt_irq(unsigned int irq) | |
503 | { | |
504 | unsigned long flags; | |
505 | ||
506 | spin_lock_irqsave(&cobalt_lock, flags); | |
507 | if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING))) | |
508 | irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING); | |
509 | enable_cobalt_irq(irq); | |
510 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static void ack_cobalt_irq(unsigned int irq) | |
515 | { | |
516 | unsigned long flags; | |
517 | ||
518 | spin_lock_irqsave(&cobalt_lock, flags); | |
519 | disable_cobalt_irq(irq); | |
520 | apic_write(APIC_EOI, APIC_EIO_ACK); | |
521 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
522 | } | |
523 | ||
524 | static void end_cobalt_irq(unsigned int irq) | |
525 | { | |
526 | unsigned long flags; | |
527 | ||
528 | spin_lock_irqsave(&cobalt_lock, flags); | |
529 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
530 | enable_cobalt_irq(irq); | |
531 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
532 | } | |
533 | ||
534 | static struct irq_chip cobalt_irq_type = { | |
535 | .typename = "Cobalt-APIC", | |
536 | .startup = startup_cobalt_irq, | |
537 | .shutdown = disable_cobalt_irq, | |
538 | .enable = enable_cobalt_irq, | |
539 | .disable = disable_cobalt_irq, | |
540 | .ack = ack_cobalt_irq, | |
541 | .end = end_cobalt_irq, | |
542 | }; | |
543 | ||
544 | ||
545 | /* | |
546 | * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt | |
547 | * -- not the manner expected by the code in i8259.c. | |
548 | * | |
549 | * there is a 'master' physical interrupt source that gets sent to | |
550 | * the CPU. But in the chipset there are various 'virtual' interrupts | |
551 | * waiting to be handled. We represent this to Linux through a 'master' | |
552 | * interrupt controller type, and through a special virtual interrupt- | |
553 | * controller. Device drivers only see the virtual interrupt sources. | |
554 | */ | |
555 | static unsigned int startup_piix4_master_irq(unsigned int irq) | |
556 | { | |
557 | init_8259A(0); | |
558 | ||
559 | return startup_cobalt_irq(irq); | |
560 | } | |
561 | ||
562 | static void end_piix4_master_irq(unsigned int irq) | |
563 | { | |
564 | unsigned long flags; | |
565 | ||
566 | spin_lock_irqsave(&cobalt_lock, flags); | |
567 | enable_cobalt_irq(irq); | |
568 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
569 | } | |
570 | ||
571 | static struct irq_chip piix4_master_irq_type = { | |
572 | .typename = "PIIX4-master", | |
573 | .startup = startup_piix4_master_irq, | |
574 | .ack = ack_cobalt_irq, | |
575 | .end = end_piix4_master_irq, | |
576 | }; | |
577 | ||
578 | ||
579 | static struct irq_chip piix4_virtual_irq_type = { | |
580 | .typename = "PIIX4-virtual", | |
581 | .shutdown = disable_8259A_irq, | |
582 | .enable = enable_8259A_irq, | |
583 | .disable = disable_8259A_irq, | |
584 | }; | |
585 | ||
586 | ||
587 | /* | |
588 | * PIIX4-8259 master/virtual functions to handle interrupt requests | |
589 | * from legacy devices: floppy, parallel, serial, rtc. | |
590 | * | |
591 | * None of these get Cobalt APIC entries, neither do they have IDT | |
592 | * entries. These interrupts are purely virtual and distributed from | |
593 | * the 'master' interrupt source: CO_IRQ_8259. | |
594 | * | |
595 | * When the 8259 interrupts its handler figures out which of these | |
596 | * devices is interrupting and dispatches to its handler. | |
597 | * | |
598 | * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/ | |
599 | * enable_irq gets the right irq. This 'master' irq is never directly | |
600 | * manipulated by any driver. | |
601 | */ | |
602 | static irqreturn_t piix4_master_intr(int irq, void *dev_id) | |
603 | { | |
604 | int realirq; | |
605 | irq_desc_t *desc; | |
606 | unsigned long flags; | |
607 | ||
608 | spin_lock_irqsave(&i8259A_lock, flags); | |
609 | ||
610 | /* Find out what's interrupting in the PIIX4 master 8259 */ | |
611 | outb(0x0c, 0x20); /* OCW3 Poll command */ | |
612 | realirq = inb(0x20); | |
613 | ||
614 | /* | |
615 | * Bit 7 == 0 means invalid/spurious | |
616 | */ | |
617 | if (unlikely(!(realirq & 0x80))) | |
618 | goto out_unlock; | |
619 | ||
620 | realirq &= 7; | |
621 | ||
622 | if (unlikely(realirq == 2)) { | |
623 | outb(0x0c, 0xa0); | |
624 | realirq = inb(0xa0); | |
625 | ||
626 | if (unlikely(!(realirq & 0x80))) | |
627 | goto out_unlock; | |
628 | ||
629 | realirq = (realirq & 7) + 8; | |
630 | } | |
631 | ||
632 | /* mask and ack interrupt */ | |
633 | cached_irq_mask |= 1 << realirq; | |
634 | if (unlikely(realirq > 7)) { | |
635 | inb(0xa1); | |
636 | outb(cached_slave_mask, 0xa1); | |
637 | outb(0x60 + (realirq & 7), 0xa0); | |
638 | outb(0x60 + 2, 0x20); | |
639 | } else { | |
640 | inb(0x21); | |
641 | outb(cached_master_mask, 0x21); | |
642 | outb(0x60 + realirq, 0x20); | |
643 | } | |
644 | ||
645 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
646 | ||
647 | desc = irq_desc + realirq; | |
648 | ||
649 | /* | |
650 | * handle this 'virtual interrupt' as a Cobalt one now. | |
651 | */ | |
652 | kstat_cpu(smp_processor_id()).irqs[realirq]++; | |
653 | ||
654 | if (likely(desc->action != NULL)) | |
655 | handle_IRQ_event(realirq, desc->action); | |
656 | ||
657 | if (!(desc->status & IRQ_DISABLED)) | |
658 | enable_8259A_irq(realirq); | |
659 | ||
660 | return IRQ_HANDLED; | |
661 | ||
662 | out_unlock: | |
663 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
664 | return IRQ_NONE; | |
665 | } | |
666 | ||
667 | static struct irqaction master_action = { | |
668 | .handler = piix4_master_intr, | |
669 | .name = "PIIX4-8259", | |
670 | }; | |
671 | ||
672 | static struct irqaction cascade_action = { | |
673 | .handler = no_action, | |
674 | .name = "cascade", | |
675 | }; | |
676 | ||
677 | ||
678 | void init_VISWS_APIC_irqs(void) | |
679 | { | |
680 | int i; | |
681 | ||
682 | for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) { | |
683 | irq_desc[i].status = IRQ_DISABLED; | |
684 | irq_desc[i].action = 0; | |
685 | irq_desc[i].depth = 1; | |
686 | ||
687 | if (i == 0) { | |
688 | irq_desc[i].chip = &cobalt_irq_type; | |
689 | } | |
690 | else if (i == CO_IRQ_IDE0) { | |
691 | irq_desc[i].chip = &cobalt_irq_type; | |
692 | } | |
693 | else if (i == CO_IRQ_IDE1) { | |
694 | irq_desc[i].chip = &cobalt_irq_type; | |
695 | } | |
696 | else if (i == CO_IRQ_8259) { | |
697 | irq_desc[i].chip = &piix4_master_irq_type; | |
698 | } | |
699 | else if (i < CO_IRQ_APIC0) { | |
700 | irq_desc[i].chip = &piix4_virtual_irq_type; | |
701 | } | |
702 | else if (IS_CO_APIC(i)) { | |
703 | irq_desc[i].chip = &cobalt_irq_type; | |
704 | } | |
705 | } | |
706 | ||
707 | setup_irq(CO_IRQ_8259, &master_action); | |
708 | setup_irq(2, &cascade_action); | |
709 | } |