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Commit | Line | Data |
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65253636 | 1 | /* |
26dd9fcf IM |
2 | * SGI Visual Workstation support and quirks, unmaintained. |
3 | * | |
65253636 | 4 | * Split out from setup.c by davej@suse.de |
26dd9fcf IM |
5 | * |
6 | * Copyright (C) 1999 Bent Hagemark, Ingo Molnar | |
7 | * | |
8 | * SGI Visual Workstation interrupt controller | |
9 | * | |
10 | * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC | |
11 | * which serves as the main interrupt controller in the system. Non-legacy | |
12 | * hardware in the system uses this controller directly. Legacy devices | |
13 | * are connected to the PIIX4 which in turn has its 8259(s) connected to | |
14 | * a of the Cobalt APIC entry. | |
15 | * | |
16 | * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com | |
17 | * | |
18 | * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru> | |
65253636 | 19 | */ |
65253636 IM |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/smp.h> | |
24 | ||
25 | #include <asm/visws/cobalt.h> | |
26 | #include <asm/visws/piix4.h> | |
3964cd3a | 27 | #include <asm/io_apic.h> |
65253636 IM |
28 | #include <asm/fixmap.h> |
29 | #include <asm/reboot.h> | |
30 | #include <asm/setup.h> | |
e641f5f5 | 31 | #include <asm/apic.h> |
65253636 | 32 | #include <asm/e820.h> |
845b3944 | 33 | #include <asm/time.h> |
65253636 IM |
34 | #include <asm/io.h> |
35 | ||
26dd9fcf | 36 | #include <linux/kernel_stat.h> |
26dd9fcf | 37 | |
26dd9fcf IM |
38 | #include <asm/i8259.h> |
39 | #include <asm/irq_vectors.h> | |
26dd9fcf | 40 | #include <asm/visws/lithium.h> |
26dd9fcf IM |
41 | |
42 | #include <linux/sched.h> | |
43 | #include <linux/kernel.h> | |
26dd9fcf IM |
44 | #include <linux/pci.h> |
45 | #include <linux/pci_ids.h> | |
46 | ||
f78cb9b1 IM |
47 | extern int no_broadcast; |
48 | ||
65253636 IM |
49 | char visws_board_type = -1; |
50 | char visws_board_rev = -1; | |
51 | ||
52 | int is_visws_box(void) | |
53 | { | |
54 | return visws_board_type >= 0; | |
55 | } | |
56 | ||
845b3944 | 57 | static void __init visws_time_init(void) |
65253636 IM |
58 | { |
59 | printk(KERN_INFO "Starting Cobalt Timer system clock\n"); | |
60 | ||
61 | /* Set the countdown value */ | |
62 | co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); | |
63 | ||
64 | /* Start the timer */ | |
65 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); | |
66 | ||
67 | /* Enable (unmask) the timer interrupt */ | |
68 | co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); | |
69 | ||
845b3944 | 70 | setup_default_timer_irq(); |
65253636 IM |
71 | } |
72 | ||
d9112f43 TG |
73 | /* Replaces the default init_ISA_irqs in the generic setup */ |
74 | static void __init visws_pre_intr_init(void) | |
65253636 IM |
75 | { |
76 | init_VISWS_APIC_irqs(); | |
65253636 IM |
77 | } |
78 | ||
79 | /* Quirk for machine specific memory setup. */ | |
80 | ||
81 | #define MB (1024 * 1024) | |
82 | ||
83 | unsigned long sgivwfb_mem_phys; | |
84 | unsigned long sgivwfb_mem_size; | |
85 | EXPORT_SYMBOL(sgivwfb_mem_phys); | |
86 | EXPORT_SYMBOL(sgivwfb_mem_size); | |
87 | ||
88 | long long mem_size __initdata = 0; | |
89 | ||
3c9cb6de | 90 | static char * __init visws_memory_setup(void) |
65253636 IM |
91 | { |
92 | long long gfx_mem_size = 8 * MB; | |
93 | ||
94 | mem_size = boot_params.alt_mem_k; | |
95 | ||
96 | if (!mem_size) { | |
97 | printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n"); | |
98 | mem_size = 128 * MB; | |
99 | } | |
100 | ||
101 | /* | |
102 | * this hardcodes the graphics memory to 8 MB | |
103 | * it really should be sized dynamically (or at least | |
104 | * set as a boot param) | |
105 | */ | |
106 | if (!sgivwfb_mem_size) { | |
107 | printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n"); | |
108 | sgivwfb_mem_size = 8 * MB; | |
109 | } | |
110 | ||
111 | /* | |
112 | * Trim to nearest MB | |
113 | */ | |
114 | sgivwfb_mem_size &= ~((1 << 20) - 1); | |
115 | sgivwfb_mem_phys = mem_size - gfx_mem_size; | |
116 | ||
117 | e820_add_region(0, LOWMEMSIZE(), E820_RAM); | |
118 | e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM); | |
119 | e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED); | |
120 | ||
121 | return "PROM"; | |
122 | } | |
123 | ||
124 | static void visws_machine_emergency_restart(void) | |
125 | { | |
126 | /* | |
127 | * Visual Workstations restart after this | |
128 | * register is poked on the PIIX4 | |
129 | */ | |
130 | outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT); | |
131 | } | |
132 | ||
133 | static void visws_machine_power_off(void) | |
134 | { | |
135 | unsigned short pm_status; | |
136 | /* extern unsigned int pci_bus0; */ | |
137 | ||
138 | while ((pm_status = inw(PMSTS_PORT)) & 0x100) | |
139 | outw(pm_status, PMSTS_PORT); | |
140 | ||
141 | outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT); | |
142 | ||
143 | mdelay(10); | |
144 | ||
145 | #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ | |
146 | (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) | |
147 | ||
148 | /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */ | |
149 | outl(PIIX_SPECIAL_STOP, 0xCFC); | |
150 | } | |
151 | ||
b3f1b617 | 152 | static void __init visws_get_smp_config(unsigned int early) |
65253636 | 153 | { |
65253636 IM |
154 | } |
155 | ||
65253636 IM |
156 | /* |
157 | * The Visual Workstation is Intel MP compliant in the hardware | |
158 | * sense, but it doesn't have a BIOS(-configuration table). | |
159 | * No problem for Linux. | |
160 | */ | |
161 | ||
f4f21b71 | 162 | static void __init MP_processor_info(struct mpc_cpu *m) |
65253636 IM |
163 | { |
164 | int ver, logical_apicid; | |
165 | physid_mask_t apic_cpus; | |
166 | ||
c4563826 | 167 | if (!(m->cpuflag & CPU_ENABLED)) |
65253636 IM |
168 | return; |
169 | ||
c4563826 | 170 | logical_apicid = m->apicid; |
65253636 | 171 | printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n", |
c4563826 JSR |
172 | m->cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "", |
173 | m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8, | |
174 | (m->cpufeature & CPU_MODEL_MASK) >> 4, m->apicver); | |
65253636 | 175 | |
c4563826 JSR |
176 | if (m->cpuflag & CPU_BOOTPROCESSOR) |
177 | boot_cpu_physical_apicid = m->apicid; | |
65253636 | 178 | |
c4563826 JSR |
179 | ver = m->apicver; |
180 | if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) { | |
65253636 | 181 | printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n", |
c4563826 | 182 | m->apicid, MAX_APICS); |
65253636 IM |
183 | return; |
184 | } | |
185 | ||
8058714a | 186 | apic_cpus = apic->apicid_to_cpu_present(m->apicid); |
65253636 IM |
187 | physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus); |
188 | /* | |
189 | * Validate version | |
190 | */ | |
191 | if (ver == 0x0) { | |
192 | printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! " | |
193 | "fixing up to 0x10. (tell your hw vendor)\n", | |
c4563826 | 194 | m->apicid); |
65253636 IM |
195 | ver = 0x10; |
196 | } | |
c4563826 | 197 | apic_version[m->apicid] = ver; |
65253636 IM |
198 | } |
199 | ||
b3f1b617 | 200 | static void __init visws_find_smp_config(unsigned int reserve) |
65253636 | 201 | { |
f4f21b71 | 202 | struct mpc_cpu *mp = phys_to_virt(CO_CPU_TAB_PHYS); |
65253636 IM |
203 | unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS)); |
204 | ||
205 | if (ncpus > CO_CPU_MAX) { | |
206 | printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n", | |
207 | ncpus, mp); | |
208 | ||
209 | ncpus = CO_CPU_MAX; | |
210 | } | |
211 | ||
23b49c19 MK |
212 | if (ncpus > setup_max_cpus) |
213 | ncpus = setup_max_cpus; | |
65253636 IM |
214 | |
215 | #ifdef CONFIG_X86_LOCAL_APIC | |
216 | smp_found_config = 1; | |
217 | #endif | |
218 | while (ncpus--) | |
219 | MP_processor_info(mp++); | |
220 | ||
221 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
65253636 IM |
222 | } |
223 | ||
428cf902 | 224 | static void visws_trap_init(void); |
3c9cb6de | 225 | |
65253636 IM |
226 | void __init visws_early_detect(void) |
227 | { | |
228 | int raw; | |
229 | ||
230 | visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG) | |
231 | >> PIIX_GPI_BD_SHIFT; | |
232 | ||
233 | if (visws_board_type < 0) | |
234 | return; | |
235 | ||
236 | /* | |
845b3944 | 237 | * Override the default platform setup functions |
65253636 | 238 | */ |
6b18ae3e | 239 | x86_init.resources.memory_setup = visws_memory_setup; |
b3f1b617 TG |
240 | x86_init.mpparse.get_smp_config = visws_get_smp_config; |
241 | x86_init.mpparse.find_smp_config = visws_find_smp_config; | |
d9112f43 | 242 | x86_init.irqs.pre_vector_init = visws_pre_intr_init; |
428cf902 | 243 | x86_init.irqs.trap_init = visws_trap_init; |
845b3944 | 244 | x86_init.timers.timer_init = visws_time_init; |
6b18ae3e | 245 | |
65253636 IM |
246 | /* |
247 | * Install reboot quirks: | |
248 | */ | |
249 | pm_power_off = visws_machine_power_off; | |
250 | machine_ops.emergency_restart = visws_machine_emergency_restart; | |
251 | ||
252 | /* | |
253 | * Do not use broadcast IPIs: | |
254 | */ | |
255 | no_broadcast = 0; | |
256 | ||
54ce7f99 IM |
257 | #ifdef CONFIG_X86_IO_APIC |
258 | /* | |
259 | * Turn off IO-APIC detection and initialization: | |
260 | */ | |
261 | skip_ioapic_setup = 1; | |
262 | #endif | |
263 | ||
65253636 IM |
264 | /* |
265 | * Get Board rev. | |
266 | * First, we have to initialize the 307 part to allow us access | |
267 | * to the GPIO registers. Let's map them at 0x0fc0 which is right | |
268 | * after the PIIX4 PM section. | |
269 | */ | |
270 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
271 | outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
272 | ||
273 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
274 | outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */ | |
275 | ||
276 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
277 | outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */ | |
278 | ||
279 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
280 | outb_p(1, SIO_DATA); /* Enable GPIO registers. */ | |
281 | ||
282 | /* | |
283 | * Now, we have to map the power management section to write | |
284 | * a bit which enables access to the GPIO registers. | |
285 | * What lunatic came up with this shit? | |
286 | */ | |
287 | outb_p(SIO_DEV_SEL, SIO_INDEX); | |
288 | outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */ | |
289 | ||
290 | outb_p(SIO_DEV_MSB, SIO_INDEX); | |
291 | outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */ | |
292 | ||
293 | outb_p(SIO_DEV_LSB, SIO_INDEX); | |
294 | outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */ | |
295 | ||
296 | outb_p(SIO_DEV_ENB, SIO_INDEX); | |
297 | outb_p(1, SIO_DATA); /* Enable PM registers. */ | |
298 | ||
299 | /* | |
300 | * Now, write the PM register which enables the GPIO registers. | |
301 | */ | |
302 | outb_p(SIO_PM_FER2, SIO_PM_INDEX); | |
303 | outb_p(SIO_PM_GP_EN, SIO_PM_DATA); | |
304 | ||
305 | /* | |
306 | * Now, initialize the GPIO registers. | |
307 | * We want them all to be inputs which is the | |
308 | * power on default, so let's leave them alone. | |
309 | * So, let's just read the board rev! | |
310 | */ | |
311 | raw = inb_p(SIO_GP_DATA1); | |
312 | raw &= 0x7f; /* 7 bits of valid board revision ID. */ | |
313 | ||
314 | if (visws_board_type == VISWS_320) { | |
315 | if (raw < 0x6) { | |
316 | visws_board_rev = 4; | |
317 | } else if (raw < 0xc) { | |
318 | visws_board_rev = 5; | |
319 | } else { | |
320 | visws_board_rev = 6; | |
321 | } | |
322 | } else if (visws_board_type == VISWS_540) { | |
323 | visws_board_rev = 2; | |
324 | } else { | |
325 | visws_board_rev = raw; | |
326 | } | |
327 | ||
328 | printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n", | |
329 | (visws_board_type == VISWS_320 ? "320" : | |
330 | (visws_board_type == VISWS_540 ? "540" : | |
331 | "unknown")), visws_board_rev); | |
332 | } | |
26dd9fcf IM |
333 | |
334 | #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4) | |
335 | #define BCD (LI_INTB | LI_INTC | LI_INTD) | |
336 | #define ALLDEVS (A01234 | BCD) | |
337 | ||
338 | static __init void lithium_init(void) | |
339 | { | |
340 | set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS); | |
341 | set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS); | |
342 | ||
343 | if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
344 | (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
345 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A'); | |
346 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
347 | } | |
348 | ||
349 | if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) || | |
350 | (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) { | |
351 | printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B'); | |
352 | /* panic("This machine is not SGI Visual Workstation 320/540"); */ | |
353 | } | |
354 | ||
355 | li_pcia_write16(LI_PCI_INTEN, ALLDEVS); | |
356 | li_pcib_write16(LI_PCI_INTEN, ALLDEVS); | |
357 | } | |
358 | ||
359 | static __init void cobalt_init(void) | |
360 | { | |
361 | /* | |
362 | * On normal SMP PC this is used only with SMP, but we have to | |
363 | * use it and set it up here to start the Cobalt clock | |
364 | */ | |
365 | set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); | |
366 | setup_local_APIC(); | |
367 | printk(KERN_INFO "Local APIC Version %#x, ID %#x\n", | |
368 | (unsigned int)apic_read(APIC_LVR), | |
369 | (unsigned int)apic_read(APIC_ID)); | |
370 | ||
371 | set_fixmap(FIX_CO_CPU, CO_CPU_PHYS); | |
372 | set_fixmap(FIX_CO_APIC, CO_APIC_PHYS); | |
373 | printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n", | |
374 | co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID)); | |
375 | ||
376 | /* Enable Cobalt APIC being careful to NOT change the ID! */ | |
377 | co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE); | |
378 | ||
379 | printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n", | |
380 | co_apic_read(CO_APIC_ID)); | |
381 | } | |
382 | ||
428cf902 | 383 | static void __init visws_trap_init(void) |
26dd9fcf IM |
384 | { |
385 | lithium_init(); | |
386 | cobalt_init(); | |
26dd9fcf IM |
387 | } |
388 | ||
389 | /* | |
390 | * IRQ controller / APIC support: | |
391 | */ | |
392 | ||
393 | static DEFINE_SPINLOCK(cobalt_lock); | |
394 | ||
395 | /* | |
396 | * Set the given Cobalt APIC Redirection Table entry to point | |
397 | * to the given IDT vector/index. | |
398 | */ | |
399 | static inline void co_apic_set(int entry, int irq) | |
400 | { | |
401 | co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR)); | |
402 | co_apic_write(CO_APIC_HI(entry), 0); | |
403 | } | |
404 | ||
405 | /* | |
406 | * Cobalt (IO)-APIC functions to handle PCI devices. | |
407 | */ | |
408 | static inline int co_apic_ide0_hack(void) | |
409 | { | |
410 | extern char visws_board_type; | |
411 | extern char visws_board_rev; | |
412 | ||
413 | if (visws_board_type == VISWS_320 && visws_board_rev == 5) | |
414 | return 5; | |
415 | return CO_APIC_IDE0; | |
416 | } | |
417 | ||
418 | static int is_co_apic(unsigned int irq) | |
419 | { | |
420 | if (IS_CO_APIC(irq)) | |
421 | return CO_APIC(irq); | |
422 | ||
423 | switch (irq) { | |
424 | case 0: return CO_APIC_CPU; | |
425 | case CO_IRQ_IDE0: return co_apic_ide0_hack(); | |
426 | case CO_IRQ_IDE1: return CO_APIC_IDE1; | |
427 | default: return -1; | |
428 | } | |
429 | } | |
430 | ||
431 | ||
432 | /* | |
433 | * This is the SGI Cobalt (IO-)APIC: | |
434 | */ | |
435 | ||
436 | static void enable_cobalt_irq(unsigned int irq) | |
437 | { | |
438 | co_apic_set(is_co_apic(irq), irq); | |
439 | } | |
440 | ||
441 | static void disable_cobalt_irq(unsigned int irq) | |
442 | { | |
443 | int entry = is_co_apic(irq); | |
444 | ||
445 | co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK); | |
446 | co_apic_read(CO_APIC_LO(entry)); | |
447 | } | |
448 | ||
449 | /* | |
450 | * "irq" really just serves to identify the device. Here is where we | |
451 | * map this to the Cobalt APIC entry where it's physically wired. | |
452 | * This is called via request_irq -> setup_irq -> irq_desc->startup() | |
453 | */ | |
454 | static unsigned int startup_cobalt_irq(unsigned int irq) | |
455 | { | |
456 | unsigned long flags; | |
08678b08 | 457 | struct irq_desc *desc = irq_to_desc(irq); |
26dd9fcf IM |
458 | |
459 | spin_lock_irqsave(&cobalt_lock, flags); | |
08678b08 YL |
460 | if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING))) |
461 | desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING); | |
26dd9fcf IM |
462 | enable_cobalt_irq(irq); |
463 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
464 | return 0; | |
465 | } | |
466 | ||
467 | static void ack_cobalt_irq(unsigned int irq) | |
468 | { | |
469 | unsigned long flags; | |
470 | ||
471 | spin_lock_irqsave(&cobalt_lock, flags); | |
472 | disable_cobalt_irq(irq); | |
473 | apic_write(APIC_EOI, APIC_EIO_ACK); | |
474 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
475 | } | |
476 | ||
477 | static void end_cobalt_irq(unsigned int irq) | |
478 | { | |
479 | unsigned long flags; | |
08678b08 | 480 | struct irq_desc *desc = irq_to_desc(irq); |
26dd9fcf IM |
481 | |
482 | spin_lock_irqsave(&cobalt_lock, flags); | |
08678b08 | 483 | if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
26dd9fcf IM |
484 | enable_cobalt_irq(irq); |
485 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
486 | } | |
487 | ||
488 | static struct irq_chip cobalt_irq_type = { | |
489 | .typename = "Cobalt-APIC", | |
490 | .startup = startup_cobalt_irq, | |
491 | .shutdown = disable_cobalt_irq, | |
492 | .enable = enable_cobalt_irq, | |
493 | .disable = disable_cobalt_irq, | |
494 | .ack = ack_cobalt_irq, | |
495 | .end = end_cobalt_irq, | |
496 | }; | |
497 | ||
498 | ||
499 | /* | |
500 | * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt | |
501 | * -- not the manner expected by the code in i8259.c. | |
502 | * | |
503 | * there is a 'master' physical interrupt source that gets sent to | |
504 | * the CPU. But in the chipset there are various 'virtual' interrupts | |
505 | * waiting to be handled. We represent this to Linux through a 'master' | |
506 | * interrupt controller type, and through a special virtual interrupt- | |
507 | * controller. Device drivers only see the virtual interrupt sources. | |
508 | */ | |
509 | static unsigned int startup_piix4_master_irq(unsigned int irq) | |
510 | { | |
511 | init_8259A(0); | |
512 | ||
513 | return startup_cobalt_irq(irq); | |
514 | } | |
515 | ||
516 | static void end_piix4_master_irq(unsigned int irq) | |
517 | { | |
518 | unsigned long flags; | |
519 | ||
520 | spin_lock_irqsave(&cobalt_lock, flags); | |
521 | enable_cobalt_irq(irq); | |
522 | spin_unlock_irqrestore(&cobalt_lock, flags); | |
523 | } | |
524 | ||
525 | static struct irq_chip piix4_master_irq_type = { | |
526 | .typename = "PIIX4-master", | |
527 | .startup = startup_piix4_master_irq, | |
528 | .ack = ack_cobalt_irq, | |
529 | .end = end_piix4_master_irq, | |
530 | }; | |
531 | ||
532 | ||
533 | static struct irq_chip piix4_virtual_irq_type = { | |
534 | .typename = "PIIX4-virtual", | |
535 | .shutdown = disable_8259A_irq, | |
536 | .enable = enable_8259A_irq, | |
537 | .disable = disable_8259A_irq, | |
538 | }; | |
539 | ||
540 | ||
541 | /* | |
542 | * PIIX4-8259 master/virtual functions to handle interrupt requests | |
543 | * from legacy devices: floppy, parallel, serial, rtc. | |
544 | * | |
545 | * None of these get Cobalt APIC entries, neither do they have IDT | |
546 | * entries. These interrupts are purely virtual and distributed from | |
547 | * the 'master' interrupt source: CO_IRQ_8259. | |
548 | * | |
549 | * When the 8259 interrupts its handler figures out which of these | |
550 | * devices is interrupting and dispatches to its handler. | |
551 | * | |
552 | * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/ | |
553 | * enable_irq gets the right irq. This 'master' irq is never directly | |
554 | * manipulated by any driver. | |
555 | */ | |
556 | static irqreturn_t piix4_master_intr(int irq, void *dev_id) | |
557 | { | |
558 | int realirq; | |
bf5172d0 | 559 | struct irq_desc *desc; |
26dd9fcf IM |
560 | unsigned long flags; |
561 | ||
562 | spin_lock_irqsave(&i8259A_lock, flags); | |
563 | ||
564 | /* Find out what's interrupting in the PIIX4 master 8259 */ | |
565 | outb(0x0c, 0x20); /* OCW3 Poll command */ | |
566 | realirq = inb(0x20); | |
567 | ||
568 | /* | |
569 | * Bit 7 == 0 means invalid/spurious | |
570 | */ | |
571 | if (unlikely(!(realirq & 0x80))) | |
572 | goto out_unlock; | |
573 | ||
574 | realirq &= 7; | |
575 | ||
576 | if (unlikely(realirq == 2)) { | |
577 | outb(0x0c, 0xa0); | |
578 | realirq = inb(0xa0); | |
579 | ||
580 | if (unlikely(!(realirq & 0x80))) | |
581 | goto out_unlock; | |
582 | ||
583 | realirq = (realirq & 7) + 8; | |
584 | } | |
585 | ||
586 | /* mask and ack interrupt */ | |
587 | cached_irq_mask |= 1 << realirq; | |
588 | if (unlikely(realirq > 7)) { | |
589 | inb(0xa1); | |
590 | outb(cached_slave_mask, 0xa1); | |
591 | outb(0x60 + (realirq & 7), 0xa0); | |
592 | outb(0x60 + 2, 0x20); | |
593 | } else { | |
594 | inb(0x21); | |
595 | outb(cached_master_mask, 0x21); | |
596 | outb(0x60 + realirq, 0x20); | |
597 | } | |
598 | ||
599 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
600 | ||
08678b08 | 601 | desc = irq_to_desc(realirq); |
26dd9fcf IM |
602 | |
603 | /* | |
604 | * handle this 'virtual interrupt' as a Cobalt one now. | |
605 | */ | |
d6c88a50 | 606 | kstat_incr_irqs_this_cpu(realirq, desc); |
26dd9fcf IM |
607 | |
608 | if (likely(desc->action != NULL)) | |
609 | handle_IRQ_event(realirq, desc->action); | |
610 | ||
611 | if (!(desc->status & IRQ_DISABLED)) | |
612 | enable_8259A_irq(realirq); | |
613 | ||
614 | return IRQ_HANDLED; | |
615 | ||
616 | out_unlock: | |
617 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
618 | return IRQ_NONE; | |
619 | } | |
620 | ||
621 | static struct irqaction master_action = { | |
622 | .handler = piix4_master_intr, | |
623 | .name = "PIIX4-8259", | |
624 | }; | |
625 | ||
626 | static struct irqaction cascade_action = { | |
627 | .handler = no_action, | |
628 | .name = "cascade", | |
629 | }; | |
630 | ||
631 | ||
632 | void init_VISWS_APIC_irqs(void) | |
633 | { | |
634 | int i; | |
635 | ||
636 | for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) { | |
08678b08 YL |
637 | struct irq_desc *desc = irq_to_desc(i); |
638 | ||
639 | desc->status = IRQ_DISABLED; | |
640 | desc->action = 0; | |
641 | desc->depth = 1; | |
26dd9fcf IM |
642 | |
643 | if (i == 0) { | |
08678b08 | 644 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
645 | } |
646 | else if (i == CO_IRQ_IDE0) { | |
08678b08 | 647 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
648 | } |
649 | else if (i == CO_IRQ_IDE1) { | |
08678b08 | 650 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
651 | } |
652 | else if (i == CO_IRQ_8259) { | |
08678b08 | 653 | desc->chip = &piix4_master_irq_type; |
26dd9fcf IM |
654 | } |
655 | else if (i < CO_IRQ_APIC0) { | |
08678b08 | 656 | desc->chip = &piix4_virtual_irq_type; |
26dd9fcf IM |
657 | } |
658 | else if (IS_CO_APIC(i)) { | |
08678b08 | 659 | desc->chip = &cobalt_irq_type; |
26dd9fcf IM |
660 | } |
661 | } | |
662 | ||
663 | setup_irq(CO_IRQ_8259, &master_action); | |
664 | setup_irq(2, &cascade_action); | |
665 | } |