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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
17ce265d
SR
2/*
3 * ld script for the x86 kernel
4 *
5 * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
6 *
91fd7fe8
IM
7 * Modernisation, unification and other changes and fixes:
8 * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org>
17ce265d
SR
9 *
10 *
11 * Don't define absolute symbols until and unless you know that symbol
12 * value is should remain constant even if kernel image is relocated
13 * at run time. Absolute symbols are not relocated. If symbol value should
14 * change if kernel is relocated, make the symbol section relative and
15 * put it inside the section definition.
16 */
17
18#ifdef CONFIG_X86_32
19#define LOAD_OFFSET __PAGE_OFFSET
20#else
21#define LOAD_OFFSET __START_KERNEL_map
22#endif
23
84d5f77f 24#define RUNTIME_DISCARD_EXIT
441110a5 25#define EMITS_PT_NOTE
f0d7ee17 26#define RO_EXCEPTION_TABLE_ALIGN 16
441110a5 27
17ce265d
SR
28#include <asm-generic/vmlinux.lds.h>
29#include <asm/asm-offsets.h>
30#include <asm/thread_info.h>
31#include <asm/page_types.h>
ee9f8fce 32#include <asm/orc_lookup.h>
17ce265d
SR
33#include <asm/cache.h>
34#include <asm/boot.h>
35
36#undef i386 /* in case the preprocessor is a 32bit one */
37
e6d7bc0b 38OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT)
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39
40#ifdef CONFIG_X86_32
41OUTPUT_ARCH(i386)
42ENTRY(phys_startup_32)
17ce265d
SR
43#else
44OUTPUT_ARCH(i386:x86-64)
45ENTRY(phys_startup_64)
17ce265d
SR
46#endif
47
d8ad6d39
BH
48jiffies = jiffies_64;
49
9ccaf77c 50#if defined(CONFIG_X86_64)
d6cc1c3a 51/*
9ccaf77c
KC
52 * On 64-bit, align RODATA to 2MB so we retain large page mappings for
53 * boundaries spanning kernel text, rodata and data sections.
d6cc1c3a
SS
54 *
55 * However, kernel identity mappings will have different RWX permissions
56 * to the pages mapping to text and to the pages padding (which are freed) the
57 * text section. Hence kernel identity mappings will be broken to smaller
58 * pages. For 64-bit, kernel text and kernel identity mappings are different,
9ccaf77c
KC
59 * so we can enable protection checks as well as retain 2MB large page
60 * mappings for kernel text.
d6cc1c3a 61 */
39d668e0 62#define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE);
74e08179 63
39d668e0 64#define X86_ALIGN_RODATA_END \
74e08179 65 . = ALIGN(HPAGE_SIZE); \
39d668e0
JR
66 __end_rodata_hpage_align = .; \
67 __end_rodata_aligned = .;
74e08179 68
2f7412ba
TG
69#define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE);
70#define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE);
71
b3f0907c
BS
72/*
73 * This section contains data which will be mapped as decrypted. Memory
74 * encryption operates on a page basis. Make this section PMD-aligned
75 * to avoid splitting the pages while mapping the section early.
76 *
77 * Note: We use a separate section so that only this section gets
78 * decrypted to avoid exposing more than we wish.
79 */
80#define BSS_DECRYPTED \
81 . = ALIGN(PMD_SIZE); \
82 __start_bss_decrypted = .; \
83 *(.bss..decrypted); \
84 . = ALIGN(PAGE_SIZE); \
85 __start_bss_decrypted_unused = .; \
86 . = ALIGN(PMD_SIZE); \
87 __end_bss_decrypted = .; \
88
74e08179
SS
89#else
90
39d668e0
JR
91#define X86_ALIGN_RODATA_BEGIN
92#define X86_ALIGN_RODATA_END \
93 . = ALIGN(PAGE_SIZE); \
94 __end_rodata_aligned = .;
74e08179 95
2f7412ba
TG
96#define ALIGN_ENTRY_TEXT_BEGIN
97#define ALIGN_ENTRY_TEXT_END
b3f0907c 98#define BSS_DECRYPTED
2f7412ba 99
74e08179
SS
100#endif
101
afb8095a
SR
102PHDRS {
103 text PT_LOAD FLAGS(5); /* R_E */
5bd5a452 104 data PT_LOAD FLAGS(6); /* RW_ */
afb8095a 105#ifdef CONFIG_X86_64
afb8095a 106#ifdef CONFIG_SMP
8d0cc631 107 percpu PT_LOAD FLAGS(6); /* RW_ */
afb8095a 108#endif
c62e4320 109 init PT_LOAD FLAGS(7); /* RWE */
afb8095a
SR
110#endif
111 note PT_NOTE FLAGS(0); /* ___ */
112}
17ce265d 113
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SR
114SECTIONS
115{
116#ifdef CONFIG_X86_32
142b9e6c
AB
117 . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR;
118 phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET);
444e0ae4 119#else
142b9e6c
AB
120 . = __START_KERNEL;
121 phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET);
444e0ae4
SR
122#endif
123
dfc20895 124 /* Text and read-only data */
dfc20895 125 .text : AT(ADDR(.text) - LOAD_OFFSET) {
4ae59b91 126 _text = .;
e728f61c 127 _stext = .;
4ae59b91
TA
128 /* bootstrapping code */
129 HEAD_TEXT
dfc20895
SR
130 TEXT_TEXT
131 SCHED_TEXT
6727ad9e 132 CPUIDLE_TEXT
dfc20895
SR
133 LOCK_TEXT
134 KPROBES_TEXT
2f7412ba 135 ALIGN_ENTRY_TEXT_BEGIN
ea714547 136 ENTRY_TEXT
2f7412ba 137 ALIGN_ENTRY_TEXT_END
be7635e7 138 SOFTIRQENTRY_TEXT
1e7e4788 139 STATIC_CALL_TEXT
dfc20895
SR
140 *(.fixup)
141 *(.gnu.warning)
3386bc8a 142
736e80a4
MH
143#ifdef CONFIG_RETPOLINE
144 __indirect_thunk_start = .;
145 *(.text.__x86.indirect_thunk)
146 __indirect_thunk_end = .;
147#endif
7705dc85 148 } :text =0xcccc
392bef70 149
b9076938
KC
150 /* End of text section, which should occupy whole number of pages */
151 _etext = .;
5bd5a452 152 . = ALIGN(PAGE_SIZE);
b9076938 153
39d668e0 154 X86_ALIGN_RODATA_BEGIN
c62e4320 155 RO_DATA(PAGE_SIZE)
39d668e0 156 X86_ALIGN_RODATA_END
448bc3ab 157
1f6397ba 158 /* Data */
1f6397ba 159 .data : AT(ADDR(.data) - LOAD_OFFSET) {
1260866a
CM
160 /* Start of data section */
161 _sdata = .;
c62e4320
JB
162
163 /* init_task */
164 INIT_TASK_DATA(THREAD_SIZE)
1f6397ba
SR
165
166#ifdef CONFIG_X86_32
c62e4320
JB
167 /* 32 bit has nosave before _edata */
168 NOSAVE_DATA
1f6397ba
SR
169#endif
170
c62e4320 171 PAGE_ALIGNED_DATA(PAGE_SIZE)
1f6397ba 172
350f8f56 173 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
1f6397ba 174
c62e4320
JB
175 DATA_DATA
176 CONSTRUCTORS
177
178 /* rarely changed data like cpu maps */
350f8f56 179 READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES)
1f6397ba 180
1f6397ba
SR
181 /* End of data section */
182 _edata = .;
c62e4320 183 } :data
1f6397ba 184
b5effd38 185 BUG_TABLE
ff6f87e1 186
ee9f8fce
JP
187 ORC_UNWIND_TABLE
188
9c40818d
AL
189 . = ALIGN(PAGE_SIZE);
190 __vvar_page = .;
191
192 .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) {
f670bb76
AL
193 /* work around gold bug 13023 */
194 __vvar_beginning_hack = .;
9c40818d 195
f670bb76 196 /* Place all vvars at the offsets in asm/vvar.h. */
64b302ab 197#define EMIT_VVAR(name, offset) \
f670bb76 198 . = __vvar_beginning_hack + offset; \
9c40818d 199 *(.vvar_ ## name)
9c40818d 200#include <asm/vvar.h>
9c40818d
AL
201#undef EMIT_VVAR
202
309944be
AL
203 /*
204 * Pad the rest of the page with zeros. Otherwise the loader
205 * can leave garbage here.
206 */
207 . = __vvar_beginning_hack + PAGE_SIZE;
9c40818d
AL
208 } :data
209
a06cc94f 210 . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
9c40818d 211
c62e4320
JB
212 /* Init code and data - will be freed after init */
213 . = ALIGN(PAGE_SIZE);
214 .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
215 __init_begin = .; /* paired with __init_end */
e58bdaa8 216 }
e58bdaa8 217
c62e4320 218#if defined(CONFIG_X86_64) && defined(CONFIG_SMP)
e58bdaa8 219 /*
c62e4320
JB
220 * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the
221 * output PHDR, so the next output section - .init.text - should
222 * start another segment - init.
e58bdaa8 223 */
19df0c2f 224 PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu)
97b67ae5
JB
225 ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START,
226 "per-CPU data too large - increase CONFIG_PHYSICAL_START")
c62e4320 227#endif
e58bdaa8 228
123f3e1d 229 INIT_TEXT_SECTION(PAGE_SIZE)
c62e4320
JB
230#ifdef CONFIG_X86_64
231 :init
232#endif
e58bdaa8 233
337e4cc8
BP
234 /*
235 * Section for code used exclusively before alternatives are run. All
236 * references to such code must be patched out by alternatives, normally
237 * by using X86_FEATURE_ALWAYS CPU feature bit.
238 *
239 * See static_cpu_has() for an example.
240 */
241 .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) {
242 *(.altinstr_aux)
243 }
244
123f3e1d 245 INIT_DATA_SECTION(16)
e58bdaa8
SR
246
247 .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) {
248 __x86_cpu_dev_start = .;
249 *(.x86_cpu_dev.init)
250 __x86_cpu_dev_end = .;
251 }
252
66ac5013
DC
253#ifdef CONFIG_X86_INTEL_MID
254 .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \
255 LOAD_OFFSET) {
256 __x86_intel_mid_dev_start = .;
257 *(.x86_intel_mid_dev.init)
258 __x86_intel_mid_dev_end = .;
259 }
260#endif
261
6f44d033
KRW
262 /*
263 * start address and size of operations which during runtime
264 * can be patched with virtualization friendly instructions or
265 * baremetal native ones. Think page table operations.
266 * Details in paravirt_types.h
267 */
ae618362
SR
268 . = ALIGN(8);
269 .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) {
270 __parainstructions = .;
271 *(.parainstructions)
272 __parainstructions_end = .;
273 }
274
a77a9f03
PZ
275#ifdef CONFIG_RETPOLINE
276 /*
277 * List of instructions that call/jmp/jcc to retpoline thunks
278 * __x86_indirect_thunk_*(). These instructions can be patched along
279 * with alternatives, after which the section can be freed.
280 */
281 . = ALIGN(8);
282 .retpoline_sites : AT(ADDR(.retpoline_sites) - LOAD_OFFSET) {
283 __retpoline_sites = .;
284 *(.retpoline_sites)
285 __retpoline_sites_end = .;
286 }
287#endif
288
6f44d033
KRW
289 /*
290 * struct alt_inst entries. From the header (alternative.h):
291 * "Alternative instructions for different CPU types or capabilities"
292 * Think locking instructions on spinlocks.
293 */
ae618362
SR
294 . = ALIGN(8);
295 .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
296 __alt_instructions = .;
297 *(.altinstructions)
298 __alt_instructions_end = .;
299 }
300
6f44d033
KRW
301 /*
302 * And here are the replacement instructions. The linker sticks
303 * them as binary blobs. The .altinstructions has enough data to
304 * get the address and the length of them to patch the kernel safely.
305 */
ae618362
SR
306 .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
307 *(.altinstr_replacement)
308 }
309
6f44d033
KRW
310 /*
311 * struct iommu_table_entry entries are injected in this section.
312 * It is an array of IOMMUs which during run time gets sorted depending
313 * on its dependency order. After rootfs_initcall is complete
314 * this section can be safely removed.
315 */
0444ad93
KRW
316 .iommu_table : AT(ADDR(.iommu_table) - LOAD_OFFSET) {
317 __iommu_table = .;
318 *(.iommu_table)
0444ad93
KRW
319 __iommu_table_end = .;
320 }
4822b7fc 321
107e0e0c
SS
322 . = ALIGN(8);
323 .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) {
324 __apicdrivers = .;
325 *(.apicdrivers);
326 __apicdrivers_end = .;
327 }
328
7ac41ccf 329 . = ALIGN(8);
bf6a5741 330 /*
6f8f0dc9
AS
331 * .exit.text is discarded at runtime, not link time, to deal with
332 * references from .altinstructions
bf6a5741
SR
333 */
334 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) {
335 EXIT_TEXT
336 }
337
338 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) {
339 EXIT_DATA
340 }
341
c62e4320 342#if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP)
0415b00d 343 PERCPU_SECTION(INTERNODE_CACHE_BYTES)
9d16e783
SR
344#endif
345
346 . = ALIGN(PAGE_SIZE);
fd073194 347
9d16e783 348 /* freed after init ends here */
fd073194
IM
349 .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) {
350 __init_end = .;
351 }
9d16e783 352
c62e4320
JB
353 /*
354 * smp_locks might be freed after init
355 * start/end must be page aligned
356 */
357 . = ALIGN(PAGE_SIZE);
358 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
359 __smp_locks = .;
360 *(.smp_locks)
c62e4320 361 . = ALIGN(PAGE_SIZE);
596b711e 362 __smp_locks_end = .;
c62e4320
JB
363 }
364
9d16e783
SR
365#ifdef CONFIG_X86_64
366 .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) {
c62e4320
JB
367 NOSAVE_DATA
368 }
9d16e783
SR
369#endif
370
091e52c3
SR
371 /* BSS */
372 . = ALIGN(PAGE_SIZE);
373 .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
374 __bss_start = .;
7c74df07 375 *(.bss..page_aligned)
de2b41be 376 . = ALIGN(PAGE_SIZE);
6a03469a 377 *(BSS_MAIN)
b3f0907c 378 BSS_DECRYPTED
5bd5a452 379 . = ALIGN(PAGE_SIZE);
091e52c3
SR
380 __bss_stop = .;
381 }
9d16e783 382
c603a309
TL
383 /*
384 * The memory occupied from _text to here, __end_of_kernel_reserve, is
385 * automatically reserved in setup_arch(). Anything after here must be
386 * explicitly reserved using memblock_reserve() or it will be discarded
387 * and treated as available memory.
388 */
389 __end_of_kernel_reserve = .;
390
091e52c3
SR
391 . = ALIGN(PAGE_SIZE);
392 .brk : AT(ADDR(.brk) - LOAD_OFFSET) {
393 __brk_base = .;
394 . += 64 * 1024; /* 64k alignment slop space */
395 *(.brk_reservation) /* areas brk users have reserved */
396 __brk_limit = .;
397 }
398
974f221c 399 . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */
873b5271 400 _end = .;
091e52c3 401
e1bfa873
TL
402#ifdef CONFIG_AMD_MEM_ENCRYPT
403 /*
404 * Early scratch/workarea section: Lives outside of the kernel proper
405 * (_text - _end).
406 *
407 * Resides after _end because even though the .brk section is after
408 * __end_of_kernel_reserve, the .brk section is later reserved as a
409 * part of the kernel. Since it is located after __end_of_kernel_reserve
410 * it will be discarded and become part of the available memory. As
411 * such, it can only be used by very early boot code and must not be
412 * needed afterwards.
413 *
414 * Currently used by SME for performing in-place encryption of the
415 * kernel during boot. Resides on a 2MB boundary to simplify the
416 * pagetable setup used for SME in-place encryption.
417 */
418 . = ALIGN(HPAGE_SIZE);
419 .init.scratch : AT(ADDR(.init.scratch) - LOAD_OFFSET) {
420 __init_scratch_begin = .;
421 *(.init.scratch)
422 . = ALIGN(HPAGE_SIZE);
423 __init_scratch_end = .;
424 }
425#endif
426
a06cc94f
C
427 STABS_DEBUG
428 DWARF_DEBUG
c604abc3 429 ELF_DETAILS
023bf6f1 430
023bf6f1 431 DISCARDS
444e0ae4 432
815d6807
KC
433 /*
434 * Make sure that the .got.plt is either completely empty or it
435 * contains only the lazy dispatch entries.
436 */
437 .got.plt (INFO) : { *(.got.plt) }
438 ASSERT(SIZEOF(.got.plt) == 0 ||
439#ifdef CONFIG_X86_64
440 SIZEOF(.got.plt) == 0x18,
441#else
442 SIZEOF(.got.plt) == 0xc,
443#endif
444 "Unexpected GOT/PLT entries detected!")
5354e845
KC
445
446 /*
447 * Sections that should stay zero sized, which is safer to
448 * explicitly check instead of blindly discarding.
449 */
450 .got : {
451 *(.got) *(.igot.*)
452 }
453 ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!")
454
455 .plt : {
456 *(.plt) *(.plt.*) *(.iplt)
457 }
458 ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!")
459
460 .rel.dyn : {
461 *(.rel.*) *(.rel_*)
462 }
463 ASSERT(SIZEOF(.rel.dyn) == 0, "Unexpected run-time relocations (.rel) detected!")
464
465 .rela.dyn : {
466 *(.rela.*) *(.rela_*)
467 }
468 ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!")
815d6807 469}
17ce265d 470
a5912f6b
IM
471/*
472 * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility:
473 */
d2ba8b21
PA
474. = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE),
475 "kernel image bigger than KERNEL_IMAGE_SIZE");
ea3186b9
AS
476
477#ifdef CONFIG_X86_64
17ce265d
SR
478/*
479 * Per-cpu symbols which need to be offset from __per_cpu_load
480 * for the boot processor.
481 */
d071ae09 482#define INIT_PER_CPU(x) init_per_cpu__##x = ABSOLUTE(x) + __per_cpu_load
17ce265d 483INIT_PER_CPU(gdt_page);
e6401c13
AL
484INIT_PER_CPU(fixed_percpu_data);
485INIT_PER_CPU(irq_stack_backing_store);
17ce265d 486
17ce265d 487#ifdef CONFIG_SMP
e6401c13
AL
488. = ASSERT((fixed_percpu_data == 0),
489 "fixed_percpu_data is not at start of per-cpu area");
17ce265d
SR
490#endif
491
ea3186b9 492#endif /* CONFIG_X86_64 */
17ce265d 493
2965faa5 494#ifdef CONFIG_KEXEC_CORE
17ce265d
SR
495#include <asm/kexec.h>
496
d2ba8b21
PA
497. = ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE,
498 "kexec control code size is too big");
17ce265d
SR
499#endif
500