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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
17ce265d SR |
2 | /* |
3 | * ld script for the x86 kernel | |
4 | * | |
5 | * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> | |
6 | * | |
91fd7fe8 IM |
7 | * Modernisation, unification and other changes and fixes: |
8 | * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org> | |
17ce265d SR |
9 | * |
10 | * | |
11 | * Don't define absolute symbols until and unless you know that symbol | |
12 | * value is should remain constant even if kernel image is relocated | |
13 | * at run time. Absolute symbols are not relocated. If symbol value should | |
14 | * change if kernel is relocated, make the symbol section relative and | |
15 | * put it inside the section definition. | |
16 | */ | |
17 | ||
18 | #ifdef CONFIG_X86_32 | |
19 | #define LOAD_OFFSET __PAGE_OFFSET | |
20 | #else | |
21 | #define LOAD_OFFSET __START_KERNEL_map | |
22 | #endif | |
23 | ||
24 | #include <asm-generic/vmlinux.lds.h> | |
25 | #include <asm/asm-offsets.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/page_types.h> | |
ee9f8fce | 28 | #include <asm/orc_lookup.h> |
17ce265d SR |
29 | #include <asm/cache.h> |
30 | #include <asm/boot.h> | |
31 | ||
32 | #undef i386 /* in case the preprocessor is a 32bit one */ | |
33 | ||
34 | OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT) | |
35 | ||
36 | #ifdef CONFIG_X86_32 | |
37 | OUTPUT_ARCH(i386) | |
38 | ENTRY(phys_startup_32) | |
6b35eb9d | 39 | jiffies = jiffies_64; |
17ce265d SR |
40 | #else |
41 | OUTPUT_ARCH(i386:x86-64) | |
42 | ENTRY(phys_startup_64) | |
6b35eb9d | 43 | jiffies_64 = jiffies; |
17ce265d SR |
44 | #endif |
45 | ||
9ccaf77c | 46 | #if defined(CONFIG_X86_64) |
d6cc1c3a | 47 | /* |
9ccaf77c KC |
48 | * On 64-bit, align RODATA to 2MB so we retain large page mappings for |
49 | * boundaries spanning kernel text, rodata and data sections. | |
d6cc1c3a SS |
50 | * |
51 | * However, kernel identity mappings will have different RWX permissions | |
52 | * to the pages mapping to text and to the pages padding (which are freed) the | |
53 | * text section. Hence kernel identity mappings will be broken to smaller | |
54 | * pages. For 64-bit, kernel text and kernel identity mappings are different, | |
9ccaf77c KC |
55 | * so we can enable protection checks as well as retain 2MB large page |
56 | * mappings for kernel text. | |
d6cc1c3a | 57 | */ |
2b51456a | 58 | #define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE); |
74e08179 | 59 | |
2b51456a | 60 | #define X86_ALIGN_RODATA_END \ |
74e08179 | 61 | . = ALIGN(HPAGE_SIZE); \ |
2b51456a JR |
62 | __end_rodata_hpage_align = .; \ |
63 | __end_rodata_aligned = .; | |
74e08179 | 64 | |
2f7412ba TG |
65 | #define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE); |
66 | #define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE); | |
67 | ||
74e08179 SS |
68 | #else |
69 | ||
2b51456a JR |
70 | #define X86_ALIGN_RODATA_BEGIN |
71 | #define X86_ALIGN_RODATA_END \ | |
72 | . = ALIGN(PAGE_SIZE); \ | |
73 | __end_rodata_aligned = .; | |
74e08179 | 74 | |
2f7412ba TG |
75 | #define ALIGN_ENTRY_TEXT_BEGIN |
76 | #define ALIGN_ENTRY_TEXT_END | |
77 | ||
74e08179 SS |
78 | #endif |
79 | ||
afb8095a SR |
80 | PHDRS { |
81 | text PT_LOAD FLAGS(5); /* R_E */ | |
5bd5a452 | 82 | data PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 83 | #ifdef CONFIG_X86_64 |
afb8095a | 84 | #ifdef CONFIG_SMP |
8d0cc631 | 85 | percpu PT_LOAD FLAGS(6); /* RW_ */ |
afb8095a | 86 | #endif |
c62e4320 | 87 | init PT_LOAD FLAGS(7); /* RWE */ |
afb8095a SR |
88 | #endif |
89 | note PT_NOTE FLAGS(0); /* ___ */ | |
90 | } | |
17ce265d | 91 | |
444e0ae4 SR |
92 | SECTIONS |
93 | { | |
94 | #ifdef CONFIG_X86_32 | |
142b9e6c AB |
95 | . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR; |
96 | phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET); | |
444e0ae4 | 97 | #else |
142b9e6c AB |
98 | . = __START_KERNEL; |
99 | phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET); | |
444e0ae4 SR |
100 | #endif |
101 | ||
dfc20895 | 102 | /* Text and read-only data */ |
dfc20895 | 103 | .text : AT(ADDR(.text) - LOAD_OFFSET) { |
4ae59b91 | 104 | _text = .; |
e728f61c | 105 | _stext = .; |
4ae59b91 TA |
106 | /* bootstrapping code */ |
107 | HEAD_TEXT | |
dfc20895 | 108 | . = ALIGN(8); |
dfc20895 SR |
109 | TEXT_TEXT |
110 | SCHED_TEXT | |
6727ad9e | 111 | CPUIDLE_TEXT |
dfc20895 SR |
112 | LOCK_TEXT |
113 | KPROBES_TEXT | |
2f7412ba | 114 | ALIGN_ENTRY_TEXT_BEGIN |
ea714547 | 115 | ENTRY_TEXT |
dfc20895 | 116 | IRQENTRY_TEXT |
2f7412ba | 117 | ALIGN_ENTRY_TEXT_END |
be7635e7 | 118 | SOFTIRQENTRY_TEXT |
dfc20895 SR |
119 | *(.fixup) |
120 | *(.gnu.warning) | |
3386bc8a AL |
121 | |
122 | #ifdef CONFIG_X86_64 | |
123 | . = ALIGN(PAGE_SIZE); | |
c47e4cc5 | 124 | VMLINUX_SYMBOL(__entry_trampoline_start) = .; |
3386bc8a AL |
125 | _entry_trampoline = .; |
126 | *(.entry_trampoline) | |
127 | . = ALIGN(PAGE_SIZE); | |
c47e4cc5 | 128 | VMLINUX_SYMBOL(__entry_trampoline_end) = .; |
3386bc8a AL |
129 | ASSERT(. - _entry_trampoline == PAGE_SIZE, "entry trampoline is too big"); |
130 | #endif | |
131 | ||
736e80a4 MH |
132 | #ifdef CONFIG_RETPOLINE |
133 | __indirect_thunk_start = .; | |
134 | *(.text.__x86.indirect_thunk) | |
135 | __indirect_thunk_end = .; | |
136 | #endif | |
137 | ||
dfc20895 SR |
138 | /* End of text section */ |
139 | _etext = .; | |
140 | } :text = 0x9090 | |
141 | ||
142 | NOTES :text :note | |
143 | ||
123f3e1d | 144 | EXCEPTION_TABLE(16) :text = 0x9090 |
448bc3ab | 145 | |
5bd5a452 MC |
146 | /* .text should occupy whole number of pages */ |
147 | . = ALIGN(PAGE_SIZE); | |
2b51456a | 148 | X86_ALIGN_RODATA_BEGIN |
c62e4320 | 149 | RO_DATA(PAGE_SIZE) |
2b51456a | 150 | X86_ALIGN_RODATA_END |
448bc3ab | 151 | |
1f6397ba | 152 | /* Data */ |
1f6397ba | 153 | .data : AT(ADDR(.data) - LOAD_OFFSET) { |
1260866a CM |
154 | /* Start of data section */ |
155 | _sdata = .; | |
c62e4320 JB |
156 | |
157 | /* init_task */ | |
158 | INIT_TASK_DATA(THREAD_SIZE) | |
1f6397ba SR |
159 | |
160 | #ifdef CONFIG_X86_32 | |
c62e4320 JB |
161 | /* 32 bit has nosave before _edata */ |
162 | NOSAVE_DATA | |
1f6397ba SR |
163 | #endif |
164 | ||
c62e4320 | 165 | PAGE_ALIGNED_DATA(PAGE_SIZE) |
1f6397ba | 166 | |
350f8f56 | 167 | CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) |
1f6397ba | 168 | |
c62e4320 JB |
169 | DATA_DATA |
170 | CONSTRUCTORS | |
171 | ||
172 | /* rarely changed data like cpu maps */ | |
350f8f56 | 173 | READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES) |
1f6397ba | 174 | |
1f6397ba SR |
175 | /* End of data section */ |
176 | _edata = .; | |
c62e4320 | 177 | } :data |
1f6397ba | 178 | |
b5effd38 | 179 | BUG_TABLE |
ff6f87e1 | 180 | |
ee9f8fce JP |
181 | ORC_UNWIND_TABLE |
182 | ||
9c40818d AL |
183 | . = ALIGN(PAGE_SIZE); |
184 | __vvar_page = .; | |
185 | ||
186 | .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) { | |
f670bb76 AL |
187 | /* work around gold bug 13023 */ |
188 | __vvar_beginning_hack = .; | |
9c40818d | 189 | |
f670bb76 AL |
190 | /* Place all vvars at the offsets in asm/vvar.h. */ |
191 | #define EMIT_VVAR(name, offset) \ | |
192 | . = __vvar_beginning_hack + offset; \ | |
9c40818d AL |
193 | *(.vvar_ ## name) |
194 | #define __VVAR_KERNEL_LDS | |
195 | #include <asm/vvar.h> | |
196 | #undef __VVAR_KERNEL_LDS | |
197 | #undef EMIT_VVAR | |
198 | ||
309944be AL |
199 | /* |
200 | * Pad the rest of the page with zeros. Otherwise the loader | |
201 | * can leave garbage here. | |
202 | */ | |
203 | . = __vvar_beginning_hack + PAGE_SIZE; | |
9c40818d AL |
204 | } :data |
205 | ||
206 | . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE); | |
207 | ||
c62e4320 JB |
208 | /* Init code and data - will be freed after init */ |
209 | . = ALIGN(PAGE_SIZE); | |
210 | .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) { | |
211 | __init_begin = .; /* paired with __init_end */ | |
e58bdaa8 | 212 | } |
e58bdaa8 | 213 | |
c62e4320 | 214 | #if defined(CONFIG_X86_64) && defined(CONFIG_SMP) |
e58bdaa8 | 215 | /* |
c62e4320 JB |
216 | * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the |
217 | * output PHDR, so the next output section - .init.text - should | |
218 | * start another segment - init. | |
e58bdaa8 | 219 | */ |
19df0c2f | 220 | PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) |
97b67ae5 JB |
221 | ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START, |
222 | "per-CPU data too large - increase CONFIG_PHYSICAL_START") | |
c62e4320 | 223 | #endif |
e58bdaa8 | 224 | |
123f3e1d | 225 | INIT_TEXT_SECTION(PAGE_SIZE) |
c62e4320 JB |
226 | #ifdef CONFIG_X86_64 |
227 | :init | |
228 | #endif | |
e58bdaa8 | 229 | |
337e4cc8 BP |
230 | /* |
231 | * Section for code used exclusively before alternatives are run. All | |
232 | * references to such code must be patched out by alternatives, normally | |
233 | * by using X86_FEATURE_ALWAYS CPU feature bit. | |
234 | * | |
235 | * See static_cpu_has() for an example. | |
236 | */ | |
237 | .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { | |
238 | *(.altinstr_aux) | |
239 | } | |
240 | ||
123f3e1d | 241 | INIT_DATA_SECTION(16) |
e58bdaa8 SR |
242 | |
243 | .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { | |
244 | __x86_cpu_dev_start = .; | |
245 | *(.x86_cpu_dev.init) | |
246 | __x86_cpu_dev_end = .; | |
247 | } | |
248 | ||
66ac5013 DC |
249 | #ifdef CONFIG_X86_INTEL_MID |
250 | .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \ | |
251 | LOAD_OFFSET) { | |
252 | __x86_intel_mid_dev_start = .; | |
253 | *(.x86_intel_mid_dev.init) | |
254 | __x86_intel_mid_dev_end = .; | |
255 | } | |
256 | #endif | |
257 | ||
6f44d033 KRW |
258 | /* |
259 | * start address and size of operations which during runtime | |
260 | * can be patched with virtualization friendly instructions or | |
261 | * baremetal native ones. Think page table operations. | |
262 | * Details in paravirt_types.h | |
263 | */ | |
ae618362 SR |
264 | . = ALIGN(8); |
265 | .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) { | |
266 | __parainstructions = .; | |
267 | *(.parainstructions) | |
268 | __parainstructions_end = .; | |
269 | } | |
270 | ||
6f44d033 KRW |
271 | /* |
272 | * struct alt_inst entries. From the header (alternative.h): | |
273 | * "Alternative instructions for different CPU types or capabilities" | |
274 | * Think locking instructions on spinlocks. | |
275 | */ | |
ae618362 SR |
276 | . = ALIGN(8); |
277 | .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) { | |
278 | __alt_instructions = .; | |
279 | *(.altinstructions) | |
280 | __alt_instructions_end = .; | |
281 | } | |
282 | ||
6f44d033 KRW |
283 | /* |
284 | * And here are the replacement instructions. The linker sticks | |
285 | * them as binary blobs. The .altinstructions has enough data to | |
286 | * get the address and the length of them to patch the kernel safely. | |
287 | */ | |
ae618362 SR |
288 | .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) { |
289 | *(.altinstr_replacement) | |
290 | } | |
291 | ||
6f44d033 KRW |
292 | /* |
293 | * struct iommu_table_entry entries are injected in this section. | |
294 | * It is an array of IOMMUs which during run time gets sorted depending | |
295 | * on its dependency order. After rootfs_initcall is complete | |
296 | * this section can be safely removed. | |
297 | */ | |
0444ad93 KRW |
298 | .iommu_table : AT(ADDR(.iommu_table) - LOAD_OFFSET) { |
299 | __iommu_table = .; | |
300 | *(.iommu_table) | |
0444ad93 KRW |
301 | __iommu_table_end = .; |
302 | } | |
4822b7fc | 303 | |
107e0e0c SS |
304 | . = ALIGN(8); |
305 | .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) { | |
306 | __apicdrivers = .; | |
307 | *(.apicdrivers); | |
308 | __apicdrivers_end = .; | |
309 | } | |
310 | ||
7ac41ccf | 311 | . = ALIGN(8); |
bf6a5741 SR |
312 | /* |
313 | * .exit.text is discard at runtime, not link time, to deal with | |
314 | * references from .altinstructions and .eh_frame | |
315 | */ | |
316 | .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { | |
317 | EXIT_TEXT | |
318 | } | |
319 | ||
320 | .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { | |
321 | EXIT_DATA | |
322 | } | |
323 | ||
c62e4320 | 324 | #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) |
0415b00d | 325 | PERCPU_SECTION(INTERNODE_CACHE_BYTES) |
9d16e783 SR |
326 | #endif |
327 | ||
328 | . = ALIGN(PAGE_SIZE); | |
fd073194 | 329 | |
9d16e783 | 330 | /* freed after init ends here */ |
fd073194 IM |
331 | .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) { |
332 | __init_end = .; | |
333 | } | |
9d16e783 | 334 | |
c62e4320 JB |
335 | /* |
336 | * smp_locks might be freed after init | |
337 | * start/end must be page aligned | |
338 | */ | |
339 | . = ALIGN(PAGE_SIZE); | |
340 | .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { | |
341 | __smp_locks = .; | |
342 | *(.smp_locks) | |
c62e4320 | 343 | . = ALIGN(PAGE_SIZE); |
596b711e | 344 | __smp_locks_end = .; |
c62e4320 JB |
345 | } |
346 | ||
9d16e783 SR |
347 | #ifdef CONFIG_X86_64 |
348 | .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) { | |
c62e4320 JB |
349 | NOSAVE_DATA |
350 | } | |
9d16e783 SR |
351 | #endif |
352 | ||
091e52c3 SR |
353 | /* BSS */ |
354 | . = ALIGN(PAGE_SIZE); | |
355 | .bss : AT(ADDR(.bss) - LOAD_OFFSET) { | |
356 | __bss_start = .; | |
7c74df07 | 357 | *(.bss..page_aligned) |
091e52c3 | 358 | *(.bss) |
5bd5a452 | 359 | . = ALIGN(PAGE_SIZE); |
091e52c3 SR |
360 | __bss_stop = .; |
361 | } | |
9d16e783 | 362 | |
091e52c3 SR |
363 | . = ALIGN(PAGE_SIZE); |
364 | .brk : AT(ADDR(.brk) - LOAD_OFFSET) { | |
365 | __brk_base = .; | |
366 | . += 64 * 1024; /* 64k alignment slop space */ | |
367 | *(.brk_reservation) /* areas brk users have reserved */ | |
368 | __brk_limit = .; | |
369 | } | |
370 | ||
974f221c | 371 | . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */ |
873b5271 | 372 | _end = .; |
091e52c3 | 373 | |
444e0ae4 SR |
374 | STABS_DEBUG |
375 | DWARF_DEBUG | |
023bf6f1 TH |
376 | |
377 | /* Sections to be discarded */ | |
378 | DISCARDS | |
9a99417a JP |
379 | /DISCARD/ : { |
380 | *(.eh_frame) | |
9a99417a | 381 | } |
444e0ae4 SR |
382 | } |
383 | ||
17ce265d SR |
384 | |
385 | #ifdef CONFIG_X86_32 | |
a5912f6b IM |
386 | /* |
387 | * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: | |
388 | */ | |
d2ba8b21 PA |
389 | . = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE), |
390 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
391 | #else |
392 | /* | |
393 | * Per-cpu symbols which need to be offset from __per_cpu_load | |
394 | * for the boot processor. | |
395 | */ | |
dd17c8f7 | 396 | #define INIT_PER_CPU(x) init_per_cpu__##x = x + __per_cpu_load |
17ce265d SR |
397 | INIT_PER_CPU(gdt_page); |
398 | INIT_PER_CPU(irq_stack_union); | |
399 | ||
400 | /* | |
401 | * Build-time check on the image size: | |
402 | */ | |
d2ba8b21 PA |
403 | . = ASSERT((_end - _text <= KERNEL_IMAGE_SIZE), |
404 | "kernel image bigger than KERNEL_IMAGE_SIZE"); | |
17ce265d SR |
405 | |
406 | #ifdef CONFIG_SMP | |
dd17c8f7 | 407 | . = ASSERT((irq_stack_union == 0), |
d2ba8b21 | 408 | "irq_stack_union is not at start of per-cpu area"); |
17ce265d SR |
409 | #endif |
410 | ||
411 | #endif /* CONFIG_X86_32 */ | |
412 | ||
2965faa5 | 413 | #ifdef CONFIG_KEXEC_CORE |
17ce265d SR |
414 | #include <asm/kexec.h> |
415 | ||
d2ba8b21 PA |
416 | . = ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE, |
417 | "kexec control code size is too big"); | |
17ce265d SR |
418 | #endif |
419 |