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Commit | Line | Data |
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57844a8f TG |
1 | /* |
2 | * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de> | |
3 | * | |
4 | * For licencing details see kernel-base/COPYING | |
5 | */ | |
6 | #include <linux/init.h> | |
9325a28c | 7 | #include <linux/ioport.h> |
186f4360 | 8 | #include <linux/export.h> |
294ee6f8 | 9 | #include <linux/pci.h> |
57844a8f | 10 | |
816c25e7 | 11 | #include <asm/bios_ebda.h> |
6f30c1ac | 12 | #include <asm/paravirt.h> |
b72d0db9 | 13 | #include <asm/pci_x86.h> |
fd6c6661 | 14 | #include <asm/mpspec.h> |
8fee697d | 15 | #include <asm/setup.h> |
736decac | 16 | #include <asm/apic.h> |
66441bd3 | 17 | #include <asm/e820/api.h> |
845b3944 | 18 | #include <asm/time.h> |
d9112f43 | 19 | #include <asm/irq.h> |
4a8e2a31 | 20 | #include <asm/io_apic.h> |
71054d88 | 21 | #include <asm/hpet.h> |
fd12a0d6 | 22 | #include <asm/pat.h> |
2d826404 | 23 | #include <asm/tsc.h> |
338bac52 | 24 | #include <asm/iommu.h> |
064a59b6 | 25 | #include <asm/mach_traps.h> |
57844a8f | 26 | |
148f9bb8 | 27 | void x86_init_noop(void) { } |
f4848472 | 28 | void __init x86_init_uint_noop(unsigned int unused) { } |
d07c1be0 | 29 | int __init iommu_init_noop(void) { return 0; } |
62ad33f6 | 30 | void iommu_shutdown_noop(void) { } |
f72e38e8 JG |
31 | bool __init bool_x86_init_noop(void) { return false; } |
32 | void x86_op_int_noop(int cpu) { } | |
57844a8f TG |
33 | |
34 | /* | |
35 | * The platform setup functions are preset with the default functions | |
36 | * for standard PC hardware. | |
37 | */ | |
54e2603f | 38 | struct x86_init_ops x86_init __initdata = { |
f7cf5a5b TG |
39 | |
40 | .resources = { | |
5d94e81f | 41 | .probe_roms = probe_roms, |
8fee697d | 42 | .reserve_resources = reserve_standard_io_resources, |
103e2063 | 43 | .memory_setup = e820__memory_setup_default, |
f7cf5a5b | 44 | }, |
f4848472 TG |
45 | |
46 | .mpparse = { | |
47 | .mpc_record = x86_init_uint_noop, | |
de934103 | 48 | .setup_ioapic_ids = x86_init_noop, |
fd6c6661 | 49 | .mpc_apic_id = default_mpc_apic_id, |
72302142 | 50 | .smp_read_mpc_oem = default_smp_read_mpc_oem, |
90e1c696 | 51 | .mpc_oem_bus_info = default_mpc_oem_bus_info, |
b3f1b617 TG |
52 | .find_smp_config = default_find_smp_config, |
53 | .get_smp_config = default_get_smp_config, | |
f4848472 | 54 | }, |
d9112f43 TG |
55 | |
56 | .irqs = { | |
57 | .pre_vector_init = init_ISA_irqs, | |
66bcaf0b | 58 | .intr_init = native_init_IRQ, |
428cf902 | 59 | .trap_init = x86_init_noop, |
34fba3e6 | 60 | .intr_mode_init = apic_intr_mode_init |
d9112f43 | 61 | }, |
42bbdb43 TG |
62 | |
63 | .oem = { | |
64 | .arch_setup = x86_init_noop, | |
6f30c1ac | 65 | .banner = default_banner, |
42bbdb43 | 66 | }, |
030cb6c0 TG |
67 | |
68 | .paging = { | |
7737b215 | 69 | .pagetable_init = native_pagetable_init, |
030cb6c0 | 70 | }, |
736decac TG |
71 | |
72 | .timers = { | |
73 | .setup_percpu_clockev = setup_boot_APIC_clock, | |
845b3944 | 74 | .timer_init = hpet_time_init, |
6b617e22 | 75 | .wallclock_init = x86_init_noop, |
736decac | 76 | }, |
d07c1be0 FT |
77 | |
78 | .iommu = { | |
79 | .iommu_init = iommu_init_noop, | |
80 | }, | |
b72d0db9 TG |
81 | |
82 | .pci = { | |
83 | .init = x86_default_pci_init, | |
ab3b3793 | 84 | .init_irq = x86_default_pci_init_irq, |
9325a28c | 85 | .fixup_irqs = x86_default_pci_fixup_irqs, |
b72d0db9 | 86 | }, |
f72e38e8 JG |
87 | |
88 | .hyper = { | |
89 | .init_platform = x86_init_noop, | |
f3614646 | 90 | .guest_late_init = x86_init_noop, |
f72e38e8 JG |
91 | .x2apic_available = bool_x86_init_noop, |
92 | .init_mem_mapping = x86_init_noop, | |
93 | }, | |
736decac TG |
94 | }; |
95 | ||
148f9bb8 | 96 | struct x86_cpuinit_ops x86_cpuinit = { |
df156f90 | 97 | .early_percpu_clock_init = x86_init_noop, |
736decac | 98 | .setup_percpu_clockev = setup_secondary_APIC_clock, |
57844a8f | 99 | }; |
2d826404 | 100 | |
78c06176 RA |
101 | static void default_nmi_init(void) { }; |
102 | ||
404f6aac | 103 | struct x86_platform_ops x86_platform __ro_after_init = { |
aa297292 | 104 | .calibrate_cpu = native_calibrate_cpu, |
2d826404 | 105 | .calibrate_tsc = native_calibrate_tsc, |
7bd867df FT |
106 | .get_wallclock = mach_get_cmos_time, |
107 | .set_wallclock = mach_set_rtc_mmss, | |
338bac52 | 108 | .iommu_shutdown = iommu_shutdown_noop, |
eb41c8be | 109 | .is_untracked_pat_range = is_ISA_range, |
c516ac58 | 110 | .nmi_init = default_nmi_init, |
064a59b6 | 111 | .get_nmi_reason = default_get_nmi_reason, |
b74f05d6 MT |
112 | .save_sched_clock_state = tsc_save_sched_clock_state, |
113 | .restore_sched_clock_state = tsc_restore_sched_clock_state, | |
f72e38e8 | 114 | .hyper.pin_vcpu = x86_op_int_noop, |
2d826404 | 115 | }; |
72550b3a PA |
116 | |
117 | EXPORT_SYMBOL_GPL(x86_platform); | |
4287d824 TP |
118 | |
119 | #if defined(CONFIG_PCI_MSI) | |
404f6aac | 120 | struct x86_msi_ops x86_msi __ro_after_init = { |
71054d88 JR |
121 | .setup_msi_irqs = native_setup_msi_irqs, |
122 | .teardown_msi_irq = native_teardown_msi_irq, | |
123 | .teardown_msi_irqs = default_teardown_msi_irqs, | |
124 | .restore_msi_irqs = default_restore_msi_irqs, | |
294ee6f8 | 125 | }; |
4a8e2a31 | 126 | |
4287d824 TP |
127 | /* MSI arch specific hooks */ |
128 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
129 | { | |
130 | return x86_msi.setup_msi_irqs(dev, nvec, type); | |
131 | } | |
132 | ||
133 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
134 | { | |
135 | x86_msi.teardown_msi_irqs(dev); | |
136 | } | |
137 | ||
138 | void arch_teardown_msi_irq(unsigned int irq) | |
139 | { | |
140 | x86_msi.teardown_msi_irq(irq); | |
141 | } | |
142 | ||
ac8344c4 | 143 | void arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 144 | { |
ac8344c4 | 145 | x86_msi.restore_msi_irqs(dev); |
4287d824 TP |
146 | } |
147 | #endif | |
148 | ||
404f6aac | 149 | struct x86_io_apic_ops x86_io_apic_ops __ro_after_init = { |
1c4248ca | 150 | .read = native_io_apic_read, |
1c4248ca | 151 | .disable = native_disable_io_apic, |
4a8e2a31 | 152 | }; |