]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kernel/xsave.c
x86, fpu: Unify signal handling code paths for x86 and x86_64 kernels
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / xsave.c
CommitLineData
dc1e35c6
SS
1/*
2 * xsave/xrstor support.
3 *
4 * Author: Suresh Siddha <suresh.b.siddha@intel.com>
5 */
c767a54b
JP
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
dc1e35c6
SS
9#include <linux/bootmem.h>
10#include <linux/compat.h>
11#include <asm/i387.h>
1361b83a 12#include <asm/fpu-internal.h>
72a671ce 13#include <asm/sigframe.h>
6152e4b1 14#include <asm/xcr.h>
dc1e35c6
SS
15
16/*
17 * Supported feature mask by the CPU and the kernel.
18 */
6152e4b1 19u64 pcntxt_mask;
dc1e35c6 20
45c2d7f4
RR
21/*
22 * Represents init state for the supported extended state.
23 */
24static struct xsave_struct *init_xstate_buf;
25
72a671ce 26static struct _fpx_sw_bytes fx_sw_reserved, fx_sw_reserved_ia32;
a1488f8b
SS
27static unsigned int *xstate_offsets, *xstate_sizes, xstate_features;
28
29104e10
SS
29/*
30 * If a processor implementation discern that a processor state component is
31 * in its initialized state it may modify the corresponding bit in the
32 * xsave_hdr.xstate_bv as '0', with out modifying the corresponding memory
33 * layout in the case of xsaveopt. While presenting the xstate information to
34 * the user, we always ensure that the memory layout of a feature will be in
35 * the init state if the corresponding header bit is zero. This is to ensure
36 * that the user doesn't see some stale state in the memory layout during
37 * signal handling, debugging etc.
38 */
39void __sanitize_i387_state(struct task_struct *tsk)
40{
29104e10 41 struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave;
72a671ce
SS
42 int feature_bit = 0x2;
43 u64 xstate_bv;
29104e10
SS
44
45 if (!fx)
46 return;
47
29104e10
SS
48 xstate_bv = tsk->thread.fpu.state->xsave.xsave_hdr.xstate_bv;
49
50 /*
51 * None of the feature bits are in init state. So nothing else
0d2eb44f 52 * to do for us, as the memory layout is up to date.
29104e10
SS
53 */
54 if ((xstate_bv & pcntxt_mask) == pcntxt_mask)
55 return;
56
57 /*
58 * FP is in init state
59 */
60 if (!(xstate_bv & XSTATE_FP)) {
61 fx->cwd = 0x37f;
62 fx->swd = 0;
63 fx->twd = 0;
64 fx->fop = 0;
65 fx->rip = 0;
66 fx->rdp = 0;
67 memset(&fx->st_space[0], 0, 128);
68 }
69
70 /*
71 * SSE is in init state
72 */
73 if (!(xstate_bv & XSTATE_SSE))
74 memset(&fx->xmm_space[0], 0, 256);
75
76 xstate_bv = (pcntxt_mask & ~xstate_bv) >> 2;
77
78 /*
79 * Update all the other memory layouts for which the corresponding
80 * header bit is in the init state.
81 */
82 while (xstate_bv) {
83 if (xstate_bv & 0x1) {
84 int offset = xstate_offsets[feature_bit];
85 int size = xstate_sizes[feature_bit];
86
87 memcpy(((void *) fx) + offset,
88 ((void *) init_xstate_buf) + offset,
89 size);
90 }
91
92 xstate_bv >>= 1;
93 feature_bit++;
94 }
95}
96
c37b5efe
SS
97/*
98 * Check for the presence of extended state information in the
99 * user fpstate pointer in the sigcontext.
100 */
72a671ce
SS
101static inline int check_for_xstate(struct i387_fxsave_struct __user *buf,
102 void __user *fpstate,
103 struct _fpx_sw_bytes *fx_sw)
c37b5efe
SS
104{
105 int min_xstate_size = sizeof(struct i387_fxsave_struct) +
106 sizeof(struct xsave_hdr_struct);
107 unsigned int magic2;
c37b5efe 108
72a671ce
SS
109 if (__copy_from_user(fx_sw, &buf->sw_reserved[0], sizeof(*fx_sw)))
110 return -1;
c37b5efe 111
72a671ce
SS
112 /* Check for the first magic field and other error scenarios. */
113 if (fx_sw->magic1 != FP_XSTATE_MAGIC1 ||
114 fx_sw->xstate_size < min_xstate_size ||
115 fx_sw->xstate_size > xstate_size ||
116 fx_sw->xstate_size > fx_sw->extended_size)
117 return -1;
c37b5efe 118
c37b5efe
SS
119 /*
120 * Check for the presence of second magic word at the end of memory
121 * layout. This detects the case where the user just copied the legacy
122 * fpstate layout with out copying the extended state information
123 * in the memory layout.
124 */
72a671ce
SS
125 if (__get_user(magic2, (__u32 __user *)(fpstate + fx_sw->xstate_size))
126 || magic2 != FP_XSTATE_MAGIC2)
127 return -1;
c37b5efe
SS
128
129 return 0;
130}
131
ab513701
SS
132/*
133 * Signal frame handlers.
134 */
72a671ce
SS
135static inline int save_fsave_header(struct task_struct *tsk, void __user *buf)
136{
137 if (use_fxsr()) {
138 struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
139 struct user_i387_ia32_struct env;
140 struct _fpstate_ia32 __user *fp = buf;
ab513701 141
72a671ce
SS
142 convert_from_fxsr(&env, tsk);
143
144 if (__copy_to_user(buf, &env, sizeof(env)) ||
145 __put_user(xsave->i387.swd, &fp->status) ||
146 __put_user(X86_FXSR_MAGIC, &fp->magic))
147 return -1;
148 } else {
149 struct i387_fsave_struct __user *fp = buf;
150 u32 swd;
151 if (__get_user(swd, &fp->swd) || __put_user(swd, &fp->status))
152 return -1;
153 }
154
155 return 0;
156}
157
158static inline int save_xstate_epilog(void __user *buf, int ia32_frame)
ab513701 159{
72a671ce
SS
160 struct xsave_struct __user *x = buf;
161 struct _fpx_sw_bytes *sw_bytes;
162 u32 xstate_bv;
163 int err;
ab513701 164
72a671ce
SS
165 /* Setup the bytes not touched by the [f]xsave and reserved for SW. */
166 sw_bytes = ia32_frame ? &fx_sw_reserved_ia32 : &fx_sw_reserved;
167 err = __copy_to_user(&x->i387.sw_reserved, sw_bytes, sizeof(*sw_bytes));
ab513701 168
72a671ce
SS
169 if (!use_xsave())
170 return err;
ab513701 171
72a671ce 172 err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size));
ab513701 173
72a671ce
SS
174 /*
175 * Read the xstate_bv which we copied (directly from the cpu or
176 * from the state in task struct) to the user buffers.
177 */
178 err |= __get_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv);
06c38d5e 179
72a671ce
SS
180 /*
181 * For legacy compatible, we always set FP/SSE bits in the bit
182 * vector while saving the state to the user context. This will
183 * enable us capturing any changes(during sigreturn) to
184 * the FP/SSE bits by the legacy applications which don't touch
185 * xstate_bv in the xsave header.
186 *
187 * xsave aware apps can change the xstate_bv in the xsave
188 * header as well as change any contents in the memory layout.
189 * xrestore as part of sigreturn will capture all the changes.
190 */
191 xstate_bv |= XSTATE_FPSSE;
c37b5efe 192
72a671ce
SS
193 err |= __put_user(xstate_bv, (__u32 *)&x->xsave_hdr.xstate_bv);
194
195 return err;
196}
197
198static inline int save_user_xstate(struct xsave_struct __user *buf)
199{
200 int err;
201
202 if (use_xsave())
203 err = xsave_user(buf);
204 else if (use_fxsr())
205 err = fxsave_user((struct i387_fxsave_struct __user *) buf);
206 else
207 err = fsave_user((struct i387_fsave_struct __user *) buf);
208
209 if (unlikely(err) && __clear_user(buf, xstate_size))
210 err = -EFAULT;
211 return err;
212}
213
214/*
215 * Save the fpu, extended register state to the user signal frame.
216 *
217 * 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save
218 * state is copied.
219 * 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'.
220 *
221 * buf == buf_fx for 64-bit frames and 32-bit fsave frame.
222 * buf != buf_fx for 32-bit frames with fxstate.
223 *
224 * If the fpu, extended register state is live, save the state directly
225 * to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise,
226 * copy the thread's fpu state to the user frame starting at 'buf_fx'.
227 *
228 * If this is a 32-bit frame with fxstate, put a fsave header before
229 * the aligned state at 'buf_fx'.
230 *
231 * For [f]xsave state, update the SW reserved fields in the [f]xsave frame
232 * indicating the absence/presence of the extended state to the user.
233 */
234int save_xstate_sig(void __user *buf, void __user *buf_fx, int size)
235{
236 struct xsave_struct *xsave = &current->thread.fpu.state->xsave;
237 struct task_struct *tsk = current;
238 int ia32_fxstate = (buf != buf_fx);
239
240 ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
241 config_enabled(CONFIG_IA32_EMULATION));
242
243 if (!access_ok(VERIFY_WRITE, buf, size))
244 return -EACCES;
245
246 if (!HAVE_HWFP)
247 return fpregs_soft_get(current, NULL, 0,
248 sizeof(struct user_i387_ia32_struct), NULL,
249 (struct _fpstate_ia32 __user *) buf) ? -1 : 1;
250
251 if (user_has_fpu()) {
252 /* Save the live register state to the user directly. */
253 if (save_user_xstate(buf_fx))
254 return -1;
255 /* Update the thread's fxstate to save the fsave header. */
256 if (ia32_fxstate)
257 fpu_fxsave(&tsk->thread.fpu);
15d8791c 258 user_fpu_end();
ab513701 259 } else {
29104e10 260 sanitize_i387_state(tsk);
72a671ce 261 if (__copy_to_user(buf_fx, xsave, xstate_size))
ab513701
SS
262 return -1;
263 }
c37b5efe 264
72a671ce
SS
265 /* Save the fsave header for the 32-bit frames. */
266 if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf))
267 return -1;
06c38d5e 268
72a671ce
SS
269 if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate))
270 return -1;
271
272 drop_fpu(tsk); /* trigger finit */
273
274 return 0;
275}
c37b5efe 276
72a671ce
SS
277static inline void
278sanitize_restored_xstate(struct task_struct *tsk,
279 struct user_i387_ia32_struct *ia32_env,
280 u64 xstate_bv, int fx_only)
281{
282 struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
283 struct xsave_hdr_struct *xsave_hdr = &xsave->xsave_hdr;
c37b5efe 284
72a671ce
SS
285 if (use_xsave()) {
286 /* These bits must be zero. */
287 xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
04944b79
SS
288
289 /*
72a671ce
SS
290 * Init the state that is not present in the memory
291 * layout and not enabled by the OS.
04944b79 292 */
72a671ce
SS
293 if (fx_only)
294 xsave_hdr->xstate_bv = XSTATE_FPSSE;
295 else
296 xsave_hdr->xstate_bv &= (pcntxt_mask & xstate_bv);
297 }
04944b79 298
72a671ce 299 if (use_fxsr()) {
04944b79 300 /*
72a671ce
SS
301 * mscsr reserved bits must be masked to zero for security
302 * reasons.
04944b79 303 */
72a671ce 304 xsave->i387.mxcsr &= mxcsr_feature_mask;
04944b79 305
72a671ce 306 convert_to_fxsr(tsk, ia32_env);
c37b5efe 307 }
ab513701
SS
308}
309
c37b5efe 310/*
72a671ce 311 * Restore the extended state if present. Otherwise, restore the FP/SSE state.
c37b5efe 312 */
72a671ce 313static inline int restore_user_xstate(void __user *buf, u64 xbv, int fx_only)
c37b5efe 314{
72a671ce
SS
315 if (use_xsave()) {
316 if ((unsigned long)buf % 64 || fx_only) {
317 u64 init_bv = pcntxt_mask & ~XSTATE_FPSSE;
318 xrstor_state(init_xstate_buf, init_bv);
319 return fxrstor_checking((__force void *) buf);
320 } else {
321 u64 init_bv = pcntxt_mask & ~xbv;
322 if (unlikely(init_bv))
323 xrstor_state(init_xstate_buf, init_bv);
324 return xrestore_user(buf, xbv);
325 }
326 } else if (use_fxsr()) {
327 return fxrstor_checking((__force void *) buf);
328 } else
329 return frstor_checking((__force void *) buf);
c37b5efe
SS
330}
331
72a671ce 332int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
ab513701 333{
72a671ce 334 int ia32_fxstate = (buf != buf_fx);
ab513701 335 struct task_struct *tsk = current;
72a671ce
SS
336 int state_size = xstate_size;
337 u64 xstate_bv = 0;
338 int fx_only = 0;
339
340 ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
341 config_enabled(CONFIG_IA32_EMULATION));
ab513701
SS
342
343 if (!buf) {
72a671ce 344 drop_fpu(tsk);
ab513701 345 return 0;
72a671ce
SS
346 }
347
348 if (!access_ok(VERIFY_READ, buf, size))
349 return -EACCES;
350
351 if (!used_math() && init_fpu(tsk))
352 return -1;
ab513701 353
72a671ce
SS
354 if (!HAVE_HWFP) {
355 return fpregs_soft_set(current, NULL,
356 0, sizeof(struct user_i387_ia32_struct),
357 NULL, buf) != 0;
ab513701
SS
358 }
359
72a671ce
SS
360 if (use_xsave()) {
361 struct _fpx_sw_bytes fx_sw_user;
362 if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) {
363 /*
364 * Couldn't find the extended state information in the
365 * memory layout. Restore just the FP/SSE and init all
366 * the other extended state.
367 */
368 state_size = sizeof(struct i387_fxsave_struct);
369 fx_only = 1;
370 } else {
371 state_size = fx_sw_user.xstate_size;
372 xstate_bv = fx_sw_user.xstate_bv;
373 }
374 }
375
376 if (ia32_fxstate) {
377 /*
378 * For 32-bit frames with fxstate, copy the user state to the
379 * thread's fpu state, reconstruct fxstate from the fsave
380 * header. Sanitize the copied state etc.
381 */
382 struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
383 struct user_i387_ia32_struct env;
384
385 stop_fpu_preload(tsk);
386 unlazy_fpu(tsk);
387
388 if (__copy_from_user(xsave, buf_fx, state_size) ||
389 __copy_from_user(&env, buf, sizeof(env))) {
390 drop_fpu(tsk);
391 return -1;
392 }
393
394 sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only);
395 } else {
ab513701 396 /*
72a671ce
SS
397 * For 64-bit frames and 32-bit fsave frames, restore the user
398 * state to the registers directly (with exceptions handled).
ab513701 399 */
72a671ce
SS
400 user_fpu_begin();
401 if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) {
402 drop_fpu(tsk);
403 return -1;
404 }
ab513701 405 }
72a671ce
SS
406
407 return 0;
ab513701 408}
ab513701 409
c37b5efe
SS
410/*
411 * Prepare the SW reserved portion of the fxsave memory layout, indicating
412 * the presence of the extended state information in the memory layout
413 * pointed by the fpstate pointer in the sigcontext.
414 * This will be saved when ever the FP and extended state context is
415 * saved on the user stack during the signal handler delivery to the user.
416 */
8bcad30f 417static void prepare_fx_sw_frame(void)
c37b5efe 418{
72a671ce
SS
419 int fsave_header_size = sizeof(struct i387_fsave_struct);
420 int size = xstate_size + FP_XSTATE_MAGIC2_SIZE;
c37b5efe 421
72a671ce
SS
422 if (config_enabled(CONFIG_X86_32))
423 size += fsave_header_size;
c37b5efe
SS
424
425 fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
72a671ce 426 fx_sw_reserved.extended_size = size;
6152e4b1 427 fx_sw_reserved.xstate_bv = pcntxt_mask;
c37b5efe 428 fx_sw_reserved.xstate_size = xstate_size;
c37b5efe 429
72a671ce
SS
430 if (config_enabled(CONFIG_IA32_EMULATION)) {
431 fx_sw_reserved_ia32 = fx_sw_reserved;
432 fx_sw_reserved_ia32.extended_size += fsave_header_size;
433 }
434}
3c1c7f10 435
dc1e35c6
SS
436/*
437 * Enable the extended processor state save/restore feature
438 */
1cff92d8 439static inline void xstate_enable(void)
dc1e35c6 440{
dc1e35c6 441 set_in_cr4(X86_CR4_OSXSAVE);
6152e4b1 442 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
dc1e35c6
SS
443}
444
a1488f8b
SS
445/*
446 * Record the offsets and sizes of different state managed by the xsave
447 * memory layout.
448 */
4995b9db 449static void __init setup_xstate_features(void)
a1488f8b
SS
450{
451 int eax, ebx, ecx, edx, leaf = 0x2;
452
453 xstate_features = fls64(pcntxt_mask);
454 xstate_offsets = alloc_bootmem(xstate_features * sizeof(int));
455 xstate_sizes = alloc_bootmem(xstate_features * sizeof(int));
456
457 do {
ee813d53 458 cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx);
a1488f8b
SS
459
460 if (eax == 0)
461 break;
462
463 xstate_offsets[leaf] = ebx;
464 xstate_sizes[leaf] = eax;
465
466 leaf++;
467 } while (1);
468}
469
dc1e35c6
SS
470/*
471 * setup the xstate image representing the init state
472 */
a19aac85 473static void __init setup_xstate_init(void)
dc1e35c6 474{
29104e10
SS
475 setup_xstate_features();
476
477 /*
478 * Setup init_xstate_buf to represent the init state of
479 * all the features managed by the xsave
480 */
10340ae1
SS
481 init_xstate_buf = alloc_bootmem_align(xstate_size,
482 __alignof__(struct xsave_struct));
dc1e35c6 483 init_xstate_buf->i387.mxcsr = MXCSR_DEFAULT;
a1488f8b 484
29104e10
SS
485 clts();
486 /*
487 * Init all the features state with header_bv being 0x0
488 */
489 xrstor_state(init_xstate_buf, -1);
490 /*
491 * Dump the init state again. This is to identify the init state
492 * of any feature which is not represented by all zero's.
493 */
494 xsave_state(init_xstate_buf, -1);
495 stts();
dc1e35c6
SS
496}
497
498/*
499 * Enable and initialize the xsave feature.
500 */
1cff92d8 501static void __init xstate_enable_boot_cpu(void)
dc1e35c6
SS
502{
503 unsigned int eax, ebx, ecx, edx;
504
ee813d53
RR
505 if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
506 WARN(1, KERN_ERR "XSTATE_CPUID missing\n");
507 return;
508 }
509
510 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
6152e4b1 511 pcntxt_mask = eax + ((u64)edx << 32);
dc1e35c6 512
6152e4b1 513 if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) {
c767a54b 514 pr_err("FP/SSE not shown under xsave features 0x%llx\n",
6152e4b1 515 pcntxt_mask);
dc1e35c6
SS
516 BUG();
517 }
518
519 /*
a30469e7 520 * Support only the state known to OS.
dc1e35c6 521 */
6152e4b1 522 pcntxt_mask = pcntxt_mask & XCNTXT_MASK;
97e80a70 523
1cff92d8 524 xstate_enable();
dc1e35c6
SS
525
526 /*
527 * Recompute the context size for enabled features
528 */
ee813d53 529 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
dc1e35c6
SS
530 xstate_size = ebx;
531
5b3efd50 532 update_regset_xstate_info(xstate_size, pcntxt_mask);
c37b5efe
SS
533 prepare_fx_sw_frame();
534
dc1e35c6
SS
535 setup_xstate_init();
536
c767a54b
JP
537 pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n",
538 pcntxt_mask, xstate_size);
dc1e35c6 539}
82d4150c 540
1cff92d8
PA
541/*
542 * For the very first instance, this calls xstate_enable_boot_cpu();
543 * for all subsequent instances, this calls xstate_enable().
544 *
545 * This is somewhat obfuscated due to the lack of powerful enough
546 * overrides for the section checks.
547 */
82d4150c
RR
548void __cpuinit xsave_init(void)
549{
1cff92d8
PA
550 static __refdata void (*next_func)(void) = xstate_enable_boot_cpu;
551 void (*this_func)(void);
552
0e49bf66
RR
553 if (!cpu_has_xsave)
554 return;
555
1cff92d8
PA
556 this_func = next_func;
557 next_func = xstate_enable;
558 this_func();
82d4150c 559}