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KVM: x86: Fix wrong masking on relative jump/call
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
6aa8b732 169
820207c8 170#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 171
d0e53325
AK		 172#define X2(x...) x, x
173#define X3(x...) X2(x), x
174#define X4(x...) X2(x), X2(x)
175#define X5(x...) X4(x), x
176#define X6(x...) X4(x), X2(x)
177#define X7(x...) X4(x), X3(x)
178#define X8(x...) X4(x), X4(x)
179#define X16(x...) X8(x), X8(x)
83babbca 180
e28bbd44
AK		 181#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
182#define FASTOP_SIZE 8
183
184/*
185 * fastop functions have a special calling convention:
186 *
017da7b6
AK		 187 * dst: rax (in/out)
188 * src: rdx (in/out)
e28bbd44
AK		 189 * src2: rcx (in)
190 * flags: rflags (in/out)
b8c0b6ae 191 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 192 *
193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
194 * different operand sizes can be reached by calculation, rather than a jump
195 * table (which would be bigger than the code).
196 *
197 * fastop functions are declared as taking a never-defined fastop parameter,
198 * so they can't be called from C directly.
199 */
200
201struct fastop;
202
d65b1dee 203struct opcode {
b1ea50b2
AK		 204 u64 flags : 56;
205 u64 intercept : 8;
120df890 206 union {
ef65c889 207 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 208 const struct opcode *group;
209 const struct group_dual *gdual;
210 const struct gprefix *gprefix;
045a282c 211 const struct escape *esc;
e28bbd44 212 void (*fastop)(struct fastop *fake);
120df890 213 } u;
d09beabd 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 215};
216
217struct group_dual {
218 struct opcode mod012[8];
219 struct opcode mod3[8];
d65b1dee
AK		 220};
221
0d7cdee8
AK		 222struct gprefix {
223 struct opcode pfx_no;
224 struct opcode pfx_66;
225 struct opcode pfx_f2;
226 struct opcode pfx_f3;
227};
228
045a282c
GN		 229struct escape {
230 struct opcode op[8];
231 struct opcode high[64];
232};
233
6aa8b732 234/* EFLAGS bit definitions. */
d4c6a154
GN		 235#define EFLG_ID (1<<21)
236#define EFLG_VIP (1<<20)
237#define EFLG_VIF (1<<19)
238#define EFLG_AC (1<<18)
b1d86143
AP		 239#define EFLG_VM (1<<17)
240#define EFLG_RF (1<<16)
d4c6a154
GN		 241#define EFLG_IOPL (3<<12)
242#define EFLG_NT (1<<14)
6aa8b732
AK		 243#define EFLG_OF (1<<11)
244#define EFLG_DF (1<<10)
b1d86143 245#define EFLG_IF (1<<9)
d4c6a154 246#define EFLG_TF (1<<8)
6aa8b732
AK		 247#define EFLG_SF (1<<7)
248#define EFLG_ZF (1<<6)
249#define EFLG_AF (1<<4)
250#define EFLG_PF (1<<2)
251#define EFLG_CF (1<<0)
252
62bd430e
MG		 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254#define EFLG_RESERVED_ONE_MASK 2
255
dd856efa
AK		 256static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
257{
258 if (!(ctxt->regs_valid & (1 << nr))) {
259 ctxt->regs_valid |= 1 << nr;
260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
261 }
262 return ctxt->_regs[nr];
263}
264
265static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->regs_dirty |= 1 << nr;
269 return &ctxt->_regs[nr];
270}
271
272static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 reg_read(ctxt, nr);
275 return reg_write(ctxt, nr);
276}
277
278static void writeback_registers(struct x86_emulate_ctxt *ctxt)
279{
280 unsigned reg;
281
282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
284}
285
286static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
287{
288 ctxt->regs_dirty = 0;
289 ctxt->regs_valid = 0;
290}
291
6aa8b732
AK		 292/*
293 * These EFLAGS bits are restored from saved value during emulation, and
294 * any changes are written back to the saved value after emulation.
295 */
296#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
297
dda96d8f
AK		 298#ifdef CONFIG_X86_64
299#define ON64(x) x
300#else
301#define ON64(x)
302#endif
303
4d758349
AK		 304static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
305
b7d491e7
AK		 306#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
307#define FOP_RET "ret \n\t"
308
309#define FOP_START(op) \
310 extern void em_##op(struct fastop *fake); \
311 asm(".pushsection .text, \"ax\" \n\t" \
312 ".global em_" #op " \n\t" \
313 FOP_ALIGN \
314 "em_" #op ": \n\t"
315
316#define FOP_END \
317 ".popsection")
318
0bdea068
AK		 319#define FOPNOP() FOP_ALIGN FOP_RET
320
b7d491e7 321#define FOP1E(op, dst) \
b8c0b6ae
AK		 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
323
324#define FOP1EEX(op, dst) \
325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 326
327#define FASTOP1(op) \
328 FOP_START(op) \
329 FOP1E(op##b, al) \
330 FOP1E(op##w, ax) \
331 FOP1E(op##l, eax) \
332 ON64(FOP1E(op##q, rax)) \
333 FOP_END
334
b9fa409b
AK		 335/* 1-operand, using src2 (for MUL/DIV r/m) */
336#define FASTOP1SRC2(op, name) \
337 FOP_START(name) \
338 FOP1E(op, cl) \
339 FOP1E(op, cx) \
340 FOP1E(op, ecx) \
341 ON64(FOP1E(op, rcx)) \
342 FOP_END
343
b8c0b6ae
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
345#define FASTOP1SRC2EX(op, name) \
346 FOP_START(name) \
347 FOP1EEX(op, cl) \
348 FOP1EEX(op, cx) \
349 FOP1EEX(op, ecx) \
350 ON64(FOP1EEX(op, rcx)) \
351 FOP_END
352
f7857f35
AK		 353#define FOP2E(op, dst, src) \
354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
355
356#define FASTOP2(op) \
357 FOP_START(op) \
017da7b6
AK		 358 FOP2E(op##b, al, dl) \
359 FOP2E(op##w, ax, dx) \
360 FOP2E(op##l, eax, edx) \
361 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 362 FOP_END
363
11c363ba
AK		 364/* 2 operand, word only */
365#define FASTOP2W(op) \
366 FOP_START(op) \
367 FOPNOP() \
017da7b6
AK		 368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 371 FOP_END
372
007a3b54
AK		 373/* 2 operand, src is CL */
374#define FASTOP2CL(op) \
375 FOP_START(op) \
376 FOP2E(op##b, al, cl) \
377 FOP2E(op##w, ax, cl) \
378 FOP2E(op##l, eax, cl) \
379 ON64(FOP2E(op##q, rax, cl)) \
380 FOP_END
381
0bdea068
AK		 382#define FOP3E(op, dst, src, src2) \
383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
384
385/* 3-operand, word-only, src2=cl */
386#define FASTOP3WCL(op) \
387 FOP_START(op) \
388 FOPNOP() \
017da7b6
AK		 389 FOP3E(op##w, ax, dx, cl) \
390 FOP3E(op##l, eax, edx, cl) \
391 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 392 FOP_END
393
9ae9feba
AK		 394/* Special case for SETcc - 1 instruction per cc */
395#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
396
b8c0b6ae
AK		 397asm(".global kvm_fastop_exception \n"
398 "kvm_fastop_exception: xor %esi, %esi; ret");
399
9ae9feba
AK		 400FOP_START(setcc)
401FOP_SETCC(seto)
402FOP_SETCC(setno)
403FOP_SETCC(setc)
404FOP_SETCC(setnc)
405FOP_SETCC(setz)
406FOP_SETCC(setnz)
407FOP_SETCC(setbe)
408FOP_SETCC(setnbe)
409FOP_SETCC(sets)
410FOP_SETCC(setns)
411FOP_SETCC(setp)
412FOP_SETCC(setnp)
413FOP_SETCC(setl)
414FOP_SETCC(setnl)
415FOP_SETCC(setle)
416FOP_SETCC(setnle)
417FOP_END;
418
326f578f
PB		 419FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
420FOP_END;
421
8a76d7f2
JR		 422static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
423 enum x86_intercept intercept,
424 enum x86_intercept_stage stage)
425{
426 struct x86_instruction_info info = {
427 .intercept = intercept,
9dac77fa
AK		 428 .rep_prefix = ctxt->rep_prefix,
429 .modrm_mod = ctxt->modrm_mod,
430 .modrm_reg = ctxt->modrm_reg,
431 .modrm_rm = ctxt->modrm_rm,
432 .src_val = ctxt->src.val64,
6cbc5f5a 433 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 434 .src_bytes = ctxt->src.bytes,
435 .dst_bytes = ctxt->dst.bytes,
436 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 437 .next_rip = ctxt->eip,
438 };
439
2953538e 440 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 441}
442
f47cfa31
AK		 443static void assign_masked(ulong *dest, ulong src, ulong mask)
444{
445 *dest = (*dest & ~mask) | (src & mask);
446}
447
9dac77fa 448static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 449{
9dac77fa 450 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 451}
452
f47cfa31
AK		 453static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
454{
455 u16 sel;
456 struct desc_struct ss;
457
458 if (ctxt->mode == X86EMUL_MODE_PROT64)
459 return ~0UL;
460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
462}
463
612e89f0
AK		 464static int stack_size(struct x86_emulate_ctxt *ctxt)
465{
466 return (__fls(stack_mask(ctxt)) + 1) >> 3;
467}
468
6aa8b732 469/* Access/update address held in a register, based on addressing mode. */
e4706772 470static inline unsigned long
9dac77fa 471address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 472{
9dac77fa 473 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 474 return reg;
475 else
9dac77fa 476 return reg & ad_mask(ctxt);
e4706772
HH		 477}
478
479static inline unsigned long
9dac77fa 480register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 481{
9dac77fa 482 return address_mask(ctxt, reg);
e4706772
HH		 483}
484
5ad105e5
AK		 485static void masked_increment(ulong *reg, ulong mask, int inc)
486{
487 assign_masked(reg, *reg + inc, mask);
488}
489
7a957275 490static inline void
9dac77fa 491register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 492{
5ad105e5
AK		 493 ulong mask;
494
9dac77fa 495 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 496 mask = ~0UL;
7a957275 497 else
5ad105e5
AK		 498 mask = ad_mask(ctxt);
499 masked_increment(reg, mask, inc);
500}
501
502static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
503{
dd856efa 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 505}
6aa8b732 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
7b105ca2 514static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 515{
516 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
517 return 0;
518
7b105ca2 519 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 520}
521
35d3d4a1
AK		 522static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
523 u32 error, bool valid)
54b8486f 524{
e0ad0b47 525 WARN_ON(vec > 0x1f);
da9cb575
AK		 526 ctxt->exception.vector = vec;
527 ctxt->exception.error_code = error;
528 ctxt->exception.error_code_valid = valid;
35d3d4a1 529 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 530}
531
3b88e41a
JR		 532static int emulate_db(struct x86_emulate_ctxt *ctxt)
533{
534 return emulate_exception(ctxt, DB_VECTOR, 0, false);
535}
536
35d3d4a1 537static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 538{
35d3d4a1 539 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 540}
541
618ff15d
AK		 542static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
543{
544 return emulate_exception(ctxt, SS_VECTOR, err, true);
545}
546
35d3d4a1 547static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 548{
35d3d4a1 549 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 550}
551
35d3d4a1 552static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 553{
35d3d4a1 554 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 555}
556
34d1f490
AK		 557static int emulate_de(struct x86_emulate_ctxt *ctxt)
558{
35d3d4a1 559 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 560}
561
1253791d
AK		 562static int emulate_nm(struct x86_emulate_ctxt *ctxt)
563{
564 return emulate_exception(ctxt, NM_VECTOR, 0, false);
565}
566
05c83ec9
NA		 567static inline void assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
568{
569 switch (ctxt->op_bytes) {
570 case 2:
571 ctxt->_eip = (u16)dst;
572 break;
573 case 4:
574 ctxt->_eip = (u32)dst;
575 break;
576 case 8:
577 ctxt->_eip = dst;
578 break;
579 default:
580 WARN(1, "unsupported eip assignment size\n");
581 }
582}
583
584static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
585{
586 assign_eip_near(ctxt, ctxt->_eip + rel);
587}
588
1aa36616
AK		 589static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
590{
591 u16 selector;
592 struct desc_struct desc;
593
594 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
595 return selector;
596}
597
598static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
599 unsigned seg)
600{
601 u16 dummy;
602 u32 base3;
603 struct desc_struct desc;
604
605 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
606 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
607}
608
1c11b376
AK		 609/*
610 * x86 defines three classes of vector instructions: explicitly
611 * aligned, explicitly unaligned, and the rest, which change behaviour
612 * depending on whether they're AVX encoded or not.
613 *
614 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
615 * subject to the same check.
616 */
617static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
618{
619 if (likely(size < 16))
620 return false;
621
622 if (ctxt->d & Aligned)
623 return true;
624 else if (ctxt->d & Unaligned)
625 return false;
626 else if (ctxt->d & Avx)
627 return false;
628 else
629 return true;
630}
631
3d9b938e 632static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 633 struct segmented_address addr,
3d9b938e 634 unsigned size, bool write, bool fetch,
52fd8b44
AK		 635 ulong *linear)
636{
618ff15d
AK		 637 struct desc_struct desc;
638 bool usable;
52fd8b44 639 ulong la;
618ff15d 640 u32 lim;
1aa36616 641 u16 sel;
3a78a4f4 642 unsigned cpl;
52fd8b44 643
7b105ca2 644 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 645 switch (ctxt->mode) {
618ff15d
AK		 646 case X86EMUL_MODE_PROT64:
647 if (((signed long)la << 16) >> 16 != la)
648 return emulate_gp(ctxt, 0);
649 break;
650 default:
1aa36616
AK		 651 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
652 addr.seg);
618ff15d
AK		 653 if (!usable)
654 goto bad;
58b7825b
GN		 655 /* code segment in protected mode or read-only data segment */
656 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
657 || !(desc.type & 2)) && write)
618ff15d
AK		 658 goto bad;
659 /* unreadable code segment */
3d9b938e 660 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 661 goto bad;
662 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 663 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
664 (ctxt->d & NoBigReal)) {
665 /* la is between zero and 0xffff */
666 if (la > 0xffff || (u32)(la + size - 1) > 0xffff)
667 goto bad;
668 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d
AK		 669 /* expand-up segment */
670 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
671 goto bad;
672 } else {
fc058680 673 /* expand-down segment */
618ff15d
AK		 674 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
675 goto bad;
676 lim = desc.d ? 0xffffffff : 0xffff;
677 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
678 goto bad;
679 }
717746e3 680 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 681 if (!(desc.type & 8)) {
682 /* data segment */
683 if (cpl > desc.dpl)
684 goto bad;
685 } else if ((desc.type & 8) && !(desc.type & 4)) {
686 /* nonconforming code segment */
687 if (cpl != desc.dpl)
688 goto bad;
689 } else if ((desc.type & 8) && (desc.type & 4)) {
690 /* conforming code segment */
691 if (cpl < desc.dpl)
692 goto bad;
693 }
694 break;
695 }
9dac77fa 696 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 697 la &= (u32)-1;
1c11b376
AK		 698 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
699 return emulate_gp(ctxt, 0);
52fd8b44
AK		 700 *linear = la;
701 return X86EMUL_CONTINUE;
618ff15d
AK		 702bad:
703 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 704 return emulate_ss(ctxt, sel);
618ff15d 705 else
0afbe2f8 706 return emulate_gp(ctxt, sel);
52fd8b44
AK		 707}
708
3d9b938e
NE		 709static int linearize(struct x86_emulate_ctxt *ctxt,
710 struct segmented_address addr,
711 unsigned size, bool write,
712 ulong *linear)
713{
714 return __linearize(ctxt, addr, size, write, false, linear);
715}
716
717
3ca3ac4d
AK		 718static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
719 struct segmented_address addr,
720 void *data,
721 unsigned size)
722{
9fa088f4
AK		 723 int rc;
724 ulong linear;
725
83b8795a 726 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 727 if (rc != X86EMUL_CONTINUE)
728 return rc;
0f65dd70 729 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 730}
731
807941b1 732/*
285ca9e9 733 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 734 * boundary if they are not in fetch_cache yet.
735 */
9506d57d 736static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 737{
62266869 738 int rc;
719d5a9b 739 unsigned size;
285ca9e9 740 unsigned long linear;
17052f16 741 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 742 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 743 .ea = ctxt->eip + cur_size };
744
719d5a9b
PB		 745 size = 15UL ^ cur_size;
746 rc = __linearize(ctxt, addr, size, false, true, &linear);
747 if (unlikely(rc != X86EMUL_CONTINUE))
748 return rc;
749
750 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 751
752 /*
753 * One instruction can only straddle two pages,
754 * and one has been loaded at the beginning of
755 * x86_decode_insn. So, if not enough bytes
756 * still, we must have hit the 15-byte boundary.
757 */
758 if (unlikely(size < op_size))
285ca9e9 759 return X86EMUL_UNHANDLEABLE;
17052f16 760 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 761 size, &ctxt->exception);
762 if (unlikely(rc != X86EMUL_CONTINUE))
763 return rc;
17052f16 764 ctxt->fetch.end += size;
3e2815e9 765 return X86EMUL_CONTINUE;
62266869
AK		 766}
767
9506d57d
PB		 768static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
769 unsigned size)
62266869 770{
17052f16 771 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size))
9506d57d
PB		 772 return __do_insn_fetch_bytes(ctxt, size);
773 else
774 return X86EMUL_CONTINUE;
62266869
AK		 775}
776
67cbc90d 777/* Fetch next part of the instruction being emulated. */
e85a1085 778#define insn_fetch(_type, _ctxt) \
9506d57d 779({ _type _x; \
9506d57d
PB		 780 \
781 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 782 if (rc != X86EMUL_CONTINUE) \
783 goto done; \
9506d57d 784 ctxt->_eip += sizeof(_type); \
17052f16
PB		 785 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
786 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 787 _x; \
67cbc90d
TY		 788})
789
807941b1 790#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 791({ \
9506d57d 792 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 793 if (rc != X86EMUL_CONTINUE) \
794 goto done; \
9506d57d 795 ctxt->_eip += (_size); \
17052f16
PB		 796 memcpy(_arr, ctxt->fetch.ptr, _size); \
797 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 798})
799
1e3c5cb0
RR		 800/*
801 * Given the 'reg' portion of a ModRM byte, and a register block, return a
802 * pointer into the block that addresses the relevant register.
803 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
804 */
dd856efa 805static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 806 int byteop)
6aa8b732
AK		 807{
808 void *p;
aa9ac1a6 809 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 810
6aa8b732 811 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 812 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
813 else
814 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 815 return p;
816}
817
818static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 819 struct segmented_address addr,
6aa8b732
AK		 820 u16 *size, unsigned long *address, int op_bytes)
821{
822 int rc;
823
824 if (op_bytes == 2)
825 op_bytes = 3;
826 *address = 0;
3ca3ac4d 827 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 828 if (rc != X86EMUL_CONTINUE)
6aa8b732 829 return rc;
30b31ab6 830 addr.ea += 2;
3ca3ac4d 831 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 832 return rc;
833}
834
34b77652
AK		 835FASTOP2(add);
836FASTOP2(or);
837FASTOP2(adc);
838FASTOP2(sbb);
839FASTOP2(and);
840FASTOP2(sub);
841FASTOP2(xor);
842FASTOP2(cmp);
843FASTOP2(test);
844
b9fa409b
AK		 845FASTOP1SRC2(mul, mul_ex);
846FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 847FASTOP1SRC2EX(div, div_ex);
848FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 849
34b77652
AK		 850FASTOP3WCL(shld);
851FASTOP3WCL(shrd);
852
853FASTOP2W(imul);
854
855FASTOP1(not);
856FASTOP1(neg);
857FASTOP1(inc);
858FASTOP1(dec);
859
860FASTOP2CL(rol);
861FASTOP2CL(ror);
862FASTOP2CL(rcl);
863FASTOP2CL(rcr);
864FASTOP2CL(shl);
865FASTOP2CL(shr);
866FASTOP2CL(sar);
867
868FASTOP2W(bsf);
869FASTOP2W(bsr);
870FASTOP2W(bt);
871FASTOP2W(bts);
872FASTOP2W(btr);
873FASTOP2W(btc);
874
e47a5f5f
AK		 875FASTOP2(xadd);
876
9ae9feba 877static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 878{
9ae9feba
AK		 879 u8 rc;
880 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 881
9ae9feba 882 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 883 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 884 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
885 return rc;
bbe9abbd
NK		 886}
887
91ff3cb4
AK		 888static void fetch_register_operand(struct operand *op)
889{
890 switch (op->bytes) {
891 case 1:
892 op->val = *(u8 *)op->addr.reg;
893 break;
894 case 2:
895 op->val = *(u16 *)op->addr.reg;
896 break;
897 case 4:
898 op->val = *(u32 *)op->addr.reg;
899 break;
900 case 8:
901 op->val = *(u64 *)op->addr.reg;
902 break;
903 }
904}
905
1253791d
AK		 906static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
907{
908 ctxt->ops->get_fpu(ctxt);
909 switch (reg) {
89a87c67
MK		 910 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
911 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
912 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
913 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
914 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
915 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
916 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
917 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 918#ifdef CONFIG_X86_64
89a87c67
MK		 919 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
920 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
921 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
922 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
923 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
924 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
925 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
926 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 927#endif
928 default: BUG();
929 }
930 ctxt->ops->put_fpu(ctxt);
931}
932
933static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
934 int reg)
935{
936 ctxt->ops->get_fpu(ctxt);
937 switch (reg) {
89a87c67
MK		 938 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
939 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
940 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
941 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
942 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
943 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
944 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
945 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 946#ifdef CONFIG_X86_64
89a87c67
MK		 947 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
948 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
949 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
950 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
951 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
952 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
953 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
954 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 955#endif
956 default: BUG();
957 }
958 ctxt->ops->put_fpu(ctxt);
959}
960
cbe2c9d3
AK		 961static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
965 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
966 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
967 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
968 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
969 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
970 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
971 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
972 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
978static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
979{
980 ctxt->ops->get_fpu(ctxt);
981 switch (reg) {
982 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
983 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
984 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
985 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
986 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
987 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
988 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
989 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
990 default: BUG();
991 }
992 ctxt->ops->put_fpu(ctxt);
993}
994
045a282c
GN		 995static int em_fninit(struct x86_emulate_ctxt *ctxt)
996{
997 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
998 return emulate_nm(ctxt);
999
1000 ctxt->ops->get_fpu(ctxt);
1001 asm volatile("fninit");
1002 ctxt->ops->put_fpu(ctxt);
1003 return X86EMUL_CONTINUE;
1004}
1005
1006static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1007{
1008 u16 fcw;
1009
1010 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1011 return emulate_nm(ctxt);
1012
1013 ctxt->ops->get_fpu(ctxt);
1014 asm volatile("fnstcw %0": "+m"(fcw));
1015 ctxt->ops->put_fpu(ctxt);
1016
1017 /* force 2 byte destination */
1018 ctxt->dst.bytes = 2;
1019 ctxt->dst.val = fcw;
1020
1021 return X86EMUL_CONTINUE;
1022}
1023
1024static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1025{
1026 u16 fsw;
1027
1028 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1029 return emulate_nm(ctxt);
1030
1031 ctxt->ops->get_fpu(ctxt);
1032 asm volatile("fnstsw %0": "+m"(fsw));
1033 ctxt->ops->put_fpu(ctxt);
1034
1035 /* force 2 byte destination */
1036 ctxt->dst.bytes = 2;
1037 ctxt->dst.val = fsw;
1038
1039 return X86EMUL_CONTINUE;
1040}
1041
1253791d 1042static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1043 struct operand *op)
3c118e24 1044{
9dac77fa 1045 unsigned reg = ctxt->modrm_reg;
33615aa9 1046
9dac77fa
AK		 1047 if (!(ctxt->d & ModRM))
1048 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1049
9dac77fa 1050 if (ctxt->d & Sse) {
1253791d
AK		 1051 op->type = OP_XMM;
1052 op->bytes = 16;
1053 op->addr.xmm = reg;
1054 read_sse_reg(ctxt, &op->vec_val, reg);
1055 return;
1056 }
cbe2c9d3
AK		 1057 if (ctxt->d & Mmx) {
1058 reg &= 7;
1059 op->type = OP_MM;
1060 op->bytes = 8;
1061 op->addr.mm = reg;
1062 return;
1063 }
1253791d 1064
3c118e24 1065 op->type = OP_REG;
6d4d85ec
GN		 1066 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1067 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1068
91ff3cb4 1069 fetch_register_operand(op);
3c118e24
AK		 1070 op->orig_val = op->val;
1071}
1072
a6e3407b
AK		 1073static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1074{
1075 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1076 ctxt->modrm_seg = VCPU_SREG_SS;
1077}
1078
1c73ef66 1079static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1080 struct operand *op)
1c73ef66 1081{
1c73ef66 1082 u8 sib;
02357bdc 1083 int index_reg, base_reg, scale;
3e2815e9 1084 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1085 ulong modrm_ea = 0;
1c73ef66 1086
02357bdc
BD		 1087 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1088 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1089 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1090
02357bdc 1091 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1092 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1093 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1094 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1095
9b88ae99 1096 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1097 op->type = OP_REG;
9dac77fa 1098 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1099 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1100 ctxt->d & ByteOp);
9dac77fa 1101 if (ctxt->d & Sse) {
1253791d
AK		 1102 op->type = OP_XMM;
1103 op->bytes = 16;
9dac77fa
AK		 1104 op->addr.xmm = ctxt->modrm_rm;
1105 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1106 return rc;
1107 }
cbe2c9d3
AK		 1108 if (ctxt->d & Mmx) {
1109 op->type = OP_MM;
1110 op->bytes = 8;
bdc90722 1111 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1112 return rc;
1113 }
2dbd0dd7 1114 fetch_register_operand(op);
1c73ef66
AK		 1115 return rc;
1116 }
1117
2dbd0dd7
AK		 1118 op->type = OP_MEM;
1119
9dac77fa 1120 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1121 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1122 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1123 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1124 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1125
1126 /* 16-bit ModR/M decode. */
9dac77fa 1127 switch (ctxt->modrm_mod) {
1c73ef66 1128 case 0:
9dac77fa 1129 if (ctxt->modrm_rm == 6)
e85a1085 1130 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1131 break;
1132 case 1:
e85a1085 1133 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1134 break;
1135 case 2:
e85a1085 1136 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1137 break;
1138 }
9dac77fa 1139 switch (ctxt->modrm_rm) {
1c73ef66 1140 case 0:
2dbd0dd7 1141 modrm_ea += bx + si;
1c73ef66
AK		 1142 break;
1143 case 1:
2dbd0dd7 1144 modrm_ea += bx + di;
1c73ef66
AK		 1145 break;
1146 case 2:
2dbd0dd7 1147 modrm_ea += bp + si;
1c73ef66
AK		 1148 break;
1149 case 3:
2dbd0dd7 1150 modrm_ea += bp + di;
1c73ef66
AK		 1151 break;
1152 case 4:
2dbd0dd7 1153 modrm_ea += si;
1c73ef66
AK		 1154 break;
1155 case 5:
2dbd0dd7 1156 modrm_ea += di;
1c73ef66
AK		 1157 break;
1158 case 6:
9dac77fa 1159 if (ctxt->modrm_mod != 0)
2dbd0dd7 1160 modrm_ea += bp;
1c73ef66
AK		 1161 break;
1162 case 7:
2dbd0dd7 1163 modrm_ea += bx;
1c73ef66
AK		 1164 break;
1165 }
9dac77fa
AK		 1166 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1167 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1168 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1169 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1170 } else {
1171 /* 32/64-bit ModR/M decode. */
9dac77fa 1172 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1173 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1174 index_reg |= (sib >> 3) & 7;
1175 base_reg |= sib & 7;
1176 scale = sib >> 6;
1177
9dac77fa 1178 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1179 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1180 else {
dd856efa 1181 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1182 adjust_modrm_seg(ctxt, base_reg);
1183 }
dc71d0f1 1184 if (index_reg != 4)
dd856efa 1185 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1186 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1187 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1188 ctxt->rip_relative = 1;
a6e3407b
AK		 1189 } else {
1190 base_reg = ctxt->modrm_rm;
dd856efa 1191 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1192 adjust_modrm_seg(ctxt, base_reg);
1193 }
9dac77fa 1194 switch (ctxt->modrm_mod) {
1c73ef66 1195 case 0:
9dac77fa 1196 if (ctxt->modrm_rm == 5)
e85a1085 1197 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1198 break;
1199 case 1:
e85a1085 1200 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1201 break;
1202 case 2:
e85a1085 1203 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1204 break;
1205 }
1206 }
90de84f5 1207 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1208 if (ctxt->ad_bytes != 8)
1209 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1210
1c73ef66
AK		 1211done:
1212 return rc;
1213}
1214
1215static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1216 struct operand *op)
1c73ef66 1217{
3e2815e9 1218 int rc = X86EMUL_CONTINUE;
1c73ef66 1219
2dbd0dd7 1220 op->type = OP_MEM;
9dac77fa 1221 switch (ctxt->ad_bytes) {
1c73ef66 1222 case 2:
e85a1085 1223 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1224 break;
1225 case 4:
e85a1085 1226 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1227 break;
1228 case 8:
e85a1085 1229 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1230 break;
1231 }
1232done:
1233 return rc;
1234}
1235
9dac77fa 1236static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1237{
7129eeca 1238 long sv = 0, mask;
35c843c4 1239
9dac77fa 1240 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1241 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1242
9dac77fa
AK		 1243 if (ctxt->src.bytes == 2)
1244 sv = (s16)ctxt->src.val & (s16)mask;
1245 else if (ctxt->src.bytes == 4)
1246 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1247 else
1248 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1249
9dac77fa 1250 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1251 }
ba7ff2b7
WY		 1252
1253 /* only subword offset */
9dac77fa 1254 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1255}
1256
dde7e6d1 1257static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1258 unsigned long addr, void *dest, unsigned size)
6aa8b732 1259{
dde7e6d1 1260 int rc;
9dac77fa 1261 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1262
f23b070e
XG		 1263 if (mc->pos < mc->end)
1264 goto read_cached;
6aa8b732 1265
f23b070e
XG		 1266 WARN_ON((mc->end + size) >= sizeof(mc->data));
1267
1268 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1269 &ctxt->exception);
1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
1272
1273 mc->end += size;
1274
1275read_cached:
1276 memcpy(dest, mc->data + mc->pos, size);
1277 mc->pos += size;
dde7e6d1
AK		 1278 return X86EMUL_CONTINUE;
1279}
6aa8b732 1280
3ca3ac4d
AK		 1281static int segmented_read(struct x86_emulate_ctxt *ctxt,
1282 struct segmented_address addr,
1283 void *data,
1284 unsigned size)
1285{
9fa088f4
AK		 1286 int rc;
1287 ulong linear;
1288
83b8795a 1289 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1290 if (rc != X86EMUL_CONTINUE)
1291 return rc;
7b105ca2 1292 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1293}
1294
1295static int segmented_write(struct x86_emulate_ctxt *ctxt,
1296 struct segmented_address addr,
1297 const void *data,
1298 unsigned size)
1299{
9fa088f4
AK		 1300 int rc;
1301 ulong linear;
1302
83b8795a 1303 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1304 if (rc != X86EMUL_CONTINUE)
1305 return rc;
0f65dd70
AK		 1306 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1307 &ctxt->exception);
3ca3ac4d
AK		 1308}
1309
1310static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1311 struct segmented_address addr,
1312 const void *orig_data, const void *data,
1313 unsigned size)
1314{
9fa088f4
AK		 1315 int rc;
1316 ulong linear;
1317
83b8795a 1318 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1319 if (rc != X86EMUL_CONTINUE)
1320 return rc;
0f65dd70
AK		 1321 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1322 size, &ctxt->exception);
3ca3ac4d
AK		 1323}
1324
dde7e6d1 1325static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1326 unsigned int size, unsigned short port,
1327 void *dest)
1328{
9dac77fa 1329 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1330
dde7e6d1 1331 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1332 unsigned int in_page, n;
9dac77fa 1333 unsigned int count = ctxt->rep_prefix ?
dd856efa 1334 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1335 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1336 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1337 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1338 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1339 if (n == 0)
1340 n = 1;
1341 rc->pos = rc->end = 0;
7b105ca2 1342 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1343 return 0;
1344 rc->end = n * size;
6aa8b732
AK		 1345 }
1346
e6e39f04
NA		 1347 if (ctxt->rep_prefix && (ctxt->d & String) &&
1348 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1349 ctxt->dst.data = rc->data + rc->pos;
1350 ctxt->dst.type = OP_MEM_STR;
1351 ctxt->dst.count = (rc->end - rc->pos) / size;
1352 rc->pos = rc->end;
1353 } else {
1354 memcpy(dest, rc->data + rc->pos, size);
1355 rc->pos += size;
1356 }
dde7e6d1
AK		 1357 return 1;
1358}
6aa8b732 1359
7f3d35fd
KW		 1360static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1361 u16 index, struct desc_struct *desc)
1362{
1363 struct desc_ptr dt;
1364 ulong addr;
1365
1366 ctxt->ops->get_idt(ctxt, &dt);
1367
1368 if (dt.size < index * 8 + 7)
1369 return emulate_gp(ctxt, index << 3 | 0x2);
1370
1371 addr = dt.address + index * 8;
1372 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1373 &ctxt->exception);
1374}
1375
dde7e6d1 1376static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1377 u16 selector, struct desc_ptr *dt)
1378{
0225fb50 1379 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1380 u32 base3 = 0;
7b105ca2 1381
dde7e6d1
AK		 1382 if (selector & 1 << 2) {
1383 struct desc_struct desc;
1aa36616
AK		 1384 u16 sel;
1385
dde7e6d1 1386 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1387 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1388 VCPU_SREG_LDTR))
dde7e6d1 1389 return;
e09d082c 1390
dde7e6d1 1391 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1392 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1393 } else
4bff1e86 1394 ops->get_gdt(ctxt, dt);
dde7e6d1 1395}
120df890 1396
dde7e6d1
AK		 1397/* allowed just for 8 bytes segments */
1398static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1399 u16 selector, struct desc_struct *desc,
1400 ulong *desc_addr_p)
dde7e6d1
AK		 1401{
1402 struct desc_ptr dt;
1403 u16 index = selector >> 3;
dde7e6d1 1404 ulong addr;
120df890 1405
7b105ca2 1406 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1407
35d3d4a1
AK		 1408 if (dt.size < index * 8 + 7)
1409 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1410
e919464b 1411 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1412 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1413 &ctxt->exception);
dde7e6d1 1414}
ef65c889 1415
dde7e6d1
AK		 1416/* allowed just for 8 bytes segments */
1417static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1418 u16 selector, struct desc_struct *desc)
1419{
1420 struct desc_ptr dt;
1421 u16 index = selector >> 3;
dde7e6d1 1422 ulong addr;
6aa8b732 1423
7b105ca2 1424 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1425
35d3d4a1
AK		 1426 if (dt.size < index * 8 + 7)
1427 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1428
dde7e6d1 1429 addr = dt.address + index * 8;
7b105ca2
TY		 1430 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1431 &ctxt->exception);
dde7e6d1 1432}
c7e75a3d 1433
5601d05b 1434/* Does not support long mode */
2356aaeb 1435static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1436 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1437{
869be99c 1438 struct desc_struct seg_desc, old_desc;
2356aaeb 1439 u8 dpl, rpl;
dde7e6d1
AK		 1440 unsigned err_vec = GP_VECTOR;
1441 u32 err_code = 0;
1442 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1443 ulong desc_addr;
dde7e6d1 1444 int ret;
03ebebeb 1445 u16 dummy;
e37a75a1 1446 u32 base3 = 0;
69f55cb1 1447
dde7e6d1 1448 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1449
f8da94e9
KW		 1450 if (ctxt->mode == X86EMUL_MODE_REAL) {
1451 /* set real mode segment descriptor (keep limit etc. for
1452 * unreal mode) */
03ebebeb 1453 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1454 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1455 goto load;
f8da94e9
KW		 1456 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1457 /* VM86 needs a clean new segment descriptor */
1458 set_desc_base(&seg_desc, selector << 4);
1459 set_desc_limit(&seg_desc, 0xffff);
1460 seg_desc.type = 3;
1461 seg_desc.p = 1;
1462 seg_desc.s = 1;
1463 seg_desc.dpl = 3;
1464 goto load;
dde7e6d1
AK		 1465 }
1466
79d5b4c3 1467 rpl = selector & 3;
79d5b4c3
AK		 1468
1469 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1470 if ((seg == VCPU_SREG_CS
1471 || (seg == VCPU_SREG_SS
1472 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1473 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1474 && null_selector)
1475 goto exception;
1476
1477 /* TR should be in GDT only */
1478 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1479 goto exception;
1480
1481 if (null_selector) /* for NULL selector skip all following checks */
1482 goto load;
1483
e919464b 1484 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1485 if (ret != X86EMUL_CONTINUE)
1486 return ret;
1487
1488 err_code = selector & 0xfffc;
15fc0752 1489 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1490
fc058680 1491 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1492 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1493 goto exception;
1494
1495 if (!seg_desc.p) {
1496 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1497 goto exception;
1498 }
1499
dde7e6d1 1500 dpl = seg_desc.dpl;
dde7e6d1
AK		 1501
1502 switch (seg) {
1503 case VCPU_SREG_SS:
1504 /*
1505 * segment is not a writable data segment or segment
1506 * selector's RPL != CPL or segment selector's RPL != CPL
1507 */
1508 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1509 goto exception;
6aa8b732 1510 break;
dde7e6d1
AK		 1511 case VCPU_SREG_CS:
1512 if (!(seg_desc.type & 8))
1513 goto exception;
1514
1515 if (seg_desc.type & 4) {
1516 /* conforming */
1517 if (dpl > cpl)
1518 goto exception;
1519 } else {
1520 /* nonconforming */
1521 if (rpl > cpl || dpl != cpl)
1522 goto exception;
1523 }
040c8dc8
NA		 1524 /* in long-mode d/b must be clear if l is set */
1525 if (seg_desc.d && seg_desc.l) {
1526 u64 efer = 0;
1527
1528 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1529 if (efer & EFER_LMA)
1530 goto exception;
1531 }
1532
dde7e6d1
AK		 1533 /* CS(RPL) <- CPL */
1534 selector = (selector & 0xfffc) | cpl;
6aa8b732 1535 break;
dde7e6d1
AK		 1536 case VCPU_SREG_TR:
1537 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1538 goto exception;
869be99c
AK		 1539 old_desc = seg_desc;
1540 seg_desc.type |= 2; /* busy */
1541 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1542 sizeof(seg_desc), &ctxt->exception);
1543 if (ret != X86EMUL_CONTINUE)
1544 return ret;
dde7e6d1
AK		 1545 break;
1546 case VCPU_SREG_LDTR:
1547 if (seg_desc.s || seg_desc.type != 2)
1548 goto exception;
1549 break;
1550 default: /* DS, ES, FS, or GS */
4e62417b 1551 /*
dde7e6d1
AK		 1552 * segment is not a data or readable code segment or
1553 * ((segment is a data or nonconforming code segment)
1554 * and (both RPL and CPL > DPL))
4e62417b 1555 */
dde7e6d1
AK		 1556 if ((seg_desc.type & 0xa) == 0x8 ||
1557 (((seg_desc.type & 0xc) != 0xc) &&
1558 (rpl > dpl && cpl > dpl)))
1559 goto exception;
6aa8b732 1560 break;
dde7e6d1
AK		 1561 }
1562
1563 if (seg_desc.s) {
1564 /* mark segment as accessed */
1565 seg_desc.type |= 1;
7b105ca2 1566 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1567 if (ret != X86EMUL_CONTINUE)
1568 return ret;
e37a75a1
NA		 1569 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1570 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1571 sizeof(base3), &ctxt->exception);
1572 if (ret != X86EMUL_CONTINUE)
1573 return ret;
dde7e6d1
AK		 1574 }
1575load:
e37a75a1 1576 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1577 return X86EMUL_CONTINUE;
1578exception:
592f0858 1579 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1580}
1581
2356aaeb
PB		 1582static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1583 u16 selector, int seg)
1584{
1585 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1586 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1587}
1588
31be40b3
WY		 1589static void write_register_operand(struct operand *op)
1590{
1591 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1592 switch (op->bytes) {
1593 case 1:
1594 *(u8 *)op->addr.reg = (u8)op->val;
1595 break;
1596 case 2:
1597 *(u16 *)op->addr.reg = (u16)op->val;
1598 break;
1599 case 4:
1600 *op->addr.reg = (u32)op->val;
1601 break; /* 64b: zero-extend */
1602 case 8:
1603 *op->addr.reg = op->val;
1604 break;
1605 }
1606}
1607
fb32b1ed 1608static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1609{
fb32b1ed 1610 switch (op->type) {
dde7e6d1 1611 case OP_REG:
fb32b1ed 1612 write_register_operand(op);
6aa8b732 1613 break;
dde7e6d1 1614 case OP_MEM:
9dac77fa 1615 if (ctxt->lock_prefix)
f5f87dfb
PB		 1616 return segmented_cmpxchg(ctxt,
1617 op->addr.mem,
1618 &op->orig_val,
1619 &op->val,
1620 op->bytes);
1621 else
1622 return segmented_write(ctxt,
fb32b1ed 1623 op->addr.mem,
fb32b1ed
AK		 1624 &op->val,
1625 op->bytes);
a682e354 1626 break;
b3356bf0 1627 case OP_MEM_STR:
f5f87dfb
PB		 1628 return segmented_write(ctxt,
1629 op->addr.mem,
1630 op->data,
1631 op->bytes * op->count);
b3356bf0 1632 break;
1253791d 1633 case OP_XMM:
fb32b1ed 1634 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1635 break;
cbe2c9d3 1636 case OP_MM:
fb32b1ed 1637 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1638 break;
dde7e6d1
AK		 1639 case OP_NONE:
1640 /* no writeback */
414e6277 1641 break;
dde7e6d1 1642 default:
414e6277 1643 break;
6aa8b732 1644 }
dde7e6d1
AK		 1645 return X86EMUL_CONTINUE;
1646}
6aa8b732 1647
51ddff50 1648static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1649{
4179bb02 1650 struct segmented_address addr;
0dc8d10f 1651
5ad105e5 1652 rsp_increment(ctxt, -bytes);
dd856efa 1653 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1654 addr.seg = VCPU_SREG_SS;
1655
51ddff50
AK		 1656 return segmented_write(ctxt, addr, data, bytes);
1657}
1658
1659static int em_push(struct x86_emulate_ctxt *ctxt)
1660{
4179bb02 1661 /* Disable writeback. */
9dac77fa 1662 ctxt->dst.type = OP_NONE;
51ddff50 1663 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1664}
69f55cb1 1665
dde7e6d1 1666static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1667 void *dest, int len)
1668{
dde7e6d1 1669 int rc;
90de84f5 1670 struct segmented_address addr;
8b4caf66 1671
dd856efa 1672 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1673 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1674 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1675 if (rc != X86EMUL_CONTINUE)
1676 return rc;
1677
5ad105e5 1678 rsp_increment(ctxt, len);
dde7e6d1 1679 return rc;
8b4caf66
LV		 1680}
1681
c54fe504
TY		 1682static int em_pop(struct x86_emulate_ctxt *ctxt)
1683{
9dac77fa 1684 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1685}
1686
dde7e6d1 1687static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1688 void *dest, int len)
9de41573
GN		 1689{
1690 int rc;
dde7e6d1
AK		 1691 unsigned long val, change_mask;
1692 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1693 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1694
3b9be3bf 1695 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1696 if (rc != X86EMUL_CONTINUE)
1697 return rc;
9de41573 1698
dde7e6d1 1699 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1700 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1701
dde7e6d1
AK		 1702 switch(ctxt->mode) {
1703 case X86EMUL_MODE_PROT64:
1704 case X86EMUL_MODE_PROT32:
1705 case X86EMUL_MODE_PROT16:
1706 if (cpl == 0)
1707 change_mask |= EFLG_IOPL;
1708 if (cpl <= iopl)
1709 change_mask |= EFLG_IF;
1710 break;
1711 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1712 if (iopl < 3)
1713 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1714 change_mask |= EFLG_IF;
1715 break;
1716 default: /* real mode */
1717 change_mask |= (EFLG_IOPL | EFLG_IF);
1718 break;
9de41573 1719 }
dde7e6d1
AK		 1720
1721 *(unsigned long *)dest =
1722 (ctxt->eflags & ~change_mask) | (val & change_mask);
1723
1724 return rc;
9de41573
GN		 1725}
1726
62aaa2f0
TY		 1727static int em_popf(struct x86_emulate_ctxt *ctxt)
1728{
9dac77fa
AK		 1729 ctxt->dst.type = OP_REG;
1730 ctxt->dst.addr.reg = &ctxt->eflags;
1731 ctxt->dst.bytes = ctxt->op_bytes;
1732 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1733}
1734
612e89f0
AK		 1735static int em_enter(struct x86_emulate_ctxt *ctxt)
1736{
1737 int rc;
1738 unsigned frame_size = ctxt->src.val;
1739 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1740 ulong rbp;
612e89f0
AK		 1741
1742 if (nesting_level)
1743 return X86EMUL_UNHANDLEABLE;
1744
dd856efa
AK		 1745 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1746 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1747 if (rc != X86EMUL_CONTINUE)
1748 return rc;
dd856efa 1749 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1750 stack_mask(ctxt));
dd856efa
AK		 1751 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1752 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1753 stack_mask(ctxt));
1754 return X86EMUL_CONTINUE;
1755}
1756
f47cfa31
AK		 1757static int em_leave(struct x86_emulate_ctxt *ctxt)
1758{
dd856efa 1759 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1760 stack_mask(ctxt));
dd856efa 1761 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1762}
1763
1cd196ea 1764static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1765{
1cd196ea
AK		 1766 int seg = ctxt->src2.val;
1767
9dac77fa 1768 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1769
4487b3b4 1770 return em_push(ctxt);
7b262e90
GN		 1771}
1772
1cd196ea 1773static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1774{
1cd196ea 1775 int seg = ctxt->src2.val;
dde7e6d1
AK		 1776 unsigned long selector;
1777 int rc;
38ba30ba 1778
9dac77fa 1779 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1780 if (rc != X86EMUL_CONTINUE)
1781 return rc;
1782
a5457e7b
PB		 1783 if (ctxt->modrm_reg == VCPU_SREG_SS)
1784 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1785
7b105ca2 1786 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1787 return rc;
38ba30ba
GN		 1788}
1789
b96a7fad 1790static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1791{
dd856efa 1792 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1793 int rc = X86EMUL_CONTINUE;
1794 int reg = VCPU_REGS_RAX;
38ba30ba 1795
dde7e6d1
AK		 1796 while (reg <= VCPU_REGS_RDI) {
1797 (reg == VCPU_REGS_RSP) ?
dd856efa 1798 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1799
4487b3b4 1800 rc = em_push(ctxt);
dde7e6d1
AK		 1801 if (rc != X86EMUL_CONTINUE)
1802 return rc;
38ba30ba 1803
dde7e6d1 1804 ++reg;
38ba30ba 1805 }
38ba30ba 1806
dde7e6d1 1807 return rc;
38ba30ba
GN		 1808}
1809
62aaa2f0
TY		 1810static int em_pushf(struct x86_emulate_ctxt *ctxt)
1811{
9dac77fa 1812 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1813 return em_push(ctxt);
1814}
1815
b96a7fad 1816static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1817{
dde7e6d1
AK		 1818 int rc = X86EMUL_CONTINUE;
1819 int reg = VCPU_REGS_RDI;
38ba30ba 1820
dde7e6d1
AK		 1821 while (reg >= VCPU_REGS_RAX) {
1822 if (reg == VCPU_REGS_RSP) {
5ad105e5 1823 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1824 --reg;
1825 }
38ba30ba 1826
dd856efa 1827 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1828 if (rc != X86EMUL_CONTINUE)
1829 break;
1830 --reg;
38ba30ba 1831 }
dde7e6d1 1832 return rc;
38ba30ba
GN		 1833}
1834
dd856efa 1835static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1836{
0225fb50 1837 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1838 int rc;
6e154e56
MG		 1839 struct desc_ptr dt;
1840 gva_t cs_addr;
1841 gva_t eip_addr;
1842 u16 cs, eip;
6e154e56
MG		 1843
1844 /* TODO: Add limit checks */
9dac77fa 1845 ctxt->src.val = ctxt->eflags;
4487b3b4 1846 rc = em_push(ctxt);
5c56e1cf
AK		 1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
6e154e56
MG		 1849
1850 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1851
9dac77fa 1852 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1853 rc = em_push(ctxt);
5c56e1cf
AK		 1854 if (rc != X86EMUL_CONTINUE)
1855 return rc;
6e154e56 1856
9dac77fa 1857 ctxt->src.val = ctxt->_eip;
4487b3b4 1858 rc = em_push(ctxt);
5c56e1cf
AK		 1859 if (rc != X86EMUL_CONTINUE)
1860 return rc;
1861
4bff1e86 1862 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1863
1864 eip_addr = dt.address + (irq << 2);
1865 cs_addr = dt.address + (irq << 2) + 2;
1866
0f65dd70 1867 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1868 if (rc != X86EMUL_CONTINUE)
1869 return rc;
1870
0f65dd70 1871 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1872 if (rc != X86EMUL_CONTINUE)
1873 return rc;
1874
7b105ca2 1875 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1876 if (rc != X86EMUL_CONTINUE)
1877 return rc;
1878
9dac77fa 1879 ctxt->_eip = eip;
6e154e56
MG		 1880
1881 return rc;
1882}
1883
dd856efa
AK		 1884int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1885{
1886 int rc;
1887
1888 invalidate_registers(ctxt);
1889 rc = __emulate_int_real(ctxt, irq);
1890 if (rc == X86EMUL_CONTINUE)
1891 writeback_registers(ctxt);
1892 return rc;
1893}
1894
7b105ca2 1895static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1896{
1897 switch(ctxt->mode) {
1898 case X86EMUL_MODE_REAL:
dd856efa 1899 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1900 case X86EMUL_MODE_VM86:
1901 case X86EMUL_MODE_PROT16:
1902 case X86EMUL_MODE_PROT32:
1903 case X86EMUL_MODE_PROT64:
1904 default:
1905 /* Protected mode interrupts unimplemented yet */
1906 return X86EMUL_UNHANDLEABLE;
1907 }
1908}
1909
7b105ca2 1910static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1911{
dde7e6d1
AK		 1912 int rc = X86EMUL_CONTINUE;
1913 unsigned long temp_eip = 0;
1914 unsigned long temp_eflags = 0;
1915 unsigned long cs = 0;
1916 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1917 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1918 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1919 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1920
dde7e6d1 1921 /* TODO: Add stack limit check */
38ba30ba 1922
9dac77fa 1923 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1924
dde7e6d1
AK		 1925 if (rc != X86EMUL_CONTINUE)
1926 return rc;
38ba30ba 1927
35d3d4a1
AK		 1928 if (temp_eip & ~0xffff)
1929 return emulate_gp(ctxt, 0);
38ba30ba 1930
9dac77fa 1931 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1932
dde7e6d1
AK		 1933 if (rc != X86EMUL_CONTINUE)
1934 return rc;
38ba30ba 1935
9dac77fa 1936 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1937
dde7e6d1
AK		 1938 if (rc != X86EMUL_CONTINUE)
1939 return rc;
38ba30ba 1940
7b105ca2 1941 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1942
dde7e6d1
AK		 1943 if (rc != X86EMUL_CONTINUE)
1944 return rc;
38ba30ba 1945
9dac77fa 1946 ctxt->_eip = temp_eip;
38ba30ba 1947
38ba30ba 1948
9dac77fa 1949 if (ctxt->op_bytes == 4)
dde7e6d1 1950 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1951 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1952 ctxt->eflags &= ~0xffff;
1953 ctxt->eflags |= temp_eflags;
38ba30ba 1954 }
dde7e6d1
AK		 1955
1956 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1957 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1958
1959 return rc;
38ba30ba
GN		 1960}
1961
e01991e7 1962static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1963{
dde7e6d1
AK		 1964 switch(ctxt->mode) {
1965 case X86EMUL_MODE_REAL:
7b105ca2 1966 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1967 case X86EMUL_MODE_VM86:
1968 case X86EMUL_MODE_PROT16:
1969 case X86EMUL_MODE_PROT32:
1970 case X86EMUL_MODE_PROT64:
c37eda13 1971 default:
dde7e6d1
AK		 1972 /* iret from protected mode unimplemented yet */
1973 return X86EMUL_UNHANDLEABLE;
c37eda13 1974 }
c37eda13
WY		 1975}
1976
d2f62766
TY		 1977static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1978{
d2f62766
TY		 1979 int rc;
1980 unsigned short sel;
1981
9dac77fa 1982 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1983
7b105ca2 1984 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
1987
9dac77fa
AK		 1988 ctxt->_eip = 0;
1989 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1990 return X86EMUL_CONTINUE;
1991}
1992
51187683 1993static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1994{
4179bb02 1995 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1996
9dac77fa 1997 switch (ctxt->modrm_reg) {
d19292e4
MG		 1998 case 2: /* call near abs */ {
1999 long int old_eip;
9dac77fa
AK		 2000 old_eip = ctxt->_eip;
2001 ctxt->_eip = ctxt->src.val;
2002 ctxt->src.val = old_eip;
4487b3b4 2003 rc = em_push(ctxt);
d19292e4
MG		 2004 break;
2005 }
8cdbd2c9 2006 case 4: /* jmp abs */
9dac77fa 2007 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2008 break;
d2f62766
TY		 2009 case 5: /* jmp far */
2010 rc = em_jmp_far(ctxt);
2011 break;
8cdbd2c9 2012 case 6: /* push */
4487b3b4 2013 rc = em_push(ctxt);
8cdbd2c9 2014 break;
8cdbd2c9 2015 }
4179bb02 2016 return rc;
8cdbd2c9
LV		 2017}
2018
e0dac408 2019static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2020{
9dac77fa 2021 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2022
aaa05f24
NA		 2023 if (ctxt->dst.bytes == 16)
2024 return X86EMUL_UNHANDLEABLE;
2025
dd856efa
AK		 2026 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2027 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2028 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2029 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2030 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2031 } else {
dd856efa
AK		 2032 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2033 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2034
05f086f8 2035 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2036 }
1b30eaa8 2037 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2038}
2039
ebda02c2
TY		 2040static int em_ret(struct x86_emulate_ctxt *ctxt)
2041{
9dac77fa
AK		 2042 ctxt->dst.type = OP_REG;
2043 ctxt->dst.addr.reg = &ctxt->_eip;
2044 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2045 return em_pop(ctxt);
2046}
2047
e01991e7 2048static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2049{
a77ab5ea
AK		 2050 int rc;
2051 unsigned long cs;
9e8919ae 2052 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2053
9dac77fa 2054 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2055 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2056 return rc;
9dac77fa
AK		 2057 if (ctxt->op_bytes == 4)
2058 ctxt->_eip = (u32)ctxt->_eip;
2059 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2060 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2061 return rc;
9e8919ae
NA		 2062 /* Outer-privilege level return is not implemented */
2063 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2064 return X86EMUL_UNHANDLEABLE;
7b105ca2 2065 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2066 return rc;
2067}
2068
3261107e
BR		 2069static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2070{
2071 int rc;
2072
2073 rc = em_ret_far(ctxt);
2074 if (rc != X86EMUL_CONTINUE)
2075 return rc;
2076 rsp_increment(ctxt, ctxt->src.val);
2077 return X86EMUL_CONTINUE;
2078}
2079
e940b5c2
TY		 2080static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2081{
2082 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2083 ctxt->dst.orig_val = ctxt->dst.val;
2084 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2085 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2086 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2087 fastop(ctxt, em_cmp);
e940b5c2
TY		 2088
2089 if (ctxt->eflags & EFLG_ZF) {
2090 /* Success: write back to memory. */
2091 ctxt->dst.val = ctxt->src.orig_val;
2092 } else {
2093 /* Failure: write the value we saw to EAX. */
2094 ctxt->dst.type = OP_REG;
dd856efa 2095 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2096 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2097 }
2098 return X86EMUL_CONTINUE;
2099}
2100
d4b4325f 2101static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2102{
d4b4325f 2103 int seg = ctxt->src2.val;
09b5f4d3
WY		 2104 unsigned short sel;
2105 int rc;
2106
9dac77fa 2107 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2108
7b105ca2 2109 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2110 if (rc != X86EMUL_CONTINUE)
2111 return rc;
2112
9dac77fa 2113 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2114 return rc;
2115}
2116
7b105ca2 2117static void
e66bb2cc 2118setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2119 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2120{
e66bb2cc 2121 cs->l = 0; /* will be adjusted later */
79168fd1 2122 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2123 cs->g = 1; /* 4kb granularity */
79168fd1 2124 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2125 cs->type = 0x0b; /* Read, Execute, Accessed */
2126 cs->s = 1;
2127 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2128 cs->p = 1;
2129 cs->d = 1;
99245b50 2130 cs->avl = 0;
e66bb2cc 2131
79168fd1
GN		 2132 set_desc_base(ss, 0); /* flat segment */
2133 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2134 ss->g = 1; /* 4kb granularity */
2135 ss->s = 1;
2136 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2137 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2138 ss->dpl = 0;
79168fd1 2139 ss->p = 1;
99245b50
GN		 2140 ss->l = 0;
2141 ss->avl = 0;
e66bb2cc
AP		 2142}
2143
1a18a69b
AK		 2144static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2145{
2146 u32 eax, ebx, ecx, edx;
2147
2148 eax = ecx = 0;
0017f93a
AK		 2149 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2150 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2151 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2152 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2153}
2154
c2226fc9
SB		 2155static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2156{
0225fb50 2157 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2158 u32 eax, ebx, ecx, edx;
2159
2160 /*
2161 * syscall should always be enabled in longmode - so only become
2162 * vendor specific (cpuid) if other modes are active...
2163 */
2164 if (ctxt->mode == X86EMUL_MODE_PROT64)
2165 return true;
2166
2167 eax = 0x00000000;
2168 ecx = 0x00000000;
0017f93a
AK		 2169 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2170 /*
2171 * Intel ("GenuineIntel")
2172 * remark: Intel CPUs only support "syscall" in 64bit
2173 * longmode. Also an 64bit guest with a
2174 * 32bit compat-app running will #UD !! While this
2175 * behaviour can be fixed (by emulating) into AMD
2176 * response - CPUs of AMD can't behave like Intel.
2177 */
2178 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2179 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2180 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2181 return false;
2182
2183 /* AMD ("AuthenticAMD") */
2184 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2185 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2186 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2187 return true;
2188
2189 /* AMD ("AMDisbetter!") */
2190 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2191 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2192 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2193 return true;
c2226fc9
SB		 2194
2195 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2196 return false;
2197}
2198
e01991e7 2199static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2200{
0225fb50 2201 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2202 struct desc_struct cs, ss;
e66bb2cc 2203 u64 msr_data;
79168fd1 2204 u16 cs_sel, ss_sel;
c2ad2bb3 2205 u64 efer = 0;
e66bb2cc
AP		 2206
2207 /* syscall is not available in real mode */
2e901c4c 2208 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2209 ctxt->mode == X86EMUL_MODE_VM86)
2210 return emulate_ud(ctxt);
e66bb2cc 2211
c2226fc9
SB		 2212 if (!(em_syscall_is_enabled(ctxt)))
2213 return emulate_ud(ctxt);
2214
c2ad2bb3 2215 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2216 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2217
c2226fc9
SB		 2218 if (!(efer & EFER_SCE))
2219 return emulate_ud(ctxt);
2220
717746e3 2221 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2222 msr_data >>= 32;
79168fd1
GN		 2223 cs_sel = (u16)(msr_data & 0xfffc);
2224 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2225
c2ad2bb3 2226 if (efer & EFER_LMA) {
79168fd1 2227 cs.d = 0;
e66bb2cc
AP		 2228 cs.l = 1;
2229 }
1aa36616
AK		 2230 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2231 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2232
dd856efa 2233 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2234 if (efer & EFER_LMA) {
e66bb2cc 2235#ifdef CONFIG_X86_64
6c6cb69b 2236 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2237
717746e3 2238 ops->get_msr(ctxt,
3fb1b5db
GN		 2239 ctxt->mode == X86EMUL_MODE_PROT64 ?
2240 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2241 ctxt->_eip = msr_data;
e66bb2cc 2242
717746e3 2243 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2244 ctxt->eflags &= ~msr_data;
e66bb2cc
AP		 2245#endif
2246 } else {
2247 /* legacy mode */
717746e3 2248 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2249 ctxt->_eip = (u32)msr_data;
e66bb2cc 2250
6c6cb69b 2251 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2252 }
2253
e54cfa97 2254 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2255}
2256
e01991e7 2257static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2258{
0225fb50 2259 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2260 struct desc_struct cs, ss;
8c604352 2261 u64 msr_data;
79168fd1 2262 u16 cs_sel, ss_sel;
c2ad2bb3 2263 u64 efer = 0;
8c604352 2264
7b105ca2 2265 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2266 /* inject #GP if in real mode */
35d3d4a1
AK		 2267 if (ctxt->mode == X86EMUL_MODE_REAL)
2268 return emulate_gp(ctxt, 0);
8c604352 2269
1a18a69b
AK		 2270 /*
2271 * Not recognized on AMD in compat mode (but is recognized in legacy
2272 * mode).
2273 */
2274 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2275 && !vendor_intel(ctxt))
2276 return emulate_ud(ctxt);
2277
8c604352
AP		 2278 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2279 * Therefore, we inject an #UD.
2280 */
35d3d4a1
AK		 2281 if (ctxt->mode == X86EMUL_MODE_PROT64)
2282 return emulate_ud(ctxt);
8c604352 2283
7b105ca2 2284 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2285
717746e3 2286 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2287 switch (ctxt->mode) {
2288 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2289 if ((msr_data & 0xfffc) == 0x0)
2290 return emulate_gp(ctxt, 0);
8c604352
AP		 2291 break;
2292 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2293 if (msr_data == 0x0)
2294 return emulate_gp(ctxt, 0);
8c604352 2295 break;
9d1b39a9
GN		 2296 default:
2297 break;
8c604352
AP		 2298 }
2299
6c6cb69b 2300 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2301 cs_sel = (u16)msr_data;
2302 cs_sel &= ~SELECTOR_RPL_MASK;
2303 ss_sel = cs_sel + 8;
2304 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2305 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2306 cs.d = 0;
8c604352
AP		 2307 cs.l = 1;
2308 }
2309
1aa36616
AK		 2310 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2311 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2312
717746e3 2313 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2314 ctxt->_eip = msr_data;
8c604352 2315
717746e3 2316 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2317 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2318
e54cfa97 2319 return X86EMUL_CONTINUE;
8c604352
AP		 2320}
2321
e01991e7 2322static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2323{
0225fb50 2324 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2325 struct desc_struct cs, ss;
4668f050
AP		 2326 u64 msr_data;
2327 int usermode;
1249b96e 2328 u16 cs_sel = 0, ss_sel = 0;
4668f050 2329
a0044755
GN		 2330 /* inject #GP if in real mode or Virtual 8086 mode */
2331 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2332 ctxt->mode == X86EMUL_MODE_VM86)
2333 return emulate_gp(ctxt, 0);
4668f050 2334
7b105ca2 2335 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2336
9dac77fa 2337 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2338 usermode = X86EMUL_MODE_PROT64;
2339 else
2340 usermode = X86EMUL_MODE_PROT32;
2341
2342 cs.dpl = 3;
2343 ss.dpl = 3;
717746e3 2344 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2345 switch (usermode) {
2346 case X86EMUL_MODE_PROT32:
79168fd1 2347 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2348 if ((msr_data & 0xfffc) == 0x0)
2349 return emulate_gp(ctxt, 0);
79168fd1 2350 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2351 break;
2352 case X86EMUL_MODE_PROT64:
79168fd1 2353 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2354 if (msr_data == 0x0)
2355 return emulate_gp(ctxt, 0);
79168fd1
GN		 2356 ss_sel = cs_sel + 8;
2357 cs.d = 0;
4668f050
AP		 2358 cs.l = 1;
2359 break;
2360 }
79168fd1
GN		 2361 cs_sel |= SELECTOR_RPL_MASK;
2362 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2363
1aa36616
AK		 2364 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2365 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2366
dd856efa
AK		 2367 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2368 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2369
e54cfa97 2370 return X86EMUL_CONTINUE;
4668f050
AP		 2371}
2372
7b105ca2 2373static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2374{
2375 int iopl;
2376 if (ctxt->mode == X86EMUL_MODE_REAL)
2377 return false;
2378 if (ctxt->mode == X86EMUL_MODE_VM86)
2379 return true;
2380 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2381 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2382}
2383
2384static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2385 u16 port, u16 len)
2386{
0225fb50 2387 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2388 struct desc_struct tr_seg;
5601d05b 2389 u32 base3;
f850e2e6 2390 int r;
1aa36616 2391 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2392 unsigned mask = (1 << len) - 1;
5601d05b 2393 unsigned long base;
f850e2e6 2394
1aa36616 2395 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2396 if (!tr_seg.p)
f850e2e6 2397 return false;
79168fd1 2398 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2399 return false;
5601d05b
GN		 2400 base = get_desc_base(&tr_seg);
2401#ifdef CONFIG_X86_64
2402 base |= ((u64)base3) << 32;
2403#endif
0f65dd70 2404 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2405 if (r != X86EMUL_CONTINUE)
2406 return false;
79168fd1 2407 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2408 return false;
0f65dd70 2409 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2410 if (r != X86EMUL_CONTINUE)
2411 return false;
2412 if ((perm >> bit_idx) & mask)
2413 return false;
2414 return true;
2415}
2416
2417static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2418 u16 port, u16 len)
2419{
4fc40f07
GN		 2420 if (ctxt->perm_ok)
2421 return true;
2422
7b105ca2
TY		 2423 if (emulator_bad_iopl(ctxt))
2424 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2425 return false;
4fc40f07
GN		 2426
2427 ctxt->perm_ok = true;
2428
f850e2e6
GN		 2429 return true;
2430}
2431
38ba30ba 2432static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2433 struct tss_segment_16 *tss)
2434{
9dac77fa 2435 tss->ip = ctxt->_eip;
38ba30ba 2436 tss->flag = ctxt->eflags;
dd856efa
AK		 2437 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2438 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2439 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2440 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2441 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2442 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2443 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2444 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2445
1aa36616
AK		 2446 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2447 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2448 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2449 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2450 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2451}
2452
2453static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2454 struct tss_segment_16 *tss)
2455{
38ba30ba 2456 int ret;
2356aaeb 2457 u8 cpl;
38ba30ba 2458
9dac77fa 2459 ctxt->_eip = tss->ip;
38ba30ba 2460 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2461 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2462 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2463 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2464 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2465 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2466 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2467 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2468 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2469
2470 /*
2471 * SDM says that segment selectors are loaded before segment
2472 * descriptors
2473 */
1aa36616
AK		 2474 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2475 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2476 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2477 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2478 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2479
2356aaeb
PB		 2480 cpl = tss->cs & 3;
2481
38ba30ba 2482 /*
fc058680 2483 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2484 * it is handled in a context of new task
2485 */
5045b468 2486 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2487 if (ret != X86EMUL_CONTINUE)
2488 return ret;
5045b468 2489 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2490 if (ret != X86EMUL_CONTINUE)
2491 return ret;
5045b468 2492 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2493 if (ret != X86EMUL_CONTINUE)
2494 return ret;
5045b468 2495 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2496 if (ret != X86EMUL_CONTINUE)
2497 return ret;
5045b468 2498 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2499 if (ret != X86EMUL_CONTINUE)
2500 return ret;
2501
2502 return X86EMUL_CONTINUE;
2503}
2504
2505static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2506 u16 tss_selector, u16 old_tss_sel,
2507 ulong old_tss_base, struct desc_struct *new_desc)
2508{
0225fb50 2509 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2510 struct tss_segment_16 tss_seg;
2511 int ret;
bcc55cba 2512 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2513
0f65dd70 2514 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2515 &ctxt->exception);
db297e3d 2516 if (ret != X86EMUL_CONTINUE)
38ba30ba 2517 /* FIXME: need to provide precise fault address */
38ba30ba 2518 return ret;
38ba30ba 2519
7b105ca2 2520 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2521
0f65dd70 2522 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2523 &ctxt->exception);
db297e3d 2524 if (ret != X86EMUL_CONTINUE)
38ba30ba 2525 /* FIXME: need to provide precise fault address */
38ba30ba 2526 return ret;
38ba30ba 2527
0f65dd70 2528 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2529 &ctxt->exception);
db297e3d 2530 if (ret != X86EMUL_CONTINUE)
38ba30ba 2531 /* FIXME: need to provide precise fault address */
38ba30ba 2532 return ret;
38ba30ba
GN		 2533
2534 if (old_tss_sel != 0xffff) {
2535 tss_seg.prev_task_link = old_tss_sel;
2536
0f65dd70 2537 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2538 &tss_seg.prev_task_link,
2539 sizeof tss_seg.prev_task_link,
0f65dd70 2540 &ctxt->exception);
db297e3d 2541 if (ret != X86EMUL_CONTINUE)
38ba30ba 2542 /* FIXME: need to provide precise fault address */
38ba30ba 2543 return ret;
38ba30ba
GN		 2544 }
2545
7b105ca2 2546 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2547}
2548
2549static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2550 struct tss_segment_32 *tss)
2551{
5c7411e2 2552 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2553 tss->eip = ctxt->_eip;
38ba30ba 2554 tss->eflags = ctxt->eflags;
dd856efa
AK		 2555 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2556 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2557 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2558 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2559 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2560 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2561 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2562 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2563
1aa36616
AK		 2564 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2565 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2566 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2567 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2568 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2569 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2570}
2571
2572static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2573 struct tss_segment_32 *tss)
2574{
38ba30ba 2575 int ret;
2356aaeb 2576 u8 cpl;
38ba30ba 2577
7b105ca2 2578 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2579 return emulate_gp(ctxt, 0);
9dac77fa 2580 ctxt->_eip = tss->eip;
38ba30ba 2581 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2582
2583 /* General purpose registers */
dd856efa
AK		 2584 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2585 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2586 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2587 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2588 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2589 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2590 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2591 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2592
2593 /*
2594 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2595 * descriptors. This is important because CPL checks will
2596 * use CS.RPL.
38ba30ba 2597 */
1aa36616
AK		 2598 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2599 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2600 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2601 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2602 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2603 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2604 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2605
4cee4798
KW		 2606 /*
2607 * If we're switching between Protected Mode and VM86, we need to make
2608 * sure to update the mode before loading the segment descriptors so
2609 * that the selectors are interpreted correctly.
4cee4798 2610 */
2356aaeb 2611 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2612 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2613 cpl = 3;
2614 } else {
4cee4798 2615 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2616 cpl = tss->cs & 3;
2617 }
4cee4798 2618
38ba30ba
GN		 2619 /*
2620 * Now load segment descriptors. If fault happenes at this stage
2621 * it is handled in a context of new task
2622 */
5045b468 2623 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
5045b468 2626 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2627 if (ret != X86EMUL_CONTINUE)
2628 return ret;
5045b468 2629 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2630 if (ret != X86EMUL_CONTINUE)
2631 return ret;
5045b468 2632 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2633 if (ret != X86EMUL_CONTINUE)
2634 return ret;
5045b468 2635 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2636 if (ret != X86EMUL_CONTINUE)
2637 return ret;
5045b468 2638 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2639 if (ret != X86EMUL_CONTINUE)
2640 return ret;
5045b468 2641 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2642 if (ret != X86EMUL_CONTINUE)
2643 return ret;
2644
2645 return X86EMUL_CONTINUE;
2646}
2647
2648static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2649 u16 tss_selector, u16 old_tss_sel,
2650 ulong old_tss_base, struct desc_struct *new_desc)
2651{
0225fb50 2652 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2653 struct tss_segment_32 tss_seg;
2654 int ret;
bcc55cba 2655 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2656 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2657 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2658
0f65dd70 2659 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2660 &ctxt->exception);
db297e3d 2661 if (ret != X86EMUL_CONTINUE)
38ba30ba 2662 /* FIXME: need to provide precise fault address */
38ba30ba 2663 return ret;
38ba30ba 2664
7b105ca2 2665 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2666
5c7411e2
NA		 2667 /* Only GP registers and segment selectors are saved */
2668 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2669 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2670 if (ret != X86EMUL_CONTINUE)
38ba30ba 2671 /* FIXME: need to provide precise fault address */
38ba30ba 2672 return ret;
38ba30ba 2673
0f65dd70 2674 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2675 &ctxt->exception);
db297e3d 2676 if (ret != X86EMUL_CONTINUE)
38ba30ba 2677 /* FIXME: need to provide precise fault address */
38ba30ba 2678 return ret;
38ba30ba
GN		 2679
2680 if (old_tss_sel != 0xffff) {
2681 tss_seg.prev_task_link = old_tss_sel;
2682
0f65dd70 2683 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2684 &tss_seg.prev_task_link,
2685 sizeof tss_seg.prev_task_link,
0f65dd70 2686 &ctxt->exception);
db297e3d 2687 if (ret != X86EMUL_CONTINUE)
38ba30ba 2688 /* FIXME: need to provide precise fault address */
38ba30ba 2689 return ret;
38ba30ba
GN		 2690 }
2691
7b105ca2 2692 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2693}
2694
2695static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2696 u16 tss_selector, int idt_index, int reason,
e269fb21 2697 bool has_error_code, u32 error_code)
38ba30ba 2698{
0225fb50 2699 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2700 struct desc_struct curr_tss_desc, next_tss_desc;
2701 int ret;
1aa36616 2702 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2703 ulong old_tss_base =
4bff1e86 2704 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2705 u32 desc_limit;
e919464b 2706 ulong desc_addr;
38ba30ba
GN		 2707
2708 /* FIXME: old_tss_base == ~0 ? */
2709
e919464b 2710 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2711 if (ret != X86EMUL_CONTINUE)
2712 return ret;
e919464b 2713 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2714 if (ret != X86EMUL_CONTINUE)
2715 return ret;
2716
2717 /* FIXME: check that next_tss_desc is tss */
2718
7f3d35fd
KW		 2719 /*
2720 * Check privileges. The three cases are task switch caused by...
2721 *
2722 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2723 * 2. Exception/IRQ/iret: No check is performed
fc058680 2724 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2725 */
2726 if (reason == TASK_SWITCH_GATE) {
2727 if (idt_index != -1) {
2728 /* Software interrupts */
2729 struct desc_struct task_gate_desc;
2730 int dpl;
2731
2732 ret = read_interrupt_descriptor(ctxt, idt_index,
2733 &task_gate_desc);
2734 if (ret != X86EMUL_CONTINUE)
2735 return ret;
2736
2737 dpl = task_gate_desc.dpl;
2738 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2739 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2740 }
2741 } else if (reason != TASK_SWITCH_IRET) {
2742 int dpl = next_tss_desc.dpl;
2743 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2744 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2745 }
2746
7f3d35fd 2747
ceffb459
GN		 2748 desc_limit = desc_limit_scaled(&next_tss_desc);
2749 if (!next_tss_desc.p ||
2750 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2751 desc_limit < 0x2b)) {
592f0858 2752 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2753 }
2754
2755 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2756 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2757 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2758 }
2759
2760 if (reason == TASK_SWITCH_IRET)
2761 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2762
2763 /* set back link to prev task only if NT bit is set in eflags
fc058680 2764 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2765 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2766 old_tss_sel = 0xffff;
2767
2768 if (next_tss_desc.type & 8)
7b105ca2 2769 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2770 old_tss_base, &next_tss_desc);
2771 else
7b105ca2 2772 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2773 old_tss_base, &next_tss_desc);
0760d448
JK		 2774 if (ret != X86EMUL_CONTINUE)
2775 return ret;
38ba30ba
GN		 2776
2777 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2778 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2779
2780 if (reason != TASK_SWITCH_IRET) {
2781 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2782 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2783 }
2784
717746e3 2785 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2786 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2787
e269fb21 2788 if (has_error_code) {
9dac77fa
AK		 2789 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2790 ctxt->lock_prefix = 0;
2791 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2792 ret = em_push(ctxt);
e269fb21
JK		 2793 }
2794
38ba30ba
GN		 2795 return ret;
2796}
2797
2798int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2799 u16 tss_selector, int idt_index, int reason,
e269fb21 2800 bool has_error_code, u32 error_code)
38ba30ba 2801{
38ba30ba
GN		 2802 int rc;
2803
dd856efa 2804 invalidate_registers(ctxt);
9dac77fa
AK		 2805 ctxt->_eip = ctxt->eip;
2806 ctxt->dst.type = OP_NONE;
38ba30ba 2807
7f3d35fd 2808 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2809 has_error_code, error_code);
38ba30ba 2810
dd856efa 2811 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2812 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2813 writeback_registers(ctxt);
2814 }
38ba30ba 2815
a0c0ab2f 2816 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2817}
2818
f3bd64c6
GN		 2819static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2820 struct operand *op)
a682e354 2821{
b3356bf0 2822 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2823
dd856efa
AK		 2824 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2825 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2826}
2827
7af04fc0
AK		 2828static int em_das(struct x86_emulate_ctxt *ctxt)
2829{
7af04fc0
AK		 2830 u8 al, old_al;
2831 bool af, cf, old_cf;
2832
2833 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2834 al = ctxt->dst.val;
7af04fc0
AK		 2835
2836 old_al = al;
2837 old_cf = cf;
2838 cf = false;
2839 af = ctxt->eflags & X86_EFLAGS_AF;
2840 if ((al & 0x0f) > 9 || af) {
2841 al -= 6;
2842 cf = old_cf | (al >= 250);
2843 af = true;
2844 } else {
2845 af = false;
2846 }
2847 if (old_al > 0x99 || old_cf) {
2848 al -= 0x60;
2849 cf = true;
2850 }
2851
9dac77fa 2852 ctxt->dst.val = al;
7af04fc0 2853 /* Set PF, ZF, SF */
9dac77fa
AK		 2854 ctxt->src.type = OP_IMM;
2855 ctxt->src.val = 0;
2856 ctxt->src.bytes = 1;
158de57f 2857 fastop(ctxt, em_or);
7af04fc0
AK		 2858 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2859 if (cf)
2860 ctxt->eflags |= X86_EFLAGS_CF;
2861 if (af)
2862 ctxt->eflags |= X86_EFLAGS_AF;
2863 return X86EMUL_CONTINUE;
2864}
2865
a035d5c6
PB		 2866static int em_aam(struct x86_emulate_ctxt *ctxt)
2867{
2868 u8 al, ah;
2869
2870 if (ctxt->src.val == 0)
2871 return emulate_de(ctxt);
2872
2873 al = ctxt->dst.val & 0xff;
2874 ah = al / ctxt->src.val;
2875 al %= ctxt->src.val;
2876
2877 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2878
2879 /* Set PF, ZF, SF */
2880 ctxt->src.type = OP_IMM;
2881 ctxt->src.val = 0;
2882 ctxt->src.bytes = 1;
2883 fastop(ctxt, em_or);
2884
2885 return X86EMUL_CONTINUE;
2886}
2887
7f662273
GN		 2888static int em_aad(struct x86_emulate_ctxt *ctxt)
2889{
2890 u8 al = ctxt->dst.val & 0xff;
2891 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2892
2893 al = (al + (ah * ctxt->src.val)) & 0xff;
2894
2895 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2896
f583c29b
GN		 2897 /* Set PF, ZF, SF */
2898 ctxt->src.type = OP_IMM;
2899 ctxt->src.val = 0;
2900 ctxt->src.bytes = 1;
2901 fastop(ctxt, em_or);
7f662273
GN		 2902
2903 return X86EMUL_CONTINUE;
2904}
2905
d4ddafcd
TY		 2906static int em_call(struct x86_emulate_ctxt *ctxt)
2907{
2908 long rel = ctxt->src.val;
2909
2910 ctxt->src.val = (unsigned long)ctxt->_eip;
2911 jmp_rel(ctxt, rel);
2912 return em_push(ctxt);
2913}
2914
0ef753b8
AK		 2915static int em_call_far(struct x86_emulate_ctxt *ctxt)
2916{
0ef753b8
AK		 2917 u16 sel, old_cs;
2918 ulong old_eip;
2919 int rc;
2920
1aa36616 2921 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2922 old_eip = ctxt->_eip;
0ef753b8 2923
9dac77fa 2924 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2925 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2926 return X86EMUL_CONTINUE;
2927
9dac77fa
AK		 2928 ctxt->_eip = 0;
2929 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2930
9dac77fa 2931 ctxt->src.val = old_cs;
4487b3b4 2932 rc = em_push(ctxt);
0ef753b8
AK		 2933 if (rc != X86EMUL_CONTINUE)
2934 return rc;
2935
9dac77fa 2936 ctxt->src.val = old_eip;
4487b3b4 2937 return em_push(ctxt);
0ef753b8
AK		 2938}
2939
40ece7c7
AK		 2940static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2941{
40ece7c7
AK		 2942 int rc;
2943
9dac77fa
AK		 2944 ctxt->dst.type = OP_REG;
2945 ctxt->dst.addr.reg = &ctxt->_eip;
2946 ctxt->dst.bytes = ctxt->op_bytes;
2947 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2948 if (rc != X86EMUL_CONTINUE)
2949 return rc;
5ad105e5 2950 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2951 return X86EMUL_CONTINUE;
2952}
2953
e4f973ae
TY		 2954static int em_xchg(struct x86_emulate_ctxt *ctxt)
2955{
e4f973ae 2956 /* Write back the register source. */
9dac77fa
AK		 2957 ctxt->src.val = ctxt->dst.val;
2958 write_register_operand(&ctxt->src);
e4f973ae
TY		 2959
2960 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2961 ctxt->dst.val = ctxt->src.orig_val;
2962 ctxt->lock_prefix = 1;
e4f973ae
TY		 2963 return X86EMUL_CONTINUE;
2964}
2965
5c82aa29
AK		 2966static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2967{
9dac77fa 2968 ctxt->dst.val = ctxt->src2.val;
4d758349 2969 return fastop(ctxt, em_imul);
5c82aa29
AK		 2970}
2971
61429142
AK		 2972static int em_cwd(struct x86_emulate_ctxt *ctxt)
2973{
9dac77fa
AK		 2974 ctxt->dst.type = OP_REG;
2975 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2976 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2977 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2978
2979 return X86EMUL_CONTINUE;
2980}
2981
48bb5d3c
AK		 2982static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2983{
48bb5d3c
AK		 2984 u64 tsc = 0;
2985
717746e3 2986 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2987 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2988 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2989 return X86EMUL_CONTINUE;
2990}
2991
222d21aa
AK		 2992static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2993{
2994 u64 pmc;
2995
dd856efa 2996 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2997 return emulate_gp(ctxt, 0);
dd856efa
AK		 2998 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2999 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3000 return X86EMUL_CONTINUE;
3001}
3002
b9eac5f4
AK		 3003static int em_mov(struct x86_emulate_ctxt *ctxt)
3004{
54cfdb3e 3005 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3006 return X86EMUL_CONTINUE;
3007}
3008
84cffe49
BP		 3009#define FFL(x) bit(X86_FEATURE_##x)
3010
3011static int em_movbe(struct x86_emulate_ctxt *ctxt)
3012{
3013 u32 ebx, ecx, edx, eax = 1;
3014 u16 tmp;
3015
3016 /*
3017 * Check MOVBE is set in the guest-visible CPUID leaf.
3018 */
3019 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3020 if (!(ecx & FFL(MOVBE)))
3021 return emulate_ud(ctxt);
3022
3023 switch (ctxt->op_bytes) {
3024 case 2:
3025 /*
3026 * From MOVBE definition: "...When the operand size is 16 bits,
3027 * the upper word of the destination register remains unchanged
3028 * ..."
3029 *
3030 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3031 * rules so we have to do the operation almost per hand.
3032 */
3033 tmp = (u16)ctxt->src.val;
3034 ctxt->dst.val &= ~0xffffUL;
3035 ctxt->dst.val |= (unsigned long)swab16(tmp);
3036 break;
3037 case 4:
3038 ctxt->dst.val = swab32((u32)ctxt->src.val);
3039 break;
3040 case 8:
3041 ctxt->dst.val = swab64(ctxt->src.val);
3042 break;
3043 default:
592f0858 3044 BUG();
84cffe49
BP		 3045 }
3046 return X86EMUL_CONTINUE;
3047}
3048
bc00f8d2
TY		 3049static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3050{
3051 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3052 return emulate_gp(ctxt, 0);
3053
3054 /* Disable writeback. */
3055 ctxt->dst.type = OP_NONE;
3056 return X86EMUL_CONTINUE;
3057}
3058
3059static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3060{
3061 unsigned long val;
3062
3063 if (ctxt->mode == X86EMUL_MODE_PROT64)
3064 val = ctxt->src.val & ~0ULL;
3065 else
3066 val = ctxt->src.val & ~0U;
3067
3068 /* #UD condition is already handled. */
3069 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3070 return emulate_gp(ctxt, 0);
3071
3072 /* Disable writeback. */
3073 ctxt->dst.type = OP_NONE;
3074 return X86EMUL_CONTINUE;
3075}
3076
e1e210b0
TY		 3077static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3078{
3079 u64 msr_data;
3080
dd856efa
AK		 3081 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3082 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3083 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3084 return emulate_gp(ctxt, 0);
3085
3086 return X86EMUL_CONTINUE;
3087}
3088
3089static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3090{
3091 u64 msr_data;
3092
dd856efa 3093 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3094 return emulate_gp(ctxt, 0);
3095
dd856efa
AK		 3096 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3097 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3098 return X86EMUL_CONTINUE;
3099}
3100
1bd5f469
TY		 3101static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3102{
9dac77fa 3103 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3104 return emulate_ud(ctxt);
3105
9dac77fa 3106 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3107 return X86EMUL_CONTINUE;
3108}
3109
3110static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3111{
9dac77fa 3112 u16 sel = ctxt->src.val;
1bd5f469 3113
9dac77fa 3114 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3115 return emulate_ud(ctxt);
3116
9dac77fa 3117 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3118 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3119
3120 /* Disable writeback. */
9dac77fa
AK		 3121 ctxt->dst.type = OP_NONE;
3122 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3123}
3124
a14e579f
AK		 3125static int em_lldt(struct x86_emulate_ctxt *ctxt)
3126{
3127 u16 sel = ctxt->src.val;
3128
3129 /* Disable writeback. */
3130 ctxt->dst.type = OP_NONE;
3131 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3132}
3133
80890006
AK		 3134static int em_ltr(struct x86_emulate_ctxt *ctxt)
3135{
3136 u16 sel = ctxt->src.val;
3137
3138 /* Disable writeback. */
3139 ctxt->dst.type = OP_NONE;
3140 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3141}
3142
38503911
AK		 3143static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3144{
9fa088f4
AK		 3145 int rc;
3146 ulong linear;
3147
9dac77fa 3148 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3149 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3150 ctxt->ops->invlpg(ctxt, linear);
38503911 3151 /* Disable writeback. */
9dac77fa 3152 ctxt->dst.type = OP_NONE;
38503911
AK		 3153 return X86EMUL_CONTINUE;
3154}
3155
2d04a05b
AK		 3156static int em_clts(struct x86_emulate_ctxt *ctxt)
3157{
3158 ulong cr0;
3159
3160 cr0 = ctxt->ops->get_cr(ctxt, 0);
3161 cr0 &= ~X86_CR0_TS;
3162 ctxt->ops->set_cr(ctxt, 0, cr0);
3163 return X86EMUL_CONTINUE;
3164}
3165
26d05cc7
AK		 3166static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3167{
0f54a321 3168 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3169
26d05cc7
AK		 3170 if (rc != X86EMUL_CONTINUE)
3171 return rc;
3172
3173 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3174 ctxt->_eip = ctxt->eip;
26d05cc7 3175 /* Disable writeback. */
9dac77fa 3176 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3177 return X86EMUL_CONTINUE;
3178}
3179
96051572
AK		 3180static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3181 void (*get)(struct x86_emulate_ctxt *ctxt,
3182 struct desc_ptr *ptr))
3183{
3184 struct desc_ptr desc_ptr;
3185
3186 if (ctxt->mode == X86EMUL_MODE_PROT64)
3187 ctxt->op_bytes = 8;
3188 get(ctxt, &desc_ptr);
3189 if (ctxt->op_bytes == 2) {
3190 ctxt->op_bytes = 4;
3191 desc_ptr.address &= 0x00ffffff;
3192 }
3193 /* Disable writeback. */
3194 ctxt->dst.type = OP_NONE;
3195 return segmented_write(ctxt, ctxt->dst.addr.mem,
3196 &desc_ptr, 2 + ctxt->op_bytes);
3197}
3198
3199static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3200{
3201 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3202}
3203
3204static int em_sidt(struct x86_emulate_ctxt *ctxt)
3205{
3206 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3207}
3208
26d05cc7
AK		 3209static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3210{
26d05cc7
AK		 3211 struct desc_ptr desc_ptr;
3212 int rc;
3213
510425ff
AK		 3214 if (ctxt->mode == X86EMUL_MODE_PROT64)
3215 ctxt->op_bytes = 8;
9dac77fa 3216 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3217 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3218 ctxt->op_bytes);
26d05cc7
AK		 3219 if (rc != X86EMUL_CONTINUE)
3220 return rc;
3221 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3222 /* Disable writeback. */
9dac77fa 3223 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3224 return X86EMUL_CONTINUE;
3225}
3226
5ef39c71 3227static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3228{
26d05cc7
AK		 3229 int rc;
3230
5ef39c71
AK		 3231 rc = ctxt->ops->fix_hypercall(ctxt);
3232
26d05cc7 3233 /* Disable writeback. */
9dac77fa 3234 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3235 return rc;
3236}
3237
3238static int em_lidt(struct x86_emulate_ctxt *ctxt)
3239{
26d05cc7
AK		 3240 struct desc_ptr desc_ptr;
3241 int rc;
3242
510425ff
AK		 3243 if (ctxt->mode == X86EMUL_MODE_PROT64)
3244 ctxt->op_bytes = 8;
9dac77fa 3245 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3246 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3247 ctxt->op_bytes);
26d05cc7
AK		 3248 if (rc != X86EMUL_CONTINUE)
3249 return rc;
3250 ctxt->ops->set_idt(ctxt, &desc_ptr);
3251 /* Disable writeback. */
9dac77fa 3252 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3253 return X86EMUL_CONTINUE;
3254}
3255
3256static int em_smsw(struct x86_emulate_ctxt *ctxt)
3257{
32e94d06
NA		 3258 if (ctxt->dst.type == OP_MEM)
3259 ctxt->dst.bytes = 2;
9dac77fa 3260 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3261 return X86EMUL_CONTINUE;
3262}
3263
3264static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3265{
26d05cc7 3266 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3267 | (ctxt->src.val & 0x0f));
3268 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3269 return X86EMUL_CONTINUE;
3270}
3271
d06e03ad
TY		 3272static int em_loop(struct x86_emulate_ctxt *ctxt)
3273{
dd856efa
AK		 3274 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3275 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3276 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3277 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3278
3279 return X86EMUL_CONTINUE;
3280}
3281
3282static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3283{
dd856efa 3284 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3285 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3286
3287 return X86EMUL_CONTINUE;
3288}
3289
d7841a4b
TY		 3290static int em_in(struct x86_emulate_ctxt *ctxt)
3291{
3292 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3293 &ctxt->dst.val))
3294 return X86EMUL_IO_NEEDED;
3295
3296 return X86EMUL_CONTINUE;
3297}
3298
3299static int em_out(struct x86_emulate_ctxt *ctxt)
3300{
3301 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3302 &ctxt->src.val, 1);
3303 /* Disable writeback. */
3304 ctxt->dst.type = OP_NONE;
3305 return X86EMUL_CONTINUE;
3306}
3307
f411e6cd
TY		 3308static int em_cli(struct x86_emulate_ctxt *ctxt)
3309{
3310 if (emulator_bad_iopl(ctxt))
3311 return emulate_gp(ctxt, 0);
3312
3313 ctxt->eflags &= ~X86_EFLAGS_IF;
3314 return X86EMUL_CONTINUE;
3315}
3316
3317static int em_sti(struct x86_emulate_ctxt *ctxt)
3318{
3319 if (emulator_bad_iopl(ctxt))
3320 return emulate_gp(ctxt, 0);
3321
3322 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3323 ctxt->eflags |= X86_EFLAGS_IF;
3324 return X86EMUL_CONTINUE;
3325}
3326
6d6eede4
AK		 3327static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3328{
3329 u32 eax, ebx, ecx, edx;
3330
dd856efa
AK		 3331 eax = reg_read(ctxt, VCPU_REGS_RAX);
3332 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3333 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3334 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3335 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3336 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3337 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3338 return X86EMUL_CONTINUE;
3339}
3340
98f73630
PB		 3341static int em_sahf(struct x86_emulate_ctxt *ctxt)
3342{
3343 u32 flags;
3344
3345 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3346 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3347
3348 ctxt->eflags &= ~0xffUL;
3349 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3350 return X86EMUL_CONTINUE;
3351}
3352
2dd7caa0
AK		 3353static int em_lahf(struct x86_emulate_ctxt *ctxt)
3354{
dd856efa
AK		 3355 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3356 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3357 return X86EMUL_CONTINUE;
3358}
3359
9299836e
AK		 3360static int em_bswap(struct x86_emulate_ctxt *ctxt)
3361{
3362 switch (ctxt->op_bytes) {
3363#ifdef CONFIG_X86_64
3364 case 8:
3365 asm("bswap %0" : "+r"(ctxt->dst.val));
3366 break;
3367#endif
3368 default:
3369 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3370 break;
3371 }
3372 return X86EMUL_CONTINUE;
3373}
3374
cfec82cb
JR		 3375static bool valid_cr(int nr)
3376{
3377 switch (nr) {
3378 case 0:
3379 case 2 ... 4:
3380 case 8:
3381 return true;
3382 default:
3383 return false;
3384 }
3385}
3386
3387static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3388{
9dac77fa 3389 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3390 return emulate_ud(ctxt);
3391
3392 return X86EMUL_CONTINUE;
3393}
3394
3395static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3396{
9dac77fa
AK		 3397 u64 new_val = ctxt->src.val64;
3398 int cr = ctxt->modrm_reg;
c2ad2bb3 3399 u64 efer = 0;
cfec82cb
JR		 3400
3401 static u64 cr_reserved_bits[] = {
3402 0xffffffff00000000ULL,
3403 0, 0, 0, /* CR3 checked later */
3404 CR4_RESERVED_BITS,
3405 0, 0, 0,
3406 CR8_RESERVED_BITS,
3407 };
3408
3409 if (!valid_cr(cr))
3410 return emulate_ud(ctxt);
3411
3412 if (new_val & cr_reserved_bits[cr])
3413 return emulate_gp(ctxt, 0);
3414
3415 switch (cr) {
3416 case 0: {
c2ad2bb3 3417 u64 cr4;
cfec82cb
JR		 3418 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3419 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3420 return emulate_gp(ctxt, 0);
3421
717746e3
AK		 3422 cr4 = ctxt->ops->get_cr(ctxt, 4);
3423 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3424
3425 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3426 !(cr4 & X86_CR4_PAE))
3427 return emulate_gp(ctxt, 0);
3428
3429 break;
3430 }
3431 case 3: {
3432 u64 rsvd = 0;
3433
c2ad2bb3
AK		 3434 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3435 if (efer & EFER_LMA)
cfec82cb 3436 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3437
3438 if (new_val & rsvd)
3439 return emulate_gp(ctxt, 0);
3440
3441 break;
3442 }
3443 case 4: {
717746e3 3444 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3445
3446 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3447 return emulate_gp(ctxt, 0);
3448
3449 break;
3450 }
3451 }
3452
3453 return X86EMUL_CONTINUE;
3454}
3455
3b88e41a
JR		 3456static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3457{
3458 unsigned long dr7;
3459
717746e3 3460 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3461
3462 /* Check if DR7.Global_Enable is set */
3463 return dr7 & (1 << 13);
3464}
3465
3466static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3467{
9dac77fa 3468 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3469 u64 cr4;
3470
3471 if (dr > 7)
3472 return emulate_ud(ctxt);
3473
717746e3 3474 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3475 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3476 return emulate_ud(ctxt);
3477
3478 if (check_dr7_gd(ctxt))
3479 return emulate_db(ctxt);
3480
3481 return X86EMUL_CONTINUE;
3482}
3483
3484static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3485{
9dac77fa
AK		 3486 u64 new_val = ctxt->src.val64;
3487 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3488
3489 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3490 return emulate_gp(ctxt, 0);
3491
3492 return check_dr_read(ctxt);
3493}
3494
01de8b09
JR		 3495static int check_svme(struct x86_emulate_ctxt *ctxt)
3496{
3497 u64 efer;
3498
717746e3 3499 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3500
3501 if (!(efer & EFER_SVME))
3502 return emulate_ud(ctxt);
3503
3504 return X86EMUL_CONTINUE;
3505}
3506
3507static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3508{
dd856efa 3509 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3510
3511 /* Valid physical address? */
d4224449 3512 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3513 return emulate_gp(ctxt, 0);
3514
3515 return check_svme(ctxt);
3516}
3517
d7eb8203
JR		 3518static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3519{
717746e3 3520 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3521
717746e3 3522 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3523 return emulate_ud(ctxt);
3524
3525 return X86EMUL_CONTINUE;
3526}
3527
8061252e
JR		 3528static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3529{
717746e3 3530 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3531 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3532
717746e3 3533 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3534 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3535 return emulate_gp(ctxt, 0);
3536
3537 return X86EMUL_CONTINUE;
3538}
3539
f6511935
JR		 3540static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3541{
9dac77fa
AK		 3542 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3543 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3544 return emulate_gp(ctxt, 0);
3545
3546 return X86EMUL_CONTINUE;
3547}
3548
3549static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3550{
9dac77fa
AK		 3551 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3552 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3553 return emulate_gp(ctxt, 0);
3554
3555 return X86EMUL_CONTINUE;
3556}
3557
73fba5f4 3558#define D(_y) { .flags = (_y) }
d40a6898
PB		 3559#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3560#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3561 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3562#define N D(NotImpl)
01de8b09 3563#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3564#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3565#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3566#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3567#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3568#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3569#define II(_f, _e, _i) \
d40a6898 3570 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3571#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3572 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3573 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3574#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3575
8d8f4e9f 3576#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3577#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3578#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3579#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3580#define I2bvIP(_f, _e, _i, _p) \
3581 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3582
fb864fbc
AK		 3583#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3584 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3585 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3586
0f54a321
NA		 3587static const struct opcode group7_rm0[] = {
3588 N,
3589 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3590 N, N, N, N, N, N,
3591};
3592
fd0a0d82 3593static const struct opcode group7_rm1[] = {
1c2545be
TY		 3594 DI(SrcNone | Priv, monitor),
3595 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3596 N, N, N, N, N, N,
3597};
3598
fd0a0d82 3599static const struct opcode group7_rm3[] = {
1c2545be 3600 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3601 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3602 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3603 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3604 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3605 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3606 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3607 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3608};
6230f7fc 3609
fd0a0d82 3610static const struct opcode group7_rm7[] = {
d7eb8203 3611 N,
1c2545be 3612 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3613 N, N, N, N, N, N,
3614};
d67fc27a 3615
fd0a0d82 3616static const struct opcode group1[] = {
fb864fbc
AK		 3617 F(Lock, em_add),
3618 F(Lock | PageTable, em_or),
3619 F(Lock, em_adc),
3620 F(Lock, em_sbb),
3621 F(Lock | PageTable, em_and),
3622 F(Lock, em_sub),
3623 F(Lock, em_xor),
3624 F(NoWrite, em_cmp),
73fba5f4
AK		 3625};
3626
fd0a0d82 3627static const struct opcode group1A[] = {
1c2545be 3628 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3629};
3630
007a3b54
AK		 3631static const struct opcode group2[] = {
3632 F(DstMem | ModRM, em_rol),
3633 F(DstMem | ModRM, em_ror),
3634 F(DstMem | ModRM, em_rcl),
3635 F(DstMem | ModRM, em_rcr),
3636 F(DstMem | ModRM, em_shl),
3637 F(DstMem | ModRM, em_shr),
3638 F(DstMem | ModRM, em_shl),
3639 F(DstMem | ModRM, em_sar),
3640};
3641
fd0a0d82 3642static const struct opcode group3[] = {
fb864fbc
AK		 3643 F(DstMem | SrcImm | NoWrite, em_test),
3644 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3645 F(DstMem | SrcNone | Lock, em_not),
3646 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3647 F(DstXacc | Src2Mem, em_mul_ex),
3648 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3649 F(DstXacc | Src2Mem, em_div_ex),
3650 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3651};
3652
fd0a0d82 3653static const struct opcode group4[] = {
95413dc4
AK		 3654 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3655 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3656 N, N, N, N, N, N,
3657};
3658
fd0a0d82 3659static const struct opcode group5[] = {
95413dc4
AK		 3660 F(DstMem | SrcNone | Lock, em_inc),
3661 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3662 I(SrcMem | Stack, em_grp45),
3663 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3664 I(SrcMem | Stack, em_grp45),
3665 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3666 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3667};
3668
fd0a0d82 3669static const struct opcode group6[] = {
1c2545be
TY		 3670 DI(Prot, sldt),
3671 DI(Prot, str),
a14e579f 3672 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3673 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3674 N, N, N, N,
3675};
3676
fd0a0d82 3677static const struct group_dual group7 = { {
606b1c3e
NA		 3678 II(Mov | DstMem, em_sgdt, sgdt),
3679 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3680 II(SrcMem | Priv, em_lgdt, lgdt),
3681 II(SrcMem | Priv, em_lidt, lidt),
3682 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3683 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3684 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3685}, {
0f54a321 3686 EXT(0, group7_rm0),
5ef39c71 3687 EXT(0, group7_rm1),
01de8b09 3688 N, EXT(0, group7_rm3),
1c2545be
TY		 3689 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3690 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3691 EXT(0, group7_rm7),
73fba5f4
AK		 3692} };
3693
fd0a0d82 3694static const struct opcode group8[] = {
73fba5f4 3695 N, N, N, N,
11c363ba
AK		 3696 F(DstMem | SrcImmByte | NoWrite, em_bt),
3697 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3698 F(DstMem | SrcImmByte | Lock, em_btr),
3699 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3700};
3701
fd0a0d82 3702static const struct group_dual group9 = { {
1c2545be 3703 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3704}, {
3705 N, N, N, N, N, N, N, N,
3706} };
3707
fd0a0d82 3708static const struct opcode group11[] = {
1c2545be 3709 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3710 X7(D(Undefined)),
a4d4a7c1
AK		 3711};
3712
fd0a0d82 3713static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3714 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3715};
3716
d5b77069
PB		 3717static const struct gprefix pfx_0f_2b = {
3718 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3719};
3720
27ce8258 3721static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3722 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3723};
3724
0a37027e
AW		 3725static const struct gprefix pfx_0f_e7 = {
3726 N, I(Sse, em_mov), N, N,
3727};
3728
045a282c
GN		 3729static const struct escape escape_d9 = { {
3730 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3731}, {
3732 /* 0xC0 - 0xC7 */
3733 N, N, N, N, N, N, N, N,
3734 /* 0xC8 - 0xCF */
3735 N, N, N, N, N, N, N, N,
3736 /* 0xD0 - 0xC7 */
3737 N, N, N, N, N, N, N, N,
3738 /* 0xD8 - 0xDF */
3739 N, N, N, N, N, N, N, N,
3740 /* 0xE0 - 0xE7 */
3741 N, N, N, N, N, N, N, N,
3742 /* 0xE8 - 0xEF */
3743 N, N, N, N, N, N, N, N,
3744 /* 0xF0 - 0xF7 */
3745 N, N, N, N, N, N, N, N,
3746 /* 0xF8 - 0xFF */
3747 N, N, N, N, N, N, N, N,
3748} };
3749
3750static const struct escape escape_db = { {
3751 N, N, N, N, N, N, N, N,
3752}, {
3753 /* 0xC0 - 0xC7 */
3754 N, N, N, N, N, N, N, N,
3755 /* 0xC8 - 0xCF */
3756 N, N, N, N, N, N, N, N,
3757 /* 0xD0 - 0xC7 */
3758 N, N, N, N, N, N, N, N,
3759 /* 0xD8 - 0xDF */
3760 N, N, N, N, N, N, N, N,
3761 /* 0xE0 - 0xE7 */
3762 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3763 /* 0xE8 - 0xEF */
3764 N, N, N, N, N, N, N, N,
3765 /* 0xF0 - 0xF7 */
3766 N, N, N, N, N, N, N, N,
3767 /* 0xF8 - 0xFF */
3768 N, N, N, N, N, N, N, N,
3769} };
3770
3771static const struct escape escape_dd = { {
3772 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3773}, {
3774 /* 0xC0 - 0xC7 */
3775 N, N, N, N, N, N, N, N,
3776 /* 0xC8 - 0xCF */
3777 N, N, N, N, N, N, N, N,
3778 /* 0xD0 - 0xC7 */
3779 N, N, N, N, N, N, N, N,
3780 /* 0xD8 - 0xDF */
3781 N, N, N, N, N, N, N, N,
3782 /* 0xE0 - 0xE7 */
3783 N, N, N, N, N, N, N, N,
3784 /* 0xE8 - 0xEF */
3785 N, N, N, N, N, N, N, N,
3786 /* 0xF0 - 0xF7 */
3787 N, N, N, N, N, N, N, N,
3788 /* 0xF8 - 0xFF */
3789 N, N, N, N, N, N, N, N,
3790} };
3791
fd0a0d82 3792static const struct opcode opcode_table[256] = {
73fba5f4 3793 /* 0x00 - 0x07 */
fb864fbc 3794 F6ALU(Lock, em_add),
1cd196ea
AK		 3795 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3796 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3797 /* 0x08 - 0x0F */
fb864fbc 3798 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3799 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3800 N,
73fba5f4 3801 /* 0x10 - 0x17 */
fb864fbc 3802 F6ALU(Lock, em_adc),
1cd196ea
AK		 3803 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3804 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3805 /* 0x18 - 0x1F */
fb864fbc 3806 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3807 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3808 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3809 /* 0x20 - 0x27 */
fb864fbc 3810 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3811 /* 0x28 - 0x2F */
fb864fbc 3812 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3813 /* 0x30 - 0x37 */
fb864fbc 3814 F6ALU(Lock, em_xor), N, N,
73fba5f4 3815 /* 0x38 - 0x3F */
fb864fbc 3816 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3817 /* 0x40 - 0x4F */
95413dc4 3818 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3819 /* 0x50 - 0x57 */
63540382 3820 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3821 /* 0x58 - 0x5F */
c54fe504 3822 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3823 /* 0x60 - 0x67 */
b96a7fad
TY		 3824 I(ImplicitOps | Stack | No64, em_pusha),
3825 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3826 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3827 N, N, N, N,
3828 /* 0x68 - 0x6F */
d46164db
AK		 3829 I(SrcImm | Mov | Stack, em_push),
3830 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3831 I(SrcImmByte | Mov | Stack, em_push),
3832 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3833 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3834 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3835 /* 0x70 - 0x7F */
3836 X16(D(SrcImmByte)),
3837 /* 0x80 - 0x87 */
1c2545be
TY		 3838 G(ByteOp | DstMem | SrcImm, group1),
3839 G(DstMem | SrcImm, group1),
3840 G(ByteOp | DstMem | SrcImm | No64, group1),
3841 G(DstMem | SrcImmByte, group1),
fb864fbc 3842 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3843 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3844 /* 0x88 - 0x8F */
d5ae7ce8 3845 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3846 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3847 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3848 D(ModRM | SrcMem | NoAccess | DstReg),
3849 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3850 G(0, group1A),
73fba5f4 3851 /* 0x90 - 0x97 */
bf608f88 3852 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3853 /* 0x98 - 0x9F */
61429142 3854 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3855 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3856 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3857 II(ImplicitOps | Stack, em_popf, popf),
3858 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3859 /* 0xA0 - 0xA7 */
b9eac5f4 3860 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3861 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3862 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3863 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3864 /* 0xA8 - 0xAF */
fb864fbc 3865 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3866 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3867 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3868 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3869 /* 0xB0 - 0xB7 */
b9eac5f4 3870 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3871 /* 0xB8 - 0xBF */
5e2c6883 3872 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3873 /* 0xC0 - 0xC7 */
007a3b54 3874 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3875 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3876 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3877 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3878 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3879 G(ByteOp, group11), G(0, group11),
73fba5f4 3880 /* 0xC8 - 0xCF */
612e89f0 3881 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3882 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3883 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3884 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3885 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3886 /* 0xD0 - 0xD7 */
007a3b54
AK		 3887 G(Src2One | ByteOp, group2), G(Src2One, group2),
3888 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3889 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3890 I(DstAcc | SrcImmUByte | No64, em_aad),
3891 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3892 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3893 /* 0xD8 - 0xDF */
045a282c 3894 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3895 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3896 X3(I(SrcImmByte, em_loop)),
3897 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3898 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3899 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3900 /* 0xE8 - 0xEF */
d4ddafcd 3901 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3902 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3903 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3904 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3905 /* 0xF0 - 0xF7 */
bf608f88 3906 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3907 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3908 G(ByteOp, group3), G(0, group3),
73fba5f4 3909 /* 0xF8 - 0xFF */
f411e6cd
TY		 3910 D(ImplicitOps), D(ImplicitOps),
3911 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3912 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3913};
3914
fd0a0d82 3915static const struct opcode twobyte_table[256] = {
73fba5f4 3916 /* 0x00 - 0x0F */
dee6bb70 3917 G(0, group6), GD(0, &group7), N, N,
b51e974f 3918 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3919 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3920 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3921 N, D(ImplicitOps | ModRM), N, N,
3922 /* 0x10 - 0x1F */
103f98ea
PB		 3923 N, N, N, N, N, N, N, N,
3924 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3925 /* 0x20 - 0x2F */
9b88ae99
NA		 3926 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3927 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3928 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3929 check_cr_write),
3930 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3931 check_dr_write),
73fba5f4 3932 N, N, N, N,
27ce8258
IM		 3933 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3934 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 3935 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 3936 N, N, N, N,
73fba5f4 3937 /* 0x30 - 0x3F */
e1e210b0 3938 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3939 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3940 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3941 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3942 I(ImplicitOps | EmulateOnUD, em_sysenter),
3943 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3944 N, N,
73fba5f4
AK		 3945 N, N, N, N, N, N, N, N,
3946 /* 0x40 - 0x4F */
140bad89 3947 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3948 /* 0x50 - 0x5F */
3949 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3950 /* 0x60 - 0x6F */
aa97bb48
AK		 3951 N, N, N, N,
3952 N, N, N, N,
3953 N, N, N, N,
3954 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3955 /* 0x70 - 0x7F */
aa97bb48
AK		 3956 N, N, N, N,
3957 N, N, N, N,
3958 N, N, N, N,
3959 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3960 /* 0x80 - 0x8F */
3961 X16(D(SrcImm)),
3962 /* 0x90 - 0x9F */
ee45b58e 3963 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3964 /* 0xA0 - 0xA7 */
1cd196ea 3965 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3966 II(ImplicitOps, em_cpuid, cpuid),
3967 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3968 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3969 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3970 /* 0xA8 - 0xAF */
1cd196ea 3971 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3972 DI(ImplicitOps, rsm),
11c363ba 3973 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3974 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3975 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3976 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3977 /* 0xB0 - 0xB7 */
e940b5c2 3978 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3979 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3980 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3981 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3982 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3983 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3984 /* 0xB8 - 0xBF */
3985 N, N,
ce7faab2 3986 G(BitOp, group8),
11c363ba
AK		 3987 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3988 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3989 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3990 /* 0xC0 - 0xC7 */
e47a5f5f 3991 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3992 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3993 N, N, N, GD(0, &group9),
9299836e
AK		 3994 /* 0xC8 - 0xCF */
3995 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3996 /* 0xD0 - 0xDF */
3997 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3998 /* 0xE0 - 0xEF */
0a37027e
AW		 3999 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4000 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4001 /* 0xF0 - 0xFF */
4002 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4003};
4004
0bc5eedb 4005static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4006 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4007};
4008
4009static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4010 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4011};
4012
4013/*
4014 * Insns below are selected by the prefix which indexed by the third opcode
4015 * byte.
4016 */
4017static const struct opcode opcode_map_0f_38[256] = {
4018 /* 0x00 - 0x7f */
4019 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4020 /* 0x80 - 0xef */
4021 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4022 /* 0xf0 - 0xf1 */
4023 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4024 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4025 /* 0xf2 - 0xff */
4026 N, N, X4(N), X8(N)
0bc5eedb
BP		 4027};
4028
73fba5f4
AK		 4029#undef D
4030#undef N
4031#undef G
4032#undef GD
4033#undef I
aa97bb48 4034#undef GP
01de8b09 4035#undef EXT
73fba5f4 4036
8d8f4e9f 4037#undef D2bv
f6511935 4038#undef D2bvIP
8d8f4e9f 4039#undef I2bv
d7841a4b 4040#undef I2bvIP
d67fc27a 4041#undef I6ALU
8d8f4e9f 4042
9dac77fa 4043static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4044{
4045 unsigned size;
4046
9dac77fa 4047 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4048 if (size == 8)
4049 size = 4;
4050 return size;
4051}
4052
4053static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4054 unsigned size, bool sign_extension)
4055{
39f21ee5
AK		 4056 int rc = X86EMUL_CONTINUE;
4057
4058 op->type = OP_IMM;
4059 op->bytes = size;
9dac77fa 4060 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4061 /* NB. Immediates are sign-extended as necessary. */
4062 switch (op->bytes) {
4063 case 1:
e85a1085 4064 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4065 break;
4066 case 2:
e85a1085 4067 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4068 break;
4069 case 4:
e85a1085 4070 op->val = insn_fetch(s32, ctxt);
39f21ee5 4071 break;
5e2c6883
NA		 4072 case 8:
4073 op->val = insn_fetch(s64, ctxt);
4074 break;
39f21ee5
AK		 4075 }
4076 if (!sign_extension) {
4077 switch (op->bytes) {
4078 case 1:
4079 op->val &= 0xff;
4080 break;
4081 case 2:
4082 op->val &= 0xffff;
4083 break;
4084 case 4:
4085 op->val &= 0xffffffff;
4086 break;
4087 }
4088 }
4089done:
4090 return rc;
4091}
4092
a9945549
AK		 4093static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4094 unsigned d)
4095{
4096 int rc = X86EMUL_CONTINUE;
4097
4098 switch (d) {
4099 case OpReg:
2adb5ad9 4100 decode_register_operand(ctxt, op);
a9945549
AK		 4101 break;
4102 case OpImmUByte:
608aabe3 4103 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4104 break;
4105 case OpMem:
41ddf978 4106 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4107 mem_common:
4108 *op = ctxt->memop;
4109 ctxt->memopp = op;
96888977 4110 if (ctxt->d & BitOp)
a9945549
AK		 4111 fetch_bit_operand(ctxt);
4112 op->orig_val = op->val;
4113 break;
41ddf978 4114 case OpMem64:
aaa05f24 4115 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4116 goto mem_common;
a9945549
AK		 4117 case OpAcc:
4118 op->type = OP_REG;
4119 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4120 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4121 fetch_register_operand(op);
4122 op->orig_val = op->val;
4123 break;
820207c8
AK		 4124 case OpAccLo:
4125 op->type = OP_REG;
4126 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4127 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4128 fetch_register_operand(op);
4129 op->orig_val = op->val;
4130 break;
4131 case OpAccHi:
4132 if (ctxt->d & ByteOp) {
4133 op->type = OP_NONE;
4134 break;
4135 }
4136 op->type = OP_REG;
4137 op->bytes = ctxt->op_bytes;
4138 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4139 fetch_register_operand(op);
4140 op->orig_val = op->val;
4141 break;
a9945549
AK		 4142 case OpDI:
4143 op->type = OP_MEM;
4144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4145 op->addr.mem.ea =
dd856efa 4146 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4147 op->addr.mem.seg = VCPU_SREG_ES;
4148 op->val = 0;
b3356bf0 4149 op->count = 1;
a9945549
AK		 4150 break;
4151 case OpDX:
4152 op->type = OP_REG;
4153 op->bytes = 2;
dd856efa 4154 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4155 fetch_register_operand(op);
4156 break;
4dd6a57d
AK		 4157 case OpCL:
4158 op->bytes = 1;
dd856efa 4159 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4160 break;
4161 case OpImmByte:
4162 rc = decode_imm(ctxt, op, 1, true);
4163 break;
4164 case OpOne:
4165 op->bytes = 1;
4166 op->val = 1;
4167 break;
4168 case OpImm:
4169 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4170 break;
5e2c6883
NA		 4171 case OpImm64:
4172 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4173 break;
28867cee
AK		 4174 case OpMem8:
4175 ctxt->memop.bytes = 1;
660696d1 4176 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4177 ctxt->memop.addr.reg = decode_register(ctxt,
4178 ctxt->modrm_rm, true);
660696d1
GN		 4179 fetch_register_operand(&ctxt->memop);
4180 }
28867cee 4181 goto mem_common;
0fe59128
AK		 4182 case OpMem16:
4183 ctxt->memop.bytes = 2;
4184 goto mem_common;
4185 case OpMem32:
4186 ctxt->memop.bytes = 4;
4187 goto mem_common;
4188 case OpImmU16:
4189 rc = decode_imm(ctxt, op, 2, false);
4190 break;
4191 case OpImmU:
4192 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4193 break;
4194 case OpSI:
4195 op->type = OP_MEM;
4196 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4197 op->addr.mem.ea =
dd856efa 4198 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4199 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4200 op->val = 0;
b3356bf0 4201 op->count = 1;
0fe59128 4202 break;
7fa57952
PB		 4203 case OpXLat:
4204 op->type = OP_MEM;
4205 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4206 op->addr.mem.ea =
4207 register_address(ctxt,
4208 reg_read(ctxt, VCPU_REGS_RBX) +
4209 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4210 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4211 op->val = 0;
4212 break;
0fe59128
AK		 4213 case OpImmFAddr:
4214 op->type = OP_IMM;
4215 op->addr.mem.ea = ctxt->_eip;
4216 op->bytes = ctxt->op_bytes + 2;
4217 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4218 break;
4219 case OpMemFAddr:
4220 ctxt->memop.bytes = ctxt->op_bytes + 2;
4221 goto mem_common;
c191a7a0
AK		 4222 case OpES:
4223 op->val = VCPU_SREG_ES;
4224 break;
4225 case OpCS:
4226 op->val = VCPU_SREG_CS;
4227 break;
4228 case OpSS:
4229 op->val = VCPU_SREG_SS;
4230 break;
4231 case OpDS:
4232 op->val = VCPU_SREG_DS;
4233 break;
4234 case OpFS:
4235 op->val = VCPU_SREG_FS;
4236 break;
4237 case OpGS:
4238 op->val = VCPU_SREG_GS;
4239 break;
a9945549
AK		 4240 case OpImplicit:
4241 /* Special instructions do their own operand decoding. */
4242 default:
4243 op->type = OP_NONE; /* Disable writeback. */
4244 break;
4245 }
4246
4247done:
4248 return rc;
4249}
4250
ef5d75cc 4251int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4252{
dde7e6d1
AK		 4253 int rc = X86EMUL_CONTINUE;
4254 int mode = ctxt->mode;
46561646 4255 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4256 bool op_prefix = false;
573e80fe 4257 bool has_seg_override = false;
46561646 4258 struct opcode opcode;
dde7e6d1 4259
f09ed83e
AK		 4260 ctxt->memop.type = OP_NONE;
4261 ctxt->memopp = NULL;
9dac77fa 4262 ctxt->_eip = ctxt->eip;
17052f16
PB		 4263 ctxt->fetch.ptr = ctxt->fetch.data;
4264 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4265 ctxt->opcode_len = 1;
dc25e89e 4266 if (insn_len > 0)
9dac77fa 4267 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4268 else {
9506d57d 4269 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4270 if (rc != X86EMUL_CONTINUE)
4271 return rc;
4272 }
dde7e6d1
AK		 4273
4274 switch (mode) {
4275 case X86EMUL_MODE_REAL:
4276 case X86EMUL_MODE_VM86:
4277 case X86EMUL_MODE_PROT16:
4278 def_op_bytes = def_ad_bytes = 2;
4279 break;
4280 case X86EMUL_MODE_PROT32:
4281 def_op_bytes = def_ad_bytes = 4;
4282 break;
4283#ifdef CONFIG_X86_64
4284 case X86EMUL_MODE_PROT64:
4285 def_op_bytes = 4;
4286 def_ad_bytes = 8;
4287 break;
4288#endif
4289 default:
1d2887e2 4290 return EMULATION_FAILED;
dde7e6d1
AK		 4291 }
4292
9dac77fa
AK		 4293 ctxt->op_bytes = def_op_bytes;
4294 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4295
4296 /* Legacy prefixes. */
4297 for (;;) {
e85a1085 4298 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4299 case 0x66: /* operand-size override */
0d7cdee8 4300 op_prefix = true;
dde7e6d1 4301 /* switch between 2/4 bytes */
9dac77fa 4302 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4303 break;
4304 case 0x67: /* address-size override */
4305 if (mode == X86EMUL_MODE_PROT64)
4306 /* switch between 4/8 bytes */
9dac77fa 4307 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4308 else
4309 /* switch between 2/4 bytes */
9dac77fa 4310 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4311 break;
4312 case 0x26: /* ES override */
4313 case 0x2e: /* CS override */
4314 case 0x36: /* SS override */
4315 case 0x3e: /* DS override */
573e80fe
BD		 4316 has_seg_override = true;
4317 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4318 break;
4319 case 0x64: /* FS override */
4320 case 0x65: /* GS override */
573e80fe
BD		 4321 has_seg_override = true;
4322 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4323 break;
4324 case 0x40 ... 0x4f: /* REX */
4325 if (mode != X86EMUL_MODE_PROT64)
4326 goto done_prefixes;
9dac77fa 4327 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4328 continue;
4329 case 0xf0: /* LOCK */
9dac77fa 4330 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4331 break;
4332 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4333 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4334 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4335 break;
4336 default:
4337 goto done_prefixes;
4338 }
4339
4340 /* Any legacy prefix after a REX prefix nullifies its effect. */
4341
9dac77fa 4342 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4343 }
4344
4345done_prefixes:
4346
4347 /* REX prefix. */
9dac77fa
AK		 4348 if (ctxt->rex_prefix & 8)
4349 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4350
4351 /* Opcode byte(s). */
9dac77fa 4352 opcode = opcode_table[ctxt->b];
d3ad6243 4353 /* Two-byte opcode? */
9dac77fa 4354 if (ctxt->b == 0x0f) {
1ce19dc1 4355 ctxt->opcode_len = 2;
e85a1085 4356 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4357 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4358
4359 /* 0F_38 opcode map */
4360 if (ctxt->b == 0x38) {
4361 ctxt->opcode_len = 3;
4362 ctxt->b = insn_fetch(u8, ctxt);
4363 opcode = opcode_map_0f_38[ctxt->b];
4364 }
dde7e6d1 4365 }
9dac77fa 4366 ctxt->d = opcode.flags;
dde7e6d1 4367
9f4260e7
TY		 4368 if (ctxt->d & ModRM)
4369 ctxt->modrm = insn_fetch(u8, ctxt);
4370
7fe864dc
NA		 4371 /* vex-prefix instructions are not implemented */
4372 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4373 (mode == X86EMUL_MODE_PROT64 ||
4374 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4375 ctxt->d = NotImpl;
4376 }
4377
9dac77fa
AK		 4378 while (ctxt->d & GroupMask) {
4379 switch (ctxt->d & GroupMask) {
46561646 4380 case Group:
9dac77fa 4381 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4382 opcode = opcode.u.group[goffset];
4383 break;
4384 case GroupDual:
9dac77fa
AK		 4385 goffset = (ctxt->modrm >> 3) & 7;
4386 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4387 opcode = opcode.u.gdual->mod3[goffset];
4388 else
4389 opcode = opcode.u.gdual->mod012[goffset];
4390 break;
4391 case RMExt:
9dac77fa 4392 goffset = ctxt->modrm & 7;
01de8b09 4393 opcode = opcode.u.group[goffset];
46561646
AK		 4394 break;
4395 case Prefix:
9dac77fa 4396 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4397 return EMULATION_FAILED;
9dac77fa 4398 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4399 switch (simd_prefix) {
4400 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4401 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4402 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4403 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4404 }
4405 break;
045a282c
GN		 4406 case Escape:
4407 if (ctxt->modrm > 0xbf)
4408 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4409 else
4410 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4411 break;
46561646 4412 default:
1d2887e2 4413 return EMULATION_FAILED;
0d7cdee8 4414 }
46561646 4415
b1ea50b2 4416 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4417 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4418 }
4419
e24186e0
PB		 4420 /* Unrecognised? */
4421 if (ctxt->d == 0)
4422 return EMULATION_FAILED;
4423
9dac77fa 4424 ctxt->execute = opcode.u.execute;
dde7e6d1 4425
3a6095a0
NA		 4426 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4427 return EMULATION_FAILED;
4428
d40a6898 4429 if (unlikely(ctxt->d &
3a6095a0 4430 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
d40a6898
PB		 4431 /*
4432 * These are copied unconditionally here, and checked unconditionally
4433 * in x86_emulate_insn.
4434 */
4435 ctxt->check_perm = opcode.check_perm;
4436 ctxt->intercept = opcode.intercept;
dde7e6d1 4437
d40a6898
PB		 4438 if (ctxt->d & NotImpl)
4439 return EMULATION_FAILED;
d867162c 4440
d40a6898 4441 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4442 ctxt->op_bytes = 8;
7f9b4b75 4443
d40a6898
PB		 4444 if (ctxt->d & Op3264) {
4445 if (mode == X86EMUL_MODE_PROT64)
4446 ctxt->op_bytes = 8;
4447 else
4448 ctxt->op_bytes = 4;
4449 }
4450
4451 if (ctxt->d & Sse)
4452 ctxt->op_bytes = 16;
4453 else if (ctxt->d & Mmx)
4454 ctxt->op_bytes = 8;
4455 }
1253791d 4456
dde7e6d1 4457 /* ModRM and SIB bytes. */
9dac77fa 4458 if (ctxt->d & ModRM) {
f09ed83e 4459 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4460 if (!has_seg_override) {
4461 has_seg_override = true;
4462 ctxt->seg_override = ctxt->modrm_seg;
4463 }
9dac77fa 4464 } else if (ctxt->d & MemAbs)
f09ed83e 4465 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4466 if (rc != X86EMUL_CONTINUE)
4467 goto done;
4468
573e80fe
BD		 4469 if (!has_seg_override)
4470 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4471
573e80fe 4472 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4473
dde7e6d1
AK		 4474 /*
4475 * Decode and fetch the source operand: register, memory
4476 * or immediate.
4477 */
0fe59128 4478 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4479 if (rc != X86EMUL_CONTINUE)
4480 goto done;
4481
dde7e6d1
AK		 4482 /*
4483 * Decode and fetch the second source operand: register, memory
4484 * or immediate.
4485 */
4dd6a57d 4486 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4487 if (rc != X86EMUL_CONTINUE)
4488 goto done;
4489
dde7e6d1 4490 /* Decode and fetch the destination operand: register or memory. */
a9945549 4491 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4492
4493done:
41061cdb 4494 if (ctxt->rip_relative)
f09ed83e 4495 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4496
1d2887e2 4497 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4498}
4499
1cb3f3ae
XG		 4500bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4501{
4502 return ctxt->d & PageTable;
4503}
4504
3e2f65d5
GN		 4505static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4506{
3e2f65d5
GN		 4507 /* The second termination condition only applies for REPE
4508 * and REPNE. Test if the repeat string operation prefix is
4509 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4510 * corresponding termination condition according to:
4511 * - if REPE/REPZ and ZF = 0 then done
4512 * - if REPNE/REPNZ and ZF = 1 then done
4513 */
9dac77fa
AK		 4514 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4515 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4516 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4517 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4518 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4519 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4520 return true;
4521
4522 return false;
4523}
4524
cbe2c9d3
AK		 4525static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4526{
4527 bool fault = false;
4528
4529 ctxt->ops->get_fpu(ctxt);
4530 asm volatile("1: fwait \n\t"
4531 "2: \n\t"
4532 ".pushsection .fixup,\"ax\" \n\t"
4533 "3: \n\t"
4534 "movb $1, %[fault] \n\t"
4535 "jmp 2b \n\t"
4536 ".popsection \n\t"
4537 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4538 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4539 ctxt->ops->put_fpu(ctxt);
4540
4541 if (unlikely(fault))
4542 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4543
4544 return X86EMUL_CONTINUE;
4545}
4546
4547static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4548 struct operand *op)
4549{
4550 if (op->type == OP_MM)
4551 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4552}
4553
e28bbd44
AK		 4554static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4555{
4556 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4557 if (!(ctxt->d & ByteOp))
4558 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4559 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4560 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4561 [fastop]"+S"(fop)
4562 : "c"(ctxt->src2.val));
e28bbd44 4563 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4564 if (!fop) /* exception is returned in fop variable */
4565 return emulate_de(ctxt);
e28bbd44
AK		 4566 return X86EMUL_CONTINUE;
4567}
dd856efa 4568
1498507a
BD		 4569void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4570{
573e80fe
BD		 4571 memset(&ctxt->rip_relative, 0,
4572 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4573
1498507a
BD		 4574 ctxt->io_read.pos = 0;
4575 ctxt->io_read.end = 0;
1498507a
BD		 4576 ctxt->mem_read.end = 0;
4577}
4578
7b105ca2 4579int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4580{
0225fb50 4581 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4582 int rc = X86EMUL_CONTINUE;
9dac77fa 4583 int saved_dst_type = ctxt->dst.type;
8b4caf66 4584
9dac77fa 4585 ctxt->mem_read.pos = 0;
310b5d30 4586
e24186e0
PB		 4587 /* LOCK prefix is allowed only with some instructions */
4588 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4589 rc = emulate_ud(ctxt);
1161624f
GN		 4590 goto done;
4591 }
4592
e24186e0 4593 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4594 rc = emulate_ud(ctxt);
d380a5e4
GN		 4595 goto done;
4596 }
4597
d40a6898
PB		 4598 if (unlikely(ctxt->d &
4599 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4600 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4601 (ctxt->d & Undefined)) {
4602 rc = emulate_ud(ctxt);
4603 goto done;
4604 }
1253791d 4605
d40a6898
PB		 4606 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4607 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4608 rc = emulate_ud(ctxt);
cbe2c9d3 4609 goto done;
d40a6898 4610 }
cbe2c9d3 4611
d40a6898
PB		 4612 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4613 rc = emulate_nm(ctxt);
c4f035c6 4614 goto done;
d40a6898 4615 }
c4f035c6 4616
d40a6898
PB		 4617 if (ctxt->d & Mmx) {
4618 rc = flush_pending_x87_faults(ctxt);
4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
4621 /*
4622 * Now that we know the fpu is exception safe, we can fetch
4623 * operands from it.
4624 */
4625 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4626 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4627 if (!(ctxt->d & Mov))
4628 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4629 }
e92805ac 4630
685bbf4a 4631 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4632 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4633 X86_ICPT_PRE_EXCEPT);
4634 if (rc != X86EMUL_CONTINUE)
4635 goto done;
4636 }
8ea7d6ae 4637
d40a6898
PB		 4638 /* Privileged instruction can be executed only in CPL=0 */
4639 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4640 if (ctxt->d & PrivUD)
4641 rc = emulate_ud(ctxt);
4642 else
4643 rc = emulate_gp(ctxt, 0);
d09beabd 4644 goto done;
d40a6898 4645 }
d09beabd 4646
d40a6898
PB		 4647 /* Instruction can only be executed in protected mode */
4648 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4649 rc = emulate_ud(ctxt);
c4f035c6 4650 goto done;
d40a6898 4651 }
c4f035c6 4652
d40a6898 4653 /* Do instruction specific permission checks */
685bbf4a 4654 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4655 rc = ctxt->check_perm(ctxt);
4656 if (rc != X86EMUL_CONTINUE)
4657 goto done;
4658 }
4659
685bbf4a 4660 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4661 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4662 X86_ICPT_POST_EXCEPT);
4663 if (rc != X86EMUL_CONTINUE)
4664 goto done;
4665 }
4666
4667 if (ctxt->rep_prefix && (ctxt->d & String)) {
4668 /* All REP prefixes have the same first termination condition */
4669 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4670 ctxt->eip = ctxt->_eip;
4467c3f1 4671 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4672 goto done;
4673 }
b9fa9d6b 4674 }
b9fa9d6b
AK		 4675 }
4676
9dac77fa
AK		 4677 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4678 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4679 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4680 if (rc != X86EMUL_CONTINUE)
8b4caf66 4681 goto done;
9dac77fa 4682 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4683 }
4684
9dac77fa
AK		 4685 if (ctxt->src2.type == OP_MEM) {
4686 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4687 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4688 if (rc != X86EMUL_CONTINUE)
4689 goto done;
4690 }
4691
9dac77fa 4692 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4693 goto special_insn;
4694
4695
9dac77fa 4696 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4697 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4698 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4699 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4700 if (rc != X86EMUL_CONTINUE)
4701 goto done;
038e51de 4702 }
9dac77fa 4703 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4704
018a98db
AK		 4705special_insn:
4706
685bbf4a 4707 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4708 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4709 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4710 if (rc != X86EMUL_CONTINUE)
4711 goto done;
4712 }
4713
b9a1ecb9
NA		 4714 if (ctxt->rep_prefix && (ctxt->d & String))
4715 ctxt->eflags |= EFLG_RF;
4716 else
4717 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4718
9dac77fa 4719 if (ctxt->execute) {
e28bbd44
AK		 4720 if (ctxt->d & Fastop) {
4721 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4722 rc = fastop(ctxt, fop);
4723 if (rc != X86EMUL_CONTINUE)
4724 goto done;
4725 goto writeback;
4726 }
9dac77fa 4727 rc = ctxt->execute(ctxt);
ef65c889
AK		 4728 if (rc != X86EMUL_CONTINUE)
4729 goto done;
4730 goto writeback;
4731 }
4732
1ce19dc1 4733 if (ctxt->opcode_len == 2)
6aa8b732 4734 goto twobyte_insn;
0bc5eedb
BP		 4735 else if (ctxt->opcode_len == 3)
4736 goto threebyte_insn;
6aa8b732 4737
9dac77fa 4738 switch (ctxt->b) {
6aa8b732 4739 case 0x63: /* movsxd */
8b4caf66 4740 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4741 goto cannot_emulate;
9dac77fa 4742 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4743 break;
b2833e3c 4744 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4745 if (test_cc(ctxt->b, ctxt->eflags))
4746 jmp_rel(ctxt, ctxt->src.val);
018a98db 4747 break;
7e0b54b1 4748 case 0x8d: /* lea r16/r32, m */
9dac77fa 4749 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4750 break;
3d9e77df 4751 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4752 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4753 ctxt->dst.type = OP_NONE;
4754 else
4755 rc = em_xchg(ctxt);
e4f973ae 4756 break;
e8b6fa70 4757 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4758 switch (ctxt->op_bytes) {
4759 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4760 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4761 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4762 }
4763 break;
6e154e56 4764 case 0xcc: /* int3 */
5c5df76b
TY		 4765 rc = emulate_int(ctxt, 3);
4766 break;
6e154e56 4767 case 0xcd: /* int n */
9dac77fa 4768 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4769 break;
4770 case 0xce: /* into */
5c5df76b
TY		 4771 if (ctxt->eflags & EFLG_OF)
4772 rc = emulate_int(ctxt, 4);
6e154e56 4773 break;
1a52e051 4774 case 0xe9: /* jmp rel */
db5b0762 4775 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4776 jmp_rel(ctxt, ctxt->src.val);
4777 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4778 break;
111de5d6 4779 case 0xf4: /* hlt */
6c3287f7 4780 ctxt->ops->halt(ctxt);
19fdfa0d 4781 break;
111de5d6
AK		 4782 case 0xf5: /* cmc */
4783 /* complement carry flag from eflags reg */
4784 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4785 break;
4786 case 0xf8: /* clc */
4787 ctxt->eflags &= ~EFLG_CF;
111de5d6 4788 break;
8744aa9a
MG		 4789 case 0xf9: /* stc */
4790 ctxt->eflags |= EFLG_CF;
4791 break;
fb4616f4
MG		 4792 case 0xfc: /* cld */
4793 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4794 break;
4795 case 0xfd: /* std */
4796 ctxt->eflags |= EFLG_DF;
fb4616f4 4797 break;
91269b8f
AK		 4798 default:
4799 goto cannot_emulate;
6aa8b732 4800 }
018a98db 4801
7d9ddaed
AK		 4802 if (rc != X86EMUL_CONTINUE)
4803 goto done;
4804
018a98db 4805writeback:
fb32b1ed
AK		 4806 if (ctxt->d & SrcWrite) {
4807 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4808 rc = writeback(ctxt, &ctxt->src);
4809 if (rc != X86EMUL_CONTINUE)
4810 goto done;
4811 }
ee212297
NA		 4812 if (!(ctxt->d & NoWrite)) {
4813 rc = writeback(ctxt, &ctxt->dst);
4814 if (rc != X86EMUL_CONTINUE)
4815 goto done;
4816 }
018a98db 4817
5cd21917
GN		 4818 /*
4819 * restore dst type in case the decoding will be reused
4820 * (happens for string instruction )
4821 */
9dac77fa 4822 ctxt->dst.type = saved_dst_type;
5cd21917 4823
9dac77fa 4824 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4825 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4826
9dac77fa 4827 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4828 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4829
9dac77fa 4830 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4831 unsigned int count;
9dac77fa 4832 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4833 if ((ctxt->d & SrcMask) == SrcSI)
4834 count = ctxt->src.count;
4835 else
4836 count = ctxt->dst.count;
4837 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4838 -count);
3e2f65d5 4839
d2ddd1c4
GN		 4840 if (!string_insn_completed(ctxt)) {
4841 /*
4842 * Re-enter guest when pio read ahead buffer is empty
4843 * or, if it is not used, after each 1024 iteration.
4844 */
dd856efa 4845 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4846 (r->end == 0 || r->end != r->pos)) {
4847 /*
4848 * Reset read cache. Usually happens before
4849 * decode, but since instruction is restarted
4850 * we have to do it here.
4851 */
9dac77fa 4852 ctxt->mem_read.end = 0;
dd856efa 4853 writeback_registers(ctxt);
d2ddd1c4
GN		 4854 return EMULATION_RESTART;
4855 }
4856 goto done; /* skip rip writeback */
0fa6ccbd 4857 }
b9a1ecb9 4858 ctxt->eflags &= ~EFLG_RF;
5cd21917 4859 }
d2ddd1c4 4860
9dac77fa 4861 ctxt->eip = ctxt->_eip;
018a98db
AK		 4862
4863done:
e0ad0b47
PB		 4864 if (rc == X86EMUL_PROPAGATE_FAULT) {
4865 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 4866 ctxt->have_exception = true;
e0ad0b47 4867 }
775fde86
JR		 4868 if (rc == X86EMUL_INTERCEPTED)
4869 return EMULATION_INTERCEPTED;
4870
dd856efa
AK		 4871 if (rc == X86EMUL_CONTINUE)
4872 writeback_registers(ctxt);
4873
d2ddd1c4 4874 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4875
4876twobyte_insn:
9dac77fa 4877 switch (ctxt->b) {
018a98db 4878 case 0x09: /* wbinvd */
cfb22375 4879 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4880 break;
4881 case 0x08: /* invd */
018a98db
AK		 4882 case 0x0d: /* GrpP (prefetch) */
4883 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4884 case 0x1f: /* nop */
018a98db
AK		 4885 break;
4886 case 0x20: /* mov cr, reg */
9dac77fa 4887 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4888 break;
6aa8b732 4889 case 0x21: /* mov from dr to reg */
9dac77fa 4890 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4891 break;
6aa8b732 4892 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4893 if (test_cc(ctxt->b, ctxt->eflags))
4894 ctxt->dst.val = ctxt->src.val;
4895 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4896 ctxt->op_bytes != 4)
9dac77fa 4897 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4898 break;
b2833e3c 4899 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4900 if (test_cc(ctxt->b, ctxt->eflags))
4901 jmp_rel(ctxt, ctxt->src.val);
018a98db 4902 break;
ee45b58e 4903 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4904 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4905 break;
2a7c5b8b
GC		 4906 case 0xae: /* clflush */
4907 break;
6aa8b732 4908 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4909 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4910 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4911 : (u16) ctxt->src.val;
6aa8b732 4912 break;
6aa8b732 4913 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4914 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4915 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4916 (s16) ctxt->src.val;
6aa8b732 4917 break;
a012e65a 4918 case 0xc3: /* movnti */
9dac77fa 4919 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4920 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4921 (u32) ctxt->src.val;
a012e65a 4922 break;
91269b8f
AK		 4923 default:
4924 goto cannot_emulate;
6aa8b732 4925 }
7d9ddaed 4926
0bc5eedb
BP		 4927threebyte_insn:
4928
7d9ddaed
AK		 4929 if (rc != X86EMUL_CONTINUE)
4930 goto done;
4931
6aa8b732
AK		 4932 goto writeback;
4933
4934cannot_emulate:
a0c0ab2f 4935 return EMULATION_FAILED;
6aa8b732 4936}
dd856efa
AK		 4937
4938void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4939{
4940 invalidate_registers(ctxt);
4941}
4942
4943void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4944{
4945 writeback_registers(ctxt);
4946}
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