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KVM: inject #UD in 64bit mode from instruction that are not valid there
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
e99f0507 36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 78/* Misc flags */
d380a5e4 79#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 80#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 81#define No64 (1<<28)
0dc8d10f
GT		 82/* Source 2 operand type */
83#define Src2None (0<<29)
84#define Src2CL (1<<29)
85#define Src2ImmByte (2<<29)
86#define Src2One (3<<29)
a5f868bd 87#define Src2Imm16 (4<<29)
0dc8d10f 88#define Src2Mask (7<<29)
6aa8b732 89
43bb19cd 90enum {
1d6ad207 91 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 92 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 93 Group8, Group9,
43bb19cd
AK		 94};
95
45ed60b3 96static u32 opcode_table[256] = {
6aa8b732 97 /* 0x00 - 0x07 */
d380a5e4 98 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 99 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 100 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 101 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 102 /* 0x08 - 0x0F */
d380a5e4 103 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 105 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
106 ImplicitOps | Stack | No64, 0,
6aa8b732 107 /* 0x10 - 0x17 */
d380a5e4 108 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 110 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 111 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 112 /* 0x18 - 0x1F */
d380a5e4 113 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 115 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 116 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 117 /* 0x20 - 0x27 */
d380a5e4 118 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 120 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 121 /* 0x28 - 0x2F */
d380a5e4 122 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 123 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
124 0, 0, 0, 0,
125 /* 0x30 - 0x37 */
d380a5e4 126 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 127 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
128 0, 0, 0, 0,
129 /* 0x38 - 0x3F */
130 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
131 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 132 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
133 0, 0,
d77a2507 134 /* 0x40 - 0x47 */
33615aa9 135 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 136 /* 0x48 - 0x4F */
33615aa9 137 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 138 /* 0x50 - 0x57 */
6e3d5dfb
AK		 139 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
140 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 141 /* 0x58 - 0x5F */
6e3d5dfb
AK		 142 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
143 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 144 /* 0x60 - 0x67 */
abcf14b5
MG		 145 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
146 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 147 0, 0, 0, 0,
148 /* 0x68 - 0x6F */
91ed7a0e 149 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 150 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
151 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 152 /* 0x70 - 0x77 */
b2833e3c
GN		 153 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 155 /* 0x78 - 0x7F */
b2833e3c
GN		 156 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
157 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 158 /* 0x80 - 0x87 */
1d6ad207
AK		 159 Group | Group1_80, Group | Group1_81,
160 Group | Group1_82, Group | Group1_83,
6aa8b732 161 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 162 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 163 /* 0x88 - 0x8F */
164 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
165 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 166 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 167 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 168 /* 0x90 - 0x97 */
169 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
170 /* 0x98 - 0x9F */
d8769fed 171 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 172 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 173 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 174 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
175 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 176 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
177 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 178 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 179 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
180 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
181 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 182 /* 0xB0 - 0xB7 */
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
185 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
186 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
187 /* 0xB8 - 0xBF */
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
190 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
191 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 192 /* 0xC0 - 0xC7 */
d9413cd7 193 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 194 0, ImplicitOps | Stack, 0, 0,
d9413cd7 195 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 196 /* 0xC8 - 0xCF */
e637b823 197 0, 0, 0, ImplicitOps | Stack,
d8769fed 198 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 199 /* 0xD0 - 0xD7 */
200 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
201 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
202 0, 0, 0, 0,
203 /* 0xD8 - 0xDF */
204 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 205 /* 0xE0 - 0xE7 */
a6a3034c 206 0, 0, 0, 0,
84ce66a6
GN		 207 ByteOp | SrcImmUByte, SrcImmUByte,
208 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 209 /* 0xE8 - 0xEF */
d53c4777 210 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 211 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 212 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
213 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 214 /* 0xF0 - 0xF7 */
215 0, 0, 0, 0,
e92805ac 216 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 217 /* 0xF8 - 0xFF */
b284be57 218 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 219 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 220};
221
45ed60b3 222static u32 twobyte_table[256] = {
6aa8b732 223 /* 0x00 - 0x0F */
e92805ac
GN		 224 0, Group | GroupDual | Group7, 0, 0,
225 0, ImplicitOps, ImplicitOps | Priv, 0,
226 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
227 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 228 /* 0x10 - 0x1F */
229 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x20 - 0x2F */
e92805ac
GN		 231 ModRM | ImplicitOps | Priv, ModRM | Priv,
232 ModRM | ImplicitOps | Priv, ModRM | Priv,
233 0, 0, 0, 0,
6aa8b732
AK		 234 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x30 - 0x3F */
e92805ac
GN		 236 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
237 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 238 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 239 /* 0x40 - 0x47 */
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
243 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
244 /* 0x48 - 0x4F */
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 /* 0x50 - 0x5F */
250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
251 /* 0x60 - 0x6F */
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
253 /* 0x70 - 0x7F */
254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
255 /* 0x80 - 0x8F */
b2833e3c
GN		 256 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
257 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 258 /* 0x90 - 0x9F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0xA0 - 0xA7 */
0934ac9d
MG		 261 ImplicitOps | Stack, ImplicitOps | Stack,
262 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 263 DstMem | SrcReg | Src2ImmByte | ModRM,
264 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 265 /* 0xA8 - 0xAF */
0934ac9d 266 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 267 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 268 DstMem | SrcReg | Src2ImmByte | ModRM,
269 DstMem | SrcReg | Src2CL | ModRM,
270 ModRM, 0,
6aa8b732 271 /* 0xB0 - 0xB7 */
d380a5e4
GN		 272 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
273 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 274 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
275 DstReg | SrcMem16 | ModRM | Mov,
276 /* 0xB8 - 0xBF */
d380a5e4
GN		 277 0, 0,
278 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 279 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
280 DstReg | SrcMem16 | ModRM | Mov,
281 /* 0xC0 - 0xCF */
60a29d4e
GN		 282 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
283 0, 0, 0, Group | GroupDual | Group9,
a012e65a 284 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 285 /* 0xD0 - 0xDF */
286 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
287 /* 0xE0 - 0xEF */
288 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
289 /* 0xF0 - 0xFF */
290 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
291};
292
45ed60b3 293static u32 group_table[] = {
1d6ad207 294 [Group1_80*8] =
d380a5e4
GN		 295 ByteOp | DstMem | SrcImm | ModRM | Lock,
296 ByteOp | DstMem | SrcImm | ModRM | Lock,
297 ByteOp | DstMem | SrcImm | ModRM | Lock,
298 ByteOp | DstMem | SrcImm | ModRM | Lock,
299 ByteOp | DstMem | SrcImm | ModRM | Lock,
300 ByteOp | DstMem | SrcImm | ModRM | Lock,
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 303 [Group1_81*8] =
d380a5e4
GN		 304 DstMem | SrcImm | ModRM | Lock,
305 DstMem | SrcImm | ModRM | Lock,
306 DstMem | SrcImm | ModRM | Lock,
307 DstMem | SrcImm | ModRM | Lock,
308 DstMem | SrcImm | ModRM | Lock,
309 DstMem | SrcImm | ModRM | Lock,
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM,
1d6ad207 312 [Group1_82*8] =
e424e191
GN		 313 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
314 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
315 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
316 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
317 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
318 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 321 [Group1_83*8] =
d380a5e4
GN		 322 DstMem | SrcImmByte | ModRM | Lock,
323 DstMem | SrcImmByte | ModRM | Lock,
324 DstMem | SrcImmByte | ModRM | Lock,
325 DstMem | SrcImmByte | ModRM | Lock,
326 DstMem | SrcImmByte | ModRM | Lock,
327 DstMem | SrcImmByte | ModRM | Lock,
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 330 [Group1A*8] =
331 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 332 [Group3_Byte*8] =
333 ByteOp | SrcImm | DstMem | ModRM, 0,
334 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
335 0, 0, 0, 0,
336 [Group3*8] =
41afa025 337 DstMem | SrcImm | ModRM, 0,
6eb06cb2 338 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 339 0, 0, 0, 0,
fd60754e
AK		 340 [Group4*8] =
341 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
342 0, 0, 0, 0, 0, 0,
343 [Group5*8] =
d19292e4
MG		 344 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
345 SrcMem | ModRM | Stack, 0,
ef46f18e 346 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1 347 [Group7*8] =
e92805ac 348 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 349 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 350 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 351 [Group8*8] =
352 0, 0, 0, 0,
d380a5e4
GN		 353 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
354 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 355 [Group9*8] =
d380a5e4 356 0, ImplicitOps | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 357};
358
45ed60b3 359static u32 group2_table[] = {
d95058a1 360 [Group7*8] =
e92805ac 361 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM,
16286d08
AK		 362 SrcNone | ModRM | DstMem | Mov, 0,
363 SrcMem16 | ModRM | Mov, 0,
60a29d4e
GN		 364 [Group9*8] =
365 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 366};
367
6aa8b732 368/* EFLAGS bit definitions. */
d4c6a154
GN		 369#define EFLG_ID (1<<21)
370#define EFLG_VIP (1<<20)
371#define EFLG_VIF (1<<19)
372#define EFLG_AC (1<<18)
b1d86143
AP		 373#define EFLG_VM (1<<17)
374#define EFLG_RF (1<<16)
d4c6a154
GN		 375#define EFLG_IOPL (3<<12)
376#define EFLG_NT (1<<14)
6aa8b732
AK		 377#define EFLG_OF (1<<11)
378#define EFLG_DF (1<<10)
b1d86143 379#define EFLG_IF (1<<9)
d4c6a154 380#define EFLG_TF (1<<8)
6aa8b732
AK		 381#define EFLG_SF (1<<7)
382#define EFLG_ZF (1<<6)
383#define EFLG_AF (1<<4)
384#define EFLG_PF (1<<2)
385#define EFLG_CF (1<<0)
386
387/*
388 * Instruction emulation:
389 * Most instructions are emulated directly via a fragment of inline assembly
390 * code. This allows us to save/restore EFLAGS and thus very easily pick up
391 * any modified flags.
392 */
393
05b3e0c2 394#if defined(CONFIG_X86_64)
6aa8b732
AK		 395#define _LO32 "k" /* force 32-bit operand */
396#define _STK "%%rsp" /* stack pointer */
397#elif defined(__i386__)
398#define _LO32 "" /* force 32-bit operand */
399#define _STK "%%esp" /* stack pointer */
400#endif
401
402/*
403 * These EFLAGS bits are restored from saved value during emulation, and
404 * any changes are written back to the saved value after emulation.
405 */
406#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
407
408/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 409#define _PRE_EFLAGS(_sav, _msk, _tmp) \
410 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
411 "movl %"_sav",%"_LO32 _tmp"; " \
412 "push %"_tmp"; " \
413 "push %"_tmp"; " \
414 "movl %"_msk",%"_LO32 _tmp"; " \
415 "andl %"_LO32 _tmp",("_STK"); " \
416 "pushf; " \
417 "notl %"_LO32 _tmp"; " \
418 "andl %"_LO32 _tmp",("_STK"); " \
419 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
420 "pop %"_tmp"; " \
421 "orl %"_LO32 _tmp",("_STK"); " \
422 "popf; " \
423 "pop %"_sav"; "
6aa8b732
AK		 424
425/* After executing instruction: write-back necessary bits in EFLAGS. */
426#define _POST_EFLAGS(_sav, _msk, _tmp) \
427 /* _sav |= EFLAGS & _msk; */ \
428 "pushf; " \
429 "pop %"_tmp"; " \
430 "andl %"_msk",%"_LO32 _tmp"; " \
431 "orl %"_LO32 _tmp",%"_sav"; "
432
dda96d8f
AK		 433#ifdef CONFIG_X86_64
434#define ON64(x) x
435#else
436#define ON64(x)
437#endif
438
6b7ad61f
AK		 439#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
440 do { \
441 __asm__ __volatile__ ( \
442 _PRE_EFLAGS("0", "4", "2") \
443 _op _suffix " %"_x"3,%1; " \
444 _POST_EFLAGS("0", "4", "2") \
445 : "=m" (_eflags), "=m" ((_dst).val), \
446 "=&r" (_tmp) \
447 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 448 } while (0)
6b7ad61f
AK		 449
450
6aa8b732
AK		 451/* Raw emulation: instruction has two explicit operands. */
452#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 453 do { \
454 unsigned long _tmp; \
455 \
456 switch ((_dst).bytes) { \
457 case 2: \
458 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
459 break; \
460 case 4: \
461 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
462 break; \
463 case 8: \
464 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
465 break; \
466 } \
6aa8b732
AK		 467 } while (0)
468
469#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
470 do { \
6b7ad61f 471 unsigned long _tmp; \
d77c26fc 472 switch ((_dst).bytes) { \
6aa8b732 473 case 1: \
6b7ad61f 474 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 475 break; \
476 default: \
477 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
478 _wx, _wy, _lx, _ly, _qx, _qy); \
479 break; \
480 } \
481 } while (0)
482
483/* Source operand is byte-sized and may be restricted to just %cl. */
484#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
485 __emulate_2op(_op, _src, _dst, _eflags, \
486 "b", "c", "b", "c", "b", "c", "b", "c")
487
488/* Source operand is byte, word, long or quad sized. */
489#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
490 __emulate_2op(_op, _src, _dst, _eflags, \
491 "b", "q", "w", "r", _LO32, "r", "", "r")
492
493/* Source operand is word, long or quad sized. */
494#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
495 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
496 "w", "r", _LO32, "r", "", "r")
497
d175226a
GT		 498/* Instruction has three operands and one operand is stored in ECX register */
499#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
500 do { \
501 unsigned long _tmp; \
502 _type _clv = (_cl).val; \
503 _type _srcv = (_src).val; \
504 _type _dstv = (_dst).val; \
505 \
506 __asm__ __volatile__ ( \
507 _PRE_EFLAGS("0", "5", "2") \
508 _op _suffix " %4,%1 \n" \
509 _POST_EFLAGS("0", "5", "2") \
510 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
511 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
512 ); \
513 \
514 (_cl).val = (unsigned long) _clv; \
515 (_src).val = (unsigned long) _srcv; \
516 (_dst).val = (unsigned long) _dstv; \
517 } while (0)
518
519#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
520 do { \
521 switch ((_dst).bytes) { \
522 case 2: \
523 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
524 "w", unsigned short); \
525 break; \
526 case 4: \
527 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
528 "l", unsigned int); \
529 break; \
530 case 8: \
531 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
532 "q", unsigned long)); \
533 break; \
534 } \
535 } while (0)
536
dda96d8f 537#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 538 do { \
539 unsigned long _tmp; \
540 \
dda96d8f
AK		 541 __asm__ __volatile__ ( \
542 _PRE_EFLAGS("0", "3", "2") \
543 _op _suffix " %1; " \
544 _POST_EFLAGS("0", "3", "2") \
545 : "=m" (_eflags), "+m" ((_dst).val), \
546 "=&r" (_tmp) \
547 : "i" (EFLAGS_MASK)); \
548 } while (0)
549
550/* Instruction has only one explicit operand (no source operand). */
551#define emulate_1op(_op, _dst, _eflags) \
552 do { \
d77c26fc 553 switch ((_dst).bytes) { \
dda96d8f
AK		 554 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
555 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
556 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
557 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 558 } \
559 } while (0)
560
6aa8b732
AK		 561/* Fetch next part of the instruction being emulated. */
562#define insn_fetch(_type, _size, _eip) \
563({ unsigned long _x; \
62266869 564 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 565 if (rc != 0) \
6aa8b732
AK		 566 goto done; \
567 (_eip) += (_size); \
568 (_type)_x; \
569})
570
ddcb2885
HH		 571static inline unsigned long ad_mask(struct decode_cache *c)
572{
573 return (1UL << (c->ad_bytes << 3)) - 1;
574}
575
6aa8b732 576/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 577static inline unsigned long
578address_mask(struct decode_cache *c, unsigned long reg)
579{
580 if (c->ad_bytes == sizeof(unsigned long))
581 return reg;
582 else
583 return reg & ad_mask(c);
584}
585
586static inline unsigned long
587register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
588{
589 return base + address_mask(c, reg);
590}
591
7a957275
HH		 592static inline void
593register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
594{
595 if (c->ad_bytes == sizeof(unsigned long))
596 *reg += inc;
597 else
598 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
599}
6aa8b732 600
7a957275
HH		 601static inline void jmp_rel(struct decode_cache *c, int rel)
602{
603 register_address_increment(c, &c->eip, rel);
604}
098c937b 605
7a5b56df
AK		 606static void set_seg_override(struct decode_cache *c, int seg)
607{
608 c->has_seg_override = true;
609 c->seg_override = seg;
610}
611
612static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
613{
614 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
615 return 0;
616
617 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
618}
619
620static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
621 struct decode_cache *c)
622{
623 if (!c->has_seg_override)
624 return 0;
625
626 return seg_base(ctxt, c->seg_override);
627}
628
629static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
630{
631 return seg_base(ctxt, VCPU_SREG_ES);
632}
633
634static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
635{
636 return seg_base(ctxt, VCPU_SREG_SS);
637}
638
62266869
AK		 639static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
640 struct x86_emulate_ops *ops,
641 unsigned long linear, u8 *dest)
642{
643 struct fetch_cache *fc = &ctxt->decode.fetch;
644 int rc;
645 int size;
646
647 if (linear < fc->start || linear >= fc->end) {
648 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
1871c602 649 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
62266869
AK		 650 if (rc)
651 return rc;
652 fc->start = linear;
653 fc->end = linear + size;
654 }
655 *dest = fc->data[linear - fc->start];
656 return 0;
657}
658
659static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
660 struct x86_emulate_ops *ops,
661 unsigned long eip, void *dest, unsigned size)
662{
663 int rc = 0;
664
eb3c79e6
AK		 665 /* x86 instructions are limited to 15 bytes. */
666 if (eip + size - ctxt->decode.eip_orig > 15)
667 return X86EMUL_UNHANDLEABLE;
62266869
AK		 668 eip += ctxt->cs_base;
669 while (size--) {
670 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
671 if (rc)
672 return rc;
673 }
674 return 0;
675}
676
1e3c5cb0
RR		 677/*
678 * Given the 'reg' portion of a ModRM byte, and a register block, return a
679 * pointer into the block that addresses the relevant register.
680 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
681 */
682static void *decode_register(u8 modrm_reg, unsigned long *regs,
683 int highbyte_regs)
6aa8b732
AK		 684{
685 void *p;
686
687 p = &regs[modrm_reg];
688 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
689 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
690 return p;
691}
692
693static int read_descriptor(struct x86_emulate_ctxt *ctxt,
694 struct x86_emulate_ops *ops,
695 void *ptr,
696 u16 *size, unsigned long *address, int op_bytes)
697{
698 int rc;
699
700 if (op_bytes == 2)
701 op_bytes = 3;
702 *address = 0;
cebff02b 703 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 704 ctxt->vcpu, NULL);
6aa8b732
AK		 705 if (rc)
706 return rc;
cebff02b 707 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 708 ctxt->vcpu, NULL);
6aa8b732
AK		 709 return rc;
710}
711
bbe9abbd
NK		 712static int test_cc(unsigned int condition, unsigned int flags)
713{
714 int rc = 0;
715
716 switch ((condition & 15) >> 1) {
717 case 0: /* o */
718 rc |= (flags & EFLG_OF);
719 break;
720 case 1: /* b/c/nae */
721 rc |= (flags & EFLG_CF);
722 break;
723 case 2: /* z/e */
724 rc |= (flags & EFLG_ZF);
725 break;
726 case 3: /* be/na */
727 rc |= (flags & (EFLG_CF|EFLG_ZF));
728 break;
729 case 4: /* s */
730 rc |= (flags & EFLG_SF);
731 break;
732 case 5: /* p/pe */
733 rc |= (flags & EFLG_PF);
734 break;
735 case 7: /* le/ng */
736 rc |= (flags & EFLG_ZF);
737 /* fall through */
738 case 6: /* l/nge */
739 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
740 break;
741 }
742
743 /* Odd condition identifiers (lsb == 1) have inverted sense. */
744 return (!!rc ^ (condition & 1));
745}
746
3c118e24
AK		 747static void decode_register_operand(struct operand *op,
748 struct decode_cache *c,
3c118e24
AK		 749 int inhibit_bytereg)
750{
33615aa9 751 unsigned reg = c->modrm_reg;
9f1ef3f8 752 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 753
754 if (!(c->d & ModRM))
755 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 756 op->type = OP_REG;
757 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 758 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 759 op->val = *(u8 *)op->ptr;
760 op->bytes = 1;
761 } else {
33615aa9 762 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 763 op->bytes = c->op_bytes;
764 switch (op->bytes) {
765 case 2:
766 op->val = *(u16 *)op->ptr;
767 break;
768 case 4:
769 op->val = *(u32 *)op->ptr;
770 break;
771 case 8:
772 op->val = *(u64 *) op->ptr;
773 break;
774 }
775 }
776 op->orig_val = op->val;
777}
778
1c73ef66
AK		 779static int decode_modrm(struct x86_emulate_ctxt *ctxt,
780 struct x86_emulate_ops *ops)
781{
782 struct decode_cache *c = &ctxt->decode;
783 u8 sib;
f5b4edcd 784 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 785 int rc = 0;
786
787 if (c->rex_prefix) {
788 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
789 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
790 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
791 }
792
793 c->modrm = insn_fetch(u8, 1, c->eip);
794 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
795 c->modrm_reg |= (c->modrm & 0x38) >> 3;
796 c->modrm_rm |= (c->modrm & 0x07);
797 c->modrm_ea = 0;
798 c->use_modrm_ea = 1;
799
800 if (c->modrm_mod == 3) {
107d6d2e
AK		 801 c->modrm_ptr = decode_register(c->modrm_rm,
802 c->regs, c->d & ByteOp);
803 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 804 return rc;
805 }
806
807 if (c->ad_bytes == 2) {
808 unsigned bx = c->regs[VCPU_REGS_RBX];
809 unsigned bp = c->regs[VCPU_REGS_RBP];
810 unsigned si = c->regs[VCPU_REGS_RSI];
811 unsigned di = c->regs[VCPU_REGS_RDI];
812
813 /* 16-bit ModR/M decode. */
814 switch (c->modrm_mod) {
815 case 0:
816 if (c->modrm_rm == 6)
817 c->modrm_ea += insn_fetch(u16, 2, c->eip);
818 break;
819 case 1:
820 c->modrm_ea += insn_fetch(s8, 1, c->eip);
821 break;
822 case 2:
823 c->modrm_ea += insn_fetch(u16, 2, c->eip);
824 break;
825 }
826 switch (c->modrm_rm) {
827 case 0:
828 c->modrm_ea += bx + si;
829 break;
830 case 1:
831 c->modrm_ea += bx + di;
832 break;
833 case 2:
834 c->modrm_ea += bp + si;
835 break;
836 case 3:
837 c->modrm_ea += bp + di;
838 break;
839 case 4:
840 c->modrm_ea += si;
841 break;
842 case 5:
843 c->modrm_ea += di;
844 break;
845 case 6:
846 if (c->modrm_mod != 0)
847 c->modrm_ea += bp;
848 break;
849 case 7:
850 c->modrm_ea += bx;
851 break;
852 }
853 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
854 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 855 if (!c->has_seg_override)
856 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 857 c->modrm_ea = (u16)c->modrm_ea;
858 } else {
859 /* 32/64-bit ModR/M decode. */
84411d85 860 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 861 sib = insn_fetch(u8, 1, c->eip);
862 index_reg |= (sib >> 3) & 7;
863 base_reg |= sib & 7;
864 scale = sib >> 6;
865
dc71d0f1
AK		 866 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
867 c->modrm_ea += insn_fetch(s32, 4, c->eip);
868 else
1c73ef66 869 c->modrm_ea += c->regs[base_reg];
dc71d0f1 870 if (index_reg != 4)
1c73ef66 871 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 872 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
873 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 874 c->rip_relative = 1;
84411d85 875 } else
1c73ef66 876 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 877 switch (c->modrm_mod) {
878 case 0:
879 if (c->modrm_rm == 5)
880 c->modrm_ea += insn_fetch(s32, 4, c->eip);
881 break;
882 case 1:
883 c->modrm_ea += insn_fetch(s8, 1, c->eip);
884 break;
885 case 2:
886 c->modrm_ea += insn_fetch(s32, 4, c->eip);
887 break;
888 }
889 }
1c73ef66
AK		 890done:
891 return rc;
892}
893
894static int decode_abs(struct x86_emulate_ctxt *ctxt,
895 struct x86_emulate_ops *ops)
896{
897 struct decode_cache *c = &ctxt->decode;
898 int rc = 0;
899
900 switch (c->ad_bytes) {
901 case 2:
902 c->modrm_ea = insn_fetch(u16, 2, c->eip);
903 break;
904 case 4:
905 c->modrm_ea = insn_fetch(u32, 4, c->eip);
906 break;
907 case 8:
908 c->modrm_ea = insn_fetch(u64, 8, c->eip);
909 break;
910 }
911done:
912 return rc;
913}
914
6aa8b732 915int
8b4caf66 916x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 917{
e4e03ded 918 struct decode_cache *c = &ctxt->decode;
6aa8b732 919 int rc = 0;
6aa8b732 920 int mode = ctxt->mode;
e09d082c 921 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 922
923 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 924
e4e03ded 925 memset(c, 0, sizeof(struct decode_cache));
eb3c79e6 926 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
7a5b56df 927 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 928 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 929
930 switch (mode) {
931 case X86EMUL_MODE_REAL:
a0044755 932 case X86EMUL_MODE_VM86:
6aa8b732 933 case X86EMUL_MODE_PROT16:
f21b8bf4 934 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 935 break;
936 case X86EMUL_MODE_PROT32:
f21b8bf4 937 def_op_bytes = def_ad_bytes = 4;
6aa8b732 938 break;
05b3e0c2 939#ifdef CONFIG_X86_64
6aa8b732 940 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 941 def_op_bytes = 4;
942 def_ad_bytes = 8;
6aa8b732
AK		 943 break;
944#endif
945 default:
946 return -1;
947 }
948
f21b8bf4
AK		 949 c->op_bytes = def_op_bytes;
950 c->ad_bytes = def_ad_bytes;
951
6aa8b732 952 /* Legacy prefixes. */
b4c6abfe 953 for (;;) {
e4e03ded 954 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 955 case 0x66: /* operand-size override */
f21b8bf4
AK		 956 /* switch between 2/4 bytes */
957 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 958 break;
959 case 0x67: /* address-size override */
960 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 961 /* switch between 4/8 bytes */
f21b8bf4 962 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 963 else
e4e03ded 964 /* switch between 2/4 bytes */
f21b8bf4 965 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 966 break;
7a5b56df 967 case 0x26: /* ES override */
6aa8b732 968 case 0x2e: /* CS override */
7a5b56df 969 case 0x36: /* SS override */
6aa8b732 970 case 0x3e: /* DS override */
7a5b56df 971 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 972 break;
973 case 0x64: /* FS override */
6aa8b732 974 case 0x65: /* GS override */
7a5b56df 975 set_seg_override(c, c->b & 7);
6aa8b732 976 break;
b4c6abfe
LV		 977 case 0x40 ... 0x4f: /* REX */
978 if (mode != X86EMUL_MODE_PROT64)
979 goto done_prefixes;
33615aa9 980 c->rex_prefix = c->b;
b4c6abfe 981 continue;
6aa8b732 982 case 0xf0: /* LOCK */
e4e03ded 983 c->lock_prefix = 1;
6aa8b732 984 break;
ae6200ba 985 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 986 c->rep_prefix = REPNE_PREFIX;
987 break;
6aa8b732 988 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 989 c->rep_prefix = REPE_PREFIX;
6aa8b732 990 break;
6aa8b732
AK		 991 default:
992 goto done_prefixes;
993 }
b4c6abfe
LV		 994
995 /* Any legacy prefix after a REX prefix nullifies its effect. */
996
33615aa9 997 c->rex_prefix = 0;
6aa8b732
AK		 998 }
999
1000done_prefixes:
1001
1002 /* REX prefix. */
1c73ef66 1003 if (c->rex_prefix)
33615aa9 1004 if (c->rex_prefix & 8)
e4e03ded 1005 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1006
1007 /* Opcode byte(s). */
e4e03ded
LV		 1008 c->d = opcode_table[c->b];
1009 if (c->d == 0) {
6aa8b732 1010 /* Two-byte opcode? */
e4e03ded
LV		 1011 if (c->b == 0x0f) {
1012 c->twobyte = 1;
1013 c->b = insn_fetch(u8, 1, c->eip);
1014 c->d = twobyte_table[c->b];
6aa8b732 1015 }
e09d082c 1016 }
6aa8b732 1017
e09d082c
AK		 1018 if (c->d & Group) {
1019 group = c->d & GroupMask;
1020 c->modrm = insn_fetch(u8, 1, c->eip);
1021 --c->eip;
1022
1023 group = (group << 3) + ((c->modrm >> 3) & 7);
1024 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1025 c->d = group2_table[group];
1026 else
1027 c->d = group_table[group];
1028 }
1029
1030 /* Unrecognised? */
1031 if (c->d == 0) {
1032 DPRINTF("Cannot emulate %02x\n", c->b);
1033 return -1;
6aa8b732
AK		 1034 }
1035
6e3d5dfb
AK		 1036 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1037 c->op_bytes = 8;
1038
6aa8b732 1039 /* ModRM and SIB bytes. */
1c73ef66
AK		 1040 if (c->d & ModRM)
1041 rc = decode_modrm(ctxt, ops);
1042 else if (c->d & MemAbs)
1043 rc = decode_abs(ctxt, ops);
1044 if (rc)
1045 goto done;
6aa8b732 1046
7a5b56df
AK		 1047 if (!c->has_seg_override)
1048 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1049
7a5b56df
AK		 1050 if (!(!c->twobyte && c->b == 0x8d))
1051 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1052
1053 if (c->ad_bytes != 8)
1054 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1055 /*
1056 * Decode and fetch the source operand: register, memory
1057 * or immediate.
1058 */
e4e03ded 1059 switch (c->d & SrcMask) {
6aa8b732
AK		 1060 case SrcNone:
1061 break;
1062 case SrcReg:
9f1ef3f8 1063 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1064 break;
1065 case SrcMem16:
e4e03ded 1066 c->src.bytes = 2;
6aa8b732
AK		 1067 goto srcmem_common;
1068 case SrcMem32:
e4e03ded 1069 c->src.bytes = 4;
6aa8b732
AK		 1070 goto srcmem_common;
1071 case SrcMem:
e4e03ded
LV		 1072 c->src.bytes = (c->d & ByteOp) ? 1 :
1073 c->op_bytes;
b85b9ee9 1074 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1075 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1076 break;
d77c26fc 1077 srcmem_common:
4e62417b
AJ		 1078 /*
1079 * For instructions with a ModR/M byte, switch to register
1080 * access if Mod = 3.
1081 */
e4e03ded
LV		 1082 if ((c->d & ModRM) && c->modrm_mod == 3) {
1083 c->src.type = OP_REG;
66b85505 1084 c->src.val = c->modrm_val;
107d6d2e 1085 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1086 break;
1087 }
e4e03ded 1088 c->src.type = OP_MEM;
6aa8b732
AK		 1089 break;
1090 case SrcImm:
c9eaf20f 1091 case SrcImmU:
e4e03ded
LV		 1092 c->src.type = OP_IMM;
1093 c->src.ptr = (unsigned long *)c->eip;
1094 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1095 if (c->src.bytes == 8)
1096 c->src.bytes = 4;
6aa8b732 1097 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1098 switch (c->src.bytes) {
6aa8b732 1099 case 1:
e4e03ded 1100 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1101 break;
1102 case 2:
e4e03ded 1103 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1104 break;
1105 case 4:
e4e03ded 1106 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1107 break;
1108 }
c9eaf20f
AK		 1109 if ((c->d & SrcMask) == SrcImmU) {
1110 switch (c->src.bytes) {
1111 case 1:
1112 c->src.val &= 0xff;
1113 break;
1114 case 2:
1115 c->src.val &= 0xffff;
1116 break;
1117 case 4:
1118 c->src.val &= 0xffffffff;
1119 break;
1120 }
1121 }
6aa8b732
AK		 1122 break;
1123 case SrcImmByte:
341de7e3 1124 case SrcImmUByte:
e4e03ded
LV		 1125 c->src.type = OP_IMM;
1126 c->src.ptr = (unsigned long *)c->eip;
1127 c->src.bytes = 1;
341de7e3
GN		 1128 if ((c->d & SrcMask) == SrcImmByte)
1129 c->src.val = insn_fetch(s8, 1, c->eip);
1130 else
1131 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1132 break;
bfcadf83
GT		 1133 case SrcOne:
1134 c->src.bytes = 1;
1135 c->src.val = 1;
1136 break;
6aa8b732
AK		 1137 }
1138
0dc8d10f
GT		 1139 /*
1140 * Decode and fetch the second source operand: register, memory
1141 * or immediate.
1142 */
1143 switch (c->d & Src2Mask) {
1144 case Src2None:
1145 break;
1146 case Src2CL:
1147 c->src2.bytes = 1;
1148 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1149 break;
1150 case Src2ImmByte:
1151 c->src2.type = OP_IMM;
1152 c->src2.ptr = (unsigned long *)c->eip;
1153 c->src2.bytes = 1;
1154 c->src2.val = insn_fetch(u8, 1, c->eip);
1155 break;
a5f868bd
GN		 1156 case Src2Imm16:
1157 c->src2.type = OP_IMM;
1158 c->src2.ptr = (unsigned long *)c->eip;
1159 c->src2.bytes = 2;
1160 c->src2.val = insn_fetch(u16, 2, c->eip);
1161 break;
0dc8d10f
GT		 1162 case Src2One:
1163 c->src2.bytes = 1;
1164 c->src2.val = 1;
1165 break;
1166 }
1167
038e51de 1168 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1169 switch (c->d & DstMask) {
038e51de
AK		 1170 case ImplicitOps:
1171 /* Special instructions do their own operand decoding. */
8b4caf66 1172 return 0;
038e51de 1173 case DstReg:
9f1ef3f8 1174 decode_register_operand(&c->dst, c,
3c118e24 1175 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1176 break;
1177 case DstMem:
e4e03ded 1178 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1179 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1180 c->dst.type = OP_REG;
66b85505 1181 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1182 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1183 break;
1184 }
8b4caf66
LV		 1185 c->dst.type = OP_MEM;
1186 break;
9c9fddd0
GT		 1187 case DstAcc:
1188 c->dst.type = OP_REG;
1189 c->dst.bytes = c->op_bytes;
1190 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1191 switch (c->op_bytes) {
1192 case 1:
1193 c->dst.val = *(u8 *)c->dst.ptr;
1194 break;
1195 case 2:
1196 c->dst.val = *(u16 *)c->dst.ptr;
1197 break;
1198 case 4:
1199 c->dst.val = *(u32 *)c->dst.ptr;
1200 break;
1201 }
1202 c->dst.orig_val = c->dst.val;
1203 break;
8b4caf66
LV		 1204 }
1205
f5b4edcd
AK		 1206 if (c->rip_relative)
1207 c->modrm_ea += c->eip;
1208
8b4caf66
LV		 1209done:
1210 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1211}
1212
8cdbd2c9
LV		 1213static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1214{
1215 struct decode_cache *c = &ctxt->decode;
1216
1217 c->dst.type = OP_MEM;
1218 c->dst.bytes = c->op_bytes;
1219 c->dst.val = c->src.val;
7a957275 1220 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1221 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1222 c->regs[VCPU_REGS_RSP]);
1223}
1224
faa5a3ae 1225static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1226 struct x86_emulate_ops *ops,
1227 void *dest, int len)
8cdbd2c9
LV		 1228{
1229 struct decode_cache *c = &ctxt->decode;
1230 int rc;
1231
781d0edc
AK		 1232 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1233 c->regs[VCPU_REGS_RSP]),
350f69dc 1234 dest, len, ctxt->vcpu);
b60d513c 1235 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1236 return rc;
1237
350f69dc 1238 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1239 return rc;
1240}
8cdbd2c9 1241
d4c6a154
GN		 1242static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1243 struct x86_emulate_ops *ops,
1244 void *dest, int len)
1245{
1246 int rc;
1247 unsigned long val, change_mask;
1248 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1249 int cpl = kvm_x86_ops->get_cpl(ctxt->vcpu);
1250
1251 rc = emulate_pop(ctxt, ops, &val, len);
1252 if (rc != X86EMUL_CONTINUE)
1253 return rc;
1254
1255 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1256 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1257
1258 switch(ctxt->mode) {
1259 case X86EMUL_MODE_PROT64:
1260 case X86EMUL_MODE_PROT32:
1261 case X86EMUL_MODE_PROT16:
1262 if (cpl == 0)
1263 change_mask |= EFLG_IOPL;
1264 if (cpl <= iopl)
1265 change_mask |= EFLG_IF;
1266 break;
1267 case X86EMUL_MODE_VM86:
1268 if (iopl < 3) {
1269 kvm_inject_gp(ctxt->vcpu, 0);
1270 return X86EMUL_PROPAGATE_FAULT;
1271 }
1272 change_mask |= EFLG_IF;
1273 break;
1274 default: /* real mode */
1275 change_mask |= (EFLG_IOPL | EFLG_IF);
1276 break;
1277 }
1278
1279 *(unsigned long *)dest =
1280 (ctxt->eflags & ~change_mask) | (val & change_mask);
1281
1282 return rc;
1283}
1284
0934ac9d
MG		 1285static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1286{
1287 struct decode_cache *c = &ctxt->decode;
1288 struct kvm_segment segment;
1289
1290 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1291
1292 c->src.val = segment.selector;
1293 emulate_push(ctxt);
1294}
1295
1296static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1297 struct x86_emulate_ops *ops, int seg)
1298{
1299 struct decode_cache *c = &ctxt->decode;
1300 unsigned long selector;
1301 int rc;
1302
1303 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1304 if (rc != 0)
1305 return rc;
1306
c697518a 1307 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, seg);
0934ac9d
MG		 1308 return rc;
1309}
1310
abcf14b5
MG		 1311static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1312{
1313 struct decode_cache *c = &ctxt->decode;
1314 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1315 int reg = VCPU_REGS_RAX;
1316
1317 while (reg <= VCPU_REGS_RDI) {
1318 (reg == VCPU_REGS_RSP) ?
1319 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1320
1321 emulate_push(ctxt);
1322 ++reg;
1323 }
1324}
1325
1326static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1327 struct x86_emulate_ops *ops)
1328{
1329 struct decode_cache *c = &ctxt->decode;
1330 int rc = 0;
1331 int reg = VCPU_REGS_RDI;
1332
1333 while (reg >= VCPU_REGS_RAX) {
1334 if (reg == VCPU_REGS_RSP) {
1335 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1336 c->op_bytes);
1337 --reg;
1338 }
1339
1340 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1341 if (rc != 0)
1342 break;
1343 --reg;
1344 }
1345 return rc;
1346}
1347
faa5a3ae
AK		 1348static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1349 struct x86_emulate_ops *ops)
1350{
1351 struct decode_cache *c = &ctxt->decode;
1352 int rc;
1353
350f69dc 1354 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1355 if (rc != 0)
1356 return rc;
8cdbd2c9
LV		 1357 return 0;
1358}
1359
05f086f8 1360static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1361{
05f086f8 1362 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1363 switch (c->modrm_reg) {
1364 case 0: /* rol */
05f086f8 1365 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1366 break;
1367 case 1: /* ror */
05f086f8 1368 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1369 break;
1370 case 2: /* rcl */
05f086f8 1371 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1372 break;
1373 case 3: /* rcr */
05f086f8 1374 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1375 break;
1376 case 4: /* sal/shl */
1377 case 6: /* sal/shl */
05f086f8 1378 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1379 break;
1380 case 5: /* shr */
05f086f8 1381 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1382 break;
1383 case 7: /* sar */
05f086f8 1384 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1385 break;
1386 }
1387}
1388
1389static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1390 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1391{
1392 struct decode_cache *c = &ctxt->decode;
1393 int rc = 0;
1394
1395 switch (c->modrm_reg) {
1396 case 0 ... 1: /* test */
05f086f8 1397 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1398 break;
1399 case 2: /* not */
1400 c->dst.val = ~c->dst.val;
1401 break;
1402 case 3: /* neg */
05f086f8 1403 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1404 break;
1405 default:
1406 DPRINTF("Cannot emulate %02x\n", c->b);
1407 rc = X86EMUL_UNHANDLEABLE;
1408 break;
1409 }
8cdbd2c9
LV		 1410 return rc;
1411}
1412
1413static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1414 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1415{
1416 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1417
1418 switch (c->modrm_reg) {
1419 case 0: /* inc */
05f086f8 1420 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1421 break;
1422 case 1: /* dec */
05f086f8 1423 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1424 break;
d19292e4
MG		 1425 case 2: /* call near abs */ {
1426 long int old_eip;
1427 old_eip = c->eip;
1428 c->eip = c->src.val;
1429 c->src.val = old_eip;
1430 emulate_push(ctxt);
1431 break;
1432 }
8cdbd2c9 1433 case 4: /* jmp abs */
fd60754e 1434 c->eip = c->src.val;
8cdbd2c9
LV		 1435 break;
1436 case 6: /* push */
fd60754e 1437 emulate_push(ctxt);
8cdbd2c9 1438 break;
8cdbd2c9
LV		 1439 }
1440 return 0;
1441}
1442
1443static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1444 struct x86_emulate_ops *ops,
e8d8d7fe 1445 unsigned long memop)
8cdbd2c9
LV		 1446{
1447 struct decode_cache *c = &ctxt->decode;
1448 u64 old, new;
1449 int rc;
1450
e8d8d7fe 1451 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1452 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1453 return rc;
1454
1455 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1456 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1457
1458 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1459 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1460 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1461
1462 } else {
1463 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1464 (u32) c->regs[VCPU_REGS_RBX];
1465
e8d8d7fe 1466 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1467 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1468 return rc;
05f086f8 1469 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1470 }
1471 return 0;
1472}
1473
a77ab5ea
AK		 1474static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1475 struct x86_emulate_ops *ops)
1476{
1477 struct decode_cache *c = &ctxt->decode;
1478 int rc;
1479 unsigned long cs;
1480
1481 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1482 if (rc)
1483 return rc;
1484 if (c->op_bytes == 4)
1485 c->eip = (u32)c->eip;
1486 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1487 if (rc)
1488 return rc;
c697518a 1489 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1490 return rc;
1491}
1492
8cdbd2c9
LV		 1493static inline int writeback(struct x86_emulate_ctxt *ctxt,
1494 struct x86_emulate_ops *ops)
1495{
1496 int rc;
1497 struct decode_cache *c = &ctxt->decode;
1498
1499 switch (c->dst.type) {
1500 case OP_REG:
1501 /* The 4-byte case *is* correct:
1502 * in 64-bit mode we zero-extend.
1503 */
1504 switch (c->dst.bytes) {
1505 case 1:
1506 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1507 break;
1508 case 2:
1509 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1510 break;
1511 case 4:
1512 *c->dst.ptr = (u32)c->dst.val;
1513 break; /* 64b: zero-ext */
1514 case 8:
1515 *c->dst.ptr = c->dst.val;
1516 break;
1517 }
1518 break;
1519 case OP_MEM:
1520 if (c->lock_prefix)
1521 rc = ops->cmpxchg_emulated(
1522 (unsigned long)c->dst.ptr,
1523 &c->dst.orig_val,
1524 &c->dst.val,
1525 c->dst.bytes,
1526 ctxt->vcpu);
1527 else
1528 rc = ops->write_emulated(
1529 (unsigned long)c->dst.ptr,
1530 &c->dst.val,
1531 c->dst.bytes,
1532 ctxt->vcpu);
b60d513c 1533 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1534 return rc;
a01af5ec
LV		 1535 break;
1536 case OP_NONE:
1537 /* no writeback */
1538 break;
8cdbd2c9
LV		 1539 default:
1540 break;
1541 }
1542 return 0;
1543}
1544
a3f9d398 1545static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1546{
1547 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1548 /*
1549 * an sti; sti; sequence only disable interrupts for the first
1550 * instruction. So, if the last instruction, be it emulated or
1551 * not, left the system with the INT_STI flag enabled, it
1552 * means that the last instruction is an sti. We should not
1553 * leave the flag on in this case. The same goes for mov ss
1554 */
1555 if (!(int_shadow & mask))
1556 ctxt->interruptibility = mask;
1557}
1558
e66bb2cc
AP		 1559static inline void
1560setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1561 struct kvm_segment *cs, struct kvm_segment *ss)
1562{
1563 memset(cs, 0, sizeof(struct kvm_segment));
1564 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1565 memset(ss, 0, sizeof(struct kvm_segment));
1566
1567 cs->l = 0; /* will be adjusted later */
1568 cs->base = 0; /* flat segment */
1569 cs->g = 1; /* 4kb granularity */
1570 cs->limit = 0xffffffff; /* 4GB limit */
1571 cs->type = 0x0b; /* Read, Execute, Accessed */
1572 cs->s = 1;
1573 cs->dpl = 0; /* will be adjusted later */
1574 cs->present = 1;
1575 cs->db = 1;
1576
1577 ss->unusable = 0;
1578 ss->base = 0; /* flat segment */
1579 ss->limit = 0xffffffff; /* 4GB limit */
1580 ss->g = 1; /* 4kb granularity */
1581 ss->s = 1;
1582 ss->type = 0x03; /* Read/Write, Accessed */
1583 ss->db = 1; /* 32bit stack segment */
1584 ss->dpl = 0;
1585 ss->present = 1;
1586}
1587
1588static int
1589emulate_syscall(struct x86_emulate_ctxt *ctxt)
1590{
1591 struct decode_cache *c = &ctxt->decode;
1592 struct kvm_segment cs, ss;
1593 u64 msr_data;
1594
1595 /* syscall is not available in real mode */
d380a5e4 1596 if (ctxt->mode == X86EMUL_MODE_REAL || ctxt->mode == X86EMUL_MODE_VM86)
e54cfa97 1597 return X86EMUL_UNHANDLEABLE;
e66bb2cc
AP		 1598
1599 setup_syscalls_segments(ctxt, &cs, &ss);
1600
1601 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1602 msr_data >>= 32;
1603 cs.selector = (u16)(msr_data & 0xfffc);
1604 ss.selector = (u16)(msr_data + 8);
1605
1606 if (is_long_mode(ctxt->vcpu)) {
1607 cs.db = 0;
1608 cs.l = 1;
1609 }
1610 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1611 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1612
1613 c->regs[VCPU_REGS_RCX] = c->eip;
1614 if (is_long_mode(ctxt->vcpu)) {
1615#ifdef CONFIG_X86_64
1616 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1617
1618 kvm_x86_ops->get_msr(ctxt->vcpu,
1619 ctxt->mode == X86EMUL_MODE_PROT64 ?
1620 MSR_LSTAR : MSR_CSTAR, &msr_data);
1621 c->eip = msr_data;
1622
1623 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1624 ctxt->eflags &= ~(msr_data | EFLG_RF);
1625#endif
1626 } else {
1627 /* legacy mode */
1628 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1629 c->eip = (u32)msr_data;
1630
1631 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1632 }
1633
e54cfa97 1634 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1635}
1636
8c604352
AP		 1637static int
1638emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1639{
1640 struct decode_cache *c = &ctxt->decode;
1641 struct kvm_segment cs, ss;
1642 u64 msr_data;
1643
a0044755
GN		 1644 /* inject #GP if in real mode */
1645 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352 1646 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1647 return X86EMUL_UNHANDLEABLE;
8c604352
AP		 1648 }
1649
1650 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1651 * Therefore, we inject an #UD.
1652 */
1653 if (ctxt->mode == X86EMUL_MODE_PROT64)
e54cfa97 1654 return X86EMUL_UNHANDLEABLE;
8c604352
AP		 1655
1656 setup_syscalls_segments(ctxt, &cs, &ss);
1657
1658 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1659 switch (ctxt->mode) {
1660 case X86EMUL_MODE_PROT32:
1661 if ((msr_data & 0xfffc) == 0x0) {
1662 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1663 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1664 }
1665 break;
1666 case X86EMUL_MODE_PROT64:
1667 if (msr_data == 0x0) {
1668 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1669 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1670 }
1671 break;
1672 }
1673
1674 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1675 cs.selector = (u16)msr_data;
1676 cs.selector &= ~SELECTOR_RPL_MASK;
1677 ss.selector = cs.selector + 8;
1678 ss.selector &= ~SELECTOR_RPL_MASK;
1679 if (ctxt->mode == X86EMUL_MODE_PROT64
1680 || is_long_mode(ctxt->vcpu)) {
1681 cs.db = 0;
1682 cs.l = 1;
1683 }
1684
1685 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1686 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1687
1688 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1689 c->eip = msr_data;
1690
1691 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1692 c->regs[VCPU_REGS_RSP] = msr_data;
1693
e54cfa97 1694 return X86EMUL_CONTINUE;
8c604352
AP		 1695}
1696
4668f050
AP		 1697static int
1698emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1699{
1700 struct decode_cache *c = &ctxt->decode;
1701 struct kvm_segment cs, ss;
1702 u64 msr_data;
1703 int usermode;
1704
a0044755
GN		 1705 /* inject #GP if in real mode or Virtual 8086 mode */
1706 if (ctxt->mode == X86EMUL_MODE_REAL ||
1707 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050 1708 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1709 return X86EMUL_UNHANDLEABLE;
4668f050
AP		 1710 }
1711
4668f050
AP		 1712 setup_syscalls_segments(ctxt, &cs, &ss);
1713
1714 if ((c->rex_prefix & 0x8) != 0x0)
1715 usermode = X86EMUL_MODE_PROT64;
1716 else
1717 usermode = X86EMUL_MODE_PROT32;
1718
1719 cs.dpl = 3;
1720 ss.dpl = 3;
1721 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1722 switch (usermode) {
1723 case X86EMUL_MODE_PROT32:
1724 cs.selector = (u16)(msr_data + 16);
1725 if ((msr_data & 0xfffc) == 0x0) {
1726 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1727 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1728 }
1729 ss.selector = (u16)(msr_data + 24);
1730 break;
1731 case X86EMUL_MODE_PROT64:
1732 cs.selector = (u16)(msr_data + 32);
1733 if (msr_data == 0x0) {
1734 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1735 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1736 }
1737 ss.selector = cs.selector + 8;
1738 cs.db = 0;
1739 cs.l = 1;
1740 break;
1741 }
1742 cs.selector |= SELECTOR_RPL_MASK;
1743 ss.selector |= SELECTOR_RPL_MASK;
1744
1745 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1746 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1747
1748 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1749 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1750
e54cfa97 1751 return X86EMUL_CONTINUE;
4668f050
AP		 1752}
1753
f850e2e6
GN		 1754static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
1755{
1756 int iopl;
1757 if (ctxt->mode == X86EMUL_MODE_REAL)
1758 return false;
1759 if (ctxt->mode == X86EMUL_MODE_VM86)
1760 return true;
1761 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1762 return kvm_x86_ops->get_cpl(ctxt->vcpu) > iopl;
1763}
1764
1765static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1766 struct x86_emulate_ops *ops,
1767 u16 port, u16 len)
1768{
1769 struct kvm_segment tr_seg;
1770 int r;
1771 u16 io_bitmap_ptr;
1772 u8 perm, bit_idx = port & 0x7;
1773 unsigned mask = (1 << len) - 1;
1774
1775 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
1776 if (tr_seg.unusable)
1777 return false;
1778 if (tr_seg.limit < 103)
1779 return false;
1780 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
1781 NULL);
1782 if (r != X86EMUL_CONTINUE)
1783 return false;
1784 if (io_bitmap_ptr + port/8 > tr_seg.limit)
1785 return false;
1786 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
1787 ctxt->vcpu, NULL);
1788 if (r != X86EMUL_CONTINUE)
1789 return false;
1790 if ((perm >> bit_idx) & mask)
1791 return false;
1792 return true;
1793}
1794
1795static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1796 struct x86_emulate_ops *ops,
1797 u16 port, u16 len)
1798{
1799 if (emulator_bad_iopl(ctxt))
1800 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1801 return false;
1802 return true;
1803}
1804
8b4caf66 1805int
1be3aa47 1806x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1807{
e8d8d7fe 1808 unsigned long memop = 0;
8b4caf66 1809 u64 msr_data;
3427318f 1810 unsigned long saved_eip = 0;
8b4caf66 1811 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1812 unsigned int port;
1813 int io_dir_in;
1be3aa47 1814 int rc = 0;
8b4caf66 1815
310b5d30
GC		 1816 ctxt->interruptibility = 0;
1817
3427318f
LV		 1818 /* Shadow copy of register state. Committed on successful emulation.
1819 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1820 * modify them.
1821 */
1822
ad312c7c 1823 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1824 saved_eip = c->eip;
1825
1161624f
GN		 1826 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
1827 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1828 goto done;
1829 }
1830
d380a5e4
GN		 1831 /* LOCK prefix is allowed only with some instructions */
1832 if (c->lock_prefix && !(c->d & Lock)) {
1833 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1834 goto done;
1835 }
1836
e92805ac
GN		 1837 /* Privileged instruction can be executed only in CPL=0 */
1838 if ((c->d & Priv) && kvm_x86_ops->get_cpl(ctxt->vcpu)) {
1839 kvm_inject_gp(ctxt->vcpu, 0);
1840 goto done;
1841 }
1842
c7e75a3d 1843 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1844 memop = c->modrm_ea;
8b4caf66 1845
b9fa9d6b
AK		 1846 if (c->rep_prefix && (c->d & String)) {
1847 /* All REP prefixes have the same first termination condition */
1848 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1849 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1850 goto done;
1851 }
1852 /* The second termination condition only applies for REPE
1853 * and REPNE. Test if the repeat string operation prefix is
1854 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1855 * corresponding termination condition according to:
1856 * - if REPE/REPZ and ZF = 0 then done
1857 * - if REPNE/REPNZ and ZF = 1 then done
1858 */
1859 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1860 (c->b == 0xae) || (c->b == 0xaf)) {
1861 if ((c->rep_prefix == REPE_PREFIX) &&
1862 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1863 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1864 goto done;
1865 }
1866 if ((c->rep_prefix == REPNE_PREFIX) &&
1867 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1868 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1869 goto done;
1870 }
1871 }
1872 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1873 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1874 }
1875
8b4caf66 1876 if (c->src.type == OP_MEM) {
e8d8d7fe 1877 c->src.ptr = (unsigned long *)memop;
8b4caf66 1878 c->src.val = 0;
d77c26fc
MD		 1879 rc = ops->read_emulated((unsigned long)c->src.ptr,
1880 &c->src.val,
1881 c->src.bytes,
1882 ctxt->vcpu);
b60d513c 1883 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 1884 goto done;
1885 c->src.orig_val = c->src.val;
1886 }
1887
1888 if ((c->d & DstMask) == ImplicitOps)
1889 goto special_insn;
1890
1891
1892 if (c->dst.type == OP_MEM) {
e8d8d7fe 1893 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1894 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1895 c->dst.val = 0;
e4e03ded
LV		 1896 if (c->d & BitOp) {
1897 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1898
e4e03ded
LV		 1899 c->dst.ptr = (void *)c->dst.ptr +
1900 (c->src.val & mask) / 8;
038e51de 1901 }
b60d513c
TY		 1902 if (!(c->d & Mov)) {
1903 /* optimisation - avoid slow emulated read */
1904 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1905 &c->dst.val,
1906 c->dst.bytes,
1907 ctxt->vcpu);
1908 if (rc != X86EMUL_CONTINUE)
1909 goto done;
1910 }
038e51de 1911 }
e4e03ded 1912 c->dst.orig_val = c->dst.val;
038e51de 1913
018a98db
AK		 1914special_insn:
1915
e4e03ded 1916 if (c->twobyte)
6aa8b732
AK		 1917 goto twobyte_insn;
1918
e4e03ded 1919 switch (c->b) {
6aa8b732
AK		 1920 case 0x00 ... 0x05:
1921 add: /* add */
05f086f8 1922 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1923 break;
0934ac9d 1924 case 0x06: /* push es */
0934ac9d
MG		 1925 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1926 break;
1927 case 0x07: /* pop es */
0934ac9d
MG		 1928 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1929 if (rc != 0)
1930 goto done;
1931 break;
6aa8b732
AK		 1932 case 0x08 ... 0x0d:
1933 or: /* or */
05f086f8 1934 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1935 break;
0934ac9d 1936 case 0x0e: /* push cs */
0934ac9d
MG		 1937 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1938 break;
6aa8b732
AK		 1939 case 0x10 ... 0x15:
1940 adc: /* adc */
05f086f8 1941 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1942 break;
0934ac9d 1943 case 0x16: /* push ss */
0934ac9d
MG		 1944 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1945 break;
1946 case 0x17: /* pop ss */
0934ac9d
MG		 1947 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1948 if (rc != 0)
1949 goto done;
1950 break;
6aa8b732
AK		 1951 case 0x18 ... 0x1d:
1952 sbb: /* sbb */
05f086f8 1953 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1954 break;
0934ac9d 1955 case 0x1e: /* push ds */
0934ac9d
MG		 1956 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1957 break;
1958 case 0x1f: /* pop ds */
0934ac9d
MG		 1959 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1960 if (rc != 0)
1961 goto done;
1962 break;
aa3a816b 1963 case 0x20 ... 0x25:
6aa8b732 1964 and: /* and */
05f086f8 1965 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1966 break;
1967 case 0x28 ... 0x2d:
1968 sub: /* sub */
05f086f8 1969 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1970 break;
1971 case 0x30 ... 0x35:
1972 xor: /* xor */
05f086f8 1973 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1974 break;
1975 case 0x38 ... 0x3d:
1976 cmp: /* cmp */
05f086f8 1977 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1978 break;
33615aa9
AK		 1979 case 0x40 ... 0x47: /* inc r16/r32 */
1980 emulate_1op("inc", c->dst, ctxt->eflags);
1981 break;
1982 case 0x48 ... 0x4f: /* dec r16/r32 */
1983 emulate_1op("dec", c->dst, ctxt->eflags);
1984 break;
1985 case 0x50 ... 0x57: /* push reg */
2786b014 1986 emulate_push(ctxt);
33615aa9
AK		 1987 break;
1988 case 0x58 ... 0x5f: /* pop reg */
1989 pop_instruction:
350f69dc 1990 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1991 if (rc != 0)
33615aa9 1992 goto done;
33615aa9 1993 break;
abcf14b5
MG		 1994 case 0x60: /* pusha */
1995 emulate_pusha(ctxt);
1996 break;
1997 case 0x61: /* popa */
1998 rc = emulate_popa(ctxt, ops);
1999 if (rc != 0)
2000 goto done;
2001 break;
6aa8b732 2002 case 0x63: /* movsxd */
8b4caf66 2003 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2004 goto cannot_emulate;
e4e03ded 2005 c->dst.val = (s32) c->src.val;
6aa8b732 2006 break;
91ed7a0e 2007 case 0x68: /* push imm */
018a98db 2008 case 0x6a: /* push imm8 */
018a98db
AK		 2009 emulate_push(ctxt);
2010 break;
2011 case 0x6c: /* insb */
2012 case 0x6d: /* insw/insd */
f850e2e6
GN		 2013 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2014 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2015 kvm_inject_gp(ctxt->vcpu, 0);
2016 goto done;
2017 }
2018 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2019 1,
2020 (c->d & ByteOp) ? 1 : c->op_bytes,
2021 c->rep_prefix ?
e4706772 2022 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2023 (ctxt->eflags & EFLG_DF),
7a5b56df 2024 register_address(c, es_base(ctxt),
018a98db
AK		 2025 c->regs[VCPU_REGS_RDI]),
2026 c->rep_prefix,
2027 c->regs[VCPU_REGS_RDX]) == 0) {
2028 c->eip = saved_eip;
2029 return -1;
2030 }
2031 return 0;
2032 case 0x6e: /* outsb */
2033 case 0x6f: /* outsw/outsd */
f850e2e6
GN		 2034 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2035 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2036 kvm_inject_gp(ctxt->vcpu, 0);
2037 goto done;
2038 }
851ba692 2039 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2040 0,
2041 (c->d & ByteOp) ? 1 : c->op_bytes,
2042 c->rep_prefix ?
e4706772 2043 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2044 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 2045 register_address(c,
2046 seg_override_base(ctxt, c),
018a98db
AK		 2047 c->regs[VCPU_REGS_RSI]),
2048 c->rep_prefix,
2049 c->regs[VCPU_REGS_RDX]) == 0) {
2050 c->eip = saved_eip;
2051 return -1;
2052 }
2053 return 0;
b2833e3c 2054 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2055 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2056 jmp_rel(c, c->src.val);
018a98db 2057 break;
6aa8b732 2058 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2059 switch (c->modrm_reg) {
6aa8b732
AK		 2060 case 0:
2061 goto add;
2062 case 1:
2063 goto or;
2064 case 2:
2065 goto adc;
2066 case 3:
2067 goto sbb;
2068 case 4:
2069 goto and;
2070 case 5:
2071 goto sub;
2072 case 6:
2073 goto xor;
2074 case 7:
2075 goto cmp;
2076 }
2077 break;
2078 case 0x84 ... 0x85:
05f086f8 2079 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2080 break;
2081 case 0x86 ... 0x87: /* xchg */
b13354f8 2082 xchg:
6aa8b732 2083 /* Write back the register source. */
e4e03ded 2084 switch (c->dst.bytes) {
6aa8b732 2085 case 1:
e4e03ded 2086 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2087 break;
2088 case 2:
e4e03ded 2089 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2090 break;
2091 case 4:
e4e03ded 2092 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2093 break; /* 64b reg: zero-extend */
2094 case 8:
e4e03ded 2095 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2096 break;
2097 }
2098 /*
2099 * Write back the memory destination with implicit LOCK
2100 * prefix.
2101 */
e4e03ded
LV		 2102 c->dst.val = c->src.val;
2103 c->lock_prefix = 1;
6aa8b732 2104 break;
6aa8b732 2105 case 0x88 ... 0x8b: /* mov */
7de75248 2106 goto mov;
38d5bc6d
GT		 2107 case 0x8c: { /* mov r/m, sreg */
2108 struct kvm_segment segreg;
2109
2110 if (c->modrm_reg <= 5)
2111 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2112 else {
2113 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
2114 c->modrm);
2115 goto cannot_emulate;
2116 }
2117 c->dst.val = segreg.selector;
2118 break;
2119 }
7e0b54b1 2120 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2121 c->dst.val = c->modrm_ea;
7e0b54b1 2122 break;
4257198a
GT		 2123 case 0x8e: { /* mov seg, r/m16 */
2124 uint16_t sel;
4257198a
GT		 2125
2126 sel = c->src.val;
8b9f4414 2127
c697518a
GN		 2128 if (c->modrm_reg == VCPU_SREG_CS ||
2129 c->modrm_reg > VCPU_SREG_GS) {
8b9f4414
GN		 2130 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2131 goto done;
2132 }
2133
310b5d30
GC		 2134 if (c->modrm_reg == VCPU_SREG_SS)
2135 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
2136
c697518a 2137 rc = kvm_load_segment_descriptor(ctxt->vcpu, sel, c->modrm_reg);
4257198a
GT		 2138
2139 c->dst.type = OP_NONE; /* Disable writeback. */
2140 break;
2141 }
6aa8b732 2142 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 2143 rc = emulate_grp1a(ctxt, ops);
2144 if (rc != 0)
6aa8b732 2145 goto done;
6aa8b732 2146 break;
b13354f8
MG		 2147 case 0x90: /* nop / xchg r8,rax */
2148 if (!(c->rex_prefix & 1)) { /* nop */
2149 c->dst.type = OP_NONE;
2150 break;
2151 }
2152 case 0x91 ... 0x97: /* xchg reg,rax */
2153 c->src.type = c->dst.type = OP_REG;
2154 c->src.bytes = c->dst.bytes = c->op_bytes;
2155 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2156 c->src.val = *(c->src.ptr);
2157 goto xchg;
fd2a7608 2158 case 0x9c: /* pushf */
05f086f8 2159 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2160 emulate_push(ctxt);
2161 break;
535eabcf 2162 case 0x9d: /* popf */
2b48cc75 2163 c->dst.type = OP_REG;
05f086f8 2164 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2165 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2166 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2167 if (rc != X86EMUL_CONTINUE)
2168 goto done;
2169 break;
018a98db
AK		 2170 case 0xa0 ... 0xa1: /* mov */
2171 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2172 c->dst.val = c->src.val;
2173 break;
2174 case 0xa2 ... 0xa3: /* mov */
2175 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2176 break;
6aa8b732 2177 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2178 c->dst.type = OP_MEM;
2179 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2180 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2181 es_base(ctxt),
e4e03ded 2182 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2183 rc = ops->read_emulated(register_address(c,
2184 seg_override_base(ctxt, c),
2185 c->regs[VCPU_REGS_RSI]),
e4e03ded 2186 &c->dst.val,
b60d513c
TY		 2187 c->dst.bytes, ctxt->vcpu);
2188 if (rc != X86EMUL_CONTINUE)
6aa8b732 2189 goto done;
7a957275 2190 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2191 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2192 : c->dst.bytes);
7a957275 2193 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2194 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2195 : c->dst.bytes);
6aa8b732
AK		 2196 break;
2197 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2198 c->src.type = OP_NONE; /* Disable writeback. */
2199 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2200 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2201 seg_override_base(ctxt, c),
d7e5117a 2202 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2203 rc = ops->read_emulated((unsigned long)c->src.ptr,
2204 &c->src.val,
2205 c->src.bytes,
2206 ctxt->vcpu);
2207 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2208 goto done;
2209
2210 c->dst.type = OP_NONE; /* Disable writeback. */
2211 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2212 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2213 es_base(ctxt),
d7e5117a 2214 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2215 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2216 &c->dst.val,
2217 c->dst.bytes,
2218 ctxt->vcpu);
2219 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2220 goto done;
2221
2222 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2223
2224 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2225
7a957275 2226 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2227 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2228 : c->src.bytes);
7a957275 2229 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2230 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2231 : c->dst.bytes);
2232
2233 break;
6aa8b732 2234 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2235 c->dst.type = OP_MEM;
2236 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2237 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2238 es_base(ctxt),
a7e6c88a 2239 c->regs[VCPU_REGS_RDI]);
e4e03ded 2240 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2241 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2242 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2243 : c->dst.bytes);
6aa8b732
AK		 2244 break;
2245 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2246 c->dst.type = OP_REG;
2247 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2248 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2249 rc = ops->read_emulated(register_address(c,
2250 seg_override_base(ctxt, c),
2251 c->regs[VCPU_REGS_RSI]),
2252 &c->dst.val,
2253 c->dst.bytes,
2254 ctxt->vcpu);
2255 if (rc != X86EMUL_CONTINUE)
6aa8b732 2256 goto done;
7a957275 2257 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2258 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2259 : c->dst.bytes);
6aa8b732
AK		 2260 break;
2261 case 0xae ... 0xaf: /* scas */
2262 DPRINTF("Urk! I don't handle SCAS.\n");
2263 goto cannot_emulate;
a5e2e82b 2264 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2265 goto mov;
018a98db
AK		 2266 case 0xc0 ... 0xc1:
2267 emulate_grp2(ctxt);
2268 break;
111de5d6 2269 case 0xc3: /* ret */
cf5de4f8 2270 c->dst.type = OP_REG;
111de5d6 2271 c->dst.ptr = &c->eip;
cf5de4f8 2272 c->dst.bytes = c->op_bytes;
111de5d6 2273 goto pop_instruction;
018a98db
AK		 2274 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2275 mov:
2276 c->dst.val = c->src.val;
2277 break;
a77ab5ea
AK		 2278 case 0xcb: /* ret far */
2279 rc = emulate_ret_far(ctxt, ops);
2280 if (rc)
2281 goto done;
2282 break;
018a98db
AK		 2283 case 0xd0 ... 0xd1: /* Grp2 */
2284 c->src.val = 1;
2285 emulate_grp2(ctxt);
2286 break;
2287 case 0xd2 ... 0xd3: /* Grp2 */
2288 c->src.val = c->regs[VCPU_REGS_RCX];
2289 emulate_grp2(ctxt);
2290 break;
a6a3034c
MG		 2291 case 0xe4: /* inb */
2292 case 0xe5: /* in */
84ce66a6 2293 port = c->src.val;
a6a3034c
MG		 2294 io_dir_in = 1;
2295 goto do_io;
2296 case 0xe6: /* outb */
2297 case 0xe7: /* out */
84ce66a6 2298 port = c->src.val;
a6a3034c
MG		 2299 io_dir_in = 0;
2300 goto do_io;
1a52e051 2301 case 0xe8: /* call (near) */ {
d53c4777 2302 long int rel = c->src.val;
e4e03ded 2303 c->src.val = (unsigned long) c->eip;
7a957275 2304 jmp_rel(c, rel);
8cdbd2c9
LV		 2305 emulate_push(ctxt);
2306 break;
1a52e051
NK		 2307 }
2308 case 0xe9: /* jmp rel */
954cd36f 2309 goto jmp;
782b877c 2310 case 0xea: /* jmp far */
c697518a
GN		 2311 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val,
2312 VCPU_SREG_CS))
2313 goto done;
954cd36f 2314
782b877c 2315 c->eip = c->src.val;
954cd36f 2316 break;
954cd36f
GT		 2317 case 0xeb:
2318 jmp: /* jmp rel short */
7a957275 2319 jmp_rel(c, c->src.val);
a01af5ec 2320 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2321 break;
a6a3034c
MG		 2322 case 0xec: /* in al,dx */
2323 case 0xed: /* in (e/r)ax,dx */
2324 port = c->regs[VCPU_REGS_RDX];
2325 io_dir_in = 1;
2326 goto do_io;
2327 case 0xee: /* out al,dx */
2328 case 0xef: /* out (e/r)ax,dx */
2329 port = c->regs[VCPU_REGS_RDX];
2330 io_dir_in = 0;
f850e2e6
GN		 2331 do_io:
2332 if (!emulator_io_permited(ctxt, ops, port,
2333 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2334 kvm_inject_gp(ctxt->vcpu, 0);
2335 goto done;
2336 }
2337 if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2338 (c->d & ByteOp) ? 1 : c->op_bytes,
2339 port) != 0) {
2340 c->eip = saved_eip;
2341 goto cannot_emulate;
2342 }
e93f36bc 2343 break;
111de5d6 2344 case 0xf4: /* hlt */
ad312c7c 2345 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2346 break;
111de5d6
AK		 2347 case 0xf5: /* cmc */
2348 /* complement carry flag from eflags reg */
2349 ctxt->eflags ^= EFLG_CF;
2350 c->dst.type = OP_NONE; /* Disable writeback. */
2351 break;
018a98db
AK		 2352 case 0xf6 ... 0xf7: /* Grp3 */
2353 rc = emulate_grp3(ctxt, ops);
2354 if (rc != 0)
2355 goto done;
2356 break;
111de5d6
AK		 2357 case 0xf8: /* clc */
2358 ctxt->eflags &= ~EFLG_CF;
2359 c->dst.type = OP_NONE; /* Disable writeback. */
2360 break;
2361 case 0xfa: /* cli */
f850e2e6
GN		 2362 if (emulator_bad_iopl(ctxt))
2363 kvm_inject_gp(ctxt->vcpu, 0);
2364 else {
2365 ctxt->eflags &= ~X86_EFLAGS_IF;
2366 c->dst.type = OP_NONE; /* Disable writeback. */
2367 }
111de5d6
AK		 2368 break;
2369 case 0xfb: /* sti */
f850e2e6
GN		 2370 if (emulator_bad_iopl(ctxt))
2371 kvm_inject_gp(ctxt->vcpu, 0);
2372 else {
2373 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
2374 ctxt->eflags |= X86_EFLAGS_IF;
2375 c->dst.type = OP_NONE; /* Disable writeback. */
2376 }
111de5d6 2377 break;
fb4616f4
MG		 2378 case 0xfc: /* cld */
2379 ctxt->eflags &= ~EFLG_DF;
2380 c->dst.type = OP_NONE; /* Disable writeback. */
2381 break;
2382 case 0xfd: /* std */
2383 ctxt->eflags |= EFLG_DF;
2384 c->dst.type = OP_NONE; /* Disable writeback. */
2385 break;
018a98db
AK		 2386 case 0xfe ... 0xff: /* Grp4/Grp5 */
2387 rc = emulate_grp45(ctxt, ops);
2388 if (rc != 0)
2389 goto done;
2390 break;
6aa8b732 2391 }
018a98db
AK		 2392
2393writeback:
2394 rc = writeback(ctxt, ops);
2395 if (rc != 0)
2396 goto done;
2397
2398 /* Commit shadow register state. */
ad312c7c 2399 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2400 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2401
2402done:
2403 if (rc == X86EMUL_UNHANDLEABLE) {
2404 c->eip = saved_eip;
2405 return -1;
2406 }
2407 return 0;
6aa8b732
AK		 2408
2409twobyte_insn:
e4e03ded 2410 switch (c->b) {
6aa8b732 2411 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2412 switch (c->modrm_reg) {
6aa8b732
AK		 2413 u16 size;
2414 unsigned long address;
2415
aca7f966 2416 case 0: /* vmcall */
e4e03ded 2417 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2418 goto cannot_emulate;
2419
7aa81cc0
AL		 2420 rc = kvm_fix_hypercall(ctxt->vcpu);
2421 if (rc)
2422 goto done;
2423
33e3885d 2424 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2425 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2426 /* Disable writeback. */
2427 c->dst.type = OP_NONE;
aca7f966 2428 break;
6aa8b732 2429 case 2: /* lgdt */
e4e03ded
LV		 2430 rc = read_descriptor(ctxt, ops, c->src.ptr,
2431 &size, &address, c->op_bytes);
6aa8b732
AK		 2432 if (rc)
2433 goto done;
2434 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2435 /* Disable writeback. */
2436 c->dst.type = OP_NONE;
6aa8b732 2437 break;
aca7f966 2438 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2439 if (c->modrm_mod == 3) {
2440 switch (c->modrm_rm) {
2441 case 1:
2442 rc = kvm_fix_hypercall(ctxt->vcpu);
2443 if (rc)
2444 goto done;
2445 break;
2446 default:
2447 goto cannot_emulate;
2448 }
aca7f966 2449 } else {
e4e03ded 2450 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2451 &size, &address,
e4e03ded 2452 c->op_bytes);
aca7f966
AL		 2453 if (rc)
2454 goto done;
2455 realmode_lidt(ctxt->vcpu, size, address);
2456 }
16286d08
AK		 2457 /* Disable writeback. */
2458 c->dst.type = OP_NONE;
6aa8b732
AK		 2459 break;
2460 case 4: /* smsw */
16286d08
AK		 2461 c->dst.bytes = 2;
2462 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2463 break;
2464 case 6: /* lmsw */
16286d08
AK		 2465 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2466 &ctxt->eflags);
dc7457ea 2467 c->dst.type = OP_NONE;
6aa8b732
AK		 2468 break;
2469 case 7: /* invlpg*/
e8d8d7fe 2470 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2471 /* Disable writeback. */
2472 c->dst.type = OP_NONE;
6aa8b732
AK		 2473 break;
2474 default:
2475 goto cannot_emulate;
2476 }
2477 break;
e99f0507 2478 case 0x05: /* syscall */
e54cfa97
TY		 2479 rc = emulate_syscall(ctxt);
2480 if (rc != X86EMUL_CONTINUE)
2481 goto done;
e66bb2cc
AP		 2482 else
2483 goto writeback;
e99f0507 2484 break;
018a98db
AK		 2485 case 0x06:
2486 emulate_clts(ctxt->vcpu);
2487 c->dst.type = OP_NONE;
2488 break;
2489 case 0x08: /* invd */
2490 case 0x09: /* wbinvd */
2491 case 0x0d: /* GrpP (prefetch) */
2492 case 0x18: /* Grp16 (prefetch/nop) */
2493 c->dst.type = OP_NONE;
2494 break;
2495 case 0x20: /* mov cr, reg */
2496 if (c->modrm_mod != 3)
2497 goto cannot_emulate;
2498 c->regs[c->modrm_rm] =
2499 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2500 c->dst.type = OP_NONE; /* no writeback */
2501 break;
6aa8b732 2502 case 0x21: /* mov from dr to reg */
e4e03ded 2503 if (c->modrm_mod != 3)
6aa8b732 2504 goto cannot_emulate;
8cdbd2c9 2505 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2506 if (rc)
2507 goto cannot_emulate;
2508 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2509 break;
018a98db
AK		 2510 case 0x22: /* mov reg, cr */
2511 if (c->modrm_mod != 3)
2512 goto cannot_emulate;
2513 realmode_set_cr(ctxt->vcpu,
2514 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2515 c->dst.type = OP_NONE;
2516 break;
6aa8b732 2517 case 0x23: /* mov from reg to dr */
e4e03ded 2518 if (c->modrm_mod != 3)
6aa8b732 2519 goto cannot_emulate;
e4e03ded
LV		 2520 rc = emulator_set_dr(ctxt, c->modrm_reg,
2521 c->regs[c->modrm_rm]);
a01af5ec
LV		 2522 if (rc)
2523 goto cannot_emulate;
2524 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2525 break;
018a98db
AK		 2526 case 0x30:
2527 /* wrmsr */
2528 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2529 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2530 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2531 if (rc) {
c1a5d4f9 2532 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2533 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2534 }
2535 rc = X86EMUL_CONTINUE;
2536 c->dst.type = OP_NONE;
2537 break;
2538 case 0x32:
2539 /* rdmsr */
2540 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2541 if (rc) {
c1a5d4f9 2542 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2543 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2544 } else {
2545 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2546 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2547 }
2548 rc = X86EMUL_CONTINUE;
2549 c->dst.type = OP_NONE;
2550 break;
e99f0507 2551 case 0x34: /* sysenter */
e54cfa97
TY		 2552 rc = emulate_sysenter(ctxt);
2553 if (rc != X86EMUL_CONTINUE)
2554 goto done;
8c604352
AP		 2555 else
2556 goto writeback;
e99f0507
AP		 2557 break;
2558 case 0x35: /* sysexit */
e54cfa97
TY		 2559 rc = emulate_sysexit(ctxt);
2560 if (rc != X86EMUL_CONTINUE)
2561 goto done;
4668f050
AP		 2562 else
2563 goto writeback;
e99f0507 2564 break;
6aa8b732 2565 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2566 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2567 if (!test_cc(c->b, ctxt->eflags))
2568 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2569 break;
b2833e3c 2570 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2571 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2572 jmp_rel(c, c->src.val);
018a98db
AK		 2573 c->dst.type = OP_NONE;
2574 break;
0934ac9d
MG		 2575 case 0xa0: /* push fs */
2576 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2577 break;
2578 case 0xa1: /* pop fs */
2579 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2580 if (rc != 0)
2581 goto done;
2582 break;
7de75248
NK		 2583 case 0xa3:
2584 bt: /* bt */
e4f8e039 2585 c->dst.type = OP_NONE;
e4e03ded
LV		 2586 /* only subword offset */
2587 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2588 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2589 break;
9bf8ea42
GT		 2590 case 0xa4: /* shld imm8, r, r/m */
2591 case 0xa5: /* shld cl, r, r/m */
2592 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2593 break;
0934ac9d
MG		 2594 case 0xa8: /* push gs */
2595 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2596 break;
2597 case 0xa9: /* pop gs */
2598 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2599 if (rc != 0)
2600 goto done;
2601 break;
7de75248
NK		 2602 case 0xab:
2603 bts: /* bts */
e4e03ded
LV		 2604 /* only subword offset */
2605 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2606 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2607 break;
9bf8ea42
GT		 2608 case 0xac: /* shrd imm8, r, r/m */
2609 case 0xad: /* shrd cl, r, r/m */
2610 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2611 break;
2a7c5b8b
GC		 2612 case 0xae: /* clflush */
2613 break;
6aa8b732
AK		 2614 case 0xb0 ... 0xb1: /* cmpxchg */
2615 /*
2616 * Save real source value, then compare EAX against
2617 * destination.
2618 */
e4e03ded
LV		 2619 c->src.orig_val = c->src.val;
2620 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2621 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2622 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2623 /* Success: write back to memory. */
e4e03ded 2624 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2625 } else {
2626 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2627 c->dst.type = OP_REG;
2628 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2629 }
2630 break;
6aa8b732
AK		 2631 case 0xb3:
2632 btr: /* btr */
e4e03ded
LV		 2633 /* only subword offset */
2634 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2635 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2636 break;
6aa8b732 2637 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2638 c->dst.bytes = c->op_bytes;
2639 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2640 : (u16) c->src.val;
6aa8b732 2641 break;
6aa8b732 2642 case 0xba: /* Grp8 */
e4e03ded 2643 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2644 case 0:
2645 goto bt;
2646 case 1:
2647 goto bts;
2648 case 2:
2649 goto btr;
2650 case 3:
2651 goto btc;
2652 }
2653 break;
7de75248
NK		 2654 case 0xbb:
2655 btc: /* btc */
e4e03ded
LV		 2656 /* only subword offset */
2657 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2658 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2659 break;
6aa8b732 2660 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2661 c->dst.bytes = c->op_bytes;
2662 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2663 (s16) c->src.val;
6aa8b732 2664 break;
a012e65a 2665 case 0xc3: /* movnti */
e4e03ded
LV		 2666 c->dst.bytes = c->op_bytes;
2667 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2668 (u64) c->src.val;
a012e65a 2669 break;
6aa8b732 2670 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2671 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2672 if (rc != 0)
2673 goto done;
018a98db 2674 c->dst.type = OP_NONE;
8cdbd2c9 2675 break;
6aa8b732
AK		 2676 }
2677 goto writeback;
2678
2679cannot_emulate:
e4e03ded 2680 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2681 c->eip = saved_eip;
6aa8b732
AK		 2682 return -1;
2683}
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