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KVM: x86: fnstcw and fnstsw may cause spurious exception
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 128#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 129/* Generic ModRM decode. */
130#define ModRM (1<<19)
131/* Destination is only written; never read. */
132#define Mov (1<<20)
d8769fed 133/* Misc flags */
8ea7d6ae 134#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 135#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 136#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 137#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 138#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 139#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 140#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 141#define No64 (1<<28)
d5ae7ce8 142#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 143#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 144/* Source 2 operand type */
0b789eee 145#define Src2Shift (31)
4dd6a57d 146#define Src2None (OpNone << Src2Shift)
ab2c5ce6 147#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 148#define Src2CL (OpCL << Src2Shift)
149#define Src2ImmByte (OpImmByte << Src2Shift)
150#define Src2One (OpOne << Src2Shift)
151#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 152#define Src2ES (OpES << Src2Shift)
153#define Src2CS (OpCS << Src2Shift)
154#define Src2SS (OpSS << Src2Shift)
155#define Src2DS (OpDS << Src2Shift)
156#define Src2FS (OpFS << Src2Shift)
157#define Src2GS (OpGS << Src2Shift)
4dd6a57d 158#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 159#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 160#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
161#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
162#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 163#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 164#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 165#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 166#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 167#define Intercept ((u64)1 << 48) /* Has valid intercept field */
168#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 169#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 170#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 171#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 172#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 173
820207c8 174#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 175
d0e53325
AK		 176#define X2(x...) x, x
177#define X3(x...) X2(x), x
178#define X4(x...) X2(x), X2(x)
179#define X5(x...) X4(x), x
180#define X6(x...) X4(x), X2(x)
181#define X7(x...) X4(x), X3(x)
182#define X8(x...) X4(x), X4(x)
183#define X16(x...) X8(x), X8(x)
83babbca 184
e28bbd44
AK		 185#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
186#define FASTOP_SIZE 8
187
188/*
189 * fastop functions have a special calling convention:
190 *
017da7b6
AK		 191 * dst: rax (in/out)
192 * src: rdx (in/out)
e28bbd44
AK		 193 * src2: rcx (in)
194 * flags: rflags (in/out)
b8c0b6ae 195 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 196 *
197 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
198 * different operand sizes can be reached by calculation, rather than a jump
199 * table (which would be bigger than the code).
200 *
201 * fastop functions are declared as taking a never-defined fastop parameter,
202 * so they can't be called from C directly.
203 */
204
205struct fastop;
206
d65b1dee 207struct opcode {
b1ea50b2
AK		 208 u64 flags : 56;
209 u64 intercept : 8;
120df890 210 union {
ef65c889 211 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 212 const struct opcode *group;
213 const struct group_dual *gdual;
214 const struct gprefix *gprefix;
045a282c 215 const struct escape *esc;
39f062ff 216 const struct instr_dual *idual;
e28bbd44 217 void (*fastop)(struct fastop *fake);
120df890 218 } u;
d09beabd 219 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 220};
221
222struct group_dual {
223 struct opcode mod012[8];
224 struct opcode mod3[8];
d65b1dee
AK		 225};
226
0d7cdee8
AK		 227struct gprefix {
228 struct opcode pfx_no;
229 struct opcode pfx_66;
230 struct opcode pfx_f2;
231 struct opcode pfx_f3;
232};
233
045a282c
GN		 234struct escape {
235 struct opcode op[8];
236 struct opcode high[64];
237};
238
39f062ff
NA		 239struct instr_dual {
240 struct opcode mod012;
241 struct opcode mod3;
242};
243
6aa8b732 244/* EFLAGS bit definitions. */
d4c6a154
GN		 245#define EFLG_ID (1<<21)
246#define EFLG_VIP (1<<20)
247#define EFLG_VIF (1<<19)
248#define EFLG_AC (1<<18)
b1d86143
AP		 249#define EFLG_VM (1<<17)
250#define EFLG_RF (1<<16)
d4c6a154
GN		 251#define EFLG_IOPL (3<<12)
252#define EFLG_NT (1<<14)
6aa8b732
AK		 253#define EFLG_OF (1<<11)
254#define EFLG_DF (1<<10)
b1d86143 255#define EFLG_IF (1<<9)
d4c6a154 256#define EFLG_TF (1<<8)
6aa8b732
AK		 257#define EFLG_SF (1<<7)
258#define EFLG_ZF (1<<6)
259#define EFLG_AF (1<<4)
260#define EFLG_PF (1<<2)
261#define EFLG_CF (1<<0)
262
62bd430e
MG		 263#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
264#define EFLG_RESERVED_ONE_MASK 2
265
dd856efa
AK		 266static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 if (!(ctxt->regs_valid & (1 << nr))) {
269 ctxt->regs_valid |= 1 << nr;
270 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
271 }
272 return ctxt->_regs[nr];
273}
274
275static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
276{
277 ctxt->regs_valid |= 1 << nr;
278 ctxt->regs_dirty |= 1 << nr;
279 return &ctxt->_regs[nr];
280}
281
282static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
283{
284 reg_read(ctxt, nr);
285 return reg_write(ctxt, nr);
286}
287
288static void writeback_registers(struct x86_emulate_ctxt *ctxt)
289{
290 unsigned reg;
291
292 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
293 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
294}
295
296static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
297{
298 ctxt->regs_dirty = 0;
299 ctxt->regs_valid = 0;
300}
301
6aa8b732
AK		 302/*
303 * These EFLAGS bits are restored from saved value during emulation, and
304 * any changes are written back to the saved value after emulation.
305 */
306#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
307
dda96d8f
AK		 308#ifdef CONFIG_X86_64
309#define ON64(x) x
310#else
311#define ON64(x)
312#endif
313
4d758349
AK		 314static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
315
b7d491e7
AK		 316#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
317#define FOP_RET "ret \n\t"
318
319#define FOP_START(op) \
320 extern void em_##op(struct fastop *fake); \
321 asm(".pushsection .text, \"ax\" \n\t" \
322 ".global em_" #op " \n\t" \
323 FOP_ALIGN \
324 "em_" #op ": \n\t"
325
326#define FOP_END \
327 ".popsection")
328
0bdea068
AK		 329#define FOPNOP() FOP_ALIGN FOP_RET
330
b7d491e7 331#define FOP1E(op, dst) \
b8c0b6ae
AK		 332 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
333
334#define FOP1EEX(op, dst) \
335 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 336
337#define FASTOP1(op) \
338 FOP_START(op) \
339 FOP1E(op##b, al) \
340 FOP1E(op##w, ax) \
341 FOP1E(op##l, eax) \
342 ON64(FOP1E(op##q, rax)) \
343 FOP_END
344
b9fa409b
AK		 345/* 1-operand, using src2 (for MUL/DIV r/m) */
346#define FASTOP1SRC2(op, name) \
347 FOP_START(name) \
348 FOP1E(op, cl) \
349 FOP1E(op, cx) \
350 FOP1E(op, ecx) \
351 ON64(FOP1E(op, rcx)) \
352 FOP_END
353
b8c0b6ae
AK		 354/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
355#define FASTOP1SRC2EX(op, name) \
356 FOP_START(name) \
357 FOP1EEX(op, cl) \
358 FOP1EEX(op, cx) \
359 FOP1EEX(op, ecx) \
360 ON64(FOP1EEX(op, rcx)) \
361 FOP_END
362
f7857f35
AK		 363#define FOP2E(op, dst, src) \
364 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
365
366#define FASTOP2(op) \
367 FOP_START(op) \
017da7b6
AK		 368 FOP2E(op##b, al, dl) \
369 FOP2E(op##w, ax, dx) \
370 FOP2E(op##l, eax, edx) \
371 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 372 FOP_END
373
11c363ba
AK		 374/* 2 operand, word only */
375#define FASTOP2W(op) \
376 FOP_START(op) \
377 FOPNOP() \
017da7b6
AK		 378 FOP2E(op##w, ax, dx) \
379 FOP2E(op##l, eax, edx) \
380 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 381 FOP_END
382
007a3b54
AK		 383/* 2 operand, src is CL */
384#define FASTOP2CL(op) \
385 FOP_START(op) \
386 FOP2E(op##b, al, cl) \
387 FOP2E(op##w, ax, cl) \
388 FOP2E(op##l, eax, cl) \
389 ON64(FOP2E(op##q, rax, cl)) \
390 FOP_END
391
5aca3722
NA		 392/* 2 operand, src and dest are reversed */
393#define FASTOP2R(op, name) \
394 FOP_START(name) \
395 FOP2E(op##b, dl, al) \
396 FOP2E(op##w, dx, ax) \
397 FOP2E(op##l, edx, eax) \
398 ON64(FOP2E(op##q, rdx, rax)) \
399 FOP_END
400
0bdea068
AK		 401#define FOP3E(op, dst, src, src2) \
402 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
403
404/* 3-operand, word-only, src2=cl */
405#define FASTOP3WCL(op) \
406 FOP_START(op) \
407 FOPNOP() \
017da7b6
AK		 408 FOP3E(op##w, ax, dx, cl) \
409 FOP3E(op##l, eax, edx, cl) \
410 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 411 FOP_END
412
9ae9feba
AK		 413/* Special case for SETcc - 1 instruction per cc */
414#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
415
b8c0b6ae
AK		 416asm(".global kvm_fastop_exception \n"
417 "kvm_fastop_exception: xor %esi, %esi; ret");
418
9ae9feba
AK		 419FOP_START(setcc)
420FOP_SETCC(seto)
421FOP_SETCC(setno)
422FOP_SETCC(setc)
423FOP_SETCC(setnc)
424FOP_SETCC(setz)
425FOP_SETCC(setnz)
426FOP_SETCC(setbe)
427FOP_SETCC(setnbe)
428FOP_SETCC(sets)
429FOP_SETCC(setns)
430FOP_SETCC(setp)
431FOP_SETCC(setnp)
432FOP_SETCC(setl)
433FOP_SETCC(setnl)
434FOP_SETCC(setle)
435FOP_SETCC(setnle)
436FOP_END;
437
326f578f
PB		 438FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
439FOP_END;
440
8a76d7f2
JR		 441static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
442 enum x86_intercept intercept,
443 enum x86_intercept_stage stage)
444{
445 struct x86_instruction_info info = {
446 .intercept = intercept,
9dac77fa
AK		 447 .rep_prefix = ctxt->rep_prefix,
448 .modrm_mod = ctxt->modrm_mod,
449 .modrm_reg = ctxt->modrm_reg,
450 .modrm_rm = ctxt->modrm_rm,
451 .src_val = ctxt->src.val64,
6cbc5f5a 452 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 453 .src_bytes = ctxt->src.bytes,
454 .dst_bytes = ctxt->dst.bytes,
455 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 456 .next_rip = ctxt->eip,
457 };
458
2953538e 459 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 460}
461
f47cfa31
AK		 462static void assign_masked(ulong *dest, ulong src, ulong mask)
463{
464 *dest = (*dest & ~mask) | (src & mask);
465}
466
9dac77fa 467static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 468{
9dac77fa 469 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 470}
471
f47cfa31
AK		 472static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
473{
474 u16 sel;
475 struct desc_struct ss;
476
477 if (ctxt->mode == X86EMUL_MODE_PROT64)
478 return ~0UL;
479 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
480 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
481}
482
612e89f0
AK		 483static int stack_size(struct x86_emulate_ctxt *ctxt)
484{
485 return (__fls(stack_mask(ctxt)) + 1) >> 3;
486}
487
6aa8b732 488/* Access/update address held in a register, based on addressing mode. */
e4706772 489static inline unsigned long
9dac77fa 490address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 491{
9dac77fa 492 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 493 return reg;
494 else
9dac77fa 495 return reg & ad_mask(ctxt);
e4706772
HH		 496}
497
498static inline unsigned long
01485a22 499register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 500{
01485a22 501 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 502}
503
5ad105e5
AK		 504static void masked_increment(ulong *reg, ulong mask, int inc)
505{
506 assign_masked(reg, *reg + inc, mask);
507}
508
7a957275 509static inline void
01485a22 510register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 511{
5ad105e5
AK		 512 ulong mask;
513
9dac77fa 514 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 515 mask = ~0UL;
7a957275 516 else
5ad105e5 517 mask = ad_mask(ctxt);
01485a22 518 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 519}
520
521static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
522{
dd856efa 523 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 524}
6aa8b732 525
56697687
AK		 526static u32 desc_limit_scaled(struct desc_struct *desc)
527{
528 u32 limit = get_desc_limit(desc);
529
530 return desc->g ? (limit << 12) | 0xfff : limit;
531}
532
7b105ca2 533static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 534{
535 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
536 return 0;
537
7b105ca2 538 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 539}
540
35d3d4a1
AK		 541static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
542 u32 error, bool valid)
54b8486f 543{
e0ad0b47 544 WARN_ON(vec > 0x1f);
da9cb575
AK		 545 ctxt->exception.vector = vec;
546 ctxt->exception.error_code = error;
547 ctxt->exception.error_code_valid = valid;
35d3d4a1 548 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 549}
550
3b88e41a
JR		 551static int emulate_db(struct x86_emulate_ctxt *ctxt)
552{
553 return emulate_exception(ctxt, DB_VECTOR, 0, false);
554}
555
35d3d4a1 556static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 557{
35d3d4a1 558 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 559}
560
618ff15d
AK		 561static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
562{
563 return emulate_exception(ctxt, SS_VECTOR, err, true);
564}
565
35d3d4a1 566static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 567{
35d3d4a1 568 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 569}
570
35d3d4a1 571static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 572{
35d3d4a1 573 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 574}
575
34d1f490
AK		 576static int emulate_de(struct x86_emulate_ctxt *ctxt)
577{
35d3d4a1 578 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 579}
580
1253791d
AK		 581static int emulate_nm(struct x86_emulate_ctxt *ctxt)
582{
583 return emulate_exception(ctxt, NM_VECTOR, 0, false);
584}
585
1aa36616
AK		 586static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
587{
588 u16 selector;
589 struct desc_struct desc;
590
591 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
592 return selector;
593}
594
595static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
596 unsigned seg)
597{
598 u16 dummy;
599 u32 base3;
600 struct desc_struct desc;
601
602 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
603 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
604}
605
1c11b376
AK		 606/*
607 * x86 defines three classes of vector instructions: explicitly
608 * aligned, explicitly unaligned, and the rest, which change behaviour
609 * depending on whether they're AVX encoded or not.
610 *
611 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
612 * subject to the same check.
613 */
614static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
615{
616 if (likely(size < 16))
617 return false;
618
619 if (ctxt->d & Aligned)
620 return true;
621 else if (ctxt->d & Unaligned)
622 return false;
623 else if (ctxt->d & Avx)
624 return false;
625 else
626 return true;
627}
628
d09155d2
PB		 629static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
630 struct segmented_address addr,
631 unsigned *max_size, unsigned size,
632 bool write, bool fetch,
d50eaa18 633 enum x86emul_mode mode, ulong *linear)
52fd8b44 634{
618ff15d
AK		 635 struct desc_struct desc;
636 bool usable;
52fd8b44 637 ulong la;
618ff15d 638 u32 lim;
1aa36616 639 u16 sel;
52fd8b44 640
7b105ca2 641 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 642 *max_size = 0;
d50eaa18 643 switch (mode) {
618ff15d 644 case X86EMUL_MODE_PROT64:
4be4de7e 645 if (is_noncanonical_address(la))
abc7d8a4 646 goto bad;
fd56e154
PB		 647
648 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
649 if (size > *max_size)
650 goto bad;
618ff15d
AK		 651 break;
652 default:
1aa36616
AK		 653 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
654 addr.seg);
618ff15d
AK		 655 if (!usable)
656 goto bad;
58b7825b
GN		 657 /* code segment in protected mode or read-only data segment */
658 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
659 || !(desc.type & 2)) && write)
618ff15d
AK		 660 goto bad;
661 /* unreadable code segment */
3d9b938e 662 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 663 goto bad;
664 lim = desc_limit_scaled(&desc);
997b0412 665 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 666 /* expand-down segment */
fd56e154 667 if (addr.ea <= lim)
618ff15d
AK		 668 goto bad;
669 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 670 }
997b0412
PB		 671 if (addr.ea > lim)
672 goto bad;
673 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 674 if (size > *max_size)
675 goto bad;
31ff6488 676 la &= (u32)-1;
618ff15d
AK		 677 break;
678 }
1c11b376
AK		 679 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
680 return emulate_gp(ctxt, 0);
52fd8b44
AK		 681 *linear = la;
682 return X86EMUL_CONTINUE;
618ff15d
AK		 683bad:
684 if (addr.seg == VCPU_SREG_SS)
3606189f 685 return emulate_ss(ctxt, 0);
618ff15d 686 else
3606189f 687 return emulate_gp(ctxt, 0);
52fd8b44
AK		 688}
689
3d9b938e
NE		 690static int linearize(struct x86_emulate_ctxt *ctxt,
691 struct segmented_address addr,
692 unsigned size, bool write,
693 ulong *linear)
694{
fd56e154 695 unsigned max_size;
d50eaa18
NA		 696 return __linearize(ctxt, addr, &max_size, size, write, false,
697 ctxt->mode, linear);
3d9b938e
NE		 698}
699
d50eaa18
NA		 700static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
701 enum x86emul_mode mode)
702{
703 ulong linear;
704 int rc;
705 unsigned max_size;
706 struct segmented_address addr = { .seg = VCPU_SREG_CS,
707 .ea = dst };
708
709 if (ctxt->op_bytes != sizeof(unsigned long))
710 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
711 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
712 if (rc == X86EMUL_CONTINUE)
713 ctxt->_eip = addr.ea;
714 return rc;
715}
716
717static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
718{
719 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 720}
721
d50eaa18
NA		 722static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
723 const struct desc_struct *cs_desc)
724{
725 enum x86emul_mode mode = ctxt->mode;
726
727#ifdef CONFIG_X86_64
728 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
729 u64 efer = 0;
730
731 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
732 if (efer & EFER_LMA)
733 mode = X86EMUL_MODE_PROT64;
734 }
735#endif
736 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
737 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
738 return assign_eip(ctxt, dst, mode);
739}
740
741static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
742{
743 return assign_eip_near(ctxt, ctxt->_eip + rel);
744}
3d9b938e 745
3ca3ac4d
AK		 746static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
747 struct segmented_address addr,
748 void *data,
749 unsigned size)
750{
9fa088f4
AK		 751 int rc;
752 ulong linear;
753
83b8795a 754 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 755 if (rc != X86EMUL_CONTINUE)
756 return rc;
0f65dd70 757 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 758}
759
807941b1 760/*
285ca9e9 761 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 762 * boundary if they are not in fetch_cache yet.
763 */
9506d57d 764static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 765{
62266869 766 int rc;
fd56e154 767 unsigned size, max_size;
285ca9e9 768 unsigned long linear;
17052f16 769 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 770 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 771 .ea = ctxt->eip + cur_size };
772
fd56e154
PB		 773 /*
774 * We do not know exactly how many bytes will be needed, and
775 * __linearize is expensive, so fetch as much as possible. We
776 * just have to avoid going beyond the 15 byte limit, the end
777 * of the segment, or the end of the page.
778 *
779 * __linearize is called with size 0 so that it does not do any
780 * boundary check itself. Instead, we use max_size to check
781 * against op_size.
782 */
d50eaa18
NA		 783 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
784 &linear);
719d5a9b
PB		 785 if (unlikely(rc != X86EMUL_CONTINUE))
786 return rc;
787
fd56e154 788 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 789 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 790
791 /*
792 * One instruction can only straddle two pages,
793 * and one has been loaded at the beginning of
794 * x86_decode_insn. So, if not enough bytes
795 * still, we must have hit the 15-byte boundary.
796 */
797 if (unlikely(size < op_size))
fd56e154
PB		 798 return emulate_gp(ctxt, 0);
799
17052f16 800 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 801 size, &ctxt->exception);
802 if (unlikely(rc != X86EMUL_CONTINUE))
803 return rc;
17052f16 804 ctxt->fetch.end += size;
3e2815e9 805 return X86EMUL_CONTINUE;
62266869
AK		 806}
807
9506d57d
PB		 808static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
809 unsigned size)
62266869 810{
08da44ae
NA		 811 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
812
813 if (unlikely(done_size < size))
814 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 815 else
816 return X86EMUL_CONTINUE;
62266869
AK		 817}
818
67cbc90d 819/* Fetch next part of the instruction being emulated. */
e85a1085 820#define insn_fetch(_type, _ctxt) \
9506d57d 821({ _type _x; \
9506d57d
PB		 822 \
823 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 824 if (rc != X86EMUL_CONTINUE) \
825 goto done; \
9506d57d 826 ctxt->_eip += sizeof(_type); \
17052f16
PB		 827 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
828 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 829 _x; \
67cbc90d
TY		 830})
831
807941b1 832#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 833({ \
9506d57d 834 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 835 if (rc != X86EMUL_CONTINUE) \
836 goto done; \
9506d57d 837 ctxt->_eip += (_size); \
17052f16
PB		 838 memcpy(_arr, ctxt->fetch.ptr, _size); \
839 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 840})
841
1e3c5cb0
RR		 842/*
843 * Given the 'reg' portion of a ModRM byte, and a register block, return a
844 * pointer into the block that addresses the relevant register.
845 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
846 */
dd856efa 847static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 848 int byteop)
6aa8b732
AK		 849{
850 void *p;
aa9ac1a6 851 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 852
6aa8b732 853 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 854 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
855 else
856 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 857 return p;
858}
859
860static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 861 struct segmented_address addr,
6aa8b732
AK		 862 u16 *size, unsigned long *address, int op_bytes)
863{
864 int rc;
865
866 if (op_bytes == 2)
867 op_bytes = 3;
868 *address = 0;
3ca3ac4d 869 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 870 if (rc != X86EMUL_CONTINUE)
6aa8b732 871 return rc;
30b31ab6 872 addr.ea += 2;
3ca3ac4d 873 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 874 return rc;
875}
876
34b77652
AK		 877FASTOP2(add);
878FASTOP2(or);
879FASTOP2(adc);
880FASTOP2(sbb);
881FASTOP2(and);
882FASTOP2(sub);
883FASTOP2(xor);
884FASTOP2(cmp);
885FASTOP2(test);
886
b9fa409b
AK		 887FASTOP1SRC2(mul, mul_ex);
888FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 889FASTOP1SRC2EX(div, div_ex);
890FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 891
34b77652
AK		 892FASTOP3WCL(shld);
893FASTOP3WCL(shrd);
894
895FASTOP2W(imul);
896
897FASTOP1(not);
898FASTOP1(neg);
899FASTOP1(inc);
900FASTOP1(dec);
901
902FASTOP2CL(rol);
903FASTOP2CL(ror);
904FASTOP2CL(rcl);
905FASTOP2CL(rcr);
906FASTOP2CL(shl);
907FASTOP2CL(shr);
908FASTOP2CL(sar);
909
910FASTOP2W(bsf);
911FASTOP2W(bsr);
912FASTOP2W(bt);
913FASTOP2W(bts);
914FASTOP2W(btr);
915FASTOP2W(btc);
916
e47a5f5f
AK		 917FASTOP2(xadd);
918
5aca3722
NA		 919FASTOP2R(cmp, cmp_r);
920
9ae9feba 921static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 922{
9ae9feba
AK		 923 u8 rc;
924 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 925
9ae9feba 926 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 927 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 928 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
929 return rc;
bbe9abbd
NK		 930}
931
91ff3cb4
AK		 932static void fetch_register_operand(struct operand *op)
933{
934 switch (op->bytes) {
935 case 1:
936 op->val = *(u8 *)op->addr.reg;
937 break;
938 case 2:
939 op->val = *(u16 *)op->addr.reg;
940 break;
941 case 4:
942 op->val = *(u32 *)op->addr.reg;
943 break;
944 case 8:
945 op->val = *(u64 *)op->addr.reg;
946 break;
947 }
948}
949
1253791d
AK		 950static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
951{
952 ctxt->ops->get_fpu(ctxt);
953 switch (reg) {
89a87c67
MK		 954 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
955 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
956 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
957 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
958 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
959 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
960 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
961 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 962#ifdef CONFIG_X86_64
89a87c67
MK		 963 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
964 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
965 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
966 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
967 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
968 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
969 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
970 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 971#endif
972 default: BUG();
973 }
974 ctxt->ops->put_fpu(ctxt);
975}
976
977static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
978 int reg)
979{
980 ctxt->ops->get_fpu(ctxt);
981 switch (reg) {
89a87c67
MK		 982 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
983 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
984 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
985 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
986 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
987 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
988 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
989 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 990#ifdef CONFIG_X86_64
89a87c67
MK		 991 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
992 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
993 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
994 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
995 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
996 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
997 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
998 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 999#endif
1000 default: BUG();
1001 }
1002 ctxt->ops->put_fpu(ctxt);
1003}
1004
cbe2c9d3
AK		 1005static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1006{
1007 ctxt->ops->get_fpu(ctxt);
1008 switch (reg) {
1009 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1010 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1011 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1012 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1013 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1014 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1015 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1016 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1017 default: BUG();
1018 }
1019 ctxt->ops->put_fpu(ctxt);
1020}
1021
1022static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1023{
1024 ctxt->ops->get_fpu(ctxt);
1025 switch (reg) {
1026 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1027 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1028 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1029 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1030 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1031 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1032 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1033 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1034 default: BUG();
1035 }
1036 ctxt->ops->put_fpu(ctxt);
1037}
1038
045a282c
GN		 1039static int em_fninit(struct x86_emulate_ctxt *ctxt)
1040{
1041 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1042 return emulate_nm(ctxt);
1043
1044 ctxt->ops->get_fpu(ctxt);
1045 asm volatile("fninit");
1046 ctxt->ops->put_fpu(ctxt);
1047 return X86EMUL_CONTINUE;
1048}
1049
1050static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1051{
1052 u16 fcw;
1053
1054 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1055 return emulate_nm(ctxt);
1056
1057 ctxt->ops->get_fpu(ctxt);
1058 asm volatile("fnstcw %0": "+m"(fcw));
1059 ctxt->ops->put_fpu(ctxt);
1060
045a282c
GN		 1061 ctxt->dst.val = fcw;
1062
1063 return X86EMUL_CONTINUE;
1064}
1065
1066static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1067{
1068 u16 fsw;
1069
1070 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1071 return emulate_nm(ctxt);
1072
1073 ctxt->ops->get_fpu(ctxt);
1074 asm volatile("fnstsw %0": "+m"(fsw));
1075 ctxt->ops->put_fpu(ctxt);
1076
045a282c
GN		 1077 ctxt->dst.val = fsw;
1078
1079 return X86EMUL_CONTINUE;
1080}
1081
1253791d 1082static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1083 struct operand *op)
3c118e24 1084{
9dac77fa 1085 unsigned reg = ctxt->modrm_reg;
33615aa9 1086
9dac77fa
AK		 1087 if (!(ctxt->d & ModRM))
1088 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1089
9dac77fa 1090 if (ctxt->d & Sse) {
1253791d
AK		 1091 op->type = OP_XMM;
1092 op->bytes = 16;
1093 op->addr.xmm = reg;
1094 read_sse_reg(ctxt, &op->vec_val, reg);
1095 return;
1096 }
cbe2c9d3
AK		 1097 if (ctxt->d & Mmx) {
1098 reg &= 7;
1099 op->type = OP_MM;
1100 op->bytes = 8;
1101 op->addr.mm = reg;
1102 return;
1103 }
1253791d 1104
3c118e24 1105 op->type = OP_REG;
6d4d85ec
GN		 1106 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1107 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1108
91ff3cb4 1109 fetch_register_operand(op);
3c118e24
AK		 1110 op->orig_val = op->val;
1111}
1112
a6e3407b
AK		 1113static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1114{
1115 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1116 ctxt->modrm_seg = VCPU_SREG_SS;
1117}
1118
1c73ef66 1119static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1120 struct operand *op)
1c73ef66 1121{
1c73ef66 1122 u8 sib;
02357bdc 1123 int index_reg, base_reg, scale;
3e2815e9 1124 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1125 ulong modrm_ea = 0;
1c73ef66 1126
02357bdc
BD		 1127 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1128 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1129 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1130
02357bdc 1131 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1132 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1133 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1134 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1135
9b88ae99 1136 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1137 op->type = OP_REG;
9dac77fa 1138 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1139 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1140 ctxt->d & ByteOp);
9dac77fa 1141 if (ctxt->d & Sse) {
1253791d
AK		 1142 op->type = OP_XMM;
1143 op->bytes = 16;
9dac77fa
AK		 1144 op->addr.xmm = ctxt->modrm_rm;
1145 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1146 return rc;
1147 }
cbe2c9d3
AK		 1148 if (ctxt->d & Mmx) {
1149 op->type = OP_MM;
1150 op->bytes = 8;
bdc90722 1151 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1152 return rc;
1153 }
2dbd0dd7 1154 fetch_register_operand(op);
1c73ef66
AK		 1155 return rc;
1156 }
1157
2dbd0dd7
AK		 1158 op->type = OP_MEM;
1159
9dac77fa 1160 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1161 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1162 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1163 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1164 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1165
1166 /* 16-bit ModR/M decode. */
9dac77fa 1167 switch (ctxt->modrm_mod) {
1c73ef66 1168 case 0:
9dac77fa 1169 if (ctxt->modrm_rm == 6)
e85a1085 1170 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1171 break;
1172 case 1:
e85a1085 1173 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1174 break;
1175 case 2:
e85a1085 1176 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1177 break;
1178 }
9dac77fa 1179 switch (ctxt->modrm_rm) {
1c73ef66 1180 case 0:
2dbd0dd7 1181 modrm_ea += bx + si;
1c73ef66
AK		 1182 break;
1183 case 1:
2dbd0dd7 1184 modrm_ea += bx + di;
1c73ef66
AK		 1185 break;
1186 case 2:
2dbd0dd7 1187 modrm_ea += bp + si;
1c73ef66
AK		 1188 break;
1189 case 3:
2dbd0dd7 1190 modrm_ea += bp + di;
1c73ef66
AK		 1191 break;
1192 case 4:
2dbd0dd7 1193 modrm_ea += si;
1c73ef66
AK		 1194 break;
1195 case 5:
2dbd0dd7 1196 modrm_ea += di;
1c73ef66
AK		 1197 break;
1198 case 6:
9dac77fa 1199 if (ctxt->modrm_mod != 0)
2dbd0dd7 1200 modrm_ea += bp;
1c73ef66
AK		 1201 break;
1202 case 7:
2dbd0dd7 1203 modrm_ea += bx;
1c73ef66
AK		 1204 break;
1205 }
9dac77fa
AK		 1206 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1207 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1208 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1209 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1210 } else {
1211 /* 32/64-bit ModR/M decode. */
9dac77fa 1212 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1213 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1214 index_reg |= (sib >> 3) & 7;
1215 base_reg |= sib & 7;
1216 scale = sib >> 6;
1217
9dac77fa 1218 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1219 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1220 else {
dd856efa 1221 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1222 adjust_modrm_seg(ctxt, base_reg);
1223 }
dc71d0f1 1224 if (index_reg != 4)
dd856efa 1225 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1226 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1227 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1228 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1229 ctxt->rip_relative = 1;
a6e3407b
AK		 1230 } else {
1231 base_reg = ctxt->modrm_rm;
dd856efa 1232 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1233 adjust_modrm_seg(ctxt, base_reg);
1234 }
9dac77fa 1235 switch (ctxt->modrm_mod) {
1c73ef66 1236 case 1:
e85a1085 1237 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1238 break;
1239 case 2:
e85a1085 1240 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1241 break;
1242 }
1243 }
90de84f5 1244 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1245 if (ctxt->ad_bytes != 8)
1246 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1247
1c73ef66
AK		 1248done:
1249 return rc;
1250}
1251
1252static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1253 struct operand *op)
1c73ef66 1254{
3e2815e9 1255 int rc = X86EMUL_CONTINUE;
1c73ef66 1256
2dbd0dd7 1257 op->type = OP_MEM;
9dac77fa 1258 switch (ctxt->ad_bytes) {
1c73ef66 1259 case 2:
e85a1085 1260 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1261 break;
1262 case 4:
e85a1085 1263 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1264 break;
1265 case 8:
e85a1085 1266 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1267 break;
1268 }
1269done:
1270 return rc;
1271}
1272
9dac77fa 1273static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1274{
7129eeca 1275 long sv = 0, mask;
35c843c4 1276
9dac77fa 1277 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1278 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1279
9dac77fa
AK		 1280 if (ctxt->src.bytes == 2)
1281 sv = (s16)ctxt->src.val & (s16)mask;
1282 else if (ctxt->src.bytes == 4)
1283 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1284 else
1285 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1286
1c1c35ae
NA		 1287 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1288 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1289 }
ba7ff2b7
WY		 1290
1291 /* only subword offset */
9dac77fa 1292 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1293}
1294
dde7e6d1 1295static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1296 unsigned long addr, void *dest, unsigned size)
6aa8b732 1297{
dde7e6d1 1298 int rc;
9dac77fa 1299 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1300
f23b070e
XG		 1301 if (mc->pos < mc->end)
1302 goto read_cached;
6aa8b732 1303
f23b070e
XG		 1304 WARN_ON((mc->end + size) >= sizeof(mc->data));
1305
1306 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1307 &ctxt->exception);
1308 if (rc != X86EMUL_CONTINUE)
1309 return rc;
1310
1311 mc->end += size;
1312
1313read_cached:
1314 memcpy(dest, mc->data + mc->pos, size);
1315 mc->pos += size;
dde7e6d1
AK		 1316 return X86EMUL_CONTINUE;
1317}
6aa8b732 1318
3ca3ac4d
AK		 1319static int segmented_read(struct x86_emulate_ctxt *ctxt,
1320 struct segmented_address addr,
1321 void *data,
1322 unsigned size)
1323{
9fa088f4
AK		 1324 int rc;
1325 ulong linear;
1326
83b8795a 1327 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1328 if (rc != X86EMUL_CONTINUE)
1329 return rc;
7b105ca2 1330 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1331}
1332
1333static int segmented_write(struct x86_emulate_ctxt *ctxt,
1334 struct segmented_address addr,
1335 const void *data,
1336 unsigned size)
1337{
9fa088f4
AK		 1338 int rc;
1339 ulong linear;
1340
83b8795a 1341 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1342 if (rc != X86EMUL_CONTINUE)
1343 return rc;
0f65dd70
AK		 1344 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1345 &ctxt->exception);
3ca3ac4d
AK		 1346}
1347
1348static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1349 struct segmented_address addr,
1350 const void *orig_data, const void *data,
1351 unsigned size)
1352{
9fa088f4
AK		 1353 int rc;
1354 ulong linear;
1355
83b8795a 1356 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
0f65dd70
AK		 1359 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1360 size, &ctxt->exception);
3ca3ac4d
AK		 1361}
1362
dde7e6d1 1363static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1364 unsigned int size, unsigned short port,
1365 void *dest)
1366{
9dac77fa 1367 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1368
dde7e6d1 1369 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1370 unsigned int in_page, n;
9dac77fa 1371 unsigned int count = ctxt->rep_prefix ?
dd856efa 1372 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1373 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1374 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1375 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1376 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1377 if (n == 0)
1378 n = 1;
1379 rc->pos = rc->end = 0;
7b105ca2 1380 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1381 return 0;
1382 rc->end = n * size;
6aa8b732
AK		 1383 }
1384
e6e39f04
NA		 1385 if (ctxt->rep_prefix && (ctxt->d & String) &&
1386 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1387 ctxt->dst.data = rc->data + rc->pos;
1388 ctxt->dst.type = OP_MEM_STR;
1389 ctxt->dst.count = (rc->end - rc->pos) / size;
1390 rc->pos = rc->end;
1391 } else {
1392 memcpy(dest, rc->data + rc->pos, size);
1393 rc->pos += size;
1394 }
dde7e6d1
AK		 1395 return 1;
1396}
6aa8b732 1397
7f3d35fd
KW		 1398static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1399 u16 index, struct desc_struct *desc)
1400{
1401 struct desc_ptr dt;
1402 ulong addr;
1403
1404 ctxt->ops->get_idt(ctxt, &dt);
1405
1406 if (dt.size < index * 8 + 7)
1407 return emulate_gp(ctxt, index << 3 | 0x2);
1408
1409 addr = dt.address + index * 8;
1410 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1411 &ctxt->exception);
1412}
1413
dde7e6d1 1414static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1415 u16 selector, struct desc_ptr *dt)
1416{
0225fb50 1417 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1418 u32 base3 = 0;
7b105ca2 1419
dde7e6d1
AK		 1420 if (selector & 1 << 2) {
1421 struct desc_struct desc;
1aa36616
AK		 1422 u16 sel;
1423
dde7e6d1 1424 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1425 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1426 VCPU_SREG_LDTR))
dde7e6d1 1427 return;
e09d082c 1428
dde7e6d1 1429 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1430 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1431 } else
4bff1e86 1432 ops->get_gdt(ctxt, dt);
dde7e6d1 1433}
120df890 1434
dde7e6d1
AK		 1435/* allowed just for 8 bytes segments */
1436static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1437 u16 selector, struct desc_struct *desc,
1438 ulong *desc_addr_p)
dde7e6d1
AK		 1439{
1440 struct desc_ptr dt;
1441 u16 index = selector >> 3;
dde7e6d1 1442 ulong addr;
120df890 1443
7b105ca2 1444 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1445
35d3d4a1
AK		 1446 if (dt.size < index * 8 + 7)
1447 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1448
e919464b 1449 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1450 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1451 &ctxt->exception);
dde7e6d1 1452}
ef65c889 1453
dde7e6d1
AK		 1454/* allowed just for 8 bytes segments */
1455static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1456 u16 selector, struct desc_struct *desc)
1457{
1458 struct desc_ptr dt;
1459 u16 index = selector >> 3;
dde7e6d1 1460 ulong addr;
6aa8b732 1461
7b105ca2 1462 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1463
35d3d4a1
AK		 1464 if (dt.size < index * 8 + 7)
1465 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1466
dde7e6d1 1467 addr = dt.address + index * 8;
7b105ca2
TY		 1468 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1469 &ctxt->exception);
dde7e6d1 1470}
c7e75a3d 1471
5601d05b 1472/* Does not support long mode */
2356aaeb 1473static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1474 u16 selector, int seg, u8 cpl,
1475 bool in_task_switch,
1476 struct desc_struct *desc)
dde7e6d1 1477{
869be99c 1478 struct desc_struct seg_desc, old_desc;
2356aaeb 1479 u8 dpl, rpl;
dde7e6d1
AK		 1480 unsigned err_vec = GP_VECTOR;
1481 u32 err_code = 0;
1482 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1483 ulong desc_addr;
dde7e6d1 1484 int ret;
03ebebeb 1485 u16 dummy;
e37a75a1 1486 u32 base3 = 0;
69f55cb1 1487
dde7e6d1 1488 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1489
f8da94e9
KW		 1490 if (ctxt->mode == X86EMUL_MODE_REAL) {
1491 /* set real mode segment descriptor (keep limit etc. for
1492 * unreal mode) */
03ebebeb 1493 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1494 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1495 goto load;
f8da94e9
KW		 1496 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1497 /* VM86 needs a clean new segment descriptor */
1498 set_desc_base(&seg_desc, selector << 4);
1499 set_desc_limit(&seg_desc, 0xffff);
1500 seg_desc.type = 3;
1501 seg_desc.p = 1;
1502 seg_desc.s = 1;
1503 seg_desc.dpl = 3;
1504 goto load;
dde7e6d1
AK		 1505 }
1506
79d5b4c3 1507 rpl = selector & 3;
79d5b4c3
AK		 1508
1509 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1510 if ((seg == VCPU_SREG_CS
1511 || (seg == VCPU_SREG_SS
1512 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1513 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1514 && null_selector)
1515 goto exception;
1516
1517 /* TR should be in GDT only */
1518 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1519 goto exception;
1520
1521 if (null_selector) /* for NULL selector skip all following checks */
1522 goto load;
1523
e919464b 1524 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1525 if (ret != X86EMUL_CONTINUE)
1526 return ret;
1527
1528 err_code = selector & 0xfffc;
15fc0752 1529 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1530
fc058680 1531 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1532 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1533 goto exception;
1534
1535 if (!seg_desc.p) {
1536 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1537 goto exception;
1538 }
1539
dde7e6d1 1540 dpl = seg_desc.dpl;
dde7e6d1
AK		 1541
1542 switch (seg) {
1543 case VCPU_SREG_SS:
1544 /*
1545 * segment is not a writable data segment or segment
1546 * selector's RPL != CPL or segment selector's RPL != CPL
1547 */
1548 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1549 goto exception;
6aa8b732 1550 break;
dde7e6d1
AK		 1551 case VCPU_SREG_CS:
1552 if (!(seg_desc.type & 8))
1553 goto exception;
1554
1555 if (seg_desc.type & 4) {
1556 /* conforming */
1557 if (dpl > cpl)
1558 goto exception;
1559 } else {
1560 /* nonconforming */
1561 if (rpl > cpl || dpl != cpl)
1562 goto exception;
1563 }
040c8dc8
NA		 1564 /* in long-mode d/b must be clear if l is set */
1565 if (seg_desc.d && seg_desc.l) {
1566 u64 efer = 0;
1567
1568 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1569 if (efer & EFER_LMA)
1570 goto exception;
1571 }
1572
dde7e6d1
AK		 1573 /* CS(RPL) <- CPL */
1574 selector = (selector & 0xfffc) | cpl;
6aa8b732 1575 break;
dde7e6d1
AK		 1576 case VCPU_SREG_TR:
1577 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1578 goto exception;
869be99c
AK		 1579 old_desc = seg_desc;
1580 seg_desc.type |= 2; /* busy */
1581 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1582 sizeof(seg_desc), &ctxt->exception);
1583 if (ret != X86EMUL_CONTINUE)
1584 return ret;
dde7e6d1
AK		 1585 break;
1586 case VCPU_SREG_LDTR:
1587 if (seg_desc.s || seg_desc.type != 2)
1588 goto exception;
1589 break;
1590 default: /* DS, ES, FS, or GS */
4e62417b 1591 /*
dde7e6d1
AK		 1592 * segment is not a data or readable code segment or
1593 * ((segment is a data or nonconforming code segment)
1594 * and (both RPL and CPL > DPL))
4e62417b 1595 */
dde7e6d1
AK		 1596 if ((seg_desc.type & 0xa) == 0x8 ||
1597 (((seg_desc.type & 0xc) != 0xc) &&
1598 (rpl > dpl && cpl > dpl)))
1599 goto exception;
6aa8b732 1600 break;
dde7e6d1
AK		 1601 }
1602
1603 if (seg_desc.s) {
1604 /* mark segment as accessed */
1605 seg_desc.type |= 1;
7b105ca2 1606 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1607 if (ret != X86EMUL_CONTINUE)
1608 return ret;
e37a75a1
NA		 1609 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1610 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1611 sizeof(base3), &ctxt->exception);
1612 if (ret != X86EMUL_CONTINUE)
1613 return ret;
9a9abf6b
NA		 1614 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1615 ((u64)base3 << 32)))
1616 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1617 }
1618load:
e37a75a1 1619 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1620 if (desc)
1621 *desc = seg_desc;
dde7e6d1
AK		 1622 return X86EMUL_CONTINUE;
1623exception:
592f0858 1624 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1625}
1626
2356aaeb
PB		 1627static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1628 u16 selector, int seg)
1629{
1630 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1631 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1632}
1633
31be40b3
WY		 1634static void write_register_operand(struct operand *op)
1635{
1636 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1637 switch (op->bytes) {
1638 case 1:
1639 *(u8 *)op->addr.reg = (u8)op->val;
1640 break;
1641 case 2:
1642 *(u16 *)op->addr.reg = (u16)op->val;
1643 break;
1644 case 4:
1645 *op->addr.reg = (u32)op->val;
1646 break; /* 64b: zero-extend */
1647 case 8:
1648 *op->addr.reg = op->val;
1649 break;
1650 }
1651}
1652
fb32b1ed 1653static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1654{
fb32b1ed 1655 switch (op->type) {
dde7e6d1 1656 case OP_REG:
fb32b1ed 1657 write_register_operand(op);
6aa8b732 1658 break;
dde7e6d1 1659 case OP_MEM:
9dac77fa 1660 if (ctxt->lock_prefix)
f5f87dfb
PB		 1661 return segmented_cmpxchg(ctxt,
1662 op->addr.mem,
1663 &op->orig_val,
1664 &op->val,
1665 op->bytes);
1666 else
1667 return segmented_write(ctxt,
fb32b1ed 1668 op->addr.mem,
fb32b1ed
AK		 1669 &op->val,
1670 op->bytes);
a682e354 1671 break;
b3356bf0 1672 case OP_MEM_STR:
f5f87dfb
PB		 1673 return segmented_write(ctxt,
1674 op->addr.mem,
1675 op->data,
1676 op->bytes * op->count);
b3356bf0 1677 break;
1253791d 1678 case OP_XMM:
fb32b1ed 1679 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1680 break;
cbe2c9d3 1681 case OP_MM:
fb32b1ed 1682 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1683 break;
dde7e6d1
AK		 1684 case OP_NONE:
1685 /* no writeback */
414e6277 1686 break;
dde7e6d1 1687 default:
414e6277 1688 break;
6aa8b732 1689 }
dde7e6d1
AK		 1690 return X86EMUL_CONTINUE;
1691}
6aa8b732 1692
51ddff50 1693static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1694{
4179bb02 1695 struct segmented_address addr;
0dc8d10f 1696
5ad105e5 1697 rsp_increment(ctxt, -bytes);
dd856efa 1698 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1699 addr.seg = VCPU_SREG_SS;
1700
51ddff50
AK		 1701 return segmented_write(ctxt, addr, data, bytes);
1702}
1703
1704static int em_push(struct x86_emulate_ctxt *ctxt)
1705{
4179bb02 1706 /* Disable writeback. */
9dac77fa 1707 ctxt->dst.type = OP_NONE;
51ddff50 1708 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1709}
69f55cb1 1710
dde7e6d1 1711static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1712 void *dest, int len)
1713{
dde7e6d1 1714 int rc;
90de84f5 1715 struct segmented_address addr;
8b4caf66 1716
dd856efa 1717 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1718 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1719 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1720 if (rc != X86EMUL_CONTINUE)
1721 return rc;
1722
5ad105e5 1723 rsp_increment(ctxt, len);
dde7e6d1 1724 return rc;
8b4caf66
LV		 1725}
1726
c54fe504
TY		 1727static int em_pop(struct x86_emulate_ctxt *ctxt)
1728{
9dac77fa 1729 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1730}
1731
dde7e6d1 1732static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1733 void *dest, int len)
9de41573
GN		 1734{
1735 int rc;
dde7e6d1
AK		 1736 unsigned long val, change_mask;
1737 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1738 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1739
3b9be3bf 1740 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1741 if (rc != X86EMUL_CONTINUE)
1742 return rc;
9de41573 1743
dde7e6d1 1744 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1745 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1746
dde7e6d1
AK		 1747 switch(ctxt->mode) {
1748 case X86EMUL_MODE_PROT64:
1749 case X86EMUL_MODE_PROT32:
1750 case X86EMUL_MODE_PROT16:
1751 if (cpl == 0)
1752 change_mask |= EFLG_IOPL;
1753 if (cpl <= iopl)
1754 change_mask |= EFLG_IF;
1755 break;
1756 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1757 if (iopl < 3)
1758 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1759 change_mask |= EFLG_IF;
1760 break;
1761 default: /* real mode */
1762 change_mask |= (EFLG_IOPL | EFLG_IF);
1763 break;
9de41573 1764 }
dde7e6d1
AK		 1765
1766 *(unsigned long *)dest =
1767 (ctxt->eflags & ~change_mask) | (val & change_mask);
1768
1769 return rc;
9de41573
GN		 1770}
1771
62aaa2f0
TY		 1772static int em_popf(struct x86_emulate_ctxt *ctxt)
1773{
9dac77fa
AK		 1774 ctxt->dst.type = OP_REG;
1775 ctxt->dst.addr.reg = &ctxt->eflags;
1776 ctxt->dst.bytes = ctxt->op_bytes;
1777 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1778}
1779
612e89f0
AK		 1780static int em_enter(struct x86_emulate_ctxt *ctxt)
1781{
1782 int rc;
1783 unsigned frame_size = ctxt->src.val;
1784 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1785 ulong rbp;
612e89f0
AK		 1786
1787 if (nesting_level)
1788 return X86EMUL_UNHANDLEABLE;
1789
dd856efa
AK		 1790 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1791 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1792 if (rc != X86EMUL_CONTINUE)
1793 return rc;
dd856efa 1794 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1795 stack_mask(ctxt));
dd856efa
AK		 1796 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1797 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1798 stack_mask(ctxt));
1799 return X86EMUL_CONTINUE;
1800}
1801
f47cfa31
AK		 1802static int em_leave(struct x86_emulate_ctxt *ctxt)
1803{
dd856efa 1804 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1805 stack_mask(ctxt));
dd856efa 1806 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1807}
1808
1cd196ea 1809static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1810{
1cd196ea
AK		 1811 int seg = ctxt->src2.val;
1812
9dac77fa 1813 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1814 if (ctxt->op_bytes == 4) {
1815 rsp_increment(ctxt, -2);
1816 ctxt->op_bytes = 2;
1817 }
7b262e90 1818
4487b3b4 1819 return em_push(ctxt);
7b262e90
GN		 1820}
1821
1cd196ea 1822static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1823{
1cd196ea 1824 int seg = ctxt->src2.val;
dde7e6d1
AK		 1825 unsigned long selector;
1826 int rc;
38ba30ba 1827
3313bc4e 1828 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1829 if (rc != X86EMUL_CONTINUE)
1830 return rc;
1831
a5457e7b
PB		 1832 if (ctxt->modrm_reg == VCPU_SREG_SS)
1833 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1834 if (ctxt->op_bytes > 2)
1835 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1836
7b105ca2 1837 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1838 return rc;
38ba30ba
GN		 1839}
1840
b96a7fad 1841static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1842{
dd856efa 1843 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1844 int rc = X86EMUL_CONTINUE;
1845 int reg = VCPU_REGS_RAX;
38ba30ba 1846
dde7e6d1
AK		 1847 while (reg <= VCPU_REGS_RDI) {
1848 (reg == VCPU_REGS_RSP) ?
dd856efa 1849 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1850
4487b3b4 1851 rc = em_push(ctxt);
dde7e6d1
AK		 1852 if (rc != X86EMUL_CONTINUE)
1853 return rc;
38ba30ba 1854
dde7e6d1 1855 ++reg;
38ba30ba 1856 }
38ba30ba 1857
dde7e6d1 1858 return rc;
38ba30ba
GN		 1859}
1860
62aaa2f0
TY		 1861static int em_pushf(struct x86_emulate_ctxt *ctxt)
1862{
bc397a6c 1863 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1864 return em_push(ctxt);
1865}
1866
b96a7fad 1867static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1868{
dde7e6d1
AK		 1869 int rc = X86EMUL_CONTINUE;
1870 int reg = VCPU_REGS_RDI;
38ba30ba 1871
dde7e6d1
AK		 1872 while (reg >= VCPU_REGS_RAX) {
1873 if (reg == VCPU_REGS_RSP) {
5ad105e5 1874 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1875 --reg;
1876 }
38ba30ba 1877
dd856efa 1878 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1879 if (rc != X86EMUL_CONTINUE)
1880 break;
1881 --reg;
38ba30ba 1882 }
dde7e6d1 1883 return rc;
38ba30ba
GN		 1884}
1885
dd856efa 1886static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1887{
0225fb50 1888 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1889 int rc;
6e154e56
MG		 1890 struct desc_ptr dt;
1891 gva_t cs_addr;
1892 gva_t eip_addr;
1893 u16 cs, eip;
6e154e56
MG		 1894
1895 /* TODO: Add limit checks */
9dac77fa 1896 ctxt->src.val = ctxt->eflags;
4487b3b4 1897 rc = em_push(ctxt);
5c56e1cf
AK		 1898 if (rc != X86EMUL_CONTINUE)
1899 return rc;
6e154e56
MG		 1900
1901 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1902
9dac77fa 1903 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1904 rc = em_push(ctxt);
5c56e1cf
AK		 1905 if (rc != X86EMUL_CONTINUE)
1906 return rc;
6e154e56 1907
9dac77fa 1908 ctxt->src.val = ctxt->_eip;
4487b3b4 1909 rc = em_push(ctxt);
5c56e1cf
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
4bff1e86 1913 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1914
1915 eip_addr = dt.address + (irq << 2);
1916 cs_addr = dt.address + (irq << 2) + 2;
1917
0f65dd70 1918 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1919 if (rc != X86EMUL_CONTINUE)
1920 return rc;
1921
0f65dd70 1922 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1923 if (rc != X86EMUL_CONTINUE)
1924 return rc;
1925
7b105ca2 1926 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1927 if (rc != X86EMUL_CONTINUE)
1928 return rc;
1929
9dac77fa 1930 ctxt->_eip = eip;
6e154e56
MG		 1931
1932 return rc;
1933}
1934
dd856efa
AK		 1935int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1936{
1937 int rc;
1938
1939 invalidate_registers(ctxt);
1940 rc = __emulate_int_real(ctxt, irq);
1941 if (rc == X86EMUL_CONTINUE)
1942 writeback_registers(ctxt);
1943 return rc;
1944}
1945
7b105ca2 1946static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1947{
1948 switch(ctxt->mode) {
1949 case X86EMUL_MODE_REAL:
dd856efa 1950 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1951 case X86EMUL_MODE_VM86:
1952 case X86EMUL_MODE_PROT16:
1953 case X86EMUL_MODE_PROT32:
1954 case X86EMUL_MODE_PROT64:
1955 default:
1956 /* Protected mode interrupts unimplemented yet */
1957 return X86EMUL_UNHANDLEABLE;
1958 }
1959}
1960
7b105ca2 1961static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1962{
dde7e6d1
AK		 1963 int rc = X86EMUL_CONTINUE;
1964 unsigned long temp_eip = 0;
1965 unsigned long temp_eflags = 0;
1966 unsigned long cs = 0;
1967 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1968 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1969 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1970 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1971
dde7e6d1 1972 /* TODO: Add stack limit check */
38ba30ba 1973
9dac77fa 1974 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1975
dde7e6d1
AK		 1976 if (rc != X86EMUL_CONTINUE)
1977 return rc;
38ba30ba 1978
35d3d4a1
AK		 1979 if (temp_eip & ~0xffff)
1980 return emulate_gp(ctxt, 0);
38ba30ba 1981
9dac77fa 1982 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1983
dde7e6d1
AK		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
38ba30ba 1986
9dac77fa 1987 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1988
dde7e6d1
AK		 1989 if (rc != X86EMUL_CONTINUE)
1990 return rc;
38ba30ba 1991
7b105ca2 1992 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1993
dde7e6d1
AK		 1994 if (rc != X86EMUL_CONTINUE)
1995 return rc;
38ba30ba 1996
9dac77fa 1997 ctxt->_eip = temp_eip;
38ba30ba 1998
38ba30ba 1999
9dac77fa 2000 if (ctxt->op_bytes == 4)
dde7e6d1 2001 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2002 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2003 ctxt->eflags &= ~0xffff;
2004 ctxt->eflags |= temp_eflags;
38ba30ba 2005 }
dde7e6d1
AK		 2006
2007 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2008 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2009
2010 return rc;
38ba30ba
GN		 2011}
2012
e01991e7 2013static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2014{
dde7e6d1
AK		 2015 switch(ctxt->mode) {
2016 case X86EMUL_MODE_REAL:
7b105ca2 2017 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2018 case X86EMUL_MODE_VM86:
2019 case X86EMUL_MODE_PROT16:
2020 case X86EMUL_MODE_PROT32:
2021 case X86EMUL_MODE_PROT64:
c37eda13 2022 default:
dde7e6d1
AK		 2023 /* iret from protected mode unimplemented yet */
2024 return X86EMUL_UNHANDLEABLE;
c37eda13 2025 }
c37eda13
WY		 2026}
2027
d2f62766
TY		 2028static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2029{
d2f62766 2030 int rc;
d1442d85
NA		 2031 unsigned short sel, old_sel;
2032 struct desc_struct old_desc, new_desc;
2033 const struct x86_emulate_ops *ops = ctxt->ops;
2034 u8 cpl = ctxt->ops->cpl(ctxt);
2035
2036 /* Assignment of RIP may only fail in 64-bit mode */
2037 if (ctxt->mode == X86EMUL_MODE_PROT64)
2038 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2039 VCPU_SREG_CS);
d2f62766 2040
9dac77fa 2041 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2042
d1442d85
NA		 2043 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2044 &new_desc);
d2f62766
TY		 2045 if (rc != X86EMUL_CONTINUE)
2046 return rc;
2047
d50eaa18 2048 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2049 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2050 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2051 /* assigning eip failed; restore the old cs */
2052 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2053 return rc;
2054 }
2055 return rc;
d2f62766
TY		 2056}
2057
f7784046 2058static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2059{
f7784046
NA		 2060 return assign_eip_near(ctxt, ctxt->src.val);
2061}
8cdbd2c9 2062
f7784046
NA		 2063static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2064{
2065 int rc;
2066 long int old_eip;
2067
2068 old_eip = ctxt->_eip;
2069 rc = assign_eip_near(ctxt, ctxt->src.val);
2070 if (rc != X86EMUL_CONTINUE)
2071 return rc;
2072 ctxt->src.val = old_eip;
2073 rc = em_push(ctxt);
4179bb02 2074 return rc;
8cdbd2c9
LV		 2075}
2076
e0dac408 2077static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2078{
9dac77fa 2079 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2080
aaa05f24
NA		 2081 if (ctxt->dst.bytes == 16)
2082 return X86EMUL_UNHANDLEABLE;
2083
dd856efa
AK		 2084 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2085 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2086 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2087 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2088 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2089 } else {
dd856efa
AK		 2090 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2091 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2092
05f086f8 2093 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2094 }
1b30eaa8 2095 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2096}
2097
ebda02c2
TY		 2098static int em_ret(struct x86_emulate_ctxt *ctxt)
2099{
234f3ce4
NA		 2100 int rc;
2101 unsigned long eip;
2102
2103 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2104 if (rc != X86EMUL_CONTINUE)
2105 return rc;
2106
2107 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2108}
2109
e01991e7 2110static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2111{
a77ab5ea 2112 int rc;
d1442d85
NA		 2113 unsigned long eip, cs;
2114 u16 old_cs;
9e8919ae 2115 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2116 struct desc_struct old_desc, new_desc;
2117 const struct x86_emulate_ops *ops = ctxt->ops;
2118
2119 if (ctxt->mode == X86EMUL_MODE_PROT64)
2120 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2121 VCPU_SREG_CS);
a77ab5ea 2122
d1442d85 2123 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2124 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2125 return rc;
9dac77fa 2126 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2127 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2128 return rc;
9e8919ae
NA		 2129 /* Outer-privilege level return is not implemented */
2130 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2131 return X86EMUL_UNHANDLEABLE;
ab646f54 2132 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, false,
d1442d85
NA		 2133 &new_desc);
2134 if (rc != X86EMUL_CONTINUE)
2135 return rc;
d50eaa18 2136 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2137 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2138 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2139 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2140 }
a77ab5ea
AK		 2141 return rc;
2142}
2143
3261107e
BR		 2144static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2145{
2146 int rc;
2147
2148 rc = em_ret_far(ctxt);
2149 if (rc != X86EMUL_CONTINUE)
2150 return rc;
2151 rsp_increment(ctxt, ctxt->src.val);
2152 return X86EMUL_CONTINUE;
2153}
2154
e940b5c2
TY		 2155static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2156{
2157 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2158 ctxt->dst.orig_val = ctxt->dst.val;
2159 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2160 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2161 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2162 fastop(ctxt, em_cmp);
e940b5c2
TY		 2163
2164 if (ctxt->eflags & EFLG_ZF) {
2165 /* Success: write back to memory. */
2166 ctxt->dst.val = ctxt->src.orig_val;
2167 } else {
2168 /* Failure: write the value we saw to EAX. */
2169 ctxt->dst.type = OP_REG;
dd856efa 2170 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2171 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2172 }
2173 return X86EMUL_CONTINUE;
2174}
2175
d4b4325f 2176static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2177{
d4b4325f 2178 int seg = ctxt->src2.val;
09b5f4d3
WY		 2179 unsigned short sel;
2180 int rc;
2181
9dac77fa 2182 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2183
7b105ca2 2184 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2185 if (rc != X86EMUL_CONTINUE)
2186 return rc;
2187
9dac77fa 2188 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2189 return rc;
2190}
2191
7b105ca2 2192static void
e66bb2cc 2193setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2194 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2195{
e66bb2cc 2196 cs->l = 0; /* will be adjusted later */
79168fd1 2197 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2198 cs->g = 1; /* 4kb granularity */
79168fd1 2199 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2200 cs->type = 0x0b; /* Read, Execute, Accessed */
2201 cs->s = 1;
2202 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2203 cs->p = 1;
2204 cs->d = 1;
99245b50 2205 cs->avl = 0;
e66bb2cc 2206
79168fd1
GN		 2207 set_desc_base(ss, 0); /* flat segment */
2208 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2209 ss->g = 1; /* 4kb granularity */
2210 ss->s = 1;
2211 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2212 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2213 ss->dpl = 0;
79168fd1 2214 ss->p = 1;
99245b50
GN		 2215 ss->l = 0;
2216 ss->avl = 0;
e66bb2cc
AP		 2217}
2218
1a18a69b
AK		 2219static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2220{
2221 u32 eax, ebx, ecx, edx;
2222
2223 eax = ecx = 0;
0017f93a
AK		 2224 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2225 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2226 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2227 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2228}
2229
c2226fc9
SB		 2230static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2231{
0225fb50 2232 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2233 u32 eax, ebx, ecx, edx;
2234
2235 /*
2236 * syscall should always be enabled in longmode - so only become
2237 * vendor specific (cpuid) if other modes are active...
2238 */
2239 if (ctxt->mode == X86EMUL_MODE_PROT64)
2240 return true;
2241
2242 eax = 0x00000000;
2243 ecx = 0x00000000;
0017f93a
AK		 2244 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2245 /*
2246 * Intel ("GenuineIntel")
2247 * remark: Intel CPUs only support "syscall" in 64bit
2248 * longmode. Also an 64bit guest with a
2249 * 32bit compat-app running will #UD !! While this
2250 * behaviour can be fixed (by emulating) into AMD
2251 * response - CPUs of AMD can't behave like Intel.
2252 */
2253 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2254 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2255 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2256 return false;
2257
2258 /* AMD ("AuthenticAMD") */
2259 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2260 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2261 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2262 return true;
2263
2264 /* AMD ("AMDisbetter!") */
2265 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2266 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2267 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2268 return true;
c2226fc9
SB		 2269
2270 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2271 return false;
2272}
2273
e01991e7 2274static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2275{
0225fb50 2276 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2277 struct desc_struct cs, ss;
e66bb2cc 2278 u64 msr_data;
79168fd1 2279 u16 cs_sel, ss_sel;
c2ad2bb3 2280 u64 efer = 0;
e66bb2cc
AP		 2281
2282 /* syscall is not available in real mode */
2e901c4c 2283 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2284 ctxt->mode == X86EMUL_MODE_VM86)
2285 return emulate_ud(ctxt);
e66bb2cc 2286
c2226fc9
SB		 2287 if (!(em_syscall_is_enabled(ctxt)))
2288 return emulate_ud(ctxt);
2289
c2ad2bb3 2290 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2291 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2292
c2226fc9
SB		 2293 if (!(efer & EFER_SCE))
2294 return emulate_ud(ctxt);
2295
717746e3 2296 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2297 msr_data >>= 32;
79168fd1
GN		 2298 cs_sel = (u16)(msr_data & 0xfffc);
2299 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2300
c2ad2bb3 2301 if (efer & EFER_LMA) {
79168fd1 2302 cs.d = 0;
e66bb2cc
AP		 2303 cs.l = 1;
2304 }
1aa36616
AK		 2305 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2306 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2307
dd856efa 2308 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2309 if (efer & EFER_LMA) {
e66bb2cc 2310#ifdef CONFIG_X86_64
6c6cb69b 2311 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2312
717746e3 2313 ops->get_msr(ctxt,
3fb1b5db
GN		 2314 ctxt->mode == X86EMUL_MODE_PROT64 ?
2315 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2316 ctxt->_eip = msr_data;
e66bb2cc 2317
717746e3 2318 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2319 ctxt->eflags &= ~msr_data;
807c1425 2320 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2321#endif
2322 } else {
2323 /* legacy mode */
717746e3 2324 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2325 ctxt->_eip = (u32)msr_data;
e66bb2cc 2326
6c6cb69b 2327 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2328 }
2329
e54cfa97 2330 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2331}
2332
e01991e7 2333static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2334{
0225fb50 2335 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2336 struct desc_struct cs, ss;
8c604352 2337 u64 msr_data;
79168fd1 2338 u16 cs_sel, ss_sel;
c2ad2bb3 2339 u64 efer = 0;
8c604352 2340
7b105ca2 2341 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2342 /* inject #GP if in real mode */
35d3d4a1
AK		 2343 if (ctxt->mode == X86EMUL_MODE_REAL)
2344 return emulate_gp(ctxt, 0);
8c604352 2345
1a18a69b
AK		 2346 /*
2347 * Not recognized on AMD in compat mode (but is recognized in legacy
2348 * mode).
2349 */
2350 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2351 && !vendor_intel(ctxt))
2352 return emulate_ud(ctxt);
2353
b2c9d43e 2354 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2355 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2356 return X86EMUL_UNHANDLEABLE;
8c604352 2357
7b105ca2 2358 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2359
717746e3 2360 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2361 switch (ctxt->mode) {
2362 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2363 if ((msr_data & 0xfffc) == 0x0)
2364 return emulate_gp(ctxt, 0);
8c604352
AP		 2365 break;
2366 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2367 if (msr_data == 0x0)
2368 return emulate_gp(ctxt, 0);
8c604352 2369 break;
9d1b39a9
GN		 2370 default:
2371 break;
8c604352
AP		 2372 }
2373
6c6cb69b 2374 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2375 cs_sel = (u16)msr_data;
2376 cs_sel &= ~SELECTOR_RPL_MASK;
2377 ss_sel = cs_sel + 8;
2378 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2379 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2380 cs.d = 0;
8c604352
AP		 2381 cs.l = 1;
2382 }
2383
1aa36616
AK		 2384 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2385 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2386
717746e3 2387 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2388 ctxt->_eip = msr_data;
8c604352 2389
717746e3 2390 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2391 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2392
e54cfa97 2393 return X86EMUL_CONTINUE;
8c604352
AP		 2394}
2395
e01991e7 2396static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2397{
0225fb50 2398 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2399 struct desc_struct cs, ss;
234f3ce4 2400 u64 msr_data, rcx, rdx;
4668f050 2401 int usermode;
1249b96e 2402 u16 cs_sel = 0, ss_sel = 0;
4668f050 2403
a0044755
GN		 2404 /* inject #GP if in real mode or Virtual 8086 mode */
2405 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2406 ctxt->mode == X86EMUL_MODE_VM86)
2407 return emulate_gp(ctxt, 0);
4668f050 2408
7b105ca2 2409 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2410
9dac77fa 2411 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2412 usermode = X86EMUL_MODE_PROT64;
2413 else
2414 usermode = X86EMUL_MODE_PROT32;
2415
234f3ce4
NA		 2416 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2417 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2418
4668f050
AP		 2419 cs.dpl = 3;
2420 ss.dpl = 3;
717746e3 2421 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2422 switch (usermode) {
2423 case X86EMUL_MODE_PROT32:
79168fd1 2424 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2425 if ((msr_data & 0xfffc) == 0x0)
2426 return emulate_gp(ctxt, 0);
79168fd1 2427 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2428 rcx = (u32)rcx;
2429 rdx = (u32)rdx;
4668f050
AP		 2430 break;
2431 case X86EMUL_MODE_PROT64:
79168fd1 2432 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2433 if (msr_data == 0x0)
2434 return emulate_gp(ctxt, 0);
79168fd1
GN		 2435 ss_sel = cs_sel + 8;
2436 cs.d = 0;
4668f050 2437 cs.l = 1;
234f3ce4
NA		 2438 if (is_noncanonical_address(rcx) ||
2439 is_noncanonical_address(rdx))
2440 return emulate_gp(ctxt, 0);
4668f050
AP		 2441 break;
2442 }
79168fd1
GN		 2443 cs_sel |= SELECTOR_RPL_MASK;
2444 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2445
1aa36616
AK		 2446 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2447 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2448
234f3ce4
NA		 2449 ctxt->_eip = rdx;
2450 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2451
e54cfa97 2452 return X86EMUL_CONTINUE;
4668f050
AP		 2453}
2454
7b105ca2 2455static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2456{
2457 int iopl;
2458 if (ctxt->mode == X86EMUL_MODE_REAL)
2459 return false;
2460 if (ctxt->mode == X86EMUL_MODE_VM86)
2461 return true;
2462 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2463 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2464}
2465
2466static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2467 u16 port, u16 len)
2468{
0225fb50 2469 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2470 struct desc_struct tr_seg;
5601d05b 2471 u32 base3;
f850e2e6 2472 int r;
1aa36616 2473 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2474 unsigned mask = (1 << len) - 1;
5601d05b 2475 unsigned long base;
f850e2e6 2476
1aa36616 2477 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2478 if (!tr_seg.p)
f850e2e6 2479 return false;
79168fd1 2480 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2481 return false;
5601d05b
GN		 2482 base = get_desc_base(&tr_seg);
2483#ifdef CONFIG_X86_64
2484 base |= ((u64)base3) << 32;
2485#endif
0f65dd70 2486 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2487 if (r != X86EMUL_CONTINUE)
2488 return false;
79168fd1 2489 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2490 return false;
0f65dd70 2491 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2492 if (r != X86EMUL_CONTINUE)
2493 return false;
2494 if ((perm >> bit_idx) & mask)
2495 return false;
2496 return true;
2497}
2498
2499static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2500 u16 port, u16 len)
2501{
4fc40f07
GN		 2502 if (ctxt->perm_ok)
2503 return true;
2504
7b105ca2
TY		 2505 if (emulator_bad_iopl(ctxt))
2506 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2507 return false;
4fc40f07
GN		 2508
2509 ctxt->perm_ok = true;
2510
f850e2e6
GN		 2511 return true;
2512}
2513
38ba30ba 2514static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2515 struct tss_segment_16 *tss)
2516{
9dac77fa 2517 tss->ip = ctxt->_eip;
38ba30ba 2518 tss->flag = ctxt->eflags;
dd856efa
AK		 2519 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2520 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2521 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2522 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2523 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2524 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2525 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2526 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2527
1aa36616
AK		 2528 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2529 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2530 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2531 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2532 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2533}
2534
2535static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2536 struct tss_segment_16 *tss)
2537{
38ba30ba 2538 int ret;
2356aaeb 2539 u8 cpl;
38ba30ba 2540
9dac77fa 2541 ctxt->_eip = tss->ip;
38ba30ba 2542 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2543 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2544 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2545 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2546 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2547 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2548 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2549 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2550 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2551
2552 /*
2553 * SDM says that segment selectors are loaded before segment
2554 * descriptors
2555 */
1aa36616
AK		 2556 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2557 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2558 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2559 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2560 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2561
2356aaeb
PB		 2562 cpl = tss->cs & 3;
2563
38ba30ba 2564 /*
fc058680 2565 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2566 * it is handled in a context of new task
2567 */
d1442d85
NA		 2568 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2569 true, NULL);
38ba30ba
GN		 2570 if (ret != X86EMUL_CONTINUE)
2571 return ret;
d1442d85
NA		 2572 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2573 true, NULL);
38ba30ba
GN		 2574 if (ret != X86EMUL_CONTINUE)
2575 return ret;
d1442d85
NA		 2576 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2577 true, NULL);
38ba30ba
GN		 2578 if (ret != X86EMUL_CONTINUE)
2579 return ret;
d1442d85
NA		 2580 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2581 true, NULL);
38ba30ba
GN		 2582 if (ret != X86EMUL_CONTINUE)
2583 return ret;
d1442d85
NA		 2584 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2585 true, NULL);
38ba30ba
GN		 2586 if (ret != X86EMUL_CONTINUE)
2587 return ret;
2588
2589 return X86EMUL_CONTINUE;
2590}
2591
2592static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2593 u16 tss_selector, u16 old_tss_sel,
2594 ulong old_tss_base, struct desc_struct *new_desc)
2595{
0225fb50 2596 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2597 struct tss_segment_16 tss_seg;
2598 int ret;
bcc55cba 2599 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2600
0f65dd70 2601 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2602 &ctxt->exception);
db297e3d 2603 if (ret != X86EMUL_CONTINUE)
38ba30ba 2604 return ret;
38ba30ba 2605
7b105ca2 2606 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2607
0f65dd70 2608 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2609 &ctxt->exception);
db297e3d 2610 if (ret != X86EMUL_CONTINUE)
38ba30ba 2611 return ret;
38ba30ba 2612
0f65dd70 2613 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2614 &ctxt->exception);
db297e3d 2615 if (ret != X86EMUL_CONTINUE)
38ba30ba 2616 return ret;
38ba30ba
GN		 2617
2618 if (old_tss_sel != 0xffff) {
2619 tss_seg.prev_task_link = old_tss_sel;
2620
0f65dd70 2621 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2622 &tss_seg.prev_task_link,
2623 sizeof tss_seg.prev_task_link,
0f65dd70 2624 &ctxt->exception);
db297e3d 2625 if (ret != X86EMUL_CONTINUE)
38ba30ba 2626 return ret;
38ba30ba
GN		 2627 }
2628
7b105ca2 2629 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2630}
2631
2632static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2633 struct tss_segment_32 *tss)
2634{
5c7411e2 2635 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2636 tss->eip = ctxt->_eip;
38ba30ba 2637 tss->eflags = ctxt->eflags;
dd856efa
AK		 2638 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2639 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2640 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2641 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2642 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2643 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2644 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2645 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2646
1aa36616
AK		 2647 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2648 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2649 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2650 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2651 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2652 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2653}
2654
2655static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2656 struct tss_segment_32 *tss)
2657{
38ba30ba 2658 int ret;
2356aaeb 2659 u8 cpl;
38ba30ba 2660
7b105ca2 2661 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2662 return emulate_gp(ctxt, 0);
9dac77fa 2663 ctxt->_eip = tss->eip;
38ba30ba 2664 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2665
2666 /* General purpose registers */
dd856efa
AK		 2667 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2668 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2669 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2670 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2671 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2672 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2673 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2674 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2675
2676 /*
2677 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2678 * descriptors. This is important because CPL checks will
2679 * use CS.RPL.
38ba30ba 2680 */
1aa36616
AK		 2681 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2682 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2683 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2684 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2685 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2686 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2687 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2688
4cee4798
KW		 2689 /*
2690 * If we're switching between Protected Mode and VM86, we need to make
2691 * sure to update the mode before loading the segment descriptors so
2692 * that the selectors are interpreted correctly.
4cee4798 2693 */
2356aaeb 2694 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2695 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2696 cpl = 3;
2697 } else {
4cee4798 2698 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2699 cpl = tss->cs & 3;
2700 }
4cee4798 2701
38ba30ba
GN		 2702 /*
2703 * Now load segment descriptors. If fault happenes at this stage
2704 * it is handled in a context of new task
2705 */
d1442d85
NA		 2706 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2707 cpl, true, NULL);
38ba30ba
GN		 2708 if (ret != X86EMUL_CONTINUE)
2709 return ret;
d1442d85
NA		 2710 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2711 true, NULL);
38ba30ba
GN		 2712 if (ret != X86EMUL_CONTINUE)
2713 return ret;
d1442d85
NA		 2714 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2715 true, NULL);
38ba30ba
GN		 2716 if (ret != X86EMUL_CONTINUE)
2717 return ret;
d1442d85
NA		 2718 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2719 true, NULL);
38ba30ba
GN		 2720 if (ret != X86EMUL_CONTINUE)
2721 return ret;
d1442d85
NA		 2722 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2723 true, NULL);
38ba30ba
GN		 2724 if (ret != X86EMUL_CONTINUE)
2725 return ret;
d1442d85
NA		 2726 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2727 true, NULL);
38ba30ba
GN		 2728 if (ret != X86EMUL_CONTINUE)
2729 return ret;
d1442d85
NA		 2730 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2731 true, NULL);
38ba30ba
GN		 2732 if (ret != X86EMUL_CONTINUE)
2733 return ret;
2734
2735 return X86EMUL_CONTINUE;
2736}
2737
2738static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2739 u16 tss_selector, u16 old_tss_sel,
2740 ulong old_tss_base, struct desc_struct *new_desc)
2741{
0225fb50 2742 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2743 struct tss_segment_32 tss_seg;
2744 int ret;
bcc55cba 2745 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2746 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2747 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2748
0f65dd70 2749 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2750 &ctxt->exception);
db297e3d 2751 if (ret != X86EMUL_CONTINUE)
38ba30ba 2752 return ret;
38ba30ba 2753
7b105ca2 2754 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2755
5c7411e2
NA		 2756 /* Only GP registers and segment selectors are saved */
2757 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2758 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2759 if (ret != X86EMUL_CONTINUE)
38ba30ba 2760 return ret;
38ba30ba 2761
0f65dd70 2762 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2763 &ctxt->exception);
db297e3d 2764 if (ret != X86EMUL_CONTINUE)
38ba30ba 2765 return ret;
38ba30ba
GN		 2766
2767 if (old_tss_sel != 0xffff) {
2768 tss_seg.prev_task_link = old_tss_sel;
2769
0f65dd70 2770 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2771 &tss_seg.prev_task_link,
2772 sizeof tss_seg.prev_task_link,
0f65dd70 2773 &ctxt->exception);
db297e3d 2774 if (ret != X86EMUL_CONTINUE)
38ba30ba 2775 return ret;
38ba30ba
GN		 2776 }
2777
7b105ca2 2778 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2779}
2780
2781static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2782 u16 tss_selector, int idt_index, int reason,
e269fb21 2783 bool has_error_code, u32 error_code)
38ba30ba 2784{
0225fb50 2785 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2786 struct desc_struct curr_tss_desc, next_tss_desc;
2787 int ret;
1aa36616 2788 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2789 ulong old_tss_base =
4bff1e86 2790 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2791 u32 desc_limit;
e919464b 2792 ulong desc_addr;
38ba30ba
GN		 2793
2794 /* FIXME: old_tss_base == ~0 ? */
2795
e919464b 2796 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2797 if (ret != X86EMUL_CONTINUE)
2798 return ret;
e919464b 2799 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2800 if (ret != X86EMUL_CONTINUE)
2801 return ret;
2802
2803 /* FIXME: check that next_tss_desc is tss */
2804
7f3d35fd
KW		 2805 /*
2806 * Check privileges. The three cases are task switch caused by...
2807 *
2808 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2809 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2810 * 3. jmp/call to TSS/task-gate: No check is performed since the
2811 * hardware checks it before exiting.
7f3d35fd
KW		 2812 */
2813 if (reason == TASK_SWITCH_GATE) {
2814 if (idt_index != -1) {
2815 /* Software interrupts */
2816 struct desc_struct task_gate_desc;
2817 int dpl;
2818
2819 ret = read_interrupt_descriptor(ctxt, idt_index,
2820 &task_gate_desc);
2821 if (ret != X86EMUL_CONTINUE)
2822 return ret;
2823
2824 dpl = task_gate_desc.dpl;
2825 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2826 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2827 }
38ba30ba
GN		 2828 }
2829
ceffb459
GN		 2830 desc_limit = desc_limit_scaled(&next_tss_desc);
2831 if (!next_tss_desc.p ||
2832 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2833 desc_limit < 0x2b)) {
592f0858 2834 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2835 }
2836
2837 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2838 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2839 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2840 }
2841
2842 if (reason == TASK_SWITCH_IRET)
2843 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2844
2845 /* set back link to prev task only if NT bit is set in eflags
fc058680 2846 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2847 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2848 old_tss_sel = 0xffff;
2849
2850 if (next_tss_desc.type & 8)
7b105ca2 2851 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2852 old_tss_base, &next_tss_desc);
2853 else
7b105ca2 2854 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2855 old_tss_base, &next_tss_desc);
0760d448
JK		 2856 if (ret != X86EMUL_CONTINUE)
2857 return ret;
38ba30ba
GN		 2858
2859 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2860 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2861
2862 if (reason != TASK_SWITCH_IRET) {
2863 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2864 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2865 }
2866
717746e3 2867 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2868 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2869
e269fb21 2870 if (has_error_code) {
9dac77fa
AK		 2871 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2872 ctxt->lock_prefix = 0;
2873 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2874 ret = em_push(ctxt);
e269fb21
JK		 2875 }
2876
38ba30ba
GN		 2877 return ret;
2878}
2879
2880int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2881 u16 tss_selector, int idt_index, int reason,
e269fb21 2882 bool has_error_code, u32 error_code)
38ba30ba 2883{
38ba30ba
GN		 2884 int rc;
2885
dd856efa 2886 invalidate_registers(ctxt);
9dac77fa
AK		 2887 ctxt->_eip = ctxt->eip;
2888 ctxt->dst.type = OP_NONE;
38ba30ba 2889
7f3d35fd 2890 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2891 has_error_code, error_code);
38ba30ba 2892
dd856efa 2893 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2894 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2895 writeback_registers(ctxt);
2896 }
38ba30ba 2897
a0c0ab2f 2898 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2899}
2900
f3bd64c6
GN		 2901static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2902 struct operand *op)
a682e354 2903{
b3356bf0 2904 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2905
01485a22
PB		 2906 register_address_increment(ctxt, reg, df * op->bytes);
2907 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2908}
2909
7af04fc0
AK		 2910static int em_das(struct x86_emulate_ctxt *ctxt)
2911{
7af04fc0
AK		 2912 u8 al, old_al;
2913 bool af, cf, old_cf;
2914
2915 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2916 al = ctxt->dst.val;
7af04fc0
AK		 2917
2918 old_al = al;
2919 old_cf = cf;
2920 cf = false;
2921 af = ctxt->eflags & X86_EFLAGS_AF;
2922 if ((al & 0x0f) > 9 || af) {
2923 al -= 6;
2924 cf = old_cf | (al >= 250);
2925 af = true;
2926 } else {
2927 af = false;
2928 }
2929 if (old_al > 0x99 || old_cf) {
2930 al -= 0x60;
2931 cf = true;
2932 }
2933
9dac77fa 2934 ctxt->dst.val = al;
7af04fc0 2935 /* Set PF, ZF, SF */
9dac77fa
AK		 2936 ctxt->src.type = OP_IMM;
2937 ctxt->src.val = 0;
2938 ctxt->src.bytes = 1;
158de57f 2939 fastop(ctxt, em_or);
7af04fc0
AK		 2940 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2941 if (cf)
2942 ctxt->eflags |= X86_EFLAGS_CF;
2943 if (af)
2944 ctxt->eflags |= X86_EFLAGS_AF;
2945 return X86EMUL_CONTINUE;
2946}
2947
a035d5c6
PB		 2948static int em_aam(struct x86_emulate_ctxt *ctxt)
2949{
2950 u8 al, ah;
2951
2952 if (ctxt->src.val == 0)
2953 return emulate_de(ctxt);
2954
2955 al = ctxt->dst.val & 0xff;
2956 ah = al / ctxt->src.val;
2957 al %= ctxt->src.val;
2958
2959 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2960
2961 /* Set PF, ZF, SF */
2962 ctxt->src.type = OP_IMM;
2963 ctxt->src.val = 0;
2964 ctxt->src.bytes = 1;
2965 fastop(ctxt, em_or);
2966
2967 return X86EMUL_CONTINUE;
2968}
2969
7f662273
GN		 2970static int em_aad(struct x86_emulate_ctxt *ctxt)
2971{
2972 u8 al = ctxt->dst.val & 0xff;
2973 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2974
2975 al = (al + (ah * ctxt->src.val)) & 0xff;
2976
2977 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2978
f583c29b
GN		 2979 /* Set PF, ZF, SF */
2980 ctxt->src.type = OP_IMM;
2981 ctxt->src.val = 0;
2982 ctxt->src.bytes = 1;
2983 fastop(ctxt, em_or);
7f662273
GN		 2984
2985 return X86EMUL_CONTINUE;
2986}
2987
d4ddafcd
TY		 2988static int em_call(struct x86_emulate_ctxt *ctxt)
2989{
234f3ce4 2990 int rc;
d4ddafcd
TY		 2991 long rel = ctxt->src.val;
2992
2993 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2994 rc = jmp_rel(ctxt, rel);
2995 if (rc != X86EMUL_CONTINUE)
2996 return rc;
d4ddafcd
TY		 2997 return em_push(ctxt);
2998}
2999
0ef753b8
AK		 3000static int em_call_far(struct x86_emulate_ctxt *ctxt)
3001{
0ef753b8
AK		 3002 u16 sel, old_cs;
3003 ulong old_eip;
3004 int rc;
d1442d85
NA		 3005 struct desc_struct old_desc, new_desc;
3006 const struct x86_emulate_ops *ops = ctxt->ops;
3007 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3008
9dac77fa 3009 old_eip = ctxt->_eip;
d1442d85 3010 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3011
9dac77fa 3012 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3013 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3014 &new_desc);
3015 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3016 return X86EMUL_CONTINUE;
3017
d50eaa18 3018 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3019 if (rc != X86EMUL_CONTINUE)
3020 goto fail;
0ef753b8 3021
9dac77fa 3022 ctxt->src.val = old_cs;
4487b3b4 3023 rc = em_push(ctxt);
0ef753b8 3024 if (rc != X86EMUL_CONTINUE)
d1442d85 3025 goto fail;
0ef753b8 3026
9dac77fa 3027 ctxt->src.val = old_eip;
d1442d85
NA		 3028 rc = em_push(ctxt);
3029 /* If we failed, we tainted the memory, but the very least we should
3030 restore cs */
3031 if (rc != X86EMUL_CONTINUE)
3032 goto fail;
3033 return rc;
3034fail:
3035 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3036 return rc;
3037
0ef753b8
AK		 3038}
3039
40ece7c7
AK		 3040static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3041{
40ece7c7 3042 int rc;
234f3ce4 3043 unsigned long eip;
40ece7c7 3044
234f3ce4
NA		 3045 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3046 if (rc != X86EMUL_CONTINUE)
3047 return rc;
3048 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3049 if (rc != X86EMUL_CONTINUE)
3050 return rc;
5ad105e5 3051 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3052 return X86EMUL_CONTINUE;
3053}
3054
e4f973ae
TY		 3055static int em_xchg(struct x86_emulate_ctxt *ctxt)
3056{
e4f973ae 3057 /* Write back the register source. */
9dac77fa
AK		 3058 ctxt->src.val = ctxt->dst.val;
3059 write_register_operand(&ctxt->src);
e4f973ae
TY		 3060
3061 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3062 ctxt->dst.val = ctxt->src.orig_val;
3063 ctxt->lock_prefix = 1;
e4f973ae
TY		 3064 return X86EMUL_CONTINUE;
3065}
3066
5c82aa29
AK		 3067static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3068{
9dac77fa 3069 ctxt->dst.val = ctxt->src2.val;
4d758349 3070 return fastop(ctxt, em_imul);
5c82aa29
AK		 3071}
3072
61429142
AK		 3073static int em_cwd(struct x86_emulate_ctxt *ctxt)
3074{
9dac77fa
AK		 3075 ctxt->dst.type = OP_REG;
3076 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3077 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3078 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3079
3080 return X86EMUL_CONTINUE;
3081}
3082
48bb5d3c
AK		 3083static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3084{
48bb5d3c
AK		 3085 u64 tsc = 0;
3086
717746e3 3087 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3088 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3089 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3090 return X86EMUL_CONTINUE;
3091}
3092
222d21aa
AK		 3093static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3094{
3095 u64 pmc;
3096
dd856efa 3097 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3098 return emulate_gp(ctxt, 0);
dd856efa
AK		 3099 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3100 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3101 return X86EMUL_CONTINUE;
3102}
3103
b9eac5f4
AK		 3104static int em_mov(struct x86_emulate_ctxt *ctxt)
3105{
54cfdb3e 3106 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3107 return X86EMUL_CONTINUE;
3108}
3109
84cffe49
BP		 3110#define FFL(x) bit(X86_FEATURE_##x)
3111
3112static int em_movbe(struct x86_emulate_ctxt *ctxt)
3113{
3114 u32 ebx, ecx, edx, eax = 1;
3115 u16 tmp;
3116
3117 /*
3118 * Check MOVBE is set in the guest-visible CPUID leaf.
3119 */
3120 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3121 if (!(ecx & FFL(MOVBE)))
3122 return emulate_ud(ctxt);
3123
3124 switch (ctxt->op_bytes) {
3125 case 2:
3126 /*
3127 * From MOVBE definition: "...When the operand size is 16 bits,
3128 * the upper word of the destination register remains unchanged
3129 * ..."
3130 *
3131 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3132 * rules so we have to do the operation almost per hand.
3133 */
3134 tmp = (u16)ctxt->src.val;
3135 ctxt->dst.val &= ~0xffffUL;
3136 ctxt->dst.val |= (unsigned long)swab16(tmp);
3137 break;
3138 case 4:
3139 ctxt->dst.val = swab32((u32)ctxt->src.val);
3140 break;
3141 case 8:
3142 ctxt->dst.val = swab64(ctxt->src.val);
3143 break;
3144 default:
592f0858 3145 BUG();
84cffe49
BP		 3146 }
3147 return X86EMUL_CONTINUE;
3148}
3149
bc00f8d2
TY		 3150static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3151{
3152 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3153 return emulate_gp(ctxt, 0);
3154
3155 /* Disable writeback. */
3156 ctxt->dst.type = OP_NONE;
3157 return X86EMUL_CONTINUE;
3158}
3159
3160static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3161{
3162 unsigned long val;
3163
3164 if (ctxt->mode == X86EMUL_MODE_PROT64)
3165 val = ctxt->src.val & ~0ULL;
3166 else
3167 val = ctxt->src.val & ~0U;
3168
3169 /* #UD condition is already handled. */
3170 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3171 return emulate_gp(ctxt, 0);
3172
3173 /* Disable writeback. */
3174 ctxt->dst.type = OP_NONE;
3175 return X86EMUL_CONTINUE;
3176}
3177
e1e210b0
TY		 3178static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3179{
3180 u64 msr_data;
3181
dd856efa
AK		 3182 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3183 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3184 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3185 return emulate_gp(ctxt, 0);
3186
3187 return X86EMUL_CONTINUE;
3188}
3189
3190static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3191{
3192 u64 msr_data;
3193
dd856efa 3194 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3195 return emulate_gp(ctxt, 0);
3196
dd856efa
AK		 3197 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3198 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3199 return X86EMUL_CONTINUE;
3200}
3201
1bd5f469
TY		 3202static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3203{
9dac77fa 3204 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3205 return emulate_ud(ctxt);
3206
9dac77fa 3207 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3208 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3209 ctxt->dst.bytes = 2;
1bd5f469
TY		 3210 return X86EMUL_CONTINUE;
3211}
3212
3213static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3214{
9dac77fa 3215 u16 sel = ctxt->src.val;
1bd5f469 3216
9dac77fa 3217 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3218 return emulate_ud(ctxt);
3219
9dac77fa 3220 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3221 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3222
3223 /* Disable writeback. */
9dac77fa
AK		 3224 ctxt->dst.type = OP_NONE;
3225 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3226}
3227
a14e579f
AK		 3228static int em_lldt(struct x86_emulate_ctxt *ctxt)
3229{
3230 u16 sel = ctxt->src.val;
3231
3232 /* Disable writeback. */
3233 ctxt->dst.type = OP_NONE;
3234 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3235}
3236
80890006
AK		 3237static int em_ltr(struct x86_emulate_ctxt *ctxt)
3238{
3239 u16 sel = ctxt->src.val;
3240
3241 /* Disable writeback. */
3242 ctxt->dst.type = OP_NONE;
3243 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3244}
3245
38503911
AK		 3246static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3247{
9fa088f4
AK		 3248 int rc;
3249 ulong linear;
3250
9dac77fa 3251 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3252 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3253 ctxt->ops->invlpg(ctxt, linear);
38503911 3254 /* Disable writeback. */
9dac77fa 3255 ctxt->dst.type = OP_NONE;
38503911
AK		 3256 return X86EMUL_CONTINUE;
3257}
3258
2d04a05b
AK		 3259static int em_clts(struct x86_emulate_ctxt *ctxt)
3260{
3261 ulong cr0;
3262
3263 cr0 = ctxt->ops->get_cr(ctxt, 0);
3264 cr0 &= ~X86_CR0_TS;
3265 ctxt->ops->set_cr(ctxt, 0, cr0);
3266 return X86EMUL_CONTINUE;
3267}
3268
26d05cc7
AK		 3269static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3270{
0f54a321 3271 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3272
26d05cc7
AK		 3273 if (rc != X86EMUL_CONTINUE)
3274 return rc;
3275
3276 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3277 ctxt->_eip = ctxt->eip;
26d05cc7 3278 /* Disable writeback. */
9dac77fa 3279 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3280 return X86EMUL_CONTINUE;
3281}
3282
96051572
AK		 3283static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3284 void (*get)(struct x86_emulate_ctxt *ctxt,
3285 struct desc_ptr *ptr))
3286{
3287 struct desc_ptr desc_ptr;
3288
3289 if (ctxt->mode == X86EMUL_MODE_PROT64)
3290 ctxt->op_bytes = 8;
3291 get(ctxt, &desc_ptr);
3292 if (ctxt->op_bytes == 2) {
3293 ctxt->op_bytes = 4;
3294 desc_ptr.address &= 0x00ffffff;
3295 }
3296 /* Disable writeback. */
3297 ctxt->dst.type = OP_NONE;
3298 return segmented_write(ctxt, ctxt->dst.addr.mem,
3299 &desc_ptr, 2 + ctxt->op_bytes);
3300}
3301
3302static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3303{
3304 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3305}
3306
3307static int em_sidt(struct x86_emulate_ctxt *ctxt)
3308{
3309 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3310}
3311
5b7f6a1e 3312static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3313{
26d05cc7
AK		 3314 struct desc_ptr desc_ptr;
3315 int rc;
3316
510425ff
AK		 3317 if (ctxt->mode == X86EMUL_MODE_PROT64)
3318 ctxt->op_bytes = 8;
9dac77fa 3319 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3320 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3321 ctxt->op_bytes);
26d05cc7
AK		 3322 if (rc != X86EMUL_CONTINUE)
3323 return rc;
9a9abf6b
NA		 3324 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3325 is_noncanonical_address(desc_ptr.address))
3326 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3327 if (lgdt)
3328 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3329 else
3330 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3331 /* Disable writeback. */
9dac77fa 3332 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3333 return X86EMUL_CONTINUE;
3334}
3335
5b7f6a1e
NA		 3336static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3337{
3338 return em_lgdt_lidt(ctxt, true);
3339}
3340
5ef39c71 3341static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3342{
26d05cc7
AK		 3343 int rc;
3344
5ef39c71
AK		 3345 rc = ctxt->ops->fix_hypercall(ctxt);
3346
26d05cc7 3347 /* Disable writeback. */
9dac77fa 3348 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3349 return rc;
3350}
3351
3352static int em_lidt(struct x86_emulate_ctxt *ctxt)
3353{
5b7f6a1e 3354 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3355}
3356
3357static int em_smsw(struct x86_emulate_ctxt *ctxt)
3358{
32e94d06
NA		 3359 if (ctxt->dst.type == OP_MEM)
3360 ctxt->dst.bytes = 2;
9dac77fa 3361 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3362 return X86EMUL_CONTINUE;
3363}
3364
3365static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3366{
26d05cc7 3367 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3368 | (ctxt->src.val & 0x0f));
3369 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3370 return X86EMUL_CONTINUE;
3371}
3372
d06e03ad
TY		 3373static int em_loop(struct x86_emulate_ctxt *ctxt)
3374{
234f3ce4
NA		 3375 int rc = X86EMUL_CONTINUE;
3376
01485a22 3377 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3378 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3379 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3380 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3381
234f3ce4 3382 return rc;
d06e03ad
TY		 3383}
3384
3385static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3386{
234f3ce4
NA		 3387 int rc = X86EMUL_CONTINUE;
3388
dd856efa 3389 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3390 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3391
234f3ce4 3392 return rc;
d06e03ad
TY		 3393}
3394
d7841a4b
TY		 3395static int em_in(struct x86_emulate_ctxt *ctxt)
3396{
3397 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3398 &ctxt->dst.val))
3399 return X86EMUL_IO_NEEDED;
3400
3401 return X86EMUL_CONTINUE;
3402}
3403
3404static int em_out(struct x86_emulate_ctxt *ctxt)
3405{
3406 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3407 &ctxt->src.val, 1);
3408 /* Disable writeback. */
3409 ctxt->dst.type = OP_NONE;
3410 return X86EMUL_CONTINUE;
3411}
3412
f411e6cd
TY		 3413static int em_cli(struct x86_emulate_ctxt *ctxt)
3414{
3415 if (emulator_bad_iopl(ctxt))
3416 return emulate_gp(ctxt, 0);
3417
3418 ctxt->eflags &= ~X86_EFLAGS_IF;
3419 return X86EMUL_CONTINUE;
3420}
3421
3422static int em_sti(struct x86_emulate_ctxt *ctxt)
3423{
3424 if (emulator_bad_iopl(ctxt))
3425 return emulate_gp(ctxt, 0);
3426
3427 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3428 ctxt->eflags |= X86_EFLAGS_IF;
3429 return X86EMUL_CONTINUE;
3430}
3431
6d6eede4
AK		 3432static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3433{
3434 u32 eax, ebx, ecx, edx;
3435
dd856efa
AK		 3436 eax = reg_read(ctxt, VCPU_REGS_RAX);
3437 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3438 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3439 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3440 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3441 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3442 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3443 return X86EMUL_CONTINUE;
3444}
3445
98f73630
PB		 3446static int em_sahf(struct x86_emulate_ctxt *ctxt)
3447{
3448 u32 flags;
3449
3450 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3451 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3452
3453 ctxt->eflags &= ~0xffUL;
3454 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3455 return X86EMUL_CONTINUE;
3456}
3457
2dd7caa0
AK		 3458static int em_lahf(struct x86_emulate_ctxt *ctxt)
3459{
dd856efa
AK		 3460 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3461 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3462 return X86EMUL_CONTINUE;
3463}
3464
9299836e
AK		 3465static int em_bswap(struct x86_emulate_ctxt *ctxt)
3466{
3467 switch (ctxt->op_bytes) {
3468#ifdef CONFIG_X86_64
3469 case 8:
3470 asm("bswap %0" : "+r"(ctxt->dst.val));
3471 break;
3472#endif
3473 default:
3474 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3475 break;
3476 }
3477 return X86EMUL_CONTINUE;
3478}
3479
13e457e0
NA		 3480static int em_clflush(struct x86_emulate_ctxt *ctxt)
3481{
3482 /* emulating clflush regardless of cpuid */
3483 return X86EMUL_CONTINUE;
3484}
3485
cfec82cb
JR		 3486static bool valid_cr(int nr)
3487{
3488 switch (nr) {
3489 case 0:
3490 case 2 ... 4:
3491 case 8:
3492 return true;
3493 default:
3494 return false;
3495 }
3496}
3497
3498static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3499{
9dac77fa 3500 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3501 return emulate_ud(ctxt);
3502
3503 return X86EMUL_CONTINUE;
3504}
3505
3506static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3507{
9dac77fa
AK		 3508 u64 new_val = ctxt->src.val64;
3509 int cr = ctxt->modrm_reg;
c2ad2bb3 3510 u64 efer = 0;
cfec82cb
JR		 3511
3512 static u64 cr_reserved_bits[] = {
3513 0xffffffff00000000ULL,
3514 0, 0, 0, /* CR3 checked later */
3515 CR4_RESERVED_BITS,
3516 0, 0, 0,
3517 CR8_RESERVED_BITS,
3518 };
3519
3520 if (!valid_cr(cr))
3521 return emulate_ud(ctxt);
3522
3523 if (new_val & cr_reserved_bits[cr])
3524 return emulate_gp(ctxt, 0);
3525
3526 switch (cr) {
3527 case 0: {
c2ad2bb3 3528 u64 cr4;
cfec82cb
JR		 3529 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3530 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3531 return emulate_gp(ctxt, 0);
3532
717746e3
AK		 3533 cr4 = ctxt->ops->get_cr(ctxt, 4);
3534 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3535
3536 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3537 !(cr4 & X86_CR4_PAE))
3538 return emulate_gp(ctxt, 0);
3539
3540 break;
3541 }
3542 case 3: {
3543 u64 rsvd = 0;
3544
c2ad2bb3
AK		 3545 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3546 if (efer & EFER_LMA)
9d88fca7 3547 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3548
3549 if (new_val & rsvd)
3550 return emulate_gp(ctxt, 0);
3551
3552 break;
3553 }
3554 case 4: {
717746e3 3555 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3556
3557 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3558 return emulate_gp(ctxt, 0);
3559
3560 break;
3561 }
3562 }
3563
3564 return X86EMUL_CONTINUE;
3565}
3566
3b88e41a
JR		 3567static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3568{
3569 unsigned long dr7;
3570
717746e3 3571 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3572
3573 /* Check if DR7.Global_Enable is set */
3574 return dr7 & (1 << 13);
3575}
3576
3577static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3578{
9dac77fa 3579 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3580 u64 cr4;
3581
3582 if (dr > 7)
3583 return emulate_ud(ctxt);
3584
717746e3 3585 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3586 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3587 return emulate_ud(ctxt);
3588
6d2a0526
NA		 3589 if (check_dr7_gd(ctxt)) {
3590 ulong dr6;
3591
3592 ctxt->ops->get_dr(ctxt, 6, &dr6);
3593 dr6 &= ~15;
3594 dr6 |= DR6_BD | DR6_RTM;
3595 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3596 return emulate_db(ctxt);
6d2a0526 3597 }
3b88e41a
JR		 3598
3599 return X86EMUL_CONTINUE;
3600}
3601
3602static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3603{
9dac77fa
AK		 3604 u64 new_val = ctxt->src.val64;
3605 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3606
3607 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3608 return emulate_gp(ctxt, 0);
3609
3610 return check_dr_read(ctxt);
3611}
3612
01de8b09
JR		 3613static int check_svme(struct x86_emulate_ctxt *ctxt)
3614{
3615 u64 efer;
3616
717746e3 3617 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3618
3619 if (!(efer & EFER_SVME))
3620 return emulate_ud(ctxt);
3621
3622 return X86EMUL_CONTINUE;
3623}
3624
3625static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3626{
dd856efa 3627 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3628
3629 /* Valid physical address? */
d4224449 3630 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3631 return emulate_gp(ctxt, 0);
3632
3633 return check_svme(ctxt);
3634}
3635
d7eb8203
JR		 3636static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3637{
717746e3 3638 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3639
717746e3 3640 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3641 return emulate_ud(ctxt);
3642
3643 return X86EMUL_CONTINUE;
3644}
3645
8061252e
JR		 3646static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3647{
717746e3 3648 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3649 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3650
717746e3 3651 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3652 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3653 return emulate_gp(ctxt, 0);
3654
3655 return X86EMUL_CONTINUE;
3656}
3657
f6511935
JR		 3658static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3659{
9dac77fa
AK		 3660 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3661 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3662 return emulate_gp(ctxt, 0);
3663
3664 return X86EMUL_CONTINUE;
3665}
3666
3667static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3668{
9dac77fa
AK		 3669 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3670 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3671 return emulate_gp(ctxt, 0);
3672
3673 return X86EMUL_CONTINUE;
3674}
3675
73fba5f4 3676#define D(_y) { .flags = (_y) }
d40a6898
PB		 3677#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3678#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3679 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3680#define N D(NotImpl)
01de8b09 3681#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3682#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3683#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3684#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3685#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3686#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3687#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3688#define II(_f, _e, _i) \
d40a6898 3689 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3690#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3691 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3692 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3693#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3694
8d8f4e9f 3695#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3696#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3697#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3698#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3699#define I2bvIP(_f, _e, _i, _p) \
3700 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3701
fb864fbc
AK		 3702#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3703 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3704 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3705
0f54a321
NA		 3706static const struct opcode group7_rm0[] = {
3707 N,
3708 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3709 N, N, N, N, N, N,
3710};
3711
fd0a0d82 3712static const struct opcode group7_rm1[] = {
1c2545be
TY		 3713 DI(SrcNone | Priv, monitor),
3714 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3715 N, N, N, N, N, N,
3716};
3717
fd0a0d82 3718static const struct opcode group7_rm3[] = {
1c2545be 3719 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3720 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3721 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3722 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3723 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3724 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3725 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3726 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3727};
6230f7fc 3728
fd0a0d82 3729static const struct opcode group7_rm7[] = {
d7eb8203 3730 N,
1c2545be 3731 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3732 N, N, N, N, N, N,
3733};
d67fc27a 3734
fd0a0d82 3735static const struct opcode group1[] = {
fb864fbc
AK		 3736 F(Lock, em_add),
3737 F(Lock | PageTable, em_or),
3738 F(Lock, em_adc),
3739 F(Lock, em_sbb),
3740 F(Lock | PageTable, em_and),
3741 F(Lock, em_sub),
3742 F(Lock, em_xor),
3743 F(NoWrite, em_cmp),
73fba5f4
AK		 3744};
3745
fd0a0d82 3746static const struct opcode group1A[] = {
1c2545be 3747 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3748};
3749
007a3b54
AK		 3750static const struct opcode group2[] = {
3751 F(DstMem | ModRM, em_rol),
3752 F(DstMem | ModRM, em_ror),
3753 F(DstMem | ModRM, em_rcl),
3754 F(DstMem | ModRM, em_rcr),
3755 F(DstMem | ModRM, em_shl),
3756 F(DstMem | ModRM, em_shr),
3757 F(DstMem | ModRM, em_shl),
3758 F(DstMem | ModRM, em_sar),
3759};
3760
fd0a0d82 3761static const struct opcode group3[] = {
fb864fbc
AK		 3762 F(DstMem | SrcImm | NoWrite, em_test),
3763 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3764 F(DstMem | SrcNone | Lock, em_not),
3765 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3766 F(DstXacc | Src2Mem, em_mul_ex),
3767 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3768 F(DstXacc | Src2Mem, em_div_ex),
3769 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3770};
3771
fd0a0d82 3772static const struct opcode group4[] = {
95413dc4
AK		 3773 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3774 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3775 N, N, N, N, N, N,
3776};
3777
fd0a0d82 3778static const struct opcode group5[] = {
95413dc4
AK		 3779 F(DstMem | SrcNone | Lock, em_inc),
3780 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3781 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3782 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3783 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3784 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3785 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3786};
3787
fd0a0d82 3788static const struct opcode group6[] = {
1c2545be
TY		 3789 DI(Prot, sldt),
3790 DI(Prot, str),
a14e579f 3791 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3792 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3793 N, N, N, N,
3794};
3795
fd0a0d82 3796static const struct group_dual group7 = { {
606b1c3e
NA		 3797 II(Mov | DstMem, em_sgdt, sgdt),
3798 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3799 II(SrcMem | Priv, em_lgdt, lgdt),
3800 II(SrcMem | Priv, em_lidt, lidt),
3801 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3802 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3803 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3804}, {
0f54a321 3805 EXT(0, group7_rm0),
5ef39c71 3806 EXT(0, group7_rm1),
01de8b09 3807 N, EXT(0, group7_rm3),
1c2545be
TY		 3808 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3809 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3810 EXT(0, group7_rm7),
73fba5f4
AK		 3811} };
3812
fd0a0d82 3813static const struct opcode group8[] = {
73fba5f4 3814 N, N, N, N,
11c363ba
AK		 3815 F(DstMem | SrcImmByte | NoWrite, em_bt),
3816 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3817 F(DstMem | SrcImmByte | Lock, em_btr),
3818 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3819};
3820
fd0a0d82 3821static const struct group_dual group9 = { {
1c2545be 3822 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3823}, {
3824 N, N, N, N, N, N, N, N,
3825} };
3826
fd0a0d82 3827static const struct opcode group11[] = {
1c2545be 3828 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3829 X7(D(Undefined)),
a4d4a7c1
AK		 3830};
3831
13e457e0 3832static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3833 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3834};
3835
3836static const struct group_dual group15 = { {
3837 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3838}, {
3839 N, N, N, N, N, N, N, N,
3840} };
3841
fd0a0d82 3842static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3843 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3844};
3845
39f062ff
NA		 3846static const struct instr_dual instr_dual_0f_2b = {
3847 I(0, em_mov), N
3848};
3849
d5b77069 3850static const struct gprefix pfx_0f_2b = {
39f062ff 3851 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3852};
3853
27ce8258 3854static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3855 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3856};
3857
0a37027e
AW		 3858static const struct gprefix pfx_0f_e7 = {
3859 N, I(Sse, em_mov), N, N,
3860};
3861
045a282c 3862static const struct escape escape_d9 = { {
16bebefe 3863 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3864}, {
3865 /* 0xC0 - 0xC7 */
3866 N, N, N, N, N, N, N, N,
3867 /* 0xC8 - 0xCF */
3868 N, N, N, N, N, N, N, N,
3869 /* 0xD0 - 0xC7 */
3870 N, N, N, N, N, N, N, N,
3871 /* 0xD8 - 0xDF */
3872 N, N, N, N, N, N, N, N,
3873 /* 0xE0 - 0xE7 */
3874 N, N, N, N, N, N, N, N,
3875 /* 0xE8 - 0xEF */
3876 N, N, N, N, N, N, N, N,
3877 /* 0xF0 - 0xF7 */
3878 N, N, N, N, N, N, N, N,
3879 /* 0xF8 - 0xFF */
3880 N, N, N, N, N, N, N, N,
3881} };
3882
3883static const struct escape escape_db = { {
3884 N, N, N, N, N, N, N, N,
3885}, {
3886 /* 0xC0 - 0xC7 */
3887 N, N, N, N, N, N, N, N,
3888 /* 0xC8 - 0xCF */
3889 N, N, N, N, N, N, N, N,
3890 /* 0xD0 - 0xC7 */
3891 N, N, N, N, N, N, N, N,
3892 /* 0xD8 - 0xDF */
3893 N, N, N, N, N, N, N, N,
3894 /* 0xE0 - 0xE7 */
3895 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3896 /* 0xE8 - 0xEF */
3897 N, N, N, N, N, N, N, N,
3898 /* 0xF0 - 0xF7 */
3899 N, N, N, N, N, N, N, N,
3900 /* 0xF8 - 0xFF */
3901 N, N, N, N, N, N, N, N,
3902} };
3903
3904static const struct escape escape_dd = { {
16bebefe 3905 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3906}, {
3907 /* 0xC0 - 0xC7 */
3908 N, N, N, N, N, N, N, N,
3909 /* 0xC8 - 0xCF */
3910 N, N, N, N, N, N, N, N,
3911 /* 0xD0 - 0xC7 */
3912 N, N, N, N, N, N, N, N,
3913 /* 0xD8 - 0xDF */
3914 N, N, N, N, N, N, N, N,
3915 /* 0xE0 - 0xE7 */
3916 N, N, N, N, N, N, N, N,
3917 /* 0xE8 - 0xEF */
3918 N, N, N, N, N, N, N, N,
3919 /* 0xF0 - 0xF7 */
3920 N, N, N, N, N, N, N, N,
3921 /* 0xF8 - 0xFF */
3922 N, N, N, N, N, N, N, N,
3923} };
3924
39f062ff
NA		 3925static const struct instr_dual instr_dual_0f_c3 = {
3926 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3927};
3928
fd0a0d82 3929static const struct opcode opcode_table[256] = {
73fba5f4 3930 /* 0x00 - 0x07 */
fb864fbc 3931 F6ALU(Lock, em_add),
1cd196ea
AK		 3932 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3933 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3934 /* 0x08 - 0x0F */
fb864fbc 3935 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3936 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3937 N,
73fba5f4 3938 /* 0x10 - 0x17 */
fb864fbc 3939 F6ALU(Lock, em_adc),
1cd196ea
AK		 3940 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3941 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3942 /* 0x18 - 0x1F */
fb864fbc 3943 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3944 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3945 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3946 /* 0x20 - 0x27 */
fb864fbc 3947 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3948 /* 0x28 - 0x2F */
fb864fbc 3949 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3950 /* 0x30 - 0x37 */
fb864fbc 3951 F6ALU(Lock, em_xor), N, N,
73fba5f4 3952 /* 0x38 - 0x3F */
fb864fbc 3953 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3954 /* 0x40 - 0x4F */
95413dc4 3955 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3956 /* 0x50 - 0x57 */
63540382 3957 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3958 /* 0x58 - 0x5F */
c54fe504 3959 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3960 /* 0x60 - 0x67 */
b96a7fad
TY		 3961 I(ImplicitOps | Stack | No64, em_pusha),
3962 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3963 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3964 N, N, N, N,
3965 /* 0x68 - 0x6F */
d46164db
AK		 3966 I(SrcImm | Mov | Stack, em_push),
3967 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3968 I(SrcImmByte | Mov | Stack, em_push),
3969 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3970 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3971 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3972 /* 0x70 - 0x7F */
58b7075d 3973 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3974 /* 0x80 - 0x87 */
1c2545be
TY		 3975 G(ByteOp | DstMem | SrcImm, group1),
3976 G(DstMem | SrcImm, group1),
3977 G(ByteOp | DstMem | SrcImm | No64, group1),
3978 G(DstMem | SrcImmByte, group1),
fb864fbc 3979 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3980 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3981 /* 0x88 - 0x8F */
d5ae7ce8 3982 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3983 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3984 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3985 D(ModRM | SrcMem | NoAccess | DstReg),
3986 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3987 G(0, group1A),
73fba5f4 3988 /* 0x90 - 0x97 */
bf608f88 3989 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3990 /* 0x98 - 0x9F */
61429142 3991 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3992 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3993 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3994 II(ImplicitOps | Stack, em_popf, popf),
3995 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3996 /* 0xA0 - 0xA7 */
b9eac5f4 3997 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3998 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3999 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4000 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4001 /* 0xA8 - 0xAF */
fb864fbc 4002 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4003 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4004 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4005 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4006 /* 0xB0 - 0xB7 */
b9eac5f4 4007 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4008 /* 0xB8 - 0xBF */
5e2c6883 4009 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4010 /* 0xC0 - 0xC7 */
007a3b54 4011 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4012 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4013 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4014 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4015 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4016 G(ByteOp, group11), G(0, group11),
73fba5f4 4017 /* 0xC8 - 0xCF */
612e89f0 4018 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4019 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4020 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4021 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4022 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4023 /* 0xD0 - 0xD7 */
007a3b54
AK		 4024 G(Src2One | ByteOp, group2), G(Src2One, group2),
4025 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4026 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4027 I(DstAcc | SrcImmUByte | No64, em_aad),
4028 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4029 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4030 /* 0xD8 - 0xDF */
045a282c 4031 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4032 /* 0xE0 - 0xE7 */
58b7075d
NA		 4033 X3(I(SrcImmByte | NearBranch, em_loop)),
4034 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4035 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4036 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4037 /* 0xE8 - 0xEF */
58b7075d
NA		 4038 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4039 I(SrcImmFAddr | No64, em_jmp_far),
4040 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4041 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4042 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4043 /* 0xF0 - 0xF7 */
bf608f88 4044 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4045 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4046 G(ByteOp, group3), G(0, group3),
73fba5f4 4047 /* 0xF8 - 0xFF */
f411e6cd
TY		 4048 D(ImplicitOps), D(ImplicitOps),
4049 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4050 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4051};
4052
fd0a0d82 4053static const struct opcode twobyte_table[256] = {
73fba5f4 4054 /* 0x00 - 0x0F */
dee6bb70 4055 G(0, group6), GD(0, &group7), N, N,
b51e974f 4056 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4057 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4058 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4059 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4060 /* 0x10 - 0x1F */
103f98ea 4061 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4062 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4063 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4064 /* 0x20 - 0x2F */
9b88ae99
NA		 4065 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4066 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4067 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4068 check_cr_write),
4069 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4070 check_dr_write),
73fba5f4 4071 N, N, N, N,
27ce8258
IM		 4072 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4073 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4074 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4075 N, N, N, N,
73fba5f4 4076 /* 0x30 - 0x3F */
e1e210b0 4077 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4078 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4079 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4080 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4081 I(ImplicitOps | EmulateOnUD, em_sysenter),
4082 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4083 N, N,
73fba5f4
AK		 4084 N, N, N, N, N, N, N, N,
4085 /* 0x40 - 0x4F */
140bad89 4086 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4087 /* 0x50 - 0x5F */
4088 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4089 /* 0x60 - 0x6F */
aa97bb48
AK		 4090 N, N, N, N,
4091 N, N, N, N,
4092 N, N, N, N,
4093 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4094 /* 0x70 - 0x7F */
aa97bb48
AK		 4095 N, N, N, N,
4096 N, N, N, N,
4097 N, N, N, N,
4098 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4099 /* 0x80 - 0x8F */
58b7075d 4100 X16(D(SrcImm | NearBranch)),
73fba5f4 4101 /* 0x90 - 0x9F */
ee45b58e 4102 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4103 /* 0xA0 - 0xA7 */
1cd196ea 4104 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4105 II(ImplicitOps, em_cpuid, cpuid),
4106 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4107 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4108 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4109 /* 0xA8 - 0xAF */
1cd196ea 4110 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4111 DI(ImplicitOps, rsm),
11c363ba 4112 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4113 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4114 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4115 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4116 /* 0xB0 - 0xB7 */
e940b5c2 4117 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4118 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4119 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4120 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4121 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4122 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4123 /* 0xB8 - 0xBF */
4124 N, N,
ce7faab2 4125 G(BitOp, group8),
11c363ba
AK		 4126 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4127 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4128 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4129 /* 0xC0 - 0xC7 */
e47a5f5f 4130 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4131 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4132 N, N, N, GD(0, &group9),
9299836e
AK		 4133 /* 0xC8 - 0xCF */
4134 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4135 /* 0xD0 - 0xDF */
4136 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4137 /* 0xE0 - 0xEF */
0a37027e
AW		 4138 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4139 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4140 /* 0xF0 - 0xFF */
4141 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4142};
4143
39f062ff
NA		 4144static const struct instr_dual instr_dual_0f_38_f0 = {
4145 I(DstReg | SrcMem | Mov, em_movbe), N
4146};
4147
4148static const struct instr_dual instr_dual_0f_38_f1 = {
4149 I(DstMem | SrcReg | Mov, em_movbe), N
4150};
4151
0bc5eedb 4152static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4153 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4154};
4155
4156static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4157 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4158};
4159
4160/*
4161 * Insns below are selected by the prefix which indexed by the third opcode
4162 * byte.
4163 */
4164static const struct opcode opcode_map_0f_38[256] = {
4165 /* 0x00 - 0x7f */
4166 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4167 /* 0x80 - 0xef */
4168 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4169 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4170 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4171 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4172 /* 0xf2 - 0xff */
4173 N, N, X4(N), X8(N)
0bc5eedb
BP		 4174};
4175
73fba5f4
AK		 4176#undef D
4177#undef N
4178#undef G
4179#undef GD
4180#undef I
aa97bb48 4181#undef GP
01de8b09 4182#undef EXT
73fba5f4 4183
8d8f4e9f 4184#undef D2bv
f6511935 4185#undef D2bvIP
8d8f4e9f 4186#undef I2bv
d7841a4b 4187#undef I2bvIP
d67fc27a 4188#undef I6ALU
8d8f4e9f 4189
9dac77fa 4190static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4191{
4192 unsigned size;
4193
9dac77fa 4194 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4195 if (size == 8)
4196 size = 4;
4197 return size;
4198}
4199
4200static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4201 unsigned size, bool sign_extension)
4202{
39f21ee5
AK		 4203 int rc = X86EMUL_CONTINUE;
4204
4205 op->type = OP_IMM;
4206 op->bytes = size;
9dac77fa 4207 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4208 /* NB. Immediates are sign-extended as necessary. */
4209 switch (op->bytes) {
4210 case 1:
e85a1085 4211 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4212 break;
4213 case 2:
e85a1085 4214 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4215 break;
4216 case 4:
e85a1085 4217 op->val = insn_fetch(s32, ctxt);
39f21ee5 4218 break;
5e2c6883
NA		 4219 case 8:
4220 op->val = insn_fetch(s64, ctxt);
4221 break;
39f21ee5
AK		 4222 }
4223 if (!sign_extension) {
4224 switch (op->bytes) {
4225 case 1:
4226 op->val &= 0xff;
4227 break;
4228 case 2:
4229 op->val &= 0xffff;
4230 break;
4231 case 4:
4232 op->val &= 0xffffffff;
4233 break;
4234 }
4235 }
4236done:
4237 return rc;
4238}
4239
a9945549
AK		 4240static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4241 unsigned d)
4242{
4243 int rc = X86EMUL_CONTINUE;
4244
4245 switch (d) {
4246 case OpReg:
2adb5ad9 4247 decode_register_operand(ctxt, op);
a9945549
AK		 4248 break;
4249 case OpImmUByte:
608aabe3 4250 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4251 break;
4252 case OpMem:
41ddf978 4253 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4254 mem_common:
4255 *op = ctxt->memop;
4256 ctxt->memopp = op;
96888977 4257 if (ctxt->d & BitOp)
a9945549
AK		 4258 fetch_bit_operand(ctxt);
4259 op->orig_val = op->val;
4260 break;
41ddf978 4261 case OpMem64:
aaa05f24 4262 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4263 goto mem_common;
a9945549
AK		 4264 case OpAcc:
4265 op->type = OP_REG;
4266 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4267 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4268 fetch_register_operand(op);
4269 op->orig_val = op->val;
4270 break;
820207c8
AK		 4271 case OpAccLo:
4272 op->type = OP_REG;
4273 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4274 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4275 fetch_register_operand(op);
4276 op->orig_val = op->val;
4277 break;
4278 case OpAccHi:
4279 if (ctxt->d & ByteOp) {
4280 op->type = OP_NONE;
4281 break;
4282 }
4283 op->type = OP_REG;
4284 op->bytes = ctxt->op_bytes;
4285 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4286 fetch_register_operand(op);
4287 op->orig_val = op->val;
4288 break;
a9945549
AK		 4289 case OpDI:
4290 op->type = OP_MEM;
4291 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4292 op->addr.mem.ea =
01485a22 4293 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4294 op->addr.mem.seg = VCPU_SREG_ES;
4295 op->val = 0;
b3356bf0 4296 op->count = 1;
a9945549
AK		 4297 break;
4298 case OpDX:
4299 op->type = OP_REG;
4300 op->bytes = 2;
dd856efa 4301 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4302 fetch_register_operand(op);
4303 break;
4dd6a57d 4304 case OpCL:
d29b9d7e 4305 op->type = OP_IMM;
4dd6a57d 4306 op->bytes = 1;
dd856efa 4307 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4308 break;
4309 case OpImmByte:
4310 rc = decode_imm(ctxt, op, 1, true);
4311 break;
4312 case OpOne:
d29b9d7e 4313 op->type = OP_IMM;
4dd6a57d
AK		 4314 op->bytes = 1;
4315 op->val = 1;
4316 break;
4317 case OpImm:
4318 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4319 break;
5e2c6883
NA		 4320 case OpImm64:
4321 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4322 break;
28867cee
AK		 4323 case OpMem8:
4324 ctxt->memop.bytes = 1;
660696d1 4325 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4326 ctxt->memop.addr.reg = decode_register(ctxt,
4327 ctxt->modrm_rm, true);
660696d1
GN		 4328 fetch_register_operand(&ctxt->memop);
4329 }
28867cee 4330 goto mem_common;
0fe59128
AK		 4331 case OpMem16:
4332 ctxt->memop.bytes = 2;
4333 goto mem_common;
4334 case OpMem32:
4335 ctxt->memop.bytes = 4;
4336 goto mem_common;
4337 case OpImmU16:
4338 rc = decode_imm(ctxt, op, 2, false);
4339 break;
4340 case OpImmU:
4341 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4342 break;
4343 case OpSI:
4344 op->type = OP_MEM;
4345 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4346 op->addr.mem.ea =
01485a22 4347 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4348 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4349 op->val = 0;
b3356bf0 4350 op->count = 1;
0fe59128 4351 break;
7fa57952
PB		 4352 case OpXLat:
4353 op->type = OP_MEM;
4354 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4355 op->addr.mem.ea =
01485a22 4356 address_mask(ctxt,
7fa57952
PB		 4357 reg_read(ctxt, VCPU_REGS_RBX) +
4358 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4359 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4360 op->val = 0;
4361 break;
0fe59128
AK		 4362 case OpImmFAddr:
4363 op->type = OP_IMM;
4364 op->addr.mem.ea = ctxt->_eip;
4365 op->bytes = ctxt->op_bytes + 2;
4366 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4367 break;
4368 case OpMemFAddr:
4369 ctxt->memop.bytes = ctxt->op_bytes + 2;
4370 goto mem_common;
c191a7a0 4371 case OpES:
d29b9d7e 4372 op->type = OP_IMM;
c191a7a0
AK		 4373 op->val = VCPU_SREG_ES;
4374 break;
4375 case OpCS:
d29b9d7e 4376 op->type = OP_IMM;
c191a7a0
AK		 4377 op->val = VCPU_SREG_CS;
4378 break;
4379 case OpSS:
d29b9d7e 4380 op->type = OP_IMM;
c191a7a0
AK		 4381 op->val = VCPU_SREG_SS;
4382 break;
4383 case OpDS:
d29b9d7e 4384 op->type = OP_IMM;
c191a7a0
AK		 4385 op->val = VCPU_SREG_DS;
4386 break;
4387 case OpFS:
d29b9d7e 4388 op->type = OP_IMM;
c191a7a0
AK		 4389 op->val = VCPU_SREG_FS;
4390 break;
4391 case OpGS:
d29b9d7e 4392 op->type = OP_IMM;
c191a7a0
AK		 4393 op->val = VCPU_SREG_GS;
4394 break;
a9945549
AK		 4395 case OpImplicit:
4396 /* Special instructions do their own operand decoding. */
4397 default:
4398 op->type = OP_NONE; /* Disable writeback. */
4399 break;
4400 }
4401
4402done:
4403 return rc;
4404}
4405
ef5d75cc 4406int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4407{
dde7e6d1
AK		 4408 int rc = X86EMUL_CONTINUE;
4409 int mode = ctxt->mode;
46561646 4410 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4411 bool op_prefix = false;
573e80fe 4412 bool has_seg_override = false;
46561646 4413 struct opcode opcode;
dde7e6d1 4414
f09ed83e
AK		 4415 ctxt->memop.type = OP_NONE;
4416 ctxt->memopp = NULL;
9dac77fa 4417 ctxt->_eip = ctxt->eip;
17052f16
PB		 4418 ctxt->fetch.ptr = ctxt->fetch.data;
4419 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4420 ctxt->opcode_len = 1;
dc25e89e 4421 if (insn_len > 0)
9dac77fa 4422 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4423 else {
9506d57d 4424 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4425 if (rc != X86EMUL_CONTINUE)
4426 return rc;
4427 }
dde7e6d1
AK		 4428
4429 switch (mode) {
4430 case X86EMUL_MODE_REAL:
4431 case X86EMUL_MODE_VM86:
4432 case X86EMUL_MODE_PROT16:
4433 def_op_bytes = def_ad_bytes = 2;
4434 break;
4435 case X86EMUL_MODE_PROT32:
4436 def_op_bytes = def_ad_bytes = 4;
4437 break;
4438#ifdef CONFIG_X86_64
4439 case X86EMUL_MODE_PROT64:
4440 def_op_bytes = 4;
4441 def_ad_bytes = 8;
4442 break;
4443#endif
4444 default:
1d2887e2 4445 return EMULATION_FAILED;
dde7e6d1
AK		 4446 }
4447
9dac77fa
AK		 4448 ctxt->op_bytes = def_op_bytes;
4449 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4450
4451 /* Legacy prefixes. */
4452 for (;;) {
e85a1085 4453 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4454 case 0x66: /* operand-size override */
0d7cdee8 4455 op_prefix = true;
dde7e6d1 4456 /* switch between 2/4 bytes */
9dac77fa 4457 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4458 break;
4459 case 0x67: /* address-size override */
4460 if (mode == X86EMUL_MODE_PROT64)
4461 /* switch between 4/8 bytes */
9dac77fa 4462 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4463 else
4464 /* switch between 2/4 bytes */
9dac77fa 4465 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4466 break;
4467 case 0x26: /* ES override */
4468 case 0x2e: /* CS override */
4469 case 0x36: /* SS override */
4470 case 0x3e: /* DS override */
573e80fe
BD		 4471 has_seg_override = true;
4472 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4473 break;
4474 case 0x64: /* FS override */
4475 case 0x65: /* GS override */
573e80fe
BD		 4476 has_seg_override = true;
4477 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4478 break;
4479 case 0x40 ... 0x4f: /* REX */
4480 if (mode != X86EMUL_MODE_PROT64)
4481 goto done_prefixes;
9dac77fa 4482 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4483 continue;
4484 case 0xf0: /* LOCK */
9dac77fa 4485 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4486 break;
4487 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4488 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4489 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4490 break;
4491 default:
4492 goto done_prefixes;
4493 }
4494
4495 /* Any legacy prefix after a REX prefix nullifies its effect. */
4496
9dac77fa 4497 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4498 }
4499
4500done_prefixes:
4501
4502 /* REX prefix. */
9dac77fa
AK		 4503 if (ctxt->rex_prefix & 8)
4504 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4505
4506 /* Opcode byte(s). */
9dac77fa 4507 opcode = opcode_table[ctxt->b];
d3ad6243 4508 /* Two-byte opcode? */
9dac77fa 4509 if (ctxt->b == 0x0f) {
1ce19dc1 4510 ctxt->opcode_len = 2;
e85a1085 4511 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4512 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4513
4514 /* 0F_38 opcode map */
4515 if (ctxt->b == 0x38) {
4516 ctxt->opcode_len = 3;
4517 ctxt->b = insn_fetch(u8, ctxt);
4518 opcode = opcode_map_0f_38[ctxt->b];
4519 }
dde7e6d1 4520 }
9dac77fa 4521 ctxt->d = opcode.flags;
dde7e6d1 4522
9f4260e7
TY		 4523 if (ctxt->d & ModRM)
4524 ctxt->modrm = insn_fetch(u8, ctxt);
4525
7fe864dc
NA		 4526 /* vex-prefix instructions are not implemented */
4527 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4528 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4529 ctxt->d = NotImpl;
4530 }
4531
9dac77fa
AK		 4532 while (ctxt->d & GroupMask) {
4533 switch (ctxt->d & GroupMask) {
46561646 4534 case Group:
9dac77fa 4535 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4536 opcode = opcode.u.group[goffset];
4537 break;
4538 case GroupDual:
9dac77fa
AK		 4539 goffset = (ctxt->modrm >> 3) & 7;
4540 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4541 opcode = opcode.u.gdual->mod3[goffset];
4542 else
4543 opcode = opcode.u.gdual->mod012[goffset];
4544 break;
4545 case RMExt:
9dac77fa 4546 goffset = ctxt->modrm & 7;
01de8b09 4547 opcode = opcode.u.group[goffset];
46561646
AK		 4548 break;
4549 case Prefix:
9dac77fa 4550 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4551 return EMULATION_FAILED;
9dac77fa 4552 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4553 switch (simd_prefix) {
4554 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4555 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4556 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4557 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4558 }
4559 break;
045a282c
GN		 4560 case Escape:
4561 if (ctxt->modrm > 0xbf)
4562 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4563 else
4564 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4565 break;
39f062ff
NA		 4566 case InstrDual:
4567 if ((ctxt->modrm >> 6) == 3)
4568 opcode = opcode.u.idual->mod3;
4569 else
4570 opcode = opcode.u.idual->mod012;
4571 break;
46561646 4572 default:
1d2887e2 4573 return EMULATION_FAILED;
0d7cdee8 4574 }
46561646 4575
b1ea50b2 4576 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4577 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4578 }
4579
e24186e0
PB		 4580 /* Unrecognised? */
4581 if (ctxt->d == 0)
4582 return EMULATION_FAILED;
4583
9dac77fa 4584 ctxt->execute = opcode.u.execute;
dde7e6d1 4585
3a6095a0
NA		 4586 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4587 return EMULATION_FAILED;
4588
d40a6898 4589 if (unlikely(ctxt->d &
ed9aad21
NA		 4590 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4591 No16))) {
d40a6898
PB		 4592 /*
4593 * These are copied unconditionally here, and checked unconditionally
4594 * in x86_emulate_insn.
4595 */
4596 ctxt->check_perm = opcode.check_perm;
4597 ctxt->intercept = opcode.intercept;
dde7e6d1 4598
d40a6898
PB		 4599 if (ctxt->d & NotImpl)
4600 return EMULATION_FAILED;
d867162c 4601
58b7075d
NA		 4602 if (mode == X86EMUL_MODE_PROT64) {
4603 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4604 ctxt->op_bytes = 8;
4605 else if (ctxt->d & NearBranch)
4606 ctxt->op_bytes = 8;
4607 }
7f9b4b75 4608
d40a6898
PB		 4609 if (ctxt->d & Op3264) {
4610 if (mode == X86EMUL_MODE_PROT64)
4611 ctxt->op_bytes = 8;
4612 else
4613 ctxt->op_bytes = 4;
4614 }
4615
ed9aad21
NA		 4616 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4617 ctxt->op_bytes = 4;
4618
d40a6898
PB		 4619 if (ctxt->d & Sse)
4620 ctxt->op_bytes = 16;
4621 else if (ctxt->d & Mmx)
4622 ctxt->op_bytes = 8;
4623 }
1253791d 4624
dde7e6d1 4625 /* ModRM and SIB bytes. */
9dac77fa 4626 if (ctxt->d & ModRM) {
f09ed83e 4627 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4628 if (!has_seg_override) {
4629 has_seg_override = true;
4630 ctxt->seg_override = ctxt->modrm_seg;
4631 }
9dac77fa 4632 } else if (ctxt->d & MemAbs)
f09ed83e 4633 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4634 if (rc != X86EMUL_CONTINUE)
4635 goto done;
4636
573e80fe
BD		 4637 if (!has_seg_override)
4638 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4639
573e80fe 4640 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4641
dde7e6d1
AK		 4642 /*
4643 * Decode and fetch the source operand: register, memory
4644 * or immediate.
4645 */
0fe59128 4646 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4647 if (rc != X86EMUL_CONTINUE)
4648 goto done;
4649
dde7e6d1
AK		 4650 /*
4651 * Decode and fetch the second source operand: register, memory
4652 * or immediate.
4653 */
4dd6a57d 4654 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4655 if (rc != X86EMUL_CONTINUE)
4656 goto done;
4657
dde7e6d1 4658 /* Decode and fetch the destination operand: register or memory. */
a9945549 4659 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4660
41061cdb 4661 if (ctxt->rip_relative)
1c1c35ae
NA		 4662 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4663 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4664
a430c916 4665done:
1d2887e2 4666 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4667}
4668
1cb3f3ae
XG		 4669bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4670{
4671 return ctxt->d & PageTable;
4672}
4673
3e2f65d5
GN		 4674static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4675{
3e2f65d5
GN		 4676 /* The second termination condition only applies for REPE
4677 * and REPNE. Test if the repeat string operation prefix is
4678 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4679 * corresponding termination condition according to:
4680 * - if REPE/REPZ and ZF = 0 then done
4681 * - if REPNE/REPNZ and ZF = 1 then done
4682 */
9dac77fa
AK		 4683 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4684 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4685 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4686 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4687 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4688 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4689 return true;
4690
4691 return false;
4692}
4693
cbe2c9d3
AK		 4694static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4695{
4696 bool fault = false;
4697
4698 ctxt->ops->get_fpu(ctxt);
4699 asm volatile("1: fwait \n\t"
4700 "2: \n\t"
4701 ".pushsection .fixup,\"ax\" \n\t"
4702 "3: \n\t"
4703 "movb $1, %[fault] \n\t"
4704 "jmp 2b \n\t"
4705 ".popsection \n\t"
4706 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4707 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4708 ctxt->ops->put_fpu(ctxt);
4709
4710 if (unlikely(fault))
4711 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4712
4713 return X86EMUL_CONTINUE;
4714}
4715
4716static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4717 struct operand *op)
4718{
4719 if (op->type == OP_MM)
4720 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4721}
4722
e28bbd44
AK		 4723static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4724{
4725 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4726 if (!(ctxt->d & ByteOp))
4727 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4728 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4729 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4730 [fastop]"+S"(fop)
4731 : "c"(ctxt->src2.val));
e28bbd44 4732 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4733 if (!fop) /* exception is returned in fop variable */
4734 return emulate_de(ctxt);
e28bbd44
AK		 4735 return X86EMUL_CONTINUE;
4736}
dd856efa 4737
1498507a
BD		 4738void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4739{
573e80fe
BD		 4740 memset(&ctxt->rip_relative, 0,
4741 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4742
1498507a
BD		 4743 ctxt->io_read.pos = 0;
4744 ctxt->io_read.end = 0;
1498507a
BD		 4745 ctxt->mem_read.end = 0;
4746}
4747
7b105ca2 4748int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4749{
0225fb50 4750 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4751 int rc = X86EMUL_CONTINUE;
9dac77fa 4752 int saved_dst_type = ctxt->dst.type;
8b4caf66 4753
9dac77fa 4754 ctxt->mem_read.pos = 0;
310b5d30 4755
e24186e0
PB		 4756 /* LOCK prefix is allowed only with some instructions */
4757 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4758 rc = emulate_ud(ctxt);
1161624f
GN		 4759 goto done;
4760 }
4761
e24186e0 4762 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4763 rc = emulate_ud(ctxt);
d380a5e4
GN		 4764 goto done;
4765 }
4766
d40a6898
PB		 4767 if (unlikely(ctxt->d &
4768 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4769 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4770 (ctxt->d & Undefined)) {
4771 rc = emulate_ud(ctxt);
4772 goto done;
4773 }
1253791d 4774
d40a6898
PB		 4775 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4776 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4777 rc = emulate_ud(ctxt);
cbe2c9d3 4778 goto done;
d40a6898 4779 }
cbe2c9d3 4780
d40a6898
PB		 4781 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4782 rc = emulate_nm(ctxt);
c4f035c6 4783 goto done;
d40a6898 4784 }
c4f035c6 4785
d40a6898
PB		 4786 if (ctxt->d & Mmx) {
4787 rc = flush_pending_x87_faults(ctxt);
4788 if (rc != X86EMUL_CONTINUE)
4789 goto done;
4790 /*
4791 * Now that we know the fpu is exception safe, we can fetch
4792 * operands from it.
4793 */
4794 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4795 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4796 if (!(ctxt->d & Mov))
4797 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4798 }
e92805ac 4799
685bbf4a 4800 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4801 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4802 X86_ICPT_PRE_EXCEPT);
4803 if (rc != X86EMUL_CONTINUE)
4804 goto done;
4805 }
8ea7d6ae 4806
64a38292
NA		 4807 /* Instruction can only be executed in protected mode */
4808 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4809 rc = emulate_ud(ctxt);
4810 goto done;
4811 }
4812
d40a6898
PB		 4813 /* Privileged instruction can be executed only in CPL=0 */
4814 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4815 if (ctxt->d & PrivUD)
4816 rc = emulate_ud(ctxt);
4817 else
4818 rc = emulate_gp(ctxt, 0);
d09beabd 4819 goto done;
d40a6898 4820 }
d09beabd 4821
d40a6898 4822 /* Do instruction specific permission checks */
685bbf4a 4823 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4824 rc = ctxt->check_perm(ctxt);
4825 if (rc != X86EMUL_CONTINUE)
4826 goto done;
4827 }
4828
685bbf4a 4829 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4830 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4831 X86_ICPT_POST_EXCEPT);
4832 if (rc != X86EMUL_CONTINUE)
4833 goto done;
4834 }
4835
4836 if (ctxt->rep_prefix && (ctxt->d & String)) {
4837 /* All REP prefixes have the same first termination condition */
4838 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4839 ctxt->eip = ctxt->_eip;
4467c3f1 4840 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4841 goto done;
4842 }
b9fa9d6b 4843 }
b9fa9d6b
AK		 4844 }
4845
9dac77fa
AK		 4846 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4847 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4848 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4849 if (rc != X86EMUL_CONTINUE)
8b4caf66 4850 goto done;
9dac77fa 4851 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4852 }
4853
9dac77fa
AK		 4854 if (ctxt->src2.type == OP_MEM) {
4855 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4856 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4857 if (rc != X86EMUL_CONTINUE)
4858 goto done;
4859 }
4860
9dac77fa 4861 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4862 goto special_insn;
4863
4864
9dac77fa 4865 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4866 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4867 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4868 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4869 if (rc != X86EMUL_CONTINUE)
4870 goto done;
038e51de 4871 }
9dac77fa 4872 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4873
018a98db
AK		 4874special_insn:
4875
685bbf4a 4876 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4877 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4878 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4879 if (rc != X86EMUL_CONTINUE)
4880 goto done;
4881 }
4882
b9a1ecb9
NA		 4883 if (ctxt->rep_prefix && (ctxt->d & String))
4884 ctxt->eflags |= EFLG_RF;
4885 else
4886 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4887
9dac77fa 4888 if (ctxt->execute) {
e28bbd44
AK		 4889 if (ctxt->d & Fastop) {
4890 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4891 rc = fastop(ctxt, fop);
4892 if (rc != X86EMUL_CONTINUE)
4893 goto done;
4894 goto writeback;
4895 }
9dac77fa 4896 rc = ctxt->execute(ctxt);
ef65c889
AK		 4897 if (rc != X86EMUL_CONTINUE)
4898 goto done;
4899 goto writeback;
4900 }
4901
1ce19dc1 4902 if (ctxt->opcode_len == 2)
6aa8b732 4903 goto twobyte_insn;
0bc5eedb
BP		 4904 else if (ctxt->opcode_len == 3)
4905 goto threebyte_insn;
6aa8b732 4906
9dac77fa 4907 switch (ctxt->b) {
6aa8b732 4908 case 0x63: /* movsxd */
8b4caf66 4909 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4910 goto cannot_emulate;
9dac77fa 4911 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4912 break;
b2833e3c 4913 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4914 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4915 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4916 break;
7e0b54b1 4917 case 0x8d: /* lea r16/r32, m */
9dac77fa 4918 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4919 break;
3d9e77df 4920 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4921 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4922 ctxt->dst.type = OP_NONE;
4923 else
4924 rc = em_xchg(ctxt);
e4f973ae 4925 break;
e8b6fa70 4926 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4927 switch (ctxt->op_bytes) {
4928 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4929 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4930 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4931 }
4932 break;
6e154e56 4933 case 0xcc: /* int3 */
5c5df76b
TY		 4934 rc = emulate_int(ctxt, 3);
4935 break;
6e154e56 4936 case 0xcd: /* int n */
9dac77fa 4937 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4938 break;
4939 case 0xce: /* into */
5c5df76b
TY		 4940 if (ctxt->eflags & EFLG_OF)
4941 rc = emulate_int(ctxt, 4);
6e154e56 4942 break;
1a52e051 4943 case 0xe9: /* jmp rel */
db5b0762 4944 case 0xeb: /* jmp rel short */
234f3ce4 4945 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4946 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4947 break;
111de5d6 4948 case 0xf4: /* hlt */
6c3287f7 4949 ctxt->ops->halt(ctxt);
19fdfa0d 4950 break;
111de5d6
AK		 4951 case 0xf5: /* cmc */
4952 /* complement carry flag from eflags reg */
4953 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4954 break;
4955 case 0xf8: /* clc */
4956 ctxt->eflags &= ~EFLG_CF;
111de5d6 4957 break;
8744aa9a
MG		 4958 case 0xf9: /* stc */
4959 ctxt->eflags |= EFLG_CF;
4960 break;
fb4616f4
MG		 4961 case 0xfc: /* cld */
4962 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4963 break;
4964 case 0xfd: /* std */
4965 ctxt->eflags |= EFLG_DF;
fb4616f4 4966 break;
91269b8f
AK		 4967 default:
4968 goto cannot_emulate;
6aa8b732 4969 }
018a98db 4970
7d9ddaed
AK		 4971 if (rc != X86EMUL_CONTINUE)
4972 goto done;
4973
018a98db 4974writeback:
fb32b1ed
AK		 4975 if (ctxt->d & SrcWrite) {
4976 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4977 rc = writeback(ctxt, &ctxt->src);
4978 if (rc != X86EMUL_CONTINUE)
4979 goto done;
4980 }
ee212297
NA		 4981 if (!(ctxt->d & NoWrite)) {
4982 rc = writeback(ctxt, &ctxt->dst);
4983 if (rc != X86EMUL_CONTINUE)
4984 goto done;
4985 }
018a98db 4986
5cd21917
GN		 4987 /*
4988 * restore dst type in case the decoding will be reused
4989 * (happens for string instruction )
4990 */
9dac77fa 4991 ctxt->dst.type = saved_dst_type;
5cd21917 4992
9dac77fa 4993 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4994 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4995
9dac77fa 4996 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4997 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4998
9dac77fa 4999 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5000 unsigned int count;
9dac77fa 5001 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5002 if ((ctxt->d & SrcMask) == SrcSI)
5003 count = ctxt->src.count;
5004 else
5005 count = ctxt->dst.count;
01485a22 5006 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5007
d2ddd1c4
GN		 5008 if (!string_insn_completed(ctxt)) {
5009 /*
5010 * Re-enter guest when pio read ahead buffer is empty
5011 * or, if it is not used, after each 1024 iteration.
5012 */
dd856efa 5013 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5014 (r->end == 0 || r->end != r->pos)) {
5015 /*
5016 * Reset read cache. Usually happens before
5017 * decode, but since instruction is restarted
5018 * we have to do it here.
5019 */
9dac77fa 5020 ctxt->mem_read.end = 0;
dd856efa 5021 writeback_registers(ctxt);
d2ddd1c4
GN		 5022 return EMULATION_RESTART;
5023 }
5024 goto done; /* skip rip writeback */
0fa6ccbd 5025 }
b9a1ecb9 5026 ctxt->eflags &= ~EFLG_RF;
5cd21917 5027 }
d2ddd1c4 5028
9dac77fa 5029 ctxt->eip = ctxt->_eip;
018a98db
AK		 5030
5031done:
e0ad0b47
PB		 5032 if (rc == X86EMUL_PROPAGATE_FAULT) {
5033 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5034 ctxt->have_exception = true;
e0ad0b47 5035 }
775fde86
JR		 5036 if (rc == X86EMUL_INTERCEPTED)
5037 return EMULATION_INTERCEPTED;
5038
dd856efa
AK		 5039 if (rc == X86EMUL_CONTINUE)
5040 writeback_registers(ctxt);
5041
d2ddd1c4 5042 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5043
5044twobyte_insn:
9dac77fa 5045 switch (ctxt->b) {
018a98db 5046 case 0x09: /* wbinvd */
cfb22375 5047 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5048 break;
5049 case 0x08: /* invd */
018a98db
AK		 5050 case 0x0d: /* GrpP (prefetch) */
5051 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5052 case 0x1f: /* nop */
018a98db
AK		 5053 break;
5054 case 0x20: /* mov cr, reg */
9dac77fa 5055 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5056 break;
6aa8b732 5057 case 0x21: /* mov from dr to reg */
9dac77fa 5058 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5059 break;
6aa8b732 5060 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5061 if (test_cc(ctxt->b, ctxt->eflags))
5062 ctxt->dst.val = ctxt->src.val;
5063 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5064 ctxt->op_bytes != 4)
9dac77fa 5065 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5066 break;
b2833e3c 5067 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5068 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5069 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5070 break;
ee45b58e 5071 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5072 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5073 break;
6aa8b732 5074 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5075 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5076 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5077 : (u16) ctxt->src.val;
6aa8b732 5078 break;
6aa8b732 5079 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5080 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5081 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5082 (s16) ctxt->src.val;
6aa8b732 5083 break;
91269b8f
AK		 5084 default:
5085 goto cannot_emulate;
6aa8b732 5086 }
7d9ddaed 5087
0bc5eedb
BP		 5088threebyte_insn:
5089
7d9ddaed
AK		 5090 if (rc != X86EMUL_CONTINUE)
5091 goto done;
5092
6aa8b732
AK		 5093 goto writeback;
5094
5095cannot_emulate:
a0c0ab2f 5096 return EMULATION_FAILED;
6aa8b732 5097}
dd856efa
AK		 5098
5099void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5100{
5101 invalidate_registers(ctxt);
5102}
5103
5104void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5105{
5106 writeback_registers(ctxt);
5107}
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