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KVM: x86 emulator: drop unused old-style inline emulation
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 133#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
6aa8b732 164
820207c8
AK		 165#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
166
d0e53325
AK		 167#define X2(x...) x, x
168#define X3(x...) X2(x), x
169#define X4(x...) X2(x), X2(x)
170#define X5(x...) X4(x), x
171#define X6(x...) X4(x), X2(x)
172#define X7(x...) X4(x), X3(x)
173#define X8(x...) X4(x), X4(x)
174#define X16(x...) X8(x), X8(x)
83babbca 175
e28bbd44
AK		 176#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177#define FASTOP_SIZE 8
178
179/*
180 * fastop functions have a special calling convention:
181 *
017da7b6
AK		 182 * dst: rax (in/out)
183 * src: rdx (in/out)
e28bbd44
AK		 184 * src2: rcx (in)
185 * flags: rflags (in/out)
b8c0b6ae 186 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 187 *
188 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
189 * different operand sizes can be reached by calculation, rather than a jump
190 * table (which would be bigger than the code).
191 *
192 * fastop functions are declared as taking a never-defined fastop parameter,
193 * so they can't be called from C directly.
194 */
195
196struct fastop;
197
d65b1dee 198struct opcode {
b1ea50b2
AK		 199 u64 flags : 56;
200 u64 intercept : 8;
120df890 201 union {
ef65c889 202 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 203 const struct opcode *group;
204 const struct group_dual *gdual;
205 const struct gprefix *gprefix;
045a282c 206 const struct escape *esc;
e28bbd44 207 void (*fastop)(struct fastop *fake);
120df890 208 } u;
d09beabd 209 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 210};
211
212struct group_dual {
213 struct opcode mod012[8];
214 struct opcode mod3[8];
d65b1dee
AK		 215};
216
0d7cdee8
AK		 217struct gprefix {
218 struct opcode pfx_no;
219 struct opcode pfx_66;
220 struct opcode pfx_f2;
221 struct opcode pfx_f3;
222};
223
045a282c
GN		 224struct escape {
225 struct opcode op[8];
226 struct opcode high[64];
227};
228
6aa8b732 229/* EFLAGS bit definitions. */
d4c6a154
GN		 230#define EFLG_ID (1<<21)
231#define EFLG_VIP (1<<20)
232#define EFLG_VIF (1<<19)
233#define EFLG_AC (1<<18)
b1d86143
AP		 234#define EFLG_VM (1<<17)
235#define EFLG_RF (1<<16)
d4c6a154
GN		 236#define EFLG_IOPL (3<<12)
237#define EFLG_NT (1<<14)
6aa8b732
AK		 238#define EFLG_OF (1<<11)
239#define EFLG_DF (1<<10)
b1d86143 240#define EFLG_IF (1<<9)
d4c6a154 241#define EFLG_TF (1<<8)
6aa8b732
AK		 242#define EFLG_SF (1<<7)
243#define EFLG_ZF (1<<6)
244#define EFLG_AF (1<<4)
245#define EFLG_PF (1<<2)
246#define EFLG_CF (1<<0)
247
62bd430e
MG		 248#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
249#define EFLG_RESERVED_ONE_MASK 2
250
dd856efa
AK		 251static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
252{
253 if (!(ctxt->regs_valid & (1 << nr))) {
254 ctxt->regs_valid |= 1 << nr;
255 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
256 }
257 return ctxt->_regs[nr];
258}
259
260static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
261{
262 ctxt->regs_valid |= 1 << nr;
263 ctxt->regs_dirty |= 1 << nr;
264 return &ctxt->_regs[nr];
265}
266
267static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
268{
269 reg_read(ctxt, nr);
270 return reg_write(ctxt, nr);
271}
272
273static void writeback_registers(struct x86_emulate_ctxt *ctxt)
274{
275 unsigned reg;
276
277 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
278 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
279}
280
281static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
282{
283 ctxt->regs_dirty = 0;
284 ctxt->regs_valid = 0;
285}
286
6aa8b732
AK		 287/*
288 * These EFLAGS bits are restored from saved value during emulation, and
289 * any changes are written back to the saved value after emulation.
290 */
291#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
292
dda96d8f
AK		 293#ifdef CONFIG_X86_64
294#define ON64(x) x
295#else
296#define ON64(x)
297#endif
298
4d758349
AK		 299static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
300
b7d491e7
AK		 301#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
302#define FOP_RET "ret \n\t"
303
304#define FOP_START(op) \
305 extern void em_##op(struct fastop *fake); \
306 asm(".pushsection .text, \"ax\" \n\t" \
307 ".global em_" #op " \n\t" \
308 FOP_ALIGN \
309 "em_" #op ": \n\t"
310
311#define FOP_END \
312 ".popsection")
313
0bdea068
AK		 314#define FOPNOP() FOP_ALIGN FOP_RET
315
b7d491e7 316#define FOP1E(op, dst) \
b8c0b6ae
AK		 317 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
318
319#define FOP1EEX(op, dst) \
320 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 321
322#define FASTOP1(op) \
323 FOP_START(op) \
324 FOP1E(op##b, al) \
325 FOP1E(op##w, ax) \
326 FOP1E(op##l, eax) \
327 ON64(FOP1E(op##q, rax)) \
328 FOP_END
329
b9fa409b
AK		 330/* 1-operand, using src2 (for MUL/DIV r/m) */
331#define FASTOP1SRC2(op, name) \
332 FOP_START(name) \
333 FOP1E(op, cl) \
334 FOP1E(op, cx) \
335 FOP1E(op, ecx) \
336 ON64(FOP1E(op, rcx)) \
337 FOP_END
338
b8c0b6ae
AK		 339/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
340#define FASTOP1SRC2EX(op, name) \
341 FOP_START(name) \
342 FOP1EEX(op, cl) \
343 FOP1EEX(op, cx) \
344 FOP1EEX(op, ecx) \
345 ON64(FOP1EEX(op, rcx)) \
346 FOP_END
347
f7857f35
AK		 348#define FOP2E(op, dst, src) \
349 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
350
351#define FASTOP2(op) \
352 FOP_START(op) \
017da7b6
AK		 353 FOP2E(op##b, al, dl) \
354 FOP2E(op##w, ax, dx) \
355 FOP2E(op##l, eax, edx) \
356 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 357 FOP_END
358
11c363ba
AK		 359/* 2 operand, word only */
360#define FASTOP2W(op) \
361 FOP_START(op) \
362 FOPNOP() \
017da7b6
AK		 363 FOP2E(op##w, ax, dx) \
364 FOP2E(op##l, eax, edx) \
365 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 366 FOP_END
367
007a3b54
AK		 368/* 2 operand, src is CL */
369#define FASTOP2CL(op) \
370 FOP_START(op) \
371 FOP2E(op##b, al, cl) \
372 FOP2E(op##w, ax, cl) \
373 FOP2E(op##l, eax, cl) \
374 ON64(FOP2E(op##q, rax, cl)) \
375 FOP_END
376
0bdea068
AK		 377#define FOP3E(op, dst, src, src2) \
378 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
379
380/* 3-operand, word-only, src2=cl */
381#define FASTOP3WCL(op) \
382 FOP_START(op) \
383 FOPNOP() \
017da7b6
AK		 384 FOP3E(op##w, ax, dx, cl) \
385 FOP3E(op##l, eax, edx, cl) \
386 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 387 FOP_END
388
9ae9feba
AK		 389/* Special case for SETcc - 1 instruction per cc */
390#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
391
b8c0b6ae
AK		 392asm(".global kvm_fastop_exception \n"
393 "kvm_fastop_exception: xor %esi, %esi; ret");
394
9ae9feba
AK		 395FOP_START(setcc)
396FOP_SETCC(seto)
397FOP_SETCC(setno)
398FOP_SETCC(setc)
399FOP_SETCC(setnc)
400FOP_SETCC(setz)
401FOP_SETCC(setnz)
402FOP_SETCC(setbe)
403FOP_SETCC(setnbe)
404FOP_SETCC(sets)
405FOP_SETCC(setns)
406FOP_SETCC(setp)
407FOP_SETCC(setnp)
408FOP_SETCC(setl)
409FOP_SETCC(setnl)
410FOP_SETCC(setle)
411FOP_SETCC(setnle)
412FOP_END;
413
326f578f
PB		 414FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
415FOP_END;
416
8a76d7f2
JR		 417static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
418 enum x86_intercept intercept,
419 enum x86_intercept_stage stage)
420{
421 struct x86_instruction_info info = {
422 .intercept = intercept,
9dac77fa
AK		 423 .rep_prefix = ctxt->rep_prefix,
424 .modrm_mod = ctxt->modrm_mod,
425 .modrm_reg = ctxt->modrm_reg,
426 .modrm_rm = ctxt->modrm_rm,
427 .src_val = ctxt->src.val64,
428 .src_bytes = ctxt->src.bytes,
429 .dst_bytes = ctxt->dst.bytes,
430 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 431 .next_rip = ctxt->eip,
432 };
433
2953538e 434 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 435}
436
f47cfa31
AK		 437static void assign_masked(ulong *dest, ulong src, ulong mask)
438{
439 *dest = (*dest & ~mask) | (src & mask);
440}
441
9dac77fa 442static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 443{
9dac77fa 444 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 445}
446
f47cfa31
AK		 447static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
448{
449 u16 sel;
450 struct desc_struct ss;
451
452 if (ctxt->mode == X86EMUL_MODE_PROT64)
453 return ~0UL;
454 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
455 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
456}
457
612e89f0
AK		 458static int stack_size(struct x86_emulate_ctxt *ctxt)
459{
460 return (__fls(stack_mask(ctxt)) + 1) >> 3;
461}
462
6aa8b732 463/* Access/update address held in a register, based on addressing mode. */
e4706772 464static inline unsigned long
9dac77fa 465address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 466{
9dac77fa 467 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 468 return reg;
469 else
9dac77fa 470 return reg & ad_mask(ctxt);
e4706772
HH		 471}
472
473static inline unsigned long
9dac77fa 474register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 475{
9dac77fa 476 return address_mask(ctxt, reg);
e4706772
HH		 477}
478
5ad105e5
AK		 479static void masked_increment(ulong *reg, ulong mask, int inc)
480{
481 assign_masked(reg, *reg + inc, mask);
482}
483
7a957275 484static inline void
9dac77fa 485register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 486{
5ad105e5
AK		 487 ulong mask;
488
9dac77fa 489 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 490 mask = ~0UL;
7a957275 491 else
5ad105e5
AK		 492 mask = ad_mask(ctxt);
493 masked_increment(reg, mask, inc);
494}
495
496static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
497{
dd856efa 498 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 499}
6aa8b732 500
9dac77fa 501static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 502{
9dac77fa 503 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 504}
098c937b 505
56697687
AK		 506static u32 desc_limit_scaled(struct desc_struct *desc)
507{
508 u32 limit = get_desc_limit(desc);
509
510 return desc->g ? (limit << 12) | 0xfff : limit;
511}
512
9dac77fa 513static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 514{
9dac77fa
AK		 515 ctxt->has_seg_override = true;
516 ctxt->seg_override = seg;
7a5b56df
AK		 517}
518
7b105ca2 519static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 520{
521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
522 return 0;
523
7b105ca2 524 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 525}
526
9dac77fa 527static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 528{
9dac77fa 529 if (!ctxt->has_seg_override)
7a5b56df
AK		 530 return 0;
531
9dac77fa 532 return ctxt->seg_override;
7a5b56df
AK		 533}
534
35d3d4a1
AK		 535static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
536 u32 error, bool valid)
54b8486f 537{
da9cb575
AK		 538 ctxt->exception.vector = vec;
539 ctxt->exception.error_code = error;
540 ctxt->exception.error_code_valid = valid;
35d3d4a1 541 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 542}
543
3b88e41a
JR		 544static int emulate_db(struct x86_emulate_ctxt *ctxt)
545{
546 return emulate_exception(ctxt, DB_VECTOR, 0, false);
547}
548
35d3d4a1 549static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 552}
553
618ff15d
AK		 554static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
555{
556 return emulate_exception(ctxt, SS_VECTOR, err, true);
557}
558
35d3d4a1 559static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 560{
35d3d4a1 561 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 562}
563
35d3d4a1 564static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 565{
35d3d4a1 566 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 567}
568
34d1f490
AK		 569static int emulate_de(struct x86_emulate_ctxt *ctxt)
570{
35d3d4a1 571 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 572}
573
1253791d
AK		 574static int emulate_nm(struct x86_emulate_ctxt *ctxt)
575{
576 return emulate_exception(ctxt, NM_VECTOR, 0, false);
577}
578
1aa36616
AK		 579static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
580{
581 u16 selector;
582 struct desc_struct desc;
583
584 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
585 return selector;
586}
587
588static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
589 unsigned seg)
590{
591 u16 dummy;
592 u32 base3;
593 struct desc_struct desc;
594
595 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
596 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
597}
598
1c11b376
AK		 599/*
600 * x86 defines three classes of vector instructions: explicitly
601 * aligned, explicitly unaligned, and the rest, which change behaviour
602 * depending on whether they're AVX encoded or not.
603 *
604 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
605 * subject to the same check.
606 */
607static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
608{
609 if (likely(size < 16))
610 return false;
611
612 if (ctxt->d & Aligned)
613 return true;
614 else if (ctxt->d & Unaligned)
615 return false;
616 else if (ctxt->d & Avx)
617 return false;
618 else
619 return true;
620}
621
3d9b938e 622static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 623 struct segmented_address addr,
3d9b938e 624 unsigned size, bool write, bool fetch,
52fd8b44
AK		 625 ulong *linear)
626{
618ff15d
AK		 627 struct desc_struct desc;
628 bool usable;
52fd8b44 629 ulong la;
618ff15d 630 u32 lim;
1aa36616 631 u16 sel;
3a78a4f4 632 unsigned cpl;
52fd8b44 633
7b105ca2 634 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 635 switch (ctxt->mode) {
618ff15d
AK		 636 case X86EMUL_MODE_PROT64:
637 if (((signed long)la << 16) >> 16 != la)
638 return emulate_gp(ctxt, 0);
639 break;
640 default:
1aa36616
AK		 641 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
642 addr.seg);
618ff15d
AK		 643 if (!usable)
644 goto bad;
58b7825b
GN		 645 /* code segment in protected mode or read-only data segment */
646 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
647 || !(desc.type & 2)) && write)
618ff15d
AK		 648 goto bad;
649 /* unreadable code segment */
3d9b938e 650 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 651 goto bad;
652 lim = desc_limit_scaled(&desc);
653 if ((desc.type & 8) || !(desc.type & 4)) {
654 /* expand-up segment */
655 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
656 goto bad;
657 } else {
fc058680 658 /* expand-down segment */
618ff15d
AK		 659 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
660 goto bad;
661 lim = desc.d ? 0xffffffff : 0xffff;
662 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
663 goto bad;
664 }
717746e3 665 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 666 if (!(desc.type & 8)) {
667 /* data segment */
668 if (cpl > desc.dpl)
669 goto bad;
670 } else if ((desc.type & 8) && !(desc.type & 4)) {
671 /* nonconforming code segment */
672 if (cpl != desc.dpl)
673 goto bad;
674 } else if ((desc.type & 8) && (desc.type & 4)) {
675 /* conforming code segment */
676 if (cpl < desc.dpl)
677 goto bad;
678 }
679 break;
680 }
9dac77fa 681 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 682 la &= (u32)-1;
1c11b376
AK		 683 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
684 return emulate_gp(ctxt, 0);
52fd8b44
AK		 685 *linear = la;
686 return X86EMUL_CONTINUE;
618ff15d
AK		 687bad:
688 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 689 return emulate_ss(ctxt, sel);
618ff15d 690 else
0afbe2f8 691 return emulate_gp(ctxt, sel);
52fd8b44
AK		 692}
693
3d9b938e
NE		 694static int linearize(struct x86_emulate_ctxt *ctxt,
695 struct segmented_address addr,
696 unsigned size, bool write,
697 ulong *linear)
698{
699 return __linearize(ctxt, addr, size, write, false, linear);
700}
701
702
3ca3ac4d
AK		 703static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
704 struct segmented_address addr,
705 void *data,
706 unsigned size)
707{
9fa088f4
AK		 708 int rc;
709 ulong linear;
710
83b8795a 711 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 712 if (rc != X86EMUL_CONTINUE)
713 return rc;
0f65dd70 714 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 715}
716
807941b1
TY		 717/*
718 * Fetch the next byte of the instruction being emulated which is pointed to
719 * by ctxt->_eip, then increment ctxt->_eip.
720 *
721 * Also prefetch the remaining bytes of the instruction without crossing page
722 * boundary if they are not in fetch_cache yet.
723 */
724static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 725{
9dac77fa 726 struct fetch_cache *fc = &ctxt->fetch;
62266869 727 int rc;
2fb53ad8 728 int size, cur_size;
62266869 729
807941b1 730 if (ctxt->_eip == fc->end) {
3d9b938e 731 unsigned long linear;
807941b1
TY		 732 struct segmented_address addr = { .seg = VCPU_SREG_CS,
733 .ea = ctxt->_eip };
2fb53ad8 734 cur_size = fc->end - fc->start;
807941b1
TY		 735 size = min(15UL - cur_size,
736 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 737 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 738 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 739 return rc;
ef5d75cc
TY		 740 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
741 size, &ctxt->exception);
7d88bb48 742 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 743 return rc;
2fb53ad8 744 fc->end += size;
62266869 745 }
807941b1
TY		 746 *dest = fc->data[ctxt->_eip - fc->start];
747 ctxt->_eip++;
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK		 749}
750
751static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 752 void *dest, unsigned size)
62266869 753{
3e2815e9 754 int rc;
62266869 755
eb3c79e6 756 /* x86 instructions are limited to 15 bytes. */
7d88bb48 757 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 758 return X86EMUL_UNHANDLEABLE;
62266869 759 while (size--) {
807941b1 760 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 761 if (rc != X86EMUL_CONTINUE)
62266869
AK		 762 return rc;
763 }
3e2815e9 764 return X86EMUL_CONTINUE;
62266869
AK		 765}
766
67cbc90d 767/* Fetch next part of the instruction being emulated. */
e85a1085 768#define insn_fetch(_type, _ctxt) \
67cbc90d 769({ unsigned long _x; \
e85a1085 770 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 771 if (rc != X86EMUL_CONTINUE) \
772 goto done; \
67cbc90d
TY		 773 (_type)_x; \
774})
775
807941b1
TY		 776#define insn_fetch_arr(_arr, _size, _ctxt) \
777({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 778 if (rc != X86EMUL_CONTINUE) \
779 goto done; \
67cbc90d
TY		 780})
781
1e3c5cb0
RR		 782/*
783 * Given the 'reg' portion of a ModRM byte, and a register block, return a
784 * pointer into the block that addresses the relevant register.
785 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
786 */
dd856efa 787static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 788 int highbyte_regs)
6aa8b732
AK		 789{
790 void *p;
791
6aa8b732 792 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 793 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
794 else
795 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 796 return p;
797}
798
799static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 800 struct segmented_address addr,
6aa8b732
AK		 801 u16 *size, unsigned long *address, int op_bytes)
802{
803 int rc;
804
805 if (op_bytes == 2)
806 op_bytes = 3;
807 *address = 0;
3ca3ac4d 808 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 809 if (rc != X86EMUL_CONTINUE)
6aa8b732 810 return rc;
30b31ab6 811 addr.ea += 2;
3ca3ac4d 812 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 813 return rc;
814}
815
34b77652
AK		 816FASTOP2(add);
817FASTOP2(or);
818FASTOP2(adc);
819FASTOP2(sbb);
820FASTOP2(and);
821FASTOP2(sub);
822FASTOP2(xor);
823FASTOP2(cmp);
824FASTOP2(test);
825
b9fa409b
AK		 826FASTOP1SRC2(mul, mul_ex);
827FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 828FASTOP1SRC2EX(div, div_ex);
829FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 830
34b77652
AK		 831FASTOP3WCL(shld);
832FASTOP3WCL(shrd);
833
834FASTOP2W(imul);
835
836FASTOP1(not);
837FASTOP1(neg);
838FASTOP1(inc);
839FASTOP1(dec);
840
841FASTOP2CL(rol);
842FASTOP2CL(ror);
843FASTOP2CL(rcl);
844FASTOP2CL(rcr);
845FASTOP2CL(shl);
846FASTOP2CL(shr);
847FASTOP2CL(sar);
848
849FASTOP2W(bsf);
850FASTOP2W(bsr);
851FASTOP2W(bt);
852FASTOP2W(bts);
853FASTOP2W(btr);
854FASTOP2W(btc);
855
9ae9feba 856static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 857{
9ae9feba
AK		 858 u8 rc;
859 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 860
9ae9feba 861 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 862 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 863 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
864 return rc;
bbe9abbd
NK		 865}
866
91ff3cb4
AK		 867static void fetch_register_operand(struct operand *op)
868{
869 switch (op->bytes) {
870 case 1:
871 op->val = *(u8 *)op->addr.reg;
872 break;
873 case 2:
874 op->val = *(u16 *)op->addr.reg;
875 break;
876 case 4:
877 op->val = *(u32 *)op->addr.reg;
878 break;
879 case 8:
880 op->val = *(u64 *)op->addr.reg;
881 break;
882 }
883}
884
1253791d
AK		 885static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
886{
887 ctxt->ops->get_fpu(ctxt);
888 switch (reg) {
89a87c67
MK		 889 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
890 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
891 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
892 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
893 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
894 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
895 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
896 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 897#ifdef CONFIG_X86_64
89a87c67
MK		 898 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
899 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
900 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
901 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
902 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
903 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
904 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
905 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 906#endif
907 default: BUG();
908 }
909 ctxt->ops->put_fpu(ctxt);
910}
911
912static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
913 int reg)
914{
915 ctxt->ops->get_fpu(ctxt);
916 switch (reg) {
89a87c67
MK		 917 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
918 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
919 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
920 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
921 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
922 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
923 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
924 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 925#ifdef CONFIG_X86_64
89a87c67
MK		 926 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
927 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
928 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
929 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
930 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
931 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
932 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
933 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 934#endif
935 default: BUG();
936 }
937 ctxt->ops->put_fpu(ctxt);
938}
939
cbe2c9d3
AK		 940static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
941{
942 ctxt->ops->get_fpu(ctxt);
943 switch (reg) {
944 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
945 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
946 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
947 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
948 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
949 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
950 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
951 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
952 default: BUG();
953 }
954 ctxt->ops->put_fpu(ctxt);
955}
956
957static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
958{
959 ctxt->ops->get_fpu(ctxt);
960 switch (reg) {
961 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
962 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
963 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
964 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
965 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
966 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
967 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
968 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
969 default: BUG();
970 }
971 ctxt->ops->put_fpu(ctxt);
972}
973
045a282c
GN		 974static int em_fninit(struct x86_emulate_ctxt *ctxt)
975{
976 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
977 return emulate_nm(ctxt);
978
979 ctxt->ops->get_fpu(ctxt);
980 asm volatile("fninit");
981 ctxt->ops->put_fpu(ctxt);
982 return X86EMUL_CONTINUE;
983}
984
985static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
986{
987 u16 fcw;
988
989 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
990 return emulate_nm(ctxt);
991
992 ctxt->ops->get_fpu(ctxt);
993 asm volatile("fnstcw %0": "+m"(fcw));
994 ctxt->ops->put_fpu(ctxt);
995
996 /* force 2 byte destination */
997 ctxt->dst.bytes = 2;
998 ctxt->dst.val = fcw;
999
1000 return X86EMUL_CONTINUE;
1001}
1002
1003static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1004{
1005 u16 fsw;
1006
1007 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1008 return emulate_nm(ctxt);
1009
1010 ctxt->ops->get_fpu(ctxt);
1011 asm volatile("fnstsw %0": "+m"(fsw));
1012 ctxt->ops->put_fpu(ctxt);
1013
1014 /* force 2 byte destination */
1015 ctxt->dst.bytes = 2;
1016 ctxt->dst.val = fsw;
1017
1018 return X86EMUL_CONTINUE;
1019}
1020
1253791d 1021static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1022 struct operand *op)
3c118e24 1023{
9dac77fa
AK		 1024 unsigned reg = ctxt->modrm_reg;
1025 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1026
9dac77fa
AK		 1027 if (!(ctxt->d & ModRM))
1028 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1029
9dac77fa 1030 if (ctxt->d & Sse) {
1253791d
AK		 1031 op->type = OP_XMM;
1032 op->bytes = 16;
1033 op->addr.xmm = reg;
1034 read_sse_reg(ctxt, &op->vec_val, reg);
1035 return;
1036 }
cbe2c9d3
AK		 1037 if (ctxt->d & Mmx) {
1038 reg &= 7;
1039 op->type = OP_MM;
1040 op->bytes = 8;
1041 op->addr.mm = reg;
1042 return;
1043 }
1253791d 1044
3c118e24 1045 op->type = OP_REG;
2adb5ad9 1046 if (ctxt->d & ByteOp) {
dd856efa 1047 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1048 op->bytes = 1;
1049 } else {
dd856efa 1050 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1051 op->bytes = ctxt->op_bytes;
3c118e24 1052 }
91ff3cb4 1053 fetch_register_operand(op);
3c118e24
AK		 1054 op->orig_val = op->val;
1055}
1056
a6e3407b
AK		 1057static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1058{
1059 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1060 ctxt->modrm_seg = VCPU_SREG_SS;
1061}
1062
1c73ef66 1063static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1064 struct operand *op)
1c73ef66 1065{
1c73ef66 1066 u8 sib;
f5b4edcd 1067 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1068 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1069 ulong modrm_ea = 0;
1c73ef66 1070
9dac77fa
AK		 1071 if (ctxt->rex_prefix) {
1072 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1073 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1074 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1075 }
1076
9dac77fa
AK		 1077 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1078 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1079 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1080 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1081
9dac77fa 1082 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1083 op->type = OP_REG;
9dac77fa 1084 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1085 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1086 if (ctxt->d & Sse) {
1253791d
AK		 1087 op->type = OP_XMM;
1088 op->bytes = 16;
9dac77fa
AK		 1089 op->addr.xmm = ctxt->modrm_rm;
1090 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1091 return rc;
1092 }
cbe2c9d3
AK		 1093 if (ctxt->d & Mmx) {
1094 op->type = OP_MM;
1095 op->bytes = 8;
1096 op->addr.xmm = ctxt->modrm_rm & 7;
1097 return rc;
1098 }
2dbd0dd7 1099 fetch_register_operand(op);
1c73ef66
AK		 1100 return rc;
1101 }
1102
2dbd0dd7
AK		 1103 op->type = OP_MEM;
1104
9dac77fa 1105 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1106 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1107 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1108 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1109 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1110
1111 /* 16-bit ModR/M decode. */
9dac77fa 1112 switch (ctxt->modrm_mod) {
1c73ef66 1113 case 0:
9dac77fa 1114 if (ctxt->modrm_rm == 6)
e85a1085 1115 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1116 break;
1117 case 1:
e85a1085 1118 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1119 break;
1120 case 2:
e85a1085 1121 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1122 break;
1123 }
9dac77fa 1124 switch (ctxt->modrm_rm) {
1c73ef66 1125 case 0:
2dbd0dd7 1126 modrm_ea += bx + si;
1c73ef66
AK		 1127 break;
1128 case 1:
2dbd0dd7 1129 modrm_ea += bx + di;
1c73ef66
AK		 1130 break;
1131 case 2:
2dbd0dd7 1132 modrm_ea += bp + si;
1c73ef66
AK		 1133 break;
1134 case 3:
2dbd0dd7 1135 modrm_ea += bp + di;
1c73ef66
AK		 1136 break;
1137 case 4:
2dbd0dd7 1138 modrm_ea += si;
1c73ef66
AK		 1139 break;
1140 case 5:
2dbd0dd7 1141 modrm_ea += di;
1c73ef66
AK		 1142 break;
1143 case 6:
9dac77fa 1144 if (ctxt->modrm_mod != 0)
2dbd0dd7 1145 modrm_ea += bp;
1c73ef66
AK		 1146 break;
1147 case 7:
2dbd0dd7 1148 modrm_ea += bx;
1c73ef66
AK		 1149 break;
1150 }
9dac77fa
AK		 1151 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1152 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1153 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1154 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1155 } else {
1156 /* 32/64-bit ModR/M decode. */
9dac77fa 1157 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1158 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1159 index_reg |= (sib >> 3) & 7;
1160 base_reg |= sib & 7;
1161 scale = sib >> 6;
1162
9dac77fa 1163 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1165 else {
dd856efa 1166 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1167 adjust_modrm_seg(ctxt, base_reg);
1168 }
dc71d0f1 1169 if (index_reg != 4)
dd856efa 1170 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1171 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1172 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1173 ctxt->rip_relative = 1;
a6e3407b
AK		 1174 } else {
1175 base_reg = ctxt->modrm_rm;
dd856efa 1176 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1177 adjust_modrm_seg(ctxt, base_reg);
1178 }
9dac77fa 1179 switch (ctxt->modrm_mod) {
1c73ef66 1180 case 0:
9dac77fa 1181 if (ctxt->modrm_rm == 5)
e85a1085 1182 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1183 break;
1184 case 1:
e85a1085 1185 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1186 break;
1187 case 2:
e85a1085 1188 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1189 break;
1190 }
1191 }
90de84f5 1192 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1193done:
1194 return rc;
1195}
1196
1197static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1198 struct operand *op)
1c73ef66 1199{
3e2815e9 1200 int rc = X86EMUL_CONTINUE;
1c73ef66 1201
2dbd0dd7 1202 op->type = OP_MEM;
9dac77fa 1203 switch (ctxt->ad_bytes) {
1c73ef66 1204 case 2:
e85a1085 1205 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1206 break;
1207 case 4:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1209 break;
1210 case 8:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1212 break;
1213 }
1214done:
1215 return rc;
1216}
1217
9dac77fa 1218static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1219{
7129eeca 1220 long sv = 0, mask;
35c843c4 1221
9dac77fa
AK		 1222 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1223 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1224
9dac77fa
AK		 1225 if (ctxt->src.bytes == 2)
1226 sv = (s16)ctxt->src.val & (s16)mask;
1227 else if (ctxt->src.bytes == 4)
1228 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1229
9dac77fa 1230 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1231 }
ba7ff2b7
WY		 1232
1233 /* only subword offset */
9dac77fa 1234 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1235}
1236
dde7e6d1 1237static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1238 unsigned long addr, void *dest, unsigned size)
6aa8b732 1239{
dde7e6d1 1240 int rc;
9dac77fa 1241 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1242
f23b070e
XG		 1243 if (mc->pos < mc->end)
1244 goto read_cached;
6aa8b732 1245
f23b070e
XG		 1246 WARN_ON((mc->end + size) >= sizeof(mc->data));
1247
1248 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1249 &ctxt->exception);
1250 if (rc != X86EMUL_CONTINUE)
1251 return rc;
1252
1253 mc->end += size;
1254
1255read_cached:
1256 memcpy(dest, mc->data + mc->pos, size);
1257 mc->pos += size;
dde7e6d1
AK		 1258 return X86EMUL_CONTINUE;
1259}
6aa8b732 1260
3ca3ac4d
AK		 1261static int segmented_read(struct x86_emulate_ctxt *ctxt,
1262 struct segmented_address addr,
1263 void *data,
1264 unsigned size)
1265{
9fa088f4
AK		 1266 int rc;
1267 ulong linear;
1268
83b8795a 1269 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
7b105ca2 1272 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1273}
1274
1275static int segmented_write(struct x86_emulate_ctxt *ctxt,
1276 struct segmented_address addr,
1277 const void *data,
1278 unsigned size)
1279{
9fa088f4
AK		 1280 int rc;
1281 ulong linear;
1282
83b8795a 1283 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
0f65dd70
AK		 1286 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1287 &ctxt->exception);
3ca3ac4d
AK		 1288}
1289
1290static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1291 struct segmented_address addr,
1292 const void *orig_data, const void *data,
1293 unsigned size)
1294{
9fa088f4
AK		 1295 int rc;
1296 ulong linear;
1297
83b8795a 1298 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
0f65dd70
AK		 1301 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1302 size, &ctxt->exception);
3ca3ac4d
AK		 1303}
1304
dde7e6d1 1305static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1306 unsigned int size, unsigned short port,
1307 void *dest)
1308{
9dac77fa 1309 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1310
dde7e6d1 1311 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1312 unsigned int in_page, n;
9dac77fa 1313 unsigned int count = ctxt->rep_prefix ?
dd856efa 1314 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1315 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1316 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1317 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1318 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1319 count);
1320 if (n == 0)
1321 n = 1;
1322 rc->pos = rc->end = 0;
7b105ca2 1323 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1324 return 0;
1325 rc->end = n * size;
6aa8b732
AK		 1326 }
1327
b3356bf0
GN		 1328 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1329 ctxt->dst.data = rc->data + rc->pos;
1330 ctxt->dst.type = OP_MEM_STR;
1331 ctxt->dst.count = (rc->end - rc->pos) / size;
1332 rc->pos = rc->end;
1333 } else {
1334 memcpy(dest, rc->data + rc->pos, size);
1335 rc->pos += size;
1336 }
dde7e6d1
AK		 1337 return 1;
1338}
6aa8b732 1339
7f3d35fd
KW		 1340static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1341 u16 index, struct desc_struct *desc)
1342{
1343 struct desc_ptr dt;
1344 ulong addr;
1345
1346 ctxt->ops->get_idt(ctxt, &dt);
1347
1348 if (dt.size < index * 8 + 7)
1349 return emulate_gp(ctxt, index << 3 | 0x2);
1350
1351 addr = dt.address + index * 8;
1352 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1353 &ctxt->exception);
1354}
1355
dde7e6d1 1356static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1357 u16 selector, struct desc_ptr *dt)
1358{
0225fb50 1359 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1360
dde7e6d1
AK		 1361 if (selector & 1 << 2) {
1362 struct desc_struct desc;
1aa36616
AK		 1363 u16 sel;
1364
dde7e6d1 1365 memset (dt, 0, sizeof *dt);
1aa36616 1366 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1367 return;
e09d082c 1368
dde7e6d1
AK		 1369 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1370 dt->address = get_desc_base(&desc);
1371 } else
4bff1e86 1372 ops->get_gdt(ctxt, dt);
dde7e6d1 1373}
120df890 1374
dde7e6d1
AK		 1375/* allowed just for 8 bytes segments */
1376static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1377 u16 selector, struct desc_struct *desc,
1378 ulong *desc_addr_p)
dde7e6d1
AK		 1379{
1380 struct desc_ptr dt;
1381 u16 index = selector >> 3;
dde7e6d1 1382 ulong addr;
120df890 1383
7b105ca2 1384 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1385
35d3d4a1
AK		 1386 if (dt.size < index * 8 + 7)
1387 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1388
e919464b 1389 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1390 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1391 &ctxt->exception);
dde7e6d1 1392}
ef65c889 1393
dde7e6d1
AK		 1394/* allowed just for 8 bytes segments */
1395static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1396 u16 selector, struct desc_struct *desc)
1397{
1398 struct desc_ptr dt;
1399 u16 index = selector >> 3;
dde7e6d1 1400 ulong addr;
6aa8b732 1401
7b105ca2 1402 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1403
35d3d4a1
AK		 1404 if (dt.size < index * 8 + 7)
1405 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1406
dde7e6d1 1407 addr = dt.address + index * 8;
7b105ca2
TY		 1408 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1409 &ctxt->exception);
dde7e6d1 1410}
c7e75a3d 1411
5601d05b 1412/* Does not support long mode */
dde7e6d1 1413static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1414 u16 selector, int seg)
1415{
869be99c 1416 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1417 u8 dpl, rpl, cpl;
1418 unsigned err_vec = GP_VECTOR;
1419 u32 err_code = 0;
1420 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1421 ulong desc_addr;
dde7e6d1 1422 int ret;
03ebebeb 1423 u16 dummy;
69f55cb1 1424
dde7e6d1 1425 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1426
f8da94e9
KW		 1427 if (ctxt->mode == X86EMUL_MODE_REAL) {
1428 /* set real mode segment descriptor (keep limit etc. for
1429 * unreal mode) */
03ebebeb 1430 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1431 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1432 goto load;
f8da94e9
KW		 1433 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1434 /* VM86 needs a clean new segment descriptor */
1435 set_desc_base(&seg_desc, selector << 4);
1436 set_desc_limit(&seg_desc, 0xffff);
1437 seg_desc.type = 3;
1438 seg_desc.p = 1;
1439 seg_desc.s = 1;
1440 seg_desc.dpl = 3;
1441 goto load;
dde7e6d1
AK		 1442 }
1443
79d5b4c3
AK		 1444 rpl = selector & 3;
1445 cpl = ctxt->ops->cpl(ctxt);
1446
1447 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1448 if ((seg == VCPU_SREG_CS
1449 || (seg == VCPU_SREG_SS
1450 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1451 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1452 && null_selector)
1453 goto exception;
1454
1455 /* TR should be in GDT only */
1456 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1457 goto exception;
1458
1459 if (null_selector) /* for NULL selector skip all following checks */
1460 goto load;
1461
e919464b 1462 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1463 if (ret != X86EMUL_CONTINUE)
1464 return ret;
1465
1466 err_code = selector & 0xfffc;
1467 err_vec = GP_VECTOR;
1468
fc058680 1469 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1470 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1471 goto exception;
1472
1473 if (!seg_desc.p) {
1474 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1475 goto exception;
1476 }
1477
dde7e6d1 1478 dpl = seg_desc.dpl;
dde7e6d1
AK		 1479
1480 switch (seg) {
1481 case VCPU_SREG_SS:
1482 /*
1483 * segment is not a writable data segment or segment
1484 * selector's RPL != CPL or segment selector's RPL != CPL
1485 */
1486 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1487 goto exception;
6aa8b732 1488 break;
dde7e6d1
AK		 1489 case VCPU_SREG_CS:
1490 if (!(seg_desc.type & 8))
1491 goto exception;
1492
1493 if (seg_desc.type & 4) {
1494 /* conforming */
1495 if (dpl > cpl)
1496 goto exception;
1497 } else {
1498 /* nonconforming */
1499 if (rpl > cpl || dpl != cpl)
1500 goto exception;
1501 }
1502 /* CS(RPL) <- CPL */
1503 selector = (selector & 0xfffc) | cpl;
6aa8b732 1504 break;
dde7e6d1
AK		 1505 case VCPU_SREG_TR:
1506 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1507 goto exception;
869be99c
AK		 1508 old_desc = seg_desc;
1509 seg_desc.type |= 2; /* busy */
1510 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1511 sizeof(seg_desc), &ctxt->exception);
1512 if (ret != X86EMUL_CONTINUE)
1513 return ret;
dde7e6d1
AK		 1514 break;
1515 case VCPU_SREG_LDTR:
1516 if (seg_desc.s || seg_desc.type != 2)
1517 goto exception;
1518 break;
1519 default: /* DS, ES, FS, or GS */
4e62417b 1520 /*
dde7e6d1
AK		 1521 * segment is not a data or readable code segment or
1522 * ((segment is a data or nonconforming code segment)
1523 * and (both RPL and CPL > DPL))
4e62417b 1524 */
dde7e6d1
AK		 1525 if ((seg_desc.type & 0xa) == 0x8 ||
1526 (((seg_desc.type & 0xc) != 0xc) &&
1527 (rpl > dpl && cpl > dpl)))
1528 goto exception;
6aa8b732 1529 break;
dde7e6d1
AK		 1530 }
1531
1532 if (seg_desc.s) {
1533 /* mark segment as accessed */
1534 seg_desc.type |= 1;
7b105ca2 1535 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1536 if (ret != X86EMUL_CONTINUE)
1537 return ret;
1538 }
1539load:
7b105ca2 1540 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1541 return X86EMUL_CONTINUE;
1542exception:
1543 emulate_exception(ctxt, err_vec, err_code, true);
1544 return X86EMUL_PROPAGATE_FAULT;
1545}
1546
31be40b3
WY		 1547static void write_register_operand(struct operand *op)
1548{
1549 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1550 switch (op->bytes) {
1551 case 1:
1552 *(u8 *)op->addr.reg = (u8)op->val;
1553 break;
1554 case 2:
1555 *(u16 *)op->addr.reg = (u16)op->val;
1556 break;
1557 case 4:
1558 *op->addr.reg = (u32)op->val;
1559 break; /* 64b: zero-extend */
1560 case 8:
1561 *op->addr.reg = op->val;
1562 break;
1563 }
1564}
1565
fb32b1ed 1566static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1567{
1568 int rc;
dde7e6d1 1569
fb32b1ed 1570 switch (op->type) {
dde7e6d1 1571 case OP_REG:
fb32b1ed 1572 write_register_operand(op);
6aa8b732 1573 break;
dde7e6d1 1574 case OP_MEM:
9dac77fa 1575 if (ctxt->lock_prefix)
3ca3ac4d 1576 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1577 op->addr.mem,
1578 &op->orig_val,
1579 &op->val,
1580 op->bytes);
341de7e3 1581 else
3ca3ac4d 1582 rc = segmented_write(ctxt,
fb32b1ed
AK		 1583 op->addr.mem,
1584 &op->val,
1585 op->bytes);
dde7e6d1
AK		 1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
a682e354 1588 break;
b3356bf0
GN		 1589 case OP_MEM_STR:
1590 rc = segmented_write(ctxt,
fb32b1ed
AK		 1591 op->addr.mem,
1592 op->data,
1593 op->bytes * op->count);
b3356bf0
GN		 1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
1596 break;
1253791d 1597 case OP_XMM:
fb32b1ed 1598 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1599 break;
cbe2c9d3 1600 case OP_MM:
fb32b1ed 1601 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1602 break;
dde7e6d1
AK		 1603 case OP_NONE:
1604 /* no writeback */
414e6277 1605 break;
dde7e6d1 1606 default:
414e6277 1607 break;
6aa8b732 1608 }
dde7e6d1
AK		 1609 return X86EMUL_CONTINUE;
1610}
6aa8b732 1611
51ddff50 1612static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1613{
4179bb02 1614 struct segmented_address addr;
0dc8d10f 1615
5ad105e5 1616 rsp_increment(ctxt, -bytes);
dd856efa 1617 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1618 addr.seg = VCPU_SREG_SS;
1619
51ddff50
AK		 1620 return segmented_write(ctxt, addr, data, bytes);
1621}
1622
1623static int em_push(struct x86_emulate_ctxt *ctxt)
1624{
4179bb02 1625 /* Disable writeback. */
9dac77fa 1626 ctxt->dst.type = OP_NONE;
51ddff50 1627 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1628}
69f55cb1 1629
dde7e6d1 1630static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1631 void *dest, int len)
1632{
dde7e6d1 1633 int rc;
90de84f5 1634 struct segmented_address addr;
8b4caf66 1635
dd856efa 1636 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1637 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1638 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1639 if (rc != X86EMUL_CONTINUE)
1640 return rc;
1641
5ad105e5 1642 rsp_increment(ctxt, len);
dde7e6d1 1643 return rc;
8b4caf66
LV		 1644}
1645
c54fe504
TY		 1646static int em_pop(struct x86_emulate_ctxt *ctxt)
1647{
9dac77fa 1648 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1649}
1650
dde7e6d1 1651static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1652 void *dest, int len)
9de41573
GN		 1653{
1654 int rc;
dde7e6d1
AK		 1655 unsigned long val, change_mask;
1656 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1657 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1658
3b9be3bf 1659 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1660 if (rc != X86EMUL_CONTINUE)
1661 return rc;
9de41573 1662
dde7e6d1
AK		 1663 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1664 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1665
dde7e6d1
AK		 1666 switch(ctxt->mode) {
1667 case X86EMUL_MODE_PROT64:
1668 case X86EMUL_MODE_PROT32:
1669 case X86EMUL_MODE_PROT16:
1670 if (cpl == 0)
1671 change_mask |= EFLG_IOPL;
1672 if (cpl <= iopl)
1673 change_mask |= EFLG_IF;
1674 break;
1675 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1676 if (iopl < 3)
1677 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1678 change_mask |= EFLG_IF;
1679 break;
1680 default: /* real mode */
1681 change_mask |= (EFLG_IOPL | EFLG_IF);
1682 break;
9de41573 1683 }
dde7e6d1
AK		 1684
1685 *(unsigned long *)dest =
1686 (ctxt->eflags & ~change_mask) | (val & change_mask);
1687
1688 return rc;
9de41573
GN		 1689}
1690
62aaa2f0
TY		 1691static int em_popf(struct x86_emulate_ctxt *ctxt)
1692{
9dac77fa
AK		 1693 ctxt->dst.type = OP_REG;
1694 ctxt->dst.addr.reg = &ctxt->eflags;
1695 ctxt->dst.bytes = ctxt->op_bytes;
1696 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1697}
1698
612e89f0
AK		 1699static int em_enter(struct x86_emulate_ctxt *ctxt)
1700{
1701 int rc;
1702 unsigned frame_size = ctxt->src.val;
1703 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1704 ulong rbp;
612e89f0
AK		 1705
1706 if (nesting_level)
1707 return X86EMUL_UNHANDLEABLE;
1708
dd856efa
AK		 1709 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1710 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1711 if (rc != X86EMUL_CONTINUE)
1712 return rc;
dd856efa 1713 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1714 stack_mask(ctxt));
dd856efa
AK		 1715 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1716 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1717 stack_mask(ctxt));
1718 return X86EMUL_CONTINUE;
1719}
1720
f47cfa31
AK		 1721static int em_leave(struct x86_emulate_ctxt *ctxt)
1722{
dd856efa 1723 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1724 stack_mask(ctxt));
dd856efa 1725 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1726}
1727
1cd196ea 1728static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1729{
1cd196ea
AK		 1730 int seg = ctxt->src2.val;
1731
9dac77fa 1732 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1733
4487b3b4 1734 return em_push(ctxt);
7b262e90
GN		 1735}
1736
1cd196ea 1737static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1738{
1cd196ea 1739 int seg = ctxt->src2.val;
dde7e6d1
AK		 1740 unsigned long selector;
1741 int rc;
38ba30ba 1742
9dac77fa 1743 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1744 if (rc != X86EMUL_CONTINUE)
1745 return rc;
1746
7b105ca2 1747 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1748 return rc;
38ba30ba
GN		 1749}
1750
b96a7fad 1751static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1752{
dd856efa 1753 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1754 int rc = X86EMUL_CONTINUE;
1755 int reg = VCPU_REGS_RAX;
38ba30ba 1756
dde7e6d1
AK		 1757 while (reg <= VCPU_REGS_RDI) {
1758 (reg == VCPU_REGS_RSP) ?
dd856efa 1759 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1760
4487b3b4 1761 rc = em_push(ctxt);
dde7e6d1
AK		 1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
38ba30ba 1764
dde7e6d1 1765 ++reg;
38ba30ba 1766 }
38ba30ba 1767
dde7e6d1 1768 return rc;
38ba30ba
GN		 1769}
1770
62aaa2f0
TY		 1771static int em_pushf(struct x86_emulate_ctxt *ctxt)
1772{
9dac77fa 1773 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1774 return em_push(ctxt);
1775}
1776
b96a7fad 1777static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1778{
dde7e6d1
AK		 1779 int rc = X86EMUL_CONTINUE;
1780 int reg = VCPU_REGS_RDI;
38ba30ba 1781
dde7e6d1
AK		 1782 while (reg >= VCPU_REGS_RAX) {
1783 if (reg == VCPU_REGS_RSP) {
5ad105e5 1784 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1785 --reg;
1786 }
38ba30ba 1787
dd856efa 1788 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1789 if (rc != X86EMUL_CONTINUE)
1790 break;
1791 --reg;
38ba30ba 1792 }
dde7e6d1 1793 return rc;
38ba30ba
GN		 1794}
1795
dd856efa 1796static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1797{
0225fb50 1798 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1799 int rc;
6e154e56
MG		 1800 struct desc_ptr dt;
1801 gva_t cs_addr;
1802 gva_t eip_addr;
1803 u16 cs, eip;
6e154e56
MG		 1804
1805 /* TODO: Add limit checks */
9dac77fa 1806 ctxt->src.val = ctxt->eflags;
4487b3b4 1807 rc = em_push(ctxt);
5c56e1cf
AK		 1808 if (rc != X86EMUL_CONTINUE)
1809 return rc;
6e154e56
MG		 1810
1811 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1812
9dac77fa 1813 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1814 rc = em_push(ctxt);
5c56e1cf
AK		 1815 if (rc != X86EMUL_CONTINUE)
1816 return rc;
6e154e56 1817
9dac77fa 1818 ctxt->src.val = ctxt->_eip;
4487b3b4 1819 rc = em_push(ctxt);
5c56e1cf
AK		 1820 if (rc != X86EMUL_CONTINUE)
1821 return rc;
1822
4bff1e86 1823 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1824
1825 eip_addr = dt.address + (irq << 2);
1826 cs_addr = dt.address + (irq << 2) + 2;
1827
0f65dd70 1828 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1829 if (rc != X86EMUL_CONTINUE)
1830 return rc;
1831
0f65dd70 1832 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
1835
7b105ca2 1836 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1837 if (rc != X86EMUL_CONTINUE)
1838 return rc;
1839
9dac77fa 1840 ctxt->_eip = eip;
6e154e56
MG		 1841
1842 return rc;
1843}
1844
dd856efa
AK		 1845int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1846{
1847 int rc;
1848
1849 invalidate_registers(ctxt);
1850 rc = __emulate_int_real(ctxt, irq);
1851 if (rc == X86EMUL_CONTINUE)
1852 writeback_registers(ctxt);
1853 return rc;
1854}
1855
7b105ca2 1856static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1857{
1858 switch(ctxt->mode) {
1859 case X86EMUL_MODE_REAL:
dd856efa 1860 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1861 case X86EMUL_MODE_VM86:
1862 case X86EMUL_MODE_PROT16:
1863 case X86EMUL_MODE_PROT32:
1864 case X86EMUL_MODE_PROT64:
1865 default:
1866 /* Protected mode interrupts unimplemented yet */
1867 return X86EMUL_UNHANDLEABLE;
1868 }
1869}
1870
7b105ca2 1871static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1872{
dde7e6d1
AK		 1873 int rc = X86EMUL_CONTINUE;
1874 unsigned long temp_eip = 0;
1875 unsigned long temp_eflags = 0;
1876 unsigned long cs = 0;
1877 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1878 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1879 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1880 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1881
dde7e6d1 1882 /* TODO: Add stack limit check */
38ba30ba 1883
9dac77fa 1884 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1885
dde7e6d1
AK		 1886 if (rc != X86EMUL_CONTINUE)
1887 return rc;
38ba30ba 1888
35d3d4a1
AK		 1889 if (temp_eip & ~0xffff)
1890 return emulate_gp(ctxt, 0);
38ba30ba 1891
9dac77fa 1892 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1893
dde7e6d1
AK		 1894 if (rc != X86EMUL_CONTINUE)
1895 return rc;
38ba30ba 1896
9dac77fa 1897 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1898
dde7e6d1
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 return rc;
38ba30ba 1901
7b105ca2 1902 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1903
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
38ba30ba 1906
9dac77fa 1907 ctxt->_eip = temp_eip;
38ba30ba 1908
38ba30ba 1909
9dac77fa 1910 if (ctxt->op_bytes == 4)
dde7e6d1 1911 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1912 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1913 ctxt->eflags &= ~0xffff;
1914 ctxt->eflags |= temp_eflags;
38ba30ba 1915 }
dde7e6d1
AK		 1916
1917 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1918 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1919
1920 return rc;
38ba30ba
GN		 1921}
1922
e01991e7 1923static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1924{
dde7e6d1
AK		 1925 switch(ctxt->mode) {
1926 case X86EMUL_MODE_REAL:
7b105ca2 1927 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1928 case X86EMUL_MODE_VM86:
1929 case X86EMUL_MODE_PROT16:
1930 case X86EMUL_MODE_PROT32:
1931 case X86EMUL_MODE_PROT64:
c37eda13 1932 default:
dde7e6d1
AK		 1933 /* iret from protected mode unimplemented yet */
1934 return X86EMUL_UNHANDLEABLE;
c37eda13 1935 }
c37eda13
WY		 1936}
1937
d2f62766
TY		 1938static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1939{
d2f62766
TY		 1940 int rc;
1941 unsigned short sel;
1942
9dac77fa 1943 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1944
7b105ca2 1945 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1946 if (rc != X86EMUL_CONTINUE)
1947 return rc;
1948
9dac77fa
AK		 1949 ctxt->_eip = 0;
1950 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1951 return X86EMUL_CONTINUE;
1952}
1953
51187683 1954static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1955{
4179bb02 1956 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1957
9dac77fa 1958 switch (ctxt->modrm_reg) {
d19292e4
MG		 1959 case 2: /* call near abs */ {
1960 long int old_eip;
9dac77fa
AK		 1961 old_eip = ctxt->_eip;
1962 ctxt->_eip = ctxt->src.val;
1963 ctxt->src.val = old_eip;
4487b3b4 1964 rc = em_push(ctxt);
d19292e4
MG		 1965 break;
1966 }
8cdbd2c9 1967 case 4: /* jmp abs */
9dac77fa 1968 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1969 break;
d2f62766
TY		 1970 case 5: /* jmp far */
1971 rc = em_jmp_far(ctxt);
1972 break;
8cdbd2c9 1973 case 6: /* push */
4487b3b4 1974 rc = em_push(ctxt);
8cdbd2c9 1975 break;
8cdbd2c9 1976 }
4179bb02 1977 return rc;
8cdbd2c9
LV		 1978}
1979
e0dac408 1980static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1981{
9dac77fa 1982 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1983
dd856efa
AK		 1984 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1985 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1986 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1987 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 1988 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1989 } else {
dd856efa
AK		 1990 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
1991 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 1992
05f086f8 1993 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1994 }
1b30eaa8 1995 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1996}
1997
ebda02c2
TY		 1998static int em_ret(struct x86_emulate_ctxt *ctxt)
1999{
9dac77fa
AK		 2000 ctxt->dst.type = OP_REG;
2001 ctxt->dst.addr.reg = &ctxt->_eip;
2002 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2003 return em_pop(ctxt);
2004}
2005
e01991e7 2006static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2007{
a77ab5ea
AK		 2008 int rc;
2009 unsigned long cs;
2010
9dac77fa 2011 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2012 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2013 return rc;
9dac77fa
AK		 2014 if (ctxt->op_bytes == 4)
2015 ctxt->_eip = (u32)ctxt->_eip;
2016 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2017 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2018 return rc;
7b105ca2 2019 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2020 return rc;
2021}
2022
e940b5c2
TY		 2023static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2024{
2025 /* Save real source value, then compare EAX against destination. */
2026 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2027 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
158de57f 2028 fastop(ctxt, em_cmp);
e940b5c2
TY		 2029
2030 if (ctxt->eflags & EFLG_ZF) {
2031 /* Success: write back to memory. */
2032 ctxt->dst.val = ctxt->src.orig_val;
2033 } else {
2034 /* Failure: write the value we saw to EAX. */
2035 ctxt->dst.type = OP_REG;
dd856efa 2036 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2037 }
2038 return X86EMUL_CONTINUE;
2039}
2040
d4b4325f 2041static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2042{
d4b4325f 2043 int seg = ctxt->src2.val;
09b5f4d3
WY		 2044 unsigned short sel;
2045 int rc;
2046
9dac77fa 2047 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2048
7b105ca2 2049 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2050 if (rc != X86EMUL_CONTINUE)
2051 return rc;
2052
9dac77fa 2053 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2054 return rc;
2055}
2056
7b105ca2 2057static void
e66bb2cc 2058setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2059 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2060{
e66bb2cc 2061 cs->l = 0; /* will be adjusted later */
79168fd1 2062 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2063 cs->g = 1; /* 4kb granularity */
79168fd1 2064 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2065 cs->type = 0x0b; /* Read, Execute, Accessed */
2066 cs->s = 1;
2067 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2068 cs->p = 1;
2069 cs->d = 1;
99245b50 2070 cs->avl = 0;
e66bb2cc 2071
79168fd1
GN		 2072 set_desc_base(ss, 0); /* flat segment */
2073 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2074 ss->g = 1; /* 4kb granularity */
2075 ss->s = 1;
2076 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2077 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2078 ss->dpl = 0;
79168fd1 2079 ss->p = 1;
99245b50
GN		 2080 ss->l = 0;
2081 ss->avl = 0;
e66bb2cc
AP		 2082}
2083
1a18a69b
AK		 2084static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2085{
2086 u32 eax, ebx, ecx, edx;
2087
2088 eax = ecx = 0;
0017f93a
AK		 2089 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2090 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2091 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2092 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2093}
2094
c2226fc9
SB		 2095static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2096{
0225fb50 2097 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2098 u32 eax, ebx, ecx, edx;
2099
2100 /*
2101 * syscall should always be enabled in longmode - so only become
2102 * vendor specific (cpuid) if other modes are active...
2103 */
2104 if (ctxt->mode == X86EMUL_MODE_PROT64)
2105 return true;
2106
2107 eax = 0x00000000;
2108 ecx = 0x00000000;
0017f93a
AK		 2109 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2110 /*
2111 * Intel ("GenuineIntel")
2112 * remark: Intel CPUs only support "syscall" in 64bit
2113 * longmode. Also an 64bit guest with a
2114 * 32bit compat-app running will #UD !! While this
2115 * behaviour can be fixed (by emulating) into AMD
2116 * response - CPUs of AMD can't behave like Intel.
2117 */
2118 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2119 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2120 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2121 return false;
2122
2123 /* AMD ("AuthenticAMD") */
2124 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2125 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2126 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2127 return true;
2128
2129 /* AMD ("AMDisbetter!") */
2130 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2131 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2132 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2133 return true;
c2226fc9
SB		 2134
2135 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2136 return false;
2137}
2138
e01991e7 2139static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2140{
0225fb50 2141 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2142 struct desc_struct cs, ss;
e66bb2cc 2143 u64 msr_data;
79168fd1 2144 u16 cs_sel, ss_sel;
c2ad2bb3 2145 u64 efer = 0;
e66bb2cc
AP		 2146
2147 /* syscall is not available in real mode */
2e901c4c 2148 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2149 ctxt->mode == X86EMUL_MODE_VM86)
2150 return emulate_ud(ctxt);
e66bb2cc 2151
c2226fc9
SB		 2152 if (!(em_syscall_is_enabled(ctxt)))
2153 return emulate_ud(ctxt);
2154
c2ad2bb3 2155 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2156 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2157
c2226fc9
SB		 2158 if (!(efer & EFER_SCE))
2159 return emulate_ud(ctxt);
2160
717746e3 2161 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2162 msr_data >>= 32;
79168fd1
GN		 2163 cs_sel = (u16)(msr_data & 0xfffc);
2164 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2165
c2ad2bb3 2166 if (efer & EFER_LMA) {
79168fd1 2167 cs.d = 0;
e66bb2cc
AP		 2168 cs.l = 1;
2169 }
1aa36616
AK		 2170 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2171 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2172
dd856efa 2173 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2174 if (efer & EFER_LMA) {
e66bb2cc 2175#ifdef CONFIG_X86_64
dd856efa 2176 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2177
717746e3 2178 ops->get_msr(ctxt,
3fb1b5db
GN		 2179 ctxt->mode == X86EMUL_MODE_PROT64 ?
2180 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2181 ctxt->_eip = msr_data;
e66bb2cc 2182
717746e3 2183 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2184 ctxt->eflags &= ~(msr_data | EFLG_RF);
2185#endif
2186 } else {
2187 /* legacy mode */
717746e3 2188 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2189 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2190
2191 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2192 }
2193
e54cfa97 2194 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2195}
2196
e01991e7 2197static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2198{
0225fb50 2199 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2200 struct desc_struct cs, ss;
8c604352 2201 u64 msr_data;
79168fd1 2202 u16 cs_sel, ss_sel;
c2ad2bb3 2203 u64 efer = 0;
8c604352 2204
7b105ca2 2205 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2206 /* inject #GP if in real mode */
35d3d4a1
AK		 2207 if (ctxt->mode == X86EMUL_MODE_REAL)
2208 return emulate_gp(ctxt, 0);
8c604352 2209
1a18a69b
AK		 2210 /*
2211 * Not recognized on AMD in compat mode (but is recognized in legacy
2212 * mode).
2213 */
2214 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2215 && !vendor_intel(ctxt))
2216 return emulate_ud(ctxt);
2217
8c604352
AP		 2218 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2219 * Therefore, we inject an #UD.
2220 */
35d3d4a1
AK		 2221 if (ctxt->mode == X86EMUL_MODE_PROT64)
2222 return emulate_ud(ctxt);
8c604352 2223
7b105ca2 2224 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2225
717746e3 2226 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2227 switch (ctxt->mode) {
2228 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2229 if ((msr_data & 0xfffc) == 0x0)
2230 return emulate_gp(ctxt, 0);
8c604352
AP		 2231 break;
2232 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2233 if (msr_data == 0x0)
2234 return emulate_gp(ctxt, 0);
8c604352 2235 break;
9d1b39a9
GN		 2236 default:
2237 break;
8c604352
AP		 2238 }
2239
2240 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2241 cs_sel = (u16)msr_data;
2242 cs_sel &= ~SELECTOR_RPL_MASK;
2243 ss_sel = cs_sel + 8;
2244 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2245 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2246 cs.d = 0;
8c604352
AP		 2247 cs.l = 1;
2248 }
2249
1aa36616
AK		 2250 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2251 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2252
717746e3 2253 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2254 ctxt->_eip = msr_data;
8c604352 2255
717746e3 2256 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2257 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2258
e54cfa97 2259 return X86EMUL_CONTINUE;
8c604352
AP		 2260}
2261
e01991e7 2262static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2263{
0225fb50 2264 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2265 struct desc_struct cs, ss;
4668f050
AP		 2266 u64 msr_data;
2267 int usermode;
1249b96e 2268 u16 cs_sel = 0, ss_sel = 0;
4668f050 2269
a0044755
GN		 2270 /* inject #GP if in real mode or Virtual 8086 mode */
2271 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2272 ctxt->mode == X86EMUL_MODE_VM86)
2273 return emulate_gp(ctxt, 0);
4668f050 2274
7b105ca2 2275 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2276
9dac77fa 2277 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2278 usermode = X86EMUL_MODE_PROT64;
2279 else
2280 usermode = X86EMUL_MODE_PROT32;
2281
2282 cs.dpl = 3;
2283 ss.dpl = 3;
717746e3 2284 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2285 switch (usermode) {
2286 case X86EMUL_MODE_PROT32:
79168fd1 2287 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2288 if ((msr_data & 0xfffc) == 0x0)
2289 return emulate_gp(ctxt, 0);
79168fd1 2290 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2291 break;
2292 case X86EMUL_MODE_PROT64:
79168fd1 2293 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2294 if (msr_data == 0x0)
2295 return emulate_gp(ctxt, 0);
79168fd1
GN		 2296 ss_sel = cs_sel + 8;
2297 cs.d = 0;
4668f050
AP		 2298 cs.l = 1;
2299 break;
2300 }
79168fd1
GN		 2301 cs_sel |= SELECTOR_RPL_MASK;
2302 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2303
1aa36616
AK		 2304 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2305 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2306
dd856efa
AK		 2307 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2308 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2309
e54cfa97 2310 return X86EMUL_CONTINUE;
4668f050
AP		 2311}
2312
7b105ca2 2313static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2314{
2315 int iopl;
2316 if (ctxt->mode == X86EMUL_MODE_REAL)
2317 return false;
2318 if (ctxt->mode == X86EMUL_MODE_VM86)
2319 return true;
2320 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2321 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2322}
2323
2324static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2325 u16 port, u16 len)
2326{
0225fb50 2327 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2328 struct desc_struct tr_seg;
5601d05b 2329 u32 base3;
f850e2e6 2330 int r;
1aa36616 2331 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2332 unsigned mask = (1 << len) - 1;
5601d05b 2333 unsigned long base;
f850e2e6 2334
1aa36616 2335 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2336 if (!tr_seg.p)
f850e2e6 2337 return false;
79168fd1 2338 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2339 return false;
5601d05b
GN		 2340 base = get_desc_base(&tr_seg);
2341#ifdef CONFIG_X86_64
2342 base |= ((u64)base3) << 32;
2343#endif
0f65dd70 2344 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2345 if (r != X86EMUL_CONTINUE)
2346 return false;
79168fd1 2347 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2348 return false;
0f65dd70 2349 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2350 if (r != X86EMUL_CONTINUE)
2351 return false;
2352 if ((perm >> bit_idx) & mask)
2353 return false;
2354 return true;
2355}
2356
2357static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2358 u16 port, u16 len)
2359{
4fc40f07
GN		 2360 if (ctxt->perm_ok)
2361 return true;
2362
7b105ca2
TY		 2363 if (emulator_bad_iopl(ctxt))
2364 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2365 return false;
4fc40f07
GN		 2366
2367 ctxt->perm_ok = true;
2368
f850e2e6
GN		 2369 return true;
2370}
2371
38ba30ba 2372static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2373 struct tss_segment_16 *tss)
2374{
9dac77fa 2375 tss->ip = ctxt->_eip;
38ba30ba 2376 tss->flag = ctxt->eflags;
dd856efa
AK		 2377 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2378 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2379 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2380 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2381 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2382 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2383 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2384 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2385
1aa36616
AK		 2386 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2387 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2388 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2389 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2390 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2391}
2392
2393static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2394 struct tss_segment_16 *tss)
2395{
38ba30ba
GN		 2396 int ret;
2397
9dac77fa 2398 ctxt->_eip = tss->ip;
38ba30ba 2399 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2400 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2401 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2402 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2403 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2404 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2405 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2406 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2407 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2408
2409 /*
2410 * SDM says that segment selectors are loaded before segment
2411 * descriptors
2412 */
1aa36616
AK		 2413 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2414 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2415 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2416 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2417 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2418
2419 /*
fc058680 2420 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2421 * it is handled in a context of new task
2422 */
7b105ca2 2423 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2424 if (ret != X86EMUL_CONTINUE)
2425 return ret;
7b105ca2 2426 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2427 if (ret != X86EMUL_CONTINUE)
2428 return ret;
7b105ca2 2429 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2430 if (ret != X86EMUL_CONTINUE)
2431 return ret;
7b105ca2 2432 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2433 if (ret != X86EMUL_CONTINUE)
2434 return ret;
7b105ca2 2435 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2436 if (ret != X86EMUL_CONTINUE)
2437 return ret;
2438
2439 return X86EMUL_CONTINUE;
2440}
2441
2442static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2443 u16 tss_selector, u16 old_tss_sel,
2444 ulong old_tss_base, struct desc_struct *new_desc)
2445{
0225fb50 2446 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2447 struct tss_segment_16 tss_seg;
2448 int ret;
bcc55cba 2449 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2450
0f65dd70 2451 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2452 &ctxt->exception);
db297e3d 2453 if (ret != X86EMUL_CONTINUE)
38ba30ba 2454 /* FIXME: need to provide precise fault address */
38ba30ba 2455 return ret;
38ba30ba 2456
7b105ca2 2457 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2458
0f65dd70 2459 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2460 &ctxt->exception);
db297e3d 2461 if (ret != X86EMUL_CONTINUE)
38ba30ba 2462 /* FIXME: need to provide precise fault address */
38ba30ba 2463 return ret;
38ba30ba 2464
0f65dd70 2465 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2466 &ctxt->exception);
db297e3d 2467 if (ret != X86EMUL_CONTINUE)
38ba30ba 2468 /* FIXME: need to provide precise fault address */
38ba30ba 2469 return ret;
38ba30ba
GN		 2470
2471 if (old_tss_sel != 0xffff) {
2472 tss_seg.prev_task_link = old_tss_sel;
2473
0f65dd70 2474 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2475 &tss_seg.prev_task_link,
2476 sizeof tss_seg.prev_task_link,
0f65dd70 2477 &ctxt->exception);
db297e3d 2478 if (ret != X86EMUL_CONTINUE)
38ba30ba 2479 /* FIXME: need to provide precise fault address */
38ba30ba 2480 return ret;
38ba30ba
GN		 2481 }
2482
7b105ca2 2483 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2484}
2485
2486static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2487 struct tss_segment_32 *tss)
2488{
7b105ca2 2489 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2490 tss->eip = ctxt->_eip;
38ba30ba 2491 tss->eflags = ctxt->eflags;
dd856efa
AK		 2492 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2493 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2494 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2495 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2496 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2497 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2498 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2499 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2500
1aa36616
AK		 2501 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2502 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2503 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2504 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2505 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2506 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2507 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2508}
2509
2510static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2511 struct tss_segment_32 *tss)
2512{
38ba30ba
GN		 2513 int ret;
2514
7b105ca2 2515 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2516 return emulate_gp(ctxt, 0);
9dac77fa 2517 ctxt->_eip = tss->eip;
38ba30ba 2518 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2519
2520 /* General purpose registers */
dd856efa
AK		 2521 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2522 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2523 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2524 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2525 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2526 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2527 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2528 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2529
2530 /*
2531 * SDM says that segment selectors are loaded before segment
2532 * descriptors
2533 */
1aa36616
AK		 2534 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2535 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2536 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2537 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2538 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2539 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2540 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2541
4cee4798
KW		 2542 /*
2543 * If we're switching between Protected Mode and VM86, we need to make
2544 * sure to update the mode before loading the segment descriptors so
2545 * that the selectors are interpreted correctly.
2546 *
2547 * Need to get rflags to the vcpu struct immediately because it
2548 * influences the CPL which is checked at least when loading the segment
2549 * descriptors and when pushing an error code to the new kernel stack.
2550 *
2551 * TODO Introduce a separate ctxt->ops->set_cpl callback
2552 */
2553 if (ctxt->eflags & X86_EFLAGS_VM)
2554 ctxt->mode = X86EMUL_MODE_VM86;
2555 else
2556 ctxt->mode = X86EMUL_MODE_PROT32;
2557
2558 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2559
38ba30ba
GN		 2560 /*
2561 * Now load segment descriptors. If fault happenes at this stage
2562 * it is handled in a context of new task
2563 */
7b105ca2 2564 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2565 if (ret != X86EMUL_CONTINUE)
2566 return ret;
7b105ca2 2567 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2568 if (ret != X86EMUL_CONTINUE)
2569 return ret;
7b105ca2 2570 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2571 if (ret != X86EMUL_CONTINUE)
2572 return ret;
7b105ca2 2573 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2574 if (ret != X86EMUL_CONTINUE)
2575 return ret;
7b105ca2 2576 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2577 if (ret != X86EMUL_CONTINUE)
2578 return ret;
7b105ca2 2579 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
7b105ca2 2582 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2583 if (ret != X86EMUL_CONTINUE)
2584 return ret;
2585
2586 return X86EMUL_CONTINUE;
2587}
2588
2589static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2590 u16 tss_selector, u16 old_tss_sel,
2591 ulong old_tss_base, struct desc_struct *new_desc)
2592{
0225fb50 2593 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2594 struct tss_segment_32 tss_seg;
2595 int ret;
bcc55cba 2596 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2597
0f65dd70 2598 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2599 &ctxt->exception);
db297e3d 2600 if (ret != X86EMUL_CONTINUE)
38ba30ba 2601 /* FIXME: need to provide precise fault address */
38ba30ba 2602 return ret;
38ba30ba 2603
7b105ca2 2604 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2605
0f65dd70 2606 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2607 &ctxt->exception);
db297e3d 2608 if (ret != X86EMUL_CONTINUE)
38ba30ba 2609 /* FIXME: need to provide precise fault address */
38ba30ba 2610 return ret;
38ba30ba 2611
0f65dd70 2612 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2613 &ctxt->exception);
db297e3d 2614 if (ret != X86EMUL_CONTINUE)
38ba30ba 2615 /* FIXME: need to provide precise fault address */
38ba30ba 2616 return ret;
38ba30ba
GN		 2617
2618 if (old_tss_sel != 0xffff) {
2619 tss_seg.prev_task_link = old_tss_sel;
2620
0f65dd70 2621 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2622 &tss_seg.prev_task_link,
2623 sizeof tss_seg.prev_task_link,
0f65dd70 2624 &ctxt->exception);
db297e3d 2625 if (ret != X86EMUL_CONTINUE)
38ba30ba 2626 /* FIXME: need to provide precise fault address */
38ba30ba 2627 return ret;
38ba30ba
GN		 2628 }
2629
7b105ca2 2630 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2631}
2632
2633static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2634 u16 tss_selector, int idt_index, int reason,
e269fb21 2635 bool has_error_code, u32 error_code)
38ba30ba 2636{
0225fb50 2637 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2638 struct desc_struct curr_tss_desc, next_tss_desc;
2639 int ret;
1aa36616 2640 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2641 ulong old_tss_base =
4bff1e86 2642 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2643 u32 desc_limit;
e919464b 2644 ulong desc_addr;
38ba30ba
GN		 2645
2646 /* FIXME: old_tss_base == ~0 ? */
2647
e919464b 2648 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2649 if (ret != X86EMUL_CONTINUE)
2650 return ret;
e919464b 2651 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2652 if (ret != X86EMUL_CONTINUE)
2653 return ret;
2654
2655 /* FIXME: check that next_tss_desc is tss */
2656
7f3d35fd
KW		 2657 /*
2658 * Check privileges. The three cases are task switch caused by...
2659 *
2660 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2661 * 2. Exception/IRQ/iret: No check is performed
fc058680 2662 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2663 */
2664 if (reason == TASK_SWITCH_GATE) {
2665 if (idt_index != -1) {
2666 /* Software interrupts */
2667 struct desc_struct task_gate_desc;
2668 int dpl;
2669
2670 ret = read_interrupt_descriptor(ctxt, idt_index,
2671 &task_gate_desc);
2672 if (ret != X86EMUL_CONTINUE)
2673 return ret;
2674
2675 dpl = task_gate_desc.dpl;
2676 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2677 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2678 }
2679 } else if (reason != TASK_SWITCH_IRET) {
2680 int dpl = next_tss_desc.dpl;
2681 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2682 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2683 }
2684
7f3d35fd 2685
ceffb459
GN		 2686 desc_limit = desc_limit_scaled(&next_tss_desc);
2687 if (!next_tss_desc.p ||
2688 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2689 desc_limit < 0x2b)) {
54b8486f 2690 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2691 return X86EMUL_PROPAGATE_FAULT;
2692 }
2693
2694 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2695 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2696 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2697 }
2698
2699 if (reason == TASK_SWITCH_IRET)
2700 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2701
2702 /* set back link to prev task only if NT bit is set in eflags
fc058680 2703 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2704 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2705 old_tss_sel = 0xffff;
2706
2707 if (next_tss_desc.type & 8)
7b105ca2 2708 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2709 old_tss_base, &next_tss_desc);
2710 else
7b105ca2 2711 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2712 old_tss_base, &next_tss_desc);
0760d448
JK		 2713 if (ret != X86EMUL_CONTINUE)
2714 return ret;
38ba30ba
GN		 2715
2716 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2717 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2718
2719 if (reason != TASK_SWITCH_IRET) {
2720 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2721 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2722 }
2723
717746e3 2724 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2725 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2726
e269fb21 2727 if (has_error_code) {
9dac77fa
AK		 2728 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2729 ctxt->lock_prefix = 0;
2730 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2731 ret = em_push(ctxt);
e269fb21
JK		 2732 }
2733
38ba30ba
GN		 2734 return ret;
2735}
2736
2737int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2738 u16 tss_selector, int idt_index, int reason,
e269fb21 2739 bool has_error_code, u32 error_code)
38ba30ba 2740{
38ba30ba
GN		 2741 int rc;
2742
dd856efa 2743 invalidate_registers(ctxt);
9dac77fa
AK		 2744 ctxt->_eip = ctxt->eip;
2745 ctxt->dst.type = OP_NONE;
38ba30ba 2746
7f3d35fd 2747 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2748 has_error_code, error_code);
38ba30ba 2749
dd856efa 2750 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2751 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2752 writeback_registers(ctxt);
2753 }
38ba30ba 2754
a0c0ab2f 2755 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2756}
2757
f3bd64c6
GN		 2758static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2759 struct operand *op)
a682e354 2760{
b3356bf0 2761 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2762
dd856efa
AK		 2763 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2764 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2765}
2766
7af04fc0
AK		 2767static int em_das(struct x86_emulate_ctxt *ctxt)
2768{
7af04fc0
AK		 2769 u8 al, old_al;
2770 bool af, cf, old_cf;
2771
2772 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2773 al = ctxt->dst.val;
7af04fc0
AK		 2774
2775 old_al = al;
2776 old_cf = cf;
2777 cf = false;
2778 af = ctxt->eflags & X86_EFLAGS_AF;
2779 if ((al & 0x0f) > 9 || af) {
2780 al -= 6;
2781 cf = old_cf | (al >= 250);
2782 af = true;
2783 } else {
2784 af = false;
2785 }
2786 if (old_al > 0x99 || old_cf) {
2787 al -= 0x60;
2788 cf = true;
2789 }
2790
9dac77fa 2791 ctxt->dst.val = al;
7af04fc0 2792 /* Set PF, ZF, SF */
9dac77fa
AK		 2793 ctxt->src.type = OP_IMM;
2794 ctxt->src.val = 0;
2795 ctxt->src.bytes = 1;
158de57f 2796 fastop(ctxt, em_or);
7af04fc0
AK		 2797 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2798 if (cf)
2799 ctxt->eflags |= X86_EFLAGS_CF;
2800 if (af)
2801 ctxt->eflags |= X86_EFLAGS_AF;
2802 return X86EMUL_CONTINUE;
2803}
2804
a035d5c6
PB		 2805static int em_aam(struct x86_emulate_ctxt *ctxt)
2806{
2807 u8 al, ah;
2808
2809 if (ctxt->src.val == 0)
2810 return emulate_de(ctxt);
2811
2812 al = ctxt->dst.val & 0xff;
2813 ah = al / ctxt->src.val;
2814 al %= ctxt->src.val;
2815
2816 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2817
2818 /* Set PF, ZF, SF */
2819 ctxt->src.type = OP_IMM;
2820 ctxt->src.val = 0;
2821 ctxt->src.bytes = 1;
2822 fastop(ctxt, em_or);
2823
2824 return X86EMUL_CONTINUE;
2825}
2826
7f662273
GN		 2827static int em_aad(struct x86_emulate_ctxt *ctxt)
2828{
2829 u8 al = ctxt->dst.val & 0xff;
2830 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2831
2832 al = (al + (ah * ctxt->src.val)) & 0xff;
2833
2834 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2835
f583c29b
GN		 2836 /* Set PF, ZF, SF */
2837 ctxt->src.type = OP_IMM;
2838 ctxt->src.val = 0;
2839 ctxt->src.bytes = 1;
2840 fastop(ctxt, em_or);
7f662273
GN		 2841
2842 return X86EMUL_CONTINUE;
2843}
2844
d4ddafcd
TY		 2845static int em_call(struct x86_emulate_ctxt *ctxt)
2846{
2847 long rel = ctxt->src.val;
2848
2849 ctxt->src.val = (unsigned long)ctxt->_eip;
2850 jmp_rel(ctxt, rel);
2851 return em_push(ctxt);
2852}
2853
0ef753b8
AK		 2854static int em_call_far(struct x86_emulate_ctxt *ctxt)
2855{
0ef753b8
AK		 2856 u16 sel, old_cs;
2857 ulong old_eip;
2858 int rc;
2859
1aa36616 2860 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2861 old_eip = ctxt->_eip;
0ef753b8 2862
9dac77fa 2863 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2864 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2865 return X86EMUL_CONTINUE;
2866
9dac77fa
AK		 2867 ctxt->_eip = 0;
2868 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2869
9dac77fa 2870 ctxt->src.val = old_cs;
4487b3b4 2871 rc = em_push(ctxt);
0ef753b8
AK		 2872 if (rc != X86EMUL_CONTINUE)
2873 return rc;
2874
9dac77fa 2875 ctxt->src.val = old_eip;
4487b3b4 2876 return em_push(ctxt);
0ef753b8
AK		 2877}
2878
40ece7c7
AK		 2879static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2880{
40ece7c7
AK		 2881 int rc;
2882
9dac77fa
AK		 2883 ctxt->dst.type = OP_REG;
2884 ctxt->dst.addr.reg = &ctxt->_eip;
2885 ctxt->dst.bytes = ctxt->op_bytes;
2886 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2887 if (rc != X86EMUL_CONTINUE)
2888 return rc;
5ad105e5 2889 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2890 return X86EMUL_CONTINUE;
2891}
2892
e4f973ae
TY		 2893static int em_xchg(struct x86_emulate_ctxt *ctxt)
2894{
e4f973ae 2895 /* Write back the register source. */
9dac77fa
AK		 2896 ctxt->src.val = ctxt->dst.val;
2897 write_register_operand(&ctxt->src);
e4f973ae
TY		 2898
2899 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2900 ctxt->dst.val = ctxt->src.orig_val;
2901 ctxt->lock_prefix = 1;
e4f973ae
TY		 2902 return X86EMUL_CONTINUE;
2903}
2904
5c82aa29
AK		 2905static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2906{
9dac77fa 2907 ctxt->dst.val = ctxt->src2.val;
4d758349 2908 return fastop(ctxt, em_imul);
5c82aa29
AK		 2909}
2910
61429142
AK		 2911static int em_cwd(struct x86_emulate_ctxt *ctxt)
2912{
9dac77fa
AK		 2913 ctxt->dst.type = OP_REG;
2914 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2915 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2916 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2917
2918 return X86EMUL_CONTINUE;
2919}
2920
48bb5d3c
AK		 2921static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2922{
48bb5d3c
AK		 2923 u64 tsc = 0;
2924
717746e3 2925 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2926 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2927 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2928 return X86EMUL_CONTINUE;
2929}
2930
222d21aa
AK		 2931static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2932{
2933 u64 pmc;
2934
dd856efa 2935 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2936 return emulate_gp(ctxt, 0);
dd856efa
AK		 2937 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2938 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2939 return X86EMUL_CONTINUE;
2940}
2941
b9eac5f4
AK		 2942static int em_mov(struct x86_emulate_ctxt *ctxt)
2943{
49597d81 2944 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2945 return X86EMUL_CONTINUE;
2946}
2947
bc00f8d2
TY		 2948static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2949{
2950 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2951 return emulate_gp(ctxt, 0);
2952
2953 /* Disable writeback. */
2954 ctxt->dst.type = OP_NONE;
2955 return X86EMUL_CONTINUE;
2956}
2957
2958static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2959{
2960 unsigned long val;
2961
2962 if (ctxt->mode == X86EMUL_MODE_PROT64)
2963 val = ctxt->src.val & ~0ULL;
2964 else
2965 val = ctxt->src.val & ~0U;
2966
2967 /* #UD condition is already handled. */
2968 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2969 return emulate_gp(ctxt, 0);
2970
2971 /* Disable writeback. */
2972 ctxt->dst.type = OP_NONE;
2973 return X86EMUL_CONTINUE;
2974}
2975
e1e210b0
TY		 2976static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2977{
2978 u64 msr_data;
2979
dd856efa
AK		 2980 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
2981 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
2982 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 2983 return emulate_gp(ctxt, 0);
2984
2985 return X86EMUL_CONTINUE;
2986}
2987
2988static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2989{
2990 u64 msr_data;
2991
dd856efa 2992 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 2993 return emulate_gp(ctxt, 0);
2994
dd856efa
AK		 2995 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
2996 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 2997 return X86EMUL_CONTINUE;
2998}
2999
1bd5f469
TY		 3000static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3001{
9dac77fa 3002 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3003 return emulate_ud(ctxt);
3004
9dac77fa 3005 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3006 return X86EMUL_CONTINUE;
3007}
3008
3009static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3010{
9dac77fa 3011 u16 sel = ctxt->src.val;
1bd5f469 3012
9dac77fa 3013 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3014 return emulate_ud(ctxt);
3015
9dac77fa 3016 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3017 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3018
3019 /* Disable writeback. */
9dac77fa
AK		 3020 ctxt->dst.type = OP_NONE;
3021 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3022}
3023
a14e579f
AK		 3024static int em_lldt(struct x86_emulate_ctxt *ctxt)
3025{
3026 u16 sel = ctxt->src.val;
3027
3028 /* Disable writeback. */
3029 ctxt->dst.type = OP_NONE;
3030 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3031}
3032
80890006
AK		 3033static int em_ltr(struct x86_emulate_ctxt *ctxt)
3034{
3035 u16 sel = ctxt->src.val;
3036
3037 /* Disable writeback. */
3038 ctxt->dst.type = OP_NONE;
3039 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3040}
3041
38503911
AK		 3042static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3043{
9fa088f4
AK		 3044 int rc;
3045 ulong linear;
3046
9dac77fa 3047 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3048 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3049 ctxt->ops->invlpg(ctxt, linear);
38503911 3050 /* Disable writeback. */
9dac77fa 3051 ctxt->dst.type = OP_NONE;
38503911
AK		 3052 return X86EMUL_CONTINUE;
3053}
3054
2d04a05b
AK		 3055static int em_clts(struct x86_emulate_ctxt *ctxt)
3056{
3057 ulong cr0;
3058
3059 cr0 = ctxt->ops->get_cr(ctxt, 0);
3060 cr0 &= ~X86_CR0_TS;
3061 ctxt->ops->set_cr(ctxt, 0, cr0);
3062 return X86EMUL_CONTINUE;
3063}
3064
26d05cc7
AK		 3065static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3066{
26d05cc7
AK		 3067 int rc;
3068
9dac77fa 3069 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3070 return X86EMUL_UNHANDLEABLE;
3071
3072 rc = ctxt->ops->fix_hypercall(ctxt);
3073 if (rc != X86EMUL_CONTINUE)
3074 return rc;
3075
3076 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3077 ctxt->_eip = ctxt->eip;
26d05cc7 3078 /* Disable writeback. */
9dac77fa 3079 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3080 return X86EMUL_CONTINUE;
3081}
3082
96051572
AK		 3083static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3084 void (*get)(struct x86_emulate_ctxt *ctxt,
3085 struct desc_ptr *ptr))
3086{
3087 struct desc_ptr desc_ptr;
3088
3089 if (ctxt->mode == X86EMUL_MODE_PROT64)
3090 ctxt->op_bytes = 8;
3091 get(ctxt, &desc_ptr);
3092 if (ctxt->op_bytes == 2) {
3093 ctxt->op_bytes = 4;
3094 desc_ptr.address &= 0x00ffffff;
3095 }
3096 /* Disable writeback. */
3097 ctxt->dst.type = OP_NONE;
3098 return segmented_write(ctxt, ctxt->dst.addr.mem,
3099 &desc_ptr, 2 + ctxt->op_bytes);
3100}
3101
3102static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3103{
3104 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3105}
3106
3107static int em_sidt(struct x86_emulate_ctxt *ctxt)
3108{
3109 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3110}
3111
26d05cc7
AK		 3112static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3113{
26d05cc7
AK		 3114 struct desc_ptr desc_ptr;
3115 int rc;
3116
510425ff
AK		 3117 if (ctxt->mode == X86EMUL_MODE_PROT64)
3118 ctxt->op_bytes = 8;
9dac77fa 3119 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3120 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3121 ctxt->op_bytes);
26d05cc7
AK		 3122 if (rc != X86EMUL_CONTINUE)
3123 return rc;
3124 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3125 /* Disable writeback. */
9dac77fa 3126 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3127 return X86EMUL_CONTINUE;
3128}
3129
5ef39c71 3130static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3131{
26d05cc7
AK		 3132 int rc;
3133
5ef39c71
AK		 3134 rc = ctxt->ops->fix_hypercall(ctxt);
3135
26d05cc7 3136 /* Disable writeback. */
9dac77fa 3137 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3138 return rc;
3139}
3140
3141static int em_lidt(struct x86_emulate_ctxt *ctxt)
3142{
26d05cc7
AK		 3143 struct desc_ptr desc_ptr;
3144 int rc;
3145
510425ff
AK		 3146 if (ctxt->mode == X86EMUL_MODE_PROT64)
3147 ctxt->op_bytes = 8;
9dac77fa 3148 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3149 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3150 ctxt->op_bytes);
26d05cc7
AK		 3151 if (rc != X86EMUL_CONTINUE)
3152 return rc;
3153 ctxt->ops->set_idt(ctxt, &desc_ptr);
3154 /* Disable writeback. */
9dac77fa 3155 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3156 return X86EMUL_CONTINUE;
3157}
3158
3159static int em_smsw(struct x86_emulate_ctxt *ctxt)
3160{
9dac77fa
AK		 3161 ctxt->dst.bytes = 2;
3162 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3163 return X86EMUL_CONTINUE;
3164}
3165
3166static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3167{
26d05cc7 3168 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3169 | (ctxt->src.val & 0x0f));
3170 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3171 return X86EMUL_CONTINUE;
3172}
3173
d06e03ad
TY		 3174static int em_loop(struct x86_emulate_ctxt *ctxt)
3175{
dd856efa
AK		 3176 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3177 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3178 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3179 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3180
3181 return X86EMUL_CONTINUE;
3182}
3183
3184static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3185{
dd856efa 3186 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3187 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3188
3189 return X86EMUL_CONTINUE;
3190}
3191
d7841a4b
TY		 3192static int em_in(struct x86_emulate_ctxt *ctxt)
3193{
3194 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3195 &ctxt->dst.val))
3196 return X86EMUL_IO_NEEDED;
3197
3198 return X86EMUL_CONTINUE;
3199}
3200
3201static int em_out(struct x86_emulate_ctxt *ctxt)
3202{
3203 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3204 &ctxt->src.val, 1);
3205 /* Disable writeback. */
3206 ctxt->dst.type = OP_NONE;
3207 return X86EMUL_CONTINUE;
3208}
3209
f411e6cd
TY		 3210static int em_cli(struct x86_emulate_ctxt *ctxt)
3211{
3212 if (emulator_bad_iopl(ctxt))
3213 return emulate_gp(ctxt, 0);
3214
3215 ctxt->eflags &= ~X86_EFLAGS_IF;
3216 return X86EMUL_CONTINUE;
3217}
3218
3219static int em_sti(struct x86_emulate_ctxt *ctxt)
3220{
3221 if (emulator_bad_iopl(ctxt))
3222 return emulate_gp(ctxt, 0);
3223
3224 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3225 ctxt->eflags |= X86_EFLAGS_IF;
3226 return X86EMUL_CONTINUE;
3227}
3228
6d6eede4
AK		 3229static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3230{
3231 u32 eax, ebx, ecx, edx;
3232
dd856efa
AK		 3233 eax = reg_read(ctxt, VCPU_REGS_RAX);
3234 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3235 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3236 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3237 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3238 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3239 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3240 return X86EMUL_CONTINUE;
3241}
3242
2dd7caa0
AK		 3243static int em_lahf(struct x86_emulate_ctxt *ctxt)
3244{
dd856efa
AK		 3245 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3246 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3247 return X86EMUL_CONTINUE;
3248}
3249
9299836e
AK		 3250static int em_bswap(struct x86_emulate_ctxt *ctxt)
3251{
3252 switch (ctxt->op_bytes) {
3253#ifdef CONFIG_X86_64
3254 case 8:
3255 asm("bswap %0" : "+r"(ctxt->dst.val));
3256 break;
3257#endif
3258 default:
3259 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3260 break;
3261 }
3262 return X86EMUL_CONTINUE;
3263}
3264
cfec82cb
JR		 3265static bool valid_cr(int nr)
3266{
3267 switch (nr) {
3268 case 0:
3269 case 2 ... 4:
3270 case 8:
3271 return true;
3272 default:
3273 return false;
3274 }
3275}
3276
3277static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3278{
9dac77fa 3279 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3280 return emulate_ud(ctxt);
3281
3282 return X86EMUL_CONTINUE;
3283}
3284
3285static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3286{
9dac77fa
AK		 3287 u64 new_val = ctxt->src.val64;
3288 int cr = ctxt->modrm_reg;
c2ad2bb3 3289 u64 efer = 0;
cfec82cb
JR		 3290
3291 static u64 cr_reserved_bits[] = {
3292 0xffffffff00000000ULL,
3293 0, 0, 0, /* CR3 checked later */
3294 CR4_RESERVED_BITS,
3295 0, 0, 0,
3296 CR8_RESERVED_BITS,
3297 };
3298
3299 if (!valid_cr(cr))
3300 return emulate_ud(ctxt);
3301
3302 if (new_val & cr_reserved_bits[cr])
3303 return emulate_gp(ctxt, 0);
3304
3305 switch (cr) {
3306 case 0: {
c2ad2bb3 3307 u64 cr4;
cfec82cb
JR		 3308 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3309 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3310 return emulate_gp(ctxt, 0);
3311
717746e3
AK		 3312 cr4 = ctxt->ops->get_cr(ctxt, 4);
3313 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3314
3315 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3316 !(cr4 & X86_CR4_PAE))
3317 return emulate_gp(ctxt, 0);
3318
3319 break;
3320 }
3321 case 3: {
3322 u64 rsvd = 0;
3323
c2ad2bb3
AK		 3324 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3325 if (efer & EFER_LMA)
cfec82cb 3326 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3327 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3328 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3329 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3330 rsvd = CR3_NONPAE_RESERVED_BITS;
3331
3332 if (new_val & rsvd)
3333 return emulate_gp(ctxt, 0);
3334
3335 break;
3336 }
3337 case 4: {
717746e3 3338 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3339
3340 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3341 return emulate_gp(ctxt, 0);
3342
3343 break;
3344 }
3345 }
3346
3347 return X86EMUL_CONTINUE;
3348}
3349
3b88e41a
JR		 3350static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3351{
3352 unsigned long dr7;
3353
717746e3 3354 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3355
3356 /* Check if DR7.Global_Enable is set */
3357 return dr7 & (1 << 13);
3358}
3359
3360static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3361{
9dac77fa 3362 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3363 u64 cr4;
3364
3365 if (dr > 7)
3366 return emulate_ud(ctxt);
3367
717746e3 3368 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3369 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3370 return emulate_ud(ctxt);
3371
3372 if (check_dr7_gd(ctxt))
3373 return emulate_db(ctxt);
3374
3375 return X86EMUL_CONTINUE;
3376}
3377
3378static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3379{
9dac77fa
AK		 3380 u64 new_val = ctxt->src.val64;
3381 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3382
3383 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3384 return emulate_gp(ctxt, 0);
3385
3386 return check_dr_read(ctxt);
3387}
3388
01de8b09
JR		 3389static int check_svme(struct x86_emulate_ctxt *ctxt)
3390{
3391 u64 efer;
3392
717746e3 3393 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3394
3395 if (!(efer & EFER_SVME))
3396 return emulate_ud(ctxt);
3397
3398 return X86EMUL_CONTINUE;
3399}
3400
3401static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3402{
dd856efa 3403 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3404
3405 /* Valid physical address? */
d4224449 3406 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3407 return emulate_gp(ctxt, 0);
3408
3409 return check_svme(ctxt);
3410}
3411
d7eb8203
JR		 3412static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3413{
717746e3 3414 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3415
717746e3 3416 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3417 return emulate_ud(ctxt);
3418
3419 return X86EMUL_CONTINUE;
3420}
3421
8061252e
JR		 3422static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3423{
717746e3 3424 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3425 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3426
717746e3 3427 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3428 (rcx > 3))
3429 return emulate_gp(ctxt, 0);
3430
3431 return X86EMUL_CONTINUE;
3432}
3433
f6511935
JR		 3434static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3435{
9dac77fa
AK		 3436 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3437 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3438 return emulate_gp(ctxt, 0);
3439
3440 return X86EMUL_CONTINUE;
3441}
3442
3443static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3444{
9dac77fa
AK		 3445 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3446 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3447 return emulate_gp(ctxt, 0);
3448
3449 return X86EMUL_CONTINUE;
3450}
3451
73fba5f4 3452#define D(_y) { .flags = (_y) }
c4f035c6 3453#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3454#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3455 .check_perm = (_p) }
0b789eee 3456#define N D(NotImpl)
01de8b09 3457#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3458#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3459#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3460#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3461#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3462#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3463#define II(_f, _e, _i) \
3464 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3465#define IIP(_f, _e, _i, _p) \
3466 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3467 .check_perm = (_p) }
aa97bb48 3468#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3469
8d8f4e9f 3470#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3471#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3472#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3473#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3474#define I2bvIP(_f, _e, _i, _p) \
3475 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3476
fb864fbc
AK		 3477#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3478 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3479 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3480
fd0a0d82 3481static const struct opcode group7_rm1[] = {
1c2545be
TY		 3482 DI(SrcNone | Priv, monitor),
3483 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3484 N, N, N, N, N, N,
3485};
3486
fd0a0d82 3487static const struct opcode group7_rm3[] = {
1c2545be
TY		 3488 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3489 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3490 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3491 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3492 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3493 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3494 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3495 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3496};
6230f7fc 3497
fd0a0d82 3498static const struct opcode group7_rm7[] = {
d7eb8203 3499 N,
1c2545be 3500 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3501 N, N, N, N, N, N,
3502};
d67fc27a 3503
fd0a0d82 3504static const struct opcode group1[] = {
fb864fbc
AK		 3505 F(Lock, em_add),
3506 F(Lock | PageTable, em_or),
3507 F(Lock, em_adc),
3508 F(Lock, em_sbb),
3509 F(Lock | PageTable, em_and),
3510 F(Lock, em_sub),
3511 F(Lock, em_xor),
3512 F(NoWrite, em_cmp),
73fba5f4
AK		 3513};
3514
fd0a0d82 3515static const struct opcode group1A[] = {
1c2545be 3516 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3517};
3518
007a3b54
AK		 3519static const struct opcode group2[] = {
3520 F(DstMem | ModRM, em_rol),
3521 F(DstMem | ModRM, em_ror),
3522 F(DstMem | ModRM, em_rcl),
3523 F(DstMem | ModRM, em_rcr),
3524 F(DstMem | ModRM, em_shl),
3525 F(DstMem | ModRM, em_shr),
3526 F(DstMem | ModRM, em_shl),
3527 F(DstMem | ModRM, em_sar),
3528};
3529
fd0a0d82 3530static const struct opcode group3[] = {
fb864fbc
AK		 3531 F(DstMem | SrcImm | NoWrite, em_test),
3532 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3533 F(DstMem | SrcNone | Lock, em_not),
3534 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3535 F(DstXacc | Src2Mem, em_mul_ex),
3536 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3537 F(DstXacc | Src2Mem, em_div_ex),
3538 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3539};
3540
fd0a0d82 3541static const struct opcode group4[] = {
95413dc4
AK		 3542 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3543 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3544 N, N, N, N, N, N,
3545};
3546
fd0a0d82 3547static const struct opcode group5[] = {
95413dc4
AK		 3548 F(DstMem | SrcNone | Lock, em_inc),
3549 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3550 I(SrcMem | Stack, em_grp45),
3551 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3552 I(SrcMem | Stack, em_grp45),
3553 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3554 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3555};
3556
fd0a0d82 3557static const struct opcode group6[] = {
1c2545be
TY		 3558 DI(Prot, sldt),
3559 DI(Prot, str),
a14e579f 3560 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3561 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3562 N, N, N, N,
3563};
3564
fd0a0d82 3565static const struct group_dual group7 = { {
96051572
AK		 3566 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3567 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3568 II(SrcMem | Priv, em_lgdt, lgdt),
3569 II(SrcMem | Priv, em_lidt, lidt),
3570 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3571 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3572 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3573}, {
1c2545be 3574 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3575 EXT(0, group7_rm1),
01de8b09 3576 N, EXT(0, group7_rm3),
1c2545be
TY		 3577 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3578 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3579 EXT(0, group7_rm7),
73fba5f4
AK		 3580} };
3581
fd0a0d82 3582static const struct opcode group8[] = {
73fba5f4 3583 N, N, N, N,
11c363ba
AK		 3584 F(DstMem | SrcImmByte | NoWrite, em_bt),
3585 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3586 F(DstMem | SrcImmByte | Lock, em_btr),
3587 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3588};
3589
fd0a0d82 3590static const struct group_dual group9 = { {
1c2545be 3591 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3592}, {
3593 N, N, N, N, N, N, N, N,
3594} };
3595
fd0a0d82 3596static const struct opcode group11[] = {
1c2545be 3597 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3598 X7(D(Undefined)),
a4d4a7c1
AK		 3599};
3600
fd0a0d82 3601static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3602 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3603};
3604
fd0a0d82 3605static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3606 I(0, em_mov), N, N, N,
3607};
3608
045a282c
GN		 3609static const struct escape escape_d9 = { {
3610 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3611}, {
3612 /* 0xC0 - 0xC7 */
3613 N, N, N, N, N, N, N, N,
3614 /* 0xC8 - 0xCF */
3615 N, N, N, N, N, N, N, N,
3616 /* 0xD0 - 0xC7 */
3617 N, N, N, N, N, N, N, N,
3618 /* 0xD8 - 0xDF */
3619 N, N, N, N, N, N, N, N,
3620 /* 0xE0 - 0xE7 */
3621 N, N, N, N, N, N, N, N,
3622 /* 0xE8 - 0xEF */
3623 N, N, N, N, N, N, N, N,
3624 /* 0xF0 - 0xF7 */
3625 N, N, N, N, N, N, N, N,
3626 /* 0xF8 - 0xFF */
3627 N, N, N, N, N, N, N, N,
3628} };
3629
3630static const struct escape escape_db = { {
3631 N, N, N, N, N, N, N, N,
3632}, {
3633 /* 0xC0 - 0xC7 */
3634 N, N, N, N, N, N, N, N,
3635 /* 0xC8 - 0xCF */
3636 N, N, N, N, N, N, N, N,
3637 /* 0xD0 - 0xC7 */
3638 N, N, N, N, N, N, N, N,
3639 /* 0xD8 - 0xDF */
3640 N, N, N, N, N, N, N, N,
3641 /* 0xE0 - 0xE7 */
3642 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3643 /* 0xE8 - 0xEF */
3644 N, N, N, N, N, N, N, N,
3645 /* 0xF0 - 0xF7 */
3646 N, N, N, N, N, N, N, N,
3647 /* 0xF8 - 0xFF */
3648 N, N, N, N, N, N, N, N,
3649} };
3650
3651static const struct escape escape_dd = { {
3652 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3653}, {
3654 /* 0xC0 - 0xC7 */
3655 N, N, N, N, N, N, N, N,
3656 /* 0xC8 - 0xCF */
3657 N, N, N, N, N, N, N, N,
3658 /* 0xD0 - 0xC7 */
3659 N, N, N, N, N, N, N, N,
3660 /* 0xD8 - 0xDF */
3661 N, N, N, N, N, N, N, N,
3662 /* 0xE0 - 0xE7 */
3663 N, N, N, N, N, N, N, N,
3664 /* 0xE8 - 0xEF */
3665 N, N, N, N, N, N, N, N,
3666 /* 0xF0 - 0xF7 */
3667 N, N, N, N, N, N, N, N,
3668 /* 0xF8 - 0xFF */
3669 N, N, N, N, N, N, N, N,
3670} };
3671
fd0a0d82 3672static const struct opcode opcode_table[256] = {
73fba5f4 3673 /* 0x00 - 0x07 */
fb864fbc 3674 F6ALU(Lock, em_add),
1cd196ea
AK		 3675 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3676 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3677 /* 0x08 - 0x0F */
fb864fbc 3678 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3679 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3680 N,
73fba5f4 3681 /* 0x10 - 0x17 */
fb864fbc 3682 F6ALU(Lock, em_adc),
1cd196ea
AK		 3683 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3684 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3685 /* 0x18 - 0x1F */
fb864fbc 3686 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3687 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3688 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3689 /* 0x20 - 0x27 */
fb864fbc 3690 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3691 /* 0x28 - 0x2F */
fb864fbc 3692 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3693 /* 0x30 - 0x37 */
fb864fbc 3694 F6ALU(Lock, em_xor), N, N,
73fba5f4 3695 /* 0x38 - 0x3F */
fb864fbc 3696 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3697 /* 0x40 - 0x4F */
95413dc4 3698 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3699 /* 0x50 - 0x57 */
63540382 3700 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3701 /* 0x58 - 0x5F */
c54fe504 3702 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3703 /* 0x60 - 0x67 */
b96a7fad
TY		 3704 I(ImplicitOps | Stack | No64, em_pusha),
3705 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3706 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3707 N, N, N, N,
3708 /* 0x68 - 0x6F */
d46164db
AK		 3709 I(SrcImm | Mov | Stack, em_push),
3710 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3711 I(SrcImmByte | Mov | Stack, em_push),
3712 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3713 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3714 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3715 /* 0x70 - 0x7F */
3716 X16(D(SrcImmByte)),
3717 /* 0x80 - 0x87 */
1c2545be
TY		 3718 G(ByteOp | DstMem | SrcImm, group1),
3719 G(DstMem | SrcImm, group1),
3720 G(ByteOp | DstMem | SrcImm | No64, group1),
3721 G(DstMem | SrcImmByte, group1),
fb864fbc 3722 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3723 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3724 /* 0x88 - 0x8F */
d5ae7ce8 3725 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3726 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3727 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3728 D(ModRM | SrcMem | NoAccess | DstReg),
3729 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3730 G(0, group1A),
73fba5f4 3731 /* 0x90 - 0x97 */
bf608f88 3732 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3733 /* 0x98 - 0x9F */
61429142 3734 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3735 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3736 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3737 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3738 /* 0xA0 - 0xA7 */
b9eac5f4 3739 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3740 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3741 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3742 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3743 /* 0xA8 - 0xAF */
fb864fbc 3744 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3745 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3746 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3747 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3748 /* 0xB0 - 0xB7 */
b9eac5f4 3749 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3750 /* 0xB8 - 0xBF */
5e2c6883 3751 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3752 /* 0xC0 - 0xC7 */
007a3b54 3753 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3754 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3755 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3756 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3757 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3758 G(ByteOp, group11), G(0, group11),
73fba5f4 3759 /* 0xC8 - 0xCF */
612e89f0
AK		 3760 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3761 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3762 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3763 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3764 /* 0xD0 - 0xD7 */
007a3b54
AK		 3765 G(Src2One | ByteOp, group2), G(Src2One, group2),
3766 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3767 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3768 I(DstAcc | SrcImmUByte | No64, em_aad),
3769 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3770 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3771 /* 0xD8 - 0xDF */
045a282c 3772 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3773 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3774 X3(I(SrcImmByte, em_loop)),
3775 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3776 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3777 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3778 /* 0xE8 - 0xEF */
d4ddafcd 3779 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3780 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3781 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3782 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3783 /* 0xF0 - 0xF7 */
bf608f88 3784 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3785 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3786 G(ByteOp, group3), G(0, group3),
73fba5f4 3787 /* 0xF8 - 0xFF */
f411e6cd
TY		 3788 D(ImplicitOps), D(ImplicitOps),
3789 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3790 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3791};
3792
fd0a0d82 3793static const struct opcode twobyte_table[256] = {
73fba5f4 3794 /* 0x00 - 0x0F */
dee6bb70 3795 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3796 N, I(ImplicitOps | VendorSpecific, em_syscall),
3797 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3798 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3799 N, D(ImplicitOps | ModRM), N, N,
3800 /* 0x10 - 0x1F */
3801 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3802 /* 0x20 - 0x2F */
cfec82cb 3803 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3804 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3805 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3806 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3807 N, N, N, N,
3e114eb4
AK		 3808 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3809 N, N, N, N,
73fba5f4 3810 /* 0x30 - 0x3F */
e1e210b0 3811 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3812 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3813 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3814 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3815 I(ImplicitOps | VendorSpecific, em_sysenter),
3816 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3817 N, N,
73fba5f4
AK		 3818 N, N, N, N, N, N, N, N,
3819 /* 0x40 - 0x4F */
3820 X16(D(DstReg | SrcMem | ModRM | Mov)),
3821 /* 0x50 - 0x5F */
3822 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3823 /* 0x60 - 0x6F */
aa97bb48
AK		 3824 N, N, N, N,
3825 N, N, N, N,
3826 N, N, N, N,
3827 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3828 /* 0x70 - 0x7F */
aa97bb48
AK		 3829 N, N, N, N,
3830 N, N, N, N,
3831 N, N, N, N,
3832 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3833 /* 0x80 - 0x8F */
3834 X16(D(SrcImm)),
3835 /* 0x90 - 0x9F */
ee45b58e 3836 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3837 /* 0xA0 - 0xA7 */
1cd196ea 3838 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3839 II(ImplicitOps, em_cpuid, cpuid),
3840 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3841 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3842 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3843 /* 0xA8 - 0xAF */
1cd196ea 3844 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3845 DI(ImplicitOps, rsm),
11c363ba 3846 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3847 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3848 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3849 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3850 /* 0xB0 - 0xB7 */
e940b5c2 3851 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3852 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3853 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3854 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3855 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3856 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3857 /* 0xB8 - 0xBF */
3858 N, N,
ce7faab2 3859 G(BitOp, group8),
11c363ba
AK		 3860 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3861 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3862 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3863 /* 0xC0 - 0xC7 */
739ae406 3864 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3865 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3866 N, N, N, GD(0, &group9),
9299836e
AK		 3867 /* 0xC8 - 0xCF */
3868 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3869 /* 0xD0 - 0xDF */
3870 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3871 /* 0xE0 - 0xEF */
3872 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3873 /* 0xF0 - 0xFF */
3874 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3875};
3876
3877#undef D
3878#undef N
3879#undef G
3880#undef GD
3881#undef I
aa97bb48 3882#undef GP
01de8b09 3883#undef EXT
73fba5f4 3884
8d8f4e9f 3885#undef D2bv
f6511935 3886#undef D2bvIP
8d8f4e9f 3887#undef I2bv
d7841a4b 3888#undef I2bvIP
d67fc27a 3889#undef I6ALU
8d8f4e9f 3890
9dac77fa 3891static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3892{
3893 unsigned size;
3894
9dac77fa 3895 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3896 if (size == 8)
3897 size = 4;
3898 return size;
3899}
3900
3901static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3902 unsigned size, bool sign_extension)
3903{
39f21ee5
AK		 3904 int rc = X86EMUL_CONTINUE;
3905
3906 op->type = OP_IMM;
3907 op->bytes = size;
9dac77fa 3908 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3909 /* NB. Immediates are sign-extended as necessary. */
3910 switch (op->bytes) {
3911 case 1:
e85a1085 3912 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3913 break;
3914 case 2:
e85a1085 3915 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3916 break;
3917 case 4:
e85a1085 3918 op->val = insn_fetch(s32, ctxt);
39f21ee5 3919 break;
5e2c6883
NA		 3920 case 8:
3921 op->val = insn_fetch(s64, ctxt);
3922 break;
39f21ee5
AK		 3923 }
3924 if (!sign_extension) {
3925 switch (op->bytes) {
3926 case 1:
3927 op->val &= 0xff;
3928 break;
3929 case 2:
3930 op->val &= 0xffff;
3931 break;
3932 case 4:
3933 op->val &= 0xffffffff;
3934 break;
3935 }
3936 }
3937done:
3938 return rc;
3939}
3940
a9945549
AK		 3941static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3942 unsigned d)
3943{
3944 int rc = X86EMUL_CONTINUE;
3945
3946 switch (d) {
3947 case OpReg:
2adb5ad9 3948 decode_register_operand(ctxt, op);
a9945549
AK		 3949 break;
3950 case OpImmUByte:
608aabe3 3951 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3952 break;
3953 case OpMem:
41ddf978 3954 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3955 mem_common:
3956 *op = ctxt->memop;
3957 ctxt->memopp = op;
3958 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3959 fetch_bit_operand(ctxt);
3960 op->orig_val = op->val;
3961 break;
41ddf978
AK		 3962 case OpMem64:
3963 ctxt->memop.bytes = 8;
3964 goto mem_common;
a9945549
AK		 3965 case OpAcc:
3966 op->type = OP_REG;
3967 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 3968 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 3969 fetch_register_operand(op);
3970 op->orig_val = op->val;
3971 break;
820207c8
AK		 3972 case OpAccLo:
3973 op->type = OP_REG;
3974 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
3975 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
3976 fetch_register_operand(op);
3977 op->orig_val = op->val;
3978 break;
3979 case OpAccHi:
3980 if (ctxt->d & ByteOp) {
3981 op->type = OP_NONE;
3982 break;
3983 }
3984 op->type = OP_REG;
3985 op->bytes = ctxt->op_bytes;
3986 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3987 fetch_register_operand(op);
3988 op->orig_val = op->val;
3989 break;
a9945549
AK		 3990 case OpDI:
3991 op->type = OP_MEM;
3992 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3993 op->addr.mem.ea =
dd856efa 3994 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 3995 op->addr.mem.seg = VCPU_SREG_ES;
3996 op->val = 0;
b3356bf0 3997 op->count = 1;
a9945549
AK		 3998 break;
3999 case OpDX:
4000 op->type = OP_REG;
4001 op->bytes = 2;
dd856efa 4002 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4003 fetch_register_operand(op);
4004 break;
4dd6a57d
AK		 4005 case OpCL:
4006 op->bytes = 1;
dd856efa 4007 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4008 break;
4009 case OpImmByte:
4010 rc = decode_imm(ctxt, op, 1, true);
4011 break;
4012 case OpOne:
4013 op->bytes = 1;
4014 op->val = 1;
4015 break;
4016 case OpImm:
4017 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4018 break;
5e2c6883
NA		 4019 case OpImm64:
4020 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4021 break;
28867cee
AK		 4022 case OpMem8:
4023 ctxt->memop.bytes = 1;
660696d1
GN		 4024 if (ctxt->memop.type == OP_REG) {
4025 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4026 fetch_register_operand(&ctxt->memop);
4027 }
28867cee 4028 goto mem_common;
0fe59128
AK		 4029 case OpMem16:
4030 ctxt->memop.bytes = 2;
4031 goto mem_common;
4032 case OpMem32:
4033 ctxt->memop.bytes = 4;
4034 goto mem_common;
4035 case OpImmU16:
4036 rc = decode_imm(ctxt, op, 2, false);
4037 break;
4038 case OpImmU:
4039 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4040 break;
4041 case OpSI:
4042 op->type = OP_MEM;
4043 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4044 op->addr.mem.ea =
dd856efa 4045 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4046 op->addr.mem.seg = seg_override(ctxt);
4047 op->val = 0;
b3356bf0 4048 op->count = 1;
0fe59128 4049 break;
7fa57952
PB		 4050 case OpXLat:
4051 op->type = OP_MEM;
4052 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4053 op->addr.mem.ea =
4054 register_address(ctxt,
4055 reg_read(ctxt, VCPU_REGS_RBX) +
4056 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4057 op->addr.mem.seg = seg_override(ctxt);
4058 op->val = 0;
4059 break;
0fe59128
AK		 4060 case OpImmFAddr:
4061 op->type = OP_IMM;
4062 op->addr.mem.ea = ctxt->_eip;
4063 op->bytes = ctxt->op_bytes + 2;
4064 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4065 break;
4066 case OpMemFAddr:
4067 ctxt->memop.bytes = ctxt->op_bytes + 2;
4068 goto mem_common;
c191a7a0
AK		 4069 case OpES:
4070 op->val = VCPU_SREG_ES;
4071 break;
4072 case OpCS:
4073 op->val = VCPU_SREG_CS;
4074 break;
4075 case OpSS:
4076 op->val = VCPU_SREG_SS;
4077 break;
4078 case OpDS:
4079 op->val = VCPU_SREG_DS;
4080 break;
4081 case OpFS:
4082 op->val = VCPU_SREG_FS;
4083 break;
4084 case OpGS:
4085 op->val = VCPU_SREG_GS;
4086 break;
a9945549
AK		 4087 case OpImplicit:
4088 /* Special instructions do their own operand decoding. */
4089 default:
4090 op->type = OP_NONE; /* Disable writeback. */
4091 break;
4092 }
4093
4094done:
4095 return rc;
4096}
4097
ef5d75cc 4098int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4099{
dde7e6d1
AK		 4100 int rc = X86EMUL_CONTINUE;
4101 int mode = ctxt->mode;
46561646 4102 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4103 bool op_prefix = false;
46561646 4104 struct opcode opcode;
dde7e6d1 4105
f09ed83e
AK		 4106 ctxt->memop.type = OP_NONE;
4107 ctxt->memopp = NULL;
9dac77fa
AK		 4108 ctxt->_eip = ctxt->eip;
4109 ctxt->fetch.start = ctxt->_eip;
4110 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4111 if (insn_len > 0)
9dac77fa 4112 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4113
4114 switch (mode) {
4115 case X86EMUL_MODE_REAL:
4116 case X86EMUL_MODE_VM86:
4117 case X86EMUL_MODE_PROT16:
4118 def_op_bytes = def_ad_bytes = 2;
4119 break;
4120 case X86EMUL_MODE_PROT32:
4121 def_op_bytes = def_ad_bytes = 4;
4122 break;
4123#ifdef CONFIG_X86_64
4124 case X86EMUL_MODE_PROT64:
4125 def_op_bytes = 4;
4126 def_ad_bytes = 8;
4127 break;
4128#endif
4129 default:
1d2887e2 4130 return EMULATION_FAILED;
dde7e6d1
AK		 4131 }
4132
9dac77fa
AK		 4133 ctxt->op_bytes = def_op_bytes;
4134 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4135
4136 /* Legacy prefixes. */
4137 for (;;) {
e85a1085 4138 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4139 case 0x66: /* operand-size override */
0d7cdee8 4140 op_prefix = true;
dde7e6d1 4141 /* switch between 2/4 bytes */
9dac77fa 4142 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4143 break;
4144 case 0x67: /* address-size override */
4145 if (mode == X86EMUL_MODE_PROT64)
4146 /* switch between 4/8 bytes */
9dac77fa 4147 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4148 else
4149 /* switch between 2/4 bytes */
9dac77fa 4150 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4151 break;
4152 case 0x26: /* ES override */
4153 case 0x2e: /* CS override */
4154 case 0x36: /* SS override */
4155 case 0x3e: /* DS override */
9dac77fa 4156 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4157 break;
4158 case 0x64: /* FS override */
4159 case 0x65: /* GS override */
9dac77fa 4160 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4161 break;
4162 case 0x40 ... 0x4f: /* REX */
4163 if (mode != X86EMUL_MODE_PROT64)
4164 goto done_prefixes;
9dac77fa 4165 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4166 continue;
4167 case 0xf0: /* LOCK */
9dac77fa 4168 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4169 break;
4170 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4171 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4172 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4173 break;
4174 default:
4175 goto done_prefixes;
4176 }
4177
4178 /* Any legacy prefix after a REX prefix nullifies its effect. */
4179
9dac77fa 4180 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4181 }
4182
4183done_prefixes:
4184
4185 /* REX prefix. */
9dac77fa
AK		 4186 if (ctxt->rex_prefix & 8)
4187 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4188
4189 /* Opcode byte(s). */
9dac77fa 4190 opcode = opcode_table[ctxt->b];
d3ad6243 4191 /* Two-byte opcode? */
9dac77fa
AK		 4192 if (ctxt->b == 0x0f) {
4193 ctxt->twobyte = 1;
e85a1085 4194 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4195 opcode = twobyte_table[ctxt->b];
dde7e6d1 4196 }
9dac77fa 4197 ctxt->d = opcode.flags;
dde7e6d1 4198
9f4260e7
TY		 4199 if (ctxt->d & ModRM)
4200 ctxt->modrm = insn_fetch(u8, ctxt);
4201
9dac77fa
AK		 4202 while (ctxt->d & GroupMask) {
4203 switch (ctxt->d & GroupMask) {
46561646 4204 case Group:
9dac77fa 4205 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4206 opcode = opcode.u.group[goffset];
4207 break;
4208 case GroupDual:
9dac77fa
AK		 4209 goffset = (ctxt->modrm >> 3) & 7;
4210 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4211 opcode = opcode.u.gdual->mod3[goffset];
4212 else
4213 opcode = opcode.u.gdual->mod012[goffset];
4214 break;
4215 case RMExt:
9dac77fa 4216 goffset = ctxt->modrm & 7;
01de8b09 4217 opcode = opcode.u.group[goffset];
46561646
AK		 4218 break;
4219 case Prefix:
9dac77fa 4220 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4221 return EMULATION_FAILED;
9dac77fa 4222 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4223 switch (simd_prefix) {
4224 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4225 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4226 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4227 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4228 }
4229 break;
045a282c
GN		 4230 case Escape:
4231 if (ctxt->modrm > 0xbf)
4232 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4233 else
4234 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4235 break;
46561646 4236 default:
1d2887e2 4237 return EMULATION_FAILED;
0d7cdee8 4238 }
46561646 4239
b1ea50b2 4240 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4241 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4242 }
4243
9dac77fa
AK		 4244 ctxt->execute = opcode.u.execute;
4245 ctxt->check_perm = opcode.check_perm;
4246 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4247
4248 /* Unrecognised? */
1146a78b 4249 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4250 return EMULATION_FAILED;
dde7e6d1 4251
9dac77fa 4252 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4253 return EMULATION_FAILED;
d867162c 4254
9dac77fa
AK		 4255 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4256 ctxt->op_bytes = 8;
dde7e6d1 4257
9dac77fa 4258 if (ctxt->d & Op3264) {
7f9b4b75 4259 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4260 ctxt->op_bytes = 8;
7f9b4b75 4261 else
9dac77fa 4262 ctxt->op_bytes = 4;
7f9b4b75
AK		 4263 }
4264
9dac77fa
AK		 4265 if (ctxt->d & Sse)
4266 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4267 else if (ctxt->d & Mmx)
4268 ctxt->op_bytes = 8;
1253791d 4269
dde7e6d1 4270 /* ModRM and SIB bytes. */
9dac77fa 4271 if (ctxt->d & ModRM) {
f09ed83e 4272 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4273 if (!ctxt->has_seg_override)
4274 set_seg_override(ctxt, ctxt->modrm_seg);
4275 } else if (ctxt->d & MemAbs)
f09ed83e 4276 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4277 if (rc != X86EMUL_CONTINUE)
4278 goto done;
4279
9dac77fa
AK		 4280 if (!ctxt->has_seg_override)
4281 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4282
f09ed83e 4283 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4284
f09ed83e
AK		 4285 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4286 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4287
dde7e6d1
AK		 4288 /*
4289 * Decode and fetch the source operand: register, memory
4290 * or immediate.
4291 */
0fe59128 4292 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4293 if (rc != X86EMUL_CONTINUE)
4294 goto done;
4295
dde7e6d1
AK		 4296 /*
4297 * Decode and fetch the second source operand: register, memory
4298 * or immediate.
4299 */
4dd6a57d 4300 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4301 if (rc != X86EMUL_CONTINUE)
4302 goto done;
4303
dde7e6d1 4304 /* Decode and fetch the destination operand: register or memory. */
a9945549 4305 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4306
4307done:
f09ed83e
AK		 4308 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4309 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4310
1d2887e2 4311 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4312}
4313
1cb3f3ae
XG		 4314bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4315{
4316 return ctxt->d & PageTable;
4317}
4318
3e2f65d5
GN		 4319static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4320{
3e2f65d5
GN		 4321 /* The second termination condition only applies for REPE
4322 * and REPNE. Test if the repeat string operation prefix is
4323 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4324 * corresponding termination condition according to:
4325 * - if REPE/REPZ and ZF = 0 then done
4326 * - if REPNE/REPNZ and ZF = 1 then done
4327 */
9dac77fa
AK		 4328 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4329 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4330 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4331 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4332 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4333 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4334 return true;
4335
4336 return false;
4337}
4338
cbe2c9d3
AK		 4339static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4340{
4341 bool fault = false;
4342
4343 ctxt->ops->get_fpu(ctxt);
4344 asm volatile("1: fwait \n\t"
4345 "2: \n\t"
4346 ".pushsection .fixup,\"ax\" \n\t"
4347 "3: \n\t"
4348 "movb $1, %[fault] \n\t"
4349 "jmp 2b \n\t"
4350 ".popsection \n\t"
4351 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4352 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4353 ctxt->ops->put_fpu(ctxt);
4354
4355 if (unlikely(fault))
4356 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4357
4358 return X86EMUL_CONTINUE;
4359}
4360
4361static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4362 struct operand *op)
4363{
4364 if (op->type == OP_MM)
4365 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4366}
4367
e28bbd44
AK		 4368static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4369{
4370 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4371 if (!(ctxt->d & ByteOp))
4372 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4373 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4374 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4375 [fastop]"+S"(fop)
4376 : "c"(ctxt->src2.val));
e28bbd44 4377 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4378 if (!fop) /* exception is returned in fop variable */
4379 return emulate_de(ctxt);
e28bbd44
AK		 4380 return X86EMUL_CONTINUE;
4381}
dd856efa 4382
7b105ca2 4383int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4384{
0225fb50 4385 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4386 int rc = X86EMUL_CONTINUE;
9dac77fa 4387 int saved_dst_type = ctxt->dst.type;
8b4caf66 4388
9dac77fa 4389 ctxt->mem_read.pos = 0;
310b5d30 4390
1146a78b
GN		 4391 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4392 (ctxt->d & Undefined)) {
35d3d4a1 4393 rc = emulate_ud(ctxt);
1161624f
GN		 4394 goto done;
4395 }
4396
d380a5e4 4397 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4398 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4399 rc = emulate_ud(ctxt);
d380a5e4
GN		 4400 goto done;
4401 }
4402
9dac77fa 4403 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4404 rc = emulate_ud(ctxt);
081bca0e
AK		 4405 goto done;
4406 }
4407
cbe2c9d3
AK		 4408 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4409 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4410 rc = emulate_ud(ctxt);
4411 goto done;
4412 }
4413
cbe2c9d3 4414 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4415 rc = emulate_nm(ctxt);
4416 goto done;
4417 }
4418
cbe2c9d3
AK		 4419 if (ctxt->d & Mmx) {
4420 rc = flush_pending_x87_faults(ctxt);
4421 if (rc != X86EMUL_CONTINUE)
4422 goto done;
4423 /*
4424 * Now that we know the fpu is exception safe, we can fetch
4425 * operands from it.
4426 */
4427 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4428 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4429 if (!(ctxt->d & Mov))
4430 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4431 }
4432
9dac77fa
AK		 4433 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4434 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4435 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4436 if (rc != X86EMUL_CONTINUE)
4437 goto done;
4438 }
4439
e92805ac 4440 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4441 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4442 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4443 goto done;
4444 }
4445
8ea7d6ae 4446 /* Instruction can only be executed in protected mode */
9d1b39a9 4447 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4448 rc = emulate_ud(ctxt);
4449 goto done;
4450 }
4451
d09beabd 4452 /* Do instruction specific permission checks */
9dac77fa
AK		 4453 if (ctxt->check_perm) {
4454 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4455 if (rc != X86EMUL_CONTINUE)
4456 goto done;
4457 }
4458
9dac77fa
AK		 4459 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4460 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4461 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4462 if (rc != X86EMUL_CONTINUE)
4463 goto done;
4464 }
4465
9dac77fa 4466 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4467 /* All REP prefixes have the same first termination condition */
dd856efa 4468 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4469 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4470 goto done;
4471 }
b9fa9d6b
AK		 4472 }
4473
9dac77fa
AK		 4474 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4475 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4476 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4477 if (rc != X86EMUL_CONTINUE)
8b4caf66 4478 goto done;
9dac77fa 4479 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4480 }
4481
9dac77fa
AK		 4482 if (ctxt->src2.type == OP_MEM) {
4483 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4484 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4485 if (rc != X86EMUL_CONTINUE)
4486 goto done;
4487 }
4488
9dac77fa 4489 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4490 goto special_insn;
4491
4492
9dac77fa 4493 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4494 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4495 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4496 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4497 if (rc != X86EMUL_CONTINUE)
4498 goto done;
038e51de 4499 }
9dac77fa 4500 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4501
018a98db
AK		 4502special_insn:
4503
9dac77fa
AK		 4504 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4505 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4506 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4507 if (rc != X86EMUL_CONTINUE)
4508 goto done;
4509 }
4510
9dac77fa 4511 if (ctxt->execute) {
e28bbd44
AK		 4512 if (ctxt->d & Fastop) {
4513 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4514 rc = fastop(ctxt, fop);
4515 if (rc != X86EMUL_CONTINUE)
4516 goto done;
4517 goto writeback;
4518 }
9dac77fa 4519 rc = ctxt->execute(ctxt);
ef65c889
AK		 4520 if (rc != X86EMUL_CONTINUE)
4521 goto done;
4522 goto writeback;
4523 }
4524
9dac77fa 4525 if (ctxt->twobyte)
6aa8b732
AK		 4526 goto twobyte_insn;
4527
9dac77fa 4528 switch (ctxt->b) {
6aa8b732 4529 case 0x63: /* movsxd */
8b4caf66 4530 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4531 goto cannot_emulate;
9dac77fa 4532 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4533 break;
b2833e3c 4534 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4535 if (test_cc(ctxt->b, ctxt->eflags))
4536 jmp_rel(ctxt, ctxt->src.val);
018a98db 4537 break;
7e0b54b1 4538 case 0x8d: /* lea r16/r32, m */
9dac77fa 4539 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4540 break;
3d9e77df 4541 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4542 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4543 break;
e4f973ae
TY		 4544 rc = em_xchg(ctxt);
4545 break;
e8b6fa70 4546 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4547 switch (ctxt->op_bytes) {
4548 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4549 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4550 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4551 }
4552 break;
6e154e56 4553 case 0xcc: /* int3 */
5c5df76b
TY		 4554 rc = emulate_int(ctxt, 3);
4555 break;
6e154e56 4556 case 0xcd: /* int n */
9dac77fa 4557 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4558 break;
4559 case 0xce: /* into */
5c5df76b
TY		 4560 if (ctxt->eflags & EFLG_OF)
4561 rc = emulate_int(ctxt, 4);
6e154e56 4562 break;
1a52e051 4563 case 0xe9: /* jmp rel */
db5b0762 4564 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4565 jmp_rel(ctxt, ctxt->src.val);
4566 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4567 break;
111de5d6 4568 case 0xf4: /* hlt */
6c3287f7 4569 ctxt->ops->halt(ctxt);
19fdfa0d 4570 break;
111de5d6
AK		 4571 case 0xf5: /* cmc */
4572 /* complement carry flag from eflags reg */
4573 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4574 break;
4575 case 0xf8: /* clc */
4576 ctxt->eflags &= ~EFLG_CF;
111de5d6 4577 break;
8744aa9a
MG		 4578 case 0xf9: /* stc */
4579 ctxt->eflags |= EFLG_CF;
4580 break;
fb4616f4
MG		 4581 case 0xfc: /* cld */
4582 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4583 break;
4584 case 0xfd: /* std */
4585 ctxt->eflags |= EFLG_DF;
fb4616f4 4586 break;
91269b8f
AK		 4587 default:
4588 goto cannot_emulate;
6aa8b732 4589 }
018a98db 4590
7d9ddaed
AK		 4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593
018a98db 4594writeback:
fb32b1ed
AK		 4595 if (!(ctxt->d & NoWrite)) {
4596 rc = writeback(ctxt, &ctxt->dst);
4597 if (rc != X86EMUL_CONTINUE)
4598 goto done;
4599 }
4600 if (ctxt->d & SrcWrite) {
4601 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4602 rc = writeback(ctxt, &ctxt->src);
4603 if (rc != X86EMUL_CONTINUE)
4604 goto done;
4605 }
018a98db 4606
5cd21917
GN		 4607 /*
4608 * restore dst type in case the decoding will be reused
4609 * (happens for string instruction )
4610 */
9dac77fa 4611 ctxt->dst.type = saved_dst_type;
5cd21917 4612
9dac77fa 4613 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4614 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4615
9dac77fa 4616 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4617 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4618
9dac77fa 4619 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4620 unsigned int count;
9dac77fa 4621 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4622 if ((ctxt->d & SrcMask) == SrcSI)
4623 count = ctxt->src.count;
4624 else
4625 count = ctxt->dst.count;
4626 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4627 -count);
3e2f65d5 4628
d2ddd1c4
GN		 4629 if (!string_insn_completed(ctxt)) {
4630 /*
4631 * Re-enter guest when pio read ahead buffer is empty
4632 * or, if it is not used, after each 1024 iteration.
4633 */
dd856efa 4634 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4635 (r->end == 0 || r->end != r->pos)) {
4636 /*
4637 * Reset read cache. Usually happens before
4638 * decode, but since instruction is restarted
4639 * we have to do it here.
4640 */
9dac77fa 4641 ctxt->mem_read.end = 0;
dd856efa 4642 writeback_registers(ctxt);
d2ddd1c4
GN		 4643 return EMULATION_RESTART;
4644 }
4645 goto done; /* skip rip writeback */
0fa6ccbd 4646 }
5cd21917 4647 }
d2ddd1c4 4648
9dac77fa 4649 ctxt->eip = ctxt->_eip;
018a98db
AK		 4650
4651done:
da9cb575
AK		 4652 if (rc == X86EMUL_PROPAGATE_FAULT)
4653 ctxt->have_exception = true;
775fde86
JR		 4654 if (rc == X86EMUL_INTERCEPTED)
4655 return EMULATION_INTERCEPTED;
4656
dd856efa
AK		 4657 if (rc == X86EMUL_CONTINUE)
4658 writeback_registers(ctxt);
4659
d2ddd1c4 4660 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4661
4662twobyte_insn:
9dac77fa 4663 switch (ctxt->b) {
018a98db 4664 case 0x09: /* wbinvd */
cfb22375 4665 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4666 break;
4667 case 0x08: /* invd */
018a98db
AK		 4668 case 0x0d: /* GrpP (prefetch) */
4669 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4670 break;
4671 case 0x20: /* mov cr, reg */
9dac77fa 4672 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4673 break;
6aa8b732 4674 case 0x21: /* mov from dr to reg */
9dac77fa 4675 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4676 break;
6aa8b732 4677 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4678 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4679 if (!test_cc(ctxt->b, ctxt->eflags))
4680 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4681 break;
b2833e3c 4682 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4683 if (test_cc(ctxt->b, ctxt->eflags))
4684 jmp_rel(ctxt, ctxt->src.val);
018a98db 4685 break;
ee45b58e 4686 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4687 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4688 break;
2a7c5b8b
GC		 4689 case 0xae: /* clflush */
4690 break;
6aa8b732 4691 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4692 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4693 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4694 : (u16) ctxt->src.val;
6aa8b732 4695 break;
6aa8b732 4696 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4697 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4698 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4699 (s16) ctxt->src.val;
6aa8b732 4700 break;
92f738a5 4701 case 0xc0 ... 0xc1: /* xadd */
158de57f 4702 fastop(ctxt, em_add);
92f738a5 4703 /* Write back the register source. */
9dac77fa
AK		 4704 ctxt->src.val = ctxt->dst.orig_val;
4705 write_register_operand(&ctxt->src);
92f738a5 4706 break;
a012e65a 4707 case 0xc3: /* movnti */
9dac77fa
AK		 4708 ctxt->dst.bytes = ctxt->op_bytes;
4709 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4710 (u64) ctxt->src.val;
a012e65a 4711 break;
91269b8f
AK		 4712 default:
4713 goto cannot_emulate;
6aa8b732 4714 }
7d9ddaed
AK		 4715
4716 if (rc != X86EMUL_CONTINUE)
4717 goto done;
4718
6aa8b732
AK		 4719 goto writeback;
4720
4721cannot_emulate:
a0c0ab2f 4722 return EMULATION_FAILED;
6aa8b732 4723}
dd856efa
AK		 4724
4725void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4726{
4727 invalidate_registers(ctxt);
4728}
4729
4730void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4731{
4732 writeback_registers(ctxt);
4733}
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