]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/emulate.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: emulate FXSAVE and FXRSTOR
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
56e82318 25#include <asm/kvm_emulate.h>
b7d491e7 26#include <linux/stringify.h>
3db176d5 27#include <asm/debugreg.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 128#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 129#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 130/* Generic ModRM decode. */
131#define ModRM (1<<19)
132/* Destination is only written; never read. */
133#define Mov (1<<20)
d8769fed 134/* Misc flags */
8ea7d6ae 135#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 136#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 137#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 138#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 139#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 140#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 141#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 142#define No64 (1<<28)
d5ae7ce8 143#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 144#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 145/* Source 2 operand type */
0b789eee 146#define Src2Shift (31)
4dd6a57d 147#define Src2None (OpNone << Src2Shift)
ab2c5ce6 148#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 149#define Src2CL (OpCL << Src2Shift)
150#define Src2ImmByte (OpImmByte << Src2Shift)
151#define Src2One (OpOne << Src2Shift)
152#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 153#define Src2ES (OpES << Src2Shift)
154#define Src2CS (OpCS << Src2Shift)
155#define Src2SS (OpSS << Src2Shift)
156#define Src2DS (OpDS << Src2Shift)
157#define Src2FS (OpFS << Src2Shift)
158#define Src2GS (OpGS << Src2Shift)
4dd6a57d 159#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 160#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 161#define AlignMask ((u64)7 << 41)
1c11b376 162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 163#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
165#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 166#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 167#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 168#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 169#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 170#define Intercept ((u64)1 << 48) /* Has valid intercept field */
171#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 172#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 173#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 174#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 175#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 176
820207c8 177#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 178
d0e53325
AK		 179#define X2(x...) x, x
180#define X3(x...) X2(x), x
181#define X4(x...) X2(x), X2(x)
182#define X5(x...) X4(x), x
183#define X6(x...) X4(x), X2(x)
184#define X7(x...) X4(x), X3(x)
185#define X8(x...) X4(x), X4(x)
186#define X16(x...) X8(x), X8(x)
83babbca 187
e28bbd44
AK		 188#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
189#define FASTOP_SIZE 8
190
191/*
192 * fastop functions have a special calling convention:
193 *
017da7b6
AK		 194 * dst: rax (in/out)
195 * src: rdx (in/out)
e28bbd44
AK		 196 * src2: rcx (in)
197 * flags: rflags (in/out)
b8c0b6ae 198 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 199 *
200 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
201 * different operand sizes can be reached by calculation, rather than a jump
202 * table (which would be bigger than the code).
203 *
204 * fastop functions are declared as taking a never-defined fastop parameter,
205 * so they can't be called from C directly.
206 */
207
208struct fastop;
209
d65b1dee 210struct opcode {
b1ea50b2
AK		 211 u64 flags : 56;
212 u64 intercept : 8;
120df890 213 union {
ef65c889 214 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 215 const struct opcode *group;
216 const struct group_dual *gdual;
217 const struct gprefix *gprefix;
045a282c 218 const struct escape *esc;
39f062ff 219 const struct instr_dual *idual;
2276b511 220 const struct mode_dual *mdual;
e28bbd44 221 void (*fastop)(struct fastop *fake);
120df890 222 } u;
d09beabd 223 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 224};
225
226struct group_dual {
227 struct opcode mod012[8];
228 struct opcode mod3[8];
d65b1dee
AK		 229};
230
0d7cdee8
AK		 231struct gprefix {
232 struct opcode pfx_no;
233 struct opcode pfx_66;
234 struct opcode pfx_f2;
235 struct opcode pfx_f3;
236};
237
045a282c
GN		 238struct escape {
239 struct opcode op[8];
240 struct opcode high[64];
241};
242
39f062ff
NA		 243struct instr_dual {
244 struct opcode mod012;
245 struct opcode mod3;
246};
247
2276b511
NA		 248struct mode_dual {
249 struct opcode mode32;
250 struct opcode mode64;
251};
252
62bd430e 253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 254
3dc4bc4f
NA		 255enum x86_transfer_type {
256 X86_TRANSFER_NONE,
257 X86_TRANSFER_CALL_JMP,
258 X86_TRANSFER_RET,
259 X86_TRANSFER_TASK_SWITCH,
260};
261
dd856efa
AK		 262static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
263{
264 if (!(ctxt->regs_valid & (1 << nr))) {
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
267 }
268 return ctxt->_regs[nr];
269}
270
271static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
272{
273 ctxt->regs_valid |= 1 << nr;
274 ctxt->regs_dirty |= 1 << nr;
275 return &ctxt->_regs[nr];
276}
277
278static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
279{
280 reg_read(ctxt, nr);
281 return reg_write(ctxt, nr);
282}
283
284static void writeback_registers(struct x86_emulate_ctxt *ctxt)
285{
286 unsigned reg;
287
288 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
289 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
290}
291
292static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
293{
294 ctxt->regs_dirty = 0;
295 ctxt->regs_valid = 0;
296}
297
6aa8b732
AK		 298/*
299 * These EFLAGS bits are restored from saved value during emulation, and
300 * any changes are written back to the saved value after emulation.
301 */
0efb0440
NA		 302#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
303 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 304
dda96d8f
AK		 305#ifdef CONFIG_X86_64
306#define ON64(x) x
307#else
308#define ON64(x)
309#endif
310
4d758349
AK		 311static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
312
1482a082
JP		 313#define FOP_FUNC(name) \
314 ".align " __stringify(FASTOP_SIZE) " \n\t" \
315 ".type " name ", @function \n\t" \
316 name ":\n\t"
317
b7d491e7
AK		 318#define FOP_RET "ret \n\t"
319
320#define FOP_START(op) \
321 extern void em_##op(struct fastop *fake); \
322 asm(".pushsection .text, \"ax\" \n\t" \
323 ".global em_" #op " \n\t" \
1482a082 324 FOP_FUNC("em_" #op)
b7d491e7
AK		 325
326#define FOP_END \
327 ".popsection")
328
1482a082
JP		 329#define FOPNOP() \
330 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
331 FOP_RET
0bdea068 332
b7d491e7 333#define FOP1E(op, dst) \
1482a082
JP		 334 FOP_FUNC(#op "_" #dst) \
335 "10: " #op " %" #dst " \n\t" FOP_RET
b8c0b6ae
AK		 336
337#define FOP1EEX(op, dst) \
338 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 339
340#define FASTOP1(op) \
341 FOP_START(op) \
342 FOP1E(op##b, al) \
343 FOP1E(op##w, ax) \
344 FOP1E(op##l, eax) \
345 ON64(FOP1E(op##q, rax)) \
346 FOP_END
347
b9fa409b
AK		 348/* 1-operand, using src2 (for MUL/DIV r/m) */
349#define FASTOP1SRC2(op, name) \
350 FOP_START(name) \
351 FOP1E(op, cl) \
352 FOP1E(op, cx) \
353 FOP1E(op, ecx) \
354 ON64(FOP1E(op, rcx)) \
355 FOP_END
356
b8c0b6ae
AK		 357/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
358#define FASTOP1SRC2EX(op, name) \
359 FOP_START(name) \
360 FOP1EEX(op, cl) \
361 FOP1EEX(op, cx) \
362 FOP1EEX(op, ecx) \
363 ON64(FOP1EEX(op, rcx)) \
364 FOP_END
365
f7857f35 366#define FOP2E(op, dst, src) \
1482a082
JP		 367 FOP_FUNC(#op "_" #dst "_" #src) \
368 #op " %" #src ", %" #dst " \n\t" FOP_RET
f7857f35
AK		 369
370#define FASTOP2(op) \
371 FOP_START(op) \
017da7b6
AK		 372 FOP2E(op##b, al, dl) \
373 FOP2E(op##w, ax, dx) \
374 FOP2E(op##l, eax, edx) \
375 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 376 FOP_END
377
11c363ba
AK		 378/* 2 operand, word only */
379#define FASTOP2W(op) \
380 FOP_START(op) \
381 FOPNOP() \
017da7b6
AK		 382 FOP2E(op##w, ax, dx) \
383 FOP2E(op##l, eax, edx) \
384 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 385 FOP_END
386
007a3b54
AK		 387/* 2 operand, src is CL */
388#define FASTOP2CL(op) \
389 FOP_START(op) \
390 FOP2E(op##b, al, cl) \
391 FOP2E(op##w, ax, cl) \
392 FOP2E(op##l, eax, cl) \
393 ON64(FOP2E(op##q, rax, cl)) \
394 FOP_END
395
5aca3722
NA		 396/* 2 operand, src and dest are reversed */
397#define FASTOP2R(op, name) \
398 FOP_START(name) \
399 FOP2E(op##b, dl, al) \
400 FOP2E(op##w, dx, ax) \
401 FOP2E(op##l, edx, eax) \
402 ON64(FOP2E(op##q, rdx, rax)) \
403 FOP_END
404
0bdea068 405#define FOP3E(op, dst, src, src2) \
1482a082
JP		 406 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
407 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
0bdea068
AK		 408
409/* 3-operand, word-only, src2=cl */
410#define FASTOP3WCL(op) \
411 FOP_START(op) \
412 FOPNOP() \
017da7b6
AK		 413 FOP3E(op##w, ax, dx, cl) \
414 FOP3E(op##l, eax, edx, cl) \
415 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 416 FOP_END
417
9ae9feba 418/* Special case for SETcc - 1 instruction per cc */
1482a082
JP		 419#define FOP_SETCC(op) \
420 ".align 4 \n\t" \
421 ".type " #op ", @function \n\t" \
422 #op ": \n\t" \
423 #op " %al \n\t" \
424 FOP_RET
9ae9feba 425
b8c0b6ae
AK		 426asm(".global kvm_fastop_exception \n"
427 "kvm_fastop_exception: xor %esi, %esi; ret");
428
9ae9feba
AK		 429FOP_START(setcc)
430FOP_SETCC(seto)
431FOP_SETCC(setno)
432FOP_SETCC(setc)
433FOP_SETCC(setnc)
434FOP_SETCC(setz)
435FOP_SETCC(setnz)
436FOP_SETCC(setbe)
437FOP_SETCC(setnbe)
438FOP_SETCC(sets)
439FOP_SETCC(setns)
440FOP_SETCC(setp)
441FOP_SETCC(setnp)
442FOP_SETCC(setl)
443FOP_SETCC(setnl)
444FOP_SETCC(setle)
445FOP_SETCC(setnle)
446FOP_END;
447
326f578f
PB		 448FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
449FOP_END;
450
aabba3c6
RK		 451/*
452 * XXX: inoutclob user must know where the argument is being expanded.
453 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
454 */
455#define asm_safe(insn, inoutclob...) \
456({ \
457 int _fault = 0; \
458 \
459 asm volatile("1:" insn "\n" \
460 "2:\n" \
461 ".pushsection .fixup, \"ax\"\n" \
462 "3: movl $1, %[_fault]\n" \
463 " jmp 2b\n" \
464 ".popsection\n" \
465 _ASM_EXTABLE(1b, 3b) \
466 : [_fault] "+qm"(_fault) inoutclob ); \
467 \
468 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
469})
470
8a76d7f2
JR		 471static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
472 enum x86_intercept intercept,
473 enum x86_intercept_stage stage)
474{
475 struct x86_instruction_info info = {
476 .intercept = intercept,
9dac77fa
AK		 477 .rep_prefix = ctxt->rep_prefix,
478 .modrm_mod = ctxt->modrm_mod,
479 .modrm_reg = ctxt->modrm_reg,
480 .modrm_rm = ctxt->modrm_rm,
481 .src_val = ctxt->src.val64,
6cbc5f5a 482 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 483 .src_bytes = ctxt->src.bytes,
484 .dst_bytes = ctxt->dst.bytes,
485 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 486 .next_rip = ctxt->eip,
487 };
488
2953538e 489 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 490}
491
f47cfa31
AK		 492static void assign_masked(ulong *dest, ulong src, ulong mask)
493{
494 *dest = (*dest & ~mask) | (src & mask);
495}
496
6fd8e127
NA		 497static void assign_register(unsigned long *reg, u64 val, int bytes)
498{
499 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
500 switch (bytes) {
501 case 1:
502 *(u8 *)reg = (u8)val;
503 break;
504 case 2:
505 *(u16 *)reg = (u16)val;
506 break;
507 case 4:
508 *reg = (u32)val;
509 break; /* 64b: zero-extend */
510 case 8:
511 *reg = val;
512 break;
513 }
514}
515
9dac77fa 516static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 517{
9dac77fa 518 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 519}
520
f47cfa31
AK		 521static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
522{
523 u16 sel;
524 struct desc_struct ss;
525
526 if (ctxt->mode == X86EMUL_MODE_PROT64)
527 return ~0UL;
528 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
529 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
530}
531
612e89f0
AK		 532static int stack_size(struct x86_emulate_ctxt *ctxt)
533{
534 return (__fls(stack_mask(ctxt)) + 1) >> 3;
535}
536
6aa8b732 537/* Access/update address held in a register, based on addressing mode. */
e4706772 538static inline unsigned long
9dac77fa 539address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 540{
9dac77fa 541 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 542 return reg;
543 else
9dac77fa 544 return reg & ad_mask(ctxt);
e4706772
HH		 545}
546
547static inline unsigned long
01485a22 548register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 549{
01485a22 550 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 551}
552
5ad105e5
AK		 553static void masked_increment(ulong *reg, ulong mask, int inc)
554{
555 assign_masked(reg, *reg + inc, mask);
556}
557
7a957275 558static inline void
01485a22 559register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 560{
ee122a71 561 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 562
ee122a71 563 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 564}
565
566static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
567{
dd856efa 568 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 569}
6aa8b732 570
56697687
AK		 571static u32 desc_limit_scaled(struct desc_struct *desc)
572{
573 u32 limit = get_desc_limit(desc);
574
575 return desc->g ? (limit << 12) | 0xfff : limit;
576}
577
7b105ca2 578static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 579{
580 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
581 return 0;
582
7b105ca2 583 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 584}
585
35d3d4a1
AK		 586static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
587 u32 error, bool valid)
54b8486f 588{
e0ad0b47 589 WARN_ON(vec > 0x1f);
da9cb575
AK		 590 ctxt->exception.vector = vec;
591 ctxt->exception.error_code = error;
592 ctxt->exception.error_code_valid = valid;
35d3d4a1 593 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 594}
595
3b88e41a
JR		 596static int emulate_db(struct x86_emulate_ctxt *ctxt)
597{
598 return emulate_exception(ctxt, DB_VECTOR, 0, false);
599}
600
35d3d4a1 601static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 602{
35d3d4a1 603 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 604}
605
618ff15d
AK		 606static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
607{
608 return emulate_exception(ctxt, SS_VECTOR, err, true);
609}
610
35d3d4a1 611static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 612{
35d3d4a1 613 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 614}
615
35d3d4a1 616static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 617{
35d3d4a1 618 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 619}
620
34d1f490
AK		 621static int emulate_de(struct x86_emulate_ctxt *ctxt)
622{
35d3d4a1 623 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 624}
625
1253791d
AK		 626static int emulate_nm(struct x86_emulate_ctxt *ctxt)
627{
628 return emulate_exception(ctxt, NM_VECTOR, 0, false);
629}
630
1aa36616
AK		 631static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
632{
633 u16 selector;
634 struct desc_struct desc;
635
636 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
637 return selector;
638}
639
640static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
641 unsigned seg)
642{
643 u16 dummy;
644 u32 base3;
645 struct desc_struct desc;
646
647 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
648 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
649}
650
1c11b376
AK		 651/*
652 * x86 defines three classes of vector instructions: explicitly
653 * aligned, explicitly unaligned, and the rest, which change behaviour
654 * depending on whether they're AVX encoded or not.
655 *
656 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 657 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
658 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 659 */
d3fe959f 660static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 661{
48520187
RK		 662 u64 alignment = ctxt->d & AlignMask;
663
1c11b376 664 if (likely(size < 16))
d3fe959f 665 return 1;
1c11b376 666
48520187
RK		 667 switch (alignment) {
668 case Unaligned:
669 case Avx:
d3fe959f 670 return 1;
48520187 671 case Aligned16:
d3fe959f 672 return 16;
48520187
RK		 673 case Aligned:
674 default:
d3fe959f 675 return size;
48520187 676 }
1c11b376
AK		 677}
678
d09155d2
PB		 679static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
680 struct segmented_address addr,
681 unsigned *max_size, unsigned size,
682 bool write, bool fetch,
d50eaa18 683 enum x86emul_mode mode, ulong *linear)
52fd8b44 684{
618ff15d
AK		 685 struct desc_struct desc;
686 bool usable;
52fd8b44 687 ulong la;
618ff15d 688 u32 lim;
1aa36616 689 u16 sel;
52fd8b44 690
7b105ca2 691 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 692 *max_size = 0;
d50eaa18 693 switch (mode) {
618ff15d 694 case X86EMUL_MODE_PROT64:
0c1d77f4 695 *linear = la;
4be4de7e 696 if (is_noncanonical_address(la))
abc7d8a4 697 goto bad;
fd56e154
PB		 698
699 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
700 if (size > *max_size)
701 goto bad;
618ff15d
AK		 702 break;
703 default:
0c1d77f4 704 *linear = la = (u32)la;
1aa36616
AK		 705 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
706 addr.seg);
618ff15d
AK		 707 if (!usable)
708 goto bad;
58b7825b
GN		 709 /* code segment in protected mode or read-only data segment */
710 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
711 || !(desc.type & 2)) && write)
618ff15d
AK		 712 goto bad;
713 /* unreadable code segment */
3d9b938e 714 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 715 goto bad;
716 lim = desc_limit_scaled(&desc);
997b0412 717 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 718 /* expand-down segment */
fd56e154 719 if (addr.ea <= lim)
618ff15d
AK		 720 goto bad;
721 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 722 }
997b0412
PB		 723 if (addr.ea > lim)
724 goto bad;
bac15531
NA		 725 if (lim == 0xffffffff)
726 *max_size = ~0u;
727 else {
728 *max_size = (u64)lim + 1 - addr.ea;
729 if (size > *max_size)
730 goto bad;
731 }
618ff15d
AK		 732 break;
733 }
d3fe959f 734 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 735 return emulate_gp(ctxt, 0);
52fd8b44 736 return X86EMUL_CONTINUE;
618ff15d
AK		 737bad:
738 if (addr.seg == VCPU_SREG_SS)
3606189f 739 return emulate_ss(ctxt, 0);
618ff15d 740 else
3606189f 741 return emulate_gp(ctxt, 0);
52fd8b44
AK		 742}
743
3d9b938e
NE		 744static int linearize(struct x86_emulate_ctxt *ctxt,
745 struct segmented_address addr,
746 unsigned size, bool write,
747 ulong *linear)
748{
fd56e154 749 unsigned max_size;
d50eaa18
NA		 750 return __linearize(ctxt, addr, &max_size, size, write, false,
751 ctxt->mode, linear);
3d9b938e
NE		 752}
753
d50eaa18
NA		 754static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
755 enum x86emul_mode mode)
756{
757 ulong linear;
758 int rc;
759 unsigned max_size;
760 struct segmented_address addr = { .seg = VCPU_SREG_CS,
761 .ea = dst };
762
763 if (ctxt->op_bytes != sizeof(unsigned long))
764 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
765 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
766 if (rc == X86EMUL_CONTINUE)
767 ctxt->_eip = addr.ea;
768 return rc;
769}
770
771static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
772{
773 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 774}
775
d50eaa18
NA		 776static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
777 const struct desc_struct *cs_desc)
778{
779 enum x86emul_mode mode = ctxt->mode;
82268083 780 int rc;
d50eaa18
NA		 781
782#ifdef CONFIG_X86_64
82268083
NA		 783 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
784 if (cs_desc->l) {
785 u64 efer = 0;
d50eaa18 786
82268083
NA		 787 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
788 if (efer & EFER_LMA)
789 mode = X86EMUL_MODE_PROT64;
790 } else
791 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 792 }
793#endif
794 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
795 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 796 rc = assign_eip(ctxt, dst, mode);
797 if (rc == X86EMUL_CONTINUE)
798 ctxt->mode = mode;
799 return rc;
d50eaa18
NA		 800}
801
802static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
803{
804 return assign_eip_near(ctxt, ctxt->_eip + rel);
805}
3d9b938e 806
3ca3ac4d
AK		 807static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
808 struct segmented_address addr,
809 void *data,
810 unsigned size)
811{
9fa088f4
AK		 812 int rc;
813 ulong linear;
814
83b8795a 815 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 816 if (rc != X86EMUL_CONTINUE)
817 return rc;
0f65dd70 818 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 819}
820
807941b1 821/*
285ca9e9 822 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 823 * boundary if they are not in fetch_cache yet.
824 */
9506d57d 825static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 826{
62266869 827 int rc;
fd56e154 828 unsigned size, max_size;
285ca9e9 829 unsigned long linear;
17052f16 830 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 831 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 832 .ea = ctxt->eip + cur_size };
833
fd56e154
PB		 834 /*
835 * We do not know exactly how many bytes will be needed, and
836 * __linearize is expensive, so fetch as much as possible. We
837 * just have to avoid going beyond the 15 byte limit, the end
838 * of the segment, or the end of the page.
839 *
840 * __linearize is called with size 0 so that it does not do any
841 * boundary check itself. Instead, we use max_size to check
842 * against op_size.
843 */
d50eaa18
NA		 844 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
845 &linear);
719d5a9b
PB		 846 if (unlikely(rc != X86EMUL_CONTINUE))
847 return rc;
848
fd56e154 849 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 850 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 851
852 /*
853 * One instruction can only straddle two pages,
854 * and one has been loaded at the beginning of
855 * x86_decode_insn. So, if not enough bytes
856 * still, we must have hit the 15-byte boundary.
857 */
858 if (unlikely(size < op_size))
fd56e154
PB		 859 return emulate_gp(ctxt, 0);
860
17052f16 861 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 862 size, &ctxt->exception);
863 if (unlikely(rc != X86EMUL_CONTINUE))
864 return rc;
17052f16 865 ctxt->fetch.end += size;
3e2815e9 866 return X86EMUL_CONTINUE;
62266869
AK		 867}
868
9506d57d
PB		 869static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
870 unsigned size)
62266869 871{
08da44ae
NA		 872 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
873
874 if (unlikely(done_size < size))
875 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 876 else
877 return X86EMUL_CONTINUE;
62266869
AK		 878}
879
67cbc90d 880/* Fetch next part of the instruction being emulated. */
e85a1085 881#define insn_fetch(_type, _ctxt) \
9506d57d 882({ _type _x; \
9506d57d
PB		 883 \
884 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 885 if (rc != X86EMUL_CONTINUE) \
886 goto done; \
9506d57d 887 ctxt->_eip += sizeof(_type); \
17052f16
PB		 888 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
889 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 890 _x; \
67cbc90d
TY		 891})
892
807941b1 893#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 894({ \
9506d57d 895 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 896 if (rc != X86EMUL_CONTINUE) \
897 goto done; \
9506d57d 898 ctxt->_eip += (_size); \
17052f16
PB		 899 memcpy(_arr, ctxt->fetch.ptr, _size); \
900 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 901})
902
1e3c5cb0
RR		 903/*
904 * Given the 'reg' portion of a ModRM byte, and a register block, return a
905 * pointer into the block that addresses the relevant register.
906 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
907 */
dd856efa 908static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 909 int byteop)
6aa8b732
AK		 910{
911 void *p;
aa9ac1a6 912 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 913
6aa8b732 914 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 915 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
916 else
917 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 918 return p;
919}
920
921static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 922 struct segmented_address addr,
6aa8b732
AK		 923 u16 *size, unsigned long *address, int op_bytes)
924{
925 int rc;
926
927 if (op_bytes == 2)
928 op_bytes = 3;
929 *address = 0;
3ca3ac4d 930 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 931 if (rc != X86EMUL_CONTINUE)
6aa8b732 932 return rc;
30b31ab6 933 addr.ea += 2;
3ca3ac4d 934 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 935 return rc;
936}
937
34b77652
AK		 938FASTOP2(add);
939FASTOP2(or);
940FASTOP2(adc);
941FASTOP2(sbb);
942FASTOP2(and);
943FASTOP2(sub);
944FASTOP2(xor);
945FASTOP2(cmp);
946FASTOP2(test);
947
b9fa409b
AK		 948FASTOP1SRC2(mul, mul_ex);
949FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 950FASTOP1SRC2EX(div, div_ex);
951FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 952
34b77652
AK		 953FASTOP3WCL(shld);
954FASTOP3WCL(shrd);
955
956FASTOP2W(imul);
957
958FASTOP1(not);
959FASTOP1(neg);
960FASTOP1(inc);
961FASTOP1(dec);
962
963FASTOP2CL(rol);
964FASTOP2CL(ror);
965FASTOP2CL(rcl);
966FASTOP2CL(rcr);
967FASTOP2CL(shl);
968FASTOP2CL(shr);
969FASTOP2CL(sar);
970
971FASTOP2W(bsf);
972FASTOP2W(bsr);
973FASTOP2W(bt);
974FASTOP2W(bts);
975FASTOP2W(btr);
976FASTOP2W(btc);
977
e47a5f5f
AK		 978FASTOP2(xadd);
979
5aca3722
NA		 980FASTOP2R(cmp, cmp_r);
981
900efe20
NA		 982static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
983{
984 /* If src is zero, do not writeback, but update flags */
985 if (ctxt->src.val == 0)
986 ctxt->dst.type = OP_NONE;
987 return fastop(ctxt, em_bsf);
988}
989
990static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
991{
992 /* If src is zero, do not writeback, but update flags */
993 if (ctxt->src.val == 0)
994 ctxt->dst.type = OP_NONE;
995 return fastop(ctxt, em_bsr);
996}
997
cb7390fe 998static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 999{
9ae9feba
AK		 1000 u8 rc;
1001 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1002
9ae9feba 1003 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1004 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1005 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1006 return rc;
bbe9abbd
NK		 1007}
1008
91ff3cb4
AK		 1009static void fetch_register_operand(struct operand *op)
1010{
1011 switch (op->bytes) {
1012 case 1:
1013 op->val = *(u8 *)op->addr.reg;
1014 break;
1015 case 2:
1016 op->val = *(u16 *)op->addr.reg;
1017 break;
1018 case 4:
1019 op->val = *(u32 *)op->addr.reg;
1020 break;
1021 case 8:
1022 op->val = *(u64 *)op->addr.reg;
1023 break;
1024 }
1025}
1026
1253791d
AK		 1027static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1028{
1029 ctxt->ops->get_fpu(ctxt);
1030 switch (reg) {
89a87c67
MK		 1031 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1032 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1033 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1034 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1035 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1036 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1037 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1038 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1039#ifdef CONFIG_X86_64
89a87c67
MK		 1040 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1041 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1042 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1043 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1044 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1045 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1046 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1047 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1048#endif
1049 default: BUG();
1050 }
1051 ctxt->ops->put_fpu(ctxt);
1052}
1053
1054static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1055 int reg)
1056{
1057 ctxt->ops->get_fpu(ctxt);
1058 switch (reg) {
89a87c67
MK		 1059 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1060 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1061 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1062 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1063 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1064 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1065 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1066 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1067#ifdef CONFIG_X86_64
89a87c67
MK		 1068 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1069 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1070 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1071 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1072 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1073 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1074 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1075 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1076#endif
1077 default: BUG();
1078 }
1079 ctxt->ops->put_fpu(ctxt);
1080}
1081
cbe2c9d3
AK		 1082static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1083{
1084 ctxt->ops->get_fpu(ctxt);
1085 switch (reg) {
1086 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1087 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1088 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1089 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1090 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1091 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1092 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1093 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1094 default: BUG();
1095 }
1096 ctxt->ops->put_fpu(ctxt);
1097}
1098
1099static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1100{
1101 ctxt->ops->get_fpu(ctxt);
1102 switch (reg) {
1103 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1104 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1105 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1106 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1107 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1108 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1109 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1110 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1111 default: BUG();
1112 }
1113 ctxt->ops->put_fpu(ctxt);
1114}
1115
045a282c
GN		 1116static int em_fninit(struct x86_emulate_ctxt *ctxt)
1117{
1118 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1119 return emulate_nm(ctxt);
1120
1121 ctxt->ops->get_fpu(ctxt);
1122 asm volatile("fninit");
1123 ctxt->ops->put_fpu(ctxt);
1124 return X86EMUL_CONTINUE;
1125}
1126
1127static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1128{
1129 u16 fcw;
1130
1131 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1132 return emulate_nm(ctxt);
1133
1134 ctxt->ops->get_fpu(ctxt);
1135 asm volatile("fnstcw %0": "+m"(fcw));
1136 ctxt->ops->put_fpu(ctxt);
1137
045a282c
GN		 1138 ctxt->dst.val = fcw;
1139
1140 return X86EMUL_CONTINUE;
1141}
1142
1143static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1144{
1145 u16 fsw;
1146
1147 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1148 return emulate_nm(ctxt);
1149
1150 ctxt->ops->get_fpu(ctxt);
1151 asm volatile("fnstsw %0": "+m"(fsw));
1152 ctxt->ops->put_fpu(ctxt);
1153
045a282c
GN		 1154 ctxt->dst.val = fsw;
1155
1156 return X86EMUL_CONTINUE;
1157}
1158
1253791d 1159static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1160 struct operand *op)
3c118e24 1161{
9dac77fa 1162 unsigned reg = ctxt->modrm_reg;
33615aa9 1163
9dac77fa
AK		 1164 if (!(ctxt->d & ModRM))
1165 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1166
9dac77fa 1167 if (ctxt->d & Sse) {
1253791d
AK		 1168 op->type = OP_XMM;
1169 op->bytes = 16;
1170 op->addr.xmm = reg;
1171 read_sse_reg(ctxt, &op->vec_val, reg);
1172 return;
1173 }
cbe2c9d3
AK		 1174 if (ctxt->d & Mmx) {
1175 reg &= 7;
1176 op->type = OP_MM;
1177 op->bytes = 8;
1178 op->addr.mm = reg;
1179 return;
1180 }
1253791d 1181
3c118e24 1182 op->type = OP_REG;
6d4d85ec
GN		 1183 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1184 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1185
91ff3cb4 1186 fetch_register_operand(op);
3c118e24
AK		 1187 op->orig_val = op->val;
1188}
1189
a6e3407b
AK		 1190static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1191{
1192 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1193 ctxt->modrm_seg = VCPU_SREG_SS;
1194}
1195
1c73ef66 1196static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1197 struct operand *op)
1c73ef66 1198{
1c73ef66 1199 u8 sib;
02357bdc 1200 int index_reg, base_reg, scale;
3e2815e9 1201 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1202 ulong modrm_ea = 0;
1c73ef66 1203
02357bdc
BD		 1204 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1205 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1206 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1207
02357bdc 1208 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1209 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1210 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1211 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1212
9b88ae99 1213 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1214 op->type = OP_REG;
9dac77fa 1215 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1216 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1217 ctxt->d & ByteOp);
9dac77fa 1218 if (ctxt->d & Sse) {
1253791d
AK		 1219 op->type = OP_XMM;
1220 op->bytes = 16;
9dac77fa
AK		 1221 op->addr.xmm = ctxt->modrm_rm;
1222 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1223 return rc;
1224 }
cbe2c9d3
AK		 1225 if (ctxt->d & Mmx) {
1226 op->type = OP_MM;
1227 op->bytes = 8;
bdc90722 1228 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1229 return rc;
1230 }
2dbd0dd7 1231 fetch_register_operand(op);
1c73ef66
AK		 1232 return rc;
1233 }
1234
2dbd0dd7
AK		 1235 op->type = OP_MEM;
1236
9dac77fa 1237 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1238 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1239 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1240 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1241 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1242
1243 /* 16-bit ModR/M decode. */
9dac77fa 1244 switch (ctxt->modrm_mod) {
1c73ef66 1245 case 0:
9dac77fa 1246 if (ctxt->modrm_rm == 6)
e85a1085 1247 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1248 break;
1249 case 1:
e85a1085 1250 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1251 break;
1252 case 2:
e85a1085 1253 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1254 break;
1255 }
9dac77fa 1256 switch (ctxt->modrm_rm) {
1c73ef66 1257 case 0:
2dbd0dd7 1258 modrm_ea += bx + si;
1c73ef66
AK		 1259 break;
1260 case 1:
2dbd0dd7 1261 modrm_ea += bx + di;
1c73ef66
AK		 1262 break;
1263 case 2:
2dbd0dd7 1264 modrm_ea += bp + si;
1c73ef66
AK		 1265 break;
1266 case 3:
2dbd0dd7 1267 modrm_ea += bp + di;
1c73ef66
AK		 1268 break;
1269 case 4:
2dbd0dd7 1270 modrm_ea += si;
1c73ef66
AK		 1271 break;
1272 case 5:
2dbd0dd7 1273 modrm_ea += di;
1c73ef66
AK		 1274 break;
1275 case 6:
9dac77fa 1276 if (ctxt->modrm_mod != 0)
2dbd0dd7 1277 modrm_ea += bp;
1c73ef66
AK		 1278 break;
1279 case 7:
2dbd0dd7 1280 modrm_ea += bx;
1c73ef66
AK		 1281 break;
1282 }
9dac77fa
AK		 1283 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1284 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1285 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1286 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1287 } else {
1288 /* 32/64-bit ModR/M decode. */
9dac77fa 1289 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1290 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1291 index_reg |= (sib >> 3) & 7;
1292 base_reg |= sib & 7;
1293 scale = sib >> 6;
1294
9dac77fa 1295 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1296 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1297 else {
dd856efa 1298 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1299 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1300 /* Increment ESP on POP [ESP] */
1301 if ((ctxt->d & IncSP) &&
1302 base_reg == VCPU_REGS_RSP)
1303 modrm_ea += ctxt->op_bytes;
a6e3407b 1304 }
dc71d0f1 1305 if (index_reg != 4)
dd856efa 1306 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1307 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1308 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1309 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1310 ctxt->rip_relative = 1;
a6e3407b
AK		 1311 } else {
1312 base_reg = ctxt->modrm_rm;
dd856efa 1313 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1314 adjust_modrm_seg(ctxt, base_reg);
1315 }
9dac77fa 1316 switch (ctxt->modrm_mod) {
1c73ef66 1317 case 1:
e85a1085 1318 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1319 break;
1320 case 2:
e85a1085 1321 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1322 break;
1323 }
1324 }
90de84f5 1325 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1326 if (ctxt->ad_bytes != 8)
1327 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1328
1c73ef66
AK		 1329done:
1330 return rc;
1331}
1332
1333static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1334 struct operand *op)
1c73ef66 1335{
3e2815e9 1336 int rc = X86EMUL_CONTINUE;
1c73ef66 1337
2dbd0dd7 1338 op->type = OP_MEM;
9dac77fa 1339 switch (ctxt->ad_bytes) {
1c73ef66 1340 case 2:
e85a1085 1341 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1342 break;
1343 case 4:
e85a1085 1344 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1345 break;
1346 case 8:
e85a1085 1347 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1348 break;
1349 }
1350done:
1351 return rc;
1352}
1353
9dac77fa 1354static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1355{
7129eeca 1356 long sv = 0, mask;
35c843c4 1357
9dac77fa 1358 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1359 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1360
9dac77fa
AK		 1361 if (ctxt->src.bytes == 2)
1362 sv = (s16)ctxt->src.val & (s16)mask;
1363 else if (ctxt->src.bytes == 4)
1364 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1365 else
1366 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1367
1c1c35ae
NA		 1368 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1369 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1370 }
ba7ff2b7
WY		 1371
1372 /* only subword offset */
9dac77fa 1373 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1374}
1375
dde7e6d1 1376static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1377 unsigned long addr, void *dest, unsigned size)
6aa8b732 1378{
dde7e6d1 1379 int rc;
9dac77fa 1380 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1381
f23b070e
XG		 1382 if (mc->pos < mc->end)
1383 goto read_cached;
6aa8b732 1384
f23b070e
XG		 1385 WARN_ON((mc->end + size) >= sizeof(mc->data));
1386
1387 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1388 &ctxt->exception);
1389 if (rc != X86EMUL_CONTINUE)
1390 return rc;
1391
1392 mc->end += size;
1393
1394read_cached:
1395 memcpy(dest, mc->data + mc->pos, size);
1396 mc->pos += size;
dde7e6d1
AK		 1397 return X86EMUL_CONTINUE;
1398}
6aa8b732 1399
3ca3ac4d
AK		 1400static int segmented_read(struct x86_emulate_ctxt *ctxt,
1401 struct segmented_address addr,
1402 void *data,
1403 unsigned size)
1404{
9fa088f4
AK		 1405 int rc;
1406 ulong linear;
1407
83b8795a 1408 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1409 if (rc != X86EMUL_CONTINUE)
1410 return rc;
7b105ca2 1411 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1412}
1413
1414static int segmented_write(struct x86_emulate_ctxt *ctxt,
1415 struct segmented_address addr,
1416 const void *data,
1417 unsigned size)
1418{
9fa088f4
AK		 1419 int rc;
1420 ulong linear;
1421
83b8795a 1422 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1423 if (rc != X86EMUL_CONTINUE)
1424 return rc;
0f65dd70
AK		 1425 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1426 &ctxt->exception);
3ca3ac4d
AK		 1427}
1428
1429static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1430 struct segmented_address addr,
1431 const void *orig_data, const void *data,
1432 unsigned size)
1433{
9fa088f4
AK		 1434 int rc;
1435 ulong linear;
1436
83b8795a 1437 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
0f65dd70
AK		 1440 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1441 size, &ctxt->exception);
3ca3ac4d
AK		 1442}
1443
dde7e6d1 1444static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1445 unsigned int size, unsigned short port,
1446 void *dest)
1447{
9dac77fa 1448 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1449
dde7e6d1 1450 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1451 unsigned int in_page, n;
9dac77fa 1452 unsigned int count = ctxt->rep_prefix ?
dd856efa 1453 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1454 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1455 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1456 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1457 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1458 if (n == 0)
1459 n = 1;
1460 rc->pos = rc->end = 0;
7b105ca2 1461 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1462 return 0;
1463 rc->end = n * size;
6aa8b732
AK		 1464 }
1465
e6e39f04 1466 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1467 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1468 ctxt->dst.data = rc->data + rc->pos;
1469 ctxt->dst.type = OP_MEM_STR;
1470 ctxt->dst.count = (rc->end - rc->pos) / size;
1471 rc->pos = rc->end;
1472 } else {
1473 memcpy(dest, rc->data + rc->pos, size);
1474 rc->pos += size;
1475 }
dde7e6d1
AK		 1476 return 1;
1477}
6aa8b732 1478
7f3d35fd
KW		 1479static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1480 u16 index, struct desc_struct *desc)
1481{
1482 struct desc_ptr dt;
1483 ulong addr;
1484
1485 ctxt->ops->get_idt(ctxt, &dt);
1486
1487 if (dt.size < index * 8 + 7)
1488 return emulate_gp(ctxt, index << 3 | 0x2);
1489
1490 addr = dt.address + index * 8;
1491 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1492 &ctxt->exception);
1493}
1494
dde7e6d1 1495static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1496 u16 selector, struct desc_ptr *dt)
1497{
0225fb50 1498 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1499 u32 base3 = 0;
7b105ca2 1500
dde7e6d1
AK		 1501 if (selector & 1 << 2) {
1502 struct desc_struct desc;
1aa36616
AK		 1503 u16 sel;
1504
dde7e6d1 1505 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1506 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1507 VCPU_SREG_LDTR))
dde7e6d1 1508 return;
e09d082c 1509
dde7e6d1 1510 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1511 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1512 } else
4bff1e86 1513 ops->get_gdt(ctxt, dt);
dde7e6d1 1514}
120df890 1515
edccda7c
NA		 1516static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1517 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1518{
1519 struct desc_ptr dt;
1520 u16 index = selector >> 3;
dde7e6d1 1521 ulong addr;
120df890 1522
7b105ca2 1523 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1524
35d3d4a1
AK		 1525 if (dt.size < index * 8 + 7)
1526 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1527
edccda7c
NA		 1528 addr = dt.address + index * 8;
1529
1530#ifdef CONFIG_X86_64
1531 if (addr >> 32 != 0) {
1532 u64 efer = 0;
1533
1534 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1535 if (!(efer & EFER_LMA))
1536 addr &= (u32)-1;
1537 }
1538#endif
1539
1540 *desc_addr_p = addr;
1541 return X86EMUL_CONTINUE;
1542}
1543
1544/* allowed just for 8 bytes segments */
1545static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1546 u16 selector, struct desc_struct *desc,
1547 ulong *desc_addr_p)
1548{
1549 int rc;
1550
1551 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1552 if (rc != X86EMUL_CONTINUE)
1553 return rc;
1554
1555 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1556 &ctxt->exception);
dde7e6d1 1557}
ef65c889 1558
dde7e6d1
AK		 1559/* allowed just for 8 bytes segments */
1560static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1561 u16 selector, struct desc_struct *desc)
1562{
edccda7c 1563 int rc;
dde7e6d1 1564 ulong addr;
6aa8b732 1565
edccda7c
NA		 1566 rc = get_descriptor_ptr(ctxt, selector, &addr);
1567 if (rc != X86EMUL_CONTINUE)
1568 return rc;
6aa8b732 1569
7b105ca2
TY		 1570 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1571 &ctxt->exception);
dde7e6d1 1572}
c7e75a3d 1573
5601d05b 1574/* Does not support long mode */
2356aaeb 1575static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1576 u16 selector, int seg, u8 cpl,
3dc4bc4f 1577 enum x86_transfer_type transfer,
d1442d85 1578 struct desc_struct *desc)
dde7e6d1 1579{
869be99c 1580 struct desc_struct seg_desc, old_desc;
2356aaeb 1581 u8 dpl, rpl;
dde7e6d1
AK		 1582 unsigned err_vec = GP_VECTOR;
1583 u32 err_code = 0;
1584 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1585 ulong desc_addr;
dde7e6d1 1586 int ret;
03ebebeb 1587 u16 dummy;
e37a75a1 1588 u32 base3 = 0;
69f55cb1 1589
dde7e6d1 1590 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1591
f8da94e9
KW		 1592 if (ctxt->mode == X86EMUL_MODE_REAL) {
1593 /* set real mode segment descriptor (keep limit etc. for
1594 * unreal mode) */
03ebebeb 1595 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1596 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1597 goto load;
f8da94e9
KW		 1598 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1599 /* VM86 needs a clean new segment descriptor */
1600 set_desc_base(&seg_desc, selector << 4);
1601 set_desc_limit(&seg_desc, 0xffff);
1602 seg_desc.type = 3;
1603 seg_desc.p = 1;
1604 seg_desc.s = 1;
1605 seg_desc.dpl = 3;
1606 goto load;
dde7e6d1
AK		 1607 }
1608
79d5b4c3 1609 rpl = selector & 3;
79d5b4c3
AK		 1610
1611 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1612 if ((seg == VCPU_SREG_CS
1613 || (seg == VCPU_SREG_SS
1614 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1615 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1616 && null_selector)
1617 goto exception;
1618
1619 /* TR should be in GDT only */
1620 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1621 goto exception;
1622
1623 if (null_selector) /* for NULL selector skip all following checks */
1624 goto load;
1625
e919464b 1626 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1627 if (ret != X86EMUL_CONTINUE)
1628 return ret;
1629
1630 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1631 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1632 GP_VECTOR;
dde7e6d1 1633
fc058680 1634 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1635 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1636 if (transfer == X86_TRANSFER_CALL_JMP)
1637 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1638 goto exception;
3dc4bc4f 1639 }
dde7e6d1
AK		 1640
1641 if (!seg_desc.p) {
1642 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1643 goto exception;
1644 }
1645
dde7e6d1 1646 dpl = seg_desc.dpl;
dde7e6d1
AK		 1647
1648 switch (seg) {
1649 case VCPU_SREG_SS:
1650 /*
1651 * segment is not a writable data segment or segment
1652 * selector's RPL != CPL or segment selector's RPL != CPL
1653 */
1654 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1655 goto exception;
6aa8b732 1656 break;
dde7e6d1
AK		 1657 case VCPU_SREG_CS:
1658 if (!(seg_desc.type & 8))
1659 goto exception;
1660
1661 if (seg_desc.type & 4) {
1662 /* conforming */
1663 if (dpl > cpl)
1664 goto exception;
1665 } else {
1666 /* nonconforming */
1667 if (rpl > cpl || dpl != cpl)
1668 goto exception;
1669 }
040c8dc8
NA		 1670 /* in long-mode d/b must be clear if l is set */
1671 if (seg_desc.d && seg_desc.l) {
1672 u64 efer = 0;
1673
1674 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1675 if (efer & EFER_LMA)
1676 goto exception;
1677 }
1678
dde7e6d1
AK		 1679 /* CS(RPL) <- CPL */
1680 selector = (selector & 0xfffc) | cpl;
6aa8b732 1681 break;
dde7e6d1
AK		 1682 case VCPU_SREG_TR:
1683 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1684 goto exception;
869be99c
AK		 1685 old_desc = seg_desc;
1686 seg_desc.type |= 2; /* busy */
1687 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1688 sizeof(seg_desc), &ctxt->exception);
1689 if (ret != X86EMUL_CONTINUE)
1690 return ret;
dde7e6d1
AK		 1691 break;
1692 case VCPU_SREG_LDTR:
1693 if (seg_desc.s || seg_desc.type != 2)
1694 goto exception;
1695 break;
1696 default: /* DS, ES, FS, or GS */
4e62417b 1697 /*
dde7e6d1
AK		 1698 * segment is not a data or readable code segment or
1699 * ((segment is a data or nonconforming code segment)
1700 * and (both RPL and CPL > DPL))
4e62417b 1701 */
dde7e6d1
AK		 1702 if ((seg_desc.type & 0xa) == 0x8 ||
1703 (((seg_desc.type & 0xc) != 0xc) &&
1704 (rpl > dpl && cpl > dpl)))
1705 goto exception;
6aa8b732 1706 break;
dde7e6d1
AK		 1707 }
1708
1709 if (seg_desc.s) {
1710 /* mark segment as accessed */
e2cefa74
NA		 1711 if (!(seg_desc.type & 1)) {
1712 seg_desc.type |= 1;
1713 ret = write_segment_descriptor(ctxt, selector,
1714 &seg_desc);
1715 if (ret != X86EMUL_CONTINUE)
1716 return ret;
1717 }
e37a75a1
NA		 1718 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1719 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1720 sizeof(base3), &ctxt->exception);
1721 if (ret != X86EMUL_CONTINUE)
1722 return ret;
9a9abf6b
NA		 1723 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1724 ((u64)base3 << 32)))
1725 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1726 }
1727load:
e37a75a1 1728 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1729 if (desc)
1730 *desc = seg_desc;
dde7e6d1
AK		 1731 return X86EMUL_CONTINUE;
1732exception:
592f0858 1733 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1734}
1735
2356aaeb
PB		 1736static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1737 u16 selector, int seg)
1738{
1739 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1740 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1741 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1742}
1743
31be40b3
WY		 1744static void write_register_operand(struct operand *op)
1745{
6fd8e127 1746 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1747}
1748
fb32b1ed 1749static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1750{
fb32b1ed 1751 switch (op->type) {
dde7e6d1 1752 case OP_REG:
fb32b1ed 1753 write_register_operand(op);
6aa8b732 1754 break;
dde7e6d1 1755 case OP_MEM:
9dac77fa 1756 if (ctxt->lock_prefix)
f5f87dfb
PB		 1757 return segmented_cmpxchg(ctxt,
1758 op->addr.mem,
1759 &op->orig_val,
1760 &op->val,
1761 op->bytes);
1762 else
1763 return segmented_write(ctxt,
fb32b1ed 1764 op->addr.mem,
fb32b1ed
AK		 1765 &op->val,
1766 op->bytes);
a682e354 1767 break;
b3356bf0 1768 case OP_MEM_STR:
f5f87dfb
PB		 1769 return segmented_write(ctxt,
1770 op->addr.mem,
1771 op->data,
1772 op->bytes * op->count);
b3356bf0 1773 break;
1253791d 1774 case OP_XMM:
fb32b1ed 1775 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1776 break;
cbe2c9d3 1777 case OP_MM:
fb32b1ed 1778 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1779 break;
dde7e6d1
AK		 1780 case OP_NONE:
1781 /* no writeback */
414e6277 1782 break;
dde7e6d1 1783 default:
414e6277 1784 break;
6aa8b732 1785 }
dde7e6d1
AK		 1786 return X86EMUL_CONTINUE;
1787}
6aa8b732 1788
51ddff50 1789static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1790{
4179bb02 1791 struct segmented_address addr;
0dc8d10f 1792
5ad105e5 1793 rsp_increment(ctxt, -bytes);
dd856efa 1794 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1795 addr.seg = VCPU_SREG_SS;
1796
51ddff50
AK		 1797 return segmented_write(ctxt, addr, data, bytes);
1798}
1799
1800static int em_push(struct x86_emulate_ctxt *ctxt)
1801{
4179bb02 1802 /* Disable writeback. */
9dac77fa 1803 ctxt->dst.type = OP_NONE;
51ddff50 1804 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1805}
69f55cb1 1806
dde7e6d1 1807static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1808 void *dest, int len)
1809{
dde7e6d1 1810 int rc;
90de84f5 1811 struct segmented_address addr;
8b4caf66 1812
dd856efa 1813 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1814 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1815 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1816 if (rc != X86EMUL_CONTINUE)
1817 return rc;
1818
5ad105e5 1819 rsp_increment(ctxt, len);
dde7e6d1 1820 return rc;
8b4caf66
LV		 1821}
1822
c54fe504
TY		 1823static int em_pop(struct x86_emulate_ctxt *ctxt)
1824{
9dac77fa 1825 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1826}
1827
dde7e6d1 1828static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1829 void *dest, int len)
9de41573
GN		 1830{
1831 int rc;
dde7e6d1 1832 unsigned long val, change_mask;
0efb0440 1833 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1834 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1835
3b9be3bf 1836 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1837 if (rc != X86EMUL_CONTINUE)
1838 return rc;
9de41573 1839
0efb0440
NA		 1840 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1841 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1842 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1843 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1844
dde7e6d1
AK		 1845 switch(ctxt->mode) {
1846 case X86EMUL_MODE_PROT64:
1847 case X86EMUL_MODE_PROT32:
1848 case X86EMUL_MODE_PROT16:
1849 if (cpl == 0)
0efb0440 1850 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1851 if (cpl <= iopl)
0efb0440 1852 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1853 break;
1854 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1855 if (iopl < 3)
1856 return emulate_gp(ctxt, 0);
0efb0440 1857 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1858 break;
1859 default: /* real mode */
0efb0440 1860 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1861 break;
9de41573 1862 }
dde7e6d1
AK		 1863
1864 *(unsigned long *)dest =
1865 (ctxt->eflags & ~change_mask) | (val & change_mask);
1866
1867 return rc;
9de41573
GN		 1868}
1869
62aaa2f0
TY		 1870static int em_popf(struct x86_emulate_ctxt *ctxt)
1871{
9dac77fa
AK		 1872 ctxt->dst.type = OP_REG;
1873 ctxt->dst.addr.reg = &ctxt->eflags;
1874 ctxt->dst.bytes = ctxt->op_bytes;
1875 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1876}
1877
612e89f0
AK		 1878static int em_enter(struct x86_emulate_ctxt *ctxt)
1879{
1880 int rc;
1881 unsigned frame_size = ctxt->src.val;
1882 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1883 ulong rbp;
612e89f0
AK		 1884
1885 if (nesting_level)
1886 return X86EMUL_UNHANDLEABLE;
1887
dd856efa
AK		 1888 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1889 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1890 if (rc != X86EMUL_CONTINUE)
1891 return rc;
dd856efa 1892 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1893 stack_mask(ctxt));
dd856efa
AK		 1894 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1895 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1896 stack_mask(ctxt));
1897 return X86EMUL_CONTINUE;
1898}
1899
f47cfa31
AK		 1900static int em_leave(struct x86_emulate_ctxt *ctxt)
1901{
dd856efa 1902 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1903 stack_mask(ctxt));
dd856efa 1904 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1905}
1906
1cd196ea 1907static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1908{
1cd196ea
AK		 1909 int seg = ctxt->src2.val;
1910
9dac77fa 1911 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1912 if (ctxt->op_bytes == 4) {
1913 rsp_increment(ctxt, -2);
1914 ctxt->op_bytes = 2;
1915 }
7b262e90 1916
4487b3b4 1917 return em_push(ctxt);
7b262e90
GN		 1918}
1919
1cd196ea 1920static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1921{
1cd196ea 1922 int seg = ctxt->src2.val;
dde7e6d1
AK		 1923 unsigned long selector;
1924 int rc;
38ba30ba 1925
3313bc4e 1926 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1927 if (rc != X86EMUL_CONTINUE)
1928 return rc;
1929
a5457e7b
PB		 1930 if (ctxt->modrm_reg == VCPU_SREG_SS)
1931 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1932 if (ctxt->op_bytes > 2)
1933 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1934
7b105ca2 1935 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1936 return rc;
38ba30ba
GN		 1937}
1938
b96a7fad 1939static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1940{
dd856efa 1941 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1942 int rc = X86EMUL_CONTINUE;
1943 int reg = VCPU_REGS_RAX;
38ba30ba 1944
dde7e6d1
AK		 1945 while (reg <= VCPU_REGS_RDI) {
1946 (reg == VCPU_REGS_RSP) ?
dd856efa 1947 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1948
4487b3b4 1949 rc = em_push(ctxt);
dde7e6d1
AK		 1950 if (rc != X86EMUL_CONTINUE)
1951 return rc;
38ba30ba 1952
dde7e6d1 1953 ++reg;
38ba30ba 1954 }
38ba30ba 1955
dde7e6d1 1956 return rc;
38ba30ba
GN		 1957}
1958
62aaa2f0
TY		 1959static int em_pushf(struct x86_emulate_ctxt *ctxt)
1960{
0efb0440 1961 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 1962 return em_push(ctxt);
1963}
1964
b96a7fad 1965static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1966{
dde7e6d1
AK		 1967 int rc = X86EMUL_CONTINUE;
1968 int reg = VCPU_REGS_RDI;
6fd8e127 1969 u32 val;
38ba30ba 1970
dde7e6d1
AK		 1971 while (reg >= VCPU_REGS_RAX) {
1972 if (reg == VCPU_REGS_RSP) {
5ad105e5 1973 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1974 --reg;
1975 }
38ba30ba 1976
6fd8e127 1977 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 break;
6fd8e127 1980 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 1981 --reg;
38ba30ba 1982 }
dde7e6d1 1983 return rc;
38ba30ba
GN		 1984}
1985
dd856efa 1986static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1987{
0225fb50 1988 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1989 int rc;
6e154e56
MG		 1990 struct desc_ptr dt;
1991 gva_t cs_addr;
1992 gva_t eip_addr;
1993 u16 cs, eip;
6e154e56
MG		 1994
1995 /* TODO: Add limit checks */
9dac77fa 1996 ctxt->src.val = ctxt->eflags;
4487b3b4 1997 rc = em_push(ctxt);
5c56e1cf
AK		 1998 if (rc != X86EMUL_CONTINUE)
1999 return rc;
6e154e56 2000
0efb0440 2001 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2002
9dac77fa 2003 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2004 rc = em_push(ctxt);
5c56e1cf
AK		 2005 if (rc != X86EMUL_CONTINUE)
2006 return rc;
6e154e56 2007
9dac77fa 2008 ctxt->src.val = ctxt->_eip;
4487b3b4 2009 rc = em_push(ctxt);
5c56e1cf
AK		 2010 if (rc != X86EMUL_CONTINUE)
2011 return rc;
2012
4bff1e86 2013 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2014
2015 eip_addr = dt.address + (irq << 2);
2016 cs_addr = dt.address + (irq << 2) + 2;
2017
0f65dd70 2018 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 2019 if (rc != X86EMUL_CONTINUE)
2020 return rc;
2021
0f65dd70 2022 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 2023 if (rc != X86EMUL_CONTINUE)
2024 return rc;
2025
7b105ca2 2026 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2027 if (rc != X86EMUL_CONTINUE)
2028 return rc;
2029
9dac77fa 2030 ctxt->_eip = eip;
6e154e56
MG		 2031
2032 return rc;
2033}
2034
dd856efa
AK		 2035int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2036{
2037 int rc;
2038
2039 invalidate_registers(ctxt);
2040 rc = __emulate_int_real(ctxt, irq);
2041 if (rc == X86EMUL_CONTINUE)
2042 writeback_registers(ctxt);
2043 return rc;
2044}
2045
7b105ca2 2046static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2047{
2048 switch(ctxt->mode) {
2049 case X86EMUL_MODE_REAL:
dd856efa 2050 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2051 case X86EMUL_MODE_VM86:
2052 case X86EMUL_MODE_PROT16:
2053 case X86EMUL_MODE_PROT32:
2054 case X86EMUL_MODE_PROT64:
2055 default:
2056 /* Protected mode interrupts unimplemented yet */
2057 return X86EMUL_UNHANDLEABLE;
2058 }
2059}
2060
7b105ca2 2061static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2062{
dde7e6d1
AK		 2063 int rc = X86EMUL_CONTINUE;
2064 unsigned long temp_eip = 0;
2065 unsigned long temp_eflags = 0;
2066 unsigned long cs = 0;
0efb0440
NA		 2067 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2068 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2069 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2070 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2071 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2072 X86_EFLAGS_FIXED;
0efb0440
NA		 2073 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2074 X86_EFLAGS_VIP;
38ba30ba 2075
dde7e6d1 2076 /* TODO: Add stack limit check */
38ba30ba 2077
9dac77fa 2078 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2079
dde7e6d1
AK		 2080 if (rc != X86EMUL_CONTINUE)
2081 return rc;
38ba30ba 2082
35d3d4a1
AK		 2083 if (temp_eip & ~0xffff)
2084 return emulate_gp(ctxt, 0);
38ba30ba 2085
9dac77fa 2086 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2087
dde7e6d1
AK		 2088 if (rc != X86EMUL_CONTINUE)
2089 return rc;
38ba30ba 2090
9dac77fa 2091 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2092
dde7e6d1
AK		 2093 if (rc != X86EMUL_CONTINUE)
2094 return rc;
38ba30ba 2095
7b105ca2 2096 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2097
dde7e6d1
AK		 2098 if (rc != X86EMUL_CONTINUE)
2099 return rc;
38ba30ba 2100
9dac77fa 2101 ctxt->_eip = temp_eip;
38ba30ba 2102
9dac77fa 2103 if (ctxt->op_bytes == 4)
dde7e6d1 2104 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2105 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2106 ctxt->eflags &= ~0xffff;
2107 ctxt->eflags |= temp_eflags;
38ba30ba 2108 }
dde7e6d1
AK		 2109
2110 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2111 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2112 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2113
2114 return rc;
38ba30ba
GN		 2115}
2116
e01991e7 2117static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2118{
dde7e6d1
AK		 2119 switch(ctxt->mode) {
2120 case X86EMUL_MODE_REAL:
7b105ca2 2121 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2122 case X86EMUL_MODE_VM86:
2123 case X86EMUL_MODE_PROT16:
2124 case X86EMUL_MODE_PROT32:
2125 case X86EMUL_MODE_PROT64:
c37eda13 2126 default:
dde7e6d1
AK		 2127 /* iret from protected mode unimplemented yet */
2128 return X86EMUL_UNHANDLEABLE;
c37eda13 2129 }
c37eda13
WY		 2130}
2131
d2f62766
TY		 2132static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2133{
d2f62766 2134 int rc;
d1442d85
NA		 2135 unsigned short sel, old_sel;
2136 struct desc_struct old_desc, new_desc;
2137 const struct x86_emulate_ops *ops = ctxt->ops;
2138 u8 cpl = ctxt->ops->cpl(ctxt);
2139
2140 /* Assignment of RIP may only fail in 64-bit mode */
2141 if (ctxt->mode == X86EMUL_MODE_PROT64)
2142 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2143 VCPU_SREG_CS);
d2f62766 2144
9dac77fa 2145 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2146
3dc4bc4f
NA		 2147 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2148 X86_TRANSFER_CALL_JMP,
d1442d85 2149 &new_desc);
d2f62766
TY		 2150 if (rc != X86EMUL_CONTINUE)
2151 return rc;
2152
d50eaa18 2153 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2154 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2155 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2156 /* assigning eip failed; restore the old cs */
2157 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2158 return rc;
2159 }
2160 return rc;
d2f62766
TY		 2161}
2162
f7784046 2163static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2164{
f7784046
NA		 2165 return assign_eip_near(ctxt, ctxt->src.val);
2166}
8cdbd2c9 2167
f7784046
NA		 2168static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2169{
2170 int rc;
2171 long int old_eip;
2172
2173 old_eip = ctxt->_eip;
2174 rc = assign_eip_near(ctxt, ctxt->src.val);
2175 if (rc != X86EMUL_CONTINUE)
2176 return rc;
2177 ctxt->src.val = old_eip;
2178 rc = em_push(ctxt);
4179bb02 2179 return rc;
8cdbd2c9
LV		 2180}
2181
e0dac408 2182static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2183{
9dac77fa 2184 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2185
aaa05f24
NA		 2186 if (ctxt->dst.bytes == 16)
2187 return X86EMUL_UNHANDLEABLE;
2188
dd856efa
AK		 2189 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2190 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2191 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2192 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2193 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2194 } else {
dd856efa
AK		 2195 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2196 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2197
0efb0440 2198 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2199 }
1b30eaa8 2200 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2201}
2202
ebda02c2
TY		 2203static int em_ret(struct x86_emulate_ctxt *ctxt)
2204{
234f3ce4
NA		 2205 int rc;
2206 unsigned long eip;
2207
2208 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2209 if (rc != X86EMUL_CONTINUE)
2210 return rc;
2211
2212 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2213}
2214
e01991e7 2215static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2216{
a77ab5ea 2217 int rc;
d1442d85
NA		 2218 unsigned long eip, cs;
2219 u16 old_cs;
9e8919ae 2220 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2221 struct desc_struct old_desc, new_desc;
2222 const struct x86_emulate_ops *ops = ctxt->ops;
2223
2224 if (ctxt->mode == X86EMUL_MODE_PROT64)
2225 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2226 VCPU_SREG_CS);
a77ab5ea 2227
d1442d85 2228 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2229 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2230 return rc;
9dac77fa 2231 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2232 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2233 return rc;
9e8919ae
NA		 2234 /* Outer-privilege level return is not implemented */
2235 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2236 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2237 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2238 X86_TRANSFER_RET,
d1442d85
NA		 2239 &new_desc);
2240 if (rc != X86EMUL_CONTINUE)
2241 return rc;
d50eaa18 2242 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2243 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2244 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2245 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2246 }
a77ab5ea
AK		 2247 return rc;
2248}
2249
3261107e
BR		 2250static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2251{
2252 int rc;
2253
2254 rc = em_ret_far(ctxt);
2255 if (rc != X86EMUL_CONTINUE)
2256 return rc;
2257 rsp_increment(ctxt, ctxt->src.val);
2258 return X86EMUL_CONTINUE;
2259}
2260
e940b5c2
TY		 2261static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2262{
2263 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2264 ctxt->dst.orig_val = ctxt->dst.val;
2265 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2266 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2267 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2268 fastop(ctxt, em_cmp);
e940b5c2 2269
0efb0440 2270 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2271 /* Success: write back to memory; no update of EAX */
2272 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2273 ctxt->dst.val = ctxt->src.orig_val;
2274 } else {
2275 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2276 ctxt->src.type = OP_REG;
2277 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2278 ctxt->src.val = ctxt->dst.orig_val;
2279 /* Create write-cycle to dest by writing the same value */
37c564f2 2280 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2281 }
2282 return X86EMUL_CONTINUE;
2283}
2284
d4b4325f 2285static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2286{
d4b4325f 2287 int seg = ctxt->src2.val;
09b5f4d3
WY		 2288 unsigned short sel;
2289 int rc;
2290
9dac77fa 2291 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2292
7b105ca2 2293 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2294 if (rc != X86EMUL_CONTINUE)
2295 return rc;
2296
9dac77fa 2297 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2298 return rc;
2299}
2300
660a5d51
PB		 2301static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2302{
2303 u32 eax, ebx, ecx, edx;
2304
2305 eax = 0x80000001;
2306 ecx = 0;
2307 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2308 return edx & bit(X86_FEATURE_LM);
2309}
2310
2311#define GET_SMSTATE(type, smbase, offset) \
2312 ({ \
2313 type __val; \
f40606b1
RK		 2314 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \
2315 sizeof(__val)); \
660a5d51
PB		 2316 if (r != X86EMUL_CONTINUE) \
2317 return X86EMUL_UNHANDLEABLE; \
2318 __val; \
2319 })
2320
2321static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2322{
2323 desc->g = (flags >> 23) & 1;
2324 desc->d = (flags >> 22) & 1;
2325 desc->l = (flags >> 21) & 1;
2326 desc->avl = (flags >> 20) & 1;
2327 desc->p = (flags >> 15) & 1;
2328 desc->dpl = (flags >> 13) & 3;
2329 desc->s = (flags >> 12) & 1;
2330 desc->type = (flags >> 8) & 15;
2331}
2332
2333static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2334{
2335 struct desc_struct desc;
2336 int offset;
2337 u16 selector;
2338
2339 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2340
2341 if (n < 3)
2342 offset = 0x7f84 + n * 12;
2343 else
2344 offset = 0x7f2c + (n - 3) * 12;
2345
2346 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2347 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2348 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2349 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2350 return X86EMUL_CONTINUE;
2351}
2352
2353static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2354{
2355 struct desc_struct desc;
2356 int offset;
2357 u16 selector;
2358 u32 base3;
2359
2360 offset = 0x7e00 + n * 16;
2361
2362 selector = GET_SMSTATE(u16, smbase, offset);
2363 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2364 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2365 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2366 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2367
2368 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2369 return X86EMUL_CONTINUE;
2370}
2371
2372static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2373 u64 cr0, u64 cr4)
2374{
2375 int bad;
2376
2377 /*
2378 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2379 * Then enable protected mode. However, PCID cannot be enabled
2380 * if EFER.LMA=0, so set it separately.
2381 */
2382 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2383 if (bad)
2384 return X86EMUL_UNHANDLEABLE;
2385
2386 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2387 if (bad)
2388 return X86EMUL_UNHANDLEABLE;
2389
2390 if (cr4 & X86_CR4_PCIDE) {
2391 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2392 if (bad)
2393 return X86EMUL_UNHANDLEABLE;
2394 }
2395
2396 return X86EMUL_CONTINUE;
2397}
2398
2399static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2400{
2401 struct desc_struct desc;
2402 struct desc_ptr dt;
2403 u16 selector;
2404 u32 val, cr0, cr4;
2405 int i;
2406
2407 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
2408 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8));
2409 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2410 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2411
2412 for (i = 0; i < 8; i++)
2413 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2414
2415 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2416 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2417 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2418 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2419
2420 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2421 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2422 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2423 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2424 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2425
2426 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2427 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2428 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2429 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2430 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2431
2432 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2433 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2434 ctxt->ops->set_gdt(ctxt, &dt);
2435
2436 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2437 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2438 ctxt->ops->set_idt(ctxt, &dt);
2439
2440 for (i = 0; i < 6; i++) {
2441 int r = rsm_load_seg_32(ctxt, smbase, i);
2442 if (r != X86EMUL_CONTINUE)
2443 return r;
2444 }
2445
2446 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2447
2448 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2449
2450 return rsm_enter_protected_mode(ctxt, cr0, cr4);
2451}
2452
2453static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2454{
2455 struct desc_struct desc;
2456 struct desc_ptr dt;
2457 u64 val, cr0, cr4;
2458 u32 base3;
2459 u16 selector;
b10d92a5 2460 int i, r;
660a5d51
PB		 2461
2462 for (i = 0; i < 16; i++)
2463 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2464
2465 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2466 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2467
2468 val = GET_SMSTATE(u32, smbase, 0x7f68);
2469 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2470 val = GET_SMSTATE(u32, smbase, 0x7f60);
2471 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2472
2473 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
2474 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50));
2475 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2476 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2477 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2478 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2479
2480 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2481 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2482 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2483 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2484 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2485 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2486
2487 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2488 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2489 ctxt->ops->set_idt(ctxt, &dt);
2490
2491 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2492 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2493 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2494 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2495 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2496 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2497
2498 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2499 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2500 ctxt->ops->set_gdt(ctxt, &dt);
2501
b10d92a5
PB		 2502 r = rsm_enter_protected_mode(ctxt, cr0, cr4);
2503 if (r != X86EMUL_CONTINUE)
2504 return r;
2505
660a5d51 2506 for (i = 0; i < 6; i++) {
b10d92a5 2507 r = rsm_load_seg_64(ctxt, smbase, i);
660a5d51
PB		 2508 if (r != X86EMUL_CONTINUE)
2509 return r;
2510 }
2511
b10d92a5 2512 return X86EMUL_CONTINUE;
660a5d51
PB		 2513}
2514
64d60670
PB		 2515static int em_rsm(struct x86_emulate_ctxt *ctxt)
2516{
660a5d51
PB		 2517 unsigned long cr0, cr4, efer;
2518 u64 smbase;
2519 int ret;
2520
64d60670
PB		 2521 if ((ctxt->emul_flags & X86EMUL_SMM_MASK) == 0)
2522 return emulate_ud(ctxt);
2523
660a5d51
PB		 2524 /*
2525 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2526 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2527 * supports long mode.
660a5d51 2528 */
89651a3d
PB		 2529 cr4 = ctxt->ops->get_cr(ctxt, 4);
2530 if (emulator_has_longmode(ctxt)) {
2531 struct desc_struct cs_desc;
2532
2533 /* Zero CR4.PCIDE before CR0.PG. */
2534 if (cr4 & X86_CR4_PCIDE) {
2535 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2536 cr4 &= ~X86_CR4_PCIDE;
2537 }
2538
2539 /* A 32-bit code segment is required to clear EFER.LMA. */
2540 memset(&cs_desc, 0, sizeof(cs_desc));
2541 cs_desc.type = 0xb;
2542 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2543 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2544 }
2545
2546 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2547 cr0 = ctxt->ops->get_cr(ctxt, 0);
2548 if (cr0 & X86_CR0_PE)
2549 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d
PB		 2550
2551 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
660a5d51
PB		 2552 if (cr4 & X86_CR4_PAE)
2553 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
89651a3d
PB		 2554
2555 /* And finally go back to 32-bit mode. */
660a5d51
PB		 2556 efer = 0;
2557 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2558
2559 smbase = ctxt->ops->get_smbase(ctxt);
2560 if (emulator_has_longmode(ctxt))
2561 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2562 else
2563 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2564
2565 if (ret != X86EMUL_CONTINUE) {
2566 /* FIXME: should triple fault */
2567 return X86EMUL_UNHANDLEABLE;
2568 }
2569
2570 if ((ctxt->emul_flags & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2571 ctxt->ops->set_nmi_mask(ctxt, false);
2572
2573 ctxt->emul_flags &= ~X86EMUL_SMM_INSIDE_NMI_MASK;
2574 ctxt->emul_flags &= ~X86EMUL_SMM_MASK;
2575 return X86EMUL_CONTINUE;
64d60670
PB		 2576}
2577
7b105ca2 2578static void
e66bb2cc 2579setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2580 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2581{
e66bb2cc 2582 cs->l = 0; /* will be adjusted later */
79168fd1 2583 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2584 cs->g = 1; /* 4kb granularity */
79168fd1 2585 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2586 cs->type = 0x0b; /* Read, Execute, Accessed */
2587 cs->s = 1;
2588 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2589 cs->p = 1;
2590 cs->d = 1;
99245b50 2591 cs->avl = 0;
e66bb2cc 2592
79168fd1
GN		 2593 set_desc_base(ss, 0); /* flat segment */
2594 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2595 ss->g = 1; /* 4kb granularity */
2596 ss->s = 1;
2597 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2598 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2599 ss->dpl = 0;
79168fd1 2600 ss->p = 1;
99245b50
GN		 2601 ss->l = 0;
2602 ss->avl = 0;
e66bb2cc
AP		 2603}
2604
1a18a69b
AK		 2605static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2606{
2607 u32 eax, ebx, ecx, edx;
2608
2609 eax = ecx = 0;
0017f93a
AK		 2610 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2611 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2612 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2613 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2614}
2615
c2226fc9
SB		 2616static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2617{
0225fb50 2618 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2619 u32 eax, ebx, ecx, edx;
2620
2621 /*
2622 * syscall should always be enabled in longmode - so only become
2623 * vendor specific (cpuid) if other modes are active...
2624 */
2625 if (ctxt->mode == X86EMUL_MODE_PROT64)
2626 return true;
2627
2628 eax = 0x00000000;
2629 ecx = 0x00000000;
0017f93a
AK		 2630 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2631 /*
2632 * Intel ("GenuineIntel")
2633 * remark: Intel CPUs only support "syscall" in 64bit
2634 * longmode. Also an 64bit guest with a
2635 * 32bit compat-app running will #UD !! While this
2636 * behaviour can be fixed (by emulating) into AMD
2637 * response - CPUs of AMD can't behave like Intel.
2638 */
2639 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2640 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2641 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2642 return false;
2643
2644 /* AMD ("AuthenticAMD") */
2645 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2646 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2647 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2648 return true;
2649
2650 /* AMD ("AMDisbetter!") */
2651 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2652 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2653 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2654 return true;
c2226fc9
SB		 2655
2656 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2657 return false;
2658}
2659
e01991e7 2660static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2661{
0225fb50 2662 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2663 struct desc_struct cs, ss;
e66bb2cc 2664 u64 msr_data;
79168fd1 2665 u16 cs_sel, ss_sel;
c2ad2bb3 2666 u64 efer = 0;
e66bb2cc
AP		 2667
2668 /* syscall is not available in real mode */
2e901c4c 2669 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2670 ctxt->mode == X86EMUL_MODE_VM86)
2671 return emulate_ud(ctxt);
e66bb2cc 2672
c2226fc9
SB		 2673 if (!(em_syscall_is_enabled(ctxt)))
2674 return emulate_ud(ctxt);
2675
c2ad2bb3 2676 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2677 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2678
c2226fc9
SB		 2679 if (!(efer & EFER_SCE))
2680 return emulate_ud(ctxt);
2681
717746e3 2682 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2683 msr_data >>= 32;
79168fd1
GN		 2684 cs_sel = (u16)(msr_data & 0xfffc);
2685 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2686
c2ad2bb3 2687 if (efer & EFER_LMA) {
79168fd1 2688 cs.d = 0;
e66bb2cc
AP		 2689 cs.l = 1;
2690 }
1aa36616
AK		 2691 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2692 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2693
dd856efa 2694 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2695 if (efer & EFER_LMA) {
e66bb2cc 2696#ifdef CONFIG_X86_64
6c6cb69b 2697 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2698
717746e3 2699 ops->get_msr(ctxt,
3fb1b5db
GN		 2700 ctxt->mode == X86EMUL_MODE_PROT64 ?
2701 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2702 ctxt->_eip = msr_data;
e66bb2cc 2703
717746e3 2704 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2705 ctxt->eflags &= ~msr_data;
35fd68a3 2706 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2707#endif
2708 } else {
2709 /* legacy mode */
717746e3 2710 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2711 ctxt->_eip = (u32)msr_data;
e66bb2cc 2712
0efb0440 2713 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2714 }
2715
e54cfa97 2716 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2717}
2718
e01991e7 2719static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2720{
0225fb50 2721 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2722 struct desc_struct cs, ss;
8c604352 2723 u64 msr_data;
79168fd1 2724 u16 cs_sel, ss_sel;
c2ad2bb3 2725 u64 efer = 0;
8c604352 2726
7b105ca2 2727 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2728 /* inject #GP if in real mode */
35d3d4a1
AK		 2729 if (ctxt->mode == X86EMUL_MODE_REAL)
2730 return emulate_gp(ctxt, 0);
8c604352 2731
1a18a69b
AK		 2732 /*
2733 * Not recognized on AMD in compat mode (but is recognized in legacy
2734 * mode).
2735 */
f3747379 2736 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2737 && !vendor_intel(ctxt))
2738 return emulate_ud(ctxt);
2739
b2c9d43e 2740 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2741 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2742 return X86EMUL_UNHANDLEABLE;
8c604352 2743
7b105ca2 2744 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2745
717746e3 2746 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2747 if ((msr_data & 0xfffc) == 0x0)
2748 return emulate_gp(ctxt, 0);
8c604352 2749
0efb0440 2750 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2751 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2752 ss_sel = cs_sel + 8;
f3747379 2753 if (efer & EFER_LMA) {
79168fd1 2754 cs.d = 0;
8c604352
AP		 2755 cs.l = 1;
2756 }
2757
1aa36616
AK		 2758 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2759 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2760
717746e3 2761 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2762 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2763
717746e3 2764 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2765 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2766 (u32)msr_data;
8c604352 2767
e54cfa97 2768 return X86EMUL_CONTINUE;
8c604352
AP		 2769}
2770
e01991e7 2771static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2772{
0225fb50 2773 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2774 struct desc_struct cs, ss;
234f3ce4 2775 u64 msr_data, rcx, rdx;
4668f050 2776 int usermode;
1249b96e 2777 u16 cs_sel = 0, ss_sel = 0;
4668f050 2778
a0044755
GN		 2779 /* inject #GP if in real mode or Virtual 8086 mode */
2780 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2781 ctxt->mode == X86EMUL_MODE_VM86)
2782 return emulate_gp(ctxt, 0);
4668f050 2783
7b105ca2 2784 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2785
9dac77fa 2786 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2787 usermode = X86EMUL_MODE_PROT64;
2788 else
2789 usermode = X86EMUL_MODE_PROT32;
2790
234f3ce4
NA		 2791 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2792 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2793
4668f050
AP		 2794 cs.dpl = 3;
2795 ss.dpl = 3;
717746e3 2796 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2797 switch (usermode) {
2798 case X86EMUL_MODE_PROT32:
79168fd1 2799 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2800 if ((msr_data & 0xfffc) == 0x0)
2801 return emulate_gp(ctxt, 0);
79168fd1 2802 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2803 rcx = (u32)rcx;
2804 rdx = (u32)rdx;
4668f050
AP		 2805 break;
2806 case X86EMUL_MODE_PROT64:
79168fd1 2807 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2808 if (msr_data == 0x0)
2809 return emulate_gp(ctxt, 0);
79168fd1
GN		 2810 ss_sel = cs_sel + 8;
2811 cs.d = 0;
4668f050 2812 cs.l = 1;
234f3ce4
NA		 2813 if (is_noncanonical_address(rcx) ||
2814 is_noncanonical_address(rdx))
2815 return emulate_gp(ctxt, 0);
4668f050
AP		 2816 break;
2817 }
b32a9918
NA		 2818 cs_sel |= SEGMENT_RPL_MASK;
2819 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2820
1aa36616
AK		 2821 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2822 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2823
234f3ce4
NA		 2824 ctxt->_eip = rdx;
2825 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2826
e54cfa97 2827 return X86EMUL_CONTINUE;
4668f050
AP		 2828}
2829
7b105ca2 2830static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2831{
2832 int iopl;
2833 if (ctxt->mode == X86EMUL_MODE_REAL)
2834 return false;
2835 if (ctxt->mode == X86EMUL_MODE_VM86)
2836 return true;
0efb0440 2837 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2838 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2839}
2840
2841static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2842 u16 port, u16 len)
2843{
0225fb50 2844 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2845 struct desc_struct tr_seg;
5601d05b 2846 u32 base3;
f850e2e6 2847 int r;
1aa36616 2848 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2849 unsigned mask = (1 << len) - 1;
5601d05b 2850 unsigned long base;
f850e2e6 2851
1aa36616 2852 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2853 if (!tr_seg.p)
f850e2e6 2854 return false;
79168fd1 2855 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2856 return false;
5601d05b
GN		 2857 base = get_desc_base(&tr_seg);
2858#ifdef CONFIG_X86_64
2859 base |= ((u64)base3) << 32;
2860#endif
0f65dd70 2861 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2862 if (r != X86EMUL_CONTINUE)
2863 return false;
79168fd1 2864 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2865 return false;
0f65dd70 2866 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2867 if (r != X86EMUL_CONTINUE)
2868 return false;
2869 if ((perm >> bit_idx) & mask)
2870 return false;
2871 return true;
2872}
2873
2874static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2875 u16 port, u16 len)
2876{
4fc40f07
GN		 2877 if (ctxt->perm_ok)
2878 return true;
2879
7b105ca2
TY		 2880 if (emulator_bad_iopl(ctxt))
2881 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2882 return false;
4fc40f07
GN		 2883
2884 ctxt->perm_ok = true;
2885
f850e2e6
GN		 2886 return true;
2887}
2888
428e3d08
NA		 2889static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2890{
2891 /*
2892 * Intel CPUs mask the counter and pointers in quite strange
2893 * manner when ECX is zero due to REP-string optimizations.
2894 */
2895#ifdef CONFIG_X86_64
2896 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2897 return;
2898
2899 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2900
2901 switch (ctxt->b) {
2902 case 0xa4: /* movsb */
2903 case 0xa5: /* movsd/w */
2904 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2905 /* fall through */
2906 case 0xaa: /* stosb */
2907 case 0xab: /* stosd/w */
2908 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2909 }
2910#endif
2911}
2912
38ba30ba 2913static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2914 struct tss_segment_16 *tss)
2915{
9dac77fa 2916 tss->ip = ctxt->_eip;
38ba30ba 2917 tss->flag = ctxt->eflags;
dd856efa
AK		 2918 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2919 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2920 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2921 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2922 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2923 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2924 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2925 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2926
1aa36616
AK		 2927 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2928 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2929 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2930 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2931 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2932}
2933
2934static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2935 struct tss_segment_16 *tss)
2936{
38ba30ba 2937 int ret;
2356aaeb 2938 u8 cpl;
38ba30ba 2939
9dac77fa 2940 ctxt->_eip = tss->ip;
38ba30ba 2941 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2942 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2943 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2944 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2945 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2946 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2947 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2948 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2949 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2950
2951 /*
2952 * SDM says that segment selectors are loaded before segment
2953 * descriptors
2954 */
1aa36616
AK		 2955 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2956 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2957 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2958 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2959 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2960
2356aaeb
PB		 2961 cpl = tss->cs & 3;
2962
38ba30ba 2963 /*
fc058680 2964 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2965 * it is handled in a context of new task
2966 */
d1442d85 2967 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2968 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2969 if (ret != X86EMUL_CONTINUE)
2970 return ret;
d1442d85 2971 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2972 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2973 if (ret != X86EMUL_CONTINUE)
2974 return ret;
d1442d85 2975 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2976 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2977 if (ret != X86EMUL_CONTINUE)
2978 return ret;
d1442d85 2979 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2980 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2981 if (ret != X86EMUL_CONTINUE)
2982 return ret;
d1442d85 2983 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2984 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2985 if (ret != X86EMUL_CONTINUE)
2986 return ret;
2987
2988 return X86EMUL_CONTINUE;
2989}
2990
2991static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2992 u16 tss_selector, u16 old_tss_sel,
2993 ulong old_tss_base, struct desc_struct *new_desc)
2994{
0225fb50 2995 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2996 struct tss_segment_16 tss_seg;
2997 int ret;
bcc55cba 2998 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2999
0f65dd70 3000 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3001 &ctxt->exception);
db297e3d 3002 if (ret != X86EMUL_CONTINUE)
38ba30ba 3003 return ret;
38ba30ba 3004
7b105ca2 3005 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3006
0f65dd70 3007 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3008 &ctxt->exception);
db297e3d 3009 if (ret != X86EMUL_CONTINUE)
38ba30ba 3010 return ret;
38ba30ba 3011
0f65dd70 3012 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3013 &ctxt->exception);
db297e3d 3014 if (ret != X86EMUL_CONTINUE)
38ba30ba 3015 return ret;
38ba30ba
GN		 3016
3017 if (old_tss_sel != 0xffff) {
3018 tss_seg.prev_task_link = old_tss_sel;
3019
0f65dd70 3020 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3021 &tss_seg.prev_task_link,
3022 sizeof tss_seg.prev_task_link,
0f65dd70 3023 &ctxt->exception);
db297e3d 3024 if (ret != X86EMUL_CONTINUE)
38ba30ba 3025 return ret;
38ba30ba
GN		 3026 }
3027
7b105ca2 3028 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3029}
3030
3031static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3032 struct tss_segment_32 *tss)
3033{
5c7411e2 3034 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3035 tss->eip = ctxt->_eip;
38ba30ba 3036 tss->eflags = ctxt->eflags;
dd856efa
AK		 3037 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3038 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3039 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3040 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3041 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3042 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3043 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3044 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3045
1aa36616
AK		 3046 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3047 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3048 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3049 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3050 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3051 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3052}
3053
3054static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3055 struct tss_segment_32 *tss)
3056{
38ba30ba 3057 int ret;
2356aaeb 3058 u8 cpl;
38ba30ba 3059
7b105ca2 3060 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3061 return emulate_gp(ctxt, 0);
9dac77fa 3062 ctxt->_eip = tss->eip;
38ba30ba 3063 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3064
3065 /* General purpose registers */
dd856efa
AK		 3066 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3067 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3068 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3069 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3070 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3071 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3072 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3073 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3074
3075 /*
3076 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3077 * descriptors. This is important because CPL checks will
3078 * use CS.RPL.
38ba30ba 3079 */
1aa36616
AK		 3080 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3081 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3082 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3083 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3084 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3085 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3086 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3087
4cee4798
KW		 3088 /*
3089 * If we're switching between Protected Mode and VM86, we need to make
3090 * sure to update the mode before loading the segment descriptors so
3091 * that the selectors are interpreted correctly.
4cee4798 3092 */
2356aaeb 3093 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3094 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3095 cpl = 3;
3096 } else {
4cee4798 3097 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3098 cpl = tss->cs & 3;
3099 }
4cee4798 3100
38ba30ba
GN		 3101 /*
3102 * Now load segment descriptors. If fault happenes at this stage
3103 * it is handled in a context of new task
3104 */
d1442d85 3105 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3106 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3107 if (ret != X86EMUL_CONTINUE)
3108 return ret;
d1442d85 3109 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3110 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3111 if (ret != X86EMUL_CONTINUE)
3112 return ret;
d1442d85 3113 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3114 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3115 if (ret != X86EMUL_CONTINUE)
3116 return ret;
d1442d85 3117 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3118 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3119 if (ret != X86EMUL_CONTINUE)
3120 return ret;
d1442d85 3121 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3122 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3123 if (ret != X86EMUL_CONTINUE)
3124 return ret;
d1442d85 3125 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3126 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3127 if (ret != X86EMUL_CONTINUE)
3128 return ret;
d1442d85 3129 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3130 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3131
2f729b10 3132 return ret;
38ba30ba
GN		 3133}
3134
3135static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3136 u16 tss_selector, u16 old_tss_sel,
3137 ulong old_tss_base, struct desc_struct *new_desc)
3138{
0225fb50 3139 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3140 struct tss_segment_32 tss_seg;
3141 int ret;
bcc55cba 3142 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3143 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3144 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3145
0f65dd70 3146 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3147 &ctxt->exception);
db297e3d 3148 if (ret != X86EMUL_CONTINUE)
38ba30ba 3149 return ret;
38ba30ba 3150
7b105ca2 3151 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3152
5c7411e2
NA		 3153 /* Only GP registers and segment selectors are saved */
3154 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3155 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 3156 if (ret != X86EMUL_CONTINUE)
38ba30ba 3157 return ret;
38ba30ba 3158
0f65dd70 3159 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3160 &ctxt->exception);
db297e3d 3161 if (ret != X86EMUL_CONTINUE)
38ba30ba 3162 return ret;
38ba30ba
GN		 3163
3164 if (old_tss_sel != 0xffff) {
3165 tss_seg.prev_task_link = old_tss_sel;
3166
0f65dd70 3167 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3168 &tss_seg.prev_task_link,
3169 sizeof tss_seg.prev_task_link,
0f65dd70 3170 &ctxt->exception);
db297e3d 3171 if (ret != X86EMUL_CONTINUE)
38ba30ba 3172 return ret;
38ba30ba
GN		 3173 }
3174
7b105ca2 3175 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3176}
3177
3178static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3179 u16 tss_selector, int idt_index, int reason,
e269fb21 3180 bool has_error_code, u32 error_code)
38ba30ba 3181{
0225fb50 3182 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3183 struct desc_struct curr_tss_desc, next_tss_desc;
3184 int ret;
1aa36616 3185 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3186 ulong old_tss_base =
4bff1e86 3187 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3188 u32 desc_limit;
3db176d5 3189 ulong desc_addr, dr7;
38ba30ba
GN		 3190
3191 /* FIXME: old_tss_base == ~0 ? */
3192
e919464b 3193 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3194 if (ret != X86EMUL_CONTINUE)
3195 return ret;
e919464b 3196 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3197 if (ret != X86EMUL_CONTINUE)
3198 return ret;
3199
3200 /* FIXME: check that next_tss_desc is tss */
3201
7f3d35fd
KW		 3202 /*
3203 * Check privileges. The three cases are task switch caused by...
3204 *
3205 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3206 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3207 * 3. jmp/call to TSS/task-gate: No check is performed since the
3208 * hardware checks it before exiting.
7f3d35fd
KW		 3209 */
3210 if (reason == TASK_SWITCH_GATE) {
3211 if (idt_index != -1) {
3212 /* Software interrupts */
3213 struct desc_struct task_gate_desc;
3214 int dpl;
3215
3216 ret = read_interrupt_descriptor(ctxt, idt_index,
3217 &task_gate_desc);
3218 if (ret != X86EMUL_CONTINUE)
3219 return ret;
3220
3221 dpl = task_gate_desc.dpl;
3222 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3223 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3224 }
38ba30ba
GN		 3225 }
3226
ceffb459
GN		 3227 desc_limit = desc_limit_scaled(&next_tss_desc);
3228 if (!next_tss_desc.p ||
3229 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3230 desc_limit < 0x2b)) {
592f0858 3231 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3232 }
3233
3234 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3235 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3236 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3237 }
3238
3239 if (reason == TASK_SWITCH_IRET)
3240 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3241
3242 /* set back link to prev task only if NT bit is set in eflags
fc058680 3243 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3244 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3245 old_tss_sel = 0xffff;
3246
3247 if (next_tss_desc.type & 8)
7b105ca2 3248 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3249 old_tss_base, &next_tss_desc);
3250 else
7b105ca2 3251 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3252 old_tss_base, &next_tss_desc);
0760d448
JK		 3253 if (ret != X86EMUL_CONTINUE)
3254 return ret;
38ba30ba
GN		 3255
3256 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3257 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3258
3259 if (reason != TASK_SWITCH_IRET) {
3260 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3261 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3262 }
3263
717746e3 3264 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3265 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3266
e269fb21 3267 if (has_error_code) {
9dac77fa
AK		 3268 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3269 ctxt->lock_prefix = 0;
3270 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3271 ret = em_push(ctxt);
e269fb21
JK		 3272 }
3273
3db176d5
NA		 3274 ops->get_dr(ctxt, 7, &dr7);
3275 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3276
38ba30ba
GN		 3277 return ret;
3278}
3279
3280int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3281 u16 tss_selector, int idt_index, int reason,
e269fb21 3282 bool has_error_code, u32 error_code)
38ba30ba 3283{
38ba30ba
GN		 3284 int rc;
3285
dd856efa 3286 invalidate_registers(ctxt);
9dac77fa
AK		 3287 ctxt->_eip = ctxt->eip;
3288 ctxt->dst.type = OP_NONE;
38ba30ba 3289
7f3d35fd 3290 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3291 has_error_code, error_code);
38ba30ba 3292
dd856efa 3293 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3294 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3295 writeback_registers(ctxt);
3296 }
38ba30ba 3297
a0c0ab2f 3298 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3299}
3300
f3bd64c6
GN		 3301static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3302 struct operand *op)
a682e354 3303{
0efb0440 3304 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3305
01485a22
PB		 3306 register_address_increment(ctxt, reg, df * op->bytes);
3307 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3308}
3309
7af04fc0
AK		 3310static int em_das(struct x86_emulate_ctxt *ctxt)
3311{
7af04fc0
AK		 3312 u8 al, old_al;
3313 bool af, cf, old_cf;
3314
3315 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3316 al = ctxt->dst.val;
7af04fc0
AK		 3317
3318 old_al = al;
3319 old_cf = cf;
3320 cf = false;
3321 af = ctxt->eflags & X86_EFLAGS_AF;
3322 if ((al & 0x0f) > 9 || af) {
3323 al -= 6;
3324 cf = old_cf | (al >= 250);
3325 af = true;
3326 } else {
3327 af = false;
3328 }
3329 if (old_al > 0x99 || old_cf) {
3330 al -= 0x60;
3331 cf = true;
3332 }
3333
9dac77fa 3334 ctxt->dst.val = al;
7af04fc0 3335 /* Set PF, ZF, SF */
9dac77fa
AK		 3336 ctxt->src.type = OP_IMM;
3337 ctxt->src.val = 0;
3338 ctxt->src.bytes = 1;
158de57f 3339 fastop(ctxt, em_or);
7af04fc0
AK		 3340 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3341 if (cf)
3342 ctxt->eflags |= X86_EFLAGS_CF;
3343 if (af)
3344 ctxt->eflags |= X86_EFLAGS_AF;
3345 return X86EMUL_CONTINUE;
3346}
3347
a035d5c6
PB		 3348static int em_aam(struct x86_emulate_ctxt *ctxt)
3349{
3350 u8 al, ah;
3351
3352 if (ctxt->src.val == 0)
3353 return emulate_de(ctxt);
3354
3355 al = ctxt->dst.val & 0xff;
3356 ah = al / ctxt->src.val;
3357 al %= ctxt->src.val;
3358
3359 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3360
3361 /* Set PF, ZF, SF */
3362 ctxt->src.type = OP_IMM;
3363 ctxt->src.val = 0;
3364 ctxt->src.bytes = 1;
3365 fastop(ctxt, em_or);
3366
3367 return X86EMUL_CONTINUE;
3368}
3369
7f662273
GN		 3370static int em_aad(struct x86_emulate_ctxt *ctxt)
3371{
3372 u8 al = ctxt->dst.val & 0xff;
3373 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3374
3375 al = (al + (ah * ctxt->src.val)) & 0xff;
3376
3377 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3378
f583c29b
GN		 3379 /* Set PF, ZF, SF */
3380 ctxt->src.type = OP_IMM;
3381 ctxt->src.val = 0;
3382 ctxt->src.bytes = 1;
3383 fastop(ctxt, em_or);
7f662273
GN		 3384
3385 return X86EMUL_CONTINUE;
3386}
3387
d4ddafcd
TY		 3388static int em_call(struct x86_emulate_ctxt *ctxt)
3389{
234f3ce4 3390 int rc;
d4ddafcd
TY		 3391 long rel = ctxt->src.val;
3392
3393 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3394 rc = jmp_rel(ctxt, rel);
3395 if (rc != X86EMUL_CONTINUE)
3396 return rc;
d4ddafcd
TY		 3397 return em_push(ctxt);
3398}
3399
0ef753b8
AK		 3400static int em_call_far(struct x86_emulate_ctxt *ctxt)
3401{
0ef753b8
AK		 3402 u16 sel, old_cs;
3403 ulong old_eip;
3404 int rc;
d1442d85
NA		 3405 struct desc_struct old_desc, new_desc;
3406 const struct x86_emulate_ops *ops = ctxt->ops;
3407 int cpl = ctxt->ops->cpl(ctxt);
82268083 3408 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3409
9dac77fa 3410 old_eip = ctxt->_eip;
d1442d85 3411 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3412
9dac77fa 3413 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3414 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3415 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3416 if (rc != X86EMUL_CONTINUE)
80976dbb 3417 return rc;
0ef753b8 3418
d50eaa18 3419 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3420 if (rc != X86EMUL_CONTINUE)
3421 goto fail;
0ef753b8 3422
9dac77fa 3423 ctxt->src.val = old_cs;
4487b3b4 3424 rc = em_push(ctxt);
0ef753b8 3425 if (rc != X86EMUL_CONTINUE)
d1442d85 3426 goto fail;
0ef753b8 3427
9dac77fa 3428 ctxt->src.val = old_eip;
d1442d85
NA		 3429 rc = em_push(ctxt);
3430 /* If we failed, we tainted the memory, but the very least we should
3431 restore cs */
82268083
NA		 3432 if (rc != X86EMUL_CONTINUE) {
3433 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3434 goto fail;
82268083 3435 }
d1442d85
NA		 3436 return rc;
3437fail:
3438 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3439 ctxt->mode = prev_mode;
d1442d85
NA		 3440 return rc;
3441
0ef753b8
AK		 3442}
3443
40ece7c7
AK		 3444static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3445{
40ece7c7 3446 int rc;
234f3ce4 3447 unsigned long eip;
40ece7c7 3448
234f3ce4
NA		 3449 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3450 if (rc != X86EMUL_CONTINUE)
3451 return rc;
3452 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3453 if (rc != X86EMUL_CONTINUE)
3454 return rc;
5ad105e5 3455 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3456 return X86EMUL_CONTINUE;
3457}
3458
e4f973ae
TY		 3459static int em_xchg(struct x86_emulate_ctxt *ctxt)
3460{
e4f973ae 3461 /* Write back the register source. */
9dac77fa
AK		 3462 ctxt->src.val = ctxt->dst.val;
3463 write_register_operand(&ctxt->src);
e4f973ae
TY		 3464
3465 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3466 ctxt->dst.val = ctxt->src.orig_val;
3467 ctxt->lock_prefix = 1;
e4f973ae
TY		 3468 return X86EMUL_CONTINUE;
3469}
3470
5c82aa29
AK		 3471static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3472{
9dac77fa 3473 ctxt->dst.val = ctxt->src2.val;
4d758349 3474 return fastop(ctxt, em_imul);
5c82aa29
AK		 3475}
3476
61429142
AK		 3477static int em_cwd(struct x86_emulate_ctxt *ctxt)
3478{
9dac77fa
AK		 3479 ctxt->dst.type = OP_REG;
3480 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3481 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3482 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3483
3484 return X86EMUL_CONTINUE;
3485}
3486
48bb5d3c
AK		 3487static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3488{
48bb5d3c
AK		 3489 u64 tsc = 0;
3490
717746e3 3491 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3492 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3493 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3494 return X86EMUL_CONTINUE;
3495}
3496
222d21aa
AK		 3497static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3498{
3499 u64 pmc;
3500
dd856efa 3501 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3502 return emulate_gp(ctxt, 0);
dd856efa
AK		 3503 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3504 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3505 return X86EMUL_CONTINUE;
3506}
3507
b9eac5f4
AK		 3508static int em_mov(struct x86_emulate_ctxt *ctxt)
3509{
54cfdb3e 3510 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3511 return X86EMUL_CONTINUE;
3512}
3513
84cffe49
BP		 3514#define FFL(x) bit(X86_FEATURE_##x)
3515
3516static int em_movbe(struct x86_emulate_ctxt *ctxt)
3517{
3518 u32 ebx, ecx, edx, eax = 1;
3519 u16 tmp;
3520
3521 /*
3522 * Check MOVBE is set in the guest-visible CPUID leaf.
3523 */
3524 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3525 if (!(ecx & FFL(MOVBE)))
3526 return emulate_ud(ctxt);
3527
3528 switch (ctxt->op_bytes) {
3529 case 2:
3530 /*
3531 * From MOVBE definition: "...When the operand size is 16 bits,
3532 * the upper word of the destination register remains unchanged
3533 * ..."
3534 *
3535 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3536 * rules so we have to do the operation almost per hand.
3537 */
3538 tmp = (u16)ctxt->src.val;
3539 ctxt->dst.val &= ~0xffffUL;
3540 ctxt->dst.val |= (unsigned long)swab16(tmp);
3541 break;
3542 case 4:
3543 ctxt->dst.val = swab32((u32)ctxt->src.val);
3544 break;
3545 case 8:
3546 ctxt->dst.val = swab64(ctxt->src.val);
3547 break;
3548 default:
592f0858 3549 BUG();
84cffe49
BP		 3550 }
3551 return X86EMUL_CONTINUE;
3552}
3553
bc00f8d2
TY		 3554static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3555{
3556 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3557 return emulate_gp(ctxt, 0);
3558
3559 /* Disable writeback. */
3560 ctxt->dst.type = OP_NONE;
3561 return X86EMUL_CONTINUE;
3562}
3563
3564static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3565{
3566 unsigned long val;
3567
3568 if (ctxt->mode == X86EMUL_MODE_PROT64)
3569 val = ctxt->src.val & ~0ULL;
3570 else
3571 val = ctxt->src.val & ~0U;
3572
3573 /* #UD condition is already handled. */
3574 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3575 return emulate_gp(ctxt, 0);
3576
3577 /* Disable writeback. */
3578 ctxt->dst.type = OP_NONE;
3579 return X86EMUL_CONTINUE;
3580}
3581
e1e210b0
TY		 3582static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3583{
3584 u64 msr_data;
3585
dd856efa
AK		 3586 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3587 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3588 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3589 return emulate_gp(ctxt, 0);
3590
3591 return X86EMUL_CONTINUE;
3592}
3593
3594static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3595{
3596 u64 msr_data;
3597
dd856efa 3598 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3599 return emulate_gp(ctxt, 0);
3600
dd856efa
AK		 3601 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3602 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3603 return X86EMUL_CONTINUE;
3604}
3605
1bd5f469
TY		 3606static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3607{
9dac77fa 3608 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3609 return emulate_ud(ctxt);
3610
9dac77fa 3611 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3612 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3613 ctxt->dst.bytes = 2;
1bd5f469
TY		 3614 return X86EMUL_CONTINUE;
3615}
3616
3617static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3618{
9dac77fa 3619 u16 sel = ctxt->src.val;
1bd5f469 3620
9dac77fa 3621 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3622 return emulate_ud(ctxt);
3623
9dac77fa 3624 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3625 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3626
3627 /* Disable writeback. */
9dac77fa
AK		 3628 ctxt->dst.type = OP_NONE;
3629 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3630}
3631
a14e579f
AK		 3632static int em_lldt(struct x86_emulate_ctxt *ctxt)
3633{
3634 u16 sel = ctxt->src.val;
3635
3636 /* Disable writeback. */
3637 ctxt->dst.type = OP_NONE;
3638 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3639}
3640
80890006
AK		 3641static int em_ltr(struct x86_emulate_ctxt *ctxt)
3642{
3643 u16 sel = ctxt->src.val;
3644
3645 /* Disable writeback. */
3646 ctxt->dst.type = OP_NONE;
3647 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3648}
3649
38503911
AK		 3650static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3651{
9fa088f4
AK		 3652 int rc;
3653 ulong linear;
3654
9dac77fa 3655 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3656 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3657 ctxt->ops->invlpg(ctxt, linear);
38503911 3658 /* Disable writeback. */
9dac77fa 3659 ctxt->dst.type = OP_NONE;
38503911
AK		 3660 return X86EMUL_CONTINUE;
3661}
3662
2d04a05b
AK		 3663static int em_clts(struct x86_emulate_ctxt *ctxt)
3664{
3665 ulong cr0;
3666
3667 cr0 = ctxt->ops->get_cr(ctxt, 0);
3668 cr0 &= ~X86_CR0_TS;
3669 ctxt->ops->set_cr(ctxt, 0, cr0);
3670 return X86EMUL_CONTINUE;
3671}
3672
b34a8051 3673static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3674{
0f54a321 3675 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3676
26d05cc7
AK		 3677 if (rc != X86EMUL_CONTINUE)
3678 return rc;
3679
3680 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3681 ctxt->_eip = ctxt->eip;
26d05cc7 3682 /* Disable writeback. */
9dac77fa 3683 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3684 return X86EMUL_CONTINUE;
3685}
3686
96051572
AK		 3687static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3688 void (*get)(struct x86_emulate_ctxt *ctxt,
3689 struct desc_ptr *ptr))
3690{
3691 struct desc_ptr desc_ptr;
3692
3693 if (ctxt->mode == X86EMUL_MODE_PROT64)
3694 ctxt->op_bytes = 8;
3695 get(ctxt, &desc_ptr);
3696 if (ctxt->op_bytes == 2) {
3697 ctxt->op_bytes = 4;
3698 desc_ptr.address &= 0x00ffffff;
3699 }
3700 /* Disable writeback. */
3701 ctxt->dst.type = OP_NONE;
3702 return segmented_write(ctxt, ctxt->dst.addr.mem,
3703 &desc_ptr, 2 + ctxt->op_bytes);
3704}
3705
3706static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3707{
3708 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3709}
3710
3711static int em_sidt(struct x86_emulate_ctxt *ctxt)
3712{
3713 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3714}
3715
5b7f6a1e 3716static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3717{
26d05cc7
AK		 3718 struct desc_ptr desc_ptr;
3719 int rc;
3720
510425ff
AK		 3721 if (ctxt->mode == X86EMUL_MODE_PROT64)
3722 ctxt->op_bytes = 8;
9dac77fa 3723 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3724 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3725 ctxt->op_bytes);
26d05cc7
AK		 3726 if (rc != X86EMUL_CONTINUE)
3727 return rc;
9a9abf6b
NA		 3728 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3729 is_noncanonical_address(desc_ptr.address))
3730 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3731 if (lgdt)
3732 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3733 else
3734 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3735 /* Disable writeback. */
9dac77fa 3736 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3737 return X86EMUL_CONTINUE;
3738}
3739
5b7f6a1e
NA		 3740static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3741{
3742 return em_lgdt_lidt(ctxt, true);
3743}
3744
26d05cc7
AK		 3745static int em_lidt(struct x86_emulate_ctxt *ctxt)
3746{
5b7f6a1e 3747 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3748}
3749
3750static int em_smsw(struct x86_emulate_ctxt *ctxt)
3751{
32e94d06
NA		 3752 if (ctxt->dst.type == OP_MEM)
3753 ctxt->dst.bytes = 2;
9dac77fa 3754 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3755 return X86EMUL_CONTINUE;
3756}
3757
3758static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3759{
26d05cc7 3760 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3761 | (ctxt->src.val & 0x0f));
3762 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3763 return X86EMUL_CONTINUE;
3764}
3765
d06e03ad
TY		 3766static int em_loop(struct x86_emulate_ctxt *ctxt)
3767{
234f3ce4
NA		 3768 int rc = X86EMUL_CONTINUE;
3769
01485a22 3770 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3771 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3772 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3773 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3774
234f3ce4 3775 return rc;
d06e03ad
TY		 3776}
3777
3778static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3779{
234f3ce4
NA		 3780 int rc = X86EMUL_CONTINUE;
3781
dd856efa 3782 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3783 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3784
234f3ce4 3785 return rc;
d06e03ad
TY		 3786}
3787
d7841a4b
TY		 3788static int em_in(struct x86_emulate_ctxt *ctxt)
3789{
3790 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3791 &ctxt->dst.val))
3792 return X86EMUL_IO_NEEDED;
3793
3794 return X86EMUL_CONTINUE;
3795}
3796
3797static int em_out(struct x86_emulate_ctxt *ctxt)
3798{
3799 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3800 &ctxt->src.val, 1);
3801 /* Disable writeback. */
3802 ctxt->dst.type = OP_NONE;
3803 return X86EMUL_CONTINUE;
3804}
3805
f411e6cd
TY		 3806static int em_cli(struct x86_emulate_ctxt *ctxt)
3807{
3808 if (emulator_bad_iopl(ctxt))
3809 return emulate_gp(ctxt, 0);
3810
3811 ctxt->eflags &= ~X86_EFLAGS_IF;
3812 return X86EMUL_CONTINUE;
3813}
3814
3815static int em_sti(struct x86_emulate_ctxt *ctxt)
3816{
3817 if (emulator_bad_iopl(ctxt))
3818 return emulate_gp(ctxt, 0);
3819
3820 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3821 ctxt->eflags |= X86_EFLAGS_IF;
3822 return X86EMUL_CONTINUE;
3823}
3824
6d6eede4
AK		 3825static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3826{
3827 u32 eax, ebx, ecx, edx;
3828
dd856efa
AK		 3829 eax = reg_read(ctxt, VCPU_REGS_RAX);
3830 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3831 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3832 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3833 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3834 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3835 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3836 return X86EMUL_CONTINUE;
3837}
3838
98f73630
PB		 3839static int em_sahf(struct x86_emulate_ctxt *ctxt)
3840{
3841 u32 flags;
3842
0efb0440
NA		 3843 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3844 X86_EFLAGS_SF;
98f73630
PB		 3845 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3846
3847 ctxt->eflags &= ~0xffUL;
3848 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3849 return X86EMUL_CONTINUE;
3850}
3851
2dd7caa0
AK		 3852static int em_lahf(struct x86_emulate_ctxt *ctxt)
3853{
dd856efa
AK		 3854 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3855 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3856 return X86EMUL_CONTINUE;
3857}
3858
9299836e
AK		 3859static int em_bswap(struct x86_emulate_ctxt *ctxt)
3860{
3861 switch (ctxt->op_bytes) {
3862#ifdef CONFIG_X86_64
3863 case 8:
3864 asm("bswap %0" : "+r"(ctxt->dst.val));
3865 break;
3866#endif
3867 default:
3868 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3869 break;
3870 }
3871 return X86EMUL_CONTINUE;
3872}
3873
13e457e0
NA		 3874static int em_clflush(struct x86_emulate_ctxt *ctxt)
3875{
3876 /* emulating clflush regardless of cpuid */
3877 return X86EMUL_CONTINUE;
3878}
3879
2276b511
NA		 3880static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3881{
3882 ctxt->dst.val = (s32) ctxt->src.val;
3883 return X86EMUL_CONTINUE;
3884}
3885
283c95d0
RK		 3886static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3887{
3888 u32 eax = 1, ebx, ecx = 0, edx;
3889
3890 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3891 if (!(edx & FFL(FXSR)))
3892 return emulate_ud(ctxt);
3893
3894 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3895 return emulate_nm(ctxt);
3896
3897 /*
3898 * Don't emulate a case that should never be hit, instead of working
3899 * around a lack of fxsave64/fxrstor64 on old compilers.
3900 */
3901 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3902 return X86EMUL_UNHANDLEABLE;
3903
3904 return X86EMUL_CONTINUE;
3905}
3906
3907/*
3908 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3909 * 1) 16 bit mode
3910 * 2) 32 bit mode
3911 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3912 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3913 * save and restore
3914 * 3) 64-bit mode with REX.W prefix
3915 * - like (2), but XMM 8-15 are being saved and restored
3916 * 4) 64-bit mode without REX.W prefix
3917 * - like (3), but FIP and FDP are 64 bit
3918 *
3919 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3920 * desired result. (4) is not emulated.
3921 *
3922 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3923 * and FPU DS) should match.
3924 */
3925static int em_fxsave(struct x86_emulate_ctxt *ctxt)
3926{
3927 struct fxregs_state fx_state;
3928 size_t size;
3929 int rc;
3930
3931 rc = check_fxsr(ctxt);
3932 if (rc != X86EMUL_CONTINUE)
3933 return rc;
3934
3935 ctxt->ops->get_fpu(ctxt);
3936
3937 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
3938
3939 ctxt->ops->put_fpu(ctxt);
3940
3941 if (rc != X86EMUL_CONTINUE)
3942 return rc;
3943
3944 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)
3945 size = offsetof(struct fxregs_state, xmm_space[8 * 16/4]);
3946 else
3947 size = offsetof(struct fxregs_state, xmm_space[0]);
3948
3949 return segmented_write(ctxt, ctxt->memop.addr.mem, &fx_state, size);
3950}
3951
3952static int fxrstor_fixup(struct x86_emulate_ctxt *ctxt,
3953 struct fxregs_state *new)
3954{
3955 int rc = X86EMUL_CONTINUE;
3956 struct fxregs_state old;
3957
3958 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(old));
3959 if (rc != X86EMUL_CONTINUE)
3960 return rc;
3961
3962 /*
3963 * 64 bit host will restore XMM 8-15, which is not correct on non-64
3964 * bit guests. Load the current values in order to preserve 64 bit
3965 * XMMs after fxrstor.
3966 */
3967#ifdef CONFIG_X86_64
3968 /* XXX: accessing XMM 8-15 very awkwardly */
3969 memcpy(&new->xmm_space[8 * 16/4], &old.xmm_space[8 * 16/4], 8 * 16);
3970#endif
3971
3972 /*
3973 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but
3974 * does save and restore MXCSR.
3975 */
3976 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))
3977 memcpy(new->xmm_space, old.xmm_space, 8 * 16);
3978
3979 return rc;
3980}
3981
3982static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
3983{
3984 struct fxregs_state fx_state;
3985 int rc;
3986
3987 rc = check_fxsr(ctxt);
3988 if (rc != X86EMUL_CONTINUE)
3989 return rc;
3990
3991 rc = segmented_read(ctxt, ctxt->memop.addr.mem, &fx_state, 512);
3992 if (rc != X86EMUL_CONTINUE)
3993 return rc;
3994
3995 if (fx_state.mxcsr >> 16)
3996 return emulate_gp(ctxt, 0);
3997
3998 ctxt->ops->get_fpu(ctxt);
3999
4000 if (ctxt->mode < X86EMUL_MODE_PROT64)
4001 rc = fxrstor_fixup(ctxt, &fx_state);
4002
4003 if (rc == X86EMUL_CONTINUE)
4004 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4005
4006 ctxt->ops->put_fpu(ctxt);
4007
4008 return rc;
4009}
4010
cfec82cb
JR		 4011static bool valid_cr(int nr)
4012{
4013 switch (nr) {
4014 case 0:
4015 case 2 ... 4:
4016 case 8:
4017 return true;
4018 default:
4019 return false;
4020 }
4021}
4022
4023static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4024{
9dac77fa 4025 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4026 return emulate_ud(ctxt);
4027
4028 return X86EMUL_CONTINUE;
4029}
4030
4031static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4032{
9dac77fa
AK		 4033 u64 new_val = ctxt->src.val64;
4034 int cr = ctxt->modrm_reg;
c2ad2bb3 4035 u64 efer = 0;
cfec82cb
JR		 4036
4037 static u64 cr_reserved_bits[] = {
4038 0xffffffff00000000ULL,
4039 0, 0, 0, /* CR3 checked later */
4040 CR4_RESERVED_BITS,
4041 0, 0, 0,
4042 CR8_RESERVED_BITS,
4043 };
4044
4045 if (!valid_cr(cr))
4046 return emulate_ud(ctxt);
4047
4048 if (new_val & cr_reserved_bits[cr])
4049 return emulate_gp(ctxt, 0);
4050
4051 switch (cr) {
4052 case 0: {
c2ad2bb3 4053 u64 cr4;
cfec82cb
JR		 4054 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4055 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4056 return emulate_gp(ctxt, 0);
4057
717746e3
AK		 4058 cr4 = ctxt->ops->get_cr(ctxt, 4);
4059 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4060
4061 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4062 !(cr4 & X86_CR4_PAE))
4063 return emulate_gp(ctxt, 0);
4064
4065 break;
4066 }
4067 case 3: {
4068 u64 rsvd = 0;
4069
c2ad2bb3
AK		 4070 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4071 if (efer & EFER_LMA)
9d88fca7 4072 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 4073
4074 if (new_val & rsvd)
4075 return emulate_gp(ctxt, 0);
4076
4077 break;
4078 }
4079 case 4: {
717746e3 4080 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4081
4082 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4083 return emulate_gp(ctxt, 0);
4084
4085 break;
4086 }
4087 }
4088
4089 return X86EMUL_CONTINUE;
4090}
4091
3b88e41a
JR		 4092static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4093{
4094 unsigned long dr7;
4095
717746e3 4096 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 4097
4098 /* Check if DR7.Global_Enable is set */
4099 return dr7 & (1 << 13);
4100}
4101
4102static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4103{
9dac77fa 4104 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4105 u64 cr4;
4106
4107 if (dr > 7)
4108 return emulate_ud(ctxt);
4109
717746e3 4110 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4111 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4112 return emulate_ud(ctxt);
4113
6d2a0526
NA		 4114 if (check_dr7_gd(ctxt)) {
4115 ulong dr6;
4116
4117 ctxt->ops->get_dr(ctxt, 6, &dr6);
4118 dr6 &= ~15;
4119 dr6 |= DR6_BD | DR6_RTM;
4120 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4121 return emulate_db(ctxt);
6d2a0526 4122 }
3b88e41a
JR		 4123
4124 return X86EMUL_CONTINUE;
4125}
4126
4127static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4128{
9dac77fa
AK		 4129 u64 new_val = ctxt->src.val64;
4130 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4131
4132 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4133 return emulate_gp(ctxt, 0);
4134
4135 return check_dr_read(ctxt);
4136}
4137
01de8b09
JR		 4138static int check_svme(struct x86_emulate_ctxt *ctxt)
4139{
4140 u64 efer;
4141
717746e3 4142 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4143
4144 if (!(efer & EFER_SVME))
4145 return emulate_ud(ctxt);
4146
4147 return X86EMUL_CONTINUE;
4148}
4149
4150static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4151{
dd856efa 4152 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4153
4154 /* Valid physical address? */
d4224449 4155 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4156 return emulate_gp(ctxt, 0);
4157
4158 return check_svme(ctxt);
4159}
4160
d7eb8203
JR		 4161static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4162{
717746e3 4163 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4164
717746e3 4165 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 4166 return emulate_ud(ctxt);
4167
4168 return X86EMUL_CONTINUE;
4169}
4170
8061252e
JR		 4171static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4172{
717746e3 4173 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4174 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4175
717746e3 4176 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4177 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4178 return emulate_gp(ctxt, 0);
4179
4180 return X86EMUL_CONTINUE;
4181}
4182
f6511935
JR		 4183static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4184{
9dac77fa
AK		 4185 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4186 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4187 return emulate_gp(ctxt, 0);
4188
4189 return X86EMUL_CONTINUE;
4190}
4191
4192static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4193{
9dac77fa
AK		 4194 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4195 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4196 return emulate_gp(ctxt, 0);
4197
4198 return X86EMUL_CONTINUE;
4199}
4200
73fba5f4 4201#define D(_y) { .flags = (_y) }
d40a6898
PB		 4202#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4203#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4204 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4205#define N D(NotImpl)
01de8b09 4206#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4207#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4208#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4209#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4210#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4211#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4212#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4213#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4214#define II(_f, _e, _i) \
d40a6898 4215 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4216#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4217 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4218 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4219#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4220
8d8f4e9f 4221#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4222#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4223#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4224#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4225#define I2bvIP(_f, _e, _i, _p) \
4226 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4227
fb864fbc
AK		 4228#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4229 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4230 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4231
0f54a321
NA		 4232static const struct opcode group7_rm0[] = {
4233 N,
b34a8051 4234 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4235 N, N, N, N, N, N,
4236};
4237
fd0a0d82 4238static const struct opcode group7_rm1[] = {
1c2545be
TY		 4239 DI(SrcNone | Priv, monitor),
4240 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4241 N, N, N, N, N, N,
4242};
4243
fd0a0d82 4244static const struct opcode group7_rm3[] = {
1c2545be 4245 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4246 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4247 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4248 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4249 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4250 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4251 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4252 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4253};
6230f7fc 4254
fd0a0d82 4255static const struct opcode group7_rm7[] = {
d7eb8203 4256 N,
1c2545be 4257 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4258 N, N, N, N, N, N,
4259};
d67fc27a 4260
fd0a0d82 4261static const struct opcode group1[] = {
fb864fbc
AK		 4262 F(Lock, em_add),
4263 F(Lock | PageTable, em_or),
4264 F(Lock, em_adc),
4265 F(Lock, em_sbb),
4266 F(Lock | PageTable, em_and),
4267 F(Lock, em_sub),
4268 F(Lock, em_xor),
4269 F(NoWrite, em_cmp),
73fba5f4
AK		 4270};
4271
fd0a0d82 4272static const struct opcode group1A[] = {
ab708099 4273 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4274};
4275
007a3b54
AK		 4276static const struct opcode group2[] = {
4277 F(DstMem | ModRM, em_rol),
4278 F(DstMem | ModRM, em_ror),
4279 F(DstMem | ModRM, em_rcl),
4280 F(DstMem | ModRM, em_rcr),
4281 F(DstMem | ModRM, em_shl),
4282 F(DstMem | ModRM, em_shr),
4283 F(DstMem | ModRM, em_shl),
4284 F(DstMem | ModRM, em_sar),
4285};
4286
fd0a0d82 4287static const struct opcode group3[] = {
fb864fbc
AK		 4288 F(DstMem | SrcImm | NoWrite, em_test),
4289 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4290 F(DstMem | SrcNone | Lock, em_not),
4291 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4292 F(DstXacc | Src2Mem, em_mul_ex),
4293 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4294 F(DstXacc | Src2Mem, em_div_ex),
4295 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4296};
4297
fd0a0d82 4298static const struct opcode group4[] = {
95413dc4
AK		 4299 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4300 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4301 N, N, N, N, N, N,
4302};
4303
fd0a0d82 4304static const struct opcode group5[] = {
95413dc4
AK		 4305 F(DstMem | SrcNone | Lock, em_inc),
4306 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4307 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4308 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4309 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 4310 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
4311 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 4312};
4313
fd0a0d82 4314static const struct opcode group6[] = {
63ea0a49
NA		 4315 DI(Prot | DstMem, sldt),
4316 DI(Prot | DstMem, str),
a14e579f 4317 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4318 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4319 N, N, N, N,
4320};
4321
fd0a0d82 4322static const struct group_dual group7 = { {
606b1c3e
NA		 4323 II(Mov | DstMem, em_sgdt, sgdt),
4324 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4325 II(SrcMem | Priv, em_lgdt, lgdt),
4326 II(SrcMem | Priv, em_lidt, lidt),
4327 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4328 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4329 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4330}, {
0f54a321 4331 EXT(0, group7_rm0),
5ef39c71 4332 EXT(0, group7_rm1),
01de8b09 4333 N, EXT(0, group7_rm3),
1c2545be
TY		 4334 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4335 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4336 EXT(0, group7_rm7),
73fba5f4
AK		 4337} };
4338
fd0a0d82 4339static const struct opcode group8[] = {
73fba5f4 4340 N, N, N, N,
11c363ba
AK		 4341 F(DstMem | SrcImmByte | NoWrite, em_bt),
4342 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4343 F(DstMem | SrcImmByte | Lock, em_btr),
4344 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4345};
4346
fd0a0d82 4347static const struct group_dual group9 = { {
1c2545be 4348 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 4349}, {
4350 N, N, N, N, N, N, N, N,
4351} };
4352
fd0a0d82 4353static const struct opcode group11[] = {
1c2545be 4354 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4355 X7(D(Undefined)),
a4d4a7c1
AK		 4356};
4357
13e457e0 4358static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 4359 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 4360};
4361
4362static const struct group_dual group15 = { {
283c95d0
RK		 4363 I(ModRM | Aligned16, em_fxsave),
4364 I(ModRM | Aligned16, em_fxrstor),
4365 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4366}, {
4367 N, N, N, N, N, N, N, N,
4368} };
4369
fd0a0d82 4370static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4371 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4372};
4373
39f062ff
NA		 4374static const struct instr_dual instr_dual_0f_2b = {
4375 I(0, em_mov), N
4376};
4377
d5b77069 4378static const struct gprefix pfx_0f_2b = {
39f062ff 4379 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4380};
4381
27ce8258 4382static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4383 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4384};
4385
0a37027e
AW		 4386static const struct gprefix pfx_0f_e7 = {
4387 N, I(Sse, em_mov), N, N,
4388};
4389
045a282c 4390static const struct escape escape_d9 = { {
16bebefe 4391 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4392}, {
4393 /* 0xC0 - 0xC7 */
4394 N, N, N, N, N, N, N, N,
4395 /* 0xC8 - 0xCF */
4396 N, N, N, N, N, N, N, N,
4397 /* 0xD0 - 0xC7 */
4398 N, N, N, N, N, N, N, N,
4399 /* 0xD8 - 0xDF */
4400 N, N, N, N, N, N, N, N,
4401 /* 0xE0 - 0xE7 */
4402 N, N, N, N, N, N, N, N,
4403 /* 0xE8 - 0xEF */
4404 N, N, N, N, N, N, N, N,
4405 /* 0xF0 - 0xF7 */
4406 N, N, N, N, N, N, N, N,
4407 /* 0xF8 - 0xFF */
4408 N, N, N, N, N, N, N, N,
4409} };
4410
4411static const struct escape escape_db = { {
4412 N, N, N, N, N, N, N, N,
4413}, {
4414 /* 0xC0 - 0xC7 */
4415 N, N, N, N, N, N, N, N,
4416 /* 0xC8 - 0xCF */
4417 N, N, N, N, N, N, N, N,
4418 /* 0xD0 - 0xC7 */
4419 N, N, N, N, N, N, N, N,
4420 /* 0xD8 - 0xDF */
4421 N, N, N, N, N, N, N, N,
4422 /* 0xE0 - 0xE7 */
4423 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4424 /* 0xE8 - 0xEF */
4425 N, N, N, N, N, N, N, N,
4426 /* 0xF0 - 0xF7 */
4427 N, N, N, N, N, N, N, N,
4428 /* 0xF8 - 0xFF */
4429 N, N, N, N, N, N, N, N,
4430} };
4431
4432static const struct escape escape_dd = { {
16bebefe 4433 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4434}, {
4435 /* 0xC0 - 0xC7 */
4436 N, N, N, N, N, N, N, N,
4437 /* 0xC8 - 0xCF */
4438 N, N, N, N, N, N, N, N,
4439 /* 0xD0 - 0xC7 */
4440 N, N, N, N, N, N, N, N,
4441 /* 0xD8 - 0xDF */
4442 N, N, N, N, N, N, N, N,
4443 /* 0xE0 - 0xE7 */
4444 N, N, N, N, N, N, N, N,
4445 /* 0xE8 - 0xEF */
4446 N, N, N, N, N, N, N, N,
4447 /* 0xF0 - 0xF7 */
4448 N, N, N, N, N, N, N, N,
4449 /* 0xF8 - 0xFF */
4450 N, N, N, N, N, N, N, N,
4451} };
4452
39f062ff
NA		 4453static const struct instr_dual instr_dual_0f_c3 = {
4454 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4455};
4456
2276b511
NA		 4457static const struct mode_dual mode_dual_63 = {
4458 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4459};
4460
fd0a0d82 4461static const struct opcode opcode_table[256] = {
73fba5f4 4462 /* 0x00 - 0x07 */
fb864fbc 4463 F6ALU(Lock, em_add),
1cd196ea
AK		 4464 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4465 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4466 /* 0x08 - 0x0F */
fb864fbc 4467 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4468 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4469 N,
73fba5f4 4470 /* 0x10 - 0x17 */
fb864fbc 4471 F6ALU(Lock, em_adc),
1cd196ea
AK		 4472 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4473 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4474 /* 0x18 - 0x1F */
fb864fbc 4475 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4476 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4477 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4478 /* 0x20 - 0x27 */
fb864fbc 4479 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4480 /* 0x28 - 0x2F */
fb864fbc 4481 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4482 /* 0x30 - 0x37 */
fb864fbc 4483 F6ALU(Lock, em_xor), N, N,
73fba5f4 4484 /* 0x38 - 0x3F */
fb864fbc 4485 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4486 /* 0x40 - 0x4F */
95413dc4 4487 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4488 /* 0x50 - 0x57 */
63540382 4489 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4490 /* 0x58 - 0x5F */
c54fe504 4491 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4492 /* 0x60 - 0x67 */
b96a7fad
TY		 4493 I(ImplicitOps | Stack | No64, em_pusha),
4494 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4495 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4496 N, N, N, N,
4497 /* 0x68 - 0x6F */
d46164db
AK		 4498 I(SrcImm | Mov | Stack, em_push),
4499 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4500 I(SrcImmByte | Mov | Stack, em_push),
4501 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4502 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4503 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4504 /* 0x70 - 0x7F */
58b7075d 4505 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4506 /* 0x80 - 0x87 */
1c2545be
TY		 4507 G(ByteOp | DstMem | SrcImm, group1),
4508 G(DstMem | SrcImm, group1),
4509 G(ByteOp | DstMem | SrcImm | No64, group1),
4510 G(DstMem | SrcImmByte, group1),
fb864fbc 4511 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4512 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4513 /* 0x88 - 0x8F */
d5ae7ce8 4514 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4515 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4516 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4517 D(ModRM | SrcMem | NoAccess | DstReg),
4518 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4519 G(0, group1A),
73fba5f4 4520 /* 0x90 - 0x97 */
bf608f88 4521 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4522 /* 0x98 - 0x9F */
61429142 4523 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4524 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4525 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4526 II(ImplicitOps | Stack, em_popf, popf),
4527 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4528 /* 0xA0 - 0xA7 */
b9eac5f4 4529 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4530 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4531 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4532 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4533 /* 0xA8 - 0xAF */
fb864fbc 4534 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4535 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4536 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4537 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4538 /* 0xB0 - 0xB7 */
b9eac5f4 4539 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4540 /* 0xB8 - 0xBF */
5e2c6883 4541 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4542 /* 0xC0 - 0xC7 */
007a3b54 4543 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4544 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4545 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4546 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4547 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4548 G(ByteOp, group11), G(0, group11),
73fba5f4 4549 /* 0xC8 - 0xCF */
612e89f0 4550 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4551 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4552 I(ImplicitOps, em_ret_far),
3c6e276f 4553 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4554 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4555 /* 0xD0 - 0xD7 */
007a3b54
AK		 4556 G(Src2One | ByteOp, group2), G(Src2One, group2),
4557 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4558 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4559 I(DstAcc | SrcImmUByte | No64, em_aad),
4560 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4561 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4562 /* 0xD8 - 0xDF */
045a282c 4563 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4564 /* 0xE0 - 0xE7 */
58b7075d
NA		 4565 X3(I(SrcImmByte | NearBranch, em_loop)),
4566 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4567 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4568 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4569 /* 0xE8 - 0xEF */
58b7075d
NA		 4570 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4571 I(SrcImmFAddr | No64, em_jmp_far),
4572 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4573 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4574 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4575 /* 0xF0 - 0xF7 */
bf608f88 4576 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4577 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4578 G(ByteOp, group3), G(0, group3),
73fba5f4 4579 /* 0xF8 - 0xFF */
f411e6cd
TY		 4580 D(ImplicitOps), D(ImplicitOps),
4581 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4582 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4583};
4584
fd0a0d82 4585static const struct opcode twobyte_table[256] = {
73fba5f4 4586 /* 0x00 - 0x0F */
dee6bb70 4587 G(0, group6), GD(0, &group7), N, N,
b51e974f 4588 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4589 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4590 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4591 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4592 /* 0x10 - 0x1F */
103f98ea 4593 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4594 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4595 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4596 /* 0x20 - 0x2F */
9b88ae99
NA		 4597 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4598 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4599 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4600 check_cr_write),
4601 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4602 check_dr_write),
73fba5f4 4603 N, N, N, N,
27ce8258
IM		 4604 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4605 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4606 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4607 N, N, N, N,
73fba5f4 4608 /* 0x30 - 0x3F */
e1e210b0 4609 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4610 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4611 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4612 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4613 I(ImplicitOps | EmulateOnUD, em_sysenter),
4614 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4615 N, N,
73fba5f4
AK		 4616 N, N, N, N, N, N, N, N,
4617 /* 0x40 - 0x4F */
140bad89 4618 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4619 /* 0x50 - 0x5F */
4620 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4621 /* 0x60 - 0x6F */
aa97bb48
AK		 4622 N, N, N, N,
4623 N, N, N, N,
4624 N, N, N, N,
4625 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4626 /* 0x70 - 0x7F */
aa97bb48
AK		 4627 N, N, N, N,
4628 N, N, N, N,
4629 N, N, N, N,
4630 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4631 /* 0x80 - 0x8F */
58b7075d 4632 X16(D(SrcImm | NearBranch)),
73fba5f4 4633 /* 0x90 - 0x9F */
ee45b58e 4634 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4635 /* 0xA0 - 0xA7 */
1cd196ea 4636 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4637 II(ImplicitOps, em_cpuid, cpuid),
4638 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4639 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4640 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4641 /* 0xA8 - 0xAF */
1cd196ea 4642 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4643 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4644 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4645 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4646 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4647 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4648 /* 0xB0 - 0xB7 */
2fcf5c8a 4649 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4650 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4651 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4652 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4653 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4654 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4655 /* 0xB8 - 0xBF */
4656 N, N,
ce7faab2 4657 G(BitOp, group8),
11c363ba 4658 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4659 I(DstReg | SrcMem | ModRM, em_bsf_c),
4660 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4661 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4662 /* 0xC0 - 0xC7 */
e47a5f5f 4663 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4664 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4665 N, N, N, GD(0, &group9),
9299836e
AK		 4666 /* 0xC8 - 0xCF */
4667 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4668 /* 0xD0 - 0xDF */
4669 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4670 /* 0xE0 - 0xEF */
0a37027e
AW		 4671 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4672 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4673 /* 0xF0 - 0xFF */
4674 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4675};
4676
39f062ff
NA		 4677static const struct instr_dual instr_dual_0f_38_f0 = {
4678 I(DstReg | SrcMem | Mov, em_movbe), N
4679};
4680
4681static const struct instr_dual instr_dual_0f_38_f1 = {
4682 I(DstMem | SrcReg | Mov, em_movbe), N
4683};
4684
0bc5eedb 4685static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4686 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4687};
4688
4689static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4690 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4691};
4692
4693/*
4694 * Insns below are selected by the prefix which indexed by the third opcode
4695 * byte.
4696 */
4697static const struct opcode opcode_map_0f_38[256] = {
4698 /* 0x00 - 0x7f */
4699 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4700 /* 0x80 - 0xef */
4701 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4702 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4703 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4704 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4705 /* 0xf2 - 0xff */
4706 N, N, X4(N), X8(N)
0bc5eedb
BP		 4707};
4708
73fba5f4
AK		 4709#undef D
4710#undef N
4711#undef G
4712#undef GD
4713#undef I
aa97bb48 4714#undef GP
01de8b09 4715#undef EXT
2276b511 4716#undef MD
2b42fce6 4717#undef ID
73fba5f4 4718
8d8f4e9f 4719#undef D2bv
f6511935 4720#undef D2bvIP
8d8f4e9f 4721#undef I2bv
d7841a4b 4722#undef I2bvIP
d67fc27a 4723#undef I6ALU
8d8f4e9f 4724
9dac77fa 4725static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4726{
4727 unsigned size;
4728
9dac77fa 4729 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4730 if (size == 8)
4731 size = 4;
4732 return size;
4733}
4734
4735static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4736 unsigned size, bool sign_extension)
4737{
39f21ee5
AK		 4738 int rc = X86EMUL_CONTINUE;
4739
4740 op->type = OP_IMM;
4741 op->bytes = size;
9dac77fa 4742 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4743 /* NB. Immediates are sign-extended as necessary. */
4744 switch (op->bytes) {
4745 case 1:
e85a1085 4746 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4747 break;
4748 case 2:
e85a1085 4749 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4750 break;
4751 case 4:
e85a1085 4752 op->val = insn_fetch(s32, ctxt);
39f21ee5 4753 break;
5e2c6883
NA		 4754 case 8:
4755 op->val = insn_fetch(s64, ctxt);
4756 break;
39f21ee5
AK		 4757 }
4758 if (!sign_extension) {
4759 switch (op->bytes) {
4760 case 1:
4761 op->val &= 0xff;
4762 break;
4763 case 2:
4764 op->val &= 0xffff;
4765 break;
4766 case 4:
4767 op->val &= 0xffffffff;
4768 break;
4769 }
4770 }
4771done:
4772 return rc;
4773}
4774
a9945549
AK		 4775static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4776 unsigned d)
4777{
4778 int rc = X86EMUL_CONTINUE;
4779
4780 switch (d) {
4781 case OpReg:
2adb5ad9 4782 decode_register_operand(ctxt, op);
a9945549
AK		 4783 break;
4784 case OpImmUByte:
608aabe3 4785 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4786 break;
4787 case OpMem:
41ddf978 4788 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4789 mem_common:
4790 *op = ctxt->memop;
4791 ctxt->memopp = op;
96888977 4792 if (ctxt->d & BitOp)
a9945549
AK		 4793 fetch_bit_operand(ctxt);
4794 op->orig_val = op->val;
4795 break;
41ddf978 4796 case OpMem64:
aaa05f24 4797 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4798 goto mem_common;
a9945549
AK		 4799 case OpAcc:
4800 op->type = OP_REG;
4801 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4802 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4803 fetch_register_operand(op);
4804 op->orig_val = op->val;
4805 break;
820207c8
AK		 4806 case OpAccLo:
4807 op->type = OP_REG;
4808 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4809 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4810 fetch_register_operand(op);
4811 op->orig_val = op->val;
4812 break;
4813 case OpAccHi:
4814 if (ctxt->d & ByteOp) {
4815 op->type = OP_NONE;
4816 break;
4817 }
4818 op->type = OP_REG;
4819 op->bytes = ctxt->op_bytes;
4820 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4821 fetch_register_operand(op);
4822 op->orig_val = op->val;
4823 break;
a9945549
AK		 4824 case OpDI:
4825 op->type = OP_MEM;
4826 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4827 op->addr.mem.ea =
01485a22 4828 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4829 op->addr.mem.seg = VCPU_SREG_ES;
4830 op->val = 0;
b3356bf0 4831 op->count = 1;
a9945549
AK		 4832 break;
4833 case OpDX:
4834 op->type = OP_REG;
4835 op->bytes = 2;
dd856efa 4836 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4837 fetch_register_operand(op);
4838 break;
4dd6a57d 4839 case OpCL:
d29b9d7e 4840 op->type = OP_IMM;
4dd6a57d 4841 op->bytes = 1;
dd856efa 4842 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4843 break;
4844 case OpImmByte:
4845 rc = decode_imm(ctxt, op, 1, true);
4846 break;
4847 case OpOne:
d29b9d7e 4848 op->type = OP_IMM;
4dd6a57d
AK		 4849 op->bytes = 1;
4850 op->val = 1;
4851 break;
4852 case OpImm:
4853 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4854 break;
5e2c6883
NA		 4855 case OpImm64:
4856 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4857 break;
28867cee
AK		 4858 case OpMem8:
4859 ctxt->memop.bytes = 1;
660696d1 4860 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4861 ctxt->memop.addr.reg = decode_register(ctxt,
4862 ctxt->modrm_rm, true);
660696d1
GN		 4863 fetch_register_operand(&ctxt->memop);
4864 }
28867cee 4865 goto mem_common;
0fe59128
AK		 4866 case OpMem16:
4867 ctxt->memop.bytes = 2;
4868 goto mem_common;
4869 case OpMem32:
4870 ctxt->memop.bytes = 4;
4871 goto mem_common;
4872 case OpImmU16:
4873 rc = decode_imm(ctxt, op, 2, false);
4874 break;
4875 case OpImmU:
4876 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4877 break;
4878 case OpSI:
4879 op->type = OP_MEM;
4880 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4881 op->addr.mem.ea =
01485a22 4882 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4883 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4884 op->val = 0;
b3356bf0 4885 op->count = 1;
0fe59128 4886 break;
7fa57952
PB		 4887 case OpXLat:
4888 op->type = OP_MEM;
4889 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4890 op->addr.mem.ea =
01485a22 4891 address_mask(ctxt,
7fa57952
PB		 4892 reg_read(ctxt, VCPU_REGS_RBX) +
4893 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4894 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4895 op->val = 0;
4896 break;
0fe59128
AK		 4897 case OpImmFAddr:
4898 op->type = OP_IMM;
4899 op->addr.mem.ea = ctxt->_eip;
4900 op->bytes = ctxt->op_bytes + 2;
4901 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4902 break;
4903 case OpMemFAddr:
4904 ctxt->memop.bytes = ctxt->op_bytes + 2;
4905 goto mem_common;
c191a7a0 4906 case OpES:
d29b9d7e 4907 op->type = OP_IMM;
c191a7a0
AK		 4908 op->val = VCPU_SREG_ES;
4909 break;
4910 case OpCS:
d29b9d7e 4911 op->type = OP_IMM;
c191a7a0
AK		 4912 op->val = VCPU_SREG_CS;
4913 break;
4914 case OpSS:
d29b9d7e 4915 op->type = OP_IMM;
c191a7a0
AK		 4916 op->val = VCPU_SREG_SS;
4917 break;
4918 case OpDS:
d29b9d7e 4919 op->type = OP_IMM;
c191a7a0
AK		 4920 op->val = VCPU_SREG_DS;
4921 break;
4922 case OpFS:
d29b9d7e 4923 op->type = OP_IMM;
c191a7a0
AK		 4924 op->val = VCPU_SREG_FS;
4925 break;
4926 case OpGS:
d29b9d7e 4927 op->type = OP_IMM;
c191a7a0
AK		 4928 op->val = VCPU_SREG_GS;
4929 break;
a9945549
AK		 4930 case OpImplicit:
4931 /* Special instructions do their own operand decoding. */
4932 default:
4933 op->type = OP_NONE; /* Disable writeback. */
4934 break;
4935 }
4936
4937done:
4938 return rc;
4939}
4940
ef5d75cc 4941int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4942{
dde7e6d1
AK		 4943 int rc = X86EMUL_CONTINUE;
4944 int mode = ctxt->mode;
46561646 4945 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4946 bool op_prefix = false;
573e80fe 4947 bool has_seg_override = false;
46561646 4948 struct opcode opcode;
dde7e6d1 4949
f09ed83e
AK		 4950 ctxt->memop.type = OP_NONE;
4951 ctxt->memopp = NULL;
9dac77fa 4952 ctxt->_eip = ctxt->eip;
17052f16
PB		 4953 ctxt->fetch.ptr = ctxt->fetch.data;
4954 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4955 ctxt->opcode_len = 1;
dc25e89e 4956 if (insn_len > 0)
9dac77fa 4957 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4958 else {
9506d57d 4959 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4960 if (rc != X86EMUL_CONTINUE)
4961 return rc;
4962 }
dde7e6d1
AK		 4963
4964 switch (mode) {
4965 case X86EMUL_MODE_REAL:
4966 case X86EMUL_MODE_VM86:
4967 case X86EMUL_MODE_PROT16:
4968 def_op_bytes = def_ad_bytes = 2;
4969 break;
4970 case X86EMUL_MODE_PROT32:
4971 def_op_bytes = def_ad_bytes = 4;
4972 break;
4973#ifdef CONFIG_X86_64
4974 case X86EMUL_MODE_PROT64:
4975 def_op_bytes = 4;
4976 def_ad_bytes = 8;
4977 break;
4978#endif
4979 default:
1d2887e2 4980 return EMULATION_FAILED;
dde7e6d1
AK		 4981 }
4982
9dac77fa
AK		 4983 ctxt->op_bytes = def_op_bytes;
4984 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4985
4986 /* Legacy prefixes. */
4987 for (;;) {
e85a1085 4988 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4989 case 0x66: /* operand-size override */
0d7cdee8 4990 op_prefix = true;
dde7e6d1 4991 /* switch between 2/4 bytes */
9dac77fa 4992 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4993 break;
4994 case 0x67: /* address-size override */
4995 if (mode == X86EMUL_MODE_PROT64)
4996 /* switch between 4/8 bytes */
9dac77fa 4997 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4998 else
4999 /* switch between 2/4 bytes */
9dac77fa 5000 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5001 break;
5002 case 0x26: /* ES override */
5003 case 0x2e: /* CS override */
5004 case 0x36: /* SS override */
5005 case 0x3e: /* DS override */
573e80fe
BD		 5006 has_seg_override = true;
5007 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 5008 break;
5009 case 0x64: /* FS override */
5010 case 0x65: /* GS override */
573e80fe
BD		 5011 has_seg_override = true;
5012 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 5013 break;
5014 case 0x40 ... 0x4f: /* REX */
5015 if (mode != X86EMUL_MODE_PROT64)
5016 goto done_prefixes;
9dac77fa 5017 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5018 continue;
5019 case 0xf0: /* LOCK */
9dac77fa 5020 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5021 break;
5022 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5023 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5024 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5025 break;
5026 default:
5027 goto done_prefixes;
5028 }
5029
5030 /* Any legacy prefix after a REX prefix nullifies its effect. */
5031
9dac77fa 5032 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5033 }
5034
5035done_prefixes:
5036
5037 /* REX prefix. */
9dac77fa
AK		 5038 if (ctxt->rex_prefix & 8)
5039 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5040
5041 /* Opcode byte(s). */
9dac77fa 5042 opcode = opcode_table[ctxt->b];
d3ad6243 5043 /* Two-byte opcode? */
9dac77fa 5044 if (ctxt->b == 0x0f) {
1ce19dc1 5045 ctxt->opcode_len = 2;
e85a1085 5046 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5047 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5048
5049 /* 0F_38 opcode map */
5050 if (ctxt->b == 0x38) {
5051 ctxt->opcode_len = 3;
5052 ctxt->b = insn_fetch(u8, ctxt);
5053 opcode = opcode_map_0f_38[ctxt->b];
5054 }
dde7e6d1 5055 }
9dac77fa 5056 ctxt->d = opcode.flags;
dde7e6d1 5057
9f4260e7
TY		 5058 if (ctxt->d & ModRM)
5059 ctxt->modrm = insn_fetch(u8, ctxt);
5060
7fe864dc
NA		 5061 /* vex-prefix instructions are not implemented */
5062 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5063 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5064 ctxt->d = NotImpl;
5065 }
5066
9dac77fa
AK		 5067 while (ctxt->d & GroupMask) {
5068 switch (ctxt->d & GroupMask) {
46561646 5069 case Group:
9dac77fa 5070 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5071 opcode = opcode.u.group[goffset];
5072 break;
5073 case GroupDual:
9dac77fa
AK		 5074 goffset = (ctxt->modrm >> 3) & 7;
5075 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5076 opcode = opcode.u.gdual->mod3[goffset];
5077 else
5078 opcode = opcode.u.gdual->mod012[goffset];
5079 break;
5080 case RMExt:
9dac77fa 5081 goffset = ctxt->modrm & 7;
01de8b09 5082 opcode = opcode.u.group[goffset];
46561646
AK		 5083 break;
5084 case Prefix:
9dac77fa 5085 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5086 return EMULATION_FAILED;
9dac77fa 5087 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5088 switch (simd_prefix) {
5089 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5090 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5091 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5092 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5093 }
5094 break;
045a282c
GN		 5095 case Escape:
5096 if (ctxt->modrm > 0xbf)
5097 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5098 else
5099 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5100 break;
39f062ff
NA		 5101 case InstrDual:
5102 if ((ctxt->modrm >> 6) == 3)
5103 opcode = opcode.u.idual->mod3;
5104 else
5105 opcode = opcode.u.idual->mod012;
5106 break;
2276b511
NA		 5107 case ModeDual:
5108 if (ctxt->mode == X86EMUL_MODE_PROT64)
5109 opcode = opcode.u.mdual->mode64;
5110 else
5111 opcode = opcode.u.mdual->mode32;
5112 break;
46561646 5113 default:
1d2887e2 5114 return EMULATION_FAILED;
0d7cdee8 5115 }
46561646 5116
b1ea50b2 5117 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5118 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5119 }
5120
e24186e0
PB		 5121 /* Unrecognised? */
5122 if (ctxt->d == 0)
5123 return EMULATION_FAILED;
5124
9dac77fa 5125 ctxt->execute = opcode.u.execute;
dde7e6d1 5126
3a6095a0
NA		 5127 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5128 return EMULATION_FAILED;
5129
d40a6898 5130 if (unlikely(ctxt->d &
ed9aad21
NA		 5131 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5132 No16))) {
d40a6898
PB		 5133 /*
5134 * These are copied unconditionally here, and checked unconditionally
5135 * in x86_emulate_insn.
5136 */
5137 ctxt->check_perm = opcode.check_perm;
5138 ctxt->intercept = opcode.intercept;
dde7e6d1 5139
d40a6898
PB		 5140 if (ctxt->d & NotImpl)
5141 return EMULATION_FAILED;
d867162c 5142
58b7075d
NA		 5143 if (mode == X86EMUL_MODE_PROT64) {
5144 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5145 ctxt->op_bytes = 8;
5146 else if (ctxt->d & NearBranch)
5147 ctxt->op_bytes = 8;
5148 }
7f9b4b75 5149
d40a6898
PB		 5150 if (ctxt->d & Op3264) {
5151 if (mode == X86EMUL_MODE_PROT64)
5152 ctxt->op_bytes = 8;
5153 else
5154 ctxt->op_bytes = 4;
5155 }
5156
ed9aad21
NA		 5157 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5158 ctxt->op_bytes = 4;
5159
d40a6898
PB		 5160 if (ctxt->d & Sse)
5161 ctxt->op_bytes = 16;
5162 else if (ctxt->d & Mmx)
5163 ctxt->op_bytes = 8;
5164 }
1253791d 5165
dde7e6d1 5166 /* ModRM and SIB bytes. */
9dac77fa 5167 if (ctxt->d & ModRM) {
f09ed83e 5168 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5169 if (!has_seg_override) {
5170 has_seg_override = true;
5171 ctxt->seg_override = ctxt->modrm_seg;
5172 }
9dac77fa 5173 } else if (ctxt->d & MemAbs)
f09ed83e 5174 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5175 if (rc != X86EMUL_CONTINUE)
5176 goto done;
5177
573e80fe
BD		 5178 if (!has_seg_override)
5179 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5180
573e80fe 5181 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5182
dde7e6d1
AK		 5183 /*
5184 * Decode and fetch the source operand: register, memory
5185 * or immediate.
5186 */
0fe59128 5187 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5188 if (rc != X86EMUL_CONTINUE)
5189 goto done;
5190
dde7e6d1
AK		 5191 /*
5192 * Decode and fetch the second source operand: register, memory
5193 * or immediate.
5194 */
4dd6a57d 5195 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5196 if (rc != X86EMUL_CONTINUE)
5197 goto done;
5198
dde7e6d1 5199 /* Decode and fetch the destination operand: register or memory. */
a9945549 5200 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5201
d9092f52 5202 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5203 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5204 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5205
a430c916 5206done:
1d2887e2 5207 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5208}
5209
1cb3f3ae
XG		 5210bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5211{
5212 return ctxt->d & PageTable;
5213}
5214
3e2f65d5
GN		 5215static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5216{
3e2f65d5
GN		 5217 /* The second termination condition only applies for REPE
5218 * and REPNE. Test if the repeat string operation prefix is
5219 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5220 * corresponding termination condition according to:
5221 * - if REPE/REPZ and ZF = 0 then done
5222 * - if REPNE/REPNZ and ZF = 1 then done
5223 */
9dac77fa
AK		 5224 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5225 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5226 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5227 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5228 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5229 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5230 return true;
5231
5232 return false;
5233}
5234
cbe2c9d3
AK		 5235static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5236{
aabba3c6 5237 int rc;
cbe2c9d3
AK		 5238
5239 ctxt->ops->get_fpu(ctxt);
aabba3c6 5240 rc = asm_safe("fwait");
cbe2c9d3
AK		 5241 ctxt->ops->put_fpu(ctxt);
5242
aabba3c6 5243 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5244 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5245
5246 return X86EMUL_CONTINUE;
5247}
5248
5249static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5250 struct operand *op)
5251{
5252 if (op->type == OP_MM)
5253 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5254}
5255
e28bbd44
AK		 5256static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5257{
4548f63e 5258 register void *__sp asm(_ASM_SP);
e28bbd44 5259 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5260
b9fa409b
AK		 5261 if (!(ctxt->d & ByteOp))
5262 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5263
e28bbd44 5264 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae 5265 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4548f63e 5266 [fastop]"+S"(fop), "+r"(__sp)
b8c0b6ae 5267 : "c"(ctxt->src2.val));
4548f63e 5268
e28bbd44 5269 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5270 if (!fop) /* exception is returned in fop variable */
5271 return emulate_de(ctxt);
e28bbd44
AK		 5272 return X86EMUL_CONTINUE;
5273}
dd856efa 5274
1498507a
BD		 5275void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5276{
573e80fe
BD		 5277 memset(&ctxt->rip_relative, 0,
5278 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5279
1498507a
BD		 5280 ctxt->io_read.pos = 0;
5281 ctxt->io_read.end = 0;
1498507a
BD		 5282 ctxt->mem_read.end = 0;
5283}
5284
7b105ca2 5285int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5286{
0225fb50 5287 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5288 int rc = X86EMUL_CONTINUE;
9dac77fa 5289 int saved_dst_type = ctxt->dst.type;
8b4caf66 5290
9dac77fa 5291 ctxt->mem_read.pos = 0;
310b5d30 5292
e24186e0
PB		 5293 /* LOCK prefix is allowed only with some instructions */
5294 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5295 rc = emulate_ud(ctxt);
1161624f
GN		 5296 goto done;
5297 }
5298
e24186e0 5299 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5300 rc = emulate_ud(ctxt);
d380a5e4
GN		 5301 goto done;
5302 }
5303
d40a6898
PB		 5304 if (unlikely(ctxt->d &
5305 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5306 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5307 (ctxt->d & Undefined)) {
5308 rc = emulate_ud(ctxt);
5309 goto done;
5310 }
1253791d 5311
d40a6898
PB		 5312 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5313 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5314 rc = emulate_ud(ctxt);
cbe2c9d3 5315 goto done;
d40a6898 5316 }
cbe2c9d3 5317
d40a6898
PB		 5318 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5319 rc = emulate_nm(ctxt);
c4f035c6 5320 goto done;
d40a6898 5321 }
c4f035c6 5322
d40a6898
PB		 5323 if (ctxt->d & Mmx) {
5324 rc = flush_pending_x87_faults(ctxt);
5325 if (rc != X86EMUL_CONTINUE)
5326 goto done;
5327 /*
5328 * Now that we know the fpu is exception safe, we can fetch
5329 * operands from it.
5330 */
5331 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5332 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5333 if (!(ctxt->d & Mov))
5334 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5335 }
e92805ac 5336
a584539b 5337 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5338 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5339 X86_ICPT_PRE_EXCEPT);
5340 if (rc != X86EMUL_CONTINUE)
5341 goto done;
5342 }
8ea7d6ae 5343
64a38292
NA		 5344 /* Instruction can only be executed in protected mode */
5345 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5346 rc = emulate_ud(ctxt);
5347 goto done;
5348 }
5349
d40a6898
PB		 5350 /* Privileged instruction can be executed only in CPL=0 */
5351 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5352 if (ctxt->d & PrivUD)
5353 rc = emulate_ud(ctxt);
5354 else
5355 rc = emulate_gp(ctxt, 0);
d09beabd 5356 goto done;
d40a6898 5357 }
d09beabd 5358
d40a6898 5359 /* Do instruction specific permission checks */
685bbf4a 5360 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5361 rc = ctxt->check_perm(ctxt);
5362 if (rc != X86EMUL_CONTINUE)
5363 goto done;
5364 }
5365
a584539b 5366 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5367 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5368 X86_ICPT_POST_EXCEPT);
5369 if (rc != X86EMUL_CONTINUE)
5370 goto done;
5371 }
5372
5373 if (ctxt->rep_prefix && (ctxt->d & String)) {
5374 /* All REP prefixes have the same first termination condition */
5375 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5376 string_registers_quirk(ctxt);
d40a6898 5377 ctxt->eip = ctxt->_eip;
0efb0440 5378 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5379 goto done;
5380 }
b9fa9d6b 5381 }
b9fa9d6b
AK		 5382 }
5383
9dac77fa
AK		 5384 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5385 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5386 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5387 if (rc != X86EMUL_CONTINUE)
8b4caf66 5388 goto done;
9dac77fa 5389 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5390 }
5391
9dac77fa
AK		 5392 if (ctxt->src2.type == OP_MEM) {
5393 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5394 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5395 if (rc != X86EMUL_CONTINUE)
5396 goto done;
5397 }
5398
9dac77fa 5399 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5400 goto special_insn;
5401
5402
9dac77fa 5403 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5404 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5405 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5406 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5407 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5408 if (!(ctxt->d & NoWrite) &&
5409 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5410 ctxt->exception.vector == PF_VECTOR)
5411 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5412 goto done;
c205fb7d 5413 }
038e51de 5414 }
4ff6f8e6
PB		 5415 /* Copy full 64-bit value for CMPXCHG8B. */
5416 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5417
018a98db
AK		 5418special_insn:
5419
a584539b 5420 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5421 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5422 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5423 if (rc != X86EMUL_CONTINUE)
5424 goto done;
5425 }
5426
b9a1ecb9 5427 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5428 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5429 else
0efb0440 5430 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5431
9dac77fa 5432 if (ctxt->execute) {
e28bbd44
AK		 5433 if (ctxt->d & Fastop) {
5434 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5435 rc = fastop(ctxt, fop);
5436 if (rc != X86EMUL_CONTINUE)
5437 goto done;
5438 goto writeback;
5439 }
9dac77fa 5440 rc = ctxt->execute(ctxt);
ef65c889
AK		 5441 if (rc != X86EMUL_CONTINUE)
5442 goto done;
5443 goto writeback;
5444 }
5445
1ce19dc1 5446 if (ctxt->opcode_len == 2)
6aa8b732 5447 goto twobyte_insn;
0bc5eedb
BP		 5448 else if (ctxt->opcode_len == 3)
5449 goto threebyte_insn;
6aa8b732 5450
9dac77fa 5451 switch (ctxt->b) {
b2833e3c 5452 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5453 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5454 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5455 break;
7e0b54b1 5456 case 0x8d: /* lea r16/r32, m */
9dac77fa 5457 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5458 break;
3d9e77df 5459 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5460 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5461 ctxt->dst.type = OP_NONE;
5462 else
5463 rc = em_xchg(ctxt);
e4f973ae 5464 break;
e8b6fa70 5465 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5466 switch (ctxt->op_bytes) {
5467 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5468 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5469 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5470 }
5471 break;
6e154e56 5472 case 0xcc: /* int3 */
5c5df76b
TY		 5473 rc = emulate_int(ctxt, 3);
5474 break;
6e154e56 5475 case 0xcd: /* int n */
9dac77fa 5476 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5477 break;
5478 case 0xce: /* into */
0efb0440 5479 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5480 rc = emulate_int(ctxt, 4);
6e154e56 5481 break;
1a52e051 5482 case 0xe9: /* jmp rel */
db5b0762 5483 case 0xeb: /* jmp rel short */
234f3ce4 5484 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5485 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5486 break;
111de5d6 5487 case 0xf4: /* hlt */
6c3287f7 5488 ctxt->ops->halt(ctxt);
19fdfa0d 5489 break;
111de5d6
AK		 5490 case 0xf5: /* cmc */
5491 /* complement carry flag from eflags reg */
0efb0440 5492 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5493 break;
5494 case 0xf8: /* clc */
0efb0440 5495 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5496 break;
8744aa9a 5497 case 0xf9: /* stc */
0efb0440 5498 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5499 break;
fb4616f4 5500 case 0xfc: /* cld */
0efb0440 5501 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5502 break;
5503 case 0xfd: /* std */
0efb0440 5504 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5505 break;
91269b8f
AK		 5506 default:
5507 goto cannot_emulate;
6aa8b732 5508 }
018a98db 5509
7d9ddaed
AK		 5510 if (rc != X86EMUL_CONTINUE)
5511 goto done;
5512
018a98db 5513writeback:
fb32b1ed
AK		 5514 if (ctxt->d & SrcWrite) {
5515 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5516 rc = writeback(ctxt, &ctxt->src);
5517 if (rc != X86EMUL_CONTINUE)
5518 goto done;
5519 }
ee212297
NA		 5520 if (!(ctxt->d & NoWrite)) {
5521 rc = writeback(ctxt, &ctxt->dst);
5522 if (rc != X86EMUL_CONTINUE)
5523 goto done;
5524 }
018a98db 5525
5cd21917
GN		 5526 /*
5527 * restore dst type in case the decoding will be reused
5528 * (happens for string instruction )
5529 */
9dac77fa 5530 ctxt->dst.type = saved_dst_type;
5cd21917 5531
9dac77fa 5532 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5533 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5534
9dac77fa 5535 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5536 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5537
9dac77fa 5538 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5539 unsigned int count;
9dac77fa 5540 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5541 if ((ctxt->d & SrcMask) == SrcSI)
5542 count = ctxt->src.count;
5543 else
5544 count = ctxt->dst.count;
01485a22 5545 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5546
d2ddd1c4
GN		 5547 if (!string_insn_completed(ctxt)) {
5548 /*
5549 * Re-enter guest when pio read ahead buffer is empty
5550 * or, if it is not used, after each 1024 iteration.
5551 */
dd856efa 5552 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5553 (r->end == 0 || r->end != r->pos)) {
5554 /*
5555 * Reset read cache. Usually happens before
5556 * decode, but since instruction is restarted
5557 * we have to do it here.
5558 */
9dac77fa 5559 ctxt->mem_read.end = 0;
dd856efa 5560 writeback_registers(ctxt);
d2ddd1c4
GN		 5561 return EMULATION_RESTART;
5562 }
5563 goto done; /* skip rip writeback */
0fa6ccbd 5564 }
0efb0440 5565 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5566 }
d2ddd1c4 5567
9dac77fa 5568 ctxt->eip = ctxt->_eip;
018a98db
AK		 5569
5570done:
e0ad0b47
PB		 5571 if (rc == X86EMUL_PROPAGATE_FAULT) {
5572 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5573 ctxt->have_exception = true;
e0ad0b47 5574 }
775fde86
JR		 5575 if (rc == X86EMUL_INTERCEPTED)
5576 return EMULATION_INTERCEPTED;
5577
dd856efa
AK		 5578 if (rc == X86EMUL_CONTINUE)
5579 writeback_registers(ctxt);
5580
d2ddd1c4 5581 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5582
5583twobyte_insn:
9dac77fa 5584 switch (ctxt->b) {
018a98db 5585 case 0x09: /* wbinvd */
cfb22375 5586 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5587 break;
5588 case 0x08: /* invd */
018a98db
AK		 5589 case 0x0d: /* GrpP (prefetch) */
5590 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5591 case 0x1f: /* nop */
018a98db
AK		 5592 break;
5593 case 0x20: /* mov cr, reg */
9dac77fa 5594 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5595 break;
6aa8b732 5596 case 0x21: /* mov from dr to reg */
9dac77fa 5597 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5598 break;
6aa8b732 5599 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5600 if (test_cc(ctxt->b, ctxt->eflags))
5601 ctxt->dst.val = ctxt->src.val;
b91aa14d 5602 else if (ctxt->op_bytes != 4)
9dac77fa 5603 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5604 break;
b2833e3c 5605 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5606 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5607 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5608 break;
ee45b58e 5609 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5610 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5611 break;
6aa8b732 5612 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5613 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5614 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5615 : (u16) ctxt->src.val;
6aa8b732 5616 break;
6aa8b732 5617 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5618 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5619 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5620 (s16) ctxt->src.val;
6aa8b732 5621 break;
91269b8f
AK		 5622 default:
5623 goto cannot_emulate;
6aa8b732 5624 }
7d9ddaed 5625
0bc5eedb
BP		 5626threebyte_insn:
5627
7d9ddaed
AK		 5628 if (rc != X86EMUL_CONTINUE)
5629 goto done;
5630
6aa8b732
AK		 5631 goto writeback;
5632
5633cannot_emulate:
a0c0ab2f 5634 return EMULATION_FAILED;
6aa8b732 5635}
dd856efa
AK		 5636
5637void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5638{
5639 invalidate_registers(ctxt);
5640}
5641
5642void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5643{
5644 writeback_registers(ctxt);
5645}
Ubuntu Artful kernel mirror