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KVM: x86 emulator: Add group8 instruction decoding
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
e99f0507 36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed
MG		 78/* Misc flags */
79#define No64 (1<<28)
0dc8d10f
GT		 80/* Source 2 operand type */
81#define Src2None (0<<29)
82#define Src2CL (1<<29)
83#define Src2ImmByte (2<<29)
84#define Src2One (3<<29)
a5f868bd 85#define Src2Imm16 (4<<29)
0dc8d10f 86#define Src2Mask (7<<29)
6aa8b732 87
43bb19cd 88enum {
1d6ad207 89 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 90 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
2db2c2eb 91 Group8,
43bb19cd
AK		 92};
93
45ed60b3 94static u32 opcode_table[256] = {
6aa8b732
AK		 95 /* 0x00 - 0x07 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 98 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 99 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 100 /* 0x08 - 0x0F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 103 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
104 ImplicitOps | Stack | No64, 0,
6aa8b732
AK		 105 /* 0x10 - 0x17 */
106 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
107 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 108 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 109 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 110 /* 0x18 - 0x1F */
111 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
112 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 113 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 114 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 115 /* 0x20 - 0x27 */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 118 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 119 /* 0x28 - 0x2F */
120 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
122 0, 0, 0, 0,
123 /* 0x30 - 0x37 */
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
126 0, 0, 0, 0,
127 /* 0x38 - 0x3F */
128 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
129 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 130 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
131 0, 0,
d77a2507 132 /* 0x40 - 0x47 */
33615aa9 133 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 134 /* 0x48 - 0x4F */
33615aa9 135 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 136 /* 0x50 - 0x57 */
6e3d5dfb
AK		 137 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
138 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 139 /* 0x58 - 0x5F */
6e3d5dfb
AK		 140 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
141 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 142 /* 0x60 - 0x67 */
abcf14b5
MG		 143 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
144 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 145 0, 0, 0, 0,
146 /* 0x68 - 0x6F */
91ed7a0e 147 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 148 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
149 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 150 /* 0x70 - 0x77 */
b2833e3c
GN		 151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
152 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 153 /* 0x78 - 0x7F */
b2833e3c
GN		 154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
155 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 156 /* 0x80 - 0x87 */
1d6ad207
AK		 157 Group | Group1_80, Group | Group1_81,
158 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 159 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
160 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
161 /* 0x88 - 0x8F */
162 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
163 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 164 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 165 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 166 /* 0x90 - 0x97 */
167 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
168 /* 0x98 - 0x9F */
d8769fed 169 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 170 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 171 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 172 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
173 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 174 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
175 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 176 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 177 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
178 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
179 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 180 /* 0xB0 - 0xB7 */
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
185 /* 0xB8 - 0xBF */
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 190 /* 0xC0 - 0xC7 */
d9413cd7 191 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 192 0, ImplicitOps | Stack, 0, 0,
d9413cd7 193 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 194 /* 0xC8 - 0xCF */
e637b823 195 0, 0, 0, ImplicitOps | Stack,
d8769fed 196 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 197 /* 0xD0 - 0xD7 */
198 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
199 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
200 0, 0, 0, 0,
201 /* 0xD8 - 0xDF */
202 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 203 /* 0xE0 - 0xE7 */
a6a3034c 204 0, 0, 0, 0,
84ce66a6
GN		 205 ByteOp | SrcImmUByte, SrcImmUByte,
206 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 207 /* 0xE8 - 0xEF */
d53c4777 208 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 209 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 210 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
211 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 212 /* 0xF0 - 0xF7 */
213 0, 0, 0, 0,
7d858a19 214 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 215 /* 0xF8 - 0xFF */
b284be57 216 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 217 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 218};
219
45ed60b3 220static u32 twobyte_table[256] = {
6aa8b732 221 /* 0x00 - 0x0F */
e99f0507 222 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
651a3e29 223 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 224 /* 0x10 - 0x1F */
225 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
226 /* 0x20 - 0x2F */
227 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0,
229 /* 0x30 - 0x3F */
e99f0507
AP		 230 ImplicitOps, 0, ImplicitOps, 0,
231 ImplicitOps, ImplicitOps, 0, 0,
232 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 233 /* 0x40 - 0x47 */
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
238 /* 0x48 - 0x4F */
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
243 /* 0x50 - 0x5F */
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
245 /* 0x60 - 0x6F */
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
247 /* 0x70 - 0x7F */
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
249 /* 0x80 - 0x8F */
b2833e3c
GN		 250 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
251 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 252 /* 0x90 - 0x9F */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0xA0 - 0xA7 */
0934ac9d
MG		 255 ImplicitOps | Stack, ImplicitOps | Stack,
256 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 257 DstMem | SrcReg | Src2ImmByte | ModRM,
258 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 259 /* 0xA8 - 0xAF */
0934ac9d
MG		 260 ImplicitOps | Stack, ImplicitOps | Stack,
261 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 262 DstMem | SrcReg | Src2ImmByte | ModRM,
263 DstMem | SrcReg | Src2CL | ModRM,
264 ModRM, 0,
6aa8b732
AK		 265 /* 0xB0 - 0xB7 */
266 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 267 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 268 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
269 DstReg | SrcMem16 | ModRM | Mov,
270 /* 0xB8 - 0xBF */
2db2c2eb 271 0, 0, Group | Group8, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 272 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
273 DstReg | SrcMem16 | ModRM | Mov,
274 /* 0xC0 - 0xCF */
a012e65a
SY		 275 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
276 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 277 /* 0xD0 - 0xDF */
278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
279 /* 0xE0 - 0xEF */
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
281 /* 0xF0 - 0xFF */
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
283};
284
45ed60b3 285static u32 group_table[] = {
1d6ad207
AK		 286 [Group1_80*8] =
287 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
288 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
289 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
290 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
291 [Group1_81*8] =
292 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
293 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
294 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
295 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
296 [Group1_82*8] =
297 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
298 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
299 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
300 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
301 [Group1_83*8] =
302 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
303 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
304 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
305 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 306 [Group1A*8] =
307 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 308 [Group3_Byte*8] =
309 ByteOp | SrcImm | DstMem | ModRM, 0,
310 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
311 0, 0, 0, 0,
312 [Group3*8] =
41afa025 313 DstMem | SrcImm | ModRM, 0,
6eb06cb2 314 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 315 0, 0, 0, 0,
fd60754e
AK		 316 [Group4*8] =
317 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
318 0, 0, 0, 0, 0, 0,
319 [Group5*8] =
d19292e4
MG		 320 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
321 SrcMem | ModRM | Stack, 0,
ef46f18e 322 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 323 [Group7*8] =
324 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 325 SrcNone | ModRM | DstMem | Mov, 0,
326 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
2db2c2eb
GN		 327 [Group8*8] =
328 0, 0, 0, 0,
329 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
330 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
e09d082c
AK		 331};
332
45ed60b3 333static u32 group2_table[] = {
d95058a1 334 [Group7*8] =
fbce554e 335 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 336 SrcNone | ModRM | DstMem | Mov, 0,
337 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 338};
339
6aa8b732 340/* EFLAGS bit definitions. */
b1d86143
AP		 341#define EFLG_VM (1<<17)
342#define EFLG_RF (1<<16)
6aa8b732
AK		 343#define EFLG_OF (1<<11)
344#define EFLG_DF (1<<10)
b1d86143 345#define EFLG_IF (1<<9)
6aa8b732
AK		 346#define EFLG_SF (1<<7)
347#define EFLG_ZF (1<<6)
348#define EFLG_AF (1<<4)
349#define EFLG_PF (1<<2)
350#define EFLG_CF (1<<0)
351
352/*
353 * Instruction emulation:
354 * Most instructions are emulated directly via a fragment of inline assembly
355 * code. This allows us to save/restore EFLAGS and thus very easily pick up
356 * any modified flags.
357 */
358
05b3e0c2 359#if defined(CONFIG_X86_64)
6aa8b732
AK		 360#define _LO32 "k" /* force 32-bit operand */
361#define _STK "%%rsp" /* stack pointer */
362#elif defined(__i386__)
363#define _LO32 "" /* force 32-bit operand */
364#define _STK "%%esp" /* stack pointer */
365#endif
366
367/*
368 * These EFLAGS bits are restored from saved value during emulation, and
369 * any changes are written back to the saved value after emulation.
370 */
371#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
372
373/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 374#define _PRE_EFLAGS(_sav, _msk, _tmp) \
375 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
376 "movl %"_sav",%"_LO32 _tmp"; " \
377 "push %"_tmp"; " \
378 "push %"_tmp"; " \
379 "movl %"_msk",%"_LO32 _tmp"; " \
380 "andl %"_LO32 _tmp",("_STK"); " \
381 "pushf; " \
382 "notl %"_LO32 _tmp"; " \
383 "andl %"_LO32 _tmp",("_STK"); " \
384 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
385 "pop %"_tmp"; " \
386 "orl %"_LO32 _tmp",("_STK"); " \
387 "popf; " \
388 "pop %"_sav"; "
6aa8b732
AK		 389
390/* After executing instruction: write-back necessary bits in EFLAGS. */
391#define _POST_EFLAGS(_sav, _msk, _tmp) \
392 /* _sav |= EFLAGS & _msk; */ \
393 "pushf; " \
394 "pop %"_tmp"; " \
395 "andl %"_msk",%"_LO32 _tmp"; " \
396 "orl %"_LO32 _tmp",%"_sav"; "
397
dda96d8f
AK		 398#ifdef CONFIG_X86_64
399#define ON64(x) x
400#else
401#define ON64(x)
402#endif
403
6b7ad61f
AK		 404#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
405 do { \
406 __asm__ __volatile__ ( \
407 _PRE_EFLAGS("0", "4", "2") \
408 _op _suffix " %"_x"3,%1; " \
409 _POST_EFLAGS("0", "4", "2") \
410 : "=m" (_eflags), "=m" ((_dst).val), \
411 "=&r" (_tmp) \
412 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 413 } while (0)
6b7ad61f
AK		 414
415
6aa8b732
AK		 416/* Raw emulation: instruction has two explicit operands. */
417#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 418 do { \
419 unsigned long _tmp; \
420 \
421 switch ((_dst).bytes) { \
422 case 2: \
423 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
424 break; \
425 case 4: \
426 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
427 break; \
428 case 8: \
429 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
430 break; \
431 } \
6aa8b732
AK		 432 } while (0)
433
434#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
435 do { \
6b7ad61f 436 unsigned long _tmp; \
d77c26fc 437 switch ((_dst).bytes) { \
6aa8b732 438 case 1: \
6b7ad61f 439 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 440 break; \
441 default: \
442 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
443 _wx, _wy, _lx, _ly, _qx, _qy); \
444 break; \
445 } \
446 } while (0)
447
448/* Source operand is byte-sized and may be restricted to just %cl. */
449#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
450 __emulate_2op(_op, _src, _dst, _eflags, \
451 "b", "c", "b", "c", "b", "c", "b", "c")
452
453/* Source operand is byte, word, long or quad sized. */
454#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
455 __emulate_2op(_op, _src, _dst, _eflags, \
456 "b", "q", "w", "r", _LO32, "r", "", "r")
457
458/* Source operand is word, long or quad sized. */
459#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
460 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
461 "w", "r", _LO32, "r", "", "r")
462
d175226a
GT		 463/* Instruction has three operands and one operand is stored in ECX register */
464#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
465 do { \
466 unsigned long _tmp; \
467 _type _clv = (_cl).val; \
468 _type _srcv = (_src).val; \
469 _type _dstv = (_dst).val; \
470 \
471 __asm__ __volatile__ ( \
472 _PRE_EFLAGS("0", "5", "2") \
473 _op _suffix " %4,%1 \n" \
474 _POST_EFLAGS("0", "5", "2") \
475 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
476 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
477 ); \
478 \
479 (_cl).val = (unsigned long) _clv; \
480 (_src).val = (unsigned long) _srcv; \
481 (_dst).val = (unsigned long) _dstv; \
482 } while (0)
483
484#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
485 do { \
486 switch ((_dst).bytes) { \
487 case 2: \
488 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
489 "w", unsigned short); \
490 break; \
491 case 4: \
492 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
493 "l", unsigned int); \
494 break; \
495 case 8: \
496 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
497 "q", unsigned long)); \
498 break; \
499 } \
500 } while (0)
501
dda96d8f 502#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 503 do { \
504 unsigned long _tmp; \
505 \
dda96d8f
AK		 506 __asm__ __volatile__ ( \
507 _PRE_EFLAGS("0", "3", "2") \
508 _op _suffix " %1; " \
509 _POST_EFLAGS("0", "3", "2") \
510 : "=m" (_eflags), "+m" ((_dst).val), \
511 "=&r" (_tmp) \
512 : "i" (EFLAGS_MASK)); \
513 } while (0)
514
515/* Instruction has only one explicit operand (no source operand). */
516#define emulate_1op(_op, _dst, _eflags) \
517 do { \
d77c26fc 518 switch ((_dst).bytes) { \
dda96d8f
AK		 519 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
520 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
521 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
522 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 523 } \
524 } while (0)
525
6aa8b732
AK		 526/* Fetch next part of the instruction being emulated. */
527#define insn_fetch(_type, _size, _eip) \
528({ unsigned long _x; \
62266869 529 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 530 if (rc != 0) \
6aa8b732
AK		 531 goto done; \
532 (_eip) += (_size); \
533 (_type)_x; \
534})
535
ddcb2885
HH		 536static inline unsigned long ad_mask(struct decode_cache *c)
537{
538 return (1UL << (c->ad_bytes << 3)) - 1;
539}
540
6aa8b732 541/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 542static inline unsigned long
543address_mask(struct decode_cache *c, unsigned long reg)
544{
545 if (c->ad_bytes == sizeof(unsigned long))
546 return reg;
547 else
548 return reg & ad_mask(c);
549}
550
551static inline unsigned long
552register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
553{
554 return base + address_mask(c, reg);
555}
556
7a957275
HH		 557static inline void
558register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
559{
560 if (c->ad_bytes == sizeof(unsigned long))
561 *reg += inc;
562 else
563 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
564}
6aa8b732 565
7a957275
HH		 566static inline void jmp_rel(struct decode_cache *c, int rel)
567{
568 register_address_increment(c, &c->eip, rel);
569}
098c937b 570
7a5b56df
AK		 571static void set_seg_override(struct decode_cache *c, int seg)
572{
573 c->has_seg_override = true;
574 c->seg_override = seg;
575}
576
577static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
578{
579 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
580 return 0;
581
582 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
583}
584
585static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
586 struct decode_cache *c)
587{
588 if (!c->has_seg_override)
589 return 0;
590
591 return seg_base(ctxt, c->seg_override);
592}
593
594static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
595{
596 return seg_base(ctxt, VCPU_SREG_ES);
597}
598
599static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
600{
601 return seg_base(ctxt, VCPU_SREG_SS);
602}
603
62266869
AK		 604static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
605 struct x86_emulate_ops *ops,
606 unsigned long linear, u8 *dest)
607{
608 struct fetch_cache *fc = &ctxt->decode.fetch;
609 int rc;
610 int size;
611
612 if (linear < fc->start || linear >= fc->end) {
613 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
614 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
615 if (rc)
616 return rc;
617 fc->start = linear;
618 fc->end = linear + size;
619 }
620 *dest = fc->data[linear - fc->start];
621 return 0;
622}
623
624static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
625 struct x86_emulate_ops *ops,
626 unsigned long eip, void *dest, unsigned size)
627{
628 int rc = 0;
629
eb3c79e6
AK		 630 /* x86 instructions are limited to 15 bytes. */
631 if (eip + size - ctxt->decode.eip_orig > 15)
632 return X86EMUL_UNHANDLEABLE;
62266869
AK		 633 eip += ctxt->cs_base;
634 while (size--) {
635 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
636 if (rc)
637 return rc;
638 }
639 return 0;
640}
641
1e3c5cb0
RR		 642/*
643 * Given the 'reg' portion of a ModRM byte, and a register block, return a
644 * pointer into the block that addresses the relevant register.
645 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
646 */
647static void *decode_register(u8 modrm_reg, unsigned long *regs,
648 int highbyte_regs)
6aa8b732
AK		 649{
650 void *p;
651
652 p = &regs[modrm_reg];
653 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
654 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
655 return p;
656}
657
658static int read_descriptor(struct x86_emulate_ctxt *ctxt,
659 struct x86_emulate_ops *ops,
660 void *ptr,
661 u16 *size, unsigned long *address, int op_bytes)
662{
663 int rc;
664
665 if (op_bytes == 2)
666 op_bytes = 3;
667 *address = 0;
cebff02b
LV		 668 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
669 ctxt->vcpu);
6aa8b732
AK		 670 if (rc)
671 return rc;
cebff02b
LV		 672 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
673 ctxt->vcpu);
6aa8b732
AK		 674 return rc;
675}
676
bbe9abbd
NK		 677static int test_cc(unsigned int condition, unsigned int flags)
678{
679 int rc = 0;
680
681 switch ((condition & 15) >> 1) {
682 case 0: /* o */
683 rc |= (flags & EFLG_OF);
684 break;
685 case 1: /* b/c/nae */
686 rc |= (flags & EFLG_CF);
687 break;
688 case 2: /* z/e */
689 rc |= (flags & EFLG_ZF);
690 break;
691 case 3: /* be/na */
692 rc |= (flags & (EFLG_CF|EFLG_ZF));
693 break;
694 case 4: /* s */
695 rc |= (flags & EFLG_SF);
696 break;
697 case 5: /* p/pe */
698 rc |= (flags & EFLG_PF);
699 break;
700 case 7: /* le/ng */
701 rc |= (flags & EFLG_ZF);
702 /* fall through */
703 case 6: /* l/nge */
704 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
705 break;
706 }
707
708 /* Odd condition identifiers (lsb == 1) have inverted sense. */
709 return (!!rc ^ (condition & 1));
710}
711
3c118e24
AK		 712static void decode_register_operand(struct operand *op,
713 struct decode_cache *c,
3c118e24
AK		 714 int inhibit_bytereg)
715{
33615aa9 716 unsigned reg = c->modrm_reg;
9f1ef3f8 717 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 718
719 if (!(c->d & ModRM))
720 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 721 op->type = OP_REG;
722 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 723 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 724 op->val = *(u8 *)op->ptr;
725 op->bytes = 1;
726 } else {
33615aa9 727 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 728 op->bytes = c->op_bytes;
729 switch (op->bytes) {
730 case 2:
731 op->val = *(u16 *)op->ptr;
732 break;
733 case 4:
734 op->val = *(u32 *)op->ptr;
735 break;
736 case 8:
737 op->val = *(u64 *) op->ptr;
738 break;
739 }
740 }
741 op->orig_val = op->val;
742}
743
1c73ef66
AK		 744static int decode_modrm(struct x86_emulate_ctxt *ctxt,
745 struct x86_emulate_ops *ops)
746{
747 struct decode_cache *c = &ctxt->decode;
748 u8 sib;
f5b4edcd 749 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 750 int rc = 0;
751
752 if (c->rex_prefix) {
753 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
754 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
755 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
756 }
757
758 c->modrm = insn_fetch(u8, 1, c->eip);
759 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
760 c->modrm_reg |= (c->modrm & 0x38) >> 3;
761 c->modrm_rm |= (c->modrm & 0x07);
762 c->modrm_ea = 0;
763 c->use_modrm_ea = 1;
764
765 if (c->modrm_mod == 3) {
107d6d2e
AK		 766 c->modrm_ptr = decode_register(c->modrm_rm,
767 c->regs, c->d & ByteOp);
768 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 769 return rc;
770 }
771
772 if (c->ad_bytes == 2) {
773 unsigned bx = c->regs[VCPU_REGS_RBX];
774 unsigned bp = c->regs[VCPU_REGS_RBP];
775 unsigned si = c->regs[VCPU_REGS_RSI];
776 unsigned di = c->regs[VCPU_REGS_RDI];
777
778 /* 16-bit ModR/M decode. */
779 switch (c->modrm_mod) {
780 case 0:
781 if (c->modrm_rm == 6)
782 c->modrm_ea += insn_fetch(u16, 2, c->eip);
783 break;
784 case 1:
785 c->modrm_ea += insn_fetch(s8, 1, c->eip);
786 break;
787 case 2:
788 c->modrm_ea += insn_fetch(u16, 2, c->eip);
789 break;
790 }
791 switch (c->modrm_rm) {
792 case 0:
793 c->modrm_ea += bx + si;
794 break;
795 case 1:
796 c->modrm_ea += bx + di;
797 break;
798 case 2:
799 c->modrm_ea += bp + si;
800 break;
801 case 3:
802 c->modrm_ea += bp + di;
803 break;
804 case 4:
805 c->modrm_ea += si;
806 break;
807 case 5:
808 c->modrm_ea += di;
809 break;
810 case 6:
811 if (c->modrm_mod != 0)
812 c->modrm_ea += bp;
813 break;
814 case 7:
815 c->modrm_ea += bx;
816 break;
817 }
818 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
819 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 820 if (!c->has_seg_override)
821 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 822 c->modrm_ea = (u16)c->modrm_ea;
823 } else {
824 /* 32/64-bit ModR/M decode. */
84411d85 825 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 826 sib = insn_fetch(u8, 1, c->eip);
827 index_reg |= (sib >> 3) & 7;
828 base_reg |= sib & 7;
829 scale = sib >> 6;
830
dc71d0f1
AK		 831 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
832 c->modrm_ea += insn_fetch(s32, 4, c->eip);
833 else
1c73ef66 834 c->modrm_ea += c->regs[base_reg];
dc71d0f1 835 if (index_reg != 4)
1c73ef66 836 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 837 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
838 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 839 c->rip_relative = 1;
84411d85 840 } else
1c73ef66 841 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 842 switch (c->modrm_mod) {
843 case 0:
844 if (c->modrm_rm == 5)
845 c->modrm_ea += insn_fetch(s32, 4, c->eip);
846 break;
847 case 1:
848 c->modrm_ea += insn_fetch(s8, 1, c->eip);
849 break;
850 case 2:
851 c->modrm_ea += insn_fetch(s32, 4, c->eip);
852 break;
853 }
854 }
1c73ef66
AK		 855done:
856 return rc;
857}
858
859static int decode_abs(struct x86_emulate_ctxt *ctxt,
860 struct x86_emulate_ops *ops)
861{
862 struct decode_cache *c = &ctxt->decode;
863 int rc = 0;
864
865 switch (c->ad_bytes) {
866 case 2:
867 c->modrm_ea = insn_fetch(u16, 2, c->eip);
868 break;
869 case 4:
870 c->modrm_ea = insn_fetch(u32, 4, c->eip);
871 break;
872 case 8:
873 c->modrm_ea = insn_fetch(u64, 8, c->eip);
874 break;
875 }
876done:
877 return rc;
878}
879
6aa8b732 880int
8b4caf66 881x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 882{
e4e03ded 883 struct decode_cache *c = &ctxt->decode;
6aa8b732 884 int rc = 0;
6aa8b732 885 int mode = ctxt->mode;
e09d082c 886 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 887
888 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 889
e4e03ded 890 memset(c, 0, sizeof(struct decode_cache));
eb3c79e6 891 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
7a5b56df 892 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 893 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 894
895 switch (mode) {
896 case X86EMUL_MODE_REAL:
897 case X86EMUL_MODE_PROT16:
f21b8bf4 898 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 899 break;
900 case X86EMUL_MODE_PROT32:
f21b8bf4 901 def_op_bytes = def_ad_bytes = 4;
6aa8b732 902 break;
05b3e0c2 903#ifdef CONFIG_X86_64
6aa8b732 904 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 905 def_op_bytes = 4;
906 def_ad_bytes = 8;
6aa8b732
AK		 907 break;
908#endif
909 default:
910 return -1;
911 }
912
f21b8bf4
AK		 913 c->op_bytes = def_op_bytes;
914 c->ad_bytes = def_ad_bytes;
915
6aa8b732 916 /* Legacy prefixes. */
b4c6abfe 917 for (;;) {
e4e03ded 918 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 919 case 0x66: /* operand-size override */
f21b8bf4
AK		 920 /* switch between 2/4 bytes */
921 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 922 break;
923 case 0x67: /* address-size override */
924 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 925 /* switch between 4/8 bytes */
f21b8bf4 926 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 927 else
e4e03ded 928 /* switch between 2/4 bytes */
f21b8bf4 929 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 930 break;
7a5b56df 931 case 0x26: /* ES override */
6aa8b732 932 case 0x2e: /* CS override */
7a5b56df 933 case 0x36: /* SS override */
6aa8b732 934 case 0x3e: /* DS override */
7a5b56df 935 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 936 break;
937 case 0x64: /* FS override */
6aa8b732 938 case 0x65: /* GS override */
7a5b56df 939 set_seg_override(c, c->b & 7);
6aa8b732 940 break;
b4c6abfe
LV		 941 case 0x40 ... 0x4f: /* REX */
942 if (mode != X86EMUL_MODE_PROT64)
943 goto done_prefixes;
33615aa9 944 c->rex_prefix = c->b;
b4c6abfe 945 continue;
6aa8b732 946 case 0xf0: /* LOCK */
e4e03ded 947 c->lock_prefix = 1;
6aa8b732 948 break;
ae6200ba 949 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 950 c->rep_prefix = REPNE_PREFIX;
951 break;
6aa8b732 952 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 953 c->rep_prefix = REPE_PREFIX;
6aa8b732 954 break;
6aa8b732
AK		 955 default:
956 goto done_prefixes;
957 }
b4c6abfe
LV		 958
959 /* Any legacy prefix after a REX prefix nullifies its effect. */
960
33615aa9 961 c->rex_prefix = 0;
6aa8b732
AK		 962 }
963
964done_prefixes:
965
966 /* REX prefix. */
1c73ef66 967 if (c->rex_prefix)
33615aa9 968 if (c->rex_prefix & 8)
e4e03ded 969 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 970
971 /* Opcode byte(s). */
e4e03ded
LV		 972 c->d = opcode_table[c->b];
973 if (c->d == 0) {
6aa8b732 974 /* Two-byte opcode? */
e4e03ded
LV		 975 if (c->b == 0x0f) {
976 c->twobyte = 1;
977 c->b = insn_fetch(u8, 1, c->eip);
978 c->d = twobyte_table[c->b];
6aa8b732 979 }
e09d082c 980 }
6aa8b732 981
d8769fed
MG		 982 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
983 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
984 return -1;
985 }
986
e09d082c
AK		 987 if (c->d & Group) {
988 group = c->d & GroupMask;
989 c->modrm = insn_fetch(u8, 1, c->eip);
990 --c->eip;
991
992 group = (group << 3) + ((c->modrm >> 3) & 7);
993 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
994 c->d = group2_table[group];
995 else
996 c->d = group_table[group];
997 }
998
999 /* Unrecognised? */
1000 if (c->d == 0) {
1001 DPRINTF("Cannot emulate %02x\n", c->b);
1002 return -1;
6aa8b732
AK		 1003 }
1004
6e3d5dfb
AK		 1005 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1006 c->op_bytes = 8;
1007
6aa8b732 1008 /* ModRM and SIB bytes. */
1c73ef66
AK		 1009 if (c->d & ModRM)
1010 rc = decode_modrm(ctxt, ops);
1011 else if (c->d & MemAbs)
1012 rc = decode_abs(ctxt, ops);
1013 if (rc)
1014 goto done;
6aa8b732 1015
7a5b56df
AK		 1016 if (!c->has_seg_override)
1017 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1018
7a5b56df
AK		 1019 if (!(!c->twobyte && c->b == 0x8d))
1020 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1021
1022 if (c->ad_bytes != 8)
1023 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1024 /*
1025 * Decode and fetch the source operand: register, memory
1026 * or immediate.
1027 */
e4e03ded 1028 switch (c->d & SrcMask) {
6aa8b732
AK		 1029 case SrcNone:
1030 break;
1031 case SrcReg:
9f1ef3f8 1032 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1033 break;
1034 case SrcMem16:
e4e03ded 1035 c->src.bytes = 2;
6aa8b732
AK		 1036 goto srcmem_common;
1037 case SrcMem32:
e4e03ded 1038 c->src.bytes = 4;
6aa8b732
AK		 1039 goto srcmem_common;
1040 case SrcMem:
e4e03ded
LV		 1041 c->src.bytes = (c->d & ByteOp) ? 1 :
1042 c->op_bytes;
b85b9ee9 1043 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1044 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1045 break;
d77c26fc 1046 srcmem_common:
4e62417b
AJ		 1047 /*
1048 * For instructions with a ModR/M byte, switch to register
1049 * access if Mod = 3.
1050 */
e4e03ded
LV		 1051 if ((c->d & ModRM) && c->modrm_mod == 3) {
1052 c->src.type = OP_REG;
66b85505 1053 c->src.val = c->modrm_val;
107d6d2e 1054 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1055 break;
1056 }
e4e03ded 1057 c->src.type = OP_MEM;
6aa8b732
AK		 1058 break;
1059 case SrcImm:
c9eaf20f 1060 case SrcImmU:
e4e03ded
LV		 1061 c->src.type = OP_IMM;
1062 c->src.ptr = (unsigned long *)c->eip;
1063 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1064 if (c->src.bytes == 8)
1065 c->src.bytes = 4;
6aa8b732 1066 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1067 switch (c->src.bytes) {
6aa8b732 1068 case 1:
e4e03ded 1069 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1070 break;
1071 case 2:
e4e03ded 1072 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1073 break;
1074 case 4:
e4e03ded 1075 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1076 break;
1077 }
c9eaf20f
AK		 1078 if ((c->d & SrcMask) == SrcImmU) {
1079 switch (c->src.bytes) {
1080 case 1:
1081 c->src.val &= 0xff;
1082 break;
1083 case 2:
1084 c->src.val &= 0xffff;
1085 break;
1086 case 4:
1087 c->src.val &= 0xffffffff;
1088 break;
1089 }
1090 }
6aa8b732
AK		 1091 break;
1092 case SrcImmByte:
341de7e3 1093 case SrcImmUByte:
e4e03ded
LV		 1094 c->src.type = OP_IMM;
1095 c->src.ptr = (unsigned long *)c->eip;
1096 c->src.bytes = 1;
341de7e3
GN		 1097 if ((c->d & SrcMask) == SrcImmByte)
1098 c->src.val = insn_fetch(s8, 1, c->eip);
1099 else
1100 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1101 break;
bfcadf83
GT		 1102 case SrcOne:
1103 c->src.bytes = 1;
1104 c->src.val = 1;
1105 break;
6aa8b732
AK		 1106 }
1107
0dc8d10f
GT		 1108 /*
1109 * Decode and fetch the second source operand: register, memory
1110 * or immediate.
1111 */
1112 switch (c->d & Src2Mask) {
1113 case Src2None:
1114 break;
1115 case Src2CL:
1116 c->src2.bytes = 1;
1117 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1118 break;
1119 case Src2ImmByte:
1120 c->src2.type = OP_IMM;
1121 c->src2.ptr = (unsigned long *)c->eip;
1122 c->src2.bytes = 1;
1123 c->src2.val = insn_fetch(u8, 1, c->eip);
1124 break;
a5f868bd
GN		 1125 case Src2Imm16:
1126 c->src2.type = OP_IMM;
1127 c->src2.ptr = (unsigned long *)c->eip;
1128 c->src2.bytes = 2;
1129 c->src2.val = insn_fetch(u16, 2, c->eip);
1130 break;
0dc8d10f
GT		 1131 case Src2One:
1132 c->src2.bytes = 1;
1133 c->src2.val = 1;
1134 break;
1135 }
1136
038e51de 1137 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1138 switch (c->d & DstMask) {
038e51de
AK		 1139 case ImplicitOps:
1140 /* Special instructions do their own operand decoding. */
8b4caf66 1141 return 0;
038e51de 1142 case DstReg:
9f1ef3f8 1143 decode_register_operand(&c->dst, c,
3c118e24 1144 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1145 break;
1146 case DstMem:
e4e03ded 1147 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1148 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1149 c->dst.type = OP_REG;
66b85505 1150 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1151 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1152 break;
1153 }
8b4caf66
LV		 1154 c->dst.type = OP_MEM;
1155 break;
9c9fddd0
GT		 1156 case DstAcc:
1157 c->dst.type = OP_REG;
1158 c->dst.bytes = c->op_bytes;
1159 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1160 switch (c->op_bytes) {
1161 case 1:
1162 c->dst.val = *(u8 *)c->dst.ptr;
1163 break;
1164 case 2:
1165 c->dst.val = *(u16 *)c->dst.ptr;
1166 break;
1167 case 4:
1168 c->dst.val = *(u32 *)c->dst.ptr;
1169 break;
1170 }
1171 c->dst.orig_val = c->dst.val;
1172 break;
8b4caf66
LV		 1173 }
1174
f5b4edcd
AK		 1175 if (c->rip_relative)
1176 c->modrm_ea += c->eip;
1177
8b4caf66
LV		 1178done:
1179 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1180}
1181
8cdbd2c9
LV		 1182static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1183{
1184 struct decode_cache *c = &ctxt->decode;
1185
1186 c->dst.type = OP_MEM;
1187 c->dst.bytes = c->op_bytes;
1188 c->dst.val = c->src.val;
7a957275 1189 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1190 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1191 c->regs[VCPU_REGS_RSP]);
1192}
1193
faa5a3ae 1194static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1195 struct x86_emulate_ops *ops,
1196 void *dest, int len)
8cdbd2c9
LV		 1197{
1198 struct decode_cache *c = &ctxt->decode;
1199 int rc;
1200
781d0edc
AK		 1201 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1202 c->regs[VCPU_REGS_RSP]),
350f69dc 1203 dest, len, ctxt->vcpu);
b60d513c 1204 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1205 return rc;
1206
350f69dc 1207 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1208 return rc;
1209}
8cdbd2c9 1210
0934ac9d
MG		 1211static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1212{
1213 struct decode_cache *c = &ctxt->decode;
1214 struct kvm_segment segment;
1215
1216 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1217
1218 c->src.val = segment.selector;
1219 emulate_push(ctxt);
1220}
1221
1222static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1223 struct x86_emulate_ops *ops, int seg)
1224{
1225 struct decode_cache *c = &ctxt->decode;
1226 unsigned long selector;
1227 int rc;
1228
1229 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1230 if (rc != 0)
1231 return rc;
1232
1233 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1234 return rc;
1235}
1236
abcf14b5
MG		 1237static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1238{
1239 struct decode_cache *c = &ctxt->decode;
1240 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1241 int reg = VCPU_REGS_RAX;
1242
1243 while (reg <= VCPU_REGS_RDI) {
1244 (reg == VCPU_REGS_RSP) ?
1245 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1246
1247 emulate_push(ctxt);
1248 ++reg;
1249 }
1250}
1251
1252static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1253 struct x86_emulate_ops *ops)
1254{
1255 struct decode_cache *c = &ctxt->decode;
1256 int rc = 0;
1257 int reg = VCPU_REGS_RDI;
1258
1259 while (reg >= VCPU_REGS_RAX) {
1260 if (reg == VCPU_REGS_RSP) {
1261 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1262 c->op_bytes);
1263 --reg;
1264 }
1265
1266 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1267 if (rc != 0)
1268 break;
1269 --reg;
1270 }
1271 return rc;
1272}
1273
faa5a3ae
AK		 1274static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1275 struct x86_emulate_ops *ops)
1276{
1277 struct decode_cache *c = &ctxt->decode;
1278 int rc;
1279
350f69dc 1280 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1281 if (rc != 0)
1282 return rc;
8cdbd2c9
LV		 1283 return 0;
1284}
1285
05f086f8 1286static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1287{
05f086f8 1288 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1289 switch (c->modrm_reg) {
1290 case 0: /* rol */
05f086f8 1291 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1292 break;
1293 case 1: /* ror */
05f086f8 1294 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1295 break;
1296 case 2: /* rcl */
05f086f8 1297 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1298 break;
1299 case 3: /* rcr */
05f086f8 1300 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1301 break;
1302 case 4: /* sal/shl */
1303 case 6: /* sal/shl */
05f086f8 1304 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1305 break;
1306 case 5: /* shr */
05f086f8 1307 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1308 break;
1309 case 7: /* sar */
05f086f8 1310 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1311 break;
1312 }
1313}
1314
1315static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1316 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1317{
1318 struct decode_cache *c = &ctxt->decode;
1319 int rc = 0;
1320
1321 switch (c->modrm_reg) {
1322 case 0 ... 1: /* test */
05f086f8 1323 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1324 break;
1325 case 2: /* not */
1326 c->dst.val = ~c->dst.val;
1327 break;
1328 case 3: /* neg */
05f086f8 1329 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1330 break;
1331 default:
1332 DPRINTF("Cannot emulate %02x\n", c->b);
1333 rc = X86EMUL_UNHANDLEABLE;
1334 break;
1335 }
8cdbd2c9
LV		 1336 return rc;
1337}
1338
1339static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1340 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1341{
1342 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1343
1344 switch (c->modrm_reg) {
1345 case 0: /* inc */
05f086f8 1346 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1347 break;
1348 case 1: /* dec */
05f086f8 1349 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1350 break;
d19292e4
MG		 1351 case 2: /* call near abs */ {
1352 long int old_eip;
1353 old_eip = c->eip;
1354 c->eip = c->src.val;
1355 c->src.val = old_eip;
1356 emulate_push(ctxt);
1357 break;
1358 }
8cdbd2c9 1359 case 4: /* jmp abs */
fd60754e 1360 c->eip = c->src.val;
8cdbd2c9
LV		 1361 break;
1362 case 6: /* push */
fd60754e 1363 emulate_push(ctxt);
8cdbd2c9 1364 break;
8cdbd2c9
LV		 1365 }
1366 return 0;
1367}
1368
1369static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1370 struct x86_emulate_ops *ops,
e8d8d7fe 1371 unsigned long memop)
8cdbd2c9
LV		 1372{
1373 struct decode_cache *c = &ctxt->decode;
1374 u64 old, new;
1375 int rc;
1376
e8d8d7fe 1377 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1378 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1379 return rc;
1380
1381 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1382 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1383
1384 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1385 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1386 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1387
1388 } else {
1389 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1390 (u32) c->regs[VCPU_REGS_RBX];
1391
e8d8d7fe 1392 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1393 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1394 return rc;
05f086f8 1395 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1396 }
1397 return 0;
1398}
1399
a77ab5ea
AK		 1400static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1401 struct x86_emulate_ops *ops)
1402{
1403 struct decode_cache *c = &ctxt->decode;
1404 int rc;
1405 unsigned long cs;
1406
1407 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1408 if (rc)
1409 return rc;
1410 if (c->op_bytes == 4)
1411 c->eip = (u32)c->eip;
1412 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1413 if (rc)
1414 return rc;
1415 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1416 return rc;
1417}
1418
8cdbd2c9
LV		 1419static inline int writeback(struct x86_emulate_ctxt *ctxt,
1420 struct x86_emulate_ops *ops)
1421{
1422 int rc;
1423 struct decode_cache *c = &ctxt->decode;
1424
1425 switch (c->dst.type) {
1426 case OP_REG:
1427 /* The 4-byte case *is* correct:
1428 * in 64-bit mode we zero-extend.
1429 */
1430 switch (c->dst.bytes) {
1431 case 1:
1432 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1433 break;
1434 case 2:
1435 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1436 break;
1437 case 4:
1438 *c->dst.ptr = (u32)c->dst.val;
1439 break; /* 64b: zero-ext */
1440 case 8:
1441 *c->dst.ptr = c->dst.val;
1442 break;
1443 }
1444 break;
1445 case OP_MEM:
1446 if (c->lock_prefix)
1447 rc = ops->cmpxchg_emulated(
1448 (unsigned long)c->dst.ptr,
1449 &c->dst.orig_val,
1450 &c->dst.val,
1451 c->dst.bytes,
1452 ctxt->vcpu);
1453 else
1454 rc = ops->write_emulated(
1455 (unsigned long)c->dst.ptr,
1456 &c->dst.val,
1457 c->dst.bytes,
1458 ctxt->vcpu);
b60d513c 1459 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1460 return rc;
a01af5ec
LV		 1461 break;
1462 case OP_NONE:
1463 /* no writeback */
1464 break;
8cdbd2c9
LV		 1465 default:
1466 break;
1467 }
1468 return 0;
1469}
1470
a3f9d398 1471static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1472{
1473 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1474 /*
1475 * an sti; sti; sequence only disable interrupts for the first
1476 * instruction. So, if the last instruction, be it emulated or
1477 * not, left the system with the INT_STI flag enabled, it
1478 * means that the last instruction is an sti. We should not
1479 * leave the flag on in this case. The same goes for mov ss
1480 */
1481 if (!(int_shadow & mask))
1482 ctxt->interruptibility = mask;
1483}
1484
e66bb2cc
AP		 1485static inline void
1486setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1487 struct kvm_segment *cs, struct kvm_segment *ss)
1488{
1489 memset(cs, 0, sizeof(struct kvm_segment));
1490 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1491 memset(ss, 0, sizeof(struct kvm_segment));
1492
1493 cs->l = 0; /* will be adjusted later */
1494 cs->base = 0; /* flat segment */
1495 cs->g = 1; /* 4kb granularity */
1496 cs->limit = 0xffffffff; /* 4GB limit */
1497 cs->type = 0x0b; /* Read, Execute, Accessed */
1498 cs->s = 1;
1499 cs->dpl = 0; /* will be adjusted later */
1500 cs->present = 1;
1501 cs->db = 1;
1502
1503 ss->unusable = 0;
1504 ss->base = 0; /* flat segment */
1505 ss->limit = 0xffffffff; /* 4GB limit */
1506 ss->g = 1; /* 4kb granularity */
1507 ss->s = 1;
1508 ss->type = 0x03; /* Read/Write, Accessed */
1509 ss->db = 1; /* 32bit stack segment */
1510 ss->dpl = 0;
1511 ss->present = 1;
1512}
1513
1514static int
1515emulate_syscall(struct x86_emulate_ctxt *ctxt)
1516{
1517 struct decode_cache *c = &ctxt->decode;
1518 struct kvm_segment cs, ss;
1519 u64 msr_data;
1520
1521 /* syscall is not available in real mode */
1522 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
3eeb3288 1523 || !is_protmode(ctxt->vcpu))
e66bb2cc
AP		 1524 return -1;
1525
1526 setup_syscalls_segments(ctxt, &cs, &ss);
1527
1528 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1529 msr_data >>= 32;
1530 cs.selector = (u16)(msr_data & 0xfffc);
1531 ss.selector = (u16)(msr_data + 8);
1532
1533 if (is_long_mode(ctxt->vcpu)) {
1534 cs.db = 0;
1535 cs.l = 1;
1536 }
1537 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1538 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1539
1540 c->regs[VCPU_REGS_RCX] = c->eip;
1541 if (is_long_mode(ctxt->vcpu)) {
1542#ifdef CONFIG_X86_64
1543 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1544
1545 kvm_x86_ops->get_msr(ctxt->vcpu,
1546 ctxt->mode == X86EMUL_MODE_PROT64 ?
1547 MSR_LSTAR : MSR_CSTAR, &msr_data);
1548 c->eip = msr_data;
1549
1550 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1551 ctxt->eflags &= ~(msr_data | EFLG_RF);
1552#endif
1553 } else {
1554 /* legacy mode */
1555 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1556 c->eip = (u32)msr_data;
1557
1558 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1559 }
1560
1561 return 0;
1562}
1563
8c604352
AP		 1564static int
1565emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1566{
1567 struct decode_cache *c = &ctxt->decode;
1568 struct kvm_segment cs, ss;
1569 u64 msr_data;
1570
1571 /* inject #UD if LOCK prefix is used */
1572 if (c->lock_prefix)
1573 return -1;
1574
1575 /* inject #GP if in real mode or paging is disabled */
3eeb3288 1576 if (ctxt->mode == X86EMUL_MODE_REAL || !is_protmode(ctxt->vcpu)) {
8c604352
AP		 1577 kvm_inject_gp(ctxt->vcpu, 0);
1578 return -1;
1579 }
1580
1581 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1582 * Therefore, we inject an #UD.
1583 */
1584 if (ctxt->mode == X86EMUL_MODE_PROT64)
1585 return -1;
1586
1587 setup_syscalls_segments(ctxt, &cs, &ss);
1588
1589 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1590 switch (ctxt->mode) {
1591 case X86EMUL_MODE_PROT32:
1592 if ((msr_data & 0xfffc) == 0x0) {
1593 kvm_inject_gp(ctxt->vcpu, 0);
1594 return -1;
1595 }
1596 break;
1597 case X86EMUL_MODE_PROT64:
1598 if (msr_data == 0x0) {
1599 kvm_inject_gp(ctxt->vcpu, 0);
1600 return -1;
1601 }
1602 break;
1603 }
1604
1605 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1606 cs.selector = (u16)msr_data;
1607 cs.selector &= ~SELECTOR_RPL_MASK;
1608 ss.selector = cs.selector + 8;
1609 ss.selector &= ~SELECTOR_RPL_MASK;
1610 if (ctxt->mode == X86EMUL_MODE_PROT64
1611 || is_long_mode(ctxt->vcpu)) {
1612 cs.db = 0;
1613 cs.l = 1;
1614 }
1615
1616 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1617 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1618
1619 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1620 c->eip = msr_data;
1621
1622 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1623 c->regs[VCPU_REGS_RSP] = msr_data;
1624
1625 return 0;
1626}
1627
4668f050
AP		 1628static int
1629emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1630{
1631 struct decode_cache *c = &ctxt->decode;
1632 struct kvm_segment cs, ss;
1633 u64 msr_data;
1634 int usermode;
1635
1636 /* inject #UD if LOCK prefix is used */
1637 if (c->lock_prefix)
1638 return -1;
1639
1640 /* inject #GP if in real mode or paging is disabled */
3eeb3288 1641 if (ctxt->mode == X86EMUL_MODE_REAL || !is_protmode(ctxt->vcpu)) {
4668f050
AP		 1642 kvm_inject_gp(ctxt->vcpu, 0);
1643 return -1;
1644 }
1645
1646 /* sysexit must be called from CPL 0 */
1647 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1648 kvm_inject_gp(ctxt->vcpu, 0);
1649 return -1;
1650 }
1651
1652 setup_syscalls_segments(ctxt, &cs, &ss);
1653
1654 if ((c->rex_prefix & 0x8) != 0x0)
1655 usermode = X86EMUL_MODE_PROT64;
1656 else
1657 usermode = X86EMUL_MODE_PROT32;
1658
1659 cs.dpl = 3;
1660 ss.dpl = 3;
1661 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1662 switch (usermode) {
1663 case X86EMUL_MODE_PROT32:
1664 cs.selector = (u16)(msr_data + 16);
1665 if ((msr_data & 0xfffc) == 0x0) {
1666 kvm_inject_gp(ctxt->vcpu, 0);
1667 return -1;
1668 }
1669 ss.selector = (u16)(msr_data + 24);
1670 break;
1671 case X86EMUL_MODE_PROT64:
1672 cs.selector = (u16)(msr_data + 32);
1673 if (msr_data == 0x0) {
1674 kvm_inject_gp(ctxt->vcpu, 0);
1675 return -1;
1676 }
1677 ss.selector = cs.selector + 8;
1678 cs.db = 0;
1679 cs.l = 1;
1680 break;
1681 }
1682 cs.selector |= SELECTOR_RPL_MASK;
1683 ss.selector |= SELECTOR_RPL_MASK;
1684
1685 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1686 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1687
1688 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1689 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1690
1691 return 0;
1692}
1693
8b4caf66 1694int
1be3aa47 1695x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1696{
e8d8d7fe 1697 unsigned long memop = 0;
8b4caf66 1698 u64 msr_data;
3427318f 1699 unsigned long saved_eip = 0;
8b4caf66 1700 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1701 unsigned int port;
1702 int io_dir_in;
1be3aa47 1703 int rc = 0;
8b4caf66 1704
310b5d30
GC		 1705 ctxt->interruptibility = 0;
1706
3427318f
LV		 1707 /* Shadow copy of register state. Committed on successful emulation.
1708 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1709 * modify them.
1710 */
1711
ad312c7c 1712 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1713 saved_eip = c->eip;
1714
c7e75a3d 1715 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1716 memop = c->modrm_ea;
8b4caf66 1717
b9fa9d6b
AK		 1718 if (c->rep_prefix && (c->d & String)) {
1719 /* All REP prefixes have the same first termination condition */
1720 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1721 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1722 goto done;
1723 }
1724 /* The second termination condition only applies for REPE
1725 * and REPNE. Test if the repeat string operation prefix is
1726 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1727 * corresponding termination condition according to:
1728 * - if REPE/REPZ and ZF = 0 then done
1729 * - if REPNE/REPNZ and ZF = 1 then done
1730 */
1731 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1732 (c->b == 0xae) || (c->b == 0xaf)) {
1733 if ((c->rep_prefix == REPE_PREFIX) &&
1734 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1735 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1736 goto done;
1737 }
1738 if ((c->rep_prefix == REPNE_PREFIX) &&
1739 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1740 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1741 goto done;
1742 }
1743 }
1744 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1745 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1746 }
1747
8b4caf66 1748 if (c->src.type == OP_MEM) {
e8d8d7fe 1749 c->src.ptr = (unsigned long *)memop;
8b4caf66 1750 c->src.val = 0;
d77c26fc
MD		 1751 rc = ops->read_emulated((unsigned long)c->src.ptr,
1752 &c->src.val,
1753 c->src.bytes,
1754 ctxt->vcpu);
b60d513c 1755 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 1756 goto done;
1757 c->src.orig_val = c->src.val;
1758 }
1759
1760 if ((c->d & DstMask) == ImplicitOps)
1761 goto special_insn;
1762
1763
1764 if (c->dst.type == OP_MEM) {
e8d8d7fe 1765 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1766 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1767 c->dst.val = 0;
e4e03ded
LV		 1768 if (c->d & BitOp) {
1769 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1770
e4e03ded
LV		 1771 c->dst.ptr = (void *)c->dst.ptr +
1772 (c->src.val & mask) / 8;
038e51de 1773 }
b60d513c
TY		 1774 if (!(c->d & Mov)) {
1775 /* optimisation - avoid slow emulated read */
1776 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1777 &c->dst.val,
1778 c->dst.bytes,
1779 ctxt->vcpu);
1780 if (rc != X86EMUL_CONTINUE)
1781 goto done;
1782 }
038e51de 1783 }
e4e03ded 1784 c->dst.orig_val = c->dst.val;
038e51de 1785
018a98db
AK		 1786special_insn:
1787
e4e03ded 1788 if (c->twobyte)
6aa8b732
AK		 1789 goto twobyte_insn;
1790
e4e03ded 1791 switch (c->b) {
6aa8b732
AK		 1792 case 0x00 ... 0x05:
1793 add: /* add */
05f086f8 1794 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1795 break;
0934ac9d 1796 case 0x06: /* push es */
0934ac9d
MG		 1797 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1798 break;
1799 case 0x07: /* pop es */
0934ac9d
MG		 1800 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1801 if (rc != 0)
1802 goto done;
1803 break;
6aa8b732
AK		 1804 case 0x08 ... 0x0d:
1805 or: /* or */
05f086f8 1806 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1807 break;
0934ac9d 1808 case 0x0e: /* push cs */
0934ac9d
MG		 1809 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1810 break;
6aa8b732
AK		 1811 case 0x10 ... 0x15:
1812 adc: /* adc */
05f086f8 1813 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1814 break;
0934ac9d 1815 case 0x16: /* push ss */
0934ac9d
MG		 1816 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1817 break;
1818 case 0x17: /* pop ss */
0934ac9d
MG		 1819 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1820 if (rc != 0)
1821 goto done;
1822 break;
6aa8b732
AK		 1823 case 0x18 ... 0x1d:
1824 sbb: /* sbb */
05f086f8 1825 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1826 break;
0934ac9d 1827 case 0x1e: /* push ds */
0934ac9d
MG		 1828 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1829 break;
1830 case 0x1f: /* pop ds */
0934ac9d
MG		 1831 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1832 if (rc != 0)
1833 goto done;
1834 break;
aa3a816b 1835 case 0x20 ... 0x25:
6aa8b732 1836 and: /* and */
05f086f8 1837 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1838 break;
1839 case 0x28 ... 0x2d:
1840 sub: /* sub */
05f086f8 1841 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1842 break;
1843 case 0x30 ... 0x35:
1844 xor: /* xor */
05f086f8 1845 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1846 break;
1847 case 0x38 ... 0x3d:
1848 cmp: /* cmp */
05f086f8 1849 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1850 break;
33615aa9
AK		 1851 case 0x40 ... 0x47: /* inc r16/r32 */
1852 emulate_1op("inc", c->dst, ctxt->eflags);
1853 break;
1854 case 0x48 ... 0x4f: /* dec r16/r32 */
1855 emulate_1op("dec", c->dst, ctxt->eflags);
1856 break;
1857 case 0x50 ... 0x57: /* push reg */
2786b014 1858 emulate_push(ctxt);
33615aa9
AK		 1859 break;
1860 case 0x58 ... 0x5f: /* pop reg */
1861 pop_instruction:
350f69dc 1862 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1863 if (rc != 0)
33615aa9 1864 goto done;
33615aa9 1865 break;
abcf14b5
MG		 1866 case 0x60: /* pusha */
1867 emulate_pusha(ctxt);
1868 break;
1869 case 0x61: /* popa */
1870 rc = emulate_popa(ctxt, ops);
1871 if (rc != 0)
1872 goto done;
1873 break;
6aa8b732 1874 case 0x63: /* movsxd */
8b4caf66 1875 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1876 goto cannot_emulate;
e4e03ded 1877 c->dst.val = (s32) c->src.val;
6aa8b732 1878 break;
91ed7a0e 1879 case 0x68: /* push imm */
018a98db 1880 case 0x6a: /* push imm8 */
018a98db
AK		 1881 emulate_push(ctxt);
1882 break;
1883 case 0x6c: /* insb */
1884 case 0x6d: /* insw/insd */
851ba692 1885 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1886 1,
1887 (c->d & ByteOp) ? 1 : c->op_bytes,
1888 c->rep_prefix ?
e4706772 1889 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1890 (ctxt->eflags & EFLG_DF),
7a5b56df 1891 register_address(c, es_base(ctxt),
018a98db
AK		 1892 c->regs[VCPU_REGS_RDI]),
1893 c->rep_prefix,
1894 c->regs[VCPU_REGS_RDX]) == 0) {
1895 c->eip = saved_eip;
1896 return -1;
1897 }
1898 return 0;
1899 case 0x6e: /* outsb */
1900 case 0x6f: /* outsw/outsd */
851ba692 1901 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1902 0,
1903 (c->d & ByteOp) ? 1 : c->op_bytes,
1904 c->rep_prefix ?
e4706772 1905 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1906 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1907 register_address(c,
1908 seg_override_base(ctxt, c),
018a98db
AK		 1909 c->regs[VCPU_REGS_RSI]),
1910 c->rep_prefix,
1911 c->regs[VCPU_REGS_RDX]) == 0) {
1912 c->eip = saved_eip;
1913 return -1;
1914 }
1915 return 0;
b2833e3c 1916 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1917 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1918 jmp_rel(c, c->src.val);
018a98db 1919 break;
6aa8b732 1920 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1921 switch (c->modrm_reg) {
6aa8b732
AK		 1922 case 0:
1923 goto add;
1924 case 1:
1925 goto or;
1926 case 2:
1927 goto adc;
1928 case 3:
1929 goto sbb;
1930 case 4:
1931 goto and;
1932 case 5:
1933 goto sub;
1934 case 6:
1935 goto xor;
1936 case 7:
1937 goto cmp;
1938 }
1939 break;
1940 case 0x84 ... 0x85:
05f086f8 1941 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1942 break;
1943 case 0x86 ... 0x87: /* xchg */
b13354f8 1944 xchg:
6aa8b732 1945 /* Write back the register source. */
e4e03ded 1946 switch (c->dst.bytes) {
6aa8b732 1947 case 1:
e4e03ded 1948 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1949 break;
1950 case 2:
e4e03ded 1951 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1952 break;
1953 case 4:
e4e03ded 1954 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1955 break; /* 64b reg: zero-extend */
1956 case 8:
e4e03ded 1957 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1958 break;
1959 }
1960 /*
1961 * Write back the memory destination with implicit LOCK
1962 * prefix.
1963 */
e4e03ded
LV		 1964 c->dst.val = c->src.val;
1965 c->lock_prefix = 1;
6aa8b732 1966 break;
6aa8b732 1967 case 0x88 ... 0x8b: /* mov */
7de75248 1968 goto mov;
38d5bc6d
GT		 1969 case 0x8c: { /* mov r/m, sreg */
1970 struct kvm_segment segreg;
1971
1972 if (c->modrm_reg <= 5)
1973 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1974 else {
1975 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1976 c->modrm);
1977 goto cannot_emulate;
1978 }
1979 c->dst.val = segreg.selector;
1980 break;
1981 }
7e0b54b1 1982 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1983 c->dst.val = c->modrm_ea;
7e0b54b1 1984 break;
4257198a
GT		 1985 case 0x8e: { /* mov seg, r/m16 */
1986 uint16_t sel;
1987 int type_bits;
1988 int err;
1989
1990 sel = c->src.val;
310b5d30
GC		 1991 if (c->modrm_reg == VCPU_SREG_SS)
1992 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1993
4257198a
GT		 1994 if (c->modrm_reg <= 5) {
1995 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1996 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1997 type_bits, c->modrm_reg);
1998 } else {
1999 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
2000 c->modrm);
2001 goto cannot_emulate;
2002 }
2003
2004 if (err < 0)
2005 goto cannot_emulate;
2006
2007 c->dst.type = OP_NONE; /* Disable writeback. */
2008 break;
2009 }
6aa8b732 2010 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 2011 rc = emulate_grp1a(ctxt, ops);
2012 if (rc != 0)
6aa8b732 2013 goto done;
6aa8b732 2014 break;
b13354f8
MG		 2015 case 0x90: /* nop / xchg r8,rax */
2016 if (!(c->rex_prefix & 1)) { /* nop */
2017 c->dst.type = OP_NONE;
2018 break;
2019 }
2020 case 0x91 ... 0x97: /* xchg reg,rax */
2021 c->src.type = c->dst.type = OP_REG;
2022 c->src.bytes = c->dst.bytes = c->op_bytes;
2023 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2024 c->src.val = *(c->src.ptr);
2025 goto xchg;
fd2a7608 2026 case 0x9c: /* pushf */
05f086f8 2027 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2028 emulate_push(ctxt);
2029 break;
535eabcf 2030 case 0x9d: /* popf */
2b48cc75 2031 c->dst.type = OP_REG;
05f086f8 2032 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2033 c->dst.bytes = c->op_bytes;
535eabcf 2034 goto pop_instruction;
018a98db
AK		 2035 case 0xa0 ... 0xa1: /* mov */
2036 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2037 c->dst.val = c->src.val;
2038 break;
2039 case 0xa2 ... 0xa3: /* mov */
2040 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2041 break;
6aa8b732 2042 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2043 c->dst.type = OP_MEM;
2044 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2045 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2046 es_base(ctxt),
e4e03ded 2047 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2048 rc = ops->read_emulated(register_address(c,
2049 seg_override_base(ctxt, c),
2050 c->regs[VCPU_REGS_RSI]),
e4e03ded 2051 &c->dst.val,
b60d513c
TY		 2052 c->dst.bytes, ctxt->vcpu);
2053 if (rc != X86EMUL_CONTINUE)
6aa8b732 2054 goto done;
7a957275 2055 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2056 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2057 : c->dst.bytes);
7a957275 2058 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2059 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2060 : c->dst.bytes);
6aa8b732
AK		 2061 break;
2062 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2063 c->src.type = OP_NONE; /* Disable writeback. */
2064 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2065 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2066 seg_override_base(ctxt, c),
d7e5117a 2067 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2068 rc = ops->read_emulated((unsigned long)c->src.ptr,
2069 &c->src.val,
2070 c->src.bytes,
2071 ctxt->vcpu);
2072 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2073 goto done;
2074
2075 c->dst.type = OP_NONE; /* Disable writeback. */
2076 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2077 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2078 es_base(ctxt),
d7e5117a 2079 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2080 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2081 &c->dst.val,
2082 c->dst.bytes,
2083 ctxt->vcpu);
2084 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2085 goto done;
2086
2087 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2088
2089 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2090
7a957275 2091 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2092 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2093 : c->src.bytes);
7a957275 2094 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2095 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2096 : c->dst.bytes);
2097
2098 break;
6aa8b732 2099 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2100 c->dst.type = OP_MEM;
2101 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2102 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2103 es_base(ctxt),
a7e6c88a 2104 c->regs[VCPU_REGS_RDI]);
e4e03ded 2105 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2106 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2107 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2108 : c->dst.bytes);
6aa8b732
AK		 2109 break;
2110 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2111 c->dst.type = OP_REG;
2112 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2113 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2114 rc = ops->read_emulated(register_address(c,
2115 seg_override_base(ctxt, c),
2116 c->regs[VCPU_REGS_RSI]),
2117 &c->dst.val,
2118 c->dst.bytes,
2119 ctxt->vcpu);
2120 if (rc != X86EMUL_CONTINUE)
6aa8b732 2121 goto done;
7a957275 2122 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2123 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2124 : c->dst.bytes);
6aa8b732
AK		 2125 break;
2126 case 0xae ... 0xaf: /* scas */
2127 DPRINTF("Urk! I don't handle SCAS.\n");
2128 goto cannot_emulate;
a5e2e82b 2129 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2130 goto mov;
018a98db
AK		 2131 case 0xc0 ... 0xc1:
2132 emulate_grp2(ctxt);
2133 break;
111de5d6 2134 case 0xc3: /* ret */
cf5de4f8 2135 c->dst.type = OP_REG;
111de5d6 2136 c->dst.ptr = &c->eip;
cf5de4f8 2137 c->dst.bytes = c->op_bytes;
111de5d6 2138 goto pop_instruction;
018a98db
AK		 2139 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2140 mov:
2141 c->dst.val = c->src.val;
2142 break;
a77ab5ea
AK		 2143 case 0xcb: /* ret far */
2144 rc = emulate_ret_far(ctxt, ops);
2145 if (rc)
2146 goto done;
2147 break;
018a98db
AK		 2148 case 0xd0 ... 0xd1: /* Grp2 */
2149 c->src.val = 1;
2150 emulate_grp2(ctxt);
2151 break;
2152 case 0xd2 ... 0xd3: /* Grp2 */
2153 c->src.val = c->regs[VCPU_REGS_RCX];
2154 emulate_grp2(ctxt);
2155 break;
a6a3034c
MG		 2156 case 0xe4: /* inb */
2157 case 0xe5: /* in */
84ce66a6 2158 port = c->src.val;
a6a3034c
MG		 2159 io_dir_in = 1;
2160 goto do_io;
2161 case 0xe6: /* outb */
2162 case 0xe7: /* out */
84ce66a6 2163 port = c->src.val;
a6a3034c
MG		 2164 io_dir_in = 0;
2165 goto do_io;
1a52e051 2166 case 0xe8: /* call (near) */ {
d53c4777 2167 long int rel = c->src.val;
e4e03ded 2168 c->src.val = (unsigned long) c->eip;
7a957275 2169 jmp_rel(c, rel);
8cdbd2c9
LV		 2170 emulate_push(ctxt);
2171 break;
1a52e051
NK		 2172 }
2173 case 0xe9: /* jmp rel */
954cd36f 2174 goto jmp;
782b877c
GN		 2175 case 0xea: /* jmp far */
2176 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2177 VCPU_SREG_CS) < 0) {
954cd36f
GT		 2178 DPRINTF("jmp far: Failed to load CS descriptor\n");
2179 goto cannot_emulate;
2180 }
2181
782b877c 2182 c->eip = c->src.val;
954cd36f 2183 break;
954cd36f
GT		 2184 case 0xeb:
2185 jmp: /* jmp rel short */
7a957275 2186 jmp_rel(c, c->src.val);
a01af5ec 2187 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2188 break;
a6a3034c
MG		 2189 case 0xec: /* in al,dx */
2190 case 0xed: /* in (e/r)ax,dx */
2191 port = c->regs[VCPU_REGS_RDX];
2192 io_dir_in = 1;
2193 goto do_io;
2194 case 0xee: /* out al,dx */
2195 case 0xef: /* out (e/r)ax,dx */
2196 port = c->regs[VCPU_REGS_RDX];
2197 io_dir_in = 0;
851ba692 2198 do_io: if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2199 (c->d & ByteOp) ? 1 : c->op_bytes,
2200 port) != 0) {
2201 c->eip = saved_eip;
2202 goto cannot_emulate;
2203 }
e93f36bc 2204 break;
111de5d6 2205 case 0xf4: /* hlt */
ad312c7c 2206 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2207 break;
111de5d6
AK		 2208 case 0xf5: /* cmc */
2209 /* complement carry flag from eflags reg */
2210 ctxt->eflags ^= EFLG_CF;
2211 c->dst.type = OP_NONE; /* Disable writeback. */
2212 break;
018a98db
AK		 2213 case 0xf6 ... 0xf7: /* Grp3 */
2214 rc = emulate_grp3(ctxt, ops);
2215 if (rc != 0)
2216 goto done;
2217 break;
111de5d6
AK		 2218 case 0xf8: /* clc */
2219 ctxt->eflags &= ~EFLG_CF;
2220 c->dst.type = OP_NONE; /* Disable writeback. */
2221 break;
2222 case 0xfa: /* cli */
2223 ctxt->eflags &= ~X86_EFLAGS_IF;
2224 c->dst.type = OP_NONE; /* Disable writeback. */
2225 break;
2226 case 0xfb: /* sti */
310b5d30 2227 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
111de5d6
AK		 2228 ctxt->eflags |= X86_EFLAGS_IF;
2229 c->dst.type = OP_NONE; /* Disable writeback. */
2230 break;
fb4616f4
MG		 2231 case 0xfc: /* cld */
2232 ctxt->eflags &= ~EFLG_DF;
2233 c->dst.type = OP_NONE; /* Disable writeback. */
2234 break;
2235 case 0xfd: /* std */
2236 ctxt->eflags |= EFLG_DF;
2237 c->dst.type = OP_NONE; /* Disable writeback. */
2238 break;
018a98db
AK		 2239 case 0xfe ... 0xff: /* Grp4/Grp5 */
2240 rc = emulate_grp45(ctxt, ops);
2241 if (rc != 0)
2242 goto done;
2243 break;
6aa8b732 2244 }
018a98db
AK		 2245
2246writeback:
2247 rc = writeback(ctxt, ops);
2248 if (rc != 0)
2249 goto done;
2250
2251 /* Commit shadow register state. */
ad312c7c 2252 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2253 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2254
2255done:
2256 if (rc == X86EMUL_UNHANDLEABLE) {
2257 c->eip = saved_eip;
2258 return -1;
2259 }
2260 return 0;
6aa8b732
AK		 2261
2262twobyte_insn:
e4e03ded 2263 switch (c->b) {
6aa8b732 2264 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2265 switch (c->modrm_reg) {
6aa8b732
AK		 2266 u16 size;
2267 unsigned long address;
2268
aca7f966 2269 case 0: /* vmcall */
e4e03ded 2270 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2271 goto cannot_emulate;
2272
7aa81cc0
AL		 2273 rc = kvm_fix_hypercall(ctxt->vcpu);
2274 if (rc)
2275 goto done;
2276
33e3885d 2277 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2278 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2279 /* Disable writeback. */
2280 c->dst.type = OP_NONE;
aca7f966 2281 break;
6aa8b732 2282 case 2: /* lgdt */
e4e03ded
LV		 2283 rc = read_descriptor(ctxt, ops, c->src.ptr,
2284 &size, &address, c->op_bytes);
6aa8b732
AK		 2285 if (rc)
2286 goto done;
2287 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2288 /* Disable writeback. */
2289 c->dst.type = OP_NONE;
6aa8b732 2290 break;
aca7f966 2291 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2292 if (c->modrm_mod == 3) {
2293 switch (c->modrm_rm) {
2294 case 1:
2295 rc = kvm_fix_hypercall(ctxt->vcpu);
2296 if (rc)
2297 goto done;
2298 break;
2299 default:
2300 goto cannot_emulate;
2301 }
aca7f966 2302 } else {
e4e03ded 2303 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2304 &size, &address,
e4e03ded 2305 c->op_bytes);
aca7f966
AL		 2306 if (rc)
2307 goto done;
2308 realmode_lidt(ctxt->vcpu, size, address);
2309 }
16286d08
AK		 2310 /* Disable writeback. */
2311 c->dst.type = OP_NONE;
6aa8b732
AK		 2312 break;
2313 case 4: /* smsw */
16286d08
AK		 2314 c->dst.bytes = 2;
2315 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2316 break;
2317 case 6: /* lmsw */
16286d08
AK		 2318 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2319 &ctxt->eflags);
dc7457ea 2320 c->dst.type = OP_NONE;
6aa8b732
AK		 2321 break;
2322 case 7: /* invlpg*/
e8d8d7fe 2323 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2324 /* Disable writeback. */
2325 c->dst.type = OP_NONE;
6aa8b732
AK		 2326 break;
2327 default:
2328 goto cannot_emulate;
2329 }
2330 break;
e99f0507 2331 case 0x05: /* syscall */
e66bb2cc
AP		 2332 if (emulate_syscall(ctxt) == -1)
2333 goto cannot_emulate;
2334 else
2335 goto writeback;
e99f0507 2336 break;
018a98db
AK		 2337 case 0x06:
2338 emulate_clts(ctxt->vcpu);
2339 c->dst.type = OP_NONE;
2340 break;
2341 case 0x08: /* invd */
2342 case 0x09: /* wbinvd */
2343 case 0x0d: /* GrpP (prefetch) */
2344 case 0x18: /* Grp16 (prefetch/nop) */
2345 c->dst.type = OP_NONE;
2346 break;
2347 case 0x20: /* mov cr, reg */
2348 if (c->modrm_mod != 3)
2349 goto cannot_emulate;
2350 c->regs[c->modrm_rm] =
2351 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2352 c->dst.type = OP_NONE; /* no writeback */
2353 break;
6aa8b732 2354 case 0x21: /* mov from dr to reg */
e4e03ded 2355 if (c->modrm_mod != 3)
6aa8b732 2356 goto cannot_emulate;
8cdbd2c9 2357 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2358 if (rc)
2359 goto cannot_emulate;
2360 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2361 break;
018a98db
AK		 2362 case 0x22: /* mov reg, cr */
2363 if (c->modrm_mod != 3)
2364 goto cannot_emulate;
2365 realmode_set_cr(ctxt->vcpu,
2366 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2367 c->dst.type = OP_NONE;
2368 break;
6aa8b732 2369 case 0x23: /* mov from reg to dr */
e4e03ded 2370 if (c->modrm_mod != 3)
6aa8b732 2371 goto cannot_emulate;
e4e03ded
LV		 2372 rc = emulator_set_dr(ctxt, c->modrm_reg,
2373 c->regs[c->modrm_rm]);
a01af5ec
LV		 2374 if (rc)
2375 goto cannot_emulate;
2376 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2377 break;
018a98db
AK		 2378 case 0x30:
2379 /* wrmsr */
2380 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2381 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2382 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2383 if (rc) {
c1a5d4f9 2384 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2385 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2386 }
2387 rc = X86EMUL_CONTINUE;
2388 c->dst.type = OP_NONE;
2389 break;
2390 case 0x32:
2391 /* rdmsr */
2392 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2393 if (rc) {
c1a5d4f9 2394 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2395 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2396 } else {
2397 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2398 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2399 }
2400 rc = X86EMUL_CONTINUE;
2401 c->dst.type = OP_NONE;
2402 break;
e99f0507 2403 case 0x34: /* sysenter */
8c604352
AP		 2404 if (emulate_sysenter(ctxt) == -1)
2405 goto cannot_emulate;
2406 else
2407 goto writeback;
e99f0507
AP		 2408 break;
2409 case 0x35: /* sysexit */
4668f050
AP		 2410 if (emulate_sysexit(ctxt) == -1)
2411 goto cannot_emulate;
2412 else
2413 goto writeback;
e99f0507 2414 break;
6aa8b732 2415 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2416 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2417 if (!test_cc(c->b, ctxt->eflags))
2418 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2419 break;
b2833e3c 2420 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2421 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2422 jmp_rel(c, c->src.val);
018a98db
AK		 2423 c->dst.type = OP_NONE;
2424 break;
0934ac9d
MG		 2425 case 0xa0: /* push fs */
2426 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2427 break;
2428 case 0xa1: /* pop fs */
2429 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2430 if (rc != 0)
2431 goto done;
2432 break;
7de75248
NK		 2433 case 0xa3:
2434 bt: /* bt */
e4f8e039 2435 c->dst.type = OP_NONE;
e4e03ded
LV		 2436 /* only subword offset */
2437 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2438 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2439 break;
9bf8ea42
GT		 2440 case 0xa4: /* shld imm8, r, r/m */
2441 case 0xa5: /* shld cl, r, r/m */
2442 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2443 break;
0934ac9d
MG		 2444 case 0xa8: /* push gs */
2445 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2446 break;
2447 case 0xa9: /* pop gs */
2448 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2449 if (rc != 0)
2450 goto done;
2451 break;
7de75248
NK		 2452 case 0xab:
2453 bts: /* bts */
e4e03ded
LV		 2454 /* only subword offset */
2455 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2456 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2457 break;
9bf8ea42
GT		 2458 case 0xac: /* shrd imm8, r, r/m */
2459 case 0xad: /* shrd cl, r, r/m */
2460 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2461 break;
2a7c5b8b
GC		 2462 case 0xae: /* clflush */
2463 break;
6aa8b732
AK		 2464 case 0xb0 ... 0xb1: /* cmpxchg */
2465 /*
2466 * Save real source value, then compare EAX against
2467 * destination.
2468 */
e4e03ded
LV		 2469 c->src.orig_val = c->src.val;
2470 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2471 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2472 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2473 /* Success: write back to memory. */
e4e03ded 2474 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2475 } else {
2476 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2477 c->dst.type = OP_REG;
2478 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2479 }
2480 break;
6aa8b732
AK		 2481 case 0xb3:
2482 btr: /* btr */
e4e03ded
LV		 2483 /* only subword offset */
2484 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2485 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2486 break;
6aa8b732 2487 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2488 c->dst.bytes = c->op_bytes;
2489 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2490 : (u16) c->src.val;
6aa8b732 2491 break;
6aa8b732 2492 case 0xba: /* Grp8 */
e4e03ded 2493 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2494 case 0:
2495 goto bt;
2496 case 1:
2497 goto bts;
2498 case 2:
2499 goto btr;
2500 case 3:
2501 goto btc;
2502 }
2503 break;
7de75248
NK		 2504 case 0xbb:
2505 btc: /* btc */
e4e03ded
LV		 2506 /* only subword offset */
2507 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2508 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2509 break;
6aa8b732 2510 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2511 c->dst.bytes = c->op_bytes;
2512 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2513 (s16) c->src.val;
6aa8b732 2514 break;
a012e65a 2515 case 0xc3: /* movnti */
e4e03ded
LV		 2516 c->dst.bytes = c->op_bytes;
2517 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2518 (u64) c->src.val;
a012e65a 2519 break;
6aa8b732 2520 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2521 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2522 if (rc != 0)
2523 goto done;
018a98db 2524 c->dst.type = OP_NONE;
8cdbd2c9 2525 break;
6aa8b732
AK		 2526 }
2527 goto writeback;
2528
2529cannot_emulate:
e4e03ded 2530 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2531 c->eip = saved_eip;
6aa8b732
AK		 2532 return -1;
2533}
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