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KVM: x86: pop sreg accesses only 2 bytes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 126#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 127#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 128/* Generic ModRM decode. */
129#define ModRM (1<<19)
130/* Destination is only written; never read. */
131#define Mov (1<<20)
d8769fed 132/* Misc flags */
8ea7d6ae 133#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 134#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 135#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 136#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 137#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 138#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 139#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 140#define No64 (1<<28)
d5ae7ce8 141#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 142#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 143/* Source 2 operand type */
0b789eee 144#define Src2Shift (31)
4dd6a57d 145#define Src2None (OpNone << Src2Shift)
ab2c5ce6 146#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 147#define Src2CL (OpCL << Src2Shift)
148#define Src2ImmByte (OpImmByte << Src2Shift)
149#define Src2One (OpOne << Src2Shift)
150#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 151#define Src2ES (OpES << Src2Shift)
152#define Src2CS (OpCS << Src2Shift)
153#define Src2SS (OpSS << Src2Shift)
154#define Src2DS (OpDS << Src2Shift)
155#define Src2FS (OpFS << Src2Shift)
156#define Src2GS (OpGS << Src2Shift)
4dd6a57d 157#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 158#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 159#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
160#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
161#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 162#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 163#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 164#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 165#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 166#define Intercept ((u64)1 << 48) /* Has valid intercept field */
167#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 168#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 169#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 170#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 171#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 172
820207c8 173#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 174
d0e53325
AK		 175#define X2(x...) x, x
176#define X3(x...) X2(x), x
177#define X4(x...) X2(x), X2(x)
178#define X5(x...) X4(x), x
179#define X6(x...) X4(x), X2(x)
180#define X7(x...) X4(x), X3(x)
181#define X8(x...) X4(x), X4(x)
182#define X16(x...) X8(x), X8(x)
83babbca 183
e28bbd44
AK		 184#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
185#define FASTOP_SIZE 8
186
187/*
188 * fastop functions have a special calling convention:
189 *
017da7b6
AK		 190 * dst: rax (in/out)
191 * src: rdx (in/out)
e28bbd44
AK		 192 * src2: rcx (in)
193 * flags: rflags (in/out)
b8c0b6ae 194 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 195 *
196 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
197 * different operand sizes can be reached by calculation, rather than a jump
198 * table (which would be bigger than the code).
199 *
200 * fastop functions are declared as taking a never-defined fastop parameter,
201 * so they can't be called from C directly.
202 */
203
204struct fastop;
205
d65b1dee 206struct opcode {
b1ea50b2
AK		 207 u64 flags : 56;
208 u64 intercept : 8;
120df890 209 union {
ef65c889 210 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 211 const struct opcode *group;
212 const struct group_dual *gdual;
213 const struct gprefix *gprefix;
045a282c 214 const struct escape *esc;
39f062ff 215 const struct instr_dual *idual;
e28bbd44 216 void (*fastop)(struct fastop *fake);
120df890 217 } u;
d09beabd 218 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 219};
220
221struct group_dual {
222 struct opcode mod012[8];
223 struct opcode mod3[8];
d65b1dee
AK		 224};
225
0d7cdee8
AK		 226struct gprefix {
227 struct opcode pfx_no;
228 struct opcode pfx_66;
229 struct opcode pfx_f2;
230 struct opcode pfx_f3;
231};
232
045a282c
GN		 233struct escape {
234 struct opcode op[8];
235 struct opcode high[64];
236};
237
39f062ff
NA		 238struct instr_dual {
239 struct opcode mod012;
240 struct opcode mod3;
241};
242
6aa8b732 243/* EFLAGS bit definitions. */
d4c6a154
GN		 244#define EFLG_ID (1<<21)
245#define EFLG_VIP (1<<20)
246#define EFLG_VIF (1<<19)
247#define EFLG_AC (1<<18)
b1d86143
AP		 248#define EFLG_VM (1<<17)
249#define EFLG_RF (1<<16)
d4c6a154
GN		 250#define EFLG_IOPL (3<<12)
251#define EFLG_NT (1<<14)
6aa8b732
AK		 252#define EFLG_OF (1<<11)
253#define EFLG_DF (1<<10)
b1d86143 254#define EFLG_IF (1<<9)
d4c6a154 255#define EFLG_TF (1<<8)
6aa8b732
AK		 256#define EFLG_SF (1<<7)
257#define EFLG_ZF (1<<6)
258#define EFLG_AF (1<<4)
259#define EFLG_PF (1<<2)
260#define EFLG_CF (1<<0)
261
62bd430e
MG		 262#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
263#define EFLG_RESERVED_ONE_MASK 2
264
dd856efa
AK		 265static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
266{
267 if (!(ctxt->regs_valid & (1 << nr))) {
268 ctxt->regs_valid |= 1 << nr;
269 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
270 }
271 return ctxt->_regs[nr];
272}
273
274static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 ctxt->regs_valid |= 1 << nr;
277 ctxt->regs_dirty |= 1 << nr;
278 return &ctxt->_regs[nr];
279}
280
281static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
282{
283 reg_read(ctxt, nr);
284 return reg_write(ctxt, nr);
285}
286
287static void writeback_registers(struct x86_emulate_ctxt *ctxt)
288{
289 unsigned reg;
290
291 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
292 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
293}
294
295static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
296{
297 ctxt->regs_dirty = 0;
298 ctxt->regs_valid = 0;
299}
300
6aa8b732
AK		 301/*
302 * These EFLAGS bits are restored from saved value during emulation, and
303 * any changes are written back to the saved value after emulation.
304 */
305#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
306
dda96d8f
AK		 307#ifdef CONFIG_X86_64
308#define ON64(x) x
309#else
310#define ON64(x)
311#endif
312
4d758349
AK		 313static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
314
b7d491e7
AK		 315#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
316#define FOP_RET "ret \n\t"
317
318#define FOP_START(op) \
319 extern void em_##op(struct fastop *fake); \
320 asm(".pushsection .text, \"ax\" \n\t" \
321 ".global em_" #op " \n\t" \
322 FOP_ALIGN \
323 "em_" #op ": \n\t"
324
325#define FOP_END \
326 ".popsection")
327
0bdea068
AK		 328#define FOPNOP() FOP_ALIGN FOP_RET
329
b7d491e7 330#define FOP1E(op, dst) \
b8c0b6ae
AK		 331 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
332
333#define FOP1EEX(op, dst) \
334 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 335
336#define FASTOP1(op) \
337 FOP_START(op) \
338 FOP1E(op##b, al) \
339 FOP1E(op##w, ax) \
340 FOP1E(op##l, eax) \
341 ON64(FOP1E(op##q, rax)) \
342 FOP_END
343
b9fa409b
AK		 344/* 1-operand, using src2 (for MUL/DIV r/m) */
345#define FASTOP1SRC2(op, name) \
346 FOP_START(name) \
347 FOP1E(op, cl) \
348 FOP1E(op, cx) \
349 FOP1E(op, ecx) \
350 ON64(FOP1E(op, rcx)) \
351 FOP_END
352
b8c0b6ae
AK		 353/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
354#define FASTOP1SRC2EX(op, name) \
355 FOP_START(name) \
356 FOP1EEX(op, cl) \
357 FOP1EEX(op, cx) \
358 FOP1EEX(op, ecx) \
359 ON64(FOP1EEX(op, rcx)) \
360 FOP_END
361
f7857f35
AK		 362#define FOP2E(op, dst, src) \
363 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
364
365#define FASTOP2(op) \
366 FOP_START(op) \
017da7b6
AK		 367 FOP2E(op##b, al, dl) \
368 FOP2E(op##w, ax, dx) \
369 FOP2E(op##l, eax, edx) \
370 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 371 FOP_END
372
11c363ba
AK		 373/* 2 operand, word only */
374#define FASTOP2W(op) \
375 FOP_START(op) \
376 FOPNOP() \
017da7b6
AK		 377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 380 FOP_END
381
007a3b54
AK		 382/* 2 operand, src is CL */
383#define FASTOP2CL(op) \
384 FOP_START(op) \
385 FOP2E(op##b, al, cl) \
386 FOP2E(op##w, ax, cl) \
387 FOP2E(op##l, eax, cl) \
388 ON64(FOP2E(op##q, rax, cl)) \
389 FOP_END
390
5aca3722
NA		 391/* 2 operand, src and dest are reversed */
392#define FASTOP2R(op, name) \
393 FOP_START(name) \
394 FOP2E(op##b, dl, al) \
395 FOP2E(op##w, dx, ax) \
396 FOP2E(op##l, edx, eax) \
397 ON64(FOP2E(op##q, rdx, rax)) \
398 FOP_END
399
0bdea068
AK		 400#define FOP3E(op, dst, src, src2) \
401 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
402
403/* 3-operand, word-only, src2=cl */
404#define FASTOP3WCL(op) \
405 FOP_START(op) \
406 FOPNOP() \
017da7b6
AK		 407 FOP3E(op##w, ax, dx, cl) \
408 FOP3E(op##l, eax, edx, cl) \
409 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 410 FOP_END
411
9ae9feba
AK		 412/* Special case for SETcc - 1 instruction per cc */
413#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
414
b8c0b6ae
AK		 415asm(".global kvm_fastop_exception \n"
416 "kvm_fastop_exception: xor %esi, %esi; ret");
417
9ae9feba
AK		 418FOP_START(setcc)
419FOP_SETCC(seto)
420FOP_SETCC(setno)
421FOP_SETCC(setc)
422FOP_SETCC(setnc)
423FOP_SETCC(setz)
424FOP_SETCC(setnz)
425FOP_SETCC(setbe)
426FOP_SETCC(setnbe)
427FOP_SETCC(sets)
428FOP_SETCC(setns)
429FOP_SETCC(setp)
430FOP_SETCC(setnp)
431FOP_SETCC(setl)
432FOP_SETCC(setnl)
433FOP_SETCC(setle)
434FOP_SETCC(setnle)
435FOP_END;
436
326f578f
PB		 437FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
438FOP_END;
439
8a76d7f2
JR		 440static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
441 enum x86_intercept intercept,
442 enum x86_intercept_stage stage)
443{
444 struct x86_instruction_info info = {
445 .intercept = intercept,
9dac77fa
AK		 446 .rep_prefix = ctxt->rep_prefix,
447 .modrm_mod = ctxt->modrm_mod,
448 .modrm_reg = ctxt->modrm_reg,
449 .modrm_rm = ctxt->modrm_rm,
450 .src_val = ctxt->src.val64,
6cbc5f5a 451 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 452 .src_bytes = ctxt->src.bytes,
453 .dst_bytes = ctxt->dst.bytes,
454 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 455 .next_rip = ctxt->eip,
456 };
457
2953538e 458 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 459}
460
f47cfa31
AK		 461static void assign_masked(ulong *dest, ulong src, ulong mask)
462{
463 *dest = (*dest & ~mask) | (src & mask);
464}
465
9dac77fa 466static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 467{
9dac77fa 468 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 469}
470
f47cfa31
AK		 471static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
472{
473 u16 sel;
474 struct desc_struct ss;
475
476 if (ctxt->mode == X86EMUL_MODE_PROT64)
477 return ~0UL;
478 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
479 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
480}
481
612e89f0
AK		 482static int stack_size(struct x86_emulate_ctxt *ctxt)
483{
484 return (__fls(stack_mask(ctxt)) + 1) >> 3;
485}
486
6aa8b732 487/* Access/update address held in a register, based on addressing mode. */
e4706772 488static inline unsigned long
9dac77fa 489address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 490{
9dac77fa 491 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 492 return reg;
493 else
9dac77fa 494 return reg & ad_mask(ctxt);
e4706772
HH		 495}
496
497static inline unsigned long
01485a22 498register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 499{
01485a22 500 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 501}
502
5ad105e5
AK		 503static void masked_increment(ulong *reg, ulong mask, int inc)
504{
505 assign_masked(reg, *reg + inc, mask);
506}
507
7a957275 508static inline void
01485a22 509register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 510{
5ad105e5
AK		 511 ulong mask;
512
9dac77fa 513 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 514 mask = ~0UL;
7a957275 515 else
5ad105e5 516 mask = ad_mask(ctxt);
01485a22 517 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 518}
519
520static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
521{
dd856efa 522 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 523}
6aa8b732 524
56697687
AK		 525static u32 desc_limit_scaled(struct desc_struct *desc)
526{
527 u32 limit = get_desc_limit(desc);
528
529 return desc->g ? (limit << 12) | 0xfff : limit;
530}
531
7b105ca2 532static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 533{
534 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
535 return 0;
536
7b105ca2 537 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 538}
539
35d3d4a1
AK		 540static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
541 u32 error, bool valid)
54b8486f 542{
e0ad0b47 543 WARN_ON(vec > 0x1f);
da9cb575
AK		 544 ctxt->exception.vector = vec;
545 ctxt->exception.error_code = error;
546 ctxt->exception.error_code_valid = valid;
35d3d4a1 547 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 548}
549
3b88e41a
JR		 550static int emulate_db(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, DB_VECTOR, 0, false);
553}
554
35d3d4a1 555static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 556{
35d3d4a1 557 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 558}
559
618ff15d
AK		 560static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
561{
562 return emulate_exception(ctxt, SS_VECTOR, err, true);
563}
564
35d3d4a1 565static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 566{
35d3d4a1 567 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 568}
569
35d3d4a1 570static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 571{
35d3d4a1 572 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 573}
574
34d1f490
AK		 575static int emulate_de(struct x86_emulate_ctxt *ctxt)
576{
35d3d4a1 577 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 578}
579
1253791d
AK		 580static int emulate_nm(struct x86_emulate_ctxt *ctxt)
581{
582 return emulate_exception(ctxt, NM_VECTOR, 0, false);
583}
584
1aa36616
AK		 585static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
586{
587 u16 selector;
588 struct desc_struct desc;
589
590 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
591 return selector;
592}
593
594static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
595 unsigned seg)
596{
597 u16 dummy;
598 u32 base3;
599 struct desc_struct desc;
600
601 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
602 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
603}
604
1c11b376
AK		 605/*
606 * x86 defines three classes of vector instructions: explicitly
607 * aligned, explicitly unaligned, and the rest, which change behaviour
608 * depending on whether they're AVX encoded or not.
609 *
610 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
611 * subject to the same check.
612 */
613static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
614{
615 if (likely(size < 16))
616 return false;
617
618 if (ctxt->d & Aligned)
619 return true;
620 else if (ctxt->d & Unaligned)
621 return false;
622 else if (ctxt->d & Avx)
623 return false;
624 else
625 return true;
626}
627
d09155d2
PB		 628static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned *max_size, unsigned size,
631 bool write, bool fetch,
d50eaa18 632 enum x86emul_mode mode, ulong *linear)
52fd8b44 633{
618ff15d
AK		 634 struct desc_struct desc;
635 bool usable;
52fd8b44 636 ulong la;
618ff15d 637 u32 lim;
1aa36616 638 u16 sel;
52fd8b44 639
7b105ca2 640 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 641 *max_size = 0;
d50eaa18 642 switch (mode) {
618ff15d 643 case X86EMUL_MODE_PROT64:
4be4de7e 644 if (is_noncanonical_address(la))
abc7d8a4 645 goto bad;
fd56e154
PB		 646
647 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
648 if (size > *max_size)
649 goto bad;
618ff15d
AK		 650 break;
651 default:
1aa36616
AK		 652 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
653 addr.seg);
618ff15d
AK		 654 if (!usable)
655 goto bad;
58b7825b
GN		 656 /* code segment in protected mode or read-only data segment */
657 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
658 || !(desc.type & 2)) && write)
618ff15d
AK		 659 goto bad;
660 /* unreadable code segment */
3d9b938e 661 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 662 goto bad;
663 lim = desc_limit_scaled(&desc);
997b0412 664 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 665 /* expand-down segment */
fd56e154 666 if (addr.ea <= lim)
618ff15d
AK		 667 goto bad;
668 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 669 }
997b0412
PB		 670 if (addr.ea > lim)
671 goto bad;
672 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 673 if (size > *max_size)
674 goto bad;
31ff6488 675 la &= (u32)-1;
618ff15d
AK		 676 break;
677 }
1c11b376
AK		 678 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
679 return emulate_gp(ctxt, 0);
52fd8b44
AK		 680 *linear = la;
681 return X86EMUL_CONTINUE;
618ff15d
AK		 682bad:
683 if (addr.seg == VCPU_SREG_SS)
3606189f 684 return emulate_ss(ctxt, 0);
618ff15d 685 else
3606189f 686 return emulate_gp(ctxt, 0);
52fd8b44
AK		 687}
688
3d9b938e
NE		 689static int linearize(struct x86_emulate_ctxt *ctxt,
690 struct segmented_address addr,
691 unsigned size, bool write,
692 ulong *linear)
693{
fd56e154 694 unsigned max_size;
d50eaa18
NA		 695 return __linearize(ctxt, addr, &max_size, size, write, false,
696 ctxt->mode, linear);
3d9b938e
NE		 697}
698
d50eaa18
NA		 699static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
700 enum x86emul_mode mode)
701{
702 ulong linear;
703 int rc;
704 unsigned max_size;
705 struct segmented_address addr = { .seg = VCPU_SREG_CS,
706 .ea = dst };
707
708 if (ctxt->op_bytes != sizeof(unsigned long))
709 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
710 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
711 if (rc == X86EMUL_CONTINUE)
712 ctxt->_eip = addr.ea;
713 return rc;
714}
715
716static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
717{
718 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 719}
720
d50eaa18
NA		 721static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
722 const struct desc_struct *cs_desc)
723{
724 enum x86emul_mode mode = ctxt->mode;
725
726#ifdef CONFIG_X86_64
727 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
728 u64 efer = 0;
729
730 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
731 if (efer & EFER_LMA)
732 mode = X86EMUL_MODE_PROT64;
733 }
734#endif
735 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
736 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
737 return assign_eip(ctxt, dst, mode);
738}
739
740static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
741{
742 return assign_eip_near(ctxt, ctxt->_eip + rel);
743}
3d9b938e 744
3ca3ac4d
AK		 745static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
746 struct segmented_address addr,
747 void *data,
748 unsigned size)
749{
9fa088f4
AK		 750 int rc;
751 ulong linear;
752
83b8795a 753 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 754 if (rc != X86EMUL_CONTINUE)
755 return rc;
0f65dd70 756 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 757}
758
807941b1 759/*
285ca9e9 760 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 761 * boundary if they are not in fetch_cache yet.
762 */
9506d57d 763static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 764{
62266869 765 int rc;
fd56e154 766 unsigned size, max_size;
285ca9e9 767 unsigned long linear;
17052f16 768 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 769 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 770 .ea = ctxt->eip + cur_size };
771
fd56e154
PB		 772 /*
773 * We do not know exactly how many bytes will be needed, and
774 * __linearize is expensive, so fetch as much as possible. We
775 * just have to avoid going beyond the 15 byte limit, the end
776 * of the segment, or the end of the page.
777 *
778 * __linearize is called with size 0 so that it does not do any
779 * boundary check itself. Instead, we use max_size to check
780 * against op_size.
781 */
d50eaa18
NA		 782 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
783 &linear);
719d5a9b
PB		 784 if (unlikely(rc != X86EMUL_CONTINUE))
785 return rc;
786
fd56e154 787 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 788 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 789
790 /*
791 * One instruction can only straddle two pages,
792 * and one has been loaded at the beginning of
793 * x86_decode_insn. So, if not enough bytes
794 * still, we must have hit the 15-byte boundary.
795 */
796 if (unlikely(size < op_size))
fd56e154
PB		 797 return emulate_gp(ctxt, 0);
798
17052f16 799 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 800 size, &ctxt->exception);
801 if (unlikely(rc != X86EMUL_CONTINUE))
802 return rc;
17052f16 803 ctxt->fetch.end += size;
3e2815e9 804 return X86EMUL_CONTINUE;
62266869
AK		 805}
806
9506d57d
PB		 807static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
808 unsigned size)
62266869 809{
08da44ae
NA		 810 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
811
812 if (unlikely(done_size < size))
813 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 814 else
815 return X86EMUL_CONTINUE;
62266869
AK		 816}
817
67cbc90d 818/* Fetch next part of the instruction being emulated. */
e85a1085 819#define insn_fetch(_type, _ctxt) \
9506d57d 820({ _type _x; \
9506d57d
PB		 821 \
822 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 823 if (rc != X86EMUL_CONTINUE) \
824 goto done; \
9506d57d 825 ctxt->_eip += sizeof(_type); \
17052f16
PB		 826 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
827 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 828 _x; \
67cbc90d
TY		 829})
830
807941b1 831#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 832({ \
9506d57d 833 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 834 if (rc != X86EMUL_CONTINUE) \
835 goto done; \
9506d57d 836 ctxt->_eip += (_size); \
17052f16
PB		 837 memcpy(_arr, ctxt->fetch.ptr, _size); \
838 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 839})
840
1e3c5cb0
RR		 841/*
842 * Given the 'reg' portion of a ModRM byte, and a register block, return a
843 * pointer into the block that addresses the relevant register.
844 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
845 */
dd856efa 846static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 847 int byteop)
6aa8b732
AK		 848{
849 void *p;
aa9ac1a6 850 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 851
6aa8b732 852 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 853 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
854 else
855 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 856 return p;
857}
858
859static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 860 struct segmented_address addr,
6aa8b732
AK		 861 u16 *size, unsigned long *address, int op_bytes)
862{
863 int rc;
864
865 if (op_bytes == 2)
866 op_bytes = 3;
867 *address = 0;
3ca3ac4d 868 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 869 if (rc != X86EMUL_CONTINUE)
6aa8b732 870 return rc;
30b31ab6 871 addr.ea += 2;
3ca3ac4d 872 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 873 return rc;
874}
875
34b77652
AK		 876FASTOP2(add);
877FASTOP2(or);
878FASTOP2(adc);
879FASTOP2(sbb);
880FASTOP2(and);
881FASTOP2(sub);
882FASTOP2(xor);
883FASTOP2(cmp);
884FASTOP2(test);
885
b9fa409b
AK		 886FASTOP1SRC2(mul, mul_ex);
887FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 888FASTOP1SRC2EX(div, div_ex);
889FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 890
34b77652
AK		 891FASTOP3WCL(shld);
892FASTOP3WCL(shrd);
893
894FASTOP2W(imul);
895
896FASTOP1(not);
897FASTOP1(neg);
898FASTOP1(inc);
899FASTOP1(dec);
900
901FASTOP2CL(rol);
902FASTOP2CL(ror);
903FASTOP2CL(rcl);
904FASTOP2CL(rcr);
905FASTOP2CL(shl);
906FASTOP2CL(shr);
907FASTOP2CL(sar);
908
909FASTOP2W(bsf);
910FASTOP2W(bsr);
911FASTOP2W(bt);
912FASTOP2W(bts);
913FASTOP2W(btr);
914FASTOP2W(btc);
915
e47a5f5f
AK		 916FASTOP2(xadd);
917
5aca3722
NA		 918FASTOP2R(cmp, cmp_r);
919
9ae9feba 920static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 921{
9ae9feba
AK		 922 u8 rc;
923 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 924
9ae9feba 925 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 926 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 927 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
928 return rc;
bbe9abbd
NK		 929}
930
91ff3cb4
AK		 931static void fetch_register_operand(struct operand *op)
932{
933 switch (op->bytes) {
934 case 1:
935 op->val = *(u8 *)op->addr.reg;
936 break;
937 case 2:
938 op->val = *(u16 *)op->addr.reg;
939 break;
940 case 4:
941 op->val = *(u32 *)op->addr.reg;
942 break;
943 case 8:
944 op->val = *(u64 *)op->addr.reg;
945 break;
946 }
947}
948
1253791d
AK		 949static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
950{
951 ctxt->ops->get_fpu(ctxt);
952 switch (reg) {
89a87c67
MK		 953 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
954 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
955 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
956 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
957 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
958 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
959 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
960 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 961#ifdef CONFIG_X86_64
89a87c67
MK		 962 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
963 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
964 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
965 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
966 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
967 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
968 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
969 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 970#endif
971 default: BUG();
972 }
973 ctxt->ops->put_fpu(ctxt);
974}
975
976static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
977 int reg)
978{
979 ctxt->ops->get_fpu(ctxt);
980 switch (reg) {
89a87c67
MK		 981 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
982 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
983 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
984 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
985 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
986 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
987 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
988 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 989#ifdef CONFIG_X86_64
89a87c67
MK		 990 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
991 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
992 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
993 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
994 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
995 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
996 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
997 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 998#endif
999 default: BUG();
1000 }
1001 ctxt->ops->put_fpu(ctxt);
1002}
1003
cbe2c9d3
AK		 1004static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1005{
1006 ctxt->ops->get_fpu(ctxt);
1007 switch (reg) {
1008 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1009 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1010 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1011 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1012 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1013 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1014 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1015 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1016 default: BUG();
1017 }
1018 ctxt->ops->put_fpu(ctxt);
1019}
1020
1021static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1022{
1023 ctxt->ops->get_fpu(ctxt);
1024 switch (reg) {
1025 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1026 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1027 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1028 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1029 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1030 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1031 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1032 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1033 default: BUG();
1034 }
1035 ctxt->ops->put_fpu(ctxt);
1036}
1037
045a282c
GN		 1038static int em_fninit(struct x86_emulate_ctxt *ctxt)
1039{
1040 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1041 return emulate_nm(ctxt);
1042
1043 ctxt->ops->get_fpu(ctxt);
1044 asm volatile("fninit");
1045 ctxt->ops->put_fpu(ctxt);
1046 return X86EMUL_CONTINUE;
1047}
1048
1049static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1050{
1051 u16 fcw;
1052
1053 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1054 return emulate_nm(ctxt);
1055
1056 ctxt->ops->get_fpu(ctxt);
1057 asm volatile("fnstcw %0": "+m"(fcw));
1058 ctxt->ops->put_fpu(ctxt);
1059
1060 /* force 2 byte destination */
1061 ctxt->dst.bytes = 2;
1062 ctxt->dst.val = fcw;
1063
1064 return X86EMUL_CONTINUE;
1065}
1066
1067static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1068{
1069 u16 fsw;
1070
1071 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1072 return emulate_nm(ctxt);
1073
1074 ctxt->ops->get_fpu(ctxt);
1075 asm volatile("fnstsw %0": "+m"(fsw));
1076 ctxt->ops->put_fpu(ctxt);
1077
1078 /* force 2 byte destination */
1079 ctxt->dst.bytes = 2;
1080 ctxt->dst.val = fsw;
1081
1082 return X86EMUL_CONTINUE;
1083}
1084
1253791d 1085static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1086 struct operand *op)
3c118e24 1087{
9dac77fa 1088 unsigned reg = ctxt->modrm_reg;
33615aa9 1089
9dac77fa
AK		 1090 if (!(ctxt->d & ModRM))
1091 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1092
9dac77fa 1093 if (ctxt->d & Sse) {
1253791d
AK		 1094 op->type = OP_XMM;
1095 op->bytes = 16;
1096 op->addr.xmm = reg;
1097 read_sse_reg(ctxt, &op->vec_val, reg);
1098 return;
1099 }
cbe2c9d3
AK		 1100 if (ctxt->d & Mmx) {
1101 reg &= 7;
1102 op->type = OP_MM;
1103 op->bytes = 8;
1104 op->addr.mm = reg;
1105 return;
1106 }
1253791d 1107
3c118e24 1108 op->type = OP_REG;
6d4d85ec
GN		 1109 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1110 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1111
91ff3cb4 1112 fetch_register_operand(op);
3c118e24
AK		 1113 op->orig_val = op->val;
1114}
1115
a6e3407b
AK		 1116static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1117{
1118 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1119 ctxt->modrm_seg = VCPU_SREG_SS;
1120}
1121
1c73ef66 1122static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1123 struct operand *op)
1c73ef66 1124{
1c73ef66 1125 u8 sib;
02357bdc 1126 int index_reg, base_reg, scale;
3e2815e9 1127 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1128 ulong modrm_ea = 0;
1c73ef66 1129
02357bdc
BD		 1130 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1131 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1132 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1133
02357bdc 1134 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1135 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1136 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1137 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1138
9b88ae99 1139 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1140 op->type = OP_REG;
9dac77fa 1141 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1142 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1143 ctxt->d & ByteOp);
9dac77fa 1144 if (ctxt->d & Sse) {
1253791d
AK		 1145 op->type = OP_XMM;
1146 op->bytes = 16;
9dac77fa
AK		 1147 op->addr.xmm = ctxt->modrm_rm;
1148 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1149 return rc;
1150 }
cbe2c9d3
AK		 1151 if (ctxt->d & Mmx) {
1152 op->type = OP_MM;
1153 op->bytes = 8;
bdc90722 1154 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1155 return rc;
1156 }
2dbd0dd7 1157 fetch_register_operand(op);
1c73ef66
AK		 1158 return rc;
1159 }
1160
2dbd0dd7
AK		 1161 op->type = OP_MEM;
1162
9dac77fa 1163 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1164 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1165 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1166 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1167 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1168
1169 /* 16-bit ModR/M decode. */
9dac77fa 1170 switch (ctxt->modrm_mod) {
1c73ef66 1171 case 0:
9dac77fa 1172 if (ctxt->modrm_rm == 6)
e85a1085 1173 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1174 break;
1175 case 1:
e85a1085 1176 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1177 break;
1178 case 2:
e85a1085 1179 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1180 break;
1181 }
9dac77fa 1182 switch (ctxt->modrm_rm) {
1c73ef66 1183 case 0:
2dbd0dd7 1184 modrm_ea += bx + si;
1c73ef66
AK		 1185 break;
1186 case 1:
2dbd0dd7 1187 modrm_ea += bx + di;
1c73ef66
AK		 1188 break;
1189 case 2:
2dbd0dd7 1190 modrm_ea += bp + si;
1c73ef66
AK		 1191 break;
1192 case 3:
2dbd0dd7 1193 modrm_ea += bp + di;
1c73ef66
AK		 1194 break;
1195 case 4:
2dbd0dd7 1196 modrm_ea += si;
1c73ef66
AK		 1197 break;
1198 case 5:
2dbd0dd7 1199 modrm_ea += di;
1c73ef66
AK		 1200 break;
1201 case 6:
9dac77fa 1202 if (ctxt->modrm_mod != 0)
2dbd0dd7 1203 modrm_ea += bp;
1c73ef66
AK		 1204 break;
1205 case 7:
2dbd0dd7 1206 modrm_ea += bx;
1c73ef66
AK		 1207 break;
1208 }
9dac77fa
AK		 1209 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1210 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1211 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1212 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1213 } else {
1214 /* 32/64-bit ModR/M decode. */
9dac77fa 1215 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1216 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1217 index_reg |= (sib >> 3) & 7;
1218 base_reg |= sib & 7;
1219 scale = sib >> 6;
1220
9dac77fa 1221 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1222 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1223 else {
dd856efa 1224 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1225 adjust_modrm_seg(ctxt, base_reg);
1226 }
dc71d0f1 1227 if (index_reg != 4)
dd856efa 1228 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1229 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1230 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1231 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1232 ctxt->rip_relative = 1;
a6e3407b
AK		 1233 } else {
1234 base_reg = ctxt->modrm_rm;
dd856efa 1235 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1236 adjust_modrm_seg(ctxt, base_reg);
1237 }
9dac77fa 1238 switch (ctxt->modrm_mod) {
1c73ef66 1239 case 1:
e85a1085 1240 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1241 break;
1242 case 2:
e85a1085 1243 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1244 break;
1245 }
1246 }
90de84f5 1247 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1248 if (ctxt->ad_bytes != 8)
1249 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1250
1c73ef66
AK		 1251done:
1252 return rc;
1253}
1254
1255static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1256 struct operand *op)
1c73ef66 1257{
3e2815e9 1258 int rc = X86EMUL_CONTINUE;
1c73ef66 1259
2dbd0dd7 1260 op->type = OP_MEM;
9dac77fa 1261 switch (ctxt->ad_bytes) {
1c73ef66 1262 case 2:
e85a1085 1263 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1264 break;
1265 case 4:
e85a1085 1266 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1267 break;
1268 case 8:
e85a1085 1269 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1270 break;
1271 }
1272done:
1273 return rc;
1274}
1275
9dac77fa 1276static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1277{
7129eeca 1278 long sv = 0, mask;
35c843c4 1279
9dac77fa 1280 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1281 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1282
9dac77fa
AK		 1283 if (ctxt->src.bytes == 2)
1284 sv = (s16)ctxt->src.val & (s16)mask;
1285 else if (ctxt->src.bytes == 4)
1286 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1287 else
1288 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1289
1c1c35ae
NA		 1290 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1291 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1292 }
ba7ff2b7
WY		 1293
1294 /* only subword offset */
9dac77fa 1295 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1296}
1297
dde7e6d1 1298static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1299 unsigned long addr, void *dest, unsigned size)
6aa8b732 1300{
dde7e6d1 1301 int rc;
9dac77fa 1302 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1303
f23b070e
XG		 1304 if (mc->pos < mc->end)
1305 goto read_cached;
6aa8b732 1306
f23b070e
XG		 1307 WARN_ON((mc->end + size) >= sizeof(mc->data));
1308
1309 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1310 &ctxt->exception);
1311 if (rc != X86EMUL_CONTINUE)
1312 return rc;
1313
1314 mc->end += size;
1315
1316read_cached:
1317 memcpy(dest, mc->data + mc->pos, size);
1318 mc->pos += size;
dde7e6d1
AK		 1319 return X86EMUL_CONTINUE;
1320}
6aa8b732 1321
3ca3ac4d
AK		 1322static int segmented_read(struct x86_emulate_ctxt *ctxt,
1323 struct segmented_address addr,
1324 void *data,
1325 unsigned size)
1326{
9fa088f4
AK		 1327 int rc;
1328 ulong linear;
1329
83b8795a 1330 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1331 if (rc != X86EMUL_CONTINUE)
1332 return rc;
7b105ca2 1333 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1334}
1335
1336static int segmented_write(struct x86_emulate_ctxt *ctxt,
1337 struct segmented_address addr,
1338 const void *data,
1339 unsigned size)
1340{
9fa088f4
AK		 1341 int rc;
1342 ulong linear;
1343
83b8795a 1344 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1345 if (rc != X86EMUL_CONTINUE)
1346 return rc;
0f65dd70
AK		 1347 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1348 &ctxt->exception);
3ca3ac4d
AK		 1349}
1350
1351static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1352 struct segmented_address addr,
1353 const void *orig_data, const void *data,
1354 unsigned size)
1355{
9fa088f4
AK		 1356 int rc;
1357 ulong linear;
1358
83b8795a 1359 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1360 if (rc != X86EMUL_CONTINUE)
1361 return rc;
0f65dd70
AK		 1362 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1363 size, &ctxt->exception);
3ca3ac4d
AK		 1364}
1365
dde7e6d1 1366static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1367 unsigned int size, unsigned short port,
1368 void *dest)
1369{
9dac77fa 1370 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1371
dde7e6d1 1372 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1373 unsigned int in_page, n;
9dac77fa 1374 unsigned int count = ctxt->rep_prefix ?
dd856efa 1375 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1376 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1377 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1378 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1379 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1380 if (n == 0)
1381 n = 1;
1382 rc->pos = rc->end = 0;
7b105ca2 1383 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1384 return 0;
1385 rc->end = n * size;
6aa8b732
AK		 1386 }
1387
e6e39f04
NA		 1388 if (ctxt->rep_prefix && (ctxt->d & String) &&
1389 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1390 ctxt->dst.data = rc->data + rc->pos;
1391 ctxt->dst.type = OP_MEM_STR;
1392 ctxt->dst.count = (rc->end - rc->pos) / size;
1393 rc->pos = rc->end;
1394 } else {
1395 memcpy(dest, rc->data + rc->pos, size);
1396 rc->pos += size;
1397 }
dde7e6d1
AK		 1398 return 1;
1399}
6aa8b732 1400
7f3d35fd
KW		 1401static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1402 u16 index, struct desc_struct *desc)
1403{
1404 struct desc_ptr dt;
1405 ulong addr;
1406
1407 ctxt->ops->get_idt(ctxt, &dt);
1408
1409 if (dt.size < index * 8 + 7)
1410 return emulate_gp(ctxt, index << 3 | 0x2);
1411
1412 addr = dt.address + index * 8;
1413 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1414 &ctxt->exception);
1415}
1416
dde7e6d1 1417static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1418 u16 selector, struct desc_ptr *dt)
1419{
0225fb50 1420 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1421 u32 base3 = 0;
7b105ca2 1422
dde7e6d1
AK		 1423 if (selector & 1 << 2) {
1424 struct desc_struct desc;
1aa36616
AK		 1425 u16 sel;
1426
dde7e6d1 1427 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1428 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1429 VCPU_SREG_LDTR))
dde7e6d1 1430 return;
e09d082c 1431
dde7e6d1 1432 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1433 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1434 } else
4bff1e86 1435 ops->get_gdt(ctxt, dt);
dde7e6d1 1436}
120df890 1437
dde7e6d1
AK		 1438/* allowed just for 8 bytes segments */
1439static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1440 u16 selector, struct desc_struct *desc,
1441 ulong *desc_addr_p)
dde7e6d1
AK		 1442{
1443 struct desc_ptr dt;
1444 u16 index = selector >> 3;
dde7e6d1 1445 ulong addr;
120df890 1446
7b105ca2 1447 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1448
35d3d4a1
AK		 1449 if (dt.size < index * 8 + 7)
1450 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1451
e919464b 1452 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1453 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1454 &ctxt->exception);
dde7e6d1 1455}
ef65c889 1456
dde7e6d1
AK		 1457/* allowed just for 8 bytes segments */
1458static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1459 u16 selector, struct desc_struct *desc)
1460{
1461 struct desc_ptr dt;
1462 u16 index = selector >> 3;
dde7e6d1 1463 ulong addr;
6aa8b732 1464
7b105ca2 1465 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1466
35d3d4a1
AK		 1467 if (dt.size < index * 8 + 7)
1468 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1469
dde7e6d1 1470 addr = dt.address + index * 8;
7b105ca2
TY		 1471 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1472 &ctxt->exception);
dde7e6d1 1473}
c7e75a3d 1474
5601d05b 1475/* Does not support long mode */
2356aaeb 1476static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1477 u16 selector, int seg, u8 cpl,
1478 bool in_task_switch,
1479 struct desc_struct *desc)
dde7e6d1 1480{
869be99c 1481 struct desc_struct seg_desc, old_desc;
2356aaeb 1482 u8 dpl, rpl;
dde7e6d1
AK		 1483 unsigned err_vec = GP_VECTOR;
1484 u32 err_code = 0;
1485 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1486 ulong desc_addr;
dde7e6d1 1487 int ret;
03ebebeb 1488 u16 dummy;
e37a75a1 1489 u32 base3 = 0;
69f55cb1 1490
dde7e6d1 1491 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1492
f8da94e9
KW		 1493 if (ctxt->mode == X86EMUL_MODE_REAL) {
1494 /* set real mode segment descriptor (keep limit etc. for
1495 * unreal mode) */
03ebebeb 1496 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1497 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1498 goto load;
f8da94e9
KW		 1499 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1500 /* VM86 needs a clean new segment descriptor */
1501 set_desc_base(&seg_desc, selector << 4);
1502 set_desc_limit(&seg_desc, 0xffff);
1503 seg_desc.type = 3;
1504 seg_desc.p = 1;
1505 seg_desc.s = 1;
1506 seg_desc.dpl = 3;
1507 goto load;
dde7e6d1
AK		 1508 }
1509
79d5b4c3 1510 rpl = selector & 3;
79d5b4c3
AK		 1511
1512 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1513 if ((seg == VCPU_SREG_CS
1514 || (seg == VCPU_SREG_SS
1515 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1516 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1517 && null_selector)
1518 goto exception;
1519
1520 /* TR should be in GDT only */
1521 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1522 goto exception;
1523
1524 if (null_selector) /* for NULL selector skip all following checks */
1525 goto load;
1526
e919464b 1527 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1528 if (ret != X86EMUL_CONTINUE)
1529 return ret;
1530
1531 err_code = selector & 0xfffc;
15fc0752 1532 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1533
fc058680 1534 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1535 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1536 goto exception;
1537
1538 if (!seg_desc.p) {
1539 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1540 goto exception;
1541 }
1542
dde7e6d1 1543 dpl = seg_desc.dpl;
dde7e6d1
AK		 1544
1545 switch (seg) {
1546 case VCPU_SREG_SS:
1547 /*
1548 * segment is not a writable data segment or segment
1549 * selector's RPL != CPL or segment selector's RPL != CPL
1550 */
1551 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1552 goto exception;
6aa8b732 1553 break;
dde7e6d1
AK		 1554 case VCPU_SREG_CS:
1555 if (!(seg_desc.type & 8))
1556 goto exception;
1557
1558 if (seg_desc.type & 4) {
1559 /* conforming */
1560 if (dpl > cpl)
1561 goto exception;
1562 } else {
1563 /* nonconforming */
1564 if (rpl > cpl || dpl != cpl)
1565 goto exception;
1566 }
040c8dc8
NA		 1567 /* in long-mode d/b must be clear if l is set */
1568 if (seg_desc.d && seg_desc.l) {
1569 u64 efer = 0;
1570
1571 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1572 if (efer & EFER_LMA)
1573 goto exception;
1574 }
1575
dde7e6d1
AK		 1576 /* CS(RPL) <- CPL */
1577 selector = (selector & 0xfffc) | cpl;
6aa8b732 1578 break;
dde7e6d1
AK		 1579 case VCPU_SREG_TR:
1580 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1581 goto exception;
869be99c
AK		 1582 old_desc = seg_desc;
1583 seg_desc.type |= 2; /* busy */
1584 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1585 sizeof(seg_desc), &ctxt->exception);
1586 if (ret != X86EMUL_CONTINUE)
1587 return ret;
dde7e6d1
AK		 1588 break;
1589 case VCPU_SREG_LDTR:
1590 if (seg_desc.s || seg_desc.type != 2)
1591 goto exception;
1592 break;
1593 default: /* DS, ES, FS, or GS */
4e62417b 1594 /*
dde7e6d1
AK		 1595 * segment is not a data or readable code segment or
1596 * ((segment is a data or nonconforming code segment)
1597 * and (both RPL and CPL > DPL))
4e62417b 1598 */
dde7e6d1
AK		 1599 if ((seg_desc.type & 0xa) == 0x8 ||
1600 (((seg_desc.type & 0xc) != 0xc) &&
1601 (rpl > dpl && cpl > dpl)))
1602 goto exception;
6aa8b732 1603 break;
dde7e6d1
AK		 1604 }
1605
1606 if (seg_desc.s) {
1607 /* mark segment as accessed */
1608 seg_desc.type |= 1;
7b105ca2 1609 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1610 if (ret != X86EMUL_CONTINUE)
1611 return ret;
e37a75a1
NA		 1612 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1613 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1614 sizeof(base3), &ctxt->exception);
1615 if (ret != X86EMUL_CONTINUE)
1616 return ret;
9a9abf6b
NA		 1617 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1618 ((u64)base3 << 32)))
1619 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1620 }
1621load:
e37a75a1 1622 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1623 if (desc)
1624 *desc = seg_desc;
dde7e6d1
AK		 1625 return X86EMUL_CONTINUE;
1626exception:
592f0858 1627 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1628}
1629
2356aaeb
PB		 1630static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1631 u16 selector, int seg)
1632{
1633 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1634 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1635}
1636
31be40b3
WY		 1637static void write_register_operand(struct operand *op)
1638{
1639 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1640 switch (op->bytes) {
1641 case 1:
1642 *(u8 *)op->addr.reg = (u8)op->val;
1643 break;
1644 case 2:
1645 *(u16 *)op->addr.reg = (u16)op->val;
1646 break;
1647 case 4:
1648 *op->addr.reg = (u32)op->val;
1649 break; /* 64b: zero-extend */
1650 case 8:
1651 *op->addr.reg = op->val;
1652 break;
1653 }
1654}
1655
fb32b1ed 1656static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1657{
fb32b1ed 1658 switch (op->type) {
dde7e6d1 1659 case OP_REG:
fb32b1ed 1660 write_register_operand(op);
6aa8b732 1661 break;
dde7e6d1 1662 case OP_MEM:
9dac77fa 1663 if (ctxt->lock_prefix)
f5f87dfb
PB		 1664 return segmented_cmpxchg(ctxt,
1665 op->addr.mem,
1666 &op->orig_val,
1667 &op->val,
1668 op->bytes);
1669 else
1670 return segmented_write(ctxt,
fb32b1ed 1671 op->addr.mem,
fb32b1ed
AK		 1672 &op->val,
1673 op->bytes);
a682e354 1674 break;
b3356bf0 1675 case OP_MEM_STR:
f5f87dfb
PB		 1676 return segmented_write(ctxt,
1677 op->addr.mem,
1678 op->data,
1679 op->bytes * op->count);
b3356bf0 1680 break;
1253791d 1681 case OP_XMM:
fb32b1ed 1682 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1683 break;
cbe2c9d3 1684 case OP_MM:
fb32b1ed 1685 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1686 break;
dde7e6d1
AK		 1687 case OP_NONE:
1688 /* no writeback */
414e6277 1689 break;
dde7e6d1 1690 default:
414e6277 1691 break;
6aa8b732 1692 }
dde7e6d1
AK		 1693 return X86EMUL_CONTINUE;
1694}
6aa8b732 1695
51ddff50 1696static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1697{
4179bb02 1698 struct segmented_address addr;
0dc8d10f 1699
5ad105e5 1700 rsp_increment(ctxt, -bytes);
dd856efa 1701 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1702 addr.seg = VCPU_SREG_SS;
1703
51ddff50
AK		 1704 return segmented_write(ctxt, addr, data, bytes);
1705}
1706
1707static int em_push(struct x86_emulate_ctxt *ctxt)
1708{
4179bb02 1709 /* Disable writeback. */
9dac77fa 1710 ctxt->dst.type = OP_NONE;
51ddff50 1711 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1712}
69f55cb1 1713
dde7e6d1 1714static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1715 void *dest, int len)
1716{
dde7e6d1 1717 int rc;
90de84f5 1718 struct segmented_address addr;
8b4caf66 1719
dd856efa 1720 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1721 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1722 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1723 if (rc != X86EMUL_CONTINUE)
1724 return rc;
1725
5ad105e5 1726 rsp_increment(ctxt, len);
dde7e6d1 1727 return rc;
8b4caf66
LV		 1728}
1729
c54fe504
TY		 1730static int em_pop(struct x86_emulate_ctxt *ctxt)
1731{
9dac77fa 1732 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1733}
1734
dde7e6d1 1735static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1736 void *dest, int len)
9de41573
GN		 1737{
1738 int rc;
dde7e6d1
AK		 1739 unsigned long val, change_mask;
1740 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1741 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1742
3b9be3bf 1743 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1744 if (rc != X86EMUL_CONTINUE)
1745 return rc;
9de41573 1746
dde7e6d1 1747 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1748 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1749
dde7e6d1
AK		 1750 switch(ctxt->mode) {
1751 case X86EMUL_MODE_PROT64:
1752 case X86EMUL_MODE_PROT32:
1753 case X86EMUL_MODE_PROT16:
1754 if (cpl == 0)
1755 change_mask |= EFLG_IOPL;
1756 if (cpl <= iopl)
1757 change_mask |= EFLG_IF;
1758 break;
1759 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1760 if (iopl < 3)
1761 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1762 change_mask |= EFLG_IF;
1763 break;
1764 default: /* real mode */
1765 change_mask |= (EFLG_IOPL | EFLG_IF);
1766 break;
9de41573 1767 }
dde7e6d1
AK		 1768
1769 *(unsigned long *)dest =
1770 (ctxt->eflags & ~change_mask) | (val & change_mask);
1771
1772 return rc;
9de41573
GN		 1773}
1774
62aaa2f0
TY		 1775static int em_popf(struct x86_emulate_ctxt *ctxt)
1776{
9dac77fa
AK		 1777 ctxt->dst.type = OP_REG;
1778 ctxt->dst.addr.reg = &ctxt->eflags;
1779 ctxt->dst.bytes = ctxt->op_bytes;
1780 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1781}
1782
612e89f0
AK		 1783static int em_enter(struct x86_emulate_ctxt *ctxt)
1784{
1785 int rc;
1786 unsigned frame_size = ctxt->src.val;
1787 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1788 ulong rbp;
612e89f0
AK		 1789
1790 if (nesting_level)
1791 return X86EMUL_UNHANDLEABLE;
1792
dd856efa
AK		 1793 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1794 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1795 if (rc != X86EMUL_CONTINUE)
1796 return rc;
dd856efa 1797 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1798 stack_mask(ctxt));
dd856efa
AK		 1799 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1800 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1801 stack_mask(ctxt));
1802 return X86EMUL_CONTINUE;
1803}
1804
f47cfa31
AK		 1805static int em_leave(struct x86_emulate_ctxt *ctxt)
1806{
dd856efa 1807 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1808 stack_mask(ctxt));
dd856efa 1809 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1810}
1811
1cd196ea 1812static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1813{
1cd196ea
AK		 1814 int seg = ctxt->src2.val;
1815
9dac77fa 1816 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1817 if (ctxt->op_bytes == 4) {
1818 rsp_increment(ctxt, -2);
1819 ctxt->op_bytes = 2;
1820 }
7b262e90 1821
4487b3b4 1822 return em_push(ctxt);
7b262e90
GN		 1823}
1824
1cd196ea 1825static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1826{
1cd196ea 1827 int seg = ctxt->src2.val;
dde7e6d1
AK		 1828 unsigned long selector;
1829 int rc;
38ba30ba 1830
3313bc4e 1831 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1832 if (rc != X86EMUL_CONTINUE)
1833 return rc;
1834
a5457e7b
PB		 1835 if (ctxt->modrm_reg == VCPU_SREG_SS)
1836 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1837 if (ctxt->op_bytes > 2)
1838 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1839
7b105ca2 1840 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1841 return rc;
38ba30ba
GN		 1842}
1843
b96a7fad 1844static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1845{
dd856efa 1846 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1847 int rc = X86EMUL_CONTINUE;
1848 int reg = VCPU_REGS_RAX;
38ba30ba 1849
dde7e6d1
AK		 1850 while (reg <= VCPU_REGS_RDI) {
1851 (reg == VCPU_REGS_RSP) ?
dd856efa 1852 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1853
4487b3b4 1854 rc = em_push(ctxt);
dde7e6d1
AK		 1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
38ba30ba 1857
dde7e6d1 1858 ++reg;
38ba30ba 1859 }
38ba30ba 1860
dde7e6d1 1861 return rc;
38ba30ba
GN		 1862}
1863
62aaa2f0
TY		 1864static int em_pushf(struct x86_emulate_ctxt *ctxt)
1865{
bc397a6c 1866 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1867 return em_push(ctxt);
1868}
1869
b96a7fad 1870static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1871{
dde7e6d1
AK		 1872 int rc = X86EMUL_CONTINUE;
1873 int reg = VCPU_REGS_RDI;
38ba30ba 1874
dde7e6d1
AK		 1875 while (reg >= VCPU_REGS_RAX) {
1876 if (reg == VCPU_REGS_RSP) {
5ad105e5 1877 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1878 --reg;
1879 }
38ba30ba 1880
dd856efa 1881 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1882 if (rc != X86EMUL_CONTINUE)
1883 break;
1884 --reg;
38ba30ba 1885 }
dde7e6d1 1886 return rc;
38ba30ba
GN		 1887}
1888
dd856efa 1889static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1890{
0225fb50 1891 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1892 int rc;
6e154e56
MG		 1893 struct desc_ptr dt;
1894 gva_t cs_addr;
1895 gva_t eip_addr;
1896 u16 cs, eip;
6e154e56
MG		 1897
1898 /* TODO: Add limit checks */
9dac77fa 1899 ctxt->src.val = ctxt->eflags;
4487b3b4 1900 rc = em_push(ctxt);
5c56e1cf
AK		 1901 if (rc != X86EMUL_CONTINUE)
1902 return rc;
6e154e56
MG		 1903
1904 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1905
9dac77fa 1906 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1907 rc = em_push(ctxt);
5c56e1cf
AK		 1908 if (rc != X86EMUL_CONTINUE)
1909 return rc;
6e154e56 1910
9dac77fa 1911 ctxt->src.val = ctxt->_eip;
4487b3b4 1912 rc = em_push(ctxt);
5c56e1cf
AK		 1913 if (rc != X86EMUL_CONTINUE)
1914 return rc;
1915
4bff1e86 1916 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1917
1918 eip_addr = dt.address + (irq << 2);
1919 cs_addr = dt.address + (irq << 2) + 2;
1920
0f65dd70 1921 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
1924
0f65dd70 1925 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1926 if (rc != X86EMUL_CONTINUE)
1927 return rc;
1928
7b105ca2 1929 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
1932
9dac77fa 1933 ctxt->_eip = eip;
6e154e56
MG		 1934
1935 return rc;
1936}
1937
dd856efa
AK		 1938int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1939{
1940 int rc;
1941
1942 invalidate_registers(ctxt);
1943 rc = __emulate_int_real(ctxt, irq);
1944 if (rc == X86EMUL_CONTINUE)
1945 writeback_registers(ctxt);
1946 return rc;
1947}
1948
7b105ca2 1949static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1950{
1951 switch(ctxt->mode) {
1952 case X86EMUL_MODE_REAL:
dd856efa 1953 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1954 case X86EMUL_MODE_VM86:
1955 case X86EMUL_MODE_PROT16:
1956 case X86EMUL_MODE_PROT32:
1957 case X86EMUL_MODE_PROT64:
1958 default:
1959 /* Protected mode interrupts unimplemented yet */
1960 return X86EMUL_UNHANDLEABLE;
1961 }
1962}
1963
7b105ca2 1964static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1965{
dde7e6d1
AK		 1966 int rc = X86EMUL_CONTINUE;
1967 unsigned long temp_eip = 0;
1968 unsigned long temp_eflags = 0;
1969 unsigned long cs = 0;
1970 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1971 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1972 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1973 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1974
dde7e6d1 1975 /* TODO: Add stack limit check */
38ba30ba 1976
9dac77fa 1977 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1978
dde7e6d1
AK		 1979 if (rc != X86EMUL_CONTINUE)
1980 return rc;
38ba30ba 1981
35d3d4a1
AK		 1982 if (temp_eip & ~0xffff)
1983 return emulate_gp(ctxt, 0);
38ba30ba 1984
9dac77fa 1985 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1986
dde7e6d1
AK		 1987 if (rc != X86EMUL_CONTINUE)
1988 return rc;
38ba30ba 1989
9dac77fa 1990 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1991
dde7e6d1
AK		 1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
38ba30ba 1994
7b105ca2 1995 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1996
dde7e6d1
AK		 1997 if (rc != X86EMUL_CONTINUE)
1998 return rc;
38ba30ba 1999
9dac77fa 2000 ctxt->_eip = temp_eip;
38ba30ba 2001
38ba30ba 2002
9dac77fa 2003 if (ctxt->op_bytes == 4)
dde7e6d1 2004 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2005 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2006 ctxt->eflags &= ~0xffff;
2007 ctxt->eflags |= temp_eflags;
38ba30ba 2008 }
dde7e6d1
AK		 2009
2010 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2011 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2012
2013 return rc;
38ba30ba
GN		 2014}
2015
e01991e7 2016static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2017{
dde7e6d1
AK		 2018 switch(ctxt->mode) {
2019 case X86EMUL_MODE_REAL:
7b105ca2 2020 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2021 case X86EMUL_MODE_VM86:
2022 case X86EMUL_MODE_PROT16:
2023 case X86EMUL_MODE_PROT32:
2024 case X86EMUL_MODE_PROT64:
c37eda13 2025 default:
dde7e6d1
AK		 2026 /* iret from protected mode unimplemented yet */
2027 return X86EMUL_UNHANDLEABLE;
c37eda13 2028 }
c37eda13
WY		 2029}
2030
d2f62766
TY		 2031static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2032{
d2f62766 2033 int rc;
d1442d85
NA		 2034 unsigned short sel, old_sel;
2035 struct desc_struct old_desc, new_desc;
2036 const struct x86_emulate_ops *ops = ctxt->ops;
2037 u8 cpl = ctxt->ops->cpl(ctxt);
2038
2039 /* Assignment of RIP may only fail in 64-bit mode */
2040 if (ctxt->mode == X86EMUL_MODE_PROT64)
2041 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2042 VCPU_SREG_CS);
d2f62766 2043
9dac77fa 2044 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2045
d1442d85
NA		 2046 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2047 &new_desc);
d2f62766
TY		 2048 if (rc != X86EMUL_CONTINUE)
2049 return rc;
2050
d50eaa18 2051 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2052 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2053 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2054 /* assigning eip failed; restore the old cs */
2055 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2056 return rc;
2057 }
2058 return rc;
d2f62766
TY		 2059}
2060
f7784046 2061static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2062{
f7784046
NA		 2063 return assign_eip_near(ctxt, ctxt->src.val);
2064}
8cdbd2c9 2065
f7784046
NA		 2066static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2067{
2068 int rc;
2069 long int old_eip;
2070
2071 old_eip = ctxt->_eip;
2072 rc = assign_eip_near(ctxt, ctxt->src.val);
2073 if (rc != X86EMUL_CONTINUE)
2074 return rc;
2075 ctxt->src.val = old_eip;
2076 rc = em_push(ctxt);
4179bb02 2077 return rc;
8cdbd2c9
LV		 2078}
2079
e0dac408 2080static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2081{
9dac77fa 2082 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2083
aaa05f24
NA		 2084 if (ctxt->dst.bytes == 16)
2085 return X86EMUL_UNHANDLEABLE;
2086
dd856efa
AK		 2087 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2088 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2089 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2090 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2091 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2092 } else {
dd856efa
AK		 2093 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2094 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2095
05f086f8 2096 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2097 }
1b30eaa8 2098 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2099}
2100
ebda02c2
TY		 2101static int em_ret(struct x86_emulate_ctxt *ctxt)
2102{
234f3ce4
NA		 2103 int rc;
2104 unsigned long eip;
2105
2106 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2107 if (rc != X86EMUL_CONTINUE)
2108 return rc;
2109
2110 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2111}
2112
e01991e7 2113static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2114{
a77ab5ea 2115 int rc;
d1442d85
NA		 2116 unsigned long eip, cs;
2117 u16 old_cs;
9e8919ae 2118 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2119 struct desc_struct old_desc, new_desc;
2120 const struct x86_emulate_ops *ops = ctxt->ops;
2121
2122 if (ctxt->mode == X86EMUL_MODE_PROT64)
2123 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2124 VCPU_SREG_CS);
a77ab5ea 2125
d1442d85 2126 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2127 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2128 return rc;
9dac77fa 2129 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2130 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2131 return rc;
9e8919ae
NA		 2132 /* Outer-privilege level return is not implemented */
2133 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2134 return X86EMUL_UNHANDLEABLE;
ab646f54 2135 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, false,
d1442d85
NA		 2136 &new_desc);
2137 if (rc != X86EMUL_CONTINUE)
2138 return rc;
d50eaa18 2139 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2140 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2141 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2142 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2143 }
a77ab5ea
AK		 2144 return rc;
2145}
2146
3261107e
BR		 2147static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2148{
2149 int rc;
2150
2151 rc = em_ret_far(ctxt);
2152 if (rc != X86EMUL_CONTINUE)
2153 return rc;
2154 rsp_increment(ctxt, ctxt->src.val);
2155 return X86EMUL_CONTINUE;
2156}
2157
e940b5c2
TY		 2158static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2159{
2160 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2161 ctxt->dst.orig_val = ctxt->dst.val;
2162 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2163 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2164 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2165 fastop(ctxt, em_cmp);
e940b5c2
TY		 2166
2167 if (ctxt->eflags & EFLG_ZF) {
2168 /* Success: write back to memory. */
2169 ctxt->dst.val = ctxt->src.orig_val;
2170 } else {
2171 /* Failure: write the value we saw to EAX. */
2172 ctxt->dst.type = OP_REG;
dd856efa 2173 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2174 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2175 }
2176 return X86EMUL_CONTINUE;
2177}
2178
d4b4325f 2179static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2180{
d4b4325f 2181 int seg = ctxt->src2.val;
09b5f4d3
WY		 2182 unsigned short sel;
2183 int rc;
2184
9dac77fa 2185 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2186
7b105ca2 2187 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2188 if (rc != X86EMUL_CONTINUE)
2189 return rc;
2190
9dac77fa 2191 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2192 return rc;
2193}
2194
7b105ca2 2195static void
e66bb2cc 2196setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2197 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2198{
e66bb2cc 2199 cs->l = 0; /* will be adjusted later */
79168fd1 2200 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2201 cs->g = 1; /* 4kb granularity */
79168fd1 2202 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2203 cs->type = 0x0b; /* Read, Execute, Accessed */
2204 cs->s = 1;
2205 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2206 cs->p = 1;
2207 cs->d = 1;
99245b50 2208 cs->avl = 0;
e66bb2cc 2209
79168fd1
GN		 2210 set_desc_base(ss, 0); /* flat segment */
2211 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2212 ss->g = 1; /* 4kb granularity */
2213 ss->s = 1;
2214 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2215 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2216 ss->dpl = 0;
79168fd1 2217 ss->p = 1;
99245b50
GN		 2218 ss->l = 0;
2219 ss->avl = 0;
e66bb2cc
AP		 2220}
2221
1a18a69b
AK		 2222static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2223{
2224 u32 eax, ebx, ecx, edx;
2225
2226 eax = ecx = 0;
0017f93a
AK		 2227 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2228 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2229 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2230 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2231}
2232
c2226fc9
SB		 2233static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2234{
0225fb50 2235 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2236 u32 eax, ebx, ecx, edx;
2237
2238 /*
2239 * syscall should always be enabled in longmode - so only become
2240 * vendor specific (cpuid) if other modes are active...
2241 */
2242 if (ctxt->mode == X86EMUL_MODE_PROT64)
2243 return true;
2244
2245 eax = 0x00000000;
2246 ecx = 0x00000000;
0017f93a
AK		 2247 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2248 /*
2249 * Intel ("GenuineIntel")
2250 * remark: Intel CPUs only support "syscall" in 64bit
2251 * longmode. Also an 64bit guest with a
2252 * 32bit compat-app running will #UD !! While this
2253 * behaviour can be fixed (by emulating) into AMD
2254 * response - CPUs of AMD can't behave like Intel.
2255 */
2256 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2257 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2258 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2259 return false;
2260
2261 /* AMD ("AuthenticAMD") */
2262 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2263 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2264 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2265 return true;
2266
2267 /* AMD ("AMDisbetter!") */
2268 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2269 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2270 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2271 return true;
c2226fc9
SB		 2272
2273 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2274 return false;
2275}
2276
e01991e7 2277static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2278{
0225fb50 2279 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2280 struct desc_struct cs, ss;
e66bb2cc 2281 u64 msr_data;
79168fd1 2282 u16 cs_sel, ss_sel;
c2ad2bb3 2283 u64 efer = 0;
e66bb2cc
AP		 2284
2285 /* syscall is not available in real mode */
2e901c4c 2286 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2287 ctxt->mode == X86EMUL_MODE_VM86)
2288 return emulate_ud(ctxt);
e66bb2cc 2289
c2226fc9
SB		 2290 if (!(em_syscall_is_enabled(ctxt)))
2291 return emulate_ud(ctxt);
2292
c2ad2bb3 2293 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2294 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2295
c2226fc9
SB		 2296 if (!(efer & EFER_SCE))
2297 return emulate_ud(ctxt);
2298
717746e3 2299 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2300 msr_data >>= 32;
79168fd1
GN		 2301 cs_sel = (u16)(msr_data & 0xfffc);
2302 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2303
c2ad2bb3 2304 if (efer & EFER_LMA) {
79168fd1 2305 cs.d = 0;
e66bb2cc
AP		 2306 cs.l = 1;
2307 }
1aa36616
AK		 2308 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2309 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2310
dd856efa 2311 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2312 if (efer & EFER_LMA) {
e66bb2cc 2313#ifdef CONFIG_X86_64
6c6cb69b 2314 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2315
717746e3 2316 ops->get_msr(ctxt,
3fb1b5db
GN		 2317 ctxt->mode == X86EMUL_MODE_PROT64 ?
2318 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2319 ctxt->_eip = msr_data;
e66bb2cc 2320
717746e3 2321 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2322 ctxt->eflags &= ~msr_data;
807c1425 2323 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2324#endif
2325 } else {
2326 /* legacy mode */
717746e3 2327 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2328 ctxt->_eip = (u32)msr_data;
e66bb2cc 2329
6c6cb69b 2330 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2331 }
2332
e54cfa97 2333 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2334}
2335
e01991e7 2336static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2337{
0225fb50 2338 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2339 struct desc_struct cs, ss;
8c604352 2340 u64 msr_data;
79168fd1 2341 u16 cs_sel, ss_sel;
c2ad2bb3 2342 u64 efer = 0;
8c604352 2343
7b105ca2 2344 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2345 /* inject #GP if in real mode */
35d3d4a1
AK		 2346 if (ctxt->mode == X86EMUL_MODE_REAL)
2347 return emulate_gp(ctxt, 0);
8c604352 2348
1a18a69b
AK		 2349 /*
2350 * Not recognized on AMD in compat mode (but is recognized in legacy
2351 * mode).
2352 */
2353 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2354 && !vendor_intel(ctxt))
2355 return emulate_ud(ctxt);
2356
b2c9d43e 2357 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2358 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2359 return X86EMUL_UNHANDLEABLE;
8c604352 2360
7b105ca2 2361 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2362
717746e3 2363 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2364 switch (ctxt->mode) {
2365 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2366 if ((msr_data & 0xfffc) == 0x0)
2367 return emulate_gp(ctxt, 0);
8c604352
AP		 2368 break;
2369 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2370 if (msr_data == 0x0)
2371 return emulate_gp(ctxt, 0);
8c604352 2372 break;
9d1b39a9
GN		 2373 default:
2374 break;
8c604352
AP		 2375 }
2376
6c6cb69b 2377 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2378 cs_sel = (u16)msr_data;
2379 cs_sel &= ~SELECTOR_RPL_MASK;
2380 ss_sel = cs_sel + 8;
2381 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2382 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2383 cs.d = 0;
8c604352
AP		 2384 cs.l = 1;
2385 }
2386
1aa36616
AK		 2387 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2388 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2389
717746e3 2390 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2391 ctxt->_eip = msr_data;
8c604352 2392
717746e3 2393 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2394 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2395
e54cfa97 2396 return X86EMUL_CONTINUE;
8c604352
AP		 2397}
2398
e01991e7 2399static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2400{
0225fb50 2401 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2402 struct desc_struct cs, ss;
234f3ce4 2403 u64 msr_data, rcx, rdx;
4668f050 2404 int usermode;
1249b96e 2405 u16 cs_sel = 0, ss_sel = 0;
4668f050 2406
a0044755
GN		 2407 /* inject #GP if in real mode or Virtual 8086 mode */
2408 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2409 ctxt->mode == X86EMUL_MODE_VM86)
2410 return emulate_gp(ctxt, 0);
4668f050 2411
7b105ca2 2412 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2413
9dac77fa 2414 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2415 usermode = X86EMUL_MODE_PROT64;
2416 else
2417 usermode = X86EMUL_MODE_PROT32;
2418
234f3ce4
NA		 2419 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2420 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2421
4668f050
AP		 2422 cs.dpl = 3;
2423 ss.dpl = 3;
717746e3 2424 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2425 switch (usermode) {
2426 case X86EMUL_MODE_PROT32:
79168fd1 2427 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2428 if ((msr_data & 0xfffc) == 0x0)
2429 return emulate_gp(ctxt, 0);
79168fd1 2430 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2431 rcx = (u32)rcx;
2432 rdx = (u32)rdx;
4668f050
AP		 2433 break;
2434 case X86EMUL_MODE_PROT64:
79168fd1 2435 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2436 if (msr_data == 0x0)
2437 return emulate_gp(ctxt, 0);
79168fd1
GN		 2438 ss_sel = cs_sel + 8;
2439 cs.d = 0;
4668f050 2440 cs.l = 1;
234f3ce4
NA		 2441 if (is_noncanonical_address(rcx) ||
2442 is_noncanonical_address(rdx))
2443 return emulate_gp(ctxt, 0);
4668f050
AP		 2444 break;
2445 }
79168fd1
GN		 2446 cs_sel |= SELECTOR_RPL_MASK;
2447 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2448
1aa36616
AK		 2449 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2450 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2451
234f3ce4
NA		 2452 ctxt->_eip = rdx;
2453 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2454
e54cfa97 2455 return X86EMUL_CONTINUE;
4668f050
AP		 2456}
2457
7b105ca2 2458static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2459{
2460 int iopl;
2461 if (ctxt->mode == X86EMUL_MODE_REAL)
2462 return false;
2463 if (ctxt->mode == X86EMUL_MODE_VM86)
2464 return true;
2465 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2466 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2467}
2468
2469static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2470 u16 port, u16 len)
2471{
0225fb50 2472 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2473 struct desc_struct tr_seg;
5601d05b 2474 u32 base3;
f850e2e6 2475 int r;
1aa36616 2476 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2477 unsigned mask = (1 << len) - 1;
5601d05b 2478 unsigned long base;
f850e2e6 2479
1aa36616 2480 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2481 if (!tr_seg.p)
f850e2e6 2482 return false;
79168fd1 2483 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2484 return false;
5601d05b
GN		 2485 base = get_desc_base(&tr_seg);
2486#ifdef CONFIG_X86_64
2487 base |= ((u64)base3) << 32;
2488#endif
0f65dd70 2489 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2490 if (r != X86EMUL_CONTINUE)
2491 return false;
79168fd1 2492 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2493 return false;
0f65dd70 2494 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2495 if (r != X86EMUL_CONTINUE)
2496 return false;
2497 if ((perm >> bit_idx) & mask)
2498 return false;
2499 return true;
2500}
2501
2502static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2503 u16 port, u16 len)
2504{
4fc40f07
GN		 2505 if (ctxt->perm_ok)
2506 return true;
2507
7b105ca2
TY		 2508 if (emulator_bad_iopl(ctxt))
2509 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2510 return false;
4fc40f07
GN		 2511
2512 ctxt->perm_ok = true;
2513
f850e2e6
GN		 2514 return true;
2515}
2516
38ba30ba 2517static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2518 struct tss_segment_16 *tss)
2519{
9dac77fa 2520 tss->ip = ctxt->_eip;
38ba30ba 2521 tss->flag = ctxt->eflags;
dd856efa
AK		 2522 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2523 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2524 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2525 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2526 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2527 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2528 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2529 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2530
1aa36616
AK		 2531 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2532 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2533 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2534 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2535 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2536}
2537
2538static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2539 struct tss_segment_16 *tss)
2540{
38ba30ba 2541 int ret;
2356aaeb 2542 u8 cpl;
38ba30ba 2543
9dac77fa 2544 ctxt->_eip = tss->ip;
38ba30ba 2545 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2546 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2547 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2548 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2549 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2550 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2551 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2552 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2553 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2554
2555 /*
2556 * SDM says that segment selectors are loaded before segment
2557 * descriptors
2558 */
1aa36616
AK		 2559 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2560 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2561 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2562 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2563 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2564
2356aaeb
PB		 2565 cpl = tss->cs & 3;
2566
38ba30ba 2567 /*
fc058680 2568 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2569 * it is handled in a context of new task
2570 */
d1442d85
NA		 2571 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2572 true, NULL);
38ba30ba
GN		 2573 if (ret != X86EMUL_CONTINUE)
2574 return ret;
d1442d85
NA		 2575 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2576 true, NULL);
38ba30ba
GN		 2577 if (ret != X86EMUL_CONTINUE)
2578 return ret;
d1442d85
NA		 2579 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2580 true, NULL);
38ba30ba
GN		 2581 if (ret != X86EMUL_CONTINUE)
2582 return ret;
d1442d85
NA		 2583 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2584 true, NULL);
38ba30ba
GN		 2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
d1442d85
NA		 2587 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2588 true, NULL);
38ba30ba
GN		 2589 if (ret != X86EMUL_CONTINUE)
2590 return ret;
2591
2592 return X86EMUL_CONTINUE;
2593}
2594
2595static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2596 u16 tss_selector, u16 old_tss_sel,
2597 ulong old_tss_base, struct desc_struct *new_desc)
2598{
0225fb50 2599 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2600 struct tss_segment_16 tss_seg;
2601 int ret;
bcc55cba 2602 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2603
0f65dd70 2604 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2605 &ctxt->exception);
db297e3d 2606 if (ret != X86EMUL_CONTINUE)
38ba30ba 2607 return ret;
38ba30ba 2608
7b105ca2 2609 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2610
0f65dd70 2611 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2612 &ctxt->exception);
db297e3d 2613 if (ret != X86EMUL_CONTINUE)
38ba30ba 2614 return ret;
38ba30ba 2615
0f65dd70 2616 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2617 &ctxt->exception);
db297e3d 2618 if (ret != X86EMUL_CONTINUE)
38ba30ba 2619 return ret;
38ba30ba
GN		 2620
2621 if (old_tss_sel != 0xffff) {
2622 tss_seg.prev_task_link = old_tss_sel;
2623
0f65dd70 2624 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2625 &tss_seg.prev_task_link,
2626 sizeof tss_seg.prev_task_link,
0f65dd70 2627 &ctxt->exception);
db297e3d 2628 if (ret != X86EMUL_CONTINUE)
38ba30ba 2629 return ret;
38ba30ba
GN		 2630 }
2631
7b105ca2 2632 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2633}
2634
2635static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2636 struct tss_segment_32 *tss)
2637{
5c7411e2 2638 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2639 tss->eip = ctxt->_eip;
38ba30ba 2640 tss->eflags = ctxt->eflags;
dd856efa
AK		 2641 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2642 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2643 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2644 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2645 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2646 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2647 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2648 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2649
1aa36616
AK		 2650 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2651 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2652 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2653 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2654 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2655 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2656}
2657
2658static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2659 struct tss_segment_32 *tss)
2660{
38ba30ba 2661 int ret;
2356aaeb 2662 u8 cpl;
38ba30ba 2663
7b105ca2 2664 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2665 return emulate_gp(ctxt, 0);
9dac77fa 2666 ctxt->_eip = tss->eip;
38ba30ba 2667 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2668
2669 /* General purpose registers */
dd856efa
AK		 2670 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2671 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2672 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2673 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2674 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2675 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2676 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2677 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2678
2679 /*
2680 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2681 * descriptors. This is important because CPL checks will
2682 * use CS.RPL.
38ba30ba 2683 */
1aa36616
AK		 2684 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2685 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2686 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2687 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2688 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2689 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2690 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2691
4cee4798
KW		 2692 /*
2693 * If we're switching between Protected Mode and VM86, we need to make
2694 * sure to update the mode before loading the segment descriptors so
2695 * that the selectors are interpreted correctly.
4cee4798 2696 */
2356aaeb 2697 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2698 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2699 cpl = 3;
2700 } else {
4cee4798 2701 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2702 cpl = tss->cs & 3;
2703 }
4cee4798 2704
38ba30ba
GN		 2705 /*
2706 * Now load segment descriptors. If fault happenes at this stage
2707 * it is handled in a context of new task
2708 */
d1442d85
NA		 2709 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2710 cpl, true, NULL);
38ba30ba
GN		 2711 if (ret != X86EMUL_CONTINUE)
2712 return ret;
d1442d85
NA		 2713 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2714 true, NULL);
38ba30ba
GN		 2715 if (ret != X86EMUL_CONTINUE)
2716 return ret;
d1442d85
NA		 2717 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2718 true, NULL);
38ba30ba
GN		 2719 if (ret != X86EMUL_CONTINUE)
2720 return ret;
d1442d85
NA		 2721 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2722 true, NULL);
38ba30ba
GN		 2723 if (ret != X86EMUL_CONTINUE)
2724 return ret;
d1442d85
NA		 2725 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2726 true, NULL);
38ba30ba
GN		 2727 if (ret != X86EMUL_CONTINUE)
2728 return ret;
d1442d85
NA		 2729 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2730 true, NULL);
38ba30ba
GN		 2731 if (ret != X86EMUL_CONTINUE)
2732 return ret;
d1442d85
NA		 2733 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2734 true, NULL);
38ba30ba
GN		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
2737
2738 return X86EMUL_CONTINUE;
2739}
2740
2741static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2742 u16 tss_selector, u16 old_tss_sel,
2743 ulong old_tss_base, struct desc_struct *new_desc)
2744{
0225fb50 2745 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2746 struct tss_segment_32 tss_seg;
2747 int ret;
bcc55cba 2748 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2749 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2750 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2751
0f65dd70 2752 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2753 &ctxt->exception);
db297e3d 2754 if (ret != X86EMUL_CONTINUE)
38ba30ba 2755 return ret;
38ba30ba 2756
7b105ca2 2757 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2758
5c7411e2
NA		 2759 /* Only GP registers and segment selectors are saved */
2760 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2761 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2762 if (ret != X86EMUL_CONTINUE)
38ba30ba 2763 return ret;
38ba30ba 2764
0f65dd70 2765 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2766 &ctxt->exception);
db297e3d 2767 if (ret != X86EMUL_CONTINUE)
38ba30ba 2768 return ret;
38ba30ba
GN		 2769
2770 if (old_tss_sel != 0xffff) {
2771 tss_seg.prev_task_link = old_tss_sel;
2772
0f65dd70 2773 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2774 &tss_seg.prev_task_link,
2775 sizeof tss_seg.prev_task_link,
0f65dd70 2776 &ctxt->exception);
db297e3d 2777 if (ret != X86EMUL_CONTINUE)
38ba30ba 2778 return ret;
38ba30ba
GN		 2779 }
2780
7b105ca2 2781 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2782}
2783
2784static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2785 u16 tss_selector, int idt_index, int reason,
e269fb21 2786 bool has_error_code, u32 error_code)
38ba30ba 2787{
0225fb50 2788 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2789 struct desc_struct curr_tss_desc, next_tss_desc;
2790 int ret;
1aa36616 2791 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2792 ulong old_tss_base =
4bff1e86 2793 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2794 u32 desc_limit;
e919464b 2795 ulong desc_addr;
38ba30ba
GN		 2796
2797 /* FIXME: old_tss_base == ~0 ? */
2798
e919464b 2799 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2800 if (ret != X86EMUL_CONTINUE)
2801 return ret;
e919464b 2802 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2803 if (ret != X86EMUL_CONTINUE)
2804 return ret;
2805
2806 /* FIXME: check that next_tss_desc is tss */
2807
7f3d35fd
KW		 2808 /*
2809 * Check privileges. The three cases are task switch caused by...
2810 *
2811 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2812 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2813 * 3. jmp/call to TSS/task-gate: No check is performed since the
2814 * hardware checks it before exiting.
7f3d35fd
KW		 2815 */
2816 if (reason == TASK_SWITCH_GATE) {
2817 if (idt_index != -1) {
2818 /* Software interrupts */
2819 struct desc_struct task_gate_desc;
2820 int dpl;
2821
2822 ret = read_interrupt_descriptor(ctxt, idt_index,
2823 &task_gate_desc);
2824 if (ret != X86EMUL_CONTINUE)
2825 return ret;
2826
2827 dpl = task_gate_desc.dpl;
2828 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2829 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2830 }
38ba30ba
GN		 2831 }
2832
ceffb459
GN		 2833 desc_limit = desc_limit_scaled(&next_tss_desc);
2834 if (!next_tss_desc.p ||
2835 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2836 desc_limit < 0x2b)) {
592f0858 2837 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2838 }
2839
2840 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2841 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2842 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2843 }
2844
2845 if (reason == TASK_SWITCH_IRET)
2846 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2847
2848 /* set back link to prev task only if NT bit is set in eflags
fc058680 2849 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2850 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2851 old_tss_sel = 0xffff;
2852
2853 if (next_tss_desc.type & 8)
7b105ca2 2854 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2855 old_tss_base, &next_tss_desc);
2856 else
7b105ca2 2857 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2858 old_tss_base, &next_tss_desc);
0760d448
JK		 2859 if (ret != X86EMUL_CONTINUE)
2860 return ret;
38ba30ba
GN		 2861
2862 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2863 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2864
2865 if (reason != TASK_SWITCH_IRET) {
2866 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2867 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2868 }
2869
717746e3 2870 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2871 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2872
e269fb21 2873 if (has_error_code) {
9dac77fa
AK		 2874 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2875 ctxt->lock_prefix = 0;
2876 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2877 ret = em_push(ctxt);
e269fb21
JK		 2878 }
2879
38ba30ba
GN		 2880 return ret;
2881}
2882
2883int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2884 u16 tss_selector, int idt_index, int reason,
e269fb21 2885 bool has_error_code, u32 error_code)
38ba30ba 2886{
38ba30ba
GN		 2887 int rc;
2888
dd856efa 2889 invalidate_registers(ctxt);
9dac77fa
AK		 2890 ctxt->_eip = ctxt->eip;
2891 ctxt->dst.type = OP_NONE;
38ba30ba 2892
7f3d35fd 2893 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2894 has_error_code, error_code);
38ba30ba 2895
dd856efa 2896 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2897 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2898 writeback_registers(ctxt);
2899 }
38ba30ba 2900
a0c0ab2f 2901 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2902}
2903
f3bd64c6
GN		 2904static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2905 struct operand *op)
a682e354 2906{
b3356bf0 2907 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2908
01485a22
PB		 2909 register_address_increment(ctxt, reg, df * op->bytes);
2910 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2911}
2912
7af04fc0
AK		 2913static int em_das(struct x86_emulate_ctxt *ctxt)
2914{
7af04fc0
AK		 2915 u8 al, old_al;
2916 bool af, cf, old_cf;
2917
2918 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2919 al = ctxt->dst.val;
7af04fc0
AK		 2920
2921 old_al = al;
2922 old_cf = cf;
2923 cf = false;
2924 af = ctxt->eflags & X86_EFLAGS_AF;
2925 if ((al & 0x0f) > 9 || af) {
2926 al -= 6;
2927 cf = old_cf | (al >= 250);
2928 af = true;
2929 } else {
2930 af = false;
2931 }
2932 if (old_al > 0x99 || old_cf) {
2933 al -= 0x60;
2934 cf = true;
2935 }
2936
9dac77fa 2937 ctxt->dst.val = al;
7af04fc0 2938 /* Set PF, ZF, SF */
9dac77fa
AK		 2939 ctxt->src.type = OP_IMM;
2940 ctxt->src.val = 0;
2941 ctxt->src.bytes = 1;
158de57f 2942 fastop(ctxt, em_or);
7af04fc0
AK		 2943 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2944 if (cf)
2945 ctxt->eflags |= X86_EFLAGS_CF;
2946 if (af)
2947 ctxt->eflags |= X86_EFLAGS_AF;
2948 return X86EMUL_CONTINUE;
2949}
2950
a035d5c6
PB		 2951static int em_aam(struct x86_emulate_ctxt *ctxt)
2952{
2953 u8 al, ah;
2954
2955 if (ctxt->src.val == 0)
2956 return emulate_de(ctxt);
2957
2958 al = ctxt->dst.val & 0xff;
2959 ah = al / ctxt->src.val;
2960 al %= ctxt->src.val;
2961
2962 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2963
2964 /* Set PF, ZF, SF */
2965 ctxt->src.type = OP_IMM;
2966 ctxt->src.val = 0;
2967 ctxt->src.bytes = 1;
2968 fastop(ctxt, em_or);
2969
2970 return X86EMUL_CONTINUE;
2971}
2972
7f662273
GN		 2973static int em_aad(struct x86_emulate_ctxt *ctxt)
2974{
2975 u8 al = ctxt->dst.val & 0xff;
2976 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2977
2978 al = (al + (ah * ctxt->src.val)) & 0xff;
2979
2980 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2981
f583c29b
GN		 2982 /* Set PF, ZF, SF */
2983 ctxt->src.type = OP_IMM;
2984 ctxt->src.val = 0;
2985 ctxt->src.bytes = 1;
2986 fastop(ctxt, em_or);
7f662273
GN		 2987
2988 return X86EMUL_CONTINUE;
2989}
2990
d4ddafcd
TY		 2991static int em_call(struct x86_emulate_ctxt *ctxt)
2992{
234f3ce4 2993 int rc;
d4ddafcd
TY		 2994 long rel = ctxt->src.val;
2995
2996 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 2997 rc = jmp_rel(ctxt, rel);
2998 if (rc != X86EMUL_CONTINUE)
2999 return rc;
d4ddafcd
TY		 3000 return em_push(ctxt);
3001}
3002
0ef753b8
AK		 3003static int em_call_far(struct x86_emulate_ctxt *ctxt)
3004{
0ef753b8
AK		 3005 u16 sel, old_cs;
3006 ulong old_eip;
3007 int rc;
d1442d85
NA		 3008 struct desc_struct old_desc, new_desc;
3009 const struct x86_emulate_ops *ops = ctxt->ops;
3010 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3011
9dac77fa 3012 old_eip = ctxt->_eip;
d1442d85 3013 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3014
9dac77fa 3015 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3016 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3017 &new_desc);
3018 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3019 return X86EMUL_CONTINUE;
3020
d50eaa18 3021 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3022 if (rc != X86EMUL_CONTINUE)
3023 goto fail;
0ef753b8 3024
9dac77fa 3025 ctxt->src.val = old_cs;
4487b3b4 3026 rc = em_push(ctxt);
0ef753b8 3027 if (rc != X86EMUL_CONTINUE)
d1442d85 3028 goto fail;
0ef753b8 3029
9dac77fa 3030 ctxt->src.val = old_eip;
d1442d85
NA		 3031 rc = em_push(ctxt);
3032 /* If we failed, we tainted the memory, but the very least we should
3033 restore cs */
3034 if (rc != X86EMUL_CONTINUE)
3035 goto fail;
3036 return rc;
3037fail:
3038 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3039 return rc;
3040
0ef753b8
AK		 3041}
3042
40ece7c7
AK		 3043static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3044{
40ece7c7 3045 int rc;
234f3ce4 3046 unsigned long eip;
40ece7c7 3047
234f3ce4
NA		 3048 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3049 if (rc != X86EMUL_CONTINUE)
3050 return rc;
3051 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3052 if (rc != X86EMUL_CONTINUE)
3053 return rc;
5ad105e5 3054 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3055 return X86EMUL_CONTINUE;
3056}
3057
e4f973ae
TY		 3058static int em_xchg(struct x86_emulate_ctxt *ctxt)
3059{
e4f973ae 3060 /* Write back the register source. */
9dac77fa
AK		 3061 ctxt->src.val = ctxt->dst.val;
3062 write_register_operand(&ctxt->src);
e4f973ae
TY		 3063
3064 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3065 ctxt->dst.val = ctxt->src.orig_val;
3066 ctxt->lock_prefix = 1;
e4f973ae
TY		 3067 return X86EMUL_CONTINUE;
3068}
3069
5c82aa29
AK		 3070static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3071{
9dac77fa 3072 ctxt->dst.val = ctxt->src2.val;
4d758349 3073 return fastop(ctxt, em_imul);
5c82aa29
AK		 3074}
3075
61429142
AK		 3076static int em_cwd(struct x86_emulate_ctxt *ctxt)
3077{
9dac77fa
AK		 3078 ctxt->dst.type = OP_REG;
3079 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3080 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3081 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3082
3083 return X86EMUL_CONTINUE;
3084}
3085
48bb5d3c
AK		 3086static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3087{
48bb5d3c
AK		 3088 u64 tsc = 0;
3089
717746e3 3090 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3091 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3092 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3093 return X86EMUL_CONTINUE;
3094}
3095
222d21aa
AK		 3096static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3097{
3098 u64 pmc;
3099
dd856efa 3100 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3101 return emulate_gp(ctxt, 0);
dd856efa
AK		 3102 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3103 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3104 return X86EMUL_CONTINUE;
3105}
3106
b9eac5f4
AK		 3107static int em_mov(struct x86_emulate_ctxt *ctxt)
3108{
54cfdb3e 3109 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3110 return X86EMUL_CONTINUE;
3111}
3112
84cffe49
BP		 3113#define FFL(x) bit(X86_FEATURE_##x)
3114
3115static int em_movbe(struct x86_emulate_ctxt *ctxt)
3116{
3117 u32 ebx, ecx, edx, eax = 1;
3118 u16 tmp;
3119
3120 /*
3121 * Check MOVBE is set in the guest-visible CPUID leaf.
3122 */
3123 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3124 if (!(ecx & FFL(MOVBE)))
3125 return emulate_ud(ctxt);
3126
3127 switch (ctxt->op_bytes) {
3128 case 2:
3129 /*
3130 * From MOVBE definition: "...When the operand size is 16 bits,
3131 * the upper word of the destination register remains unchanged
3132 * ..."
3133 *
3134 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3135 * rules so we have to do the operation almost per hand.
3136 */
3137 tmp = (u16)ctxt->src.val;
3138 ctxt->dst.val &= ~0xffffUL;
3139 ctxt->dst.val |= (unsigned long)swab16(tmp);
3140 break;
3141 case 4:
3142 ctxt->dst.val = swab32((u32)ctxt->src.val);
3143 break;
3144 case 8:
3145 ctxt->dst.val = swab64(ctxt->src.val);
3146 break;
3147 default:
592f0858 3148 BUG();
84cffe49
BP		 3149 }
3150 return X86EMUL_CONTINUE;
3151}
3152
bc00f8d2
TY		 3153static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3154{
3155 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3156 return emulate_gp(ctxt, 0);
3157
3158 /* Disable writeback. */
3159 ctxt->dst.type = OP_NONE;
3160 return X86EMUL_CONTINUE;
3161}
3162
3163static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3164{
3165 unsigned long val;
3166
3167 if (ctxt->mode == X86EMUL_MODE_PROT64)
3168 val = ctxt->src.val & ~0ULL;
3169 else
3170 val = ctxt->src.val & ~0U;
3171
3172 /* #UD condition is already handled. */
3173 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3174 return emulate_gp(ctxt, 0);
3175
3176 /* Disable writeback. */
3177 ctxt->dst.type = OP_NONE;
3178 return X86EMUL_CONTINUE;
3179}
3180
e1e210b0
TY		 3181static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3182{
3183 u64 msr_data;
3184
dd856efa
AK		 3185 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3186 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3187 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3188 return emulate_gp(ctxt, 0);
3189
3190 return X86EMUL_CONTINUE;
3191}
3192
3193static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3194{
3195 u64 msr_data;
3196
dd856efa 3197 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3198 return emulate_gp(ctxt, 0);
3199
dd856efa
AK		 3200 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3201 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3202 return X86EMUL_CONTINUE;
3203}
3204
1bd5f469
TY		 3205static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3206{
9dac77fa 3207 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3208 return emulate_ud(ctxt);
3209
9dac77fa 3210 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3211 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3212 ctxt->dst.bytes = 2;
1bd5f469
TY		 3213 return X86EMUL_CONTINUE;
3214}
3215
3216static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3217{
9dac77fa 3218 u16 sel = ctxt->src.val;
1bd5f469 3219
9dac77fa 3220 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3221 return emulate_ud(ctxt);
3222
9dac77fa 3223 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3224 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3225
3226 /* Disable writeback. */
9dac77fa
AK		 3227 ctxt->dst.type = OP_NONE;
3228 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3229}
3230
a14e579f
AK		 3231static int em_lldt(struct x86_emulate_ctxt *ctxt)
3232{
3233 u16 sel = ctxt->src.val;
3234
3235 /* Disable writeback. */
3236 ctxt->dst.type = OP_NONE;
3237 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3238}
3239
80890006
AK		 3240static int em_ltr(struct x86_emulate_ctxt *ctxt)
3241{
3242 u16 sel = ctxt->src.val;
3243
3244 /* Disable writeback. */
3245 ctxt->dst.type = OP_NONE;
3246 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3247}
3248
38503911
AK		 3249static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3250{
9fa088f4
AK		 3251 int rc;
3252 ulong linear;
3253
9dac77fa 3254 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3255 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3256 ctxt->ops->invlpg(ctxt, linear);
38503911 3257 /* Disable writeback. */
9dac77fa 3258 ctxt->dst.type = OP_NONE;
38503911
AK		 3259 return X86EMUL_CONTINUE;
3260}
3261
2d04a05b
AK		 3262static int em_clts(struct x86_emulate_ctxt *ctxt)
3263{
3264 ulong cr0;
3265
3266 cr0 = ctxt->ops->get_cr(ctxt, 0);
3267 cr0 &= ~X86_CR0_TS;
3268 ctxt->ops->set_cr(ctxt, 0, cr0);
3269 return X86EMUL_CONTINUE;
3270}
3271
26d05cc7
AK		 3272static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3273{
0f54a321 3274 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3275
26d05cc7
AK		 3276 if (rc != X86EMUL_CONTINUE)
3277 return rc;
3278
3279 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3280 ctxt->_eip = ctxt->eip;
26d05cc7 3281 /* Disable writeback. */
9dac77fa 3282 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3283 return X86EMUL_CONTINUE;
3284}
3285
96051572
AK		 3286static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3287 void (*get)(struct x86_emulate_ctxt *ctxt,
3288 struct desc_ptr *ptr))
3289{
3290 struct desc_ptr desc_ptr;
3291
3292 if (ctxt->mode == X86EMUL_MODE_PROT64)
3293 ctxt->op_bytes = 8;
3294 get(ctxt, &desc_ptr);
3295 if (ctxt->op_bytes == 2) {
3296 ctxt->op_bytes = 4;
3297 desc_ptr.address &= 0x00ffffff;
3298 }
3299 /* Disable writeback. */
3300 ctxt->dst.type = OP_NONE;
3301 return segmented_write(ctxt, ctxt->dst.addr.mem,
3302 &desc_ptr, 2 + ctxt->op_bytes);
3303}
3304
3305static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3306{
3307 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3308}
3309
3310static int em_sidt(struct x86_emulate_ctxt *ctxt)
3311{
3312 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3313}
3314
5b7f6a1e 3315static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3316{
26d05cc7
AK		 3317 struct desc_ptr desc_ptr;
3318 int rc;
3319
510425ff
AK		 3320 if (ctxt->mode == X86EMUL_MODE_PROT64)
3321 ctxt->op_bytes = 8;
9dac77fa 3322 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3323 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3324 ctxt->op_bytes);
26d05cc7
AK		 3325 if (rc != X86EMUL_CONTINUE)
3326 return rc;
9a9abf6b
NA		 3327 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3328 is_noncanonical_address(desc_ptr.address))
3329 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3330 if (lgdt)
3331 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3332 else
3333 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3334 /* Disable writeback. */
9dac77fa 3335 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3336 return X86EMUL_CONTINUE;
3337}
3338
5b7f6a1e
NA		 3339static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3340{
3341 return em_lgdt_lidt(ctxt, true);
3342}
3343
5ef39c71 3344static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3345{
26d05cc7
AK		 3346 int rc;
3347
5ef39c71
AK		 3348 rc = ctxt->ops->fix_hypercall(ctxt);
3349
26d05cc7 3350 /* Disable writeback. */
9dac77fa 3351 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3352 return rc;
3353}
3354
3355static int em_lidt(struct x86_emulate_ctxt *ctxt)
3356{
5b7f6a1e 3357 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3358}
3359
3360static int em_smsw(struct x86_emulate_ctxt *ctxt)
3361{
32e94d06
NA		 3362 if (ctxt->dst.type == OP_MEM)
3363 ctxt->dst.bytes = 2;
9dac77fa 3364 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3365 return X86EMUL_CONTINUE;
3366}
3367
3368static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3369{
26d05cc7 3370 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3371 | (ctxt->src.val & 0x0f));
3372 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3373 return X86EMUL_CONTINUE;
3374}
3375
d06e03ad
TY		 3376static int em_loop(struct x86_emulate_ctxt *ctxt)
3377{
234f3ce4
NA		 3378 int rc = X86EMUL_CONTINUE;
3379
01485a22 3380 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3381 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3382 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3383 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3384
234f3ce4 3385 return rc;
d06e03ad
TY		 3386}
3387
3388static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3389{
234f3ce4
NA		 3390 int rc = X86EMUL_CONTINUE;
3391
dd856efa 3392 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3393 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3394
234f3ce4 3395 return rc;
d06e03ad
TY		 3396}
3397
d7841a4b
TY		 3398static int em_in(struct x86_emulate_ctxt *ctxt)
3399{
3400 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3401 &ctxt->dst.val))
3402 return X86EMUL_IO_NEEDED;
3403
3404 return X86EMUL_CONTINUE;
3405}
3406
3407static int em_out(struct x86_emulate_ctxt *ctxt)
3408{
3409 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3410 &ctxt->src.val, 1);
3411 /* Disable writeback. */
3412 ctxt->dst.type = OP_NONE;
3413 return X86EMUL_CONTINUE;
3414}
3415
f411e6cd
TY		 3416static int em_cli(struct x86_emulate_ctxt *ctxt)
3417{
3418 if (emulator_bad_iopl(ctxt))
3419 return emulate_gp(ctxt, 0);
3420
3421 ctxt->eflags &= ~X86_EFLAGS_IF;
3422 return X86EMUL_CONTINUE;
3423}
3424
3425static int em_sti(struct x86_emulate_ctxt *ctxt)
3426{
3427 if (emulator_bad_iopl(ctxt))
3428 return emulate_gp(ctxt, 0);
3429
3430 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3431 ctxt->eflags |= X86_EFLAGS_IF;
3432 return X86EMUL_CONTINUE;
3433}
3434
6d6eede4
AK		 3435static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3436{
3437 u32 eax, ebx, ecx, edx;
3438
dd856efa
AK		 3439 eax = reg_read(ctxt, VCPU_REGS_RAX);
3440 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3441 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3442 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3443 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3444 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3445 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3446 return X86EMUL_CONTINUE;
3447}
3448
98f73630
PB		 3449static int em_sahf(struct x86_emulate_ctxt *ctxt)
3450{
3451 u32 flags;
3452
3453 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3454 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3455
3456 ctxt->eflags &= ~0xffUL;
3457 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3458 return X86EMUL_CONTINUE;
3459}
3460
2dd7caa0
AK		 3461static int em_lahf(struct x86_emulate_ctxt *ctxt)
3462{
dd856efa
AK		 3463 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3464 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3465 return X86EMUL_CONTINUE;
3466}
3467
9299836e
AK		 3468static int em_bswap(struct x86_emulate_ctxt *ctxt)
3469{
3470 switch (ctxt->op_bytes) {
3471#ifdef CONFIG_X86_64
3472 case 8:
3473 asm("bswap %0" : "+r"(ctxt->dst.val));
3474 break;
3475#endif
3476 default:
3477 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3478 break;
3479 }
3480 return X86EMUL_CONTINUE;
3481}
3482
13e457e0
NA		 3483static int em_clflush(struct x86_emulate_ctxt *ctxt)
3484{
3485 /* emulating clflush regardless of cpuid */
3486 return X86EMUL_CONTINUE;
3487}
3488
cfec82cb
JR		 3489static bool valid_cr(int nr)
3490{
3491 switch (nr) {
3492 case 0:
3493 case 2 ... 4:
3494 case 8:
3495 return true;
3496 default:
3497 return false;
3498 }
3499}
3500
3501static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3502{
9dac77fa 3503 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3504 return emulate_ud(ctxt);
3505
3506 return X86EMUL_CONTINUE;
3507}
3508
3509static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3510{
9dac77fa
AK		 3511 u64 new_val = ctxt->src.val64;
3512 int cr = ctxt->modrm_reg;
c2ad2bb3 3513 u64 efer = 0;
cfec82cb
JR		 3514
3515 static u64 cr_reserved_bits[] = {
3516 0xffffffff00000000ULL,
3517 0, 0, 0, /* CR3 checked later */
3518 CR4_RESERVED_BITS,
3519 0, 0, 0,
3520 CR8_RESERVED_BITS,
3521 };
3522
3523 if (!valid_cr(cr))
3524 return emulate_ud(ctxt);
3525
3526 if (new_val & cr_reserved_bits[cr])
3527 return emulate_gp(ctxt, 0);
3528
3529 switch (cr) {
3530 case 0: {
c2ad2bb3 3531 u64 cr4;
cfec82cb
JR		 3532 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3533 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3534 return emulate_gp(ctxt, 0);
3535
717746e3
AK		 3536 cr4 = ctxt->ops->get_cr(ctxt, 4);
3537 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3538
3539 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3540 !(cr4 & X86_CR4_PAE))
3541 return emulate_gp(ctxt, 0);
3542
3543 break;
3544 }
3545 case 3: {
3546 u64 rsvd = 0;
3547
c2ad2bb3
AK		 3548 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3549 if (efer & EFER_LMA)
9d88fca7 3550 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3551
3552 if (new_val & rsvd)
3553 return emulate_gp(ctxt, 0);
3554
3555 break;
3556 }
3557 case 4: {
717746e3 3558 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3559
3560 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3561 return emulate_gp(ctxt, 0);
3562
3563 break;
3564 }
3565 }
3566
3567 return X86EMUL_CONTINUE;
3568}
3569
3b88e41a
JR		 3570static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3571{
3572 unsigned long dr7;
3573
717746e3 3574 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3575
3576 /* Check if DR7.Global_Enable is set */
3577 return dr7 & (1 << 13);
3578}
3579
3580static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3581{
9dac77fa 3582 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3583 u64 cr4;
3584
3585 if (dr > 7)
3586 return emulate_ud(ctxt);
3587
717746e3 3588 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3589 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3590 return emulate_ud(ctxt);
3591
6d2a0526
NA		 3592 if (check_dr7_gd(ctxt)) {
3593 ulong dr6;
3594
3595 ctxt->ops->get_dr(ctxt, 6, &dr6);
3596 dr6 &= ~15;
3597 dr6 |= DR6_BD | DR6_RTM;
3598 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3599 return emulate_db(ctxt);
6d2a0526 3600 }
3b88e41a
JR		 3601
3602 return X86EMUL_CONTINUE;
3603}
3604
3605static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3606{
9dac77fa
AK		 3607 u64 new_val = ctxt->src.val64;
3608 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3609
3610 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3611 return emulate_gp(ctxt, 0);
3612
3613 return check_dr_read(ctxt);
3614}
3615
01de8b09
JR		 3616static int check_svme(struct x86_emulate_ctxt *ctxt)
3617{
3618 u64 efer;
3619
717746e3 3620 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3621
3622 if (!(efer & EFER_SVME))
3623 return emulate_ud(ctxt);
3624
3625 return X86EMUL_CONTINUE;
3626}
3627
3628static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3629{
dd856efa 3630 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3631
3632 /* Valid physical address? */
d4224449 3633 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3634 return emulate_gp(ctxt, 0);
3635
3636 return check_svme(ctxt);
3637}
3638
d7eb8203
JR		 3639static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3640{
717746e3 3641 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3642
717746e3 3643 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3644 return emulate_ud(ctxt);
3645
3646 return X86EMUL_CONTINUE;
3647}
3648
8061252e
JR		 3649static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3650{
717746e3 3651 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3652 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3653
717746e3 3654 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3655 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3656 return emulate_gp(ctxt, 0);
3657
3658 return X86EMUL_CONTINUE;
3659}
3660
f6511935
JR		 3661static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3662{
9dac77fa
AK		 3663 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3664 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3665 return emulate_gp(ctxt, 0);
3666
3667 return X86EMUL_CONTINUE;
3668}
3669
3670static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3671{
9dac77fa
AK		 3672 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3673 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3674 return emulate_gp(ctxt, 0);
3675
3676 return X86EMUL_CONTINUE;
3677}
3678
73fba5f4 3679#define D(_y) { .flags = (_y) }
d40a6898
PB		 3680#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3681#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3682 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3683#define N D(NotImpl)
01de8b09 3684#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3685#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3686#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3687#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3688#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3689#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3690#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3691#define II(_f, _e, _i) \
d40a6898 3692 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3693#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3694 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3695 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3696#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3697
8d8f4e9f 3698#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3699#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3700#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3701#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3702#define I2bvIP(_f, _e, _i, _p) \
3703 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3704
fb864fbc
AK		 3705#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3706 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3707 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3708
0f54a321
NA		 3709static const struct opcode group7_rm0[] = {
3710 N,
3711 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3712 N, N, N, N, N, N,
3713};
3714
fd0a0d82 3715static const struct opcode group7_rm1[] = {
1c2545be
TY		 3716 DI(SrcNone | Priv, monitor),
3717 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3718 N, N, N, N, N, N,
3719};
3720
fd0a0d82 3721static const struct opcode group7_rm3[] = {
1c2545be 3722 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3723 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3724 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3725 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3726 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3727 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3728 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3729 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3730};
6230f7fc 3731
fd0a0d82 3732static const struct opcode group7_rm7[] = {
d7eb8203 3733 N,
1c2545be 3734 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3735 N, N, N, N, N, N,
3736};
d67fc27a 3737
fd0a0d82 3738static const struct opcode group1[] = {
fb864fbc
AK		 3739 F(Lock, em_add),
3740 F(Lock | PageTable, em_or),
3741 F(Lock, em_adc),
3742 F(Lock, em_sbb),
3743 F(Lock | PageTable, em_and),
3744 F(Lock, em_sub),
3745 F(Lock, em_xor),
3746 F(NoWrite, em_cmp),
73fba5f4
AK		 3747};
3748
fd0a0d82 3749static const struct opcode group1A[] = {
1c2545be 3750 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3751};
3752
007a3b54
AK		 3753static const struct opcode group2[] = {
3754 F(DstMem | ModRM, em_rol),
3755 F(DstMem | ModRM, em_ror),
3756 F(DstMem | ModRM, em_rcl),
3757 F(DstMem | ModRM, em_rcr),
3758 F(DstMem | ModRM, em_shl),
3759 F(DstMem | ModRM, em_shr),
3760 F(DstMem | ModRM, em_shl),
3761 F(DstMem | ModRM, em_sar),
3762};
3763
fd0a0d82 3764static const struct opcode group3[] = {
fb864fbc
AK		 3765 F(DstMem | SrcImm | NoWrite, em_test),
3766 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3767 F(DstMem | SrcNone | Lock, em_not),
3768 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3769 F(DstXacc | Src2Mem, em_mul_ex),
3770 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3771 F(DstXacc | Src2Mem, em_div_ex),
3772 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3773};
3774
fd0a0d82 3775static const struct opcode group4[] = {
95413dc4
AK		 3776 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3777 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3778 N, N, N, N, N, N,
3779};
3780
fd0a0d82 3781static const struct opcode group5[] = {
95413dc4
AK		 3782 F(DstMem | SrcNone | Lock, em_inc),
3783 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3784 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3785 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3786 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3787 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3788 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3789};
3790
fd0a0d82 3791static const struct opcode group6[] = {
1c2545be
TY		 3792 DI(Prot, sldt),
3793 DI(Prot, str),
a14e579f 3794 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3795 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3796 N, N, N, N,
3797};
3798
fd0a0d82 3799static const struct group_dual group7 = { {
606b1c3e
NA		 3800 II(Mov | DstMem, em_sgdt, sgdt),
3801 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3802 II(SrcMem | Priv, em_lgdt, lgdt),
3803 II(SrcMem | Priv, em_lidt, lidt),
3804 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3805 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3806 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3807}, {
0f54a321 3808 EXT(0, group7_rm0),
5ef39c71 3809 EXT(0, group7_rm1),
01de8b09 3810 N, EXT(0, group7_rm3),
1c2545be
TY		 3811 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3812 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3813 EXT(0, group7_rm7),
73fba5f4
AK		 3814} };
3815
fd0a0d82 3816static const struct opcode group8[] = {
73fba5f4 3817 N, N, N, N,
11c363ba
AK		 3818 F(DstMem | SrcImmByte | NoWrite, em_bt),
3819 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3820 F(DstMem | SrcImmByte | Lock, em_btr),
3821 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3822};
3823
fd0a0d82 3824static const struct group_dual group9 = { {
1c2545be 3825 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3826}, {
3827 N, N, N, N, N, N, N, N,
3828} };
3829
fd0a0d82 3830static const struct opcode group11[] = {
1c2545be 3831 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3832 X7(D(Undefined)),
a4d4a7c1
AK		 3833};
3834
13e457e0 3835static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3836 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3837};
3838
3839static const struct group_dual group15 = { {
3840 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3841}, {
3842 N, N, N, N, N, N, N, N,
3843} };
3844
fd0a0d82 3845static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3846 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3847};
3848
39f062ff
NA		 3849static const struct instr_dual instr_dual_0f_2b = {
3850 I(0, em_mov), N
3851};
3852
d5b77069 3853static const struct gprefix pfx_0f_2b = {
39f062ff 3854 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3855};
3856
27ce8258 3857static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3858 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3859};
3860
0a37027e
AW		 3861static const struct gprefix pfx_0f_e7 = {
3862 N, I(Sse, em_mov), N, N,
3863};
3864
045a282c
GN		 3865static const struct escape escape_d9 = { {
3866 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3867}, {
3868 /* 0xC0 - 0xC7 */
3869 N, N, N, N, N, N, N, N,
3870 /* 0xC8 - 0xCF */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xD0 - 0xC7 */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xD8 - 0xDF */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xE0 - 0xE7 */
3877 N, N, N, N, N, N, N, N,
3878 /* 0xE8 - 0xEF */
3879 N, N, N, N, N, N, N, N,
3880 /* 0xF0 - 0xF7 */
3881 N, N, N, N, N, N, N, N,
3882 /* 0xF8 - 0xFF */
3883 N, N, N, N, N, N, N, N,
3884} };
3885
3886static const struct escape escape_db = { {
3887 N, N, N, N, N, N, N, N,
3888}, {
3889 /* 0xC0 - 0xC7 */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xC8 - 0xCF */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xD0 - 0xC7 */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xD8 - 0xDF */
3896 N, N, N, N, N, N, N, N,
3897 /* 0xE0 - 0xE7 */
3898 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3899 /* 0xE8 - 0xEF */
3900 N, N, N, N, N, N, N, N,
3901 /* 0xF0 - 0xF7 */
3902 N, N, N, N, N, N, N, N,
3903 /* 0xF8 - 0xFF */
3904 N, N, N, N, N, N, N, N,
3905} };
3906
3907static const struct escape escape_dd = { {
3908 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3909}, {
3910 /* 0xC0 - 0xC7 */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xC8 - 0xCF */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xD0 - 0xC7 */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xD8 - 0xDF */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xE0 - 0xE7 */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xE8 - 0xEF */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xF0 - 0xF7 */
3923 N, N, N, N, N, N, N, N,
3924 /* 0xF8 - 0xFF */
3925 N, N, N, N, N, N, N, N,
3926} };
3927
39f062ff
NA		 3928static const struct instr_dual instr_dual_0f_c3 = {
3929 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3930};
3931
fd0a0d82 3932static const struct opcode opcode_table[256] = {
73fba5f4 3933 /* 0x00 - 0x07 */
fb864fbc 3934 F6ALU(Lock, em_add),
1cd196ea
AK		 3935 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3936 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3937 /* 0x08 - 0x0F */
fb864fbc 3938 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3939 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3940 N,
73fba5f4 3941 /* 0x10 - 0x17 */
fb864fbc 3942 F6ALU(Lock, em_adc),
1cd196ea
AK		 3943 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3944 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3945 /* 0x18 - 0x1F */
fb864fbc 3946 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3947 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3948 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3949 /* 0x20 - 0x27 */
fb864fbc 3950 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3951 /* 0x28 - 0x2F */
fb864fbc 3952 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3953 /* 0x30 - 0x37 */
fb864fbc 3954 F6ALU(Lock, em_xor), N, N,
73fba5f4 3955 /* 0x38 - 0x3F */
fb864fbc 3956 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3957 /* 0x40 - 0x4F */
95413dc4 3958 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3959 /* 0x50 - 0x57 */
63540382 3960 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3961 /* 0x58 - 0x5F */
c54fe504 3962 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3963 /* 0x60 - 0x67 */
b96a7fad
TY		 3964 I(ImplicitOps | Stack | No64, em_pusha),
3965 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3966 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3967 N, N, N, N,
3968 /* 0x68 - 0x6F */
d46164db
AK		 3969 I(SrcImm | Mov | Stack, em_push),
3970 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3971 I(SrcImmByte | Mov | Stack, em_push),
3972 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3973 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3974 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3975 /* 0x70 - 0x7F */
58b7075d 3976 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3977 /* 0x80 - 0x87 */
1c2545be
TY		 3978 G(ByteOp | DstMem | SrcImm, group1),
3979 G(DstMem | SrcImm, group1),
3980 G(ByteOp | DstMem | SrcImm | No64, group1),
3981 G(DstMem | SrcImmByte, group1),
fb864fbc 3982 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3983 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3984 /* 0x88 - 0x8F */
d5ae7ce8 3985 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3986 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3987 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3988 D(ModRM | SrcMem | NoAccess | DstReg),
3989 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3990 G(0, group1A),
73fba5f4 3991 /* 0x90 - 0x97 */
bf608f88 3992 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3993 /* 0x98 - 0x9F */
61429142 3994 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3995 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3996 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3997 II(ImplicitOps | Stack, em_popf, popf),
3998 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3999 /* 0xA0 - 0xA7 */
b9eac5f4 4000 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4001 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4002 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4003 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4004 /* 0xA8 - 0xAF */
fb864fbc 4005 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4006 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4007 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4008 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4009 /* 0xB0 - 0xB7 */
b9eac5f4 4010 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4011 /* 0xB8 - 0xBF */
5e2c6883 4012 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4013 /* 0xC0 - 0xC7 */
007a3b54 4014 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4015 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4016 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4017 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4018 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4019 G(ByteOp, group11), G(0, group11),
73fba5f4 4020 /* 0xC8 - 0xCF */
612e89f0 4021 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4022 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4023 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4024 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4025 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4026 /* 0xD0 - 0xD7 */
007a3b54
AK		 4027 G(Src2One | ByteOp, group2), G(Src2One, group2),
4028 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4029 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4030 I(DstAcc | SrcImmUByte | No64, em_aad),
4031 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4032 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4033 /* 0xD8 - 0xDF */
045a282c 4034 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4035 /* 0xE0 - 0xE7 */
58b7075d
NA		 4036 X3(I(SrcImmByte | NearBranch, em_loop)),
4037 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4038 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4039 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4040 /* 0xE8 - 0xEF */
58b7075d
NA		 4041 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4042 I(SrcImmFAddr | No64, em_jmp_far),
4043 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4044 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4045 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4046 /* 0xF0 - 0xF7 */
bf608f88 4047 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4048 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4049 G(ByteOp, group3), G(0, group3),
73fba5f4 4050 /* 0xF8 - 0xFF */
f411e6cd
TY		 4051 D(ImplicitOps), D(ImplicitOps),
4052 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4053 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4054};
4055
fd0a0d82 4056static const struct opcode twobyte_table[256] = {
73fba5f4 4057 /* 0x00 - 0x0F */
dee6bb70 4058 G(0, group6), GD(0, &group7), N, N,
b51e974f 4059 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4060 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4061 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4062 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4063 /* 0x10 - 0x1F */
103f98ea 4064 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4065 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4066 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4067 /* 0x20 - 0x2F */
9b88ae99
NA		 4068 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4069 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4070 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4071 check_cr_write),
4072 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4073 check_dr_write),
73fba5f4 4074 N, N, N, N,
27ce8258
IM		 4075 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4076 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4077 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4078 N, N, N, N,
73fba5f4 4079 /* 0x30 - 0x3F */
e1e210b0 4080 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4081 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4082 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4083 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4084 I(ImplicitOps | EmulateOnUD, em_sysenter),
4085 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4086 N, N,
73fba5f4
AK		 4087 N, N, N, N, N, N, N, N,
4088 /* 0x40 - 0x4F */
140bad89 4089 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4090 /* 0x50 - 0x5F */
4091 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4092 /* 0x60 - 0x6F */
aa97bb48
AK		 4093 N, N, N, N,
4094 N, N, N, N,
4095 N, N, N, N,
4096 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4097 /* 0x70 - 0x7F */
aa97bb48
AK		 4098 N, N, N, N,
4099 N, N, N, N,
4100 N, N, N, N,
4101 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4102 /* 0x80 - 0x8F */
58b7075d 4103 X16(D(SrcImm | NearBranch)),
73fba5f4 4104 /* 0x90 - 0x9F */
ee45b58e 4105 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4106 /* 0xA0 - 0xA7 */
1cd196ea 4107 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4108 II(ImplicitOps, em_cpuid, cpuid),
4109 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4110 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4111 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4112 /* 0xA8 - 0xAF */
1cd196ea 4113 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4114 DI(ImplicitOps, rsm),
11c363ba 4115 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4116 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4117 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4118 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4119 /* 0xB0 - 0xB7 */
e940b5c2 4120 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4121 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4122 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4123 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4124 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4125 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4126 /* 0xB8 - 0xBF */
4127 N, N,
ce7faab2 4128 G(BitOp, group8),
11c363ba
AK		 4129 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4130 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4131 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4132 /* 0xC0 - 0xC7 */
e47a5f5f 4133 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4134 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4135 N, N, N, GD(0, &group9),
9299836e
AK		 4136 /* 0xC8 - 0xCF */
4137 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4138 /* 0xD0 - 0xDF */
4139 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4140 /* 0xE0 - 0xEF */
0a37027e
AW		 4141 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4142 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4143 /* 0xF0 - 0xFF */
4144 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4145};
4146
39f062ff
NA		 4147static const struct instr_dual instr_dual_0f_38_f0 = {
4148 I(DstReg | SrcMem | Mov, em_movbe), N
4149};
4150
4151static const struct instr_dual instr_dual_0f_38_f1 = {
4152 I(DstMem | SrcReg | Mov, em_movbe), N
4153};
4154
0bc5eedb 4155static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4156 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4157};
4158
4159static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4160 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4161};
4162
4163/*
4164 * Insns below are selected by the prefix which indexed by the third opcode
4165 * byte.
4166 */
4167static const struct opcode opcode_map_0f_38[256] = {
4168 /* 0x00 - 0x7f */
4169 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4170 /* 0x80 - 0xef */
4171 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4172 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4173 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4174 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4175 /* 0xf2 - 0xff */
4176 N, N, X4(N), X8(N)
0bc5eedb
BP		 4177};
4178
73fba5f4
AK		 4179#undef D
4180#undef N
4181#undef G
4182#undef GD
4183#undef I
aa97bb48 4184#undef GP
01de8b09 4185#undef EXT
73fba5f4 4186
8d8f4e9f 4187#undef D2bv
f6511935 4188#undef D2bvIP
8d8f4e9f 4189#undef I2bv
d7841a4b 4190#undef I2bvIP
d67fc27a 4191#undef I6ALU
8d8f4e9f 4192
9dac77fa 4193static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4194{
4195 unsigned size;
4196
9dac77fa 4197 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4198 if (size == 8)
4199 size = 4;
4200 return size;
4201}
4202
4203static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4204 unsigned size, bool sign_extension)
4205{
39f21ee5
AK		 4206 int rc = X86EMUL_CONTINUE;
4207
4208 op->type = OP_IMM;
4209 op->bytes = size;
9dac77fa 4210 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4211 /* NB. Immediates are sign-extended as necessary. */
4212 switch (op->bytes) {
4213 case 1:
e85a1085 4214 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4215 break;
4216 case 2:
e85a1085 4217 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4218 break;
4219 case 4:
e85a1085 4220 op->val = insn_fetch(s32, ctxt);
39f21ee5 4221 break;
5e2c6883
NA		 4222 case 8:
4223 op->val = insn_fetch(s64, ctxt);
4224 break;
39f21ee5
AK		 4225 }
4226 if (!sign_extension) {
4227 switch (op->bytes) {
4228 case 1:
4229 op->val &= 0xff;
4230 break;
4231 case 2:
4232 op->val &= 0xffff;
4233 break;
4234 case 4:
4235 op->val &= 0xffffffff;
4236 break;
4237 }
4238 }
4239done:
4240 return rc;
4241}
4242
a9945549
AK		 4243static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4244 unsigned d)
4245{
4246 int rc = X86EMUL_CONTINUE;
4247
4248 switch (d) {
4249 case OpReg:
2adb5ad9 4250 decode_register_operand(ctxt, op);
a9945549
AK		 4251 break;
4252 case OpImmUByte:
608aabe3 4253 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4254 break;
4255 case OpMem:
41ddf978 4256 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4257 mem_common:
4258 *op = ctxt->memop;
4259 ctxt->memopp = op;
96888977 4260 if (ctxt->d & BitOp)
a9945549
AK		 4261 fetch_bit_operand(ctxt);
4262 op->orig_val = op->val;
4263 break;
41ddf978 4264 case OpMem64:
aaa05f24 4265 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4266 goto mem_common;
a9945549
AK		 4267 case OpAcc:
4268 op->type = OP_REG;
4269 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4270 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4271 fetch_register_operand(op);
4272 op->orig_val = op->val;
4273 break;
820207c8
AK		 4274 case OpAccLo:
4275 op->type = OP_REG;
4276 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4277 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4278 fetch_register_operand(op);
4279 op->orig_val = op->val;
4280 break;
4281 case OpAccHi:
4282 if (ctxt->d & ByteOp) {
4283 op->type = OP_NONE;
4284 break;
4285 }
4286 op->type = OP_REG;
4287 op->bytes = ctxt->op_bytes;
4288 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4289 fetch_register_operand(op);
4290 op->orig_val = op->val;
4291 break;
a9945549
AK		 4292 case OpDI:
4293 op->type = OP_MEM;
4294 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4295 op->addr.mem.ea =
01485a22 4296 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4297 op->addr.mem.seg = VCPU_SREG_ES;
4298 op->val = 0;
b3356bf0 4299 op->count = 1;
a9945549
AK		 4300 break;
4301 case OpDX:
4302 op->type = OP_REG;
4303 op->bytes = 2;
dd856efa 4304 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4305 fetch_register_operand(op);
4306 break;
4dd6a57d 4307 case OpCL:
d29b9d7e 4308 op->type = OP_IMM;
4dd6a57d 4309 op->bytes = 1;
dd856efa 4310 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4311 break;
4312 case OpImmByte:
4313 rc = decode_imm(ctxt, op, 1, true);
4314 break;
4315 case OpOne:
d29b9d7e 4316 op->type = OP_IMM;
4dd6a57d
AK		 4317 op->bytes = 1;
4318 op->val = 1;
4319 break;
4320 case OpImm:
4321 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4322 break;
5e2c6883
NA		 4323 case OpImm64:
4324 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4325 break;
28867cee
AK		 4326 case OpMem8:
4327 ctxt->memop.bytes = 1;
660696d1 4328 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4329 ctxt->memop.addr.reg = decode_register(ctxt,
4330 ctxt->modrm_rm, true);
660696d1
GN		 4331 fetch_register_operand(&ctxt->memop);
4332 }
28867cee 4333 goto mem_common;
0fe59128
AK		 4334 case OpMem16:
4335 ctxt->memop.bytes = 2;
4336 goto mem_common;
4337 case OpMem32:
4338 ctxt->memop.bytes = 4;
4339 goto mem_common;
4340 case OpImmU16:
4341 rc = decode_imm(ctxt, op, 2, false);
4342 break;
4343 case OpImmU:
4344 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4345 break;
4346 case OpSI:
4347 op->type = OP_MEM;
4348 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4349 op->addr.mem.ea =
01485a22 4350 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4351 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4352 op->val = 0;
b3356bf0 4353 op->count = 1;
0fe59128 4354 break;
7fa57952
PB		 4355 case OpXLat:
4356 op->type = OP_MEM;
4357 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4358 op->addr.mem.ea =
01485a22 4359 address_mask(ctxt,
7fa57952
PB		 4360 reg_read(ctxt, VCPU_REGS_RBX) +
4361 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4362 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4363 op->val = 0;
4364 break;
0fe59128
AK		 4365 case OpImmFAddr:
4366 op->type = OP_IMM;
4367 op->addr.mem.ea = ctxt->_eip;
4368 op->bytes = ctxt->op_bytes + 2;
4369 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4370 break;
4371 case OpMemFAddr:
4372 ctxt->memop.bytes = ctxt->op_bytes + 2;
4373 goto mem_common;
c191a7a0 4374 case OpES:
d29b9d7e 4375 op->type = OP_IMM;
c191a7a0
AK		 4376 op->val = VCPU_SREG_ES;
4377 break;
4378 case OpCS:
d29b9d7e 4379 op->type = OP_IMM;
c191a7a0
AK		 4380 op->val = VCPU_SREG_CS;
4381 break;
4382 case OpSS:
d29b9d7e 4383 op->type = OP_IMM;
c191a7a0
AK		 4384 op->val = VCPU_SREG_SS;
4385 break;
4386 case OpDS:
d29b9d7e 4387 op->type = OP_IMM;
c191a7a0
AK		 4388 op->val = VCPU_SREG_DS;
4389 break;
4390 case OpFS:
d29b9d7e 4391 op->type = OP_IMM;
c191a7a0
AK		 4392 op->val = VCPU_SREG_FS;
4393 break;
4394 case OpGS:
d29b9d7e 4395 op->type = OP_IMM;
c191a7a0
AK		 4396 op->val = VCPU_SREG_GS;
4397 break;
a9945549
AK		 4398 case OpImplicit:
4399 /* Special instructions do their own operand decoding. */
4400 default:
4401 op->type = OP_NONE; /* Disable writeback. */
4402 break;
4403 }
4404
4405done:
4406 return rc;
4407}
4408
ef5d75cc 4409int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4410{
dde7e6d1
AK		 4411 int rc = X86EMUL_CONTINUE;
4412 int mode = ctxt->mode;
46561646 4413 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4414 bool op_prefix = false;
573e80fe 4415 bool has_seg_override = false;
46561646 4416 struct opcode opcode;
dde7e6d1 4417
f09ed83e
AK		 4418 ctxt->memop.type = OP_NONE;
4419 ctxt->memopp = NULL;
9dac77fa 4420 ctxt->_eip = ctxt->eip;
17052f16
PB		 4421 ctxt->fetch.ptr = ctxt->fetch.data;
4422 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4423 ctxt->opcode_len = 1;
dc25e89e 4424 if (insn_len > 0)
9dac77fa 4425 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4426 else {
9506d57d 4427 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4428 if (rc != X86EMUL_CONTINUE)
4429 return rc;
4430 }
dde7e6d1
AK		 4431
4432 switch (mode) {
4433 case X86EMUL_MODE_REAL:
4434 case X86EMUL_MODE_VM86:
4435 case X86EMUL_MODE_PROT16:
4436 def_op_bytes = def_ad_bytes = 2;
4437 break;
4438 case X86EMUL_MODE_PROT32:
4439 def_op_bytes = def_ad_bytes = 4;
4440 break;
4441#ifdef CONFIG_X86_64
4442 case X86EMUL_MODE_PROT64:
4443 def_op_bytes = 4;
4444 def_ad_bytes = 8;
4445 break;
4446#endif
4447 default:
1d2887e2 4448 return EMULATION_FAILED;
dde7e6d1
AK		 4449 }
4450
9dac77fa
AK		 4451 ctxt->op_bytes = def_op_bytes;
4452 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4453
4454 /* Legacy prefixes. */
4455 for (;;) {
e85a1085 4456 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4457 case 0x66: /* operand-size override */
0d7cdee8 4458 op_prefix = true;
dde7e6d1 4459 /* switch between 2/4 bytes */
9dac77fa 4460 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4461 break;
4462 case 0x67: /* address-size override */
4463 if (mode == X86EMUL_MODE_PROT64)
4464 /* switch between 4/8 bytes */
9dac77fa 4465 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4466 else
4467 /* switch between 2/4 bytes */
9dac77fa 4468 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4469 break;
4470 case 0x26: /* ES override */
4471 case 0x2e: /* CS override */
4472 case 0x36: /* SS override */
4473 case 0x3e: /* DS override */
573e80fe
BD		 4474 has_seg_override = true;
4475 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4476 break;
4477 case 0x64: /* FS override */
4478 case 0x65: /* GS override */
573e80fe
BD		 4479 has_seg_override = true;
4480 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4481 break;
4482 case 0x40 ... 0x4f: /* REX */
4483 if (mode != X86EMUL_MODE_PROT64)
4484 goto done_prefixes;
9dac77fa 4485 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4486 continue;
4487 case 0xf0: /* LOCK */
9dac77fa 4488 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4489 break;
4490 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4491 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4492 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4493 break;
4494 default:
4495 goto done_prefixes;
4496 }
4497
4498 /* Any legacy prefix after a REX prefix nullifies its effect. */
4499
9dac77fa 4500 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4501 }
4502
4503done_prefixes:
4504
4505 /* REX prefix. */
9dac77fa
AK		 4506 if (ctxt->rex_prefix & 8)
4507 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4508
4509 /* Opcode byte(s). */
9dac77fa 4510 opcode = opcode_table[ctxt->b];
d3ad6243 4511 /* Two-byte opcode? */
9dac77fa 4512 if (ctxt->b == 0x0f) {
1ce19dc1 4513 ctxt->opcode_len = 2;
e85a1085 4514 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4515 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4516
4517 /* 0F_38 opcode map */
4518 if (ctxt->b == 0x38) {
4519 ctxt->opcode_len = 3;
4520 ctxt->b = insn_fetch(u8, ctxt);
4521 opcode = opcode_map_0f_38[ctxt->b];
4522 }
dde7e6d1 4523 }
9dac77fa 4524 ctxt->d = opcode.flags;
dde7e6d1 4525
9f4260e7
TY		 4526 if (ctxt->d & ModRM)
4527 ctxt->modrm = insn_fetch(u8, ctxt);
4528
7fe864dc
NA		 4529 /* vex-prefix instructions are not implemented */
4530 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4531 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4532 ctxt->d = NotImpl;
4533 }
4534
9dac77fa
AK		 4535 while (ctxt->d & GroupMask) {
4536 switch (ctxt->d & GroupMask) {
46561646 4537 case Group:
9dac77fa 4538 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4539 opcode = opcode.u.group[goffset];
4540 break;
4541 case GroupDual:
9dac77fa
AK		 4542 goffset = (ctxt->modrm >> 3) & 7;
4543 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4544 opcode = opcode.u.gdual->mod3[goffset];
4545 else
4546 opcode = opcode.u.gdual->mod012[goffset];
4547 break;
4548 case RMExt:
9dac77fa 4549 goffset = ctxt->modrm & 7;
01de8b09 4550 opcode = opcode.u.group[goffset];
46561646
AK		 4551 break;
4552 case Prefix:
9dac77fa 4553 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4554 return EMULATION_FAILED;
9dac77fa 4555 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4556 switch (simd_prefix) {
4557 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4558 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4559 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4560 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4561 }
4562 break;
045a282c
GN		 4563 case Escape:
4564 if (ctxt->modrm > 0xbf)
4565 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4566 else
4567 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4568 break;
39f062ff
NA		 4569 case InstrDual:
4570 if ((ctxt->modrm >> 6) == 3)
4571 opcode = opcode.u.idual->mod3;
4572 else
4573 opcode = opcode.u.idual->mod012;
4574 break;
46561646 4575 default:
1d2887e2 4576 return EMULATION_FAILED;
0d7cdee8 4577 }
46561646 4578
b1ea50b2 4579 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4580 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4581 }
4582
e24186e0
PB		 4583 /* Unrecognised? */
4584 if (ctxt->d == 0)
4585 return EMULATION_FAILED;
4586
9dac77fa 4587 ctxt->execute = opcode.u.execute;
dde7e6d1 4588
3a6095a0
NA		 4589 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4590 return EMULATION_FAILED;
4591
d40a6898 4592 if (unlikely(ctxt->d &
ed9aad21
NA		 4593 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4594 No16))) {
d40a6898
PB		 4595 /*
4596 * These are copied unconditionally here, and checked unconditionally
4597 * in x86_emulate_insn.
4598 */
4599 ctxt->check_perm = opcode.check_perm;
4600 ctxt->intercept = opcode.intercept;
dde7e6d1 4601
d40a6898
PB		 4602 if (ctxt->d & NotImpl)
4603 return EMULATION_FAILED;
d867162c 4604
58b7075d
NA		 4605 if (mode == X86EMUL_MODE_PROT64) {
4606 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4607 ctxt->op_bytes = 8;
4608 else if (ctxt->d & NearBranch)
4609 ctxt->op_bytes = 8;
4610 }
7f9b4b75 4611
d40a6898
PB		 4612 if (ctxt->d & Op3264) {
4613 if (mode == X86EMUL_MODE_PROT64)
4614 ctxt->op_bytes = 8;
4615 else
4616 ctxt->op_bytes = 4;
4617 }
4618
ed9aad21
NA		 4619 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4620 ctxt->op_bytes = 4;
4621
d40a6898
PB		 4622 if (ctxt->d & Sse)
4623 ctxt->op_bytes = 16;
4624 else if (ctxt->d & Mmx)
4625 ctxt->op_bytes = 8;
4626 }
1253791d 4627
dde7e6d1 4628 /* ModRM and SIB bytes. */
9dac77fa 4629 if (ctxt->d & ModRM) {
f09ed83e 4630 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4631 if (!has_seg_override) {
4632 has_seg_override = true;
4633 ctxt->seg_override = ctxt->modrm_seg;
4634 }
9dac77fa 4635 } else if (ctxt->d & MemAbs)
f09ed83e 4636 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4637 if (rc != X86EMUL_CONTINUE)
4638 goto done;
4639
573e80fe
BD		 4640 if (!has_seg_override)
4641 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4642
573e80fe 4643 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4644
dde7e6d1
AK		 4645 /*
4646 * Decode and fetch the source operand: register, memory
4647 * or immediate.
4648 */
0fe59128 4649 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4650 if (rc != X86EMUL_CONTINUE)
4651 goto done;
4652
dde7e6d1
AK		 4653 /*
4654 * Decode and fetch the second source operand: register, memory
4655 * or immediate.
4656 */
4dd6a57d 4657 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4658 if (rc != X86EMUL_CONTINUE)
4659 goto done;
4660
dde7e6d1 4661 /* Decode and fetch the destination operand: register or memory. */
a9945549 4662 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4663
41061cdb 4664 if (ctxt->rip_relative)
1c1c35ae
NA		 4665 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4666 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4667
a430c916 4668done:
1d2887e2 4669 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4670}
4671
1cb3f3ae
XG		 4672bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4673{
4674 return ctxt->d & PageTable;
4675}
4676
3e2f65d5
GN		 4677static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4678{
3e2f65d5
GN		 4679 /* The second termination condition only applies for REPE
4680 * and REPNE. Test if the repeat string operation prefix is
4681 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4682 * corresponding termination condition according to:
4683 * - if REPE/REPZ and ZF = 0 then done
4684 * - if REPNE/REPNZ and ZF = 1 then done
4685 */
9dac77fa
AK		 4686 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4687 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4688 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4689 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4690 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4691 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4692 return true;
4693
4694 return false;
4695}
4696
cbe2c9d3
AK		 4697static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4698{
4699 bool fault = false;
4700
4701 ctxt->ops->get_fpu(ctxt);
4702 asm volatile("1: fwait \n\t"
4703 "2: \n\t"
4704 ".pushsection .fixup,\"ax\" \n\t"
4705 "3: \n\t"
4706 "movb $1, %[fault] \n\t"
4707 "jmp 2b \n\t"
4708 ".popsection \n\t"
4709 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4710 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4711 ctxt->ops->put_fpu(ctxt);
4712
4713 if (unlikely(fault))
4714 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4715
4716 return X86EMUL_CONTINUE;
4717}
4718
4719static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4720 struct operand *op)
4721{
4722 if (op->type == OP_MM)
4723 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4724}
4725
e28bbd44
AK		 4726static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4727{
4728 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4729 if (!(ctxt->d & ByteOp))
4730 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4731 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4732 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4733 [fastop]"+S"(fop)
4734 : "c"(ctxt->src2.val));
e28bbd44 4735 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4736 if (!fop) /* exception is returned in fop variable */
4737 return emulate_de(ctxt);
e28bbd44
AK		 4738 return X86EMUL_CONTINUE;
4739}
dd856efa 4740
1498507a
BD		 4741void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4742{
573e80fe
BD		 4743 memset(&ctxt->rip_relative, 0,
4744 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4745
1498507a
BD		 4746 ctxt->io_read.pos = 0;
4747 ctxt->io_read.end = 0;
1498507a
BD		 4748 ctxt->mem_read.end = 0;
4749}
4750
7b105ca2 4751int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4752{
0225fb50 4753 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4754 int rc = X86EMUL_CONTINUE;
9dac77fa 4755 int saved_dst_type = ctxt->dst.type;
8b4caf66 4756
9dac77fa 4757 ctxt->mem_read.pos = 0;
310b5d30 4758
e24186e0
PB		 4759 /* LOCK prefix is allowed only with some instructions */
4760 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4761 rc = emulate_ud(ctxt);
1161624f
GN		 4762 goto done;
4763 }
4764
e24186e0 4765 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4766 rc = emulate_ud(ctxt);
d380a5e4
GN		 4767 goto done;
4768 }
4769
d40a6898
PB		 4770 if (unlikely(ctxt->d &
4771 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4772 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4773 (ctxt->d & Undefined)) {
4774 rc = emulate_ud(ctxt);
4775 goto done;
4776 }
1253791d 4777
d40a6898
PB		 4778 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4779 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4780 rc = emulate_ud(ctxt);
cbe2c9d3 4781 goto done;
d40a6898 4782 }
cbe2c9d3 4783
d40a6898
PB		 4784 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4785 rc = emulate_nm(ctxt);
c4f035c6 4786 goto done;
d40a6898 4787 }
c4f035c6 4788
d40a6898
PB		 4789 if (ctxt->d & Mmx) {
4790 rc = flush_pending_x87_faults(ctxt);
4791 if (rc != X86EMUL_CONTINUE)
4792 goto done;
4793 /*
4794 * Now that we know the fpu is exception safe, we can fetch
4795 * operands from it.
4796 */
4797 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4798 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4799 if (!(ctxt->d & Mov))
4800 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4801 }
e92805ac 4802
685bbf4a 4803 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4804 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4805 X86_ICPT_PRE_EXCEPT);
4806 if (rc != X86EMUL_CONTINUE)
4807 goto done;
4808 }
8ea7d6ae 4809
64a38292
NA		 4810 /* Instruction can only be executed in protected mode */
4811 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4812 rc = emulate_ud(ctxt);
4813 goto done;
4814 }
4815
d40a6898
PB		 4816 /* Privileged instruction can be executed only in CPL=0 */
4817 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4818 if (ctxt->d & PrivUD)
4819 rc = emulate_ud(ctxt);
4820 else
4821 rc = emulate_gp(ctxt, 0);
d09beabd 4822 goto done;
d40a6898 4823 }
d09beabd 4824
d40a6898 4825 /* Do instruction specific permission checks */
685bbf4a 4826 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4827 rc = ctxt->check_perm(ctxt);
4828 if (rc != X86EMUL_CONTINUE)
4829 goto done;
4830 }
4831
685bbf4a 4832 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4833 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4834 X86_ICPT_POST_EXCEPT);
4835 if (rc != X86EMUL_CONTINUE)
4836 goto done;
4837 }
4838
4839 if (ctxt->rep_prefix && (ctxt->d & String)) {
4840 /* All REP prefixes have the same first termination condition */
4841 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4842 ctxt->eip = ctxt->_eip;
4467c3f1 4843 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4844 goto done;
4845 }
b9fa9d6b 4846 }
b9fa9d6b
AK		 4847 }
4848
9dac77fa
AK		 4849 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4850 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4851 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4852 if (rc != X86EMUL_CONTINUE)
8b4caf66 4853 goto done;
9dac77fa 4854 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4855 }
4856
9dac77fa
AK		 4857 if (ctxt->src2.type == OP_MEM) {
4858 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4859 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4860 if (rc != X86EMUL_CONTINUE)
4861 goto done;
4862 }
4863
9dac77fa 4864 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4865 goto special_insn;
4866
4867
9dac77fa 4868 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4869 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4870 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4871 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4872 if (rc != X86EMUL_CONTINUE)
4873 goto done;
038e51de 4874 }
9dac77fa 4875 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4876
018a98db
AK		 4877special_insn:
4878
685bbf4a 4879 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4880 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4881 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4882 if (rc != X86EMUL_CONTINUE)
4883 goto done;
4884 }
4885
b9a1ecb9
NA		 4886 if (ctxt->rep_prefix && (ctxt->d & String))
4887 ctxt->eflags |= EFLG_RF;
4888 else
4889 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4890
9dac77fa 4891 if (ctxt->execute) {
e28bbd44
AK		 4892 if (ctxt->d & Fastop) {
4893 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4894 rc = fastop(ctxt, fop);
4895 if (rc != X86EMUL_CONTINUE)
4896 goto done;
4897 goto writeback;
4898 }
9dac77fa 4899 rc = ctxt->execute(ctxt);
ef65c889
AK		 4900 if (rc != X86EMUL_CONTINUE)
4901 goto done;
4902 goto writeback;
4903 }
4904
1ce19dc1 4905 if (ctxt->opcode_len == 2)
6aa8b732 4906 goto twobyte_insn;
0bc5eedb
BP		 4907 else if (ctxt->opcode_len == 3)
4908 goto threebyte_insn;
6aa8b732 4909
9dac77fa 4910 switch (ctxt->b) {
6aa8b732 4911 case 0x63: /* movsxd */
8b4caf66 4912 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4913 goto cannot_emulate;
9dac77fa 4914 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4915 break;
b2833e3c 4916 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4917 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4918 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4919 break;
7e0b54b1 4920 case 0x8d: /* lea r16/r32, m */
9dac77fa 4921 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4922 break;
3d9e77df 4923 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4924 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4925 ctxt->dst.type = OP_NONE;
4926 else
4927 rc = em_xchg(ctxt);
e4f973ae 4928 break;
e8b6fa70 4929 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4930 switch (ctxt->op_bytes) {
4931 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4932 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4933 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4934 }
4935 break;
6e154e56 4936 case 0xcc: /* int3 */
5c5df76b
TY		 4937 rc = emulate_int(ctxt, 3);
4938 break;
6e154e56 4939 case 0xcd: /* int n */
9dac77fa 4940 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4941 break;
4942 case 0xce: /* into */
5c5df76b
TY		 4943 if (ctxt->eflags & EFLG_OF)
4944 rc = emulate_int(ctxt, 4);
6e154e56 4945 break;
1a52e051 4946 case 0xe9: /* jmp rel */
db5b0762 4947 case 0xeb: /* jmp rel short */
234f3ce4 4948 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4949 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4950 break;
111de5d6 4951 case 0xf4: /* hlt */
6c3287f7 4952 ctxt->ops->halt(ctxt);
19fdfa0d 4953 break;
111de5d6
AK		 4954 case 0xf5: /* cmc */
4955 /* complement carry flag from eflags reg */
4956 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4957 break;
4958 case 0xf8: /* clc */
4959 ctxt->eflags &= ~EFLG_CF;
111de5d6 4960 break;
8744aa9a
MG		 4961 case 0xf9: /* stc */
4962 ctxt->eflags |= EFLG_CF;
4963 break;
fb4616f4
MG		 4964 case 0xfc: /* cld */
4965 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4966 break;
4967 case 0xfd: /* std */
4968 ctxt->eflags |= EFLG_DF;
fb4616f4 4969 break;
91269b8f
AK		 4970 default:
4971 goto cannot_emulate;
6aa8b732 4972 }
018a98db 4973
7d9ddaed
AK		 4974 if (rc != X86EMUL_CONTINUE)
4975 goto done;
4976
018a98db 4977writeback:
fb32b1ed
AK		 4978 if (ctxt->d & SrcWrite) {
4979 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4980 rc = writeback(ctxt, &ctxt->src);
4981 if (rc != X86EMUL_CONTINUE)
4982 goto done;
4983 }
ee212297
NA		 4984 if (!(ctxt->d & NoWrite)) {
4985 rc = writeback(ctxt, &ctxt->dst);
4986 if (rc != X86EMUL_CONTINUE)
4987 goto done;
4988 }
018a98db 4989
5cd21917
GN		 4990 /*
4991 * restore dst type in case the decoding will be reused
4992 * (happens for string instruction )
4993 */
9dac77fa 4994 ctxt->dst.type = saved_dst_type;
5cd21917 4995
9dac77fa 4996 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4997 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4998
9dac77fa 4999 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5000 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5001
9dac77fa 5002 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5003 unsigned int count;
9dac77fa 5004 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5005 if ((ctxt->d & SrcMask) == SrcSI)
5006 count = ctxt->src.count;
5007 else
5008 count = ctxt->dst.count;
01485a22 5009 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5010
d2ddd1c4
GN		 5011 if (!string_insn_completed(ctxt)) {
5012 /*
5013 * Re-enter guest when pio read ahead buffer is empty
5014 * or, if it is not used, after each 1024 iteration.
5015 */
dd856efa 5016 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5017 (r->end == 0 || r->end != r->pos)) {
5018 /*
5019 * Reset read cache. Usually happens before
5020 * decode, but since instruction is restarted
5021 * we have to do it here.
5022 */
9dac77fa 5023 ctxt->mem_read.end = 0;
dd856efa 5024 writeback_registers(ctxt);
d2ddd1c4
GN		 5025 return EMULATION_RESTART;
5026 }
5027 goto done; /* skip rip writeback */
0fa6ccbd 5028 }
b9a1ecb9 5029 ctxt->eflags &= ~EFLG_RF;
5cd21917 5030 }
d2ddd1c4 5031
9dac77fa 5032 ctxt->eip = ctxt->_eip;
018a98db
AK		 5033
5034done:
e0ad0b47
PB		 5035 if (rc == X86EMUL_PROPAGATE_FAULT) {
5036 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5037 ctxt->have_exception = true;
e0ad0b47 5038 }
775fde86
JR		 5039 if (rc == X86EMUL_INTERCEPTED)
5040 return EMULATION_INTERCEPTED;
5041
dd856efa
AK		 5042 if (rc == X86EMUL_CONTINUE)
5043 writeback_registers(ctxt);
5044
d2ddd1c4 5045 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5046
5047twobyte_insn:
9dac77fa 5048 switch (ctxt->b) {
018a98db 5049 case 0x09: /* wbinvd */
cfb22375 5050 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5051 break;
5052 case 0x08: /* invd */
018a98db
AK		 5053 case 0x0d: /* GrpP (prefetch) */
5054 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5055 case 0x1f: /* nop */
018a98db
AK		 5056 break;
5057 case 0x20: /* mov cr, reg */
9dac77fa 5058 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5059 break;
6aa8b732 5060 case 0x21: /* mov from dr to reg */
9dac77fa 5061 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5062 break;
6aa8b732 5063 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5064 if (test_cc(ctxt->b, ctxt->eflags))
5065 ctxt->dst.val = ctxt->src.val;
5066 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5067 ctxt->op_bytes != 4)
9dac77fa 5068 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5069 break;
b2833e3c 5070 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5071 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5072 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5073 break;
ee45b58e 5074 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5075 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5076 break;
6aa8b732 5077 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5078 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5079 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5080 : (u16) ctxt->src.val;
6aa8b732 5081 break;
6aa8b732 5082 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5083 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5084 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5085 (s16) ctxt->src.val;
6aa8b732 5086 break;
91269b8f
AK		 5087 default:
5088 goto cannot_emulate;
6aa8b732 5089 }
7d9ddaed 5090
0bc5eedb
BP		 5091threebyte_insn:
5092
7d9ddaed
AK		 5093 if (rc != X86EMUL_CONTINUE)
5094 goto done;
5095
6aa8b732
AK		 5096 goto writeback;
5097
5098cannot_emulate:
a0c0ab2f 5099 return EMULATION_FAILED;
6aa8b732 5100}
dd856efa
AK		 5101
5102void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5103{
5104 invalidate_registers(ctxt);
5105}
5106
5107void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5108{
5109 writeback_registers(ctxt);
5110}
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