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KVM: x86 emulator: use SrcAcc to simplify xchg decoding
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
57#define DstMask (7<<1)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 85/* Misc flags */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Mask (7<<29)
6aa8b732 96
d0e53325
AK		 97#define X2(x...) x, x
98#define X3(x...) X2(x), x
99#define X4(x...) X2(x), X2(x)
100#define X5(x...) X4(x), x
101#define X6(x...) X4(x), X2(x)
102#define X7(x...) X4(x), X3(x)
103#define X8(x...) X4(x), X4(x)
104#define X16(x...) X8(x), X8(x)
83babbca 105
d65b1dee
AK		 106struct opcode {
107 u32 flags;
120df890 108 union {
ef65c889 109 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 110 struct opcode *group;
111 struct group_dual *gdual;
112 } u;
113};
114
115struct group_dual {
116 struct opcode mod012[8];
117 struct opcode mod3[8];
d65b1dee
AK		 118};
119
6aa8b732 120/* EFLAGS bit definitions. */
d4c6a154
GN		 121#define EFLG_ID (1<<21)
122#define EFLG_VIP (1<<20)
123#define EFLG_VIF (1<<19)
124#define EFLG_AC (1<<18)
b1d86143
AP		 125#define EFLG_VM (1<<17)
126#define EFLG_RF (1<<16)
d4c6a154
GN		 127#define EFLG_IOPL (3<<12)
128#define EFLG_NT (1<<14)
6aa8b732
AK		 129#define EFLG_OF (1<<11)
130#define EFLG_DF (1<<10)
b1d86143 131#define EFLG_IF (1<<9)
d4c6a154 132#define EFLG_TF (1<<8)
6aa8b732
AK		 133#define EFLG_SF (1<<7)
134#define EFLG_ZF (1<<6)
135#define EFLG_AF (1<<4)
136#define EFLG_PF (1<<2)
137#define EFLG_CF (1<<0)
138
62bd430e
MG		 139#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
140#define EFLG_RESERVED_ONE_MASK 2
141
6aa8b732
AK		 142/*
143 * Instruction emulation:
144 * Most instructions are emulated directly via a fragment of inline assembly
145 * code. This allows us to save/restore EFLAGS and thus very easily pick up
146 * any modified flags.
147 */
148
05b3e0c2 149#if defined(CONFIG_X86_64)
6aa8b732
AK		 150#define _LO32 "k" /* force 32-bit operand */
151#define _STK "%%rsp" /* stack pointer */
152#elif defined(__i386__)
153#define _LO32 "" /* force 32-bit operand */
154#define _STK "%%esp" /* stack pointer */
155#endif
156
157/*
158 * These EFLAGS bits are restored from saved value during emulation, and
159 * any changes are written back to the saved value after emulation.
160 */
161#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
162
163/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 164#define _PRE_EFLAGS(_sav, _msk, _tmp) \
165 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
166 "movl %"_sav",%"_LO32 _tmp"; " \
167 "push %"_tmp"; " \
168 "push %"_tmp"; " \
169 "movl %"_msk",%"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "pushf; " \
172 "notl %"_LO32 _tmp"; " \
173 "andl %"_LO32 _tmp",("_STK"); " \
174 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
175 "pop %"_tmp"; " \
176 "orl %"_LO32 _tmp",("_STK"); " \
177 "popf; " \
178 "pop %"_sav"; "
6aa8b732
AK		 179
180/* After executing instruction: write-back necessary bits in EFLAGS. */
181#define _POST_EFLAGS(_sav, _msk, _tmp) \
182 /* _sav |= EFLAGS & _msk; */ \
183 "pushf; " \
184 "pop %"_tmp"; " \
185 "andl %"_msk",%"_LO32 _tmp"; " \
186 "orl %"_LO32 _tmp",%"_sav"; "
187
dda96d8f
AK		 188#ifdef CONFIG_X86_64
189#define ON64(x) x
190#else
191#define ON64(x)
192#endif
193
6b7ad61f
AK		 194#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
195 do { \
196 __asm__ __volatile__ ( \
197 _PRE_EFLAGS("0", "4", "2") \
198 _op _suffix " %"_x"3,%1; " \
199 _POST_EFLAGS("0", "4", "2") \
200 : "=m" (_eflags), "=m" ((_dst).val), \
201 "=&r" (_tmp) \
202 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 203 } while (0)
6b7ad61f
AK		 204
205
6aa8b732
AK		 206/* Raw emulation: instruction has two explicit operands. */
207#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 208 do { \
209 unsigned long _tmp; \
210 \
211 switch ((_dst).bytes) { \
212 case 2: \
213 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
214 break; \
215 case 4: \
216 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
217 break; \
218 case 8: \
219 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
220 break; \
221 } \
6aa8b732
AK		 222 } while (0)
223
224#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
225 do { \
6b7ad61f 226 unsigned long _tmp; \
d77c26fc 227 switch ((_dst).bytes) { \
6aa8b732 228 case 1: \
6b7ad61f 229 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 230 break; \
231 default: \
232 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
233 _wx, _wy, _lx, _ly, _qx, _qy); \
234 break; \
235 } \
236 } while (0)
237
238/* Source operand is byte-sized and may be restricted to just %cl. */
239#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
240 __emulate_2op(_op, _src, _dst, _eflags, \
241 "b", "c", "b", "c", "b", "c", "b", "c")
242
243/* Source operand is byte, word, long or quad sized. */
244#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
245 __emulate_2op(_op, _src, _dst, _eflags, \
246 "b", "q", "w", "r", _LO32, "r", "", "r")
247
248/* Source operand is word, long or quad sized. */
249#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
250 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
251 "w", "r", _LO32, "r", "", "r")
252
d175226a
GT		 253/* Instruction has three operands and one operand is stored in ECX register */
254#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
255 do { \
256 unsigned long _tmp; \
257 _type _clv = (_cl).val; \
258 _type _srcv = (_src).val; \
259 _type _dstv = (_dst).val; \
260 \
261 __asm__ __volatile__ ( \
262 _PRE_EFLAGS("0", "5", "2") \
263 _op _suffix " %4,%1 \n" \
264 _POST_EFLAGS("0", "5", "2") \
265 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
266 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
267 ); \
268 \
269 (_cl).val = (unsigned long) _clv; \
270 (_src).val = (unsigned long) _srcv; \
271 (_dst).val = (unsigned long) _dstv; \
272 } while (0)
273
274#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
275 do { \
276 switch ((_dst).bytes) { \
277 case 2: \
278 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
279 "w", unsigned short); \
280 break; \
281 case 4: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "l", unsigned int); \
284 break; \
285 case 8: \
286 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "q", unsigned long)); \
288 break; \
289 } \
290 } while (0)
291
dda96d8f 292#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 293 do { \
294 unsigned long _tmp; \
295 \
dda96d8f
AK		 296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0", "3", "2") \
298 _op _suffix " %1; " \
299 _POST_EFLAGS("0", "3", "2") \
300 : "=m" (_eflags), "+m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : "i" (EFLAGS_MASK)); \
303 } while (0)
304
305/* Instruction has only one explicit operand (no source operand). */
306#define emulate_1op(_op, _dst, _eflags) \
307 do { \
d77c26fc 308 switch ((_dst).bytes) { \
dda96d8f
AK		 309 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
310 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
311 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
312 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 313 } \
314 } while (0)
315
6aa8b732
AK		 316/* Fetch next part of the instruction being emulated. */
317#define insn_fetch(_type, _size, _eip) \
318({ unsigned long _x; \
62266869 319 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 320 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 321 goto done; \
322 (_eip) += (_size); \
323 (_type)_x; \
324})
325
414e6277
GN		 326#define insn_fetch_arr(_arr, _size, _eip) \
327({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
328 if (rc != X86EMUL_CONTINUE) \
329 goto done; \
330 (_eip) += (_size); \
331})
332
ddcb2885
HH		 333static inline unsigned long ad_mask(struct decode_cache *c)
334{
335 return (1UL << (c->ad_bytes << 3)) - 1;
336}
337
6aa8b732 338/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 339static inline unsigned long
340address_mask(struct decode_cache *c, unsigned long reg)
341{
342 if (c->ad_bytes == sizeof(unsigned long))
343 return reg;
344 else
345 return reg & ad_mask(c);
346}
347
348static inline unsigned long
349register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
350{
351 return base + address_mask(c, reg);
352}
353
7a957275
HH		 354static inline void
355register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
356{
357 if (c->ad_bytes == sizeof(unsigned long))
358 *reg += inc;
359 else
360 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
361}
6aa8b732 362
7a957275
HH		 363static inline void jmp_rel(struct decode_cache *c, int rel)
364{
365 register_address_increment(c, &c->eip, rel);
366}
098c937b 367
7a5b56df
AK		 368static void set_seg_override(struct decode_cache *c, int seg)
369{
370 c->has_seg_override = true;
371 c->seg_override = seg;
372}
373
79168fd1
GN		 374static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
375 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 376{
377 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
378 return 0;
379
79168fd1 380 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 381}
382
383static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 384 struct x86_emulate_ops *ops,
7a5b56df
AK		 385 struct decode_cache *c)
386{
387 if (!c->has_seg_override)
388 return 0;
389
79168fd1 390 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 391}
392
79168fd1
GN		 393static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
394 struct x86_emulate_ops *ops)
7a5b56df 395{
79168fd1 396 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 397}
398
79168fd1
GN		 399static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
400 struct x86_emulate_ops *ops)
7a5b56df 401{
79168fd1 402 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 403}
404
54b8486f
GN		 405static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
406 u32 error, bool valid)
407{
408 ctxt->exception = vec;
409 ctxt->error_code = error;
410 ctxt->error_code_valid = valid;
411 ctxt->restart = false;
412}
413
414static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
415{
416 emulate_exception(ctxt, GP_VECTOR, err, true);
417}
418
419static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
420 int err)
421{
422 ctxt->cr2 = addr;
423 emulate_exception(ctxt, PF_VECTOR, err, true);
424}
425
426static void emulate_ud(struct x86_emulate_ctxt *ctxt)
427{
428 emulate_exception(ctxt, UD_VECTOR, 0, false);
429}
430
431static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
432{
433 emulate_exception(ctxt, TS_VECTOR, err, true);
434}
435
62266869
AK		 436static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
437 struct x86_emulate_ops *ops,
2fb53ad8 438 unsigned long eip, u8 *dest)
62266869
AK		 439{
440 struct fetch_cache *fc = &ctxt->decode.fetch;
441 int rc;
2fb53ad8 442 int size, cur_size;
62266869 443
2fb53ad8
AK		 444 if (eip == fc->end) {
445 cur_size = fc->end - fc->start;
446 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
447 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
448 size, ctxt->vcpu, NULL);
3e2815e9 449 if (rc != X86EMUL_CONTINUE)
62266869 450 return rc;
2fb53ad8 451 fc->end += size;
62266869 452 }
2fb53ad8 453 *dest = fc->data[eip - fc->start];
3e2815e9 454 return X86EMUL_CONTINUE;
62266869
AK		 455}
456
457static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
458 struct x86_emulate_ops *ops,
459 unsigned long eip, void *dest, unsigned size)
460{
3e2815e9 461 int rc;
62266869 462
eb3c79e6 463 /* x86 instructions are limited to 15 bytes. */
063db061 464 if (eip + size - ctxt->eip > 15)
eb3c79e6 465 return X86EMUL_UNHANDLEABLE;
62266869
AK		 466 while (size--) {
467 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 468 if (rc != X86EMUL_CONTINUE)
62266869
AK		 469 return rc;
470 }
3e2815e9 471 return X86EMUL_CONTINUE;
62266869
AK		 472}
473
1e3c5cb0
RR		 474/*
475 * Given the 'reg' portion of a ModRM byte, and a register block, return a
476 * pointer into the block that addresses the relevant register.
477 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
478 */
479static void *decode_register(u8 modrm_reg, unsigned long *regs,
480 int highbyte_regs)
6aa8b732
AK		 481{
482 void *p;
483
484 p = &regs[modrm_reg];
485 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
486 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
487 return p;
488}
489
490static int read_descriptor(struct x86_emulate_ctxt *ctxt,
491 struct x86_emulate_ops *ops,
1a6440ae 492 ulong addr,
6aa8b732
AK		 493 u16 *size, unsigned long *address, int op_bytes)
494{
495 int rc;
496
497 if (op_bytes == 2)
498 op_bytes = 3;
499 *address = 0;
1a6440ae 500 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
1b30eaa8 501 if (rc != X86EMUL_CONTINUE)
6aa8b732 502 return rc;
1a6440ae 503 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
6aa8b732
AK		 504 return rc;
505}
506
bbe9abbd
NK		 507static int test_cc(unsigned int condition, unsigned int flags)
508{
509 int rc = 0;
510
511 switch ((condition & 15) >> 1) {
512 case 0: /* o */
513 rc |= (flags & EFLG_OF);
514 break;
515 case 1: /* b/c/nae */
516 rc |= (flags & EFLG_CF);
517 break;
518 case 2: /* z/e */
519 rc |= (flags & EFLG_ZF);
520 break;
521 case 3: /* be/na */
522 rc |= (flags & (EFLG_CF|EFLG_ZF));
523 break;
524 case 4: /* s */
525 rc |= (flags & EFLG_SF);
526 break;
527 case 5: /* p/pe */
528 rc |= (flags & EFLG_PF);
529 break;
530 case 7: /* le/ng */
531 rc |= (flags & EFLG_ZF);
532 /* fall through */
533 case 6: /* l/nge */
534 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
535 break;
536 }
537
538 /* Odd condition identifiers (lsb == 1) have inverted sense. */
539 return (!!rc ^ (condition & 1));
540}
541
3c118e24
AK		 542static void decode_register_operand(struct operand *op,
543 struct decode_cache *c,
3c118e24
AK		 544 int inhibit_bytereg)
545{
33615aa9 546 unsigned reg = c->modrm_reg;
9f1ef3f8 547 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 548
549 if (!(c->d & ModRM))
550 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 551 op->type = OP_REG;
552 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae
AK		 553 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
554 op->val = *(u8 *)op->addr.reg;
3c118e24
AK		 555 op->bytes = 1;
556 } else {
1a6440ae 557 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24
AK		 558 op->bytes = c->op_bytes;
559 switch (op->bytes) {
560 case 2:
1a6440ae 561 op->val = *(u16 *)op->addr.reg;
3c118e24
AK		 562 break;
563 case 4:
1a6440ae 564 op->val = *(u32 *)op->addr.reg;
3c118e24
AK		 565 break;
566 case 8:
1a6440ae 567 op->val = *(u64 *) op->addr.reg;
3c118e24
AK		 568 break;
569 }
570 }
571 op->orig_val = op->val;
572}
573
1c73ef66
AK		 574static int decode_modrm(struct x86_emulate_ctxt *ctxt,
575 struct x86_emulate_ops *ops)
576{
577 struct decode_cache *c = &ctxt->decode;
578 u8 sib;
f5b4edcd 579 int index_reg = 0, base_reg = 0, scale;
3e2815e9 580 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 581
582 if (c->rex_prefix) {
583 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
584 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
585 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
586 }
587
588 c->modrm = insn_fetch(u8, 1, c->eip);
589 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
590 c->modrm_reg |= (c->modrm & 0x38) >> 3;
591 c->modrm_rm |= (c->modrm & 0x07);
592 c->modrm_ea = 0;
593 c->use_modrm_ea = 1;
09ee57cd 594 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 595
596 if (c->modrm_mod == 3) {
107d6d2e
AK		 597 c->modrm_ptr = decode_register(c->modrm_rm,
598 c->regs, c->d & ByteOp);
599 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 600 return rc;
601 }
602
603 if (c->ad_bytes == 2) {
604 unsigned bx = c->regs[VCPU_REGS_RBX];
605 unsigned bp = c->regs[VCPU_REGS_RBP];
606 unsigned si = c->regs[VCPU_REGS_RSI];
607 unsigned di = c->regs[VCPU_REGS_RDI];
608
609 /* 16-bit ModR/M decode. */
610 switch (c->modrm_mod) {
611 case 0:
612 if (c->modrm_rm == 6)
613 c->modrm_ea += insn_fetch(u16, 2, c->eip);
614 break;
615 case 1:
616 c->modrm_ea += insn_fetch(s8, 1, c->eip);
617 break;
618 case 2:
619 c->modrm_ea += insn_fetch(u16, 2, c->eip);
620 break;
621 }
622 switch (c->modrm_rm) {
623 case 0:
624 c->modrm_ea += bx + si;
625 break;
626 case 1:
627 c->modrm_ea += bx + di;
628 break;
629 case 2:
630 c->modrm_ea += bp + si;
631 break;
632 case 3:
633 c->modrm_ea += bp + di;
634 break;
635 case 4:
636 c->modrm_ea += si;
637 break;
638 case 5:
639 c->modrm_ea += di;
640 break;
641 case 6:
642 if (c->modrm_mod != 0)
643 c->modrm_ea += bp;
644 break;
645 case 7:
646 c->modrm_ea += bx;
647 break;
648 }
649 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
650 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 651 c->modrm_seg = VCPU_SREG_SS;
1c73ef66
AK		 652 c->modrm_ea = (u16)c->modrm_ea;
653 } else {
654 /* 32/64-bit ModR/M decode. */
84411d85 655 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 656 sib = insn_fetch(u8, 1, c->eip);
657 index_reg |= (sib >> 3) & 7;
658 base_reg |= sib & 7;
659 scale = sib >> 6;
660
dc71d0f1
AK		 661 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
662 c->modrm_ea += insn_fetch(s32, 4, c->eip);
663 else
1c73ef66 664 c->modrm_ea += c->regs[base_reg];
dc71d0f1 665 if (index_reg != 4)
1c73ef66 666 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 667 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
668 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 669 c->rip_relative = 1;
84411d85 670 } else
1c73ef66 671 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 672 switch (c->modrm_mod) {
673 case 0:
674 if (c->modrm_rm == 5)
675 c->modrm_ea += insn_fetch(s32, 4, c->eip);
676 break;
677 case 1:
678 c->modrm_ea += insn_fetch(s8, 1, c->eip);
679 break;
680 case 2:
681 c->modrm_ea += insn_fetch(s32, 4, c->eip);
682 break;
683 }
684 }
1c73ef66
AK		 685done:
686 return rc;
687}
688
689static int decode_abs(struct x86_emulate_ctxt *ctxt,
690 struct x86_emulate_ops *ops)
691{
692 struct decode_cache *c = &ctxt->decode;
3e2815e9 693 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 694
695 switch (c->ad_bytes) {
696 case 2:
697 c->modrm_ea = insn_fetch(u16, 2, c->eip);
698 break;
699 case 4:
700 c->modrm_ea = insn_fetch(u32, 4, c->eip);
701 break;
702 case 8:
703 c->modrm_ea = insn_fetch(u64, 8, c->eip);
704 break;
705 }
706done:
707 return rc;
708}
709
dde7e6d1
AK		 710static int read_emulated(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 unsigned long addr, void *dest, unsigned size)
6aa8b732 713{
dde7e6d1
AK		 714 int rc;
715 struct read_cache *mc = &ctxt->decode.mem_read;
716 u32 err;
6aa8b732 717
dde7e6d1
AK		 718 while (size) {
719 int n = min(size, 8u);
720 size -= n;
721 if (mc->pos < mc->end)
722 goto read_cached;
5cd21917 723
dde7e6d1
AK		 724 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
725 ctxt->vcpu);
726 if (rc == X86EMUL_PROPAGATE_FAULT)
727 emulate_pf(ctxt, addr, err);
728 if (rc != X86EMUL_CONTINUE)
729 return rc;
730 mc->end += n;
6aa8b732 731
dde7e6d1
AK		 732 read_cached:
733 memcpy(dest, mc->data + mc->pos, n);
734 mc->pos += n;
735 dest += n;
736 addr += n;
6aa8b732 737 }
dde7e6d1
AK		 738 return X86EMUL_CONTINUE;
739}
6aa8b732 740
dde7e6d1
AK		 741static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
742 struct x86_emulate_ops *ops,
743 unsigned int size, unsigned short port,
744 void *dest)
745{
746 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 747
dde7e6d1
AK		 748 if (rc->pos == rc->end) { /* refill pio read ahead */
749 struct decode_cache *c = &ctxt->decode;
750 unsigned int in_page, n;
751 unsigned int count = c->rep_prefix ?
752 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
753 in_page = (ctxt->eflags & EFLG_DF) ?
754 offset_in_page(c->regs[VCPU_REGS_RDI]) :
755 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
756 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
757 count);
758 if (n == 0)
759 n = 1;
760 rc->pos = rc->end = 0;
761 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
762 return 0;
763 rc->end = n * size;
6aa8b732
AK		 764 }
765
dde7e6d1
AK		 766 memcpy(dest, rc->data + rc->pos, size);
767 rc->pos += size;
768 return 1;
769}
6aa8b732 770
dde7e6d1
AK		 771static u32 desc_limit_scaled(struct desc_struct *desc)
772{
773 u32 limit = get_desc_limit(desc);
6aa8b732 774
dde7e6d1
AK		 775 return desc->g ? (limit << 12) | 0xfff : limit;
776}
6aa8b732 777
dde7e6d1
AK		 778static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
779 struct x86_emulate_ops *ops,
780 u16 selector, struct desc_ptr *dt)
781{
782 if (selector & 1 << 2) {
783 struct desc_struct desc;
784 memset (dt, 0, sizeof *dt);
785 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
786 return;
e09d082c 787
dde7e6d1
AK		 788 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
789 dt->address = get_desc_base(&desc);
790 } else
791 ops->get_gdt(dt, ctxt->vcpu);
792}
120df890 793
dde7e6d1
AK		 794/* allowed just for 8 bytes segments */
795static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
796 struct x86_emulate_ops *ops,
797 u16 selector, struct desc_struct *desc)
798{
799 struct desc_ptr dt;
800 u16 index = selector >> 3;
801 int ret;
802 u32 err;
803 ulong addr;
120df890 804
dde7e6d1 805 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 806
dde7e6d1
AK		 807 if (dt.size < index * 8 + 7) {
808 emulate_gp(ctxt, selector & 0xfffc);
809 return X86EMUL_PROPAGATE_FAULT;
e09d082c 810 }
dde7e6d1
AK		 811 addr = dt.address + index * 8;
812 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
813 if (ret == X86EMUL_PROPAGATE_FAULT)
814 emulate_pf(ctxt, addr, err);
e09d082c 815
dde7e6d1
AK		 816 return ret;
817}
ef65c889 818
dde7e6d1
AK		 819/* allowed just for 8 bytes segments */
820static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
821 struct x86_emulate_ops *ops,
822 u16 selector, struct desc_struct *desc)
823{
824 struct desc_ptr dt;
825 u16 index = selector >> 3;
826 u32 err;
827 ulong addr;
828 int ret;
6aa8b732 829
dde7e6d1 830 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 831
dde7e6d1
AK		 832 if (dt.size < index * 8 + 7) {
833 emulate_gp(ctxt, selector & 0xfffc);
834 return X86EMUL_PROPAGATE_FAULT;
835 }
6aa8b732 836
dde7e6d1
AK		 837 addr = dt.address + index * 8;
838 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
839 if (ret == X86EMUL_PROPAGATE_FAULT)
840 emulate_pf(ctxt, addr, err);
c7e75a3d 841
dde7e6d1
AK		 842 return ret;
843}
c7e75a3d 844
dde7e6d1
AK		 845static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
846 struct x86_emulate_ops *ops,
847 u16 selector, int seg)
848{
849 struct desc_struct seg_desc;
850 u8 dpl, rpl, cpl;
851 unsigned err_vec = GP_VECTOR;
852 u32 err_code = 0;
853 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
854 int ret;
69f55cb1 855
dde7e6d1 856 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 857
dde7e6d1
AK		 858 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
859 || ctxt->mode == X86EMUL_MODE_REAL) {
860 /* set real mode segment descriptor */
861 set_desc_base(&seg_desc, selector << 4);
862 set_desc_limit(&seg_desc, 0xffff);
863 seg_desc.type = 3;
864 seg_desc.p = 1;
865 seg_desc.s = 1;
866 goto load;
867 }
868
869 /* NULL selector is not valid for TR, CS and SS */
870 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
871 && null_selector)
872 goto exception;
873
874 /* TR should be in GDT only */
875 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
876 goto exception;
877
878 if (null_selector) /* for NULL selector skip all following checks */
879 goto load;
880
881 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
882 if (ret != X86EMUL_CONTINUE)
883 return ret;
884
885 err_code = selector & 0xfffc;
886 err_vec = GP_VECTOR;
887
888 /* can't load system descriptor into segment selecor */
889 if (seg <= VCPU_SREG_GS && !seg_desc.s)
890 goto exception;
891
892 if (!seg_desc.p) {
893 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
894 goto exception;
895 }
896
897 rpl = selector & 3;
898 dpl = seg_desc.dpl;
899 cpl = ops->cpl(ctxt->vcpu);
900
901 switch (seg) {
902 case VCPU_SREG_SS:
903 /*
904 * segment is not a writable data segment or segment
905 * selector's RPL != CPL or segment selector's RPL != CPL
906 */
907 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
908 goto exception;
6aa8b732 909 break;
dde7e6d1
AK		 910 case VCPU_SREG_CS:
911 if (!(seg_desc.type & 8))
912 goto exception;
913
914 if (seg_desc.type & 4) {
915 /* conforming */
916 if (dpl > cpl)
917 goto exception;
918 } else {
919 /* nonconforming */
920 if (rpl > cpl || dpl != cpl)
921 goto exception;
922 }
923 /* CS(RPL) <- CPL */
924 selector = (selector & 0xfffc) | cpl;
6aa8b732 925 break;
dde7e6d1
AK		 926 case VCPU_SREG_TR:
927 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
928 goto exception;
929 break;
930 case VCPU_SREG_LDTR:
931 if (seg_desc.s || seg_desc.type != 2)
932 goto exception;
933 break;
934 default: /* DS, ES, FS, or GS */
4e62417b 935 /*
dde7e6d1
AK		 936 * segment is not a data or readable code segment or
937 * ((segment is a data or nonconforming code segment)
938 * and (both RPL and CPL > DPL))
4e62417b 939 */
dde7e6d1
AK		 940 if ((seg_desc.type & 0xa) == 0x8 ||
941 (((seg_desc.type & 0xc) != 0xc) &&
942 (rpl > dpl && cpl > dpl)))
943 goto exception;
6aa8b732 944 break;
dde7e6d1
AK		 945 }
946
947 if (seg_desc.s) {
948 /* mark segment as accessed */
949 seg_desc.type |= 1;
950 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
951 if (ret != X86EMUL_CONTINUE)
952 return ret;
953 }
954load:
955 ops->set_segment_selector(selector, seg, ctxt->vcpu);
956 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
957 return X86EMUL_CONTINUE;
958exception:
959 emulate_exception(ctxt, err_vec, err_code, true);
960 return X86EMUL_PROPAGATE_FAULT;
961}
962
963static inline int writeback(struct x86_emulate_ctxt *ctxt,
964 struct x86_emulate_ops *ops)
965{
966 int rc;
967 struct decode_cache *c = &ctxt->decode;
968 u32 err;
969
970 switch (c->dst.type) {
971 case OP_REG:
972 /* The 4-byte case *is* correct:
973 * in 64-bit mode we zero-extend.
974 */
975 switch (c->dst.bytes) {
6aa8b732 976 case 1:
1a6440ae 977 *(u8 *)c->dst.addr.reg = (u8)c->dst.val;
6aa8b732
AK		 978 break;
979 case 2:
1a6440ae 980 *(u16 *)c->dst.addr.reg = (u16)c->dst.val;
6aa8b732
AK		 981 break;
982 case 4:
1a6440ae 983 *c->dst.addr.reg = (u32)c->dst.val;
dde7e6d1
AK		 984 break; /* 64b: zero-ext */
985 case 8:
1a6440ae 986 *c->dst.addr.reg = c->dst.val;
6aa8b732
AK		 987 break;
988 }
989 break;
dde7e6d1
AK		 990 case OP_MEM:
991 if (c->lock_prefix)
992 rc = ops->cmpxchg_emulated(
1a6440ae 993 c->dst.addr.mem,
dde7e6d1
AK		 994 &c->dst.orig_val,
995 &c->dst.val,
996 c->dst.bytes,
997 &err,
998 ctxt->vcpu);
341de7e3 999 else
dde7e6d1 1000 rc = ops->write_emulated(
1a6440ae 1001 c->dst.addr.mem,
dde7e6d1
AK		 1002 &c->dst.val,
1003 c->dst.bytes,
1004 &err,
1005 ctxt->vcpu);
1006 if (rc == X86EMUL_PROPAGATE_FAULT)
1a6440ae 1007 emulate_pf(ctxt, c->dst.addr.mem, err);
dde7e6d1
AK		 1008 if (rc != X86EMUL_CONTINUE)
1009 return rc;
a682e354 1010 break;
dde7e6d1
AK		 1011 case OP_NONE:
1012 /* no writeback */
414e6277 1013 break;
dde7e6d1 1014 default:
414e6277 1015 break;
6aa8b732 1016 }
dde7e6d1
AK		 1017 return X86EMUL_CONTINUE;
1018}
6aa8b732 1019
dde7e6d1
AK		 1020static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1021 struct x86_emulate_ops *ops)
1022{
1023 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1024
dde7e6d1
AK		 1025 c->dst.type = OP_MEM;
1026 c->dst.bytes = c->op_bytes;
1027 c->dst.val = c->src.val;
1028 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1a6440ae
AK		 1029 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1030 c->regs[VCPU_REGS_RSP]);
dde7e6d1 1031}
69f55cb1 1032
dde7e6d1
AK		 1033static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1034 struct x86_emulate_ops *ops,
1035 void *dest, int len)
1036{
1037 struct decode_cache *c = &ctxt->decode;
1038 int rc;
8b4caf66 1039
dde7e6d1
AK		 1040 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1041 c->regs[VCPU_REGS_RSP]),
1042 dest, len);
1043 if (rc != X86EMUL_CONTINUE)
1044 return rc;
1045
1046 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1047 return rc;
8b4caf66
LV		 1048}
1049
dde7e6d1
AK		 1050static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1051 struct x86_emulate_ops *ops,
1052 void *dest, int len)
9de41573
GN		 1053{
1054 int rc;
dde7e6d1
AK		 1055 unsigned long val, change_mask;
1056 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1057 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1058
dde7e6d1
AK		 1059 rc = emulate_pop(ctxt, ops, &val, len);
1060 if (rc != X86EMUL_CONTINUE)
1061 return rc;
9de41573 1062
dde7e6d1
AK		 1063 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1064 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1065
dde7e6d1
AK		 1066 switch(ctxt->mode) {
1067 case X86EMUL_MODE_PROT64:
1068 case X86EMUL_MODE_PROT32:
1069 case X86EMUL_MODE_PROT16:
1070 if (cpl == 0)
1071 change_mask |= EFLG_IOPL;
1072 if (cpl <= iopl)
1073 change_mask |= EFLG_IF;
1074 break;
1075 case X86EMUL_MODE_VM86:
1076 if (iopl < 3) {
1077 emulate_gp(ctxt, 0);
1078 return X86EMUL_PROPAGATE_FAULT;
1079 }
1080 change_mask |= EFLG_IF;
1081 break;
1082 default: /* real mode */
1083 change_mask |= (EFLG_IOPL | EFLG_IF);
1084 break;
9de41573 1085 }
dde7e6d1
AK		 1086
1087 *(unsigned long *)dest =
1088 (ctxt->eflags & ~change_mask) | (val & change_mask);
1089
1090 return rc;
9de41573
GN		 1091}
1092
dde7e6d1
AK		 1093static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1094 struct x86_emulate_ops *ops, int seg)
7b262e90 1095{
dde7e6d1 1096 struct decode_cache *c = &ctxt->decode;
7b262e90 1097
dde7e6d1 1098 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1099
dde7e6d1 1100 emulate_push(ctxt, ops);
7b262e90
GN		 1101}
1102
dde7e6d1
AK		 1103static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1104 struct x86_emulate_ops *ops, int seg)
38ba30ba 1105{
dde7e6d1
AK		 1106 struct decode_cache *c = &ctxt->decode;
1107 unsigned long selector;
1108 int rc;
38ba30ba 1109
dde7e6d1
AK		 1110 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1111 if (rc != X86EMUL_CONTINUE)
1112 return rc;
1113
1114 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1115 return rc;
38ba30ba
GN		 1116}
1117
dde7e6d1
AK		 1118static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1119 struct x86_emulate_ops *ops)
38ba30ba 1120{
dde7e6d1
AK		 1121 struct decode_cache *c = &ctxt->decode;
1122 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1123 int rc = X86EMUL_CONTINUE;
1124 int reg = VCPU_REGS_RAX;
38ba30ba 1125
dde7e6d1
AK		 1126 while (reg <= VCPU_REGS_RDI) {
1127 (reg == VCPU_REGS_RSP) ?
1128 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1129
dde7e6d1 1130 emulate_push(ctxt, ops);
38ba30ba 1131
dde7e6d1
AK		 1132 rc = writeback(ctxt, ops);
1133 if (rc != X86EMUL_CONTINUE)
1134 return rc;
38ba30ba 1135
dde7e6d1 1136 ++reg;
38ba30ba 1137 }
38ba30ba 1138
dde7e6d1
AK		 1139 /* Disable writeback. */
1140 c->dst.type = OP_NONE;
1141
1142 return rc;
38ba30ba
GN		 1143}
1144
dde7e6d1
AK		 1145static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1146 struct x86_emulate_ops *ops)
38ba30ba 1147{
dde7e6d1
AK		 1148 struct decode_cache *c = &ctxt->decode;
1149 int rc = X86EMUL_CONTINUE;
1150 int reg = VCPU_REGS_RDI;
38ba30ba 1151
dde7e6d1
AK		 1152 while (reg >= VCPU_REGS_RAX) {
1153 if (reg == VCPU_REGS_RSP) {
1154 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1155 c->op_bytes);
1156 --reg;
1157 }
38ba30ba 1158
dde7e6d1
AK		 1159 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1160 if (rc != X86EMUL_CONTINUE)
1161 break;
1162 --reg;
38ba30ba 1163 }
dde7e6d1 1164 return rc;
38ba30ba
GN		 1165}
1166
dde7e6d1
AK		 1167static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1168 struct x86_emulate_ops *ops)
38ba30ba 1169{
dde7e6d1
AK		 1170 struct decode_cache *c = &ctxt->decode;
1171 int rc = X86EMUL_CONTINUE;
1172 unsigned long temp_eip = 0;
1173 unsigned long temp_eflags = 0;
1174 unsigned long cs = 0;
1175 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1176 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1177 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1178 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1179
dde7e6d1 1180 /* TODO: Add stack limit check */
38ba30ba 1181
dde7e6d1 1182 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1183
dde7e6d1
AK		 1184 if (rc != X86EMUL_CONTINUE)
1185 return rc;
38ba30ba 1186
dde7e6d1
AK		 1187 if (temp_eip & ~0xffff) {
1188 emulate_gp(ctxt, 0);
1189 return X86EMUL_PROPAGATE_FAULT;
1190 }
38ba30ba 1191
dde7e6d1 1192 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1193
dde7e6d1
AK		 1194 if (rc != X86EMUL_CONTINUE)
1195 return rc;
38ba30ba 1196
dde7e6d1 1197 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1198
dde7e6d1
AK		 1199 if (rc != X86EMUL_CONTINUE)
1200 return rc;
38ba30ba 1201
dde7e6d1 1202 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1203
dde7e6d1
AK		 1204 if (rc != X86EMUL_CONTINUE)
1205 return rc;
38ba30ba 1206
dde7e6d1 1207 c->eip = temp_eip;
38ba30ba 1208
38ba30ba 1209
dde7e6d1
AK		 1210 if (c->op_bytes == 4)
1211 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1212 else if (c->op_bytes == 2) {
1213 ctxt->eflags &= ~0xffff;
1214 ctxt->eflags |= temp_eflags;
38ba30ba 1215 }
dde7e6d1
AK		 1216
1217 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1218 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1219
1220 return rc;
38ba30ba
GN		 1221}
1222
dde7e6d1
AK		 1223static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1224 struct x86_emulate_ops* ops)
c37eda13 1225{
dde7e6d1
AK		 1226 switch(ctxt->mode) {
1227 case X86EMUL_MODE_REAL:
1228 return emulate_iret_real(ctxt, ops);
1229 case X86EMUL_MODE_VM86:
1230 case X86EMUL_MODE_PROT16:
1231 case X86EMUL_MODE_PROT32:
1232 case X86EMUL_MODE_PROT64:
c37eda13 1233 default:
dde7e6d1
AK		 1234 /* iret from protected mode unimplemented yet */
1235 return X86EMUL_UNHANDLEABLE;
c37eda13 1236 }
c37eda13
WY		 1237}
1238
dde7e6d1 1239static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1240 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1241{
1242 struct decode_cache *c = &ctxt->decode;
1243
dde7e6d1 1244 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1245}
1246
dde7e6d1 1247static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1248{
05f086f8 1249 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1250 switch (c->modrm_reg) {
1251 case 0: /* rol */
05f086f8 1252 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1253 break;
1254 case 1: /* ror */
05f086f8 1255 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1256 break;
1257 case 2: /* rcl */
05f086f8 1258 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1259 break;
1260 case 3: /* rcr */
05f086f8 1261 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1262 break;
1263 case 4: /* sal/shl */
1264 case 6: /* sal/shl */
05f086f8 1265 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1266 break;
1267 case 5: /* shr */
05f086f8 1268 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1269 break;
1270 case 7: /* sar */
05f086f8 1271 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1272 break;
1273 }
1274}
1275
1276static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1277 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1278{
1279 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1280
1281 switch (c->modrm_reg) {
1282 case 0 ... 1: /* test */
05f086f8 1283 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1284 break;
1285 case 2: /* not */
1286 c->dst.val = ~c->dst.val;
1287 break;
1288 case 3: /* neg */
05f086f8 1289 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1290 break;
1291 default:
aca06a83 1292 return 0;
8cdbd2c9 1293 }
aca06a83 1294 return 1;
8cdbd2c9
LV		 1295}
1296
1297static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1298 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1299{
1300 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1301
1302 switch (c->modrm_reg) {
1303 case 0: /* inc */
05f086f8 1304 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1305 break;
1306 case 1: /* dec */
05f086f8 1307 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1308 break;
d19292e4
MG		 1309 case 2: /* call near abs */ {
1310 long int old_eip;
1311 old_eip = c->eip;
1312 c->eip = c->src.val;
1313 c->src.val = old_eip;
79168fd1 1314 emulate_push(ctxt, ops);
d19292e4
MG		 1315 break;
1316 }
8cdbd2c9 1317 case 4: /* jmp abs */
fd60754e 1318 c->eip = c->src.val;
8cdbd2c9
LV		 1319 break;
1320 case 6: /* push */
79168fd1 1321 emulate_push(ctxt, ops);
8cdbd2c9 1322 break;
8cdbd2c9 1323 }
1b30eaa8 1324 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1325}
1326
1327static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1328 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1329{
1330 struct decode_cache *c = &ctxt->decode;
16518d5a 1331 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1332
1333 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1334 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1335 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1336 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1337 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1338 } else {
16518d5a
AK		 1339 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1340 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1341
05f086f8 1342 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1343 }
1b30eaa8 1344 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1345}
1346
a77ab5ea
AK		 1347static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1348 struct x86_emulate_ops *ops)
1349{
1350 struct decode_cache *c = &ctxt->decode;
1351 int rc;
1352 unsigned long cs;
1353
1354 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1355 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1356 return rc;
1357 if (c->op_bytes == 4)
1358 c->eip = (u32)c->eip;
1359 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1360 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1361 return rc;
2e873022 1362 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1363 return rc;
1364}
1365
e66bb2cc
AP		 1366static inline void
1367setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1368 struct x86_emulate_ops *ops, struct desc_struct *cs,
1369 struct desc_struct *ss)
e66bb2cc 1370{
79168fd1
GN		 1371 memset(cs, 0, sizeof(struct desc_struct));
1372 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1373 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1374
1375 cs->l = 0; /* will be adjusted later */
79168fd1 1376 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1377 cs->g = 1; /* 4kb granularity */
79168fd1 1378 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1379 cs->type = 0x0b; /* Read, Execute, Accessed */
1380 cs->s = 1;
1381 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1382 cs->p = 1;
1383 cs->d = 1;
e66bb2cc 1384
79168fd1
GN		 1385 set_desc_base(ss, 0); /* flat segment */
1386 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1387 ss->g = 1; /* 4kb granularity */
1388 ss->s = 1;
1389 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1390 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1391 ss->dpl = 0;
79168fd1 1392 ss->p = 1;
e66bb2cc
AP		 1393}
1394
1395static int
3fb1b5db 1396emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1397{
1398 struct decode_cache *c = &ctxt->decode;
79168fd1 1399 struct desc_struct cs, ss;
e66bb2cc 1400 u64 msr_data;
79168fd1 1401 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1402
1403 /* syscall is not available in real mode */
2e901c4c
GN		 1404 if (ctxt->mode == X86EMUL_MODE_REAL ||
1405 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1406 emulate_ud(ctxt);
2e901c4c
GN		 1407 return X86EMUL_PROPAGATE_FAULT;
1408 }
e66bb2cc 1409
79168fd1 1410 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1411
3fb1b5db 1412 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1413 msr_data >>= 32;
79168fd1
GN		 1414 cs_sel = (u16)(msr_data & 0xfffc);
1415 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1416
1417 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1418 cs.d = 0;
e66bb2cc
AP		 1419 cs.l = 1;
1420 }
79168fd1
GN		 1421 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1422 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1423 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1424 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1425
1426 c->regs[VCPU_REGS_RCX] = c->eip;
1427 if (is_long_mode(ctxt->vcpu)) {
1428#ifdef CONFIG_X86_64
1429 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1430
3fb1b5db
GN		 1431 ops->get_msr(ctxt->vcpu,
1432 ctxt->mode == X86EMUL_MODE_PROT64 ?
1433 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1434 c->eip = msr_data;
1435
3fb1b5db 1436 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1437 ctxt->eflags &= ~(msr_data | EFLG_RF);
1438#endif
1439 } else {
1440 /* legacy mode */
3fb1b5db 1441 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1442 c->eip = (u32)msr_data;
1443
1444 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1445 }
1446
e54cfa97 1447 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1448}
1449
8c604352 1450static int
3fb1b5db 1451emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1452{
1453 struct decode_cache *c = &ctxt->decode;
79168fd1 1454 struct desc_struct cs, ss;
8c604352 1455 u64 msr_data;
79168fd1 1456 u16 cs_sel, ss_sel;
8c604352 1457
a0044755
GN		 1458 /* inject #GP if in real mode */
1459 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1460 emulate_gp(ctxt, 0);
2e901c4c 1461 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1462 }
1463
1464 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1465 * Therefore, we inject an #UD.
1466 */
2e901c4c 1467 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1468 emulate_ud(ctxt);
2e901c4c
GN		 1469 return X86EMUL_PROPAGATE_FAULT;
1470 }
8c604352 1471
79168fd1 1472 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1473
3fb1b5db 1474 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1475 switch (ctxt->mode) {
1476 case X86EMUL_MODE_PROT32:
1477 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1478 emulate_gp(ctxt, 0);
e54cfa97 1479 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1480 }
1481 break;
1482 case X86EMUL_MODE_PROT64:
1483 if (msr_data == 0x0) {
54b8486f 1484 emulate_gp(ctxt, 0);
e54cfa97 1485 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1486 }
1487 break;
1488 }
1489
1490 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1491 cs_sel = (u16)msr_data;
1492 cs_sel &= ~SELECTOR_RPL_MASK;
1493 ss_sel = cs_sel + 8;
1494 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1495 if (ctxt->mode == X86EMUL_MODE_PROT64
1496 || is_long_mode(ctxt->vcpu)) {
79168fd1 1497 cs.d = 0;
8c604352
AP		 1498 cs.l = 1;
1499 }
1500
79168fd1
GN		 1501 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1502 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1503 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1504 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1505
3fb1b5db 1506 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1507 c->eip = msr_data;
1508
3fb1b5db 1509 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1510 c->regs[VCPU_REGS_RSP] = msr_data;
1511
e54cfa97 1512 return X86EMUL_CONTINUE;
8c604352
AP		 1513}
1514
4668f050 1515static int
3fb1b5db 1516emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1517{
1518 struct decode_cache *c = &ctxt->decode;
79168fd1 1519 struct desc_struct cs, ss;
4668f050
AP		 1520 u64 msr_data;
1521 int usermode;
79168fd1 1522 u16 cs_sel, ss_sel;
4668f050 1523
a0044755
GN		 1524 /* inject #GP if in real mode or Virtual 8086 mode */
1525 if (ctxt->mode == X86EMUL_MODE_REAL ||
1526 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1527 emulate_gp(ctxt, 0);
2e901c4c 1528 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1529 }
1530
79168fd1 1531 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1532
1533 if ((c->rex_prefix & 0x8) != 0x0)
1534 usermode = X86EMUL_MODE_PROT64;
1535 else
1536 usermode = X86EMUL_MODE_PROT32;
1537
1538 cs.dpl = 3;
1539 ss.dpl = 3;
3fb1b5db 1540 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1541 switch (usermode) {
1542 case X86EMUL_MODE_PROT32:
79168fd1 1543 cs_sel = (u16)(msr_data + 16);
4668f050 1544 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1545 emulate_gp(ctxt, 0);
e54cfa97 1546 return X86EMUL_PROPAGATE_FAULT;
4668f050 1547 }
79168fd1 1548 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1549 break;
1550 case X86EMUL_MODE_PROT64:
79168fd1 1551 cs_sel = (u16)(msr_data + 32);
4668f050 1552 if (msr_data == 0x0) {
54b8486f 1553 emulate_gp(ctxt, 0);
e54cfa97 1554 return X86EMUL_PROPAGATE_FAULT;
4668f050 1555 }
79168fd1
GN		 1556 ss_sel = cs_sel + 8;
1557 cs.d = 0;
4668f050
AP		 1558 cs.l = 1;
1559 break;
1560 }
79168fd1
GN		 1561 cs_sel |= SELECTOR_RPL_MASK;
1562 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1563
79168fd1
GN		 1564 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1565 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1566 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1567 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1568
bdb475a3
GN		 1569 c->eip = c->regs[VCPU_REGS_RDX];
1570 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1571
e54cfa97 1572 return X86EMUL_CONTINUE;
4668f050
AP		 1573}
1574
9c537244
GN		 1575static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1576 struct x86_emulate_ops *ops)
f850e2e6
GN		 1577{
1578 int iopl;
1579 if (ctxt->mode == X86EMUL_MODE_REAL)
1580 return false;
1581 if (ctxt->mode == X86EMUL_MODE_VM86)
1582 return true;
1583 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1584 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1585}
1586
1587static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1588 struct x86_emulate_ops *ops,
1589 u16 port, u16 len)
1590{
79168fd1 1591 struct desc_struct tr_seg;
f850e2e6
GN		 1592 int r;
1593 u16 io_bitmap_ptr;
1594 u8 perm, bit_idx = port & 0x7;
1595 unsigned mask = (1 << len) - 1;
1596
79168fd1
GN		 1597 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1598 if (!tr_seg.p)
f850e2e6 1599 return false;
79168fd1 1600 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1601 return false;
79168fd1
GN		 1602 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1603 ctxt->vcpu, NULL);
f850e2e6
GN		 1604 if (r != X86EMUL_CONTINUE)
1605 return false;
79168fd1 1606 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1607 return false;
79168fd1
GN		 1608 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1609 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1610 if (r != X86EMUL_CONTINUE)
1611 return false;
1612 if ((perm >> bit_idx) & mask)
1613 return false;
1614 return true;
1615}
1616
1617static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1618 struct x86_emulate_ops *ops,
1619 u16 port, u16 len)
1620{
4fc40f07
GN		 1621 if (ctxt->perm_ok)
1622 return true;
1623
9c537244 1624 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1625 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1626 return false;
4fc40f07
GN		 1627
1628 ctxt->perm_ok = true;
1629
f850e2e6
GN		 1630 return true;
1631}
1632
38ba30ba
GN		 1633static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1634 struct x86_emulate_ops *ops,
1635 struct tss_segment_16 *tss)
1636{
1637 struct decode_cache *c = &ctxt->decode;
1638
1639 tss->ip = c->eip;
1640 tss->flag = ctxt->eflags;
1641 tss->ax = c->regs[VCPU_REGS_RAX];
1642 tss->cx = c->regs[VCPU_REGS_RCX];
1643 tss->dx = c->regs[VCPU_REGS_RDX];
1644 tss->bx = c->regs[VCPU_REGS_RBX];
1645 tss->sp = c->regs[VCPU_REGS_RSP];
1646 tss->bp = c->regs[VCPU_REGS_RBP];
1647 tss->si = c->regs[VCPU_REGS_RSI];
1648 tss->di = c->regs[VCPU_REGS_RDI];
1649
1650 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1651 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1652 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1653 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1654 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1655}
1656
1657static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1658 struct x86_emulate_ops *ops,
1659 struct tss_segment_16 *tss)
1660{
1661 struct decode_cache *c = &ctxt->decode;
1662 int ret;
1663
1664 c->eip = tss->ip;
1665 ctxt->eflags = tss->flag | 2;
1666 c->regs[VCPU_REGS_RAX] = tss->ax;
1667 c->regs[VCPU_REGS_RCX] = tss->cx;
1668 c->regs[VCPU_REGS_RDX] = tss->dx;
1669 c->regs[VCPU_REGS_RBX] = tss->bx;
1670 c->regs[VCPU_REGS_RSP] = tss->sp;
1671 c->regs[VCPU_REGS_RBP] = tss->bp;
1672 c->regs[VCPU_REGS_RSI] = tss->si;
1673 c->regs[VCPU_REGS_RDI] = tss->di;
1674
1675 /*
1676 * SDM says that segment selectors are loaded before segment
1677 * descriptors
1678 */
1679 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1680 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1681 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1682 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1683 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1684
1685 /*
1686 * Now load segment descriptors. If fault happenes at this stage
1687 * it is handled in a context of new task
1688 */
1689 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1690 if (ret != X86EMUL_CONTINUE)
1691 return ret;
1692 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1693 if (ret != X86EMUL_CONTINUE)
1694 return ret;
1695 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1696 if (ret != X86EMUL_CONTINUE)
1697 return ret;
1698 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1699 if (ret != X86EMUL_CONTINUE)
1700 return ret;
1701 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1702 if (ret != X86EMUL_CONTINUE)
1703 return ret;
1704
1705 return X86EMUL_CONTINUE;
1706}
1707
1708static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1709 struct x86_emulate_ops *ops,
1710 u16 tss_selector, u16 old_tss_sel,
1711 ulong old_tss_base, struct desc_struct *new_desc)
1712{
1713 struct tss_segment_16 tss_seg;
1714 int ret;
1715 u32 err, new_tss_base = get_desc_base(new_desc);
1716
1717 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1718 &err);
1719 if (ret == X86EMUL_PROPAGATE_FAULT) {
1720 /* FIXME: need to provide precise fault address */
54b8486f 1721 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1722 return ret;
1723 }
1724
1725 save_state_to_tss16(ctxt, ops, &tss_seg);
1726
1727 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1728 &err);
1729 if (ret == X86EMUL_PROPAGATE_FAULT) {
1730 /* FIXME: need to provide precise fault address */
54b8486f 1731 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1732 return ret;
1733 }
1734
1735 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1736 &err);
1737 if (ret == X86EMUL_PROPAGATE_FAULT) {
1738 /* FIXME: need to provide precise fault address */
54b8486f 1739 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1740 return ret;
1741 }
1742
1743 if (old_tss_sel != 0xffff) {
1744 tss_seg.prev_task_link = old_tss_sel;
1745
1746 ret = ops->write_std(new_tss_base,
1747 &tss_seg.prev_task_link,
1748 sizeof tss_seg.prev_task_link,
1749 ctxt->vcpu, &err);
1750 if (ret == X86EMUL_PROPAGATE_FAULT) {
1751 /* FIXME: need to provide precise fault address */
54b8486f 1752 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1753 return ret;
1754 }
1755 }
1756
1757 return load_state_from_tss16(ctxt, ops, &tss_seg);
1758}
1759
1760static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1761 struct x86_emulate_ops *ops,
1762 struct tss_segment_32 *tss)
1763{
1764 struct decode_cache *c = &ctxt->decode;
1765
1766 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1767 tss->eip = c->eip;
1768 tss->eflags = ctxt->eflags;
1769 tss->eax = c->regs[VCPU_REGS_RAX];
1770 tss->ecx = c->regs[VCPU_REGS_RCX];
1771 tss->edx = c->regs[VCPU_REGS_RDX];
1772 tss->ebx = c->regs[VCPU_REGS_RBX];
1773 tss->esp = c->regs[VCPU_REGS_RSP];
1774 tss->ebp = c->regs[VCPU_REGS_RBP];
1775 tss->esi = c->regs[VCPU_REGS_RSI];
1776 tss->edi = c->regs[VCPU_REGS_RDI];
1777
1778 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1779 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1780 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1781 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1782 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1783 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1784 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1785}
1786
1787static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1788 struct x86_emulate_ops *ops,
1789 struct tss_segment_32 *tss)
1790{
1791 struct decode_cache *c = &ctxt->decode;
1792 int ret;
1793
0f12244f 1794 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 1795 emulate_gp(ctxt, 0);
0f12244f
GN		 1796 return X86EMUL_PROPAGATE_FAULT;
1797 }
38ba30ba
GN		 1798 c->eip = tss->eip;
1799 ctxt->eflags = tss->eflags | 2;
1800 c->regs[VCPU_REGS_RAX] = tss->eax;
1801 c->regs[VCPU_REGS_RCX] = tss->ecx;
1802 c->regs[VCPU_REGS_RDX] = tss->edx;
1803 c->regs[VCPU_REGS_RBX] = tss->ebx;
1804 c->regs[VCPU_REGS_RSP] = tss->esp;
1805 c->regs[VCPU_REGS_RBP] = tss->ebp;
1806 c->regs[VCPU_REGS_RSI] = tss->esi;
1807 c->regs[VCPU_REGS_RDI] = tss->edi;
1808
1809 /*
1810 * SDM says that segment selectors are loaded before segment
1811 * descriptors
1812 */
1813 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1814 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1815 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1816 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1817 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1818 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1819 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1820
1821 /*
1822 * Now load segment descriptors. If fault happenes at this stage
1823 * it is handled in a context of new task
1824 */
1825 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1826 if (ret != X86EMUL_CONTINUE)
1827 return ret;
1828 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1829 if (ret != X86EMUL_CONTINUE)
1830 return ret;
1831 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1832 if (ret != X86EMUL_CONTINUE)
1833 return ret;
1834 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1835 if (ret != X86EMUL_CONTINUE)
1836 return ret;
1837 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1838 if (ret != X86EMUL_CONTINUE)
1839 return ret;
1840 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1841 if (ret != X86EMUL_CONTINUE)
1842 return ret;
1843 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1844 if (ret != X86EMUL_CONTINUE)
1845 return ret;
1846
1847 return X86EMUL_CONTINUE;
1848}
1849
1850static int task_switch_32(struct x86_emulate_ctxt *ctxt,
1851 struct x86_emulate_ops *ops,
1852 u16 tss_selector, u16 old_tss_sel,
1853 ulong old_tss_base, struct desc_struct *new_desc)
1854{
1855 struct tss_segment_32 tss_seg;
1856 int ret;
1857 u32 err, new_tss_base = get_desc_base(new_desc);
1858
1859 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1860 &err);
1861 if (ret == X86EMUL_PROPAGATE_FAULT) {
1862 /* FIXME: need to provide precise fault address */
54b8486f 1863 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1864 return ret;
1865 }
1866
1867 save_state_to_tss32(ctxt, ops, &tss_seg);
1868
1869 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1870 &err);
1871 if (ret == X86EMUL_PROPAGATE_FAULT) {
1872 /* FIXME: need to provide precise fault address */
54b8486f 1873 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1874 return ret;
1875 }
1876
1877 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1878 &err);
1879 if (ret == X86EMUL_PROPAGATE_FAULT) {
1880 /* FIXME: need to provide precise fault address */
54b8486f 1881 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1882 return ret;
1883 }
1884
1885 if (old_tss_sel != 0xffff) {
1886 tss_seg.prev_task_link = old_tss_sel;
1887
1888 ret = ops->write_std(new_tss_base,
1889 &tss_seg.prev_task_link,
1890 sizeof tss_seg.prev_task_link,
1891 ctxt->vcpu, &err);
1892 if (ret == X86EMUL_PROPAGATE_FAULT) {
1893 /* FIXME: need to provide precise fault address */
54b8486f 1894 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1895 return ret;
1896 }
1897 }
1898
1899 return load_state_from_tss32(ctxt, ops, &tss_seg);
1900}
1901
1902static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1903 struct x86_emulate_ops *ops,
1904 u16 tss_selector, int reason,
1905 bool has_error_code, u32 error_code)
38ba30ba
GN		 1906{
1907 struct desc_struct curr_tss_desc, next_tss_desc;
1908 int ret;
1909 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
1910 ulong old_tss_base =
5951c442 1911 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 1912 u32 desc_limit;
38ba30ba
GN		 1913
1914 /* FIXME: old_tss_base == ~0 ? */
1915
1916 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
1917 if (ret != X86EMUL_CONTINUE)
1918 return ret;
1919 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
1920 if (ret != X86EMUL_CONTINUE)
1921 return ret;
1922
1923 /* FIXME: check that next_tss_desc is tss */
1924
1925 if (reason != TASK_SWITCH_IRET) {
1926 if ((tss_selector & 3) > next_tss_desc.dpl ||
1927 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 1928 emulate_gp(ctxt, 0);
38ba30ba
GN		 1929 return X86EMUL_PROPAGATE_FAULT;
1930 }
1931 }
1932
ceffb459
GN		 1933 desc_limit = desc_limit_scaled(&next_tss_desc);
1934 if (!next_tss_desc.p ||
1935 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
1936 desc_limit < 0x2b)) {
54b8486f 1937 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 1938 return X86EMUL_PROPAGATE_FAULT;
1939 }
1940
1941 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
1942 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
1943 write_segment_descriptor(ctxt, ops, old_tss_sel,
1944 &curr_tss_desc);
1945 }
1946
1947 if (reason == TASK_SWITCH_IRET)
1948 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
1949
1950 /* set back link to prev task only if NT bit is set in eflags
1951 note that old_tss_sel is not used afetr this point */
1952 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
1953 old_tss_sel = 0xffff;
1954
1955 if (next_tss_desc.type & 8)
1956 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
1957 old_tss_base, &next_tss_desc);
1958 else
1959 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
1960 old_tss_base, &next_tss_desc);
0760d448
JK		 1961 if (ret != X86EMUL_CONTINUE)
1962 return ret;
38ba30ba
GN		 1963
1964 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
1965 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
1966
1967 if (reason != TASK_SWITCH_IRET) {
1968 next_tss_desc.type |= (1 << 1); /* set busy flag */
1969 write_segment_descriptor(ctxt, ops, tss_selector,
1970 &next_tss_desc);
1971 }
1972
1973 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
1974 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
1975 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
1976
e269fb21
JK		 1977 if (has_error_code) {
1978 struct decode_cache *c = &ctxt->decode;
1979
1980 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
1981 c->lock_prefix = 0;
1982 c->src.val = (unsigned long) error_code;
79168fd1 1983 emulate_push(ctxt, ops);
e269fb21
JK		 1984 }
1985
38ba30ba
GN		 1986 return ret;
1987}
1988
1989int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1990 u16 tss_selector, int reason,
1991 bool has_error_code, u32 error_code)
38ba30ba 1992{
9aabc88f 1993 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 1994 struct decode_cache *c = &ctxt->decode;
1995 int rc;
1996
38ba30ba 1997 c->eip = ctxt->eip;
e269fb21 1998 c->dst.type = OP_NONE;
38ba30ba 1999
e269fb21
JK		 2000 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2001 has_error_code, error_code);
38ba30ba
GN		 2002
2003 if (rc == X86EMUL_CONTINUE) {
e269fb21 2004 rc = writeback(ctxt, ops);
95c55886
GN		 2005 if (rc == X86EMUL_CONTINUE)
2006 ctxt->eip = c->eip;
38ba30ba
GN		 2007 }
2008
19d04437 2009 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2010}
2011
a682e354 2012static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2013 int reg, struct operand *op)
a682e354
GN		 2014{
2015 struct decode_cache *c = &ctxt->decode;
2016 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2017
d9271123 2018 register_address_increment(c, &c->regs[reg], df * op->bytes);
1a6440ae 2019 op->addr.mem = register_address(c, base, c->regs[reg]);
a682e354
GN		 2020}
2021
63540382
AK		 2022static int em_push(struct x86_emulate_ctxt *ctxt)
2023{
2024 emulate_push(ctxt, ctxt->ops);
2025 return X86EMUL_CONTINUE;
2026}
2027
73fba5f4
AK		 2028#define D(_y) { .flags = (_y) }
2029#define N D(0)
2030#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2031#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2032#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2033
2034static struct opcode group1[] = {
2035 X7(D(Lock)), N
2036};
2037
2038static struct opcode group1A[] = {
2039 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2040};
2041
2042static struct opcode group3[] = {
2043 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2044 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2045 X4(D(Undefined)),
2046};
2047
2048static struct opcode group4[] = {
2049 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2050 N, N, N, N, N, N,
2051};
2052
2053static struct opcode group5[] = {
2054 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2055 D(SrcMem | ModRM | Stack), N,
2056 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2057 D(SrcMem | ModRM | Stack), N,
2058};
2059
2060static struct group_dual group7 = { {
2061 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2062 D(SrcNone | ModRM | DstMem | Mov), N,
2063 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2064}, {
2065 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2066 D(SrcNone | ModRM | DstMem | Mov), N,
2067 D(SrcMem16 | ModRM | Mov | Priv), N,
2068} };
2069
2070static struct opcode group8[] = {
2071 N, N, N, N,
2072 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2073 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2074};
2075
2076static struct group_dual group9 = { {
2077 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2078}, {
2079 N, N, N, N, N, N, N, N,
2080} };
2081
2082static struct opcode opcode_table[256] = {
2083 /* 0x00 - 0x07 */
2084 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2085 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2086 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2087 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2088 /* 0x08 - 0x0F */
2089 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2090 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2091 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2092 D(ImplicitOps | Stack | No64), N,
2093 /* 0x10 - 0x17 */
2094 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2095 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2096 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2097 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2098 /* 0x18 - 0x1F */
2099 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2100 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2101 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2102 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2103 /* 0x20 - 0x27 */
2104 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2105 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2106 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2107 /* 0x28 - 0x2F */
2108 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2109 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2110 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2111 /* 0x30 - 0x37 */
2112 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2113 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2114 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2115 /* 0x38 - 0x3F */
2116 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2117 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2118 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2119 N, N,
2120 /* 0x40 - 0x4F */
2121 X16(D(DstReg)),
2122 /* 0x50 - 0x57 */
63540382 2123 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2124 /* 0x58 - 0x5F */
2125 X8(D(DstReg | Stack)),
2126 /* 0x60 - 0x67 */
2127 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2128 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2129 N, N, N, N,
2130 /* 0x68 - 0x6F */
63540382
AK		 2131 I(SrcImm | Mov | Stack, em_push), N,
2132 I(SrcImmByte | Mov | Stack, em_push), N,
73fba5f4
AK		 2133 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2134 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2135 /* 0x70 - 0x7F */
2136 X16(D(SrcImmByte)),
2137 /* 0x80 - 0x87 */
2138 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2139 G(DstMem | SrcImm | ModRM | Group, group1),
2140 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2141 G(DstMem | SrcImmByte | ModRM | Group, group1),
2142 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2143 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2144 /* 0x88 - 0x8F */
2145 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2146 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2147 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
2148 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2149 /* 0x90 - 0x97 */
3d9e77df 2150 X8(D(SrcAcc | DstReg)),
73fba5f4
AK		 2151 /* 0x98 - 0x9F */
2152 N, N, D(SrcImmFAddr | No64), N,
2153 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2154 /* 0xA0 - 0xA7 */
2155 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2156 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2157 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2158 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2159 /* 0xA8 - 0xAF */
2160 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
2161 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2162 D(ByteOp | DstDI | String), D(DstDI | String),
2163 /* 0xB0 - 0xB7 */
2164 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2165 /* 0xB8 - 0xBF */
2166 X8(D(DstReg | SrcImm | Mov)),
2167 /* 0xC0 - 0xC7 */
2168 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2169 N, D(ImplicitOps | Stack), N, N,
2170 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2171 /* 0xC8 - 0xCF */
2172 N, N, N, D(ImplicitOps | Stack),
2173 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2174 /* 0xD0 - 0xD7 */
2175 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2176 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2177 N, N, N, N,
2178 /* 0xD8 - 0xDF */
2179 N, N, N, N, N, N, N, N,
2180 /* 0xE0 - 0xE7 */
2181 N, N, N, N,
2182 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2183 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2184 /* 0xE8 - 0xEF */
2185 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2186 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2187 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2188 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2189 /* 0xF0 - 0xF7 */
2190 N, N, N, N,
2191 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2192 /* 0xF8 - 0xFF */
2193 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
2194 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2195};
2196
2197static struct opcode twobyte_table[256] = {
2198 /* 0x00 - 0x0F */
2199 N, GD(0, &group7), N, N,
2200 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2201 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2202 N, D(ImplicitOps | ModRM), N, N,
2203 /* 0x10 - 0x1F */
2204 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2205 /* 0x20 - 0x2F */
2206 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2207 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2208 N, N, N, N,
2209 N, N, N, N, N, N, N, N,
2210 /* 0x30 - 0x3F */
2211 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2212 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2213 N, N, N, N, N, N, N, N,
2214 /* 0x40 - 0x4F */
2215 X16(D(DstReg | SrcMem | ModRM | Mov)),
2216 /* 0x50 - 0x5F */
2217 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2218 /* 0x60 - 0x6F */
2219 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2220 /* 0x70 - 0x7F */
2221 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2222 /* 0x80 - 0x8F */
2223 X16(D(SrcImm)),
2224 /* 0x90 - 0x9F */
2225 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2226 /* 0xA0 - 0xA7 */
2227 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2228 N, D(DstMem | SrcReg | ModRM | BitOp),
2229 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2230 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2231 /* 0xA8 - 0xAF */
2232 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2233 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2234 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2235 D(DstMem | SrcReg | Src2CL | ModRM),
2236 D(ModRM), N,
2237 /* 0xB0 - 0xB7 */
2238 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2239 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2240 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2241 D(DstReg | SrcMem16 | ModRM | Mov),
2242 /* 0xB8 - 0xBF */
2243 N, N,
2244 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2245 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2246 D(DstReg | SrcMem16 | ModRM | Mov),
2247 /* 0xC0 - 0xCF */
2248 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
2249 N, N, N, GD(0, &group9),
2250 N, N, N, N, N, N, N, N,
2251 /* 0xD0 - 0xDF */
2252 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2253 /* 0xE0 - 0xEF */
2254 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2255 /* 0xF0 - 0xFF */
2256 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2257};
2258
2259#undef D
2260#undef N
2261#undef G
2262#undef GD
2263#undef I
2264
dde7e6d1
AK		 2265int
2266x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2267{
2268 struct x86_emulate_ops *ops = ctxt->ops;
2269 struct decode_cache *c = &ctxt->decode;
2270 int rc = X86EMUL_CONTINUE;
2271 int mode = ctxt->mode;
2272 int def_op_bytes, def_ad_bytes, dual, goffset;
2273 struct opcode opcode, *g_mod012, *g_mod3;
2274
2275 /* we cannot decode insn before we complete previous rep insn */
2276 WARN_ON(ctxt->restart);
2277
2278 c->eip = ctxt->eip;
2279 c->fetch.start = c->fetch.end = c->eip;
2280 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2281
2282 switch (mode) {
2283 case X86EMUL_MODE_REAL:
2284 case X86EMUL_MODE_VM86:
2285 case X86EMUL_MODE_PROT16:
2286 def_op_bytes = def_ad_bytes = 2;
2287 break;
2288 case X86EMUL_MODE_PROT32:
2289 def_op_bytes = def_ad_bytes = 4;
2290 break;
2291#ifdef CONFIG_X86_64
2292 case X86EMUL_MODE_PROT64:
2293 def_op_bytes = 4;
2294 def_ad_bytes = 8;
2295 break;
2296#endif
2297 default:
2298 return -1;
2299 }
2300
2301 c->op_bytes = def_op_bytes;
2302 c->ad_bytes = def_ad_bytes;
2303
2304 /* Legacy prefixes. */
2305 for (;;) {
2306 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2307 case 0x66: /* operand-size override */
2308 /* switch between 2/4 bytes */
2309 c->op_bytes = def_op_bytes ^ 6;
2310 break;
2311 case 0x67: /* address-size override */
2312 if (mode == X86EMUL_MODE_PROT64)
2313 /* switch between 4/8 bytes */
2314 c->ad_bytes = def_ad_bytes ^ 12;
2315 else
2316 /* switch between 2/4 bytes */
2317 c->ad_bytes = def_ad_bytes ^ 6;
2318 break;
2319 case 0x26: /* ES override */
2320 case 0x2e: /* CS override */
2321 case 0x36: /* SS override */
2322 case 0x3e: /* DS override */
2323 set_seg_override(c, (c->b >> 3) & 3);
2324 break;
2325 case 0x64: /* FS override */
2326 case 0x65: /* GS override */
2327 set_seg_override(c, c->b & 7);
2328 break;
2329 case 0x40 ... 0x4f: /* REX */
2330 if (mode != X86EMUL_MODE_PROT64)
2331 goto done_prefixes;
2332 c->rex_prefix = c->b;
2333 continue;
2334 case 0xf0: /* LOCK */
2335 c->lock_prefix = 1;
2336 break;
2337 case 0xf2: /* REPNE/REPNZ */
2338 c->rep_prefix = REPNE_PREFIX;
2339 break;
2340 case 0xf3: /* REP/REPE/REPZ */
2341 c->rep_prefix = REPE_PREFIX;
2342 break;
2343 default:
2344 goto done_prefixes;
2345 }
2346
2347 /* Any legacy prefix after a REX prefix nullifies its effect. */
2348
2349 c->rex_prefix = 0;
2350 }
2351
2352done_prefixes:
2353
2354 /* REX prefix. */
2355 if (c->rex_prefix)
2356 if (c->rex_prefix & 8)
2357 c->op_bytes = 8; /* REX.W */
2358
2359 /* Opcode byte(s). */
2360 opcode = opcode_table[c->b];
2361 if (opcode.flags == 0) {
2362 /* Two-byte opcode? */
2363 if (c->b == 0x0f) {
2364 c->twobyte = 1;
2365 c->b = insn_fetch(u8, 1, c->eip);
2366 opcode = twobyte_table[c->b];
2367 }
2368 }
2369 c->d = opcode.flags;
2370
2371 if (c->d & Group) {
2372 dual = c->d & GroupDual;
2373 c->modrm = insn_fetch(u8, 1, c->eip);
2374 --c->eip;
2375
2376 if (c->d & GroupDual) {
2377 g_mod012 = opcode.u.gdual->mod012;
2378 g_mod3 = opcode.u.gdual->mod3;
2379 } else
2380 g_mod012 = g_mod3 = opcode.u.group;
2381
2382 c->d &= ~(Group | GroupDual);
2383
2384 goffset = (c->modrm >> 3) & 7;
2385
2386 if ((c->modrm >> 6) == 3)
2387 opcode = g_mod3[goffset];
2388 else
2389 opcode = g_mod012[goffset];
2390 c->d |= opcode.flags;
2391 }
2392
2393 c->execute = opcode.u.execute;
2394
2395 /* Unrecognised? */
2396 if (c->d == 0 || (c->d & Undefined)) {
2397 DPRINTF("Cannot emulate %02x\n", c->b);
2398 return -1;
2399 }
2400
2401 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2402 c->op_bytes = 8;
2403
2404 /* ModRM and SIB bytes. */
09ee57cd 2405 if (c->d & ModRM) {
dde7e6d1 2406 rc = decode_modrm(ctxt, ops);
09ee57cd
AK		 2407 if (!c->has_seg_override)
2408 set_seg_override(c, c->modrm_seg);
2409 } else if (c->d & MemAbs)
dde7e6d1
AK		 2410 rc = decode_abs(ctxt, ops);
2411 if (rc != X86EMUL_CONTINUE)
2412 goto done;
2413
2414 if (!c->has_seg_override)
2415 set_seg_override(c, VCPU_SREG_DS);
2416
2417 if (!(!c->twobyte && c->b == 0x8d))
2418 c->modrm_ea += seg_override_base(ctxt, ops, c);
2419
2420 if (c->ad_bytes != 8)
2421 c->modrm_ea = (u32)c->modrm_ea;
2422
2423 if (c->rip_relative)
2424 c->modrm_ea += c->eip;
2425
2426 /*
2427 * Decode and fetch the source operand: register, memory
2428 * or immediate.
2429 */
2430 switch (c->d & SrcMask) {
2431 case SrcNone:
2432 break;
2433 case SrcReg:
2434 decode_register_operand(&c->src, c, 0);
2435 break;
2436 case SrcMem16:
2437 c->src.bytes = 2;
2438 goto srcmem_common;
2439 case SrcMem32:
2440 c->src.bytes = 4;
2441 goto srcmem_common;
2442 case SrcMem:
2443 c->src.bytes = (c->d & ByteOp) ? 1 :
2444 c->op_bytes;
2445 /* Don't fetch the address for invlpg: it could be unmapped. */
2446 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
2447 break;
2448 srcmem_common:
2449 /*
2450 * For instructions with a ModR/M byte, switch to register
2451 * access if Mod = 3.
2452 */
2453 if ((c->d & ModRM) && c->modrm_mod == 3) {
2454 c->src.type = OP_REG;
2455 c->src.val = c->modrm_val;
1a6440ae 2456 c->src.addr.reg = c->modrm_ptr;
dde7e6d1
AK		 2457 break;
2458 }
2459 c->src.type = OP_MEM;
1a6440ae 2460 c->src.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2461 c->src.val = 0;
2462 break;
2463 case SrcImm:
2464 case SrcImmU:
2465 c->src.type = OP_IMM;
1a6440ae 2466 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2467 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2468 if (c->src.bytes == 8)
2469 c->src.bytes = 4;
2470 /* NB. Immediates are sign-extended as necessary. */
2471 switch (c->src.bytes) {
2472 case 1:
2473 c->src.val = insn_fetch(s8, 1, c->eip);
2474 break;
2475 case 2:
2476 c->src.val = insn_fetch(s16, 2, c->eip);
2477 break;
2478 case 4:
2479 c->src.val = insn_fetch(s32, 4, c->eip);
2480 break;
2481 }
2482 if ((c->d & SrcMask) == SrcImmU) {
2483 switch (c->src.bytes) {
2484 case 1:
2485 c->src.val &= 0xff;
2486 break;
2487 case 2:
2488 c->src.val &= 0xffff;
2489 break;
2490 case 4:
2491 c->src.val &= 0xffffffff;
2492 break;
2493 }
2494 }
2495 break;
2496 case SrcImmByte:
2497 case SrcImmUByte:
2498 c->src.type = OP_IMM;
1a6440ae 2499 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2500 c->src.bytes = 1;
2501 if ((c->d & SrcMask) == SrcImmByte)
2502 c->src.val = insn_fetch(s8, 1, c->eip);
2503 else
2504 c->src.val = insn_fetch(u8, 1, c->eip);
2505 break;
2506 case SrcAcc:
2507 c->src.type = OP_REG;
2508 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2509 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
dde7e6d1
AK		 2510 switch (c->src.bytes) {
2511 case 1:
1a6440ae 2512 c->src.val = *(u8 *)c->src.addr.reg;
dde7e6d1
AK		 2513 break;
2514 case 2:
1a6440ae 2515 c->src.val = *(u16 *)c->src.addr.reg;
dde7e6d1
AK		 2516 break;
2517 case 4:
1a6440ae 2518 c->src.val = *(u32 *)c->src.addr.reg;
dde7e6d1
AK		 2519 break;
2520 case 8:
1a6440ae 2521 c->src.val = *(u64 *)c->src.addr.reg;
dde7e6d1
AK		 2522 break;
2523 }
2524 break;
2525 case SrcOne:
2526 c->src.bytes = 1;
2527 c->src.val = 1;
2528 break;
2529 case SrcSI:
2530 c->src.type = OP_MEM;
2531 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2532 c->src.addr.mem =
dde7e6d1
AK		 2533 register_address(c, seg_override_base(ctxt, ops, c),
2534 c->regs[VCPU_REGS_RSI]);
2535 c->src.val = 0;
2536 break;
2537 case SrcImmFAddr:
2538 c->src.type = OP_IMM;
1a6440ae 2539 c->src.addr.mem = c->eip;
dde7e6d1
AK		 2540 c->src.bytes = c->op_bytes + 2;
2541 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2542 break;
2543 case SrcMemFAddr:
2544 c->src.type = OP_MEM;
1a6440ae 2545 c->src.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2546 c->src.bytes = c->op_bytes + 2;
2547 break;
2548 }
2549
2550 /*
2551 * Decode and fetch the second source operand: register, memory
2552 * or immediate.
2553 */
2554 switch (c->d & Src2Mask) {
2555 case Src2None:
2556 break;
2557 case Src2CL:
2558 c->src2.bytes = 1;
2559 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2560 break;
2561 case Src2ImmByte:
2562 c->src2.type = OP_IMM;
1a6440ae 2563 c->src2.addr.mem = c->eip;
dde7e6d1
AK		 2564 c->src2.bytes = 1;
2565 c->src2.val = insn_fetch(u8, 1, c->eip);
2566 break;
2567 case Src2One:
2568 c->src2.bytes = 1;
2569 c->src2.val = 1;
2570 break;
2571 }
2572
2573 /* Decode and fetch the destination operand: register or memory. */
2574 switch (c->d & DstMask) {
2575 case ImplicitOps:
2576 /* Special instructions do their own operand decoding. */
2577 return 0;
2578 case DstReg:
2579 decode_register_operand(&c->dst, c,
2580 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2581 break;
2582 case DstMem:
2583 case DstMem64:
2584 if ((c->d & ModRM) && c->modrm_mod == 3) {
2585 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2586 c->dst.type = OP_REG;
2587 c->dst.val = c->dst.orig_val = c->modrm_val;
1a6440ae 2588 c->dst.addr.reg = c->modrm_ptr;
dde7e6d1
AK		 2589 break;
2590 }
2591 c->dst.type = OP_MEM;
1a6440ae 2592 c->dst.addr.mem = c->modrm_ea;
dde7e6d1
AK		 2593 if ((c->d & DstMask) == DstMem64)
2594 c->dst.bytes = 8;
2595 else
2596 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2597 c->dst.val = 0;
2598 if (c->d & BitOp) {
2599 unsigned long mask = ~(c->dst.bytes * 8 - 1);
2600
1a6440ae 2601 c->dst.addr.mem = c->dst.addr.mem +
dde7e6d1
AK		 2602 (c->src.val & mask) / 8;
2603 }
2604 break;
2605 case DstAcc:
2606 c->dst.type = OP_REG;
2607 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2608 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
dde7e6d1
AK		 2609 switch (c->dst.bytes) {
2610 case 1:
1a6440ae 2611 c->dst.val = *(u8 *)c->dst.addr.reg;
dde7e6d1
AK		 2612 break;
2613 case 2:
1a6440ae 2614 c->dst.val = *(u16 *)c->dst.addr.reg;
dde7e6d1
AK		 2615 break;
2616 case 4:
1a6440ae 2617 c->dst.val = *(u32 *)c->dst.addr.reg;
dde7e6d1
AK		 2618 break;
2619 case 8:
1a6440ae 2620 c->dst.val = *(u64 *)c->dst.addr.reg;
dde7e6d1
AK		 2621 break;
2622 }
2623 c->dst.orig_val = c->dst.val;
2624 break;
2625 case DstDI:
2626 c->dst.type = OP_MEM;
2627 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 2628 c->dst.addr.mem =
dde7e6d1
AK		 2629 register_address(c, es_base(ctxt, ops),
2630 c->regs[VCPU_REGS_RDI]);
2631 c->dst.val = 0;
2632 break;
2633 }
2634
2635done:
2636 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2637}
2638
8b4caf66 2639int
9aabc88f 2640x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2641{
9aabc88f 2642 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2643 u64 msr_data;
8b4caf66 2644 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2645 int rc = X86EMUL_CONTINUE;
5cd21917 2646 int saved_dst_type = c->dst.type;
8b4caf66 2647
9de41573 2648 ctxt->decode.mem_read.pos = 0;
310b5d30 2649
1161624f 2650 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2651 emulate_ud(ctxt);
1161624f
GN		 2652 goto done;
2653 }
2654
d380a5e4 2655 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2656 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2657 emulate_ud(ctxt);
d380a5e4
GN		 2658 goto done;
2659 }
2660
e92805ac 2661 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2662 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2663 emulate_gp(ctxt, 0);
e92805ac
GN		 2664 goto done;
2665 }
2666
b9fa9d6b 2667 if (c->rep_prefix && (c->d & String)) {
5cd21917 2668 ctxt->restart = true;
b9fa9d6b 2669 /* All REP prefixes have the same first termination condition */
c73e197b 2670 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2671 string_done:
2672 ctxt->restart = false;
95c55886 2673 ctxt->eip = c->eip;
b9fa9d6b
AK		 2674 goto done;
2675 }
2676 /* The second termination condition only applies for REPE
2677 * and REPNE. Test if the repeat string operation prefix is
2678 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2679 * corresponding termination condition according to:
2680 * - if REPE/REPZ and ZF = 0 then done
2681 * - if REPNE/REPNZ and ZF = 1 then done
2682 */
2683 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2684 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2685 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2686 ((ctxt->eflags & EFLG_ZF) == 0))
2687 goto string_done;
b9fa9d6b 2688 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2689 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2690 goto string_done;
b9fa9d6b 2691 }
063db061 2692 c->eip = ctxt->eip;
b9fa9d6b
AK		 2693 }
2694
8b4caf66 2695 if (c->src.type == OP_MEM) {
1a6440ae 2696 rc = read_emulated(ctxt, ops, c->src.addr.mem,
414e6277 2697 c->src.valptr, c->src.bytes);
b60d513c 2698 if (rc != X86EMUL_CONTINUE)
8b4caf66 2699 goto done;
16518d5a 2700 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2701 }
2702
e35b7b9c 2703 if (c->src2.type == OP_MEM) {
1a6440ae 2704 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
9de41573 2705 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2706 if (rc != X86EMUL_CONTINUE)
2707 goto done;
2708 }
2709
8b4caf66
LV		 2710 if ((c->d & DstMask) == ImplicitOps)
2711 goto special_insn;
2712
2713
69f55cb1
GN		 2714 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2715 /* optimisation - avoid slow emulated read if Mov */
1a6440ae 2716 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
9de41573 2717 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2718 if (rc != X86EMUL_CONTINUE)
2719 goto done;
038e51de 2720 }
e4e03ded 2721 c->dst.orig_val = c->dst.val;
038e51de 2722
018a98db
AK		 2723special_insn:
2724
ef65c889
AK		 2725 if (c->execute) {
2726 rc = c->execute(ctxt);
2727 if (rc != X86EMUL_CONTINUE)
2728 goto done;
2729 goto writeback;
2730 }
2731
e4e03ded 2732 if (c->twobyte)
6aa8b732
AK		 2733 goto twobyte_insn;
2734
e4e03ded 2735 switch (c->b) {
6aa8b732
AK		 2736 case 0x00 ... 0x05:
2737 add: /* add */
05f086f8 2738 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2739 break;
0934ac9d 2740 case 0x06: /* push es */
79168fd1 2741 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2742 break;
2743 case 0x07: /* pop es */
0934ac9d 2744 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2745 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2746 goto done;
2747 break;
6aa8b732
AK		 2748 case 0x08 ... 0x0d:
2749 or: /* or */
05f086f8 2750 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2751 break;
0934ac9d 2752 case 0x0e: /* push cs */
79168fd1 2753 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2754 break;
6aa8b732
AK		 2755 case 0x10 ... 0x15:
2756 adc: /* adc */
05f086f8 2757 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2758 break;
0934ac9d 2759 case 0x16: /* push ss */
79168fd1 2760 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2761 break;
2762 case 0x17: /* pop ss */
0934ac9d 2763 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2764 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2765 goto done;
2766 break;
6aa8b732
AK		 2767 case 0x18 ... 0x1d:
2768 sbb: /* sbb */
05f086f8 2769 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2770 break;
0934ac9d 2771 case 0x1e: /* push ds */
79168fd1 2772 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2773 break;
2774 case 0x1f: /* pop ds */
0934ac9d 2775 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2776 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2777 goto done;
2778 break;
aa3a816b 2779 case 0x20 ... 0x25:
6aa8b732 2780 and: /* and */
05f086f8 2781 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2782 break;
2783 case 0x28 ... 0x2d:
2784 sub: /* sub */
05f086f8 2785 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2786 break;
2787 case 0x30 ... 0x35:
2788 xor: /* xor */
05f086f8 2789 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2790 break;
2791 case 0x38 ... 0x3d:
2792 cmp: /* cmp */
05f086f8 2793 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2794 break;
33615aa9
AK		 2795 case 0x40 ... 0x47: /* inc r16/r32 */
2796 emulate_1op("inc", c->dst, ctxt->eflags);
2797 break;
2798 case 0x48 ... 0x4f: /* dec r16/r32 */
2799 emulate_1op("dec", c->dst, ctxt->eflags);
2800 break;
33615aa9
AK		 2801 case 0x58 ... 0x5f: /* pop reg */
2802 pop_instruction:
350f69dc 2803 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2804 if (rc != X86EMUL_CONTINUE)
33615aa9 2805 goto done;
33615aa9 2806 break;
abcf14b5 2807 case 0x60: /* pusha */
c37eda13
WY		 2808 rc = emulate_pusha(ctxt, ops);
2809 if (rc != X86EMUL_CONTINUE)
2810 goto done;
abcf14b5
MG		 2811 break;
2812 case 0x61: /* popa */
2813 rc = emulate_popa(ctxt, ops);
1b30eaa8 2814 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2815 goto done;
2816 break;
6aa8b732 2817 case 0x63: /* movsxd */
8b4caf66 2818 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2819 goto cannot_emulate;
e4e03ded 2820 c->dst.val = (s32) c->src.val;
6aa8b732 2821 break;
018a98db
AK		 2822 case 0x6c: /* insb */
2823 case 0x6d: /* insw/insd */
7972995b 2824 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2825 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2826 c->dst.bytes)) {
54b8486f 2827 emulate_gp(ctxt, 0);
f850e2e6
GN		 2828 goto done;
2829 }
7b262e90
GN		 2830 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2831 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2832 goto done; /* IO is needed, skip writeback */
2833 break;
018a98db
AK		 2834 case 0x6e: /* outsb */
2835 case 0x6f: /* outsw/outsd */
7972995b 2836 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2837 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2838 c->src.bytes)) {
54b8486f 2839 emulate_gp(ctxt, 0);
f850e2e6
GN		 2840 goto done;
2841 }
7972995b
GN		 2842 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2843 &c->src.val, 1, ctxt->vcpu);
2844
2845 c->dst.type = OP_NONE; /* nothing to writeback */
2846 break;
b2833e3c 2847 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2848 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2849 jmp_rel(c, c->src.val);
018a98db 2850 break;
6aa8b732 2851 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2852 switch (c->modrm_reg) {
6aa8b732
AK		 2853 case 0:
2854 goto add;
2855 case 1:
2856 goto or;
2857 case 2:
2858 goto adc;
2859 case 3:
2860 goto sbb;
2861 case 4:
2862 goto and;
2863 case 5:
2864 goto sub;
2865 case 6:
2866 goto xor;
2867 case 7:
2868 goto cmp;
2869 }
2870 break;
2871 case 0x84 ... 0x85:
dfb507c4 2872 test:
05f086f8 2873 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2874 break;
2875 case 0x86 ... 0x87: /* xchg */
b13354f8 2876 xchg:
6aa8b732 2877 /* Write back the register source. */
e4e03ded 2878 switch (c->dst.bytes) {
6aa8b732 2879 case 1:
1a6440ae 2880 *(u8 *) c->src.addr.reg = (u8) c->dst.val;
6aa8b732
AK		 2881 break;
2882 case 2:
1a6440ae 2883 *(u16 *) c->src.addr.reg = (u16) c->dst.val;
6aa8b732
AK		 2884 break;
2885 case 4:
1a6440ae 2886 *c->src.addr.reg = (u32) c->dst.val;
6aa8b732
AK		 2887 break; /* 64b reg: zero-extend */
2888 case 8:
1a6440ae 2889 *c->src.addr.reg = c->dst.val;
6aa8b732
AK		 2890 break;
2891 }
2892 /*
2893 * Write back the memory destination with implicit LOCK
2894 * prefix.
2895 */
e4e03ded
LV		 2896 c->dst.val = c->src.val;
2897 c->lock_prefix = 1;
6aa8b732 2898 break;
6aa8b732 2899 case 0x88 ... 0x8b: /* mov */
7de75248 2900 goto mov;
79168fd1
GN		 2901 case 0x8c: /* mov r/m, sreg */
2902 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2903 emulate_ud(ctxt);
5e3ae6c5 2904 goto done;
38d5bc6d 2905 }
79168fd1 2906 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2907 break;
7e0b54b1 2908 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2909 c->dst.val = c->modrm_ea;
7e0b54b1 2910 break;
4257198a
GT		 2911 case 0x8e: { /* mov seg, r/m16 */
2912 uint16_t sel;
4257198a
GT		 2913
2914 sel = c->src.val;
8b9f4414 2915
c697518a
GN		 2916 if (c->modrm_reg == VCPU_SREG_CS ||
2917 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2918 emulate_ud(ctxt);
8b9f4414
GN		 2919 goto done;
2920 }
2921
310b5d30 2922 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2923 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2924
2e873022 2925 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2926
2927 c->dst.type = OP_NONE; /* Disable writeback. */
2928 break;
2929 }
6aa8b732 2930 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2931 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2932 if (rc != X86EMUL_CONTINUE)
6aa8b732 2933 goto done;
6aa8b732 2934 break;
3d9e77df
AK		 2935 case 0x90 ... 0x97: /* nop / xchg reg, rax */
2936 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
2937 goto done;
b13354f8 2938 goto xchg;
fd2a7608 2939 case 0x9c: /* pushf */
05f086f8 2940 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2941 emulate_push(ctxt, ops);
8cdbd2c9 2942 break;
535eabcf 2943 case 0x9d: /* popf */
2b48cc75 2944 c->dst.type = OP_REG;
1a6440ae 2945 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 2946 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2947 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2948 if (rc != X86EMUL_CONTINUE)
2949 goto done;
2950 break;
5d55f299 2951 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2952 case 0xa4 ... 0xa5: /* movs */
a682e354 2953 goto mov;
6aa8b732 2954 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2955 c->dst.type = OP_NONE; /* Disable writeback. */
1a6440ae 2956 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
a682e354 2957 goto cmp;
dfb507c4
MG		 2958 case 0xa8 ... 0xa9: /* test ax, imm */
2959 goto test;
6aa8b732 2960 case 0xaa ... 0xab: /* stos */
e4e03ded 2961 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2962 break;
2963 case 0xac ... 0xad: /* lods */
a682e354 2964 goto mov;
6aa8b732
AK		 2965 case 0xae ... 0xaf: /* scas */
2966 DPRINTF("Urk! I don't handle SCAS.\n");
2967 goto cannot_emulate;
a5e2e82b 2968 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2969 goto mov;
018a98db
AK		 2970 case 0xc0 ... 0xc1:
2971 emulate_grp2(ctxt);
2972 break;
111de5d6 2973 case 0xc3: /* ret */
cf5de4f8 2974 c->dst.type = OP_REG;
1a6440ae 2975 c->dst.addr.reg = &c->eip;
cf5de4f8 2976 c->dst.bytes = c->op_bytes;
111de5d6 2977 goto pop_instruction;
018a98db
AK		 2978 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2979 mov:
2980 c->dst.val = c->src.val;
2981 break;
a77ab5ea
AK		 2982 case 0xcb: /* ret far */
2983 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2984 if (rc != X86EMUL_CONTINUE)
2985 goto done;
2986 break;
2987 case 0xcf: /* iret */
2988 rc = emulate_iret(ctxt, ops);
2989
1b30eaa8 2990 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2991 goto done;
2992 break;
018a98db
AK		 2993 case 0xd0 ... 0xd1: /* Grp2 */
2994 c->src.val = 1;
2995 emulate_grp2(ctxt);
2996 break;
2997 case 0xd2 ... 0xd3: /* Grp2 */
2998 c->src.val = c->regs[VCPU_REGS_RCX];
2999 emulate_grp2(ctxt);
3000 break;
a6a3034c
MG		 3001 case 0xe4: /* inb */
3002 case 0xe5: /* in */
cf8f70bf 3003 goto do_io_in;
a6a3034c
MG		 3004 case 0xe6: /* outb */
3005 case 0xe7: /* out */
cf8f70bf 3006 goto do_io_out;
1a52e051 3007 case 0xe8: /* call (near) */ {
d53c4777 3008 long int rel = c->src.val;
e4e03ded 3009 c->src.val = (unsigned long) c->eip;
7a957275 3010 jmp_rel(c, rel);
79168fd1 3011 emulate_push(ctxt, ops);
8cdbd2c9 3012 break;
1a52e051
NK		 3013 }
3014 case 0xe9: /* jmp rel */
954cd36f 3015 goto jmp;
414e6277
GN		 3016 case 0xea: { /* jmp far */
3017 unsigned short sel;
ea79849d 3018 jump_far:
414e6277
GN		 3019 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3020
3021 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3022 goto done;
954cd36f 3023
414e6277
GN		 3024 c->eip = 0;
3025 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3026 break;
414e6277 3027 }
954cd36f
GT		 3028 case 0xeb:
3029 jmp: /* jmp rel short */
7a957275 3030 jmp_rel(c, c->src.val);
a01af5ec 3031 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3032 break;
a6a3034c
MG		 3033 case 0xec: /* in al,dx */
3034 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3035 c->src.val = c->regs[VCPU_REGS_RDX];
3036 do_io_in:
3037 c->dst.bytes = min(c->dst.bytes, 4u);
3038 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3039 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3040 goto done;
3041 }
7b262e90
GN		 3042 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3043 &c->dst.val))
cf8f70bf
GN		 3044 goto done; /* IO is needed */
3045 break;
ce7a0ad3
WY		 3046 case 0xee: /* out dx,al */
3047 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3048 c->src.val = c->regs[VCPU_REGS_RDX];
3049 do_io_out:
3050 c->dst.bytes = min(c->dst.bytes, 4u);
3051 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3052 emulate_gp(ctxt, 0);
f850e2e6
GN		 3053 goto done;
3054 }
cf8f70bf
GN		 3055 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3056 ctxt->vcpu);
3057 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3058 break;
111de5d6 3059 case 0xf4: /* hlt */
ad312c7c 3060 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3061 break;
111de5d6
AK		 3062 case 0xf5: /* cmc */
3063 /* complement carry flag from eflags reg */
3064 ctxt->eflags ^= EFLG_CF;
3065 c->dst.type = OP_NONE; /* Disable writeback. */
3066 break;
018a98db 3067 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3068 if (!emulate_grp3(ctxt, ops))
3069 goto cannot_emulate;
018a98db 3070 break;
111de5d6
AK		 3071 case 0xf8: /* clc */
3072 ctxt->eflags &= ~EFLG_CF;
3073 c->dst.type = OP_NONE; /* Disable writeback. */
3074 break;
3075 case 0xfa: /* cli */
07cbc6c1 3076 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3077 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3078 goto done;
3079 } else {
f850e2e6
GN		 3080 ctxt->eflags &= ~X86_EFLAGS_IF;
3081 c->dst.type = OP_NONE; /* Disable writeback. */
3082 }
111de5d6
AK		 3083 break;
3084 case 0xfb: /* sti */
07cbc6c1 3085 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3086 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3087 goto done;
3088 } else {
95cb2295 3089 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3090 ctxt->eflags |= X86_EFLAGS_IF;
3091 c->dst.type = OP_NONE; /* Disable writeback. */
3092 }
111de5d6 3093 break;
fb4616f4
MG		 3094 case 0xfc: /* cld */
3095 ctxt->eflags &= ~EFLG_DF;
3096 c->dst.type = OP_NONE; /* Disable writeback. */
3097 break;
3098 case 0xfd: /* std */
3099 ctxt->eflags |= EFLG_DF;
3100 c->dst.type = OP_NONE; /* Disable writeback. */
3101 break;
ea79849d
GN		 3102 case 0xfe: /* Grp4 */
3103 grp45:
018a98db 3104 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3105 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3106 goto done;
3107 break;
ea79849d
GN		 3108 case 0xff: /* Grp5 */
3109 if (c->modrm_reg == 5)
3110 goto jump_far;
3111 goto grp45;
91269b8f
AK		 3112 default:
3113 goto cannot_emulate;
6aa8b732 3114 }
018a98db
AK		 3115
3116writeback:
3117 rc = writeback(ctxt, ops);
1b30eaa8 3118 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3119 goto done;
3120
5cd21917
GN		 3121 /*
3122 * restore dst type in case the decoding will be reused
3123 * (happens for string instruction )
3124 */
3125 c->dst.type = saved_dst_type;
3126
a682e354 3127 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3128 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3129 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3130
3131 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3132 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3133 &c->dst);
d9271123 3134
5cd21917 3135 if (c->rep_prefix && (c->d & String)) {
7b262e90 3136 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3137 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3138 /*
3139 * Re-enter guest when pio read ahead buffer is empty or,
3140 * if it is not used, after each 1024 iteration.
3141 */
3142 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3143 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3144 ctxt->restart = false;
3145 }
9de41573
GN		 3146 /*
3147 * reset read cache here in case string instruction is restared
3148 * without decoding
3149 */
3150 ctxt->decode.mem_read.end = 0;
95c55886 3151 ctxt->eip = c->eip;
018a98db
AK		 3152
3153done:
cb404fe0 3154 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3155
3156twobyte_insn:
e4e03ded 3157 switch (c->b) {
6aa8b732 3158 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3159 switch (c->modrm_reg) {
6aa8b732
AK		 3160 u16 size;
3161 unsigned long address;
3162
aca7f966 3163 case 0: /* vmcall */
e4e03ded 3164 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3165 goto cannot_emulate;
3166
7aa81cc0 3167 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3168 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3169 goto done;
3170
33e3885d 3171 /* Let the processor re-execute the fixed hypercall */
063db061 3172 c->eip = ctxt->eip;
16286d08
AK		 3173 /* Disable writeback. */
3174 c->dst.type = OP_NONE;
aca7f966 3175 break;
6aa8b732 3176 case 2: /* lgdt */
1a6440ae 3177 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3178 &size, &address, c->op_bytes);
1b30eaa8 3179 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3180 goto done;
3181 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3182 /* Disable writeback. */
3183 c->dst.type = OP_NONE;
6aa8b732 3184 break;
aca7f966 3185 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3186 if (c->modrm_mod == 3) {
3187 switch (c->modrm_rm) {
3188 case 1:
3189 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3190 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3191 goto done;
3192 break;
3193 default:
3194 goto cannot_emulate;
3195 }
aca7f966 3196 } else {
1a6440ae 3197 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3198 &size, &address,
e4e03ded 3199 c->op_bytes);
1b30eaa8 3200 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3201 goto done;
3202 realmode_lidt(ctxt->vcpu, size, address);
3203 }
16286d08
AK		 3204 /* Disable writeback. */
3205 c->dst.type = OP_NONE;
6aa8b732
AK		 3206 break;
3207 case 4: /* smsw */
16286d08 3208 c->dst.bytes = 2;
52a46617 3209 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3210 break;
3211 case 6: /* lmsw */
9928ff60 3212 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3213 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3214 c->dst.type = OP_NONE;
6aa8b732 3215 break;
6e1e5ffe 3216 case 5: /* not defined */
54b8486f 3217 emulate_ud(ctxt);
6e1e5ffe 3218 goto done;
6aa8b732 3219 case 7: /* invlpg*/
69f55cb1 3220 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3221 /* Disable writeback. */
3222 c->dst.type = OP_NONE;
6aa8b732
AK		 3223 break;
3224 default:
3225 goto cannot_emulate;
3226 }
3227 break;
e99f0507 3228 case 0x05: /* syscall */
3fb1b5db 3229 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3230 if (rc != X86EMUL_CONTINUE)
3231 goto done;
e66bb2cc
AP		 3232 else
3233 goto writeback;
e99f0507 3234 break;
018a98db
AK		 3235 case 0x06:
3236 emulate_clts(ctxt->vcpu);
3237 c->dst.type = OP_NONE;
3238 break;
018a98db 3239 case 0x09: /* wbinvd */
f5f48ee1
SY		 3240 kvm_emulate_wbinvd(ctxt->vcpu);
3241 c->dst.type = OP_NONE;
3242 break;
3243 case 0x08: /* invd */
018a98db
AK		 3244 case 0x0d: /* GrpP (prefetch) */
3245 case 0x18: /* Grp16 (prefetch/nop) */
3246 c->dst.type = OP_NONE;
3247 break;
3248 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3249 switch (c->modrm_reg) {
3250 case 1:
3251 case 5 ... 7:
3252 case 9 ... 15:
54b8486f 3253 emulate_ud(ctxt);
6aebfa6e
GN		 3254 goto done;
3255 }
52a46617 3256 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3257 c->dst.type = OP_NONE; /* no writeback */
3258 break;
6aa8b732 3259 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3260 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3261 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3262 emulate_ud(ctxt);
1e470be5
GN		 3263 goto done;
3264 }
35aa5375 3265 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3266 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3267 break;
018a98db 3268 case 0x22: /* mov reg, cr */
0f12244f 3269 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3270 emulate_gp(ctxt, 0);
0f12244f
GN		 3271 goto done;
3272 }
018a98db
AK		 3273 c->dst.type = OP_NONE;
3274 break;
6aa8b732 3275 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3276 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3277 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3278 emulate_ud(ctxt);
1e470be5
GN		 3279 goto done;
3280 }
35aa5375 3281
338dbc97
GN		 3282 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3283 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3284 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3285 /* #UD condition is already handled by the code above */
54b8486f 3286 emulate_gp(ctxt, 0);
338dbc97
GN		 3287 goto done;
3288 }
3289
a01af5ec 3290 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3291 break;
018a98db
AK		 3292 case 0x30:
3293 /* wrmsr */
3294 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3295 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3296 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3297 emulate_gp(ctxt, 0);
fd525365 3298 goto done;
018a98db
AK		 3299 }
3300 rc = X86EMUL_CONTINUE;
3301 c->dst.type = OP_NONE;
3302 break;
3303 case 0x32:
3304 /* rdmsr */
3fb1b5db 3305 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3306 emulate_gp(ctxt, 0);
fd525365 3307 goto done;
018a98db
AK		 3308 } else {
3309 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3310 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3311 }
3312 rc = X86EMUL_CONTINUE;
3313 c->dst.type = OP_NONE;
3314 break;
e99f0507 3315 case 0x34: /* sysenter */
3fb1b5db 3316 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3317 if (rc != X86EMUL_CONTINUE)
3318 goto done;
8c604352
AP		 3319 else
3320 goto writeback;
e99f0507
AP		 3321 break;
3322 case 0x35: /* sysexit */
3fb1b5db 3323 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3324 if (rc != X86EMUL_CONTINUE)
3325 goto done;
4668f050
AP		 3326 else
3327 goto writeback;
e99f0507 3328 break;
6aa8b732 3329 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3330 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3331 if (!test_cc(c->b, ctxt->eflags))
3332 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3333 break;
b2833e3c 3334 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3335 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3336 jmp_rel(c, c->src.val);
018a98db
AK		 3337 c->dst.type = OP_NONE;
3338 break;
0934ac9d 3339 case 0xa0: /* push fs */
79168fd1 3340 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3341 break;
3342 case 0xa1: /* pop fs */
3343 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3344 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3345 goto done;
3346 break;
7de75248
NK		 3347 case 0xa3:
3348 bt: /* bt */
e4f8e039 3349 c->dst.type = OP_NONE;
e4e03ded
LV		 3350 /* only subword offset */
3351 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3352 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3353 break;
9bf8ea42
GT		 3354 case 0xa4: /* shld imm8, r, r/m */
3355 case 0xa5: /* shld cl, r, r/m */
3356 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3357 break;
0934ac9d 3358 case 0xa8: /* push gs */
79168fd1 3359 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3360 break;
3361 case 0xa9: /* pop gs */
3362 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3363 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3364 goto done;
3365 break;
7de75248
NK		 3366 case 0xab:
3367 bts: /* bts */
e4e03ded
LV		 3368 /* only subword offset */
3369 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3370 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3371 break;
9bf8ea42
GT		 3372 case 0xac: /* shrd imm8, r, r/m */
3373 case 0xad: /* shrd cl, r, r/m */
3374 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3375 break;
2a7c5b8b
GC		 3376 case 0xae: /* clflush */
3377 break;
6aa8b732
AK		 3378 case 0xb0 ... 0xb1: /* cmpxchg */
3379 /*
3380 * Save real source value, then compare EAX against
3381 * destination.
3382 */
e4e03ded
LV		 3383 c->src.orig_val = c->src.val;
3384 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3385 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3386 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3387 /* Success: write back to memory. */
e4e03ded 3388 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3389 } else {
3390 /* Failure: write the value we saw to EAX. */
e4e03ded 3391 c->dst.type = OP_REG;
1a6440ae 3392 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3393 }
3394 break;
6aa8b732
AK		 3395 case 0xb3:
3396 btr: /* btr */
e4e03ded
LV		 3397 /* only subword offset */
3398 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3399 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3400 break;
6aa8b732 3401 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3402 c->dst.bytes = c->op_bytes;
3403 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3404 : (u16) c->src.val;
6aa8b732 3405 break;
6aa8b732 3406 case 0xba: /* Grp8 */
e4e03ded 3407 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3408 case 0:
3409 goto bt;
3410 case 1:
3411 goto bts;
3412 case 2:
3413 goto btr;
3414 case 3:
3415 goto btc;
3416 }
3417 break;
7de75248
NK		 3418 case 0xbb:
3419 btc: /* btc */
e4e03ded
LV		 3420 /* only subword offset */
3421 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3422 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3423 break;
6aa8b732 3424 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3425 c->dst.bytes = c->op_bytes;
3426 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3427 (s16) c->src.val;
6aa8b732 3428 break;
a012e65a 3429 case 0xc3: /* movnti */
e4e03ded
LV		 3430 c->dst.bytes = c->op_bytes;
3431 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3432 (u64) c->src.val;
a012e65a 3433 break;
6aa8b732 3434 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3435 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3436 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3437 goto done;
3438 break;
91269b8f
AK		 3439 default:
3440 goto cannot_emulate;
6aa8b732
AK		 3441 }
3442 goto writeback;
3443
3444cannot_emulate:
e4e03ded 3445 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3446 return -1;
3447}
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