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KVM: emulate: do not initialize memopp
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
7b105ca2 517static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 518{
519 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
520 return 0;
521
7b105ca2 522 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 523}
524
35d3d4a1
AK		 525static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
526 u32 error, bool valid)
54b8486f 527{
da9cb575
AK		 528 ctxt->exception.vector = vec;
529 ctxt->exception.error_code = error;
530 ctxt->exception.error_code_valid = valid;
35d3d4a1 531 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 532}
533
3b88e41a
JR		 534static int emulate_db(struct x86_emulate_ctxt *ctxt)
535{
536 return emulate_exception(ctxt, DB_VECTOR, 0, false);
537}
538
35d3d4a1 539static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 540{
35d3d4a1 541 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 542}
543
618ff15d
AK		 544static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
545{
546 return emulate_exception(ctxt, SS_VECTOR, err, true);
547}
548
35d3d4a1 549static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 552}
553
35d3d4a1 554static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 555{
35d3d4a1 556 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 557}
558
34d1f490
AK		 559static int emulate_de(struct x86_emulate_ctxt *ctxt)
560{
35d3d4a1 561 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 562}
563
1253791d
AK		 564static int emulate_nm(struct x86_emulate_ctxt *ctxt)
565{
566 return emulate_exception(ctxt, NM_VECTOR, 0, false);
567}
568
1aa36616
AK		 569static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
570{
571 u16 selector;
572 struct desc_struct desc;
573
574 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
575 return selector;
576}
577
578static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
579 unsigned seg)
580{
581 u16 dummy;
582 u32 base3;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
586 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
587}
588
1c11b376
AK		 589/*
590 * x86 defines three classes of vector instructions: explicitly
591 * aligned, explicitly unaligned, and the rest, which change behaviour
592 * depending on whether they're AVX encoded or not.
593 *
594 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
595 * subject to the same check.
596 */
597static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
598{
599 if (likely(size < 16))
600 return false;
601
602 if (ctxt->d & Aligned)
603 return true;
604 else if (ctxt->d & Unaligned)
605 return false;
606 else if (ctxt->d & Avx)
607 return false;
608 else
609 return true;
610}
611
3d9b938e 612static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 613 struct segmented_address addr,
3d9b938e 614 unsigned size, bool write, bool fetch,
52fd8b44
AK		 615 ulong *linear)
616{
618ff15d
AK		 617 struct desc_struct desc;
618 bool usable;
52fd8b44 619 ulong la;
618ff15d 620 u32 lim;
1aa36616 621 u16 sel;
3a78a4f4 622 unsigned cpl;
52fd8b44 623
7b105ca2 624 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 625 switch (ctxt->mode) {
618ff15d
AK		 626 case X86EMUL_MODE_PROT64:
627 if (((signed long)la << 16) >> 16 != la)
628 return emulate_gp(ctxt, 0);
629 break;
630 default:
1aa36616
AK		 631 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
632 addr.seg);
618ff15d
AK		 633 if (!usable)
634 goto bad;
58b7825b
GN		 635 /* code segment in protected mode or read-only data segment */
636 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
637 || !(desc.type & 2)) && write)
618ff15d
AK		 638 goto bad;
639 /* unreadable code segment */
3d9b938e 640 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 641 goto bad;
642 lim = desc_limit_scaled(&desc);
643 if ((desc.type & 8) || !(desc.type & 4)) {
644 /* expand-up segment */
645 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
646 goto bad;
647 } else {
fc058680 648 /* expand-down segment */
618ff15d
AK		 649 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
650 goto bad;
651 lim = desc.d ? 0xffffffff : 0xffff;
652 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
653 goto bad;
654 }
717746e3 655 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 656 if (!(desc.type & 8)) {
657 /* data segment */
658 if (cpl > desc.dpl)
659 goto bad;
660 } else if ((desc.type & 8) && !(desc.type & 4)) {
661 /* nonconforming code segment */
662 if (cpl != desc.dpl)
663 goto bad;
664 } else if ((desc.type & 8) && (desc.type & 4)) {
665 /* conforming code segment */
666 if (cpl < desc.dpl)
667 goto bad;
668 }
669 break;
670 }
9dac77fa 671 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 672 la &= (u32)-1;
1c11b376
AK		 673 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
674 return emulate_gp(ctxt, 0);
52fd8b44
AK		 675 *linear = la;
676 return X86EMUL_CONTINUE;
618ff15d
AK		 677bad:
678 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 679 return emulate_ss(ctxt, sel);
618ff15d 680 else
0afbe2f8 681 return emulate_gp(ctxt, sel);
52fd8b44
AK		 682}
683
3d9b938e
NE		 684static int linearize(struct x86_emulate_ctxt *ctxt,
685 struct segmented_address addr,
686 unsigned size, bool write,
687 ulong *linear)
688{
689 return __linearize(ctxt, addr, size, write, false, linear);
690}
691
692
3ca3ac4d
AK		 693static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
694 struct segmented_address addr,
695 void *data,
696 unsigned size)
697{
9fa088f4
AK		 698 int rc;
699 ulong linear;
700
83b8795a 701 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 702 if (rc != X86EMUL_CONTINUE)
703 return rc;
0f65dd70 704 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 705}
706
807941b1
TY		 707/*
708 * Fetch the next byte of the instruction being emulated which is pointed to
709 * by ctxt->_eip, then increment ctxt->_eip.
710 *
711 * Also prefetch the remaining bytes of the instruction without crossing page
712 * boundary if they are not in fetch_cache yet.
713 */
714static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 715{
9dac77fa 716 struct fetch_cache *fc = &ctxt->fetch;
62266869 717 int rc;
2fb53ad8 718 int size, cur_size;
62266869 719
807941b1 720 if (ctxt->_eip == fc->end) {
3d9b938e 721 unsigned long linear;
807941b1
TY		 722 struct segmented_address addr = { .seg = VCPU_SREG_CS,
723 .ea = ctxt->_eip };
2fb53ad8 724 cur_size = fc->end - fc->start;
807941b1
TY		 725 size = min(15UL - cur_size,
726 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 727 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 728 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 729 return rc;
ef5d75cc
TY		 730 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
731 size, &ctxt->exception);
7d88bb48 732 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 733 return rc;
2fb53ad8 734 fc->end += size;
62266869 735 }
807941b1
TY		 736 *dest = fc->data[ctxt->_eip - fc->start];
737 ctxt->_eip++;
3e2815e9 738 return X86EMUL_CONTINUE;
62266869
AK		 739}
740
741static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 742 void *dest, unsigned size)
62266869 743{
3e2815e9 744 int rc;
62266869 745
eb3c79e6 746 /* x86 instructions are limited to 15 bytes. */
7d88bb48 747 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 748 return X86EMUL_UNHANDLEABLE;
62266869 749 while (size--) {
807941b1 750 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 751 if (rc != X86EMUL_CONTINUE)
62266869
AK		 752 return rc;
753 }
3e2815e9 754 return X86EMUL_CONTINUE;
62266869
AK		 755}
756
67cbc90d 757/* Fetch next part of the instruction being emulated. */
e85a1085 758#define insn_fetch(_type, _ctxt) \
67cbc90d 759({ unsigned long _x; \
e85a1085 760 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 761 if (rc != X86EMUL_CONTINUE) \
762 goto done; \
67cbc90d
TY		 763 (_type)_x; \
764})
765
807941b1
TY		 766#define insn_fetch_arr(_arr, _size, _ctxt) \
767({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 768 if (rc != X86EMUL_CONTINUE) \
769 goto done; \
67cbc90d
TY		 770})
771
1e3c5cb0
RR		 772/*
773 * Given the 'reg' portion of a ModRM byte, and a register block, return a
774 * pointer into the block that addresses the relevant register.
775 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
776 */
dd856efa 777static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 778 int byteop)
6aa8b732
AK		 779{
780 void *p;
aa9ac1a6 781 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 782
6aa8b732 783 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 784 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
785 else
786 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 787 return p;
788}
789
790static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 791 struct segmented_address addr,
6aa8b732
AK		 792 u16 *size, unsigned long *address, int op_bytes)
793{
794 int rc;
795
796 if (op_bytes == 2)
797 op_bytes = 3;
798 *address = 0;
3ca3ac4d 799 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 800 if (rc != X86EMUL_CONTINUE)
6aa8b732 801 return rc;
30b31ab6 802 addr.ea += 2;
3ca3ac4d 803 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 804 return rc;
805}
806
34b77652
AK		 807FASTOP2(add);
808FASTOP2(or);
809FASTOP2(adc);
810FASTOP2(sbb);
811FASTOP2(and);
812FASTOP2(sub);
813FASTOP2(xor);
814FASTOP2(cmp);
815FASTOP2(test);
816
b9fa409b
AK		 817FASTOP1SRC2(mul, mul_ex);
818FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 819FASTOP1SRC2EX(div, div_ex);
820FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 821
34b77652
AK		 822FASTOP3WCL(shld);
823FASTOP3WCL(shrd);
824
825FASTOP2W(imul);
826
827FASTOP1(not);
828FASTOP1(neg);
829FASTOP1(inc);
830FASTOP1(dec);
831
832FASTOP2CL(rol);
833FASTOP2CL(ror);
834FASTOP2CL(rcl);
835FASTOP2CL(rcr);
836FASTOP2CL(shl);
837FASTOP2CL(shr);
838FASTOP2CL(sar);
839
840FASTOP2W(bsf);
841FASTOP2W(bsr);
842FASTOP2W(bt);
843FASTOP2W(bts);
844FASTOP2W(btr);
845FASTOP2W(btc);
846
e47a5f5f
AK		 847FASTOP2(xadd);
848
9ae9feba 849static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 850{
9ae9feba
AK		 851 u8 rc;
852 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 853
9ae9feba 854 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 855 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 856 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
857 return rc;
bbe9abbd
NK		 858}
859
91ff3cb4
AK		 860static void fetch_register_operand(struct operand *op)
861{
862 switch (op->bytes) {
863 case 1:
864 op->val = *(u8 *)op->addr.reg;
865 break;
866 case 2:
867 op->val = *(u16 *)op->addr.reg;
868 break;
869 case 4:
870 op->val = *(u32 *)op->addr.reg;
871 break;
872 case 8:
873 op->val = *(u64 *)op->addr.reg;
874 break;
875 }
876}
877
1253791d
AK		 878static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
879{
880 ctxt->ops->get_fpu(ctxt);
881 switch (reg) {
89a87c67
MK		 882 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
883 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
884 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
885 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
886 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
887 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
888 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
889 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 890#ifdef CONFIG_X86_64
89a87c67
MK		 891 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
892 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
893 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
894 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
895 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
896 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
897 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
898 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 899#endif
900 default: BUG();
901 }
902 ctxt->ops->put_fpu(ctxt);
903}
904
905static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
906 int reg)
907{
908 ctxt->ops->get_fpu(ctxt);
909 switch (reg) {
89a87c67
MK		 910 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
911 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
912 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
913 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
914 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
915 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
916 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
917 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 918#ifdef CONFIG_X86_64
89a87c67
MK		 919 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
920 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
921 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
922 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
923 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
924 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
925 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
926 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 927#endif
928 default: BUG();
929 }
930 ctxt->ops->put_fpu(ctxt);
931}
932
cbe2c9d3
AK		 933static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
934{
935 ctxt->ops->get_fpu(ctxt);
936 switch (reg) {
937 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
938 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
939 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
940 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
941 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
942 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
943 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
944 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
945 default: BUG();
946 }
947 ctxt->ops->put_fpu(ctxt);
948}
949
950static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
951{
952 ctxt->ops->get_fpu(ctxt);
953 switch (reg) {
954 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
955 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
956 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
957 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
958 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
959 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
960 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
961 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
962 default: BUG();
963 }
964 ctxt->ops->put_fpu(ctxt);
965}
966
045a282c
GN		 967static int em_fninit(struct x86_emulate_ctxt *ctxt)
968{
969 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
970 return emulate_nm(ctxt);
971
972 ctxt->ops->get_fpu(ctxt);
973 asm volatile("fninit");
974 ctxt->ops->put_fpu(ctxt);
975 return X86EMUL_CONTINUE;
976}
977
978static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
979{
980 u16 fcw;
981
982 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
983 return emulate_nm(ctxt);
984
985 ctxt->ops->get_fpu(ctxt);
986 asm volatile("fnstcw %0": "+m"(fcw));
987 ctxt->ops->put_fpu(ctxt);
988
989 /* force 2 byte destination */
990 ctxt->dst.bytes = 2;
991 ctxt->dst.val = fcw;
992
993 return X86EMUL_CONTINUE;
994}
995
996static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
997{
998 u16 fsw;
999
1000 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1001 return emulate_nm(ctxt);
1002
1003 ctxt->ops->get_fpu(ctxt);
1004 asm volatile("fnstsw %0": "+m"(fsw));
1005 ctxt->ops->put_fpu(ctxt);
1006
1007 /* force 2 byte destination */
1008 ctxt->dst.bytes = 2;
1009 ctxt->dst.val = fsw;
1010
1011 return X86EMUL_CONTINUE;
1012}
1013
1253791d 1014static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1015 struct operand *op)
3c118e24 1016{
9dac77fa 1017 unsigned reg = ctxt->modrm_reg;
33615aa9 1018
9dac77fa
AK		 1019 if (!(ctxt->d & ModRM))
1020 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1021
9dac77fa 1022 if (ctxt->d & Sse) {
1253791d
AK		 1023 op->type = OP_XMM;
1024 op->bytes = 16;
1025 op->addr.xmm = reg;
1026 read_sse_reg(ctxt, &op->vec_val, reg);
1027 return;
1028 }
cbe2c9d3
AK		 1029 if (ctxt->d & Mmx) {
1030 reg &= 7;
1031 op->type = OP_MM;
1032 op->bytes = 8;
1033 op->addr.mm = reg;
1034 return;
1035 }
1253791d 1036
3c118e24 1037 op->type = OP_REG;
6d4d85ec
GN		 1038 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1039 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1040
91ff3cb4 1041 fetch_register_operand(op);
3c118e24
AK		 1042 op->orig_val = op->val;
1043}
1044
a6e3407b
AK		 1045static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1046{
1047 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1048 ctxt->modrm_seg = VCPU_SREG_SS;
1049}
1050
1c73ef66 1051static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1052 struct operand *op)
1c73ef66 1053{
1c73ef66 1054 u8 sib;
02357bdc 1055 int index_reg, base_reg, scale;
3e2815e9 1056 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1057 ulong modrm_ea = 0;
1c73ef66 1058
02357bdc
BD		 1059 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1060 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1061 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1062
02357bdc 1063 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1064 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1065 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1066 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1067
9b88ae99 1068 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1069 op->type = OP_REG;
9dac77fa 1070 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1071 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1072 ctxt->d & ByteOp);
9dac77fa 1073 if (ctxt->d & Sse) {
1253791d
AK		 1074 op->type = OP_XMM;
1075 op->bytes = 16;
9dac77fa
AK		 1076 op->addr.xmm = ctxt->modrm_rm;
1077 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1078 return rc;
1079 }
cbe2c9d3
AK		 1080 if (ctxt->d & Mmx) {
1081 op->type = OP_MM;
1082 op->bytes = 8;
bdc90722 1083 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1084 return rc;
1085 }
2dbd0dd7 1086 fetch_register_operand(op);
1c73ef66
AK		 1087 return rc;
1088 }
1089
2dbd0dd7
AK		 1090 op->type = OP_MEM;
1091
9dac77fa 1092 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1093 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1094 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1095 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1096 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1097
1098 /* 16-bit ModR/M decode. */
9dac77fa 1099 switch (ctxt->modrm_mod) {
1c73ef66 1100 case 0:
9dac77fa 1101 if (ctxt->modrm_rm == 6)
e85a1085 1102 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1103 break;
1104 case 1:
e85a1085 1105 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1106 break;
1107 case 2:
e85a1085 1108 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1109 break;
1110 }
9dac77fa 1111 switch (ctxt->modrm_rm) {
1c73ef66 1112 case 0:
2dbd0dd7 1113 modrm_ea += bx + si;
1c73ef66
AK		 1114 break;
1115 case 1:
2dbd0dd7 1116 modrm_ea += bx + di;
1c73ef66
AK		 1117 break;
1118 case 2:
2dbd0dd7 1119 modrm_ea += bp + si;
1c73ef66
AK		 1120 break;
1121 case 3:
2dbd0dd7 1122 modrm_ea += bp + di;
1c73ef66
AK		 1123 break;
1124 case 4:
2dbd0dd7 1125 modrm_ea += si;
1c73ef66
AK		 1126 break;
1127 case 5:
2dbd0dd7 1128 modrm_ea += di;
1c73ef66
AK		 1129 break;
1130 case 6:
9dac77fa 1131 if (ctxt->modrm_mod != 0)
2dbd0dd7 1132 modrm_ea += bp;
1c73ef66
AK		 1133 break;
1134 case 7:
2dbd0dd7 1135 modrm_ea += bx;
1c73ef66
AK		 1136 break;
1137 }
9dac77fa
AK		 1138 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1139 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1140 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1141 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1142 } else {
1143 /* 32/64-bit ModR/M decode. */
9dac77fa 1144 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1145 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1146 index_reg |= (sib >> 3) & 7;
1147 base_reg |= sib & 7;
1148 scale = sib >> 6;
1149
9dac77fa 1150 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1151 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1152 else {
dd856efa 1153 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1154 adjust_modrm_seg(ctxt, base_reg);
1155 }
dc71d0f1 1156 if (index_reg != 4)
dd856efa 1157 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1158 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1159 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1160 ctxt->rip_relative = 1;
a6e3407b
AK		 1161 } else {
1162 base_reg = ctxt->modrm_rm;
dd856efa 1163 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1164 adjust_modrm_seg(ctxt, base_reg);
1165 }
9dac77fa 1166 switch (ctxt->modrm_mod) {
1c73ef66 1167 case 0:
9dac77fa 1168 if (ctxt->modrm_rm == 5)
e85a1085 1169 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1170 break;
1171 case 1:
e85a1085 1172 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1173 break;
1174 case 2:
e85a1085 1175 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1176 break;
1177 }
1178 }
90de84f5 1179 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1180 if (ctxt->ad_bytes != 8)
1181 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1182
1c73ef66
AK		 1183done:
1184 return rc;
1185}
1186
1187static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1188 struct operand *op)
1c73ef66 1189{
3e2815e9 1190 int rc = X86EMUL_CONTINUE;
1c73ef66 1191
2dbd0dd7 1192 op->type = OP_MEM;
9dac77fa 1193 switch (ctxt->ad_bytes) {
1c73ef66 1194 case 2:
e85a1085 1195 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1196 break;
1197 case 4:
e85a1085 1198 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1199 break;
1200 case 8:
e85a1085 1201 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1202 break;
1203 }
1204done:
1205 return rc;
1206}
1207
9dac77fa 1208static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1209{
7129eeca 1210 long sv = 0, mask;
35c843c4 1211
9dac77fa 1212 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1213 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1214
9dac77fa
AK		 1215 if (ctxt->src.bytes == 2)
1216 sv = (s16)ctxt->src.val & (s16)mask;
1217 else if (ctxt->src.bytes == 4)
1218 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1219 else
1220 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1221
9dac77fa 1222 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1223 }
ba7ff2b7
WY		 1224
1225 /* only subword offset */
9dac77fa 1226 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1227}
1228
dde7e6d1 1229static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1230 unsigned long addr, void *dest, unsigned size)
6aa8b732 1231{
dde7e6d1 1232 int rc;
9dac77fa 1233 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1234
f23b070e
XG		 1235 if (mc->pos < mc->end)
1236 goto read_cached;
6aa8b732 1237
f23b070e
XG		 1238 WARN_ON((mc->end + size) >= sizeof(mc->data));
1239
1240 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1241 &ctxt->exception);
1242 if (rc != X86EMUL_CONTINUE)
1243 return rc;
1244
1245 mc->end += size;
1246
1247read_cached:
1248 memcpy(dest, mc->data + mc->pos, size);
1249 mc->pos += size;
dde7e6d1
AK		 1250 return X86EMUL_CONTINUE;
1251}
6aa8b732 1252
3ca3ac4d
AK		 1253static int segmented_read(struct x86_emulate_ctxt *ctxt,
1254 struct segmented_address addr,
1255 void *data,
1256 unsigned size)
1257{
9fa088f4
AK		 1258 int rc;
1259 ulong linear;
1260
83b8795a 1261 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1262 if (rc != X86EMUL_CONTINUE)
1263 return rc;
7b105ca2 1264 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1265}
1266
1267static int segmented_write(struct x86_emulate_ctxt *ctxt,
1268 struct segmented_address addr,
1269 const void *data,
1270 unsigned size)
1271{
9fa088f4
AK		 1272 int rc;
1273 ulong linear;
1274
83b8795a 1275 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1276 if (rc != X86EMUL_CONTINUE)
1277 return rc;
0f65dd70
AK		 1278 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1279 &ctxt->exception);
3ca3ac4d
AK		 1280}
1281
1282static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1283 struct segmented_address addr,
1284 const void *orig_data, const void *data,
1285 unsigned size)
1286{
9fa088f4
AK		 1287 int rc;
1288 ulong linear;
1289
83b8795a 1290 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1291 if (rc != X86EMUL_CONTINUE)
1292 return rc;
0f65dd70
AK		 1293 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1294 size, &ctxt->exception);
3ca3ac4d
AK		 1295}
1296
dde7e6d1 1297static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1298 unsigned int size, unsigned short port,
1299 void *dest)
1300{
9dac77fa 1301 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1302
dde7e6d1 1303 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1304 unsigned int in_page, n;
9dac77fa 1305 unsigned int count = ctxt->rep_prefix ?
dd856efa 1306 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1307 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1308 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1309 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1310 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1311 count);
1312 if (n == 0)
1313 n = 1;
1314 rc->pos = rc->end = 0;
7b105ca2 1315 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1316 return 0;
1317 rc->end = n * size;
6aa8b732
AK		 1318 }
1319
e6e39f04
NA		 1320 if (ctxt->rep_prefix && (ctxt->d & String) &&
1321 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1322 ctxt->dst.data = rc->data + rc->pos;
1323 ctxt->dst.type = OP_MEM_STR;
1324 ctxt->dst.count = (rc->end - rc->pos) / size;
1325 rc->pos = rc->end;
1326 } else {
1327 memcpy(dest, rc->data + rc->pos, size);
1328 rc->pos += size;
1329 }
dde7e6d1
AK		 1330 return 1;
1331}
6aa8b732 1332
7f3d35fd
KW		 1333static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1334 u16 index, struct desc_struct *desc)
1335{
1336 struct desc_ptr dt;
1337 ulong addr;
1338
1339 ctxt->ops->get_idt(ctxt, &dt);
1340
1341 if (dt.size < index * 8 + 7)
1342 return emulate_gp(ctxt, index << 3 | 0x2);
1343
1344 addr = dt.address + index * 8;
1345 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1346 &ctxt->exception);
1347}
1348
dde7e6d1 1349static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1350 u16 selector, struct desc_ptr *dt)
1351{
0225fb50 1352 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1353 u32 base3 = 0;
7b105ca2 1354
dde7e6d1
AK		 1355 if (selector & 1 << 2) {
1356 struct desc_struct desc;
1aa36616
AK		 1357 u16 sel;
1358
dde7e6d1 1359 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1360 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1361 VCPU_SREG_LDTR))
dde7e6d1 1362 return;
e09d082c 1363
dde7e6d1 1364 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1365 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1366 } else
4bff1e86 1367 ops->get_gdt(ctxt, dt);
dde7e6d1 1368}
120df890 1369
dde7e6d1
AK		 1370/* allowed just for 8 bytes segments */
1371static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1372 u16 selector, struct desc_struct *desc,
1373 ulong *desc_addr_p)
dde7e6d1
AK		 1374{
1375 struct desc_ptr dt;
1376 u16 index = selector >> 3;
dde7e6d1 1377 ulong addr;
120df890 1378
7b105ca2 1379 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1380
35d3d4a1
AK		 1381 if (dt.size < index * 8 + 7)
1382 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1383
e919464b 1384 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1385 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1386 &ctxt->exception);
dde7e6d1 1387}
ef65c889 1388
dde7e6d1
AK		 1389/* allowed just for 8 bytes segments */
1390static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1391 u16 selector, struct desc_struct *desc)
1392{
1393 struct desc_ptr dt;
1394 u16 index = selector >> 3;
dde7e6d1 1395 ulong addr;
6aa8b732 1396
7b105ca2 1397 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1398
35d3d4a1
AK		 1399 if (dt.size < index * 8 + 7)
1400 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1401
dde7e6d1 1402 addr = dt.address + index * 8;
7b105ca2
TY		 1403 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1404 &ctxt->exception);
dde7e6d1 1405}
c7e75a3d 1406
5601d05b 1407/* Does not support long mode */
2356aaeb 1408static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1409 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1410{
869be99c 1411 struct desc_struct seg_desc, old_desc;
2356aaeb 1412 u8 dpl, rpl;
dde7e6d1
AK		 1413 unsigned err_vec = GP_VECTOR;
1414 u32 err_code = 0;
1415 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1416 ulong desc_addr;
dde7e6d1 1417 int ret;
03ebebeb 1418 u16 dummy;
e37a75a1 1419 u32 base3 = 0;
69f55cb1 1420
dde7e6d1 1421 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1422
f8da94e9
KW		 1423 if (ctxt->mode == X86EMUL_MODE_REAL) {
1424 /* set real mode segment descriptor (keep limit etc. for
1425 * unreal mode) */
03ebebeb 1426 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1427 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1428 goto load;
f8da94e9
KW		 1429 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1430 /* VM86 needs a clean new segment descriptor */
1431 set_desc_base(&seg_desc, selector << 4);
1432 set_desc_limit(&seg_desc, 0xffff);
1433 seg_desc.type = 3;
1434 seg_desc.p = 1;
1435 seg_desc.s = 1;
1436 seg_desc.dpl = 3;
1437 goto load;
dde7e6d1
AK		 1438 }
1439
79d5b4c3 1440 rpl = selector & 3;
79d5b4c3
AK		 1441
1442 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1443 if ((seg == VCPU_SREG_CS
1444 || (seg == VCPU_SREG_SS
1445 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1446 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1447 && null_selector)
1448 goto exception;
1449
1450 /* TR should be in GDT only */
1451 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1452 goto exception;
1453
1454 if (null_selector) /* for NULL selector skip all following checks */
1455 goto load;
1456
e919464b 1457 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1458 if (ret != X86EMUL_CONTINUE)
1459 return ret;
1460
1461 err_code = selector & 0xfffc;
1462 err_vec = GP_VECTOR;
1463
fc058680 1464 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1465 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1466 goto exception;
1467
1468 if (!seg_desc.p) {
1469 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1470 goto exception;
1471 }
1472
dde7e6d1 1473 dpl = seg_desc.dpl;
dde7e6d1
AK		 1474
1475 switch (seg) {
1476 case VCPU_SREG_SS:
1477 /*
1478 * segment is not a writable data segment or segment
1479 * selector's RPL != CPL or segment selector's RPL != CPL
1480 */
1481 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1482 goto exception;
6aa8b732 1483 break;
dde7e6d1 1484 case VCPU_SREG_CS:
5045b468
PB		 1485 if (in_task_switch && rpl != dpl)
1486 goto exception;
1487
dde7e6d1
AK		 1488 if (!(seg_desc.type & 8))
1489 goto exception;
1490
1491 if (seg_desc.type & 4) {
1492 /* conforming */
1493 if (dpl > cpl)
1494 goto exception;
1495 } else {
1496 /* nonconforming */
1497 if (rpl > cpl || dpl != cpl)
1498 goto exception;
1499 }
1500 /* CS(RPL) <- CPL */
1501 selector = (selector & 0xfffc) | cpl;
6aa8b732 1502 break;
dde7e6d1
AK		 1503 case VCPU_SREG_TR:
1504 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1505 goto exception;
869be99c
AK		 1506 old_desc = seg_desc;
1507 seg_desc.type |= 2; /* busy */
1508 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1509 sizeof(seg_desc), &ctxt->exception);
1510 if (ret != X86EMUL_CONTINUE)
1511 return ret;
dde7e6d1
AK		 1512 break;
1513 case VCPU_SREG_LDTR:
1514 if (seg_desc.s || seg_desc.type != 2)
1515 goto exception;
1516 break;
1517 default: /* DS, ES, FS, or GS */
4e62417b 1518 /*
dde7e6d1
AK		 1519 * segment is not a data or readable code segment or
1520 * ((segment is a data or nonconforming code segment)
1521 * and (both RPL and CPL > DPL))
4e62417b 1522 */
dde7e6d1
AK		 1523 if ((seg_desc.type & 0xa) == 0x8 ||
1524 (((seg_desc.type & 0xc) != 0xc) &&
1525 (rpl > dpl && cpl > dpl)))
1526 goto exception;
6aa8b732 1527 break;
dde7e6d1
AK		 1528 }
1529
1530 if (seg_desc.s) {
1531 /* mark segment as accessed */
1532 seg_desc.type |= 1;
7b105ca2 1533 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1534 if (ret != X86EMUL_CONTINUE)
1535 return ret;
e37a75a1
NA		 1536 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1537 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1538 sizeof(base3), &ctxt->exception);
1539 if (ret != X86EMUL_CONTINUE)
1540 return ret;
dde7e6d1
AK		 1541 }
1542load:
e37a75a1 1543 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1544 return X86EMUL_CONTINUE;
1545exception:
1546 emulate_exception(ctxt, err_vec, err_code, true);
1547 return X86EMUL_PROPAGATE_FAULT;
1548}
1549
2356aaeb
PB		 1550static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1551 u16 selector, int seg)
1552{
1553 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1554 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1555}
1556
31be40b3
WY		 1557static void write_register_operand(struct operand *op)
1558{
1559 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1560 switch (op->bytes) {
1561 case 1:
1562 *(u8 *)op->addr.reg = (u8)op->val;
1563 break;
1564 case 2:
1565 *(u16 *)op->addr.reg = (u16)op->val;
1566 break;
1567 case 4:
1568 *op->addr.reg = (u32)op->val;
1569 break; /* 64b: zero-extend */
1570 case 8:
1571 *op->addr.reg = op->val;
1572 break;
1573 }
1574}
1575
fb32b1ed 1576static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1577{
fb32b1ed 1578 switch (op->type) {
dde7e6d1 1579 case OP_REG:
fb32b1ed 1580 write_register_operand(op);
6aa8b732 1581 break;
dde7e6d1 1582 case OP_MEM:
9dac77fa 1583 if (ctxt->lock_prefix)
f5f87dfb
PB		 1584 return segmented_cmpxchg(ctxt,
1585 op->addr.mem,
1586 &op->orig_val,
1587 &op->val,
1588 op->bytes);
1589 else
1590 return segmented_write(ctxt,
fb32b1ed 1591 op->addr.mem,
fb32b1ed
AK		 1592 &op->val,
1593 op->bytes);
a682e354 1594 break;
b3356bf0 1595 case OP_MEM_STR:
f5f87dfb
PB		 1596 return segmented_write(ctxt,
1597 op->addr.mem,
1598 op->data,
1599 op->bytes * op->count);
b3356bf0 1600 break;
1253791d 1601 case OP_XMM:
fb32b1ed 1602 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1603 break;
cbe2c9d3 1604 case OP_MM:
fb32b1ed 1605 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1606 break;
dde7e6d1
AK		 1607 case OP_NONE:
1608 /* no writeback */
414e6277 1609 break;
dde7e6d1 1610 default:
414e6277 1611 break;
6aa8b732 1612 }
dde7e6d1
AK		 1613 return X86EMUL_CONTINUE;
1614}
6aa8b732 1615
51ddff50 1616static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1617{
4179bb02 1618 struct segmented_address addr;
0dc8d10f 1619
5ad105e5 1620 rsp_increment(ctxt, -bytes);
dd856efa 1621 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1622 addr.seg = VCPU_SREG_SS;
1623
51ddff50
AK		 1624 return segmented_write(ctxt, addr, data, bytes);
1625}
1626
1627static int em_push(struct x86_emulate_ctxt *ctxt)
1628{
4179bb02 1629 /* Disable writeback. */
9dac77fa 1630 ctxt->dst.type = OP_NONE;
51ddff50 1631 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1632}
69f55cb1 1633
dde7e6d1 1634static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1635 void *dest, int len)
1636{
dde7e6d1 1637 int rc;
90de84f5 1638 struct segmented_address addr;
8b4caf66 1639
dd856efa 1640 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1641 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1642 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1643 if (rc != X86EMUL_CONTINUE)
1644 return rc;
1645
5ad105e5 1646 rsp_increment(ctxt, len);
dde7e6d1 1647 return rc;
8b4caf66
LV		 1648}
1649
c54fe504
TY		 1650static int em_pop(struct x86_emulate_ctxt *ctxt)
1651{
9dac77fa 1652 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1653}
1654
dde7e6d1 1655static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1656 void *dest, int len)
9de41573
GN		 1657{
1658 int rc;
dde7e6d1
AK		 1659 unsigned long val, change_mask;
1660 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1661 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1662
3b9be3bf 1663 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1664 if (rc != X86EMUL_CONTINUE)
1665 return rc;
9de41573 1666
dde7e6d1
AK		 1667 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1668 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1669
dde7e6d1
AK		 1670 switch(ctxt->mode) {
1671 case X86EMUL_MODE_PROT64:
1672 case X86EMUL_MODE_PROT32:
1673 case X86EMUL_MODE_PROT16:
1674 if (cpl == 0)
1675 change_mask |= EFLG_IOPL;
1676 if (cpl <= iopl)
1677 change_mask |= EFLG_IF;
1678 break;
1679 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1680 if (iopl < 3)
1681 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1682 change_mask |= EFLG_IF;
1683 break;
1684 default: /* real mode */
1685 change_mask |= (EFLG_IOPL | EFLG_IF);
1686 break;
9de41573 1687 }
dde7e6d1
AK		 1688
1689 *(unsigned long *)dest =
1690 (ctxt->eflags & ~change_mask) | (val & change_mask);
1691
1692 return rc;
9de41573
GN		 1693}
1694
62aaa2f0
TY		 1695static int em_popf(struct x86_emulate_ctxt *ctxt)
1696{
9dac77fa
AK		 1697 ctxt->dst.type = OP_REG;
1698 ctxt->dst.addr.reg = &ctxt->eflags;
1699 ctxt->dst.bytes = ctxt->op_bytes;
1700 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1701}
1702
612e89f0
AK		 1703static int em_enter(struct x86_emulate_ctxt *ctxt)
1704{
1705 int rc;
1706 unsigned frame_size = ctxt->src.val;
1707 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1708 ulong rbp;
612e89f0
AK		 1709
1710 if (nesting_level)
1711 return X86EMUL_UNHANDLEABLE;
1712
dd856efa
AK		 1713 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1714 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1715 if (rc != X86EMUL_CONTINUE)
1716 return rc;
dd856efa 1717 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1718 stack_mask(ctxt));
dd856efa
AK		 1719 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1720 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1721 stack_mask(ctxt));
1722 return X86EMUL_CONTINUE;
1723}
1724
f47cfa31
AK		 1725static int em_leave(struct x86_emulate_ctxt *ctxt)
1726{
dd856efa 1727 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1728 stack_mask(ctxt));
dd856efa 1729 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1730}
1731
1cd196ea 1732static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1733{
1cd196ea
AK		 1734 int seg = ctxt->src2.val;
1735
9dac77fa 1736 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1737
4487b3b4 1738 return em_push(ctxt);
7b262e90
GN		 1739}
1740
1cd196ea 1741static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1742{
1cd196ea 1743 int seg = ctxt->src2.val;
dde7e6d1
AK		 1744 unsigned long selector;
1745 int rc;
38ba30ba 1746
9dac77fa 1747 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1748 if (rc != X86EMUL_CONTINUE)
1749 return rc;
1750
a5457e7b
PB		 1751 if (ctxt->modrm_reg == VCPU_SREG_SS)
1752 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1753
7b105ca2 1754 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1755 return rc;
38ba30ba
GN		 1756}
1757
b96a7fad 1758static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1759{
dd856efa 1760 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1761 int rc = X86EMUL_CONTINUE;
1762 int reg = VCPU_REGS_RAX;
38ba30ba 1763
dde7e6d1
AK		 1764 while (reg <= VCPU_REGS_RDI) {
1765 (reg == VCPU_REGS_RSP) ?
dd856efa 1766 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1767
4487b3b4 1768 rc = em_push(ctxt);
dde7e6d1
AK		 1769 if (rc != X86EMUL_CONTINUE)
1770 return rc;
38ba30ba 1771
dde7e6d1 1772 ++reg;
38ba30ba 1773 }
38ba30ba 1774
dde7e6d1 1775 return rc;
38ba30ba
GN		 1776}
1777
62aaa2f0
TY		 1778static int em_pushf(struct x86_emulate_ctxt *ctxt)
1779{
9dac77fa 1780 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1781 return em_push(ctxt);
1782}
1783
b96a7fad 1784static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1785{
dde7e6d1
AK		 1786 int rc = X86EMUL_CONTINUE;
1787 int reg = VCPU_REGS_RDI;
38ba30ba 1788
dde7e6d1
AK		 1789 while (reg >= VCPU_REGS_RAX) {
1790 if (reg == VCPU_REGS_RSP) {
5ad105e5 1791 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1792 --reg;
1793 }
38ba30ba 1794
dd856efa 1795 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1796 if (rc != X86EMUL_CONTINUE)
1797 break;
1798 --reg;
38ba30ba 1799 }
dde7e6d1 1800 return rc;
38ba30ba
GN		 1801}
1802
dd856efa 1803static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1804{
0225fb50 1805 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1806 int rc;
6e154e56
MG		 1807 struct desc_ptr dt;
1808 gva_t cs_addr;
1809 gva_t eip_addr;
1810 u16 cs, eip;
6e154e56
MG		 1811
1812 /* TODO: Add limit checks */
9dac77fa 1813 ctxt->src.val = ctxt->eflags;
4487b3b4 1814 rc = em_push(ctxt);
5c56e1cf
AK		 1815 if (rc != X86EMUL_CONTINUE)
1816 return rc;
6e154e56
MG		 1817
1818 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1819
9dac77fa 1820 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1821 rc = em_push(ctxt);
5c56e1cf
AK		 1822 if (rc != X86EMUL_CONTINUE)
1823 return rc;
6e154e56 1824
9dac77fa 1825 ctxt->src.val = ctxt->_eip;
4487b3b4 1826 rc = em_push(ctxt);
5c56e1cf
AK		 1827 if (rc != X86EMUL_CONTINUE)
1828 return rc;
1829
4bff1e86 1830 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1831
1832 eip_addr = dt.address + (irq << 2);
1833 cs_addr = dt.address + (irq << 2) + 2;
1834
0f65dd70 1835 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1836 if (rc != X86EMUL_CONTINUE)
1837 return rc;
1838
0f65dd70 1839 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1840 if (rc != X86EMUL_CONTINUE)
1841 return rc;
1842
7b105ca2 1843 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1844 if (rc != X86EMUL_CONTINUE)
1845 return rc;
1846
9dac77fa 1847 ctxt->_eip = eip;
6e154e56
MG		 1848
1849 return rc;
1850}
1851
dd856efa
AK		 1852int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1853{
1854 int rc;
1855
1856 invalidate_registers(ctxt);
1857 rc = __emulate_int_real(ctxt, irq);
1858 if (rc == X86EMUL_CONTINUE)
1859 writeback_registers(ctxt);
1860 return rc;
1861}
1862
7b105ca2 1863static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1864{
1865 switch(ctxt->mode) {
1866 case X86EMUL_MODE_REAL:
dd856efa 1867 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1868 case X86EMUL_MODE_VM86:
1869 case X86EMUL_MODE_PROT16:
1870 case X86EMUL_MODE_PROT32:
1871 case X86EMUL_MODE_PROT64:
1872 default:
1873 /* Protected mode interrupts unimplemented yet */
1874 return X86EMUL_UNHANDLEABLE;
1875 }
1876}
1877
7b105ca2 1878static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1879{
dde7e6d1
AK		 1880 int rc = X86EMUL_CONTINUE;
1881 unsigned long temp_eip = 0;
1882 unsigned long temp_eflags = 0;
1883 unsigned long cs = 0;
1884 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1885 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1886 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1887 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1888
dde7e6d1 1889 /* TODO: Add stack limit check */
38ba30ba 1890
9dac77fa 1891 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1892
dde7e6d1
AK		 1893 if (rc != X86EMUL_CONTINUE)
1894 return rc;
38ba30ba 1895
35d3d4a1
AK		 1896 if (temp_eip & ~0xffff)
1897 return emulate_gp(ctxt, 0);
38ba30ba 1898
9dac77fa 1899 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1900
dde7e6d1
AK		 1901 if (rc != X86EMUL_CONTINUE)
1902 return rc;
38ba30ba 1903
9dac77fa 1904 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1905
dde7e6d1
AK		 1906 if (rc != X86EMUL_CONTINUE)
1907 return rc;
38ba30ba 1908
7b105ca2 1909 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1910
dde7e6d1
AK		 1911 if (rc != X86EMUL_CONTINUE)
1912 return rc;
38ba30ba 1913
9dac77fa 1914 ctxt->_eip = temp_eip;
38ba30ba 1915
38ba30ba 1916
9dac77fa 1917 if (ctxt->op_bytes == 4)
dde7e6d1 1918 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1919 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1920 ctxt->eflags &= ~0xffff;
1921 ctxt->eflags |= temp_eflags;
38ba30ba 1922 }
dde7e6d1
AK		 1923
1924 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1925 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1926
1927 return rc;
38ba30ba
GN		 1928}
1929
e01991e7 1930static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1931{
dde7e6d1
AK		 1932 switch(ctxt->mode) {
1933 case X86EMUL_MODE_REAL:
7b105ca2 1934 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1935 case X86EMUL_MODE_VM86:
1936 case X86EMUL_MODE_PROT16:
1937 case X86EMUL_MODE_PROT32:
1938 case X86EMUL_MODE_PROT64:
c37eda13 1939 default:
dde7e6d1
AK		 1940 /* iret from protected mode unimplemented yet */
1941 return X86EMUL_UNHANDLEABLE;
c37eda13 1942 }
c37eda13
WY		 1943}
1944
d2f62766
TY		 1945static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1946{
d2f62766
TY		 1947 int rc;
1948 unsigned short sel;
1949
9dac77fa 1950 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1951
7b105ca2 1952 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1953 if (rc != X86EMUL_CONTINUE)
1954 return rc;
1955
9dac77fa
AK		 1956 ctxt->_eip = 0;
1957 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1958 return X86EMUL_CONTINUE;
1959}
1960
51187683 1961static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1962{
4179bb02 1963 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1964
9dac77fa 1965 switch (ctxt->modrm_reg) {
d19292e4
MG		 1966 case 2: /* call near abs */ {
1967 long int old_eip;
9dac77fa
AK		 1968 old_eip = ctxt->_eip;
1969 ctxt->_eip = ctxt->src.val;
1970 ctxt->src.val = old_eip;
4487b3b4 1971 rc = em_push(ctxt);
d19292e4
MG		 1972 break;
1973 }
8cdbd2c9 1974 case 4: /* jmp abs */
9dac77fa 1975 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1976 break;
d2f62766
TY		 1977 case 5: /* jmp far */
1978 rc = em_jmp_far(ctxt);
1979 break;
8cdbd2c9 1980 case 6: /* push */
4487b3b4 1981 rc = em_push(ctxt);
8cdbd2c9 1982 break;
8cdbd2c9 1983 }
4179bb02 1984 return rc;
8cdbd2c9
LV		 1985}
1986
e0dac408 1987static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1988{
9dac77fa 1989 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1990
aaa05f24
NA		 1991 if (ctxt->dst.bytes == 16)
1992 return X86EMUL_UNHANDLEABLE;
1993
dd856efa
AK		 1994 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
1995 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
1996 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
1997 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 1998 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1999 } else {
dd856efa
AK		 2000 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2001 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2002
05f086f8 2003 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2004 }
1b30eaa8 2005 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2006}
2007
ebda02c2
TY		 2008static int em_ret(struct x86_emulate_ctxt *ctxt)
2009{
9dac77fa
AK		 2010 ctxt->dst.type = OP_REG;
2011 ctxt->dst.addr.reg = &ctxt->_eip;
2012 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2013 return em_pop(ctxt);
2014}
2015
e01991e7 2016static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2017{
a77ab5ea
AK		 2018 int rc;
2019 unsigned long cs;
9e8919ae 2020 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2021
9dac77fa 2022 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2023 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2024 return rc;
9dac77fa
AK		 2025 if (ctxt->op_bytes == 4)
2026 ctxt->_eip = (u32)ctxt->_eip;
2027 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2028 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2029 return rc;
9e8919ae
NA		 2030 /* Outer-privilege level return is not implemented */
2031 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2032 return X86EMUL_UNHANDLEABLE;
7b105ca2 2033 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2034 return rc;
2035}
2036
3261107e
BR		 2037static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2038{
2039 int rc;
2040
2041 rc = em_ret_far(ctxt);
2042 if (rc != X86EMUL_CONTINUE)
2043 return rc;
2044 rsp_increment(ctxt, ctxt->src.val);
2045 return X86EMUL_CONTINUE;
2046}
2047
e940b5c2
TY		 2048static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2049{
2050 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2051 ctxt->dst.orig_val = ctxt->dst.val;
2052 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2053 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2054 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2055 fastop(ctxt, em_cmp);
e940b5c2
TY		 2056
2057 if (ctxt->eflags & EFLG_ZF) {
2058 /* Success: write back to memory. */
2059 ctxt->dst.val = ctxt->src.orig_val;
2060 } else {
2061 /* Failure: write the value we saw to EAX. */
2062 ctxt->dst.type = OP_REG;
dd856efa 2063 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2064 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2065 }
2066 return X86EMUL_CONTINUE;
2067}
2068
d4b4325f 2069static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2070{
d4b4325f 2071 int seg = ctxt->src2.val;
09b5f4d3
WY		 2072 unsigned short sel;
2073 int rc;
2074
9dac77fa 2075 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2076
7b105ca2 2077 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2078 if (rc != X86EMUL_CONTINUE)
2079 return rc;
2080
9dac77fa 2081 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2082 return rc;
2083}
2084
7b105ca2 2085static void
e66bb2cc 2086setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2087 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2088{
e66bb2cc 2089 cs->l = 0; /* will be adjusted later */
79168fd1 2090 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2091 cs->g = 1; /* 4kb granularity */
79168fd1 2092 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2093 cs->type = 0x0b; /* Read, Execute, Accessed */
2094 cs->s = 1;
2095 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2096 cs->p = 1;
2097 cs->d = 1;
99245b50 2098 cs->avl = 0;
e66bb2cc 2099
79168fd1
GN		 2100 set_desc_base(ss, 0); /* flat segment */
2101 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2102 ss->g = 1; /* 4kb granularity */
2103 ss->s = 1;
2104 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2105 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2106 ss->dpl = 0;
79168fd1 2107 ss->p = 1;
99245b50
GN		 2108 ss->l = 0;
2109 ss->avl = 0;
e66bb2cc
AP		 2110}
2111
1a18a69b
AK		 2112static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2113{
2114 u32 eax, ebx, ecx, edx;
2115
2116 eax = ecx = 0;
0017f93a
AK		 2117 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2118 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2119 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2120 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2121}
2122
c2226fc9
SB		 2123static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2124{
0225fb50 2125 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2126 u32 eax, ebx, ecx, edx;
2127
2128 /*
2129 * syscall should always be enabled in longmode - so only become
2130 * vendor specific (cpuid) if other modes are active...
2131 */
2132 if (ctxt->mode == X86EMUL_MODE_PROT64)
2133 return true;
2134
2135 eax = 0x00000000;
2136 ecx = 0x00000000;
0017f93a
AK		 2137 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2138 /*
2139 * Intel ("GenuineIntel")
2140 * remark: Intel CPUs only support "syscall" in 64bit
2141 * longmode. Also an 64bit guest with a
2142 * 32bit compat-app running will #UD !! While this
2143 * behaviour can be fixed (by emulating) into AMD
2144 * response - CPUs of AMD can't behave like Intel.
2145 */
2146 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2147 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2148 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2149 return false;
2150
2151 /* AMD ("AuthenticAMD") */
2152 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2153 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2154 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2155 return true;
2156
2157 /* AMD ("AMDisbetter!") */
2158 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2159 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2160 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2161 return true;
c2226fc9
SB		 2162
2163 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2164 return false;
2165}
2166
e01991e7 2167static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2168{
0225fb50 2169 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2170 struct desc_struct cs, ss;
e66bb2cc 2171 u64 msr_data;
79168fd1 2172 u16 cs_sel, ss_sel;
c2ad2bb3 2173 u64 efer = 0;
e66bb2cc
AP		 2174
2175 /* syscall is not available in real mode */
2e901c4c 2176 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2177 ctxt->mode == X86EMUL_MODE_VM86)
2178 return emulate_ud(ctxt);
e66bb2cc 2179
c2226fc9
SB		 2180 if (!(em_syscall_is_enabled(ctxt)))
2181 return emulate_ud(ctxt);
2182
c2ad2bb3 2183 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2184 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2185
c2226fc9
SB		 2186 if (!(efer & EFER_SCE))
2187 return emulate_ud(ctxt);
2188
717746e3 2189 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2190 msr_data >>= 32;
79168fd1
GN		 2191 cs_sel = (u16)(msr_data & 0xfffc);
2192 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2193
c2ad2bb3 2194 if (efer & EFER_LMA) {
79168fd1 2195 cs.d = 0;
e66bb2cc
AP		 2196 cs.l = 1;
2197 }
1aa36616
AK		 2198 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2199 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2200
dd856efa 2201 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2202 if (efer & EFER_LMA) {
e66bb2cc 2203#ifdef CONFIG_X86_64
dd856efa 2204 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2205
717746e3 2206 ops->get_msr(ctxt,
3fb1b5db
GN		 2207 ctxt->mode == X86EMUL_MODE_PROT64 ?
2208 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2209 ctxt->_eip = msr_data;
e66bb2cc 2210
717746e3 2211 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2212 ctxt->eflags &= ~(msr_data | EFLG_RF);
2213#endif
2214 } else {
2215 /* legacy mode */
717746e3 2216 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2217 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2218
2219 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2220 }
2221
e54cfa97 2222 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2223}
2224
e01991e7 2225static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2226{
0225fb50 2227 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2228 struct desc_struct cs, ss;
8c604352 2229 u64 msr_data;
79168fd1 2230 u16 cs_sel, ss_sel;
c2ad2bb3 2231 u64 efer = 0;
8c604352 2232
7b105ca2 2233 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2234 /* inject #GP if in real mode */
35d3d4a1
AK		 2235 if (ctxt->mode == X86EMUL_MODE_REAL)
2236 return emulate_gp(ctxt, 0);
8c604352 2237
1a18a69b
AK		 2238 /*
2239 * Not recognized on AMD in compat mode (but is recognized in legacy
2240 * mode).
2241 */
2242 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2243 && !vendor_intel(ctxt))
2244 return emulate_ud(ctxt);
2245
8c604352
AP		 2246 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2247 * Therefore, we inject an #UD.
2248 */
35d3d4a1
AK		 2249 if (ctxt->mode == X86EMUL_MODE_PROT64)
2250 return emulate_ud(ctxt);
8c604352 2251
7b105ca2 2252 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2253
717746e3 2254 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2255 switch (ctxt->mode) {
2256 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2257 if ((msr_data & 0xfffc) == 0x0)
2258 return emulate_gp(ctxt, 0);
8c604352
AP		 2259 break;
2260 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2261 if (msr_data == 0x0)
2262 return emulate_gp(ctxt, 0);
8c604352 2263 break;
9d1b39a9
GN		 2264 default:
2265 break;
8c604352
AP		 2266 }
2267
2268 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2269 cs_sel = (u16)msr_data;
2270 cs_sel &= ~SELECTOR_RPL_MASK;
2271 ss_sel = cs_sel + 8;
2272 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2273 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2274 cs.d = 0;
8c604352
AP		 2275 cs.l = 1;
2276 }
2277
1aa36616
AK		 2278 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2279 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2280
717746e3 2281 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2282 ctxt->_eip = msr_data;
8c604352 2283
717746e3 2284 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2285 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2286
e54cfa97 2287 return X86EMUL_CONTINUE;
8c604352
AP		 2288}
2289
e01991e7 2290static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2291{
0225fb50 2292 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2293 struct desc_struct cs, ss;
4668f050
AP		 2294 u64 msr_data;
2295 int usermode;
1249b96e 2296 u16 cs_sel = 0, ss_sel = 0;
4668f050 2297
a0044755
GN		 2298 /* inject #GP if in real mode or Virtual 8086 mode */
2299 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2300 ctxt->mode == X86EMUL_MODE_VM86)
2301 return emulate_gp(ctxt, 0);
4668f050 2302
7b105ca2 2303 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2304
9dac77fa 2305 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2306 usermode = X86EMUL_MODE_PROT64;
2307 else
2308 usermode = X86EMUL_MODE_PROT32;
2309
2310 cs.dpl = 3;
2311 ss.dpl = 3;
717746e3 2312 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2313 switch (usermode) {
2314 case X86EMUL_MODE_PROT32:
79168fd1 2315 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2316 if ((msr_data & 0xfffc) == 0x0)
2317 return emulate_gp(ctxt, 0);
79168fd1 2318 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2319 break;
2320 case X86EMUL_MODE_PROT64:
79168fd1 2321 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2322 if (msr_data == 0x0)
2323 return emulate_gp(ctxt, 0);
79168fd1
GN		 2324 ss_sel = cs_sel + 8;
2325 cs.d = 0;
4668f050
AP		 2326 cs.l = 1;
2327 break;
2328 }
79168fd1
GN		 2329 cs_sel |= SELECTOR_RPL_MASK;
2330 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2331
1aa36616
AK		 2332 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2333 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2334
dd856efa
AK		 2335 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2336 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2337
e54cfa97 2338 return X86EMUL_CONTINUE;
4668f050
AP		 2339}
2340
7b105ca2 2341static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2342{
2343 int iopl;
2344 if (ctxt->mode == X86EMUL_MODE_REAL)
2345 return false;
2346 if (ctxt->mode == X86EMUL_MODE_VM86)
2347 return true;
2348 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2349 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2350}
2351
2352static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2353 u16 port, u16 len)
2354{
0225fb50 2355 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2356 struct desc_struct tr_seg;
5601d05b 2357 u32 base3;
f850e2e6 2358 int r;
1aa36616 2359 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2360 unsigned mask = (1 << len) - 1;
5601d05b 2361 unsigned long base;
f850e2e6 2362
1aa36616 2363 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2364 if (!tr_seg.p)
f850e2e6 2365 return false;
79168fd1 2366 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2367 return false;
5601d05b
GN		 2368 base = get_desc_base(&tr_seg);
2369#ifdef CONFIG_X86_64
2370 base |= ((u64)base3) << 32;
2371#endif
0f65dd70 2372 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2373 if (r != X86EMUL_CONTINUE)
2374 return false;
79168fd1 2375 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2376 return false;
0f65dd70 2377 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2378 if (r != X86EMUL_CONTINUE)
2379 return false;
2380 if ((perm >> bit_idx) & mask)
2381 return false;
2382 return true;
2383}
2384
2385static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2386 u16 port, u16 len)
2387{
4fc40f07
GN		 2388 if (ctxt->perm_ok)
2389 return true;
2390
7b105ca2
TY		 2391 if (emulator_bad_iopl(ctxt))
2392 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2393 return false;
4fc40f07
GN		 2394
2395 ctxt->perm_ok = true;
2396
f850e2e6
GN		 2397 return true;
2398}
2399
38ba30ba 2400static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2401 struct tss_segment_16 *tss)
2402{
9dac77fa 2403 tss->ip = ctxt->_eip;
38ba30ba 2404 tss->flag = ctxt->eflags;
dd856efa
AK		 2405 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2406 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2407 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2408 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2409 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2410 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2411 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2412 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2413
1aa36616
AK		 2414 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2415 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2416 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2417 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2418 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2419}
2420
2421static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2422 struct tss_segment_16 *tss)
2423{
38ba30ba 2424 int ret;
2356aaeb 2425 u8 cpl;
38ba30ba 2426
9dac77fa 2427 ctxt->_eip = tss->ip;
38ba30ba 2428 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2429 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2430 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2431 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2432 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2433 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2434 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2435 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2436 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2437
2438 /*
2439 * SDM says that segment selectors are loaded before segment
2440 * descriptors
2441 */
1aa36616
AK		 2442 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2443 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2444 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2445 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2446 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2447
2356aaeb
PB		 2448 cpl = tss->cs & 3;
2449
38ba30ba 2450 /*
fc058680 2451 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2452 * it is handled in a context of new task
2453 */
5045b468 2454 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2455 if (ret != X86EMUL_CONTINUE)
2456 return ret;
5045b468 2457 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2458 if (ret != X86EMUL_CONTINUE)
2459 return ret;
5045b468 2460 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2461 if (ret != X86EMUL_CONTINUE)
2462 return ret;
5045b468 2463 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2464 if (ret != X86EMUL_CONTINUE)
2465 return ret;
5045b468 2466 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2467 if (ret != X86EMUL_CONTINUE)
2468 return ret;
2469
2470 return X86EMUL_CONTINUE;
2471}
2472
2473static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2474 u16 tss_selector, u16 old_tss_sel,
2475 ulong old_tss_base, struct desc_struct *new_desc)
2476{
0225fb50 2477 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2478 struct tss_segment_16 tss_seg;
2479 int ret;
bcc55cba 2480 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2481
0f65dd70 2482 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2483 &ctxt->exception);
db297e3d 2484 if (ret != X86EMUL_CONTINUE)
38ba30ba 2485 /* FIXME: need to provide precise fault address */
38ba30ba 2486 return ret;
38ba30ba 2487
7b105ca2 2488 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2489
0f65dd70 2490 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2491 &ctxt->exception);
db297e3d 2492 if (ret != X86EMUL_CONTINUE)
38ba30ba 2493 /* FIXME: need to provide precise fault address */
38ba30ba 2494 return ret;
38ba30ba 2495
0f65dd70 2496 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2497 &ctxt->exception);
db297e3d 2498 if (ret != X86EMUL_CONTINUE)
38ba30ba 2499 /* FIXME: need to provide precise fault address */
38ba30ba 2500 return ret;
38ba30ba
GN		 2501
2502 if (old_tss_sel != 0xffff) {
2503 tss_seg.prev_task_link = old_tss_sel;
2504
0f65dd70 2505 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2506 &tss_seg.prev_task_link,
2507 sizeof tss_seg.prev_task_link,
0f65dd70 2508 &ctxt->exception);
db297e3d 2509 if (ret != X86EMUL_CONTINUE)
38ba30ba 2510 /* FIXME: need to provide precise fault address */
38ba30ba 2511 return ret;
38ba30ba
GN		 2512 }
2513
7b105ca2 2514 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2515}
2516
2517static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2518 struct tss_segment_32 *tss)
2519{
5c7411e2 2520 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2521 tss->eip = ctxt->_eip;
38ba30ba 2522 tss->eflags = ctxt->eflags;
dd856efa
AK		 2523 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2524 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2525 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2526 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2527 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2528 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2529 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2530 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2531
1aa36616
AK		 2532 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2533 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2534 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2535 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2536 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2537 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2538}
2539
2540static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2541 struct tss_segment_32 *tss)
2542{
38ba30ba 2543 int ret;
2356aaeb 2544 u8 cpl;
38ba30ba 2545
7b105ca2 2546 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2547 return emulate_gp(ctxt, 0);
9dac77fa 2548 ctxt->_eip = tss->eip;
38ba30ba 2549 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2550
2551 /* General purpose registers */
dd856efa
AK		 2552 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2553 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2554 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2555 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2556 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2557 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2558 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2559 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2560
2561 /*
2562 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2563 * descriptors. This is important because CPL checks will
2564 * use CS.RPL.
38ba30ba 2565 */
1aa36616
AK		 2566 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2567 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2568 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2569 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2570 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2571 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2572 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2573
4cee4798
KW		 2574 /*
2575 * If we're switching between Protected Mode and VM86, we need to make
2576 * sure to update the mode before loading the segment descriptors so
2577 * that the selectors are interpreted correctly.
4cee4798 2578 */
2356aaeb 2579 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2580 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2581 cpl = 3;
2582 } else {
4cee4798 2583 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2584 cpl = tss->cs & 3;
2585 }
4cee4798 2586
38ba30ba
GN		 2587 /*
2588 * Now load segment descriptors. If fault happenes at this stage
2589 * it is handled in a context of new task
2590 */
5045b468 2591 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2592 if (ret != X86EMUL_CONTINUE)
2593 return ret;
5045b468 2594 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2595 if (ret != X86EMUL_CONTINUE)
2596 return ret;
5045b468 2597 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2598 if (ret != X86EMUL_CONTINUE)
2599 return ret;
5045b468 2600 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2601 if (ret != X86EMUL_CONTINUE)
2602 return ret;
5045b468 2603 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
5045b468 2606 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2607 if (ret != X86EMUL_CONTINUE)
2608 return ret;
5045b468 2609 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2610 if (ret != X86EMUL_CONTINUE)
2611 return ret;
2612
2613 return X86EMUL_CONTINUE;
2614}
2615
2616static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2617 u16 tss_selector, u16 old_tss_sel,
2618 ulong old_tss_base, struct desc_struct *new_desc)
2619{
0225fb50 2620 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2621 struct tss_segment_32 tss_seg;
2622 int ret;
bcc55cba 2623 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2624 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2625 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2626
0f65dd70 2627 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2628 &ctxt->exception);
db297e3d 2629 if (ret != X86EMUL_CONTINUE)
38ba30ba 2630 /* FIXME: need to provide precise fault address */
38ba30ba 2631 return ret;
38ba30ba 2632
7b105ca2 2633 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2634
5c7411e2
NA		 2635 /* Only GP registers and segment selectors are saved */
2636 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2637 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2638 if (ret != X86EMUL_CONTINUE)
38ba30ba 2639 /* FIXME: need to provide precise fault address */
38ba30ba 2640 return ret;
38ba30ba 2641
0f65dd70 2642 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2643 &ctxt->exception);
db297e3d 2644 if (ret != X86EMUL_CONTINUE)
38ba30ba 2645 /* FIXME: need to provide precise fault address */
38ba30ba 2646 return ret;
38ba30ba
GN		 2647
2648 if (old_tss_sel != 0xffff) {
2649 tss_seg.prev_task_link = old_tss_sel;
2650
0f65dd70 2651 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2652 &tss_seg.prev_task_link,
2653 sizeof tss_seg.prev_task_link,
0f65dd70 2654 &ctxt->exception);
db297e3d 2655 if (ret != X86EMUL_CONTINUE)
38ba30ba 2656 /* FIXME: need to provide precise fault address */
38ba30ba 2657 return ret;
38ba30ba
GN		 2658 }
2659
7b105ca2 2660 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2661}
2662
2663static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2664 u16 tss_selector, int idt_index, int reason,
e269fb21 2665 bool has_error_code, u32 error_code)
38ba30ba 2666{
0225fb50 2667 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2668 struct desc_struct curr_tss_desc, next_tss_desc;
2669 int ret;
1aa36616 2670 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2671 ulong old_tss_base =
4bff1e86 2672 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2673 u32 desc_limit;
e919464b 2674 ulong desc_addr;
38ba30ba
GN		 2675
2676 /* FIXME: old_tss_base == ~0 ? */
2677
e919464b 2678 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2679 if (ret != X86EMUL_CONTINUE)
2680 return ret;
e919464b 2681 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2682 if (ret != X86EMUL_CONTINUE)
2683 return ret;
2684
2685 /* FIXME: check that next_tss_desc is tss */
2686
7f3d35fd
KW		 2687 /*
2688 * Check privileges. The three cases are task switch caused by...
2689 *
2690 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2691 * 2. Exception/IRQ/iret: No check is performed
fc058680 2692 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2693 */
2694 if (reason == TASK_SWITCH_GATE) {
2695 if (idt_index != -1) {
2696 /* Software interrupts */
2697 struct desc_struct task_gate_desc;
2698 int dpl;
2699
2700 ret = read_interrupt_descriptor(ctxt, idt_index,
2701 &task_gate_desc);
2702 if (ret != X86EMUL_CONTINUE)
2703 return ret;
2704
2705 dpl = task_gate_desc.dpl;
2706 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2707 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2708 }
2709 } else if (reason != TASK_SWITCH_IRET) {
2710 int dpl = next_tss_desc.dpl;
2711 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2712 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2713 }
2714
7f3d35fd 2715
ceffb459
GN		 2716 desc_limit = desc_limit_scaled(&next_tss_desc);
2717 if (!next_tss_desc.p ||
2718 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2719 desc_limit < 0x2b)) {
54b8486f 2720 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2721 return X86EMUL_PROPAGATE_FAULT;
2722 }
2723
2724 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2725 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2726 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2727 }
2728
2729 if (reason == TASK_SWITCH_IRET)
2730 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2731
2732 /* set back link to prev task only if NT bit is set in eflags
fc058680 2733 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2734 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2735 old_tss_sel = 0xffff;
2736
2737 if (next_tss_desc.type & 8)
7b105ca2 2738 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2739 old_tss_base, &next_tss_desc);
2740 else
7b105ca2 2741 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2742 old_tss_base, &next_tss_desc);
0760d448
JK		 2743 if (ret != X86EMUL_CONTINUE)
2744 return ret;
38ba30ba
GN		 2745
2746 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2747 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2748
2749 if (reason != TASK_SWITCH_IRET) {
2750 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2751 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2752 }
2753
717746e3 2754 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2755 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2756
e269fb21 2757 if (has_error_code) {
9dac77fa
AK		 2758 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2759 ctxt->lock_prefix = 0;
2760 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2761 ret = em_push(ctxt);
e269fb21
JK		 2762 }
2763
38ba30ba
GN		 2764 return ret;
2765}
2766
2767int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2768 u16 tss_selector, int idt_index, int reason,
e269fb21 2769 bool has_error_code, u32 error_code)
38ba30ba 2770{
38ba30ba
GN		 2771 int rc;
2772
dd856efa 2773 invalidate_registers(ctxt);
9dac77fa
AK		 2774 ctxt->_eip = ctxt->eip;
2775 ctxt->dst.type = OP_NONE;
38ba30ba 2776
7f3d35fd 2777 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2778 has_error_code, error_code);
38ba30ba 2779
dd856efa 2780 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2781 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2782 writeback_registers(ctxt);
2783 }
38ba30ba 2784
a0c0ab2f 2785 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2786}
2787
f3bd64c6
GN		 2788static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2789 struct operand *op)
a682e354 2790{
b3356bf0 2791 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2792
dd856efa
AK		 2793 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2794 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2795}
2796
7af04fc0
AK		 2797static int em_das(struct x86_emulate_ctxt *ctxt)
2798{
7af04fc0
AK		 2799 u8 al, old_al;
2800 bool af, cf, old_cf;
2801
2802 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2803 al = ctxt->dst.val;
7af04fc0
AK		 2804
2805 old_al = al;
2806 old_cf = cf;
2807 cf = false;
2808 af = ctxt->eflags & X86_EFLAGS_AF;
2809 if ((al & 0x0f) > 9 || af) {
2810 al -= 6;
2811 cf = old_cf | (al >= 250);
2812 af = true;
2813 } else {
2814 af = false;
2815 }
2816 if (old_al > 0x99 || old_cf) {
2817 al -= 0x60;
2818 cf = true;
2819 }
2820
9dac77fa 2821 ctxt->dst.val = al;
7af04fc0 2822 /* Set PF, ZF, SF */
9dac77fa
AK		 2823 ctxt->src.type = OP_IMM;
2824 ctxt->src.val = 0;
2825 ctxt->src.bytes = 1;
158de57f 2826 fastop(ctxt, em_or);
7af04fc0
AK		 2827 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2828 if (cf)
2829 ctxt->eflags |= X86_EFLAGS_CF;
2830 if (af)
2831 ctxt->eflags |= X86_EFLAGS_AF;
2832 return X86EMUL_CONTINUE;
2833}
2834
a035d5c6
PB		 2835static int em_aam(struct x86_emulate_ctxt *ctxt)
2836{
2837 u8 al, ah;
2838
2839 if (ctxt->src.val == 0)
2840 return emulate_de(ctxt);
2841
2842 al = ctxt->dst.val & 0xff;
2843 ah = al / ctxt->src.val;
2844 al %= ctxt->src.val;
2845
2846 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2847
2848 /* Set PF, ZF, SF */
2849 ctxt->src.type = OP_IMM;
2850 ctxt->src.val = 0;
2851 ctxt->src.bytes = 1;
2852 fastop(ctxt, em_or);
2853
2854 return X86EMUL_CONTINUE;
2855}
2856
7f662273
GN		 2857static int em_aad(struct x86_emulate_ctxt *ctxt)
2858{
2859 u8 al = ctxt->dst.val & 0xff;
2860 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2861
2862 al = (al + (ah * ctxt->src.val)) & 0xff;
2863
2864 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2865
f583c29b
GN		 2866 /* Set PF, ZF, SF */
2867 ctxt->src.type = OP_IMM;
2868 ctxt->src.val = 0;
2869 ctxt->src.bytes = 1;
2870 fastop(ctxt, em_or);
7f662273
GN		 2871
2872 return X86EMUL_CONTINUE;
2873}
2874
d4ddafcd
TY		 2875static int em_call(struct x86_emulate_ctxt *ctxt)
2876{
2877 long rel = ctxt->src.val;
2878
2879 ctxt->src.val = (unsigned long)ctxt->_eip;
2880 jmp_rel(ctxt, rel);
2881 return em_push(ctxt);
2882}
2883
0ef753b8
AK		 2884static int em_call_far(struct x86_emulate_ctxt *ctxt)
2885{
0ef753b8
AK		 2886 u16 sel, old_cs;
2887 ulong old_eip;
2888 int rc;
2889
1aa36616 2890 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2891 old_eip = ctxt->_eip;
0ef753b8 2892
9dac77fa 2893 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2894 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2895 return X86EMUL_CONTINUE;
2896
9dac77fa
AK		 2897 ctxt->_eip = 0;
2898 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2899
9dac77fa 2900 ctxt->src.val = old_cs;
4487b3b4 2901 rc = em_push(ctxt);
0ef753b8
AK		 2902 if (rc != X86EMUL_CONTINUE)
2903 return rc;
2904
9dac77fa 2905 ctxt->src.val = old_eip;
4487b3b4 2906 return em_push(ctxt);
0ef753b8
AK		 2907}
2908
40ece7c7
AK		 2909static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2910{
40ece7c7
AK		 2911 int rc;
2912
9dac77fa
AK		 2913 ctxt->dst.type = OP_REG;
2914 ctxt->dst.addr.reg = &ctxt->_eip;
2915 ctxt->dst.bytes = ctxt->op_bytes;
2916 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2917 if (rc != X86EMUL_CONTINUE)
2918 return rc;
5ad105e5 2919 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2920 return X86EMUL_CONTINUE;
2921}
2922
e4f973ae
TY		 2923static int em_xchg(struct x86_emulate_ctxt *ctxt)
2924{
e4f973ae 2925 /* Write back the register source. */
9dac77fa
AK		 2926 ctxt->src.val = ctxt->dst.val;
2927 write_register_operand(&ctxt->src);
e4f973ae
TY		 2928
2929 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2930 ctxt->dst.val = ctxt->src.orig_val;
2931 ctxt->lock_prefix = 1;
e4f973ae
TY		 2932 return X86EMUL_CONTINUE;
2933}
2934
5c82aa29
AK		 2935static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2936{
9dac77fa 2937 ctxt->dst.val = ctxt->src2.val;
4d758349 2938 return fastop(ctxt, em_imul);
5c82aa29
AK		 2939}
2940
61429142
AK		 2941static int em_cwd(struct x86_emulate_ctxt *ctxt)
2942{
9dac77fa
AK		 2943 ctxt->dst.type = OP_REG;
2944 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2945 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2946 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2947
2948 return X86EMUL_CONTINUE;
2949}
2950
48bb5d3c
AK		 2951static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2952{
48bb5d3c
AK		 2953 u64 tsc = 0;
2954
717746e3 2955 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2956 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2957 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2958 return X86EMUL_CONTINUE;
2959}
2960
222d21aa
AK		 2961static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2962{
2963 u64 pmc;
2964
dd856efa 2965 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2966 return emulate_gp(ctxt, 0);
dd856efa
AK		 2967 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2968 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2969 return X86EMUL_CONTINUE;
2970}
2971
b9eac5f4
AK		 2972static int em_mov(struct x86_emulate_ctxt *ctxt)
2973{
54cfdb3e 2974 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2975 return X86EMUL_CONTINUE;
2976}
2977
84cffe49
BP		 2978#define FFL(x) bit(X86_FEATURE_##x)
2979
2980static int em_movbe(struct x86_emulate_ctxt *ctxt)
2981{
2982 u32 ebx, ecx, edx, eax = 1;
2983 u16 tmp;
2984
2985 /*
2986 * Check MOVBE is set in the guest-visible CPUID leaf.
2987 */
2988 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2989 if (!(ecx & FFL(MOVBE)))
2990 return emulate_ud(ctxt);
2991
2992 switch (ctxt->op_bytes) {
2993 case 2:
2994 /*
2995 * From MOVBE definition: "...When the operand size is 16 bits,
2996 * the upper word of the destination register remains unchanged
2997 * ..."
2998 *
2999 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3000 * rules so we have to do the operation almost per hand.
3001 */
3002 tmp = (u16)ctxt->src.val;
3003 ctxt->dst.val &= ~0xffffUL;
3004 ctxt->dst.val |= (unsigned long)swab16(tmp);
3005 break;
3006 case 4:
3007 ctxt->dst.val = swab32((u32)ctxt->src.val);
3008 break;
3009 case 8:
3010 ctxt->dst.val = swab64(ctxt->src.val);
3011 break;
3012 default:
3013 return X86EMUL_PROPAGATE_FAULT;
3014 }
3015 return X86EMUL_CONTINUE;
3016}
3017
bc00f8d2
TY		 3018static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3019{
3020 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3021 return emulate_gp(ctxt, 0);
3022
3023 /* Disable writeback. */
3024 ctxt->dst.type = OP_NONE;
3025 return X86EMUL_CONTINUE;
3026}
3027
3028static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3029{
3030 unsigned long val;
3031
3032 if (ctxt->mode == X86EMUL_MODE_PROT64)
3033 val = ctxt->src.val & ~0ULL;
3034 else
3035 val = ctxt->src.val & ~0U;
3036
3037 /* #UD condition is already handled. */
3038 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3039 return emulate_gp(ctxt, 0);
3040
3041 /* Disable writeback. */
3042 ctxt->dst.type = OP_NONE;
3043 return X86EMUL_CONTINUE;
3044}
3045
e1e210b0
TY		 3046static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3047{
3048 u64 msr_data;
3049
dd856efa
AK		 3050 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3051 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3052 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3053 return emulate_gp(ctxt, 0);
3054
3055 return X86EMUL_CONTINUE;
3056}
3057
3058static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3059{
3060 u64 msr_data;
3061
dd856efa 3062 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3063 return emulate_gp(ctxt, 0);
3064
dd856efa
AK		 3065 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3066 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3067 return X86EMUL_CONTINUE;
3068}
3069
1bd5f469
TY		 3070static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3071{
9dac77fa 3072 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3073 return emulate_ud(ctxt);
3074
9dac77fa 3075 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3076 return X86EMUL_CONTINUE;
3077}
3078
3079static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3080{
9dac77fa 3081 u16 sel = ctxt->src.val;
1bd5f469 3082
9dac77fa 3083 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3084 return emulate_ud(ctxt);
3085
9dac77fa 3086 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3087 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3088
3089 /* Disable writeback. */
9dac77fa
AK		 3090 ctxt->dst.type = OP_NONE;
3091 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3092}
3093
a14e579f
AK		 3094static int em_lldt(struct x86_emulate_ctxt *ctxt)
3095{
3096 u16 sel = ctxt->src.val;
3097
3098 /* Disable writeback. */
3099 ctxt->dst.type = OP_NONE;
3100 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3101}
3102
80890006
AK		 3103static int em_ltr(struct x86_emulate_ctxt *ctxt)
3104{
3105 u16 sel = ctxt->src.val;
3106
3107 /* Disable writeback. */
3108 ctxt->dst.type = OP_NONE;
3109 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3110}
3111
38503911
AK		 3112static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3113{
9fa088f4
AK		 3114 int rc;
3115 ulong linear;
3116
9dac77fa 3117 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3118 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3119 ctxt->ops->invlpg(ctxt, linear);
38503911 3120 /* Disable writeback. */
9dac77fa 3121 ctxt->dst.type = OP_NONE;
38503911
AK		 3122 return X86EMUL_CONTINUE;
3123}
3124
2d04a05b
AK		 3125static int em_clts(struct x86_emulate_ctxt *ctxt)
3126{
3127 ulong cr0;
3128
3129 cr0 = ctxt->ops->get_cr(ctxt, 0);
3130 cr0 &= ~X86_CR0_TS;
3131 ctxt->ops->set_cr(ctxt, 0, cr0);
3132 return X86EMUL_CONTINUE;
3133}
3134
26d05cc7
AK		 3135static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3136{
26d05cc7
AK		 3137 int rc;
3138
9dac77fa 3139 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3140 return X86EMUL_UNHANDLEABLE;
3141
3142 rc = ctxt->ops->fix_hypercall(ctxt);
3143 if (rc != X86EMUL_CONTINUE)
3144 return rc;
3145
3146 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3147 ctxt->_eip = ctxt->eip;
26d05cc7 3148 /* Disable writeback. */
9dac77fa 3149 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3150 return X86EMUL_CONTINUE;
3151}
3152
96051572
AK		 3153static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3154 void (*get)(struct x86_emulate_ctxt *ctxt,
3155 struct desc_ptr *ptr))
3156{
3157 struct desc_ptr desc_ptr;
3158
3159 if (ctxt->mode == X86EMUL_MODE_PROT64)
3160 ctxt->op_bytes = 8;
3161 get(ctxt, &desc_ptr);
3162 if (ctxt->op_bytes == 2) {
3163 ctxt->op_bytes = 4;
3164 desc_ptr.address &= 0x00ffffff;
3165 }
3166 /* Disable writeback. */
3167 ctxt->dst.type = OP_NONE;
3168 return segmented_write(ctxt, ctxt->dst.addr.mem,
3169 &desc_ptr, 2 + ctxt->op_bytes);
3170}
3171
3172static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3173{
3174 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3175}
3176
3177static int em_sidt(struct x86_emulate_ctxt *ctxt)
3178{
3179 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3180}
3181
26d05cc7
AK		 3182static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3183{
26d05cc7
AK		 3184 struct desc_ptr desc_ptr;
3185 int rc;
3186
510425ff
AK		 3187 if (ctxt->mode == X86EMUL_MODE_PROT64)
3188 ctxt->op_bytes = 8;
9dac77fa 3189 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3190 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3191 ctxt->op_bytes);
26d05cc7
AK		 3192 if (rc != X86EMUL_CONTINUE)
3193 return rc;
3194 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3195 /* Disable writeback. */
9dac77fa 3196 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3197 return X86EMUL_CONTINUE;
3198}
3199
5ef39c71 3200static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3201{
26d05cc7
AK		 3202 int rc;
3203
5ef39c71
AK		 3204 rc = ctxt->ops->fix_hypercall(ctxt);
3205
26d05cc7 3206 /* Disable writeback. */
9dac77fa 3207 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3208 return rc;
3209}
3210
3211static int em_lidt(struct x86_emulate_ctxt *ctxt)
3212{
26d05cc7
AK		 3213 struct desc_ptr desc_ptr;
3214 int rc;
3215
510425ff
AK		 3216 if (ctxt->mode == X86EMUL_MODE_PROT64)
3217 ctxt->op_bytes = 8;
9dac77fa 3218 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3219 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3220 ctxt->op_bytes);
26d05cc7
AK		 3221 if (rc != X86EMUL_CONTINUE)
3222 return rc;
3223 ctxt->ops->set_idt(ctxt, &desc_ptr);
3224 /* Disable writeback. */
9dac77fa 3225 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3226 return X86EMUL_CONTINUE;
3227}
3228
3229static int em_smsw(struct x86_emulate_ctxt *ctxt)
3230{
32e94d06
NA		 3231 if (ctxt->dst.type == OP_MEM)
3232 ctxt->dst.bytes = 2;
9dac77fa 3233 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3234 return X86EMUL_CONTINUE;
3235}
3236
3237static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3238{
26d05cc7 3239 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3240 | (ctxt->src.val & 0x0f));
3241 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3242 return X86EMUL_CONTINUE;
3243}
3244
d06e03ad
TY		 3245static int em_loop(struct x86_emulate_ctxt *ctxt)
3246{
dd856efa
AK		 3247 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3248 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3249 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3250 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3251
3252 return X86EMUL_CONTINUE;
3253}
3254
3255static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3256{
dd856efa 3257 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3258 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3259
3260 return X86EMUL_CONTINUE;
3261}
3262
d7841a4b
TY		 3263static int em_in(struct x86_emulate_ctxt *ctxt)
3264{
3265 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3266 &ctxt->dst.val))
3267 return X86EMUL_IO_NEEDED;
3268
3269 return X86EMUL_CONTINUE;
3270}
3271
3272static int em_out(struct x86_emulate_ctxt *ctxt)
3273{
3274 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3275 &ctxt->src.val, 1);
3276 /* Disable writeback. */
3277 ctxt->dst.type = OP_NONE;
3278 return X86EMUL_CONTINUE;
3279}
3280
f411e6cd
TY		 3281static int em_cli(struct x86_emulate_ctxt *ctxt)
3282{
3283 if (emulator_bad_iopl(ctxt))
3284 return emulate_gp(ctxt, 0);
3285
3286 ctxt->eflags &= ~X86_EFLAGS_IF;
3287 return X86EMUL_CONTINUE;
3288}
3289
3290static int em_sti(struct x86_emulate_ctxt *ctxt)
3291{
3292 if (emulator_bad_iopl(ctxt))
3293 return emulate_gp(ctxt, 0);
3294
3295 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3296 ctxt->eflags |= X86_EFLAGS_IF;
3297 return X86EMUL_CONTINUE;
3298}
3299
6d6eede4
AK		 3300static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3301{
3302 u32 eax, ebx, ecx, edx;
3303
dd856efa
AK		 3304 eax = reg_read(ctxt, VCPU_REGS_RAX);
3305 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3306 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3307 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3308 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3309 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3310 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3311 return X86EMUL_CONTINUE;
3312}
3313
98f73630
PB		 3314static int em_sahf(struct x86_emulate_ctxt *ctxt)
3315{
3316 u32 flags;
3317
3318 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3319 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3320
3321 ctxt->eflags &= ~0xffUL;
3322 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3323 return X86EMUL_CONTINUE;
3324}
3325
2dd7caa0
AK		 3326static int em_lahf(struct x86_emulate_ctxt *ctxt)
3327{
dd856efa
AK		 3328 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3329 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3330 return X86EMUL_CONTINUE;
3331}
3332
9299836e
AK		 3333static int em_bswap(struct x86_emulate_ctxt *ctxt)
3334{
3335 switch (ctxt->op_bytes) {
3336#ifdef CONFIG_X86_64
3337 case 8:
3338 asm("bswap %0" : "+r"(ctxt->dst.val));
3339 break;
3340#endif
3341 default:
3342 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3343 break;
3344 }
3345 return X86EMUL_CONTINUE;
3346}
3347
cfec82cb
JR		 3348static bool valid_cr(int nr)
3349{
3350 switch (nr) {
3351 case 0:
3352 case 2 ... 4:
3353 case 8:
3354 return true;
3355 default:
3356 return false;
3357 }
3358}
3359
3360static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3361{
9dac77fa 3362 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3363 return emulate_ud(ctxt);
3364
3365 return X86EMUL_CONTINUE;
3366}
3367
3368static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3369{
9dac77fa
AK		 3370 u64 new_val = ctxt->src.val64;
3371 int cr = ctxt->modrm_reg;
c2ad2bb3 3372 u64 efer = 0;
cfec82cb
JR		 3373
3374 static u64 cr_reserved_bits[] = {
3375 0xffffffff00000000ULL,
3376 0, 0, 0, /* CR3 checked later */
3377 CR4_RESERVED_BITS,
3378 0, 0, 0,
3379 CR8_RESERVED_BITS,
3380 };
3381
3382 if (!valid_cr(cr))
3383 return emulate_ud(ctxt);
3384
3385 if (new_val & cr_reserved_bits[cr])
3386 return emulate_gp(ctxt, 0);
3387
3388 switch (cr) {
3389 case 0: {
c2ad2bb3 3390 u64 cr4;
cfec82cb
JR		 3391 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3392 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3393 return emulate_gp(ctxt, 0);
3394
717746e3
AK		 3395 cr4 = ctxt->ops->get_cr(ctxt, 4);
3396 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3397
3398 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3399 !(cr4 & X86_CR4_PAE))
3400 return emulate_gp(ctxt, 0);
3401
3402 break;
3403 }
3404 case 3: {
3405 u64 rsvd = 0;
3406
c2ad2bb3
AK		 3407 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3408 if (efer & EFER_LMA)
cfec82cb 3409 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3410
3411 if (new_val & rsvd)
3412 return emulate_gp(ctxt, 0);
3413
3414 break;
3415 }
3416 case 4: {
717746e3 3417 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3418
3419 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3420 return emulate_gp(ctxt, 0);
3421
3422 break;
3423 }
3424 }
3425
3426 return X86EMUL_CONTINUE;
3427}
3428
3b88e41a
JR		 3429static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3430{
3431 unsigned long dr7;
3432
717746e3 3433 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3434
3435 /* Check if DR7.Global_Enable is set */
3436 return dr7 & (1 << 13);
3437}
3438
3439static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3440{
9dac77fa 3441 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3442 u64 cr4;
3443
3444 if (dr > 7)
3445 return emulate_ud(ctxt);
3446
717746e3 3447 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3448 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3449 return emulate_ud(ctxt);
3450
3451 if (check_dr7_gd(ctxt))
3452 return emulate_db(ctxt);
3453
3454 return X86EMUL_CONTINUE;
3455}
3456
3457static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3458{
9dac77fa
AK		 3459 u64 new_val = ctxt->src.val64;
3460 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3461
3462 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3463 return emulate_gp(ctxt, 0);
3464
3465 return check_dr_read(ctxt);
3466}
3467
01de8b09
JR		 3468static int check_svme(struct x86_emulate_ctxt *ctxt)
3469{
3470 u64 efer;
3471
717746e3 3472 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3473
3474 if (!(efer & EFER_SVME))
3475 return emulate_ud(ctxt);
3476
3477 return X86EMUL_CONTINUE;
3478}
3479
3480static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3481{
dd856efa 3482 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3483
3484 /* Valid physical address? */
d4224449 3485 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3486 return emulate_gp(ctxt, 0);
3487
3488 return check_svme(ctxt);
3489}
3490
d7eb8203
JR		 3491static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3492{
717746e3 3493 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3494
717746e3 3495 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3496 return emulate_ud(ctxt);
3497
3498 return X86EMUL_CONTINUE;
3499}
3500
8061252e
JR		 3501static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3502{
717746e3 3503 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3504 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3505
717746e3 3506 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3507 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3508 return emulate_gp(ctxt, 0);
3509
3510 return X86EMUL_CONTINUE;
3511}
3512
f6511935
JR		 3513static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3514{
9dac77fa
AK		 3515 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3516 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3517 return emulate_gp(ctxt, 0);
3518
3519 return X86EMUL_CONTINUE;
3520}
3521
3522static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3523{
9dac77fa
AK		 3524 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3525 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3526 return emulate_gp(ctxt, 0);
3527
3528 return X86EMUL_CONTINUE;
3529}
3530
73fba5f4 3531#define D(_y) { .flags = (_y) }
d40a6898
PB		 3532#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3533#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3534 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3535#define N D(NotImpl)
01de8b09 3536#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3537#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3538#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3539#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3540#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3541#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3542#define II(_f, _e, _i) \
d40a6898 3543 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3544#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3545 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3546 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3547#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3548
8d8f4e9f 3549#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3550#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3551#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3552#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3553#define I2bvIP(_f, _e, _i, _p) \
3554 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3555
fb864fbc
AK		 3556#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3557 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3558 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3559
fd0a0d82 3560static const struct opcode group7_rm1[] = {
1c2545be
TY		 3561 DI(SrcNone | Priv, monitor),
3562 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3563 N, N, N, N, N, N,
3564};
3565
fd0a0d82 3566static const struct opcode group7_rm3[] = {
1c2545be 3567 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3568 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3569 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3570 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3571 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3572 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3573 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3574 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3575};
6230f7fc 3576
fd0a0d82 3577static const struct opcode group7_rm7[] = {
d7eb8203 3578 N,
1c2545be 3579 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3580 N, N, N, N, N, N,
3581};
d67fc27a 3582
fd0a0d82 3583static const struct opcode group1[] = {
fb864fbc
AK		 3584 F(Lock, em_add),
3585 F(Lock | PageTable, em_or),
3586 F(Lock, em_adc),
3587 F(Lock, em_sbb),
3588 F(Lock | PageTable, em_and),
3589 F(Lock, em_sub),
3590 F(Lock, em_xor),
3591 F(NoWrite, em_cmp),
73fba5f4
AK		 3592};
3593
fd0a0d82 3594static const struct opcode group1A[] = {
1c2545be 3595 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3596};
3597
007a3b54
AK		 3598static const struct opcode group2[] = {
3599 F(DstMem | ModRM, em_rol),
3600 F(DstMem | ModRM, em_ror),
3601 F(DstMem | ModRM, em_rcl),
3602 F(DstMem | ModRM, em_rcr),
3603 F(DstMem | ModRM, em_shl),
3604 F(DstMem | ModRM, em_shr),
3605 F(DstMem | ModRM, em_shl),
3606 F(DstMem | ModRM, em_sar),
3607};
3608
fd0a0d82 3609static const struct opcode group3[] = {
fb864fbc
AK		 3610 F(DstMem | SrcImm | NoWrite, em_test),
3611 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3612 F(DstMem | SrcNone | Lock, em_not),
3613 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3614 F(DstXacc | Src2Mem, em_mul_ex),
3615 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3616 F(DstXacc | Src2Mem, em_div_ex),
3617 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3618};
3619
fd0a0d82 3620static const struct opcode group4[] = {
95413dc4
AK		 3621 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3622 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3623 N, N, N, N, N, N,
3624};
3625
fd0a0d82 3626static const struct opcode group5[] = {
95413dc4
AK		 3627 F(DstMem | SrcNone | Lock, em_inc),
3628 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3629 I(SrcMem | Stack, em_grp45),
3630 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3631 I(SrcMem | Stack, em_grp45),
3632 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3633 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3634};
3635
fd0a0d82 3636static const struct opcode group6[] = {
1c2545be
TY		 3637 DI(Prot, sldt),
3638 DI(Prot, str),
a14e579f 3639 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3640 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3641 N, N, N, N,
3642};
3643
fd0a0d82 3644static const struct group_dual group7 = { {
606b1c3e
NA		 3645 II(Mov | DstMem, em_sgdt, sgdt),
3646 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3647 II(SrcMem | Priv, em_lgdt, lgdt),
3648 II(SrcMem | Priv, em_lidt, lidt),
3649 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3650 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3651 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3652}, {
b51e974f 3653 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3654 EXT(0, group7_rm1),
01de8b09 3655 N, EXT(0, group7_rm3),
1c2545be
TY		 3656 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3657 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3658 EXT(0, group7_rm7),
73fba5f4
AK		 3659} };
3660
fd0a0d82 3661static const struct opcode group8[] = {
73fba5f4 3662 N, N, N, N,
11c363ba
AK		 3663 F(DstMem | SrcImmByte | NoWrite, em_bt),
3664 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3665 F(DstMem | SrcImmByte | Lock, em_btr),
3666 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3667};
3668
fd0a0d82 3669static const struct group_dual group9 = { {
1c2545be 3670 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3671}, {
3672 N, N, N, N, N, N, N, N,
3673} };
3674
fd0a0d82 3675static const struct opcode group11[] = {
1c2545be 3676 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3677 X7(D(Undefined)),
a4d4a7c1
AK		 3678};
3679
fd0a0d82 3680static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3681 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3682};
3683
fd0a0d82 3684static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3685 I(0, em_mov), N, N, N,
3686};
3687
27ce8258 3688static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3689 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3690};
3691
045a282c
GN		 3692static const struct escape escape_d9 = { {
3693 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3694}, {
3695 /* 0xC0 - 0xC7 */
3696 N, N, N, N, N, N, N, N,
3697 /* 0xC8 - 0xCF */
3698 N, N, N, N, N, N, N, N,
3699 /* 0xD0 - 0xC7 */
3700 N, N, N, N, N, N, N, N,
3701 /* 0xD8 - 0xDF */
3702 N, N, N, N, N, N, N, N,
3703 /* 0xE0 - 0xE7 */
3704 N, N, N, N, N, N, N, N,
3705 /* 0xE8 - 0xEF */
3706 N, N, N, N, N, N, N, N,
3707 /* 0xF0 - 0xF7 */
3708 N, N, N, N, N, N, N, N,
3709 /* 0xF8 - 0xFF */
3710 N, N, N, N, N, N, N, N,
3711} };
3712
3713static const struct escape escape_db = { {
3714 N, N, N, N, N, N, N, N,
3715}, {
3716 /* 0xC0 - 0xC7 */
3717 N, N, N, N, N, N, N, N,
3718 /* 0xC8 - 0xCF */
3719 N, N, N, N, N, N, N, N,
3720 /* 0xD0 - 0xC7 */
3721 N, N, N, N, N, N, N, N,
3722 /* 0xD8 - 0xDF */
3723 N, N, N, N, N, N, N, N,
3724 /* 0xE0 - 0xE7 */
3725 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3726 /* 0xE8 - 0xEF */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xF0 - 0xF7 */
3729 N, N, N, N, N, N, N, N,
3730 /* 0xF8 - 0xFF */
3731 N, N, N, N, N, N, N, N,
3732} };
3733
3734static const struct escape escape_dd = { {
3735 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3736}, {
3737 /* 0xC0 - 0xC7 */
3738 N, N, N, N, N, N, N, N,
3739 /* 0xC8 - 0xCF */
3740 N, N, N, N, N, N, N, N,
3741 /* 0xD0 - 0xC7 */
3742 N, N, N, N, N, N, N, N,
3743 /* 0xD8 - 0xDF */
3744 N, N, N, N, N, N, N, N,
3745 /* 0xE0 - 0xE7 */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xE8 - 0xEF */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xF0 - 0xF7 */
3750 N, N, N, N, N, N, N, N,
3751 /* 0xF8 - 0xFF */
3752 N, N, N, N, N, N, N, N,
3753} };
3754
fd0a0d82 3755static const struct opcode opcode_table[256] = {
73fba5f4 3756 /* 0x00 - 0x07 */
fb864fbc 3757 F6ALU(Lock, em_add),
1cd196ea
AK		 3758 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3759 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3760 /* 0x08 - 0x0F */
fb864fbc 3761 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3762 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3763 N,
73fba5f4 3764 /* 0x10 - 0x17 */
fb864fbc 3765 F6ALU(Lock, em_adc),
1cd196ea
AK		 3766 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3767 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3768 /* 0x18 - 0x1F */
fb864fbc 3769 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3770 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3771 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3772 /* 0x20 - 0x27 */
fb864fbc 3773 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3774 /* 0x28 - 0x2F */
fb864fbc 3775 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3776 /* 0x30 - 0x37 */
fb864fbc 3777 F6ALU(Lock, em_xor), N, N,
73fba5f4 3778 /* 0x38 - 0x3F */
fb864fbc 3779 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3780 /* 0x40 - 0x4F */
95413dc4 3781 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3782 /* 0x50 - 0x57 */
63540382 3783 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3784 /* 0x58 - 0x5F */
c54fe504 3785 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3786 /* 0x60 - 0x67 */
b96a7fad
TY		 3787 I(ImplicitOps | Stack | No64, em_pusha),
3788 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3789 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3790 N, N, N, N,
3791 /* 0x68 - 0x6F */
d46164db
AK		 3792 I(SrcImm | Mov | Stack, em_push),
3793 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3794 I(SrcImmByte | Mov | Stack, em_push),
3795 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3796 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3797 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3798 /* 0x70 - 0x7F */
3799 X16(D(SrcImmByte)),
3800 /* 0x80 - 0x87 */
1c2545be
TY		 3801 G(ByteOp | DstMem | SrcImm, group1),
3802 G(DstMem | SrcImm, group1),
3803 G(ByteOp | DstMem | SrcImm | No64, group1),
3804 G(DstMem | SrcImmByte, group1),
fb864fbc 3805 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3806 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3807 /* 0x88 - 0x8F */
d5ae7ce8 3808 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3809 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3810 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3811 D(ModRM | SrcMem | NoAccess | DstReg),
3812 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3813 G(0, group1A),
73fba5f4 3814 /* 0x90 - 0x97 */
bf608f88 3815 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3816 /* 0x98 - 0x9F */
61429142 3817 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3818 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3819 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3820 II(ImplicitOps | Stack, em_popf, popf),
3821 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3822 /* 0xA0 - 0xA7 */
b9eac5f4 3823 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3824 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3825 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3826 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3827 /* 0xA8 - 0xAF */
fb864fbc 3828 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3829 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3830 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3831 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3832 /* 0xB0 - 0xB7 */
b9eac5f4 3833 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3834 /* 0xB8 - 0xBF */
5e2c6883 3835 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3836 /* 0xC0 - 0xC7 */
007a3b54 3837 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3838 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3839 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3840 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3841 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3842 G(ByteOp, group11), G(0, group11),
73fba5f4 3843 /* 0xC8 - 0xCF */
612e89f0 3844 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3845 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3846 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3847 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3848 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3849 /* 0xD0 - 0xD7 */
007a3b54
AK		 3850 G(Src2One | ByteOp, group2), G(Src2One, group2),
3851 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3852 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3853 I(DstAcc | SrcImmUByte | No64, em_aad),
3854 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3855 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3856 /* 0xD8 - 0xDF */
045a282c 3857 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3858 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3859 X3(I(SrcImmByte, em_loop)),
3860 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3861 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3862 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3863 /* 0xE8 - 0xEF */
d4ddafcd 3864 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3865 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3866 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3867 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3868 /* 0xF0 - 0xF7 */
bf608f88 3869 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3870 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3871 G(ByteOp, group3), G(0, group3),
73fba5f4 3872 /* 0xF8 - 0xFF */
f411e6cd
TY		 3873 D(ImplicitOps), D(ImplicitOps),
3874 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3875 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3876};
3877
fd0a0d82 3878static const struct opcode twobyte_table[256] = {
73fba5f4 3879 /* 0x00 - 0x0F */
dee6bb70 3880 G(0, group6), GD(0, &group7), N, N,
b51e974f 3881 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3882 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3883 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3884 N, D(ImplicitOps | ModRM), N, N,
3885 /* 0x10 - 0x1F */
103f98ea
PB		 3886 N, N, N, N, N, N, N, N,
3887 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3888 /* 0x20 - 0x2F */
9b88ae99
NA		 3889 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3890 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3891 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3892 check_cr_write),
3893 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3894 check_dr_write),
73fba5f4 3895 N, N, N, N,
27ce8258
IM		 3896 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3897 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3898 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3899 N, N, N, N,
73fba5f4 3900 /* 0x30 - 0x3F */
e1e210b0 3901 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3902 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3903 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3904 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3905 I(ImplicitOps | EmulateOnUD, em_sysenter),
3906 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3907 N, N,
73fba5f4
AK		 3908 N, N, N, N, N, N, N, N,
3909 /* 0x40 - 0x4F */
140bad89 3910 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3911 /* 0x50 - 0x5F */
3912 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3913 /* 0x60 - 0x6F */
aa97bb48
AK		 3914 N, N, N, N,
3915 N, N, N, N,
3916 N, N, N, N,
3917 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3918 /* 0x70 - 0x7F */
aa97bb48
AK		 3919 N, N, N, N,
3920 N, N, N, N,
3921 N, N, N, N,
3922 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3923 /* 0x80 - 0x8F */
3924 X16(D(SrcImm)),
3925 /* 0x90 - 0x9F */
ee45b58e 3926 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3927 /* 0xA0 - 0xA7 */
1cd196ea 3928 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3929 II(ImplicitOps, em_cpuid, cpuid),
3930 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3931 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3932 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3933 /* 0xA8 - 0xAF */
1cd196ea 3934 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3935 DI(ImplicitOps, rsm),
11c363ba 3936 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3937 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3938 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3939 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3940 /* 0xB0 - 0xB7 */
e940b5c2 3941 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3942 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3943 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3944 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3945 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3946 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3947 /* 0xB8 - 0xBF */
3948 N, N,
ce7faab2 3949 G(BitOp, group8),
11c363ba
AK		 3950 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3951 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3952 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3953 /* 0xC0 - 0xC7 */
e47a5f5f 3954 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3955 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3956 N, N, N, GD(0, &group9),
9299836e
AK		 3957 /* 0xC8 - 0xCF */
3958 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3959 /* 0xD0 - 0xDF */
3960 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3961 /* 0xE0 - 0xEF */
3962 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3963 /* 0xF0 - 0xFF */
3964 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3965};
3966
0bc5eedb 3967static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3968 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3969};
3970
3971static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3972 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3973};
3974
3975/*
3976 * Insns below are selected by the prefix which indexed by the third opcode
3977 * byte.
3978 */
3979static const struct opcode opcode_map_0f_38[256] = {
3980 /* 0x00 - 0x7f */
3981 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3982 /* 0x80 - 0xef */
3983 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3984 /* 0xf0 - 0xf1 */
3985 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3986 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3987 /* 0xf2 - 0xff */
3988 N, N, X4(N), X8(N)
0bc5eedb
BP		 3989};
3990
73fba5f4
AK		 3991#undef D
3992#undef N
3993#undef G
3994#undef GD
3995#undef I
aa97bb48 3996#undef GP
01de8b09 3997#undef EXT
73fba5f4 3998
8d8f4e9f 3999#undef D2bv
f6511935 4000#undef D2bvIP
8d8f4e9f 4001#undef I2bv
d7841a4b 4002#undef I2bvIP
d67fc27a 4003#undef I6ALU
8d8f4e9f 4004
9dac77fa 4005static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4006{
4007 unsigned size;
4008
9dac77fa 4009 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4010 if (size == 8)
4011 size = 4;
4012 return size;
4013}
4014
4015static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4016 unsigned size, bool sign_extension)
4017{
39f21ee5
AK		 4018 int rc = X86EMUL_CONTINUE;
4019
4020 op->type = OP_IMM;
4021 op->bytes = size;
9dac77fa 4022 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4023 /* NB. Immediates are sign-extended as necessary. */
4024 switch (op->bytes) {
4025 case 1:
e85a1085 4026 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4027 break;
4028 case 2:
e85a1085 4029 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4030 break;
4031 case 4:
e85a1085 4032 op->val = insn_fetch(s32, ctxt);
39f21ee5 4033 break;
5e2c6883
NA		 4034 case 8:
4035 op->val = insn_fetch(s64, ctxt);
4036 break;
39f21ee5
AK		 4037 }
4038 if (!sign_extension) {
4039 switch (op->bytes) {
4040 case 1:
4041 op->val &= 0xff;
4042 break;
4043 case 2:
4044 op->val &= 0xffff;
4045 break;
4046 case 4:
4047 op->val &= 0xffffffff;
4048 break;
4049 }
4050 }
4051done:
4052 return rc;
4053}
4054
a9945549
AK		 4055static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4056 unsigned d)
4057{
4058 int rc = X86EMUL_CONTINUE;
4059
4060 switch (d) {
4061 case OpReg:
2adb5ad9 4062 decode_register_operand(ctxt, op);
a9945549
AK		 4063 break;
4064 case OpImmUByte:
608aabe3 4065 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4066 break;
4067 case OpMem:
41ddf978 4068 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4069 mem_common:
4070 *op = ctxt->memop;
4071 ctxt->memopp = op;
96888977 4072 if (ctxt->d & BitOp)
a9945549
AK		 4073 fetch_bit_operand(ctxt);
4074 op->orig_val = op->val;
4075 break;
41ddf978 4076 case OpMem64:
aaa05f24 4077 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4078 goto mem_common;
a9945549
AK		 4079 case OpAcc:
4080 op->type = OP_REG;
4081 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4082 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4083 fetch_register_operand(op);
4084 op->orig_val = op->val;
4085 break;
820207c8
AK		 4086 case OpAccLo:
4087 op->type = OP_REG;
4088 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4089 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4090 fetch_register_operand(op);
4091 op->orig_val = op->val;
4092 break;
4093 case OpAccHi:
4094 if (ctxt->d & ByteOp) {
4095 op->type = OP_NONE;
4096 break;
4097 }
4098 op->type = OP_REG;
4099 op->bytes = ctxt->op_bytes;
4100 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4101 fetch_register_operand(op);
4102 op->orig_val = op->val;
4103 break;
a9945549
AK		 4104 case OpDI:
4105 op->type = OP_MEM;
4106 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4107 op->addr.mem.ea =
dd856efa 4108 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4109 op->addr.mem.seg = VCPU_SREG_ES;
4110 op->val = 0;
b3356bf0 4111 op->count = 1;
a9945549
AK		 4112 break;
4113 case OpDX:
4114 op->type = OP_REG;
4115 op->bytes = 2;
dd856efa 4116 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4117 fetch_register_operand(op);
4118 break;
4dd6a57d
AK		 4119 case OpCL:
4120 op->bytes = 1;
dd856efa 4121 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4122 break;
4123 case OpImmByte:
4124 rc = decode_imm(ctxt, op, 1, true);
4125 break;
4126 case OpOne:
4127 op->bytes = 1;
4128 op->val = 1;
4129 break;
4130 case OpImm:
4131 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4132 break;
5e2c6883
NA		 4133 case OpImm64:
4134 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4135 break;
28867cee
AK		 4136 case OpMem8:
4137 ctxt->memop.bytes = 1;
660696d1 4138 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4139 ctxt->memop.addr.reg = decode_register(ctxt,
4140 ctxt->modrm_rm, true);
660696d1
GN		 4141 fetch_register_operand(&ctxt->memop);
4142 }
28867cee 4143 goto mem_common;
0fe59128
AK		 4144 case OpMem16:
4145 ctxt->memop.bytes = 2;
4146 goto mem_common;
4147 case OpMem32:
4148 ctxt->memop.bytes = 4;
4149 goto mem_common;
4150 case OpImmU16:
4151 rc = decode_imm(ctxt, op, 2, false);
4152 break;
4153 case OpImmU:
4154 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4155 break;
4156 case OpSI:
4157 op->type = OP_MEM;
4158 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4159 op->addr.mem.ea =
dd856efa 4160 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4161 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4162 op->val = 0;
b3356bf0 4163 op->count = 1;
0fe59128 4164 break;
7fa57952
PB		 4165 case OpXLat:
4166 op->type = OP_MEM;
4167 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4168 op->addr.mem.ea =
4169 register_address(ctxt,
4170 reg_read(ctxt, VCPU_REGS_RBX) +
4171 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4172 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4173 op->val = 0;
4174 break;
0fe59128
AK		 4175 case OpImmFAddr:
4176 op->type = OP_IMM;
4177 op->addr.mem.ea = ctxt->_eip;
4178 op->bytes = ctxt->op_bytes + 2;
4179 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4180 break;
4181 case OpMemFAddr:
4182 ctxt->memop.bytes = ctxt->op_bytes + 2;
4183 goto mem_common;
c191a7a0
AK		 4184 case OpES:
4185 op->val = VCPU_SREG_ES;
4186 break;
4187 case OpCS:
4188 op->val = VCPU_SREG_CS;
4189 break;
4190 case OpSS:
4191 op->val = VCPU_SREG_SS;
4192 break;
4193 case OpDS:
4194 op->val = VCPU_SREG_DS;
4195 break;
4196 case OpFS:
4197 op->val = VCPU_SREG_FS;
4198 break;
4199 case OpGS:
4200 op->val = VCPU_SREG_GS;
4201 break;
a9945549
AK		 4202 case OpImplicit:
4203 /* Special instructions do their own operand decoding. */
4204 default:
4205 op->type = OP_NONE; /* Disable writeback. */
4206 break;
4207 }
4208
4209done:
4210 return rc;
4211}
4212
ef5d75cc 4213int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4214{
dde7e6d1
AK		 4215 int rc = X86EMUL_CONTINUE;
4216 int mode = ctxt->mode;
46561646 4217 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4218 bool op_prefix = false;
573e80fe 4219 bool has_seg_override = false;
46561646 4220 struct opcode opcode;
dde7e6d1 4221
f09ed83e
AK		 4222 ctxt->memop.type = OP_NONE;
4223 ctxt->memopp = NULL;
9dac77fa
AK		 4224 ctxt->_eip = ctxt->eip;
4225 ctxt->fetch.start = ctxt->_eip;
4226 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4227 ctxt->opcode_len = 1;
dc25e89e 4228 if (insn_len > 0)
9dac77fa 4229 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4230
4231 switch (mode) {
4232 case X86EMUL_MODE_REAL:
4233 case X86EMUL_MODE_VM86:
4234 case X86EMUL_MODE_PROT16:
4235 def_op_bytes = def_ad_bytes = 2;
4236 break;
4237 case X86EMUL_MODE_PROT32:
4238 def_op_bytes = def_ad_bytes = 4;
4239 break;
4240#ifdef CONFIG_X86_64
4241 case X86EMUL_MODE_PROT64:
4242 def_op_bytes = 4;
4243 def_ad_bytes = 8;
4244 break;
4245#endif
4246 default:
1d2887e2 4247 return EMULATION_FAILED;
dde7e6d1
AK		 4248 }
4249
9dac77fa
AK		 4250 ctxt->op_bytes = def_op_bytes;
4251 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4252
4253 /* Legacy prefixes. */
4254 for (;;) {
e85a1085 4255 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4256 case 0x66: /* operand-size override */
0d7cdee8 4257 op_prefix = true;
dde7e6d1 4258 /* switch between 2/4 bytes */
9dac77fa 4259 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4260 break;
4261 case 0x67: /* address-size override */
4262 if (mode == X86EMUL_MODE_PROT64)
4263 /* switch between 4/8 bytes */
9dac77fa 4264 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4265 else
4266 /* switch between 2/4 bytes */
9dac77fa 4267 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4268 break;
4269 case 0x26: /* ES override */
4270 case 0x2e: /* CS override */
4271 case 0x36: /* SS override */
4272 case 0x3e: /* DS override */
573e80fe
BD		 4273 has_seg_override = true;
4274 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4275 break;
4276 case 0x64: /* FS override */
4277 case 0x65: /* GS override */
573e80fe
BD		 4278 has_seg_override = true;
4279 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4280 break;
4281 case 0x40 ... 0x4f: /* REX */
4282 if (mode != X86EMUL_MODE_PROT64)
4283 goto done_prefixes;
9dac77fa 4284 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4285 continue;
4286 case 0xf0: /* LOCK */
9dac77fa 4287 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4288 break;
4289 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4290 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4291 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4292 break;
4293 default:
4294 goto done_prefixes;
4295 }
4296
4297 /* Any legacy prefix after a REX prefix nullifies its effect. */
4298
9dac77fa 4299 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4300 }
4301
4302done_prefixes:
4303
4304 /* REX prefix. */
9dac77fa
AK		 4305 if (ctxt->rex_prefix & 8)
4306 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4307
4308 /* Opcode byte(s). */
9dac77fa 4309 opcode = opcode_table[ctxt->b];
d3ad6243 4310 /* Two-byte opcode? */
9dac77fa 4311 if (ctxt->b == 0x0f) {
1ce19dc1 4312 ctxt->opcode_len = 2;
e85a1085 4313 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4314 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4315
4316 /* 0F_38 opcode map */
4317 if (ctxt->b == 0x38) {
4318 ctxt->opcode_len = 3;
4319 ctxt->b = insn_fetch(u8, ctxt);
4320 opcode = opcode_map_0f_38[ctxt->b];
4321 }
dde7e6d1 4322 }
9dac77fa 4323 ctxt->d = opcode.flags;
dde7e6d1 4324
9f4260e7
TY		 4325 if (ctxt->d & ModRM)
4326 ctxt->modrm = insn_fetch(u8, ctxt);
4327
7fe864dc
NA		 4328 /* vex-prefix instructions are not implemented */
4329 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4330 (mode == X86EMUL_MODE_PROT64 ||
4331 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4332 ctxt->d = NotImpl;
4333 }
4334
9dac77fa
AK		 4335 while (ctxt->d & GroupMask) {
4336 switch (ctxt->d & GroupMask) {
46561646 4337 case Group:
9dac77fa 4338 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4339 opcode = opcode.u.group[goffset];
4340 break;
4341 case GroupDual:
9dac77fa
AK		 4342 goffset = (ctxt->modrm >> 3) & 7;
4343 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4344 opcode = opcode.u.gdual->mod3[goffset];
4345 else
4346 opcode = opcode.u.gdual->mod012[goffset];
4347 break;
4348 case RMExt:
9dac77fa 4349 goffset = ctxt->modrm & 7;
01de8b09 4350 opcode = opcode.u.group[goffset];
46561646
AK		 4351 break;
4352 case Prefix:
9dac77fa 4353 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4354 return EMULATION_FAILED;
9dac77fa 4355 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4356 switch (simd_prefix) {
4357 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4358 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4359 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4360 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4361 }
4362 break;
045a282c
GN		 4363 case Escape:
4364 if (ctxt->modrm > 0xbf)
4365 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4366 else
4367 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4368 break;
46561646 4369 default:
1d2887e2 4370 return EMULATION_FAILED;
0d7cdee8 4371 }
46561646 4372
b1ea50b2 4373 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4374 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4375 }
4376
e24186e0
PB		 4377 /* Unrecognised? */
4378 if (ctxt->d == 0)
4379 return EMULATION_FAILED;
4380
9dac77fa 4381 ctxt->execute = opcode.u.execute;
dde7e6d1 4382
d40a6898
PB		 4383 if (unlikely(ctxt->d &
4384 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4385 /*
4386 * These are copied unconditionally here, and checked unconditionally
4387 * in x86_emulate_insn.
4388 */
4389 ctxt->check_perm = opcode.check_perm;
4390 ctxt->intercept = opcode.intercept;
dde7e6d1 4391
d40a6898
PB		 4392 if (ctxt->d & NotImpl)
4393 return EMULATION_FAILED;
d867162c 4394
d40a6898
PB		 4395 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4396 return EMULATION_FAILED;
dde7e6d1 4397
d40a6898 4398 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4399 ctxt->op_bytes = 8;
7f9b4b75 4400
d40a6898
PB		 4401 if (ctxt->d & Op3264) {
4402 if (mode == X86EMUL_MODE_PROT64)
4403 ctxt->op_bytes = 8;
4404 else
4405 ctxt->op_bytes = 4;
4406 }
4407
4408 if (ctxt->d & Sse)
4409 ctxt->op_bytes = 16;
4410 else if (ctxt->d & Mmx)
4411 ctxt->op_bytes = 8;
4412 }
1253791d 4413
dde7e6d1 4414 /* ModRM and SIB bytes. */
9dac77fa 4415 if (ctxt->d & ModRM) {
f09ed83e 4416 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4417 if (!has_seg_override) {
4418 has_seg_override = true;
4419 ctxt->seg_override = ctxt->modrm_seg;
4420 }
9dac77fa 4421 } else if (ctxt->d & MemAbs)
f09ed83e 4422 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4423 if (rc != X86EMUL_CONTINUE)
4424 goto done;
4425
573e80fe
BD		 4426 if (!has_seg_override)
4427 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4428
573e80fe 4429 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4430
dde7e6d1
AK		 4431 /*
4432 * Decode and fetch the source operand: register, memory
4433 * or immediate.
4434 */
0fe59128 4435 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4436 if (rc != X86EMUL_CONTINUE)
4437 goto done;
4438
dde7e6d1
AK		 4439 /*
4440 * Decode and fetch the second source operand: register, memory
4441 * or immediate.
4442 */
4dd6a57d 4443 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4444 if (rc != X86EMUL_CONTINUE)
4445 goto done;
4446
dde7e6d1 4447 /* Decode and fetch the destination operand: register or memory. */
a9945549 4448 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4449
4450done:
41061cdb 4451 if (ctxt->rip_relative)
f09ed83e 4452 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4453
1d2887e2 4454 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4455}
4456
1cb3f3ae
XG		 4457bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4458{
4459 return ctxt->d & PageTable;
4460}
4461
3e2f65d5
GN		 4462static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4463{
3e2f65d5
GN		 4464 /* The second termination condition only applies for REPE
4465 * and REPNE. Test if the repeat string operation prefix is
4466 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4467 * corresponding termination condition according to:
4468 * - if REPE/REPZ and ZF = 0 then done
4469 * - if REPNE/REPNZ and ZF = 1 then done
4470 */
9dac77fa
AK		 4471 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4472 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4473 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4474 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4475 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4476 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4477 return true;
4478
4479 return false;
4480}
4481
cbe2c9d3
AK		 4482static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4483{
4484 bool fault = false;
4485
4486 ctxt->ops->get_fpu(ctxt);
4487 asm volatile("1: fwait \n\t"
4488 "2: \n\t"
4489 ".pushsection .fixup,\"ax\" \n\t"
4490 "3: \n\t"
4491 "movb $1, %[fault] \n\t"
4492 "jmp 2b \n\t"
4493 ".popsection \n\t"
4494 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4495 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4496 ctxt->ops->put_fpu(ctxt);
4497
4498 if (unlikely(fault))
4499 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4500
4501 return X86EMUL_CONTINUE;
4502}
4503
4504static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4505 struct operand *op)
4506{
4507 if (op->type == OP_MM)
4508 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4509}
4510
e28bbd44
AK		 4511static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4512{
4513 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4514 if (!(ctxt->d & ByteOp))
4515 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4516 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4517 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4518 [fastop]"+S"(fop)
4519 : "c"(ctxt->src2.val));
e28bbd44 4520 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4521 if (!fop) /* exception is returned in fop variable */
4522 return emulate_de(ctxt);
e28bbd44
AK		 4523 return X86EMUL_CONTINUE;
4524}
dd856efa 4525
1498507a
BD		 4526void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4527{
573e80fe
BD		 4528 memset(&ctxt->rip_relative, 0,
4529 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4530
1498507a
BD		 4531 ctxt->io_read.pos = 0;
4532 ctxt->io_read.end = 0;
1498507a
BD		 4533 ctxt->mem_read.end = 0;
4534}
4535
7b105ca2 4536int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4537{
0225fb50 4538 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4539 int rc = X86EMUL_CONTINUE;
9dac77fa 4540 int saved_dst_type = ctxt->dst.type;
8b4caf66 4541
9dac77fa 4542 ctxt->mem_read.pos = 0;
310b5d30 4543
e24186e0
PB		 4544 /* LOCK prefix is allowed only with some instructions */
4545 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4546 rc = emulate_ud(ctxt);
1161624f
GN		 4547 goto done;
4548 }
4549
e24186e0 4550 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4551 rc = emulate_ud(ctxt);
d380a5e4
GN		 4552 goto done;
4553 }
4554
d40a6898
PB		 4555 if (unlikely(ctxt->d &
4556 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4557 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4558 (ctxt->d & Undefined)) {
4559 rc = emulate_ud(ctxt);
4560 goto done;
4561 }
1253791d 4562
d40a6898
PB		 4563 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4564 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4565 rc = emulate_ud(ctxt);
cbe2c9d3 4566 goto done;
d40a6898 4567 }
cbe2c9d3 4568
d40a6898
PB		 4569 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4570 rc = emulate_nm(ctxt);
c4f035c6 4571 goto done;
d40a6898 4572 }
c4f035c6 4573
d40a6898
PB		 4574 if (ctxt->d & Mmx) {
4575 rc = flush_pending_x87_faults(ctxt);
4576 if (rc != X86EMUL_CONTINUE)
4577 goto done;
4578 /*
4579 * Now that we know the fpu is exception safe, we can fetch
4580 * operands from it.
4581 */
4582 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4583 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4584 if (!(ctxt->d & Mov))
4585 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4586 }
e92805ac 4587
685bbf4a 4588 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4589 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4590 X86_ICPT_PRE_EXCEPT);
4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593 }
8ea7d6ae 4594
d40a6898
PB		 4595 /* Privileged instruction can be executed only in CPL=0 */
4596 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4597 rc = emulate_gp(ctxt, 0);
d09beabd 4598 goto done;
d40a6898 4599 }
d09beabd 4600
d40a6898
PB		 4601 /* Instruction can only be executed in protected mode */
4602 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4603 rc = emulate_ud(ctxt);
c4f035c6 4604 goto done;
d40a6898 4605 }
c4f035c6 4606
d40a6898 4607 /* Do instruction specific permission checks */
685bbf4a 4608 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4609 rc = ctxt->check_perm(ctxt);
4610 if (rc != X86EMUL_CONTINUE)
4611 goto done;
4612 }
4613
685bbf4a 4614 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4615 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4616 X86_ICPT_POST_EXCEPT);
4617 if (rc != X86EMUL_CONTINUE)
4618 goto done;
4619 }
4620
4621 if (ctxt->rep_prefix && (ctxt->d & String)) {
4622 /* All REP prefixes have the same first termination condition */
4623 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4624 ctxt->eip = ctxt->_eip;
4625 goto done;
4626 }
b9fa9d6b 4627 }
b9fa9d6b
AK		 4628 }
4629
9dac77fa
AK		 4630 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4631 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4632 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4633 if (rc != X86EMUL_CONTINUE)
8b4caf66 4634 goto done;
9dac77fa 4635 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4636 }
4637
9dac77fa
AK		 4638 if (ctxt->src2.type == OP_MEM) {
4639 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4640 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4641 if (rc != X86EMUL_CONTINUE)
4642 goto done;
4643 }
4644
9dac77fa 4645 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4646 goto special_insn;
4647
4648
9dac77fa 4649 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4650 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4651 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4652 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4653 if (rc != X86EMUL_CONTINUE)
4654 goto done;
038e51de 4655 }
9dac77fa 4656 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4657
018a98db
AK		 4658special_insn:
4659
685bbf4a 4660 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4661 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4662 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4663 if (rc != X86EMUL_CONTINUE)
4664 goto done;
4665 }
4666
9dac77fa 4667 if (ctxt->execute) {
e28bbd44
AK		 4668 if (ctxt->d & Fastop) {
4669 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4670 rc = fastop(ctxt, fop);
4671 if (rc != X86EMUL_CONTINUE)
4672 goto done;
4673 goto writeback;
4674 }
9dac77fa 4675 rc = ctxt->execute(ctxt);
ef65c889
AK		 4676 if (rc != X86EMUL_CONTINUE)
4677 goto done;
4678 goto writeback;
4679 }
4680
1ce19dc1 4681 if (ctxt->opcode_len == 2)
6aa8b732 4682 goto twobyte_insn;
0bc5eedb
BP		 4683 else if (ctxt->opcode_len == 3)
4684 goto threebyte_insn;
6aa8b732 4685
9dac77fa 4686 switch (ctxt->b) {
6aa8b732 4687 case 0x63: /* movsxd */
8b4caf66 4688 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4689 goto cannot_emulate;
9dac77fa 4690 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4691 break;
b2833e3c 4692 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4693 if (test_cc(ctxt->b, ctxt->eflags))
4694 jmp_rel(ctxt, ctxt->src.val);
018a98db 4695 break;
7e0b54b1 4696 case 0x8d: /* lea r16/r32, m */
9dac77fa 4697 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4698 break;
3d9e77df 4699 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4700 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4701 ctxt->dst.type = OP_NONE;
4702 else
4703 rc = em_xchg(ctxt);
e4f973ae 4704 break;
e8b6fa70 4705 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4706 switch (ctxt->op_bytes) {
4707 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4708 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4709 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4710 }
4711 break;
6e154e56 4712 case 0xcc: /* int3 */
5c5df76b
TY		 4713 rc = emulate_int(ctxt, 3);
4714 break;
6e154e56 4715 case 0xcd: /* int n */
9dac77fa 4716 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4717 break;
4718 case 0xce: /* into */
5c5df76b
TY		 4719 if (ctxt->eflags & EFLG_OF)
4720 rc = emulate_int(ctxt, 4);
6e154e56 4721 break;
1a52e051 4722 case 0xe9: /* jmp rel */
db5b0762 4723 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4724 jmp_rel(ctxt, ctxt->src.val);
4725 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4726 break;
111de5d6 4727 case 0xf4: /* hlt */
6c3287f7 4728 ctxt->ops->halt(ctxt);
19fdfa0d 4729 break;
111de5d6
AK		 4730 case 0xf5: /* cmc */
4731 /* complement carry flag from eflags reg */
4732 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4733 break;
4734 case 0xf8: /* clc */
4735 ctxt->eflags &= ~EFLG_CF;
111de5d6 4736 break;
8744aa9a
MG		 4737 case 0xf9: /* stc */
4738 ctxt->eflags |= EFLG_CF;
4739 break;
fb4616f4
MG		 4740 case 0xfc: /* cld */
4741 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4742 break;
4743 case 0xfd: /* std */
4744 ctxt->eflags |= EFLG_DF;
fb4616f4 4745 break;
91269b8f
AK		 4746 default:
4747 goto cannot_emulate;
6aa8b732 4748 }
018a98db 4749
7d9ddaed
AK		 4750 if (rc != X86EMUL_CONTINUE)
4751 goto done;
4752
018a98db 4753writeback:
fb32b1ed
AK		 4754 if (ctxt->d & SrcWrite) {
4755 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4756 rc = writeback(ctxt, &ctxt->src);
4757 if (rc != X86EMUL_CONTINUE)
4758 goto done;
4759 }
ee212297
NA		 4760 if (!(ctxt->d & NoWrite)) {
4761 rc = writeback(ctxt, &ctxt->dst);
4762 if (rc != X86EMUL_CONTINUE)
4763 goto done;
4764 }
018a98db 4765
5cd21917
GN		 4766 /*
4767 * restore dst type in case the decoding will be reused
4768 * (happens for string instruction )
4769 */
9dac77fa 4770 ctxt->dst.type = saved_dst_type;
5cd21917 4771
9dac77fa 4772 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4773 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4774
9dac77fa 4775 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4776 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4777
9dac77fa 4778 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4779 unsigned int count;
9dac77fa 4780 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4781 if ((ctxt->d & SrcMask) == SrcSI)
4782 count = ctxt->src.count;
4783 else
4784 count = ctxt->dst.count;
4785 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4786 -count);
3e2f65d5 4787
d2ddd1c4
GN		 4788 if (!string_insn_completed(ctxt)) {
4789 /*
4790 * Re-enter guest when pio read ahead buffer is empty
4791 * or, if it is not used, after each 1024 iteration.
4792 */
dd856efa 4793 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4794 (r->end == 0 || r->end != r->pos)) {
4795 /*
4796 * Reset read cache. Usually happens before
4797 * decode, but since instruction is restarted
4798 * we have to do it here.
4799 */
9dac77fa 4800 ctxt->mem_read.end = 0;
dd856efa 4801 writeback_registers(ctxt);
d2ddd1c4
GN		 4802 return EMULATION_RESTART;
4803 }
4804 goto done; /* skip rip writeback */
0fa6ccbd 4805 }
5cd21917 4806 }
d2ddd1c4 4807
9dac77fa 4808 ctxt->eip = ctxt->_eip;
018a98db
AK		 4809
4810done:
da9cb575
AK		 4811 if (rc == X86EMUL_PROPAGATE_FAULT)
4812 ctxt->have_exception = true;
775fde86
JR		 4813 if (rc == X86EMUL_INTERCEPTED)
4814 return EMULATION_INTERCEPTED;
4815
dd856efa
AK		 4816 if (rc == X86EMUL_CONTINUE)
4817 writeback_registers(ctxt);
4818
d2ddd1c4 4819 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4820
4821twobyte_insn:
9dac77fa 4822 switch (ctxt->b) {
018a98db 4823 case 0x09: /* wbinvd */
cfb22375 4824 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4825 break;
4826 case 0x08: /* invd */
018a98db
AK		 4827 case 0x0d: /* GrpP (prefetch) */
4828 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4829 case 0x1f: /* nop */
018a98db
AK		 4830 break;
4831 case 0x20: /* mov cr, reg */
9dac77fa 4832 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4833 break;
6aa8b732 4834 case 0x21: /* mov from dr to reg */
9dac77fa 4835 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4836 break;
6aa8b732 4837 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4838 if (test_cc(ctxt->b, ctxt->eflags))
4839 ctxt->dst.val = ctxt->src.val;
4840 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4841 ctxt->op_bytes != 4)
9dac77fa 4842 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4843 break;
b2833e3c 4844 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4845 if (test_cc(ctxt->b, ctxt->eflags))
4846 jmp_rel(ctxt, ctxt->src.val);
018a98db 4847 break;
ee45b58e 4848 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4849 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4850 break;
2a7c5b8b
GC		 4851 case 0xae: /* clflush */
4852 break;
6aa8b732 4853 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4854 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4855 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4856 : (u16) ctxt->src.val;
6aa8b732 4857 break;
6aa8b732 4858 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4859 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4860 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4861 (s16) ctxt->src.val;
6aa8b732 4862 break;
a012e65a 4863 case 0xc3: /* movnti */
9dac77fa 4864 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4865 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4866 (u32) ctxt->src.val;
a012e65a 4867 break;
91269b8f
AK		 4868 default:
4869 goto cannot_emulate;
6aa8b732 4870 }
7d9ddaed 4871
0bc5eedb
BP		 4872threebyte_insn:
4873
7d9ddaed
AK		 4874 if (rc != X86EMUL_CONTINUE)
4875 goto done;
4876
6aa8b732
AK		 4877 goto writeback;
4878
4879cannot_emulate:
a0c0ab2f 4880 return EMULATION_FAILED;
6aa8b732 4881}
dd856efa
AK		 4882
4883void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4884{
4885 invalidate_registers(ctxt);
4886}
4887
4888void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4889{
4890 writeback_registers(ctxt);
4891}
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