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KVM: x86 emulator: qualify OpReg inhibit_byte_regs hack
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
a9945549
AK		 47
48#define OpBits 4 /* Width of operand field */
b1ea50b2 49#define OpMask ((1ull << OpBits) - 1)
a9945549 50
6aa8b732
AK		 51/*
52 * Opcode effective-address decode tables.
53 * Note that we only emulate instructions that have at least one memory
54 * operand (excluding implicit stack references). We assume that stack
55 * references and instruction fetches will never occur in special memory
56 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
57 * not be handled.
58 */
59
60/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 61#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 62/* Destination operand type. */
a9945549
AK		 63#define DstShift 1
64#define ImplicitOps (OpImplicit << DstShift)
65#define DstReg (OpReg << DstShift)
66#define DstMem (OpMem << DstShift)
67#define DstAcc (OpAcc << DstShift)
68#define DstDI (OpDI << DstShift)
69#define DstMem64 (OpMem64 << DstShift)
70#define DstImmUByte (OpImmUByte << DstShift)
71#define DstDX (OpDX << DstShift)
72#define DstMask (OpMask << DstShift)
6aa8b732 73/* Source operand type. */
221192bd
MT		 74#define SrcNone (0<<5) /* No source operand. */
75#define SrcReg (1<<5) /* Register operand. */
76#define SrcMem (2<<5) /* Memory operand. */
77#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
78#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
79#define SrcImm (5<<5) /* Immediate operand. */
80#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
81#define SrcOne (7<<5) /* Implied '1' */
82#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
83#define SrcImmU (9<<5) /* Immediate operand, unsigned */
84#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
85#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
86#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
87#define SrcAcc (0xd<<5) /* Source Accumulator */
88#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
89#define SrcDX (0xf<<5) /* Source is in DX register */
90#define SrcMask (0xf<<5)
221192bd
MT		 91#define BitOp (1<<11)
92#define MemAbs (1<<12) /* Memory operand is absolute displacement */
93#define String (1<<13) /* String instruction (rep capable) */
94#define Stack (1<<14) /* Stack instruction (push/pop) */
95#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
96#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
97#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
98#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
99#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
100#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 101/* Generic ModRM decode. */
102#define ModRM (1<<19)
103/* Destination is only written; never read. */
104#define Mov (1<<20)
d8769fed 105/* Misc flags */
8ea7d6ae 106#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 107#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 108#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 109#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 110#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 111#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 112#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 113#define No64 (1<<28)
0dc8d10f 114/* Source 2 operand type */
4dd6a57d
AK		 115#define Src2Shift (29)
116#define Src2None (OpNone << Src2Shift)
117#define Src2CL (OpCL << Src2Shift)
118#define Src2ImmByte (OpImmByte << Src2Shift)
119#define Src2One (OpOne << Src2Shift)
120#define Src2Imm (OpImm << Src2Shift)
121#define Src2Mask (OpMask << Src2Shift)
6aa8b732 122
d0e53325
AK		 123#define X2(x...) x, x
124#define X3(x...) X2(x), x
125#define X4(x...) X2(x), X2(x)
126#define X5(x...) X4(x), x
127#define X6(x...) X4(x), X2(x)
128#define X7(x...) X4(x), X3(x)
129#define X8(x...) X4(x), X4(x)
130#define X16(x...) X8(x), X8(x)
83babbca 131
d65b1dee 132struct opcode {
b1ea50b2
AK		 133 u64 flags : 56;
134 u64 intercept : 8;
120df890 135 union {
ef65c889 136 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 137 struct opcode *group;
138 struct group_dual *gdual;
0d7cdee8 139 struct gprefix *gprefix;
120df890 140 } u;
d09beabd 141 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 142};
143
144struct group_dual {
145 struct opcode mod012[8];
146 struct opcode mod3[8];
d65b1dee
AK		 147};
148
0d7cdee8
AK		 149struct gprefix {
150 struct opcode pfx_no;
151 struct opcode pfx_66;
152 struct opcode pfx_f2;
153 struct opcode pfx_f3;
154};
155
6aa8b732 156/* EFLAGS bit definitions. */
d4c6a154
GN		 157#define EFLG_ID (1<<21)
158#define EFLG_VIP (1<<20)
159#define EFLG_VIF (1<<19)
160#define EFLG_AC (1<<18)
b1d86143
AP		 161#define EFLG_VM (1<<17)
162#define EFLG_RF (1<<16)
d4c6a154
GN		 163#define EFLG_IOPL (3<<12)
164#define EFLG_NT (1<<14)
6aa8b732
AK		 165#define EFLG_OF (1<<11)
166#define EFLG_DF (1<<10)
b1d86143 167#define EFLG_IF (1<<9)
d4c6a154 168#define EFLG_TF (1<<8)
6aa8b732
AK		 169#define EFLG_SF (1<<7)
170#define EFLG_ZF (1<<6)
171#define EFLG_AF (1<<4)
172#define EFLG_PF (1<<2)
173#define EFLG_CF (1<<0)
174
62bd430e
MG		 175#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
176#define EFLG_RESERVED_ONE_MASK 2
177
6aa8b732
AK		 178/*
179 * Instruction emulation:
180 * Most instructions are emulated directly via a fragment of inline assembly
181 * code. This allows us to save/restore EFLAGS and thus very easily pick up
182 * any modified flags.
183 */
184
05b3e0c2 185#if defined(CONFIG_X86_64)
6aa8b732
AK		 186#define _LO32 "k" /* force 32-bit operand */
187#define _STK "%%rsp" /* stack pointer */
188#elif defined(__i386__)
189#define _LO32 "" /* force 32-bit operand */
190#define _STK "%%esp" /* stack pointer */
191#endif
192
193/*
194 * These EFLAGS bits are restored from saved value during emulation, and
195 * any changes are written back to the saved value after emulation.
196 */
197#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
198
199/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 200#define _PRE_EFLAGS(_sav, _msk, _tmp) \
201 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
202 "movl %"_sav",%"_LO32 _tmp"; " \
203 "push %"_tmp"; " \
204 "push %"_tmp"; " \
205 "movl %"_msk",%"_LO32 _tmp"; " \
206 "andl %"_LO32 _tmp",("_STK"); " \
207 "pushf; " \
208 "notl %"_LO32 _tmp"; " \
209 "andl %"_LO32 _tmp",("_STK"); " \
210 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
211 "pop %"_tmp"; " \
212 "orl %"_LO32 _tmp",("_STK"); " \
213 "popf; " \
214 "pop %"_sav"; "
6aa8b732
AK		 215
216/* After executing instruction: write-back necessary bits in EFLAGS. */
217#define _POST_EFLAGS(_sav, _msk, _tmp) \
218 /* _sav |= EFLAGS & _msk; */ \
219 "pushf; " \
220 "pop %"_tmp"; " \
221 "andl %"_msk",%"_LO32 _tmp"; " \
222 "orl %"_LO32 _tmp",%"_sav"; "
223
dda96d8f
AK		 224#ifdef CONFIG_X86_64
225#define ON64(x) x
226#else
227#define ON64(x)
228#endif
229
a31b9cea 230#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 231 do { \
232 __asm__ __volatile__ ( \
233 _PRE_EFLAGS("0", "4", "2") \
234 _op _suffix " %"_x"3,%1; " \
235 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 236 : "=m" ((ctxt)->eflags), \
237 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 238 "=&r" (_tmp) \
a31b9cea 239 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 240 } while (0)
6b7ad61f
AK		 241
242
6aa8b732 243/* Raw emulation: instruction has two explicit operands. */
a31b9cea 244#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 245 do { \
246 unsigned long _tmp; \
247 \
a31b9cea 248 switch ((ctxt)->dst.bytes) { \
6b7ad61f 249 case 2: \
a31b9cea 250 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 251 break; \
252 case 4: \
a31b9cea 253 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 254 break; \
255 case 8: \
a31b9cea 256 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 257 break; \
258 } \
6aa8b732
AK		 259 } while (0)
260
a31b9cea 261#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 262 do { \
6b7ad61f 263 unsigned long _tmp; \
a31b9cea 264 switch ((ctxt)->dst.bytes) { \
6aa8b732 265 case 1: \
a31b9cea 266 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 267 break; \
268 default: \
a31b9cea 269 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 270 _wx, _wy, _lx, _ly, _qx, _qy); \
271 break; \
272 } \
273 } while (0)
274
275/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 276#define emulate_2op_SrcB(ctxt, _op) \
277 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 278
279/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 280#define emulate_2op_SrcV(ctxt, _op) \
281 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 282
283/* Source operand is word, long or quad sized. */
a31b9cea
AK		 284#define emulate_2op_SrcV_nobyte(ctxt, _op) \
285 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 286
d175226a 287/* Instruction has three operands and one operand is stored in ECX register */
29053a60 288#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 289 do { \
290 unsigned long _tmp; \
761441b9
AK		 291 _type _clv = (ctxt)->src2.val; \
292 _type _srcv = (ctxt)->src.val; \
293 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 294 \
295 __asm__ __volatile__ ( \
296 _PRE_EFLAGS("0", "5", "2") \
297 _op _suffix " %4,%1 \n" \
298 _POST_EFLAGS("0", "5", "2") \
761441b9 299 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 300 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
301 ); \
302 \
761441b9
AK		 303 (ctxt)->src2.val = (unsigned long) _clv; \
304 (ctxt)->src2.val = (unsigned long) _srcv; \
305 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 306 } while (0)
307
761441b9 308#define emulate_2op_cl(ctxt, _op) \
7295261c 309 do { \
761441b9 310 switch ((ctxt)->dst.bytes) { \
7295261c 311 case 2: \
29053a60 312 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 313 break; \
314 case 4: \
29053a60 315 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 316 break; \
317 case 8: \
29053a60 318 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 319 break; \
320 } \
d175226a
GT		 321 } while (0)
322
d1eef45d 323#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 324 do { \
325 unsigned long _tmp; \
326 \
dda96d8f
AK		 327 __asm__ __volatile__ ( \
328 _PRE_EFLAGS("0", "3", "2") \
329 _op _suffix " %1; " \
330 _POST_EFLAGS("0", "3", "2") \
d1eef45d 331 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 332 "=&r" (_tmp) \
333 : "i" (EFLAGS_MASK)); \
334 } while (0)
335
336/* Instruction has only one explicit operand (no source operand). */
d1eef45d 337#define emulate_1op(ctxt, _op) \
dda96d8f 338 do { \
d1eef45d
AK		 339 switch ((ctxt)->dst.bytes) { \
340 case 1: __emulate_1op(ctxt, _op, "b"); break; \
341 case 2: __emulate_1op(ctxt, _op, "w"); break; \
342 case 4: __emulate_1op(ctxt, _op, "l"); break; \
343 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 344 } \
345 } while (0)
346
e8f2b1d6 347#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 348 do { \
349 unsigned long _tmp; \
e8f2b1d6
AK		 350 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
351 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 352 \
353 __asm__ __volatile__ ( \
354 _PRE_EFLAGS("0", "5", "1") \
355 "1: \n\t" \
356 _op _suffix " %6; " \
357 "2: \n\t" \
358 _POST_EFLAGS("0", "5", "1") \
359 ".pushsection .fixup,\"ax\" \n\t" \
360 "3: movb $1, %4 \n\t" \
361 "jmp 2b \n\t" \
362 ".popsection \n\t" \
363 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 364 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
365 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
366 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
367 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 368 } while (0)
369
3f9f53b0 370/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 371#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 372 do { \
e8f2b1d6 373 switch((ctxt)->src.bytes) { \
7295261c 374 case 1: \
e8f2b1d6 375 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 376 break; \
377 case 2: \
e8f2b1d6 378 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 379 break; \
380 case 4: \
e8f2b1d6 381 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 382 break; \
383 case 8: ON64( \
e8f2b1d6 384 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 385 break; \
386 } \
387 } while (0)
388
8a76d7f2
JR		 389static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
390 enum x86_intercept intercept,
391 enum x86_intercept_stage stage)
392{
393 struct x86_instruction_info info = {
394 .intercept = intercept,
9dac77fa
AK		 395 .rep_prefix = ctxt->rep_prefix,
396 .modrm_mod = ctxt->modrm_mod,
397 .modrm_reg = ctxt->modrm_reg,
398 .modrm_rm = ctxt->modrm_rm,
399 .src_val = ctxt->src.val64,
400 .src_bytes = ctxt->src.bytes,
401 .dst_bytes = ctxt->dst.bytes,
402 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 403 .next_rip = ctxt->eip,
404 };
405
2953538e 406 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 407}
408
9dac77fa 409static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 410{
9dac77fa 411 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 412}
413
6aa8b732 414/* Access/update address held in a register, based on addressing mode. */
e4706772 415static inline unsigned long
9dac77fa 416address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 417{
9dac77fa 418 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 419 return reg;
420 else
9dac77fa 421 return reg & ad_mask(ctxt);
e4706772
HH		 422}
423
424static inline unsigned long
9dac77fa 425register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 426{
9dac77fa 427 return address_mask(ctxt, reg);
e4706772
HH		 428}
429
7a957275 430static inline void
9dac77fa 431register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 432{
9dac77fa 433 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 434 *reg += inc;
435 else
9dac77fa 436 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 437}
6aa8b732 438
9dac77fa 439static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 440{
9dac77fa 441 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 442}
098c937b 443
56697687
AK		 444static u32 desc_limit_scaled(struct desc_struct *desc)
445{
446 u32 limit = get_desc_limit(desc);
447
448 return desc->g ? (limit << 12) | 0xfff : limit;
449}
450
9dac77fa 451static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 452{
9dac77fa
AK		 453 ctxt->has_seg_override = true;
454 ctxt->seg_override = seg;
7a5b56df
AK		 455}
456
7b105ca2 457static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 458{
459 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
460 return 0;
461
7b105ca2 462 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 463}
464
9dac77fa 465static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 466{
9dac77fa 467 if (!ctxt->has_seg_override)
7a5b56df
AK		 468 return 0;
469
9dac77fa 470 return ctxt->seg_override;
7a5b56df
AK		 471}
472
35d3d4a1
AK		 473static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
474 u32 error, bool valid)
54b8486f 475{
da9cb575
AK		 476 ctxt->exception.vector = vec;
477 ctxt->exception.error_code = error;
478 ctxt->exception.error_code_valid = valid;
35d3d4a1 479 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 480}
481
3b88e41a
JR		 482static int emulate_db(struct x86_emulate_ctxt *ctxt)
483{
484 return emulate_exception(ctxt, DB_VECTOR, 0, false);
485}
486
35d3d4a1 487static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 488{
35d3d4a1 489 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 490}
491
618ff15d
AK		 492static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
493{
494 return emulate_exception(ctxt, SS_VECTOR, err, true);
495}
496
35d3d4a1 497static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 498{
35d3d4a1 499 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 500}
501
35d3d4a1 502static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 503{
35d3d4a1 504 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 505}
506
34d1f490
AK		 507static int emulate_de(struct x86_emulate_ctxt *ctxt)
508{
35d3d4a1 509 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 510}
511
1253791d
AK		 512static int emulate_nm(struct x86_emulate_ctxt *ctxt)
513{
514 return emulate_exception(ctxt, NM_VECTOR, 0, false);
515}
516
1aa36616
AK		 517static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
518{
519 u16 selector;
520 struct desc_struct desc;
521
522 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
523 return selector;
524}
525
526static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
527 unsigned seg)
528{
529 u16 dummy;
530 u32 base3;
531 struct desc_struct desc;
532
533 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
534 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
535}
536
3d9b938e 537static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 538 struct segmented_address addr,
3d9b938e 539 unsigned size, bool write, bool fetch,
52fd8b44
AK		 540 ulong *linear)
541{
618ff15d
AK		 542 struct desc_struct desc;
543 bool usable;
52fd8b44 544 ulong la;
618ff15d 545 u32 lim;
1aa36616 546 u16 sel;
618ff15d 547 unsigned cpl, rpl;
52fd8b44 548
7b105ca2 549 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 550 switch (ctxt->mode) {
551 case X86EMUL_MODE_REAL:
552 break;
553 case X86EMUL_MODE_PROT64:
554 if (((signed long)la << 16) >> 16 != la)
555 return emulate_gp(ctxt, 0);
556 break;
557 default:
1aa36616
AK		 558 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
559 addr.seg);
618ff15d
AK		 560 if (!usable)
561 goto bad;
562 /* code segment or read-only data segment */
563 if (((desc.type & 8) || !(desc.type & 2)) && write)
564 goto bad;
565 /* unreadable code segment */
3d9b938e 566 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 567 goto bad;
568 lim = desc_limit_scaled(&desc);
569 if ((desc.type & 8) || !(desc.type & 4)) {
570 /* expand-up segment */
571 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
572 goto bad;
573 } else {
574 /* exapand-down segment */
575 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
576 goto bad;
577 lim = desc.d ? 0xffffffff : 0xffff;
578 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
579 goto bad;
580 }
717746e3 581 cpl = ctxt->ops->cpl(ctxt);
1aa36616 582 rpl = sel & 3;
618ff15d
AK		 583 cpl = max(cpl, rpl);
584 if (!(desc.type & 8)) {
585 /* data segment */
586 if (cpl > desc.dpl)
587 goto bad;
588 } else if ((desc.type & 8) && !(desc.type & 4)) {
589 /* nonconforming code segment */
590 if (cpl != desc.dpl)
591 goto bad;
592 } else if ((desc.type & 8) && (desc.type & 4)) {
593 /* conforming code segment */
594 if (cpl < desc.dpl)
595 goto bad;
596 }
597 break;
598 }
9dac77fa 599 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 600 la &= (u32)-1;
601 *linear = la;
602 return X86EMUL_CONTINUE;
618ff15d
AK		 603bad:
604 if (addr.seg == VCPU_SREG_SS)
605 return emulate_ss(ctxt, addr.seg);
606 else
607 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 608}
609
3d9b938e
NE		 610static int linearize(struct x86_emulate_ctxt *ctxt,
611 struct segmented_address addr,
612 unsigned size, bool write,
613 ulong *linear)
614{
615 return __linearize(ctxt, addr, size, write, false, linear);
616}
617
618
3ca3ac4d
AK		 619static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
620 struct segmented_address addr,
621 void *data,
622 unsigned size)
623{
9fa088f4
AK		 624 int rc;
625 ulong linear;
626
83b8795a 627 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 628 if (rc != X86EMUL_CONTINUE)
629 return rc;
0f65dd70 630 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 631}
632
807941b1
TY		 633/*
634 * Fetch the next byte of the instruction being emulated which is pointed to
635 * by ctxt->_eip, then increment ctxt->_eip.
636 *
637 * Also prefetch the remaining bytes of the instruction without crossing page
638 * boundary if they are not in fetch_cache yet.
639 */
640static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 641{
9dac77fa 642 struct fetch_cache *fc = &ctxt->fetch;
62266869 643 int rc;
2fb53ad8 644 int size, cur_size;
62266869 645
807941b1 646 if (ctxt->_eip == fc->end) {
3d9b938e 647 unsigned long linear;
807941b1
TY		 648 struct segmented_address addr = { .seg = VCPU_SREG_CS,
649 .ea = ctxt->_eip };
2fb53ad8 650 cur_size = fc->end - fc->start;
807941b1
TY		 651 size = min(15UL - cur_size,
652 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 653 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 654 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 655 return rc;
ef5d75cc
TY		 656 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
657 size, &ctxt->exception);
7d88bb48 658 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 659 return rc;
2fb53ad8 660 fc->end += size;
62266869 661 }
807941b1
TY		 662 *dest = fc->data[ctxt->_eip - fc->start];
663 ctxt->_eip++;
3e2815e9 664 return X86EMUL_CONTINUE;
62266869
AK		 665}
666
667static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 668 void *dest, unsigned size)
62266869 669{
3e2815e9 670 int rc;
62266869 671
eb3c79e6 672 /* x86 instructions are limited to 15 bytes. */
7d88bb48 673 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 674 return X86EMUL_UNHANDLEABLE;
62266869 675 while (size--) {
807941b1 676 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 677 if (rc != X86EMUL_CONTINUE)
62266869
AK		 678 return rc;
679 }
3e2815e9 680 return X86EMUL_CONTINUE;
62266869
AK		 681}
682
67cbc90d 683/* Fetch next part of the instruction being emulated. */
e85a1085 684#define insn_fetch(_type, _ctxt) \
67cbc90d 685({ unsigned long _x; \
e85a1085 686 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 687 if (rc != X86EMUL_CONTINUE) \
688 goto done; \
67cbc90d
TY		 689 (_type)_x; \
690})
691
807941b1
TY		 692#define insn_fetch_arr(_arr, _size, _ctxt) \
693({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 694 if (rc != X86EMUL_CONTINUE) \
695 goto done; \
67cbc90d
TY		 696})
697
1e3c5cb0
RR		 698/*
699 * Given the 'reg' portion of a ModRM byte, and a register block, return a
700 * pointer into the block that addresses the relevant register.
701 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
702 */
703static void *decode_register(u8 modrm_reg, unsigned long *regs,
704 int highbyte_regs)
6aa8b732
AK		 705{
706 void *p;
707
708 p = &regs[modrm_reg];
709 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
710 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
711 return p;
712}
713
714static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 715 struct segmented_address addr,
6aa8b732
AK		 716 u16 *size, unsigned long *address, int op_bytes)
717{
718 int rc;
719
720 if (op_bytes == 2)
721 op_bytes = 3;
722 *address = 0;
3ca3ac4d 723 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 724 if (rc != X86EMUL_CONTINUE)
6aa8b732 725 return rc;
30b31ab6 726 addr.ea += 2;
3ca3ac4d 727 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 728 return rc;
729}
730
bbe9abbd
NK		 731static int test_cc(unsigned int condition, unsigned int flags)
732{
733 int rc = 0;
734
735 switch ((condition & 15) >> 1) {
736 case 0: /* o */
737 rc |= (flags & EFLG_OF);
738 break;
739 case 1: /* b/c/nae */
740 rc |= (flags & EFLG_CF);
741 break;
742 case 2: /* z/e */
743 rc |= (flags & EFLG_ZF);
744 break;
745 case 3: /* be/na */
746 rc |= (flags & (EFLG_CF|EFLG_ZF));
747 break;
748 case 4: /* s */
749 rc |= (flags & EFLG_SF);
750 break;
751 case 5: /* p/pe */
752 rc |= (flags & EFLG_PF);
753 break;
754 case 7: /* le/ng */
755 rc |= (flags & EFLG_ZF);
756 /* fall through */
757 case 6: /* l/nge */
758 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
759 break;
760 }
761
762 /* Odd condition identifiers (lsb == 1) have inverted sense. */
763 return (!!rc ^ (condition & 1));
764}
765
91ff3cb4
AK		 766static void fetch_register_operand(struct operand *op)
767{
768 switch (op->bytes) {
769 case 1:
770 op->val = *(u8 *)op->addr.reg;
771 break;
772 case 2:
773 op->val = *(u16 *)op->addr.reg;
774 break;
775 case 4:
776 op->val = *(u32 *)op->addr.reg;
777 break;
778 case 8:
779 op->val = *(u64 *)op->addr.reg;
780 break;
781 }
782}
783
1253791d
AK		 784static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
785{
786 ctxt->ops->get_fpu(ctxt);
787 switch (reg) {
788 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
789 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
790 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
791 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
792 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
793 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
794 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
795 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
796#ifdef CONFIG_X86_64
797 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
798 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
799 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
800 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
801 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
802 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
803 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
804 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
805#endif
806 default: BUG();
807 }
808 ctxt->ops->put_fpu(ctxt);
809}
810
811static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
812 int reg)
813{
814 ctxt->ops->get_fpu(ctxt);
815 switch (reg) {
816 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
817 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
818 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
819 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
820 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
821 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
822 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
823 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
824#ifdef CONFIG_X86_64
825 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
826 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
827 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
828 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
829 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
830 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
831 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
832 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
833#endif
834 default: BUG();
835 }
836 ctxt->ops->put_fpu(ctxt);
837}
838
839static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
840 struct operand *op,
3c118e24
AK		 841 int inhibit_bytereg)
842{
9dac77fa
AK		 843 unsigned reg = ctxt->modrm_reg;
844 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 845
9dac77fa
AK		 846 if (!(ctxt->d & ModRM))
847 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 848
9dac77fa 849 if (ctxt->d & Sse) {
1253791d
AK		 850 op->type = OP_XMM;
851 op->bytes = 16;
852 op->addr.xmm = reg;
853 read_sse_reg(ctxt, &op->vec_val, reg);
854 return;
855 }
856
3c118e24 857 op->type = OP_REG;
9dac77fa
AK		 858 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
859 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 860 op->bytes = 1;
861 } else {
9dac77fa
AK		 862 op->addr.reg = decode_register(reg, ctxt->regs, 0);
863 op->bytes = ctxt->op_bytes;
3c118e24 864 }
91ff3cb4 865 fetch_register_operand(op);
3c118e24
AK		 866 op->orig_val = op->val;
867}
868
1c73ef66 869static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 870 struct operand *op)
1c73ef66 871{
1c73ef66 872 u8 sib;
f5b4edcd 873 int index_reg = 0, base_reg = 0, scale;
3e2815e9 874 int rc = X86EMUL_CONTINUE;
2dbd0dd7 875 ulong modrm_ea = 0;
1c73ef66 876
9dac77fa
AK		 877 if (ctxt->rex_prefix) {
878 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
880 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 881 }
882
e85a1085 883 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 884 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
885 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
886 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
887 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 888
9dac77fa 889 if (ctxt->modrm_mod == 3) {
2dbd0dd7 890 op->type = OP_REG;
9dac77fa
AK		 891 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
892 op->addr.reg = decode_register(ctxt->modrm_rm,
893 ctxt->regs, ctxt->d & ByteOp);
894 if (ctxt->d & Sse) {
1253791d
AK		 895 op->type = OP_XMM;
896 op->bytes = 16;
9dac77fa
AK		 897 op->addr.xmm = ctxt->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 899 return rc;
900 }
2dbd0dd7 901 fetch_register_operand(op);
1c73ef66
AK		 902 return rc;
903 }
904
2dbd0dd7
AK		 905 op->type = OP_MEM;
906
9dac77fa
AK		 907 if (ctxt->ad_bytes == 2) {
908 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
909 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
910 unsigned si = ctxt->regs[VCPU_REGS_RSI];
911 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 912
913 /* 16-bit ModR/M decode. */
9dac77fa 914 switch (ctxt->modrm_mod) {
1c73ef66 915 case 0:
9dac77fa 916 if (ctxt->modrm_rm == 6)
e85a1085 917 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 918 break;
919 case 1:
e85a1085 920 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 921 break;
922 case 2:
e85a1085 923 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 924 break;
925 }
9dac77fa 926 switch (ctxt->modrm_rm) {
1c73ef66 927 case 0:
2dbd0dd7 928 modrm_ea += bx + si;
1c73ef66
AK		 929 break;
930 case 1:
2dbd0dd7 931 modrm_ea += bx + di;
1c73ef66
AK		 932 break;
933 case 2:
2dbd0dd7 934 modrm_ea += bp + si;
1c73ef66
AK		 935 break;
936 case 3:
2dbd0dd7 937 modrm_ea += bp + di;
1c73ef66
AK		 938 break;
939 case 4:
2dbd0dd7 940 modrm_ea += si;
1c73ef66
AK		 941 break;
942 case 5:
2dbd0dd7 943 modrm_ea += di;
1c73ef66
AK		 944 break;
945 case 6:
9dac77fa 946 if (ctxt->modrm_mod != 0)
2dbd0dd7 947 modrm_ea += bp;
1c73ef66
AK		 948 break;
949 case 7:
2dbd0dd7 950 modrm_ea += bx;
1c73ef66
AK		 951 break;
952 }
9dac77fa
AK		 953 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
954 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
955 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 956 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 957 } else {
958 /* 32/64-bit ModR/M decode. */
9dac77fa 959 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 960 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
9dac77fa 965 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 966 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 967 else
9dac77fa 968 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 969 if (index_reg != 4)
9dac77fa
AK		 970 modrm_ea += ctxt->regs[index_reg] << scale;
971 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 972 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 973 ctxt->rip_relative = 1;
84411d85 974 } else
9dac77fa
AK		 975 modrm_ea += ctxt->regs[ctxt->modrm_rm];
976 switch (ctxt->modrm_mod) {
1c73ef66 977 case 0:
9dac77fa 978 if (ctxt->modrm_rm == 5)
e85a1085 979 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 980 break;
981 case 1:
e85a1085 982 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 983 break;
984 case 2:
e85a1085 985 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 986 break;
987 }
988 }
90de84f5 989 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 990done:
991 return rc;
992}
993
994static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 995 struct operand *op)
1c73ef66 996{
3e2815e9 997 int rc = X86EMUL_CONTINUE;
1c73ef66 998
2dbd0dd7 999 op->type = OP_MEM;
9dac77fa 1000 switch (ctxt->ad_bytes) {
1c73ef66 1001 case 2:
e85a1085 1002 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1003 break;
1004 case 4:
e85a1085 1005 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1006 break;
1007 case 8:
e85a1085 1008 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1009 break;
1010 }
1011done:
1012 return rc;
1013}
1014
9dac77fa 1015static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1016{
7129eeca 1017 long sv = 0, mask;
35c843c4 1018
9dac77fa
AK		 1019 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1020 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1021
9dac77fa
AK		 1022 if (ctxt->src.bytes == 2)
1023 sv = (s16)ctxt->src.val & (s16)mask;
1024 else if (ctxt->src.bytes == 4)
1025 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1026
9dac77fa 1027 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1028 }
ba7ff2b7
WY		 1029
1030 /* only subword offset */
9dac77fa 1031 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1032}
1033
dde7e6d1 1034static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1035 unsigned long addr, void *dest, unsigned size)
6aa8b732 1036{
dde7e6d1 1037 int rc;
9dac77fa 1038 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1039
dde7e6d1
AK		 1040 while (size) {
1041 int n = min(size, 8u);
1042 size -= n;
1043 if (mc->pos < mc->end)
1044 goto read_cached;
5cd21917 1045
7b105ca2
TY		 1046 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1047 &ctxt->exception);
dde7e6d1
AK		 1048 if (rc != X86EMUL_CONTINUE)
1049 return rc;
1050 mc->end += n;
6aa8b732 1051
dde7e6d1
AK		 1052 read_cached:
1053 memcpy(dest, mc->data + mc->pos, n);
1054 mc->pos += n;
1055 dest += n;
1056 addr += n;
6aa8b732 1057 }
dde7e6d1
AK		 1058 return X86EMUL_CONTINUE;
1059}
6aa8b732 1060
3ca3ac4d
AK		 1061static int segmented_read(struct x86_emulate_ctxt *ctxt,
1062 struct segmented_address addr,
1063 void *data,
1064 unsigned size)
1065{
9fa088f4
AK		 1066 int rc;
1067 ulong linear;
1068
83b8795a 1069 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1070 if (rc != X86EMUL_CONTINUE)
1071 return rc;
7b105ca2 1072 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1073}
1074
1075static int segmented_write(struct x86_emulate_ctxt *ctxt,
1076 struct segmented_address addr,
1077 const void *data,
1078 unsigned size)
1079{
9fa088f4
AK		 1080 int rc;
1081 ulong linear;
1082
83b8795a 1083 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1084 if (rc != X86EMUL_CONTINUE)
1085 return rc;
0f65dd70
AK		 1086 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1087 &ctxt->exception);
3ca3ac4d
AK		 1088}
1089
1090static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1091 struct segmented_address addr,
1092 const void *orig_data, const void *data,
1093 unsigned size)
1094{
9fa088f4
AK		 1095 int rc;
1096 ulong linear;
1097
83b8795a 1098 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1099 if (rc != X86EMUL_CONTINUE)
1100 return rc;
0f65dd70
AK		 1101 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1102 size, &ctxt->exception);
3ca3ac4d
AK		 1103}
1104
dde7e6d1 1105static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1106 unsigned int size, unsigned short port,
1107 void *dest)
1108{
9dac77fa 1109 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1110
dde7e6d1 1111 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1112 unsigned int in_page, n;
9dac77fa
AK		 1113 unsigned int count = ctxt->rep_prefix ?
1114 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1115 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1116 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1117 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1118 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1119 count);
1120 if (n == 0)
1121 n = 1;
1122 rc->pos = rc->end = 0;
7b105ca2 1123 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1124 return 0;
1125 rc->end = n * size;
6aa8b732
AK		 1126 }
1127
dde7e6d1
AK		 1128 memcpy(dest, rc->data + rc->pos, size);
1129 rc->pos += size;
1130 return 1;
1131}
6aa8b732 1132
dde7e6d1 1133static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1134 u16 selector, struct desc_ptr *dt)
1135{
7b105ca2
TY		 1136 struct x86_emulate_ops *ops = ctxt->ops;
1137
dde7e6d1
AK		 1138 if (selector & 1 << 2) {
1139 struct desc_struct desc;
1aa36616
AK		 1140 u16 sel;
1141
dde7e6d1 1142 memset (dt, 0, sizeof *dt);
1aa36616 1143 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1144 return;
e09d082c 1145
dde7e6d1
AK		 1146 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1147 dt->address = get_desc_base(&desc);
1148 } else
4bff1e86 1149 ops->get_gdt(ctxt, dt);
dde7e6d1 1150}
120df890 1151
dde7e6d1
AK		 1152/* allowed just for 8 bytes segments */
1153static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1154 u16 selector, struct desc_struct *desc)
1155{
1156 struct desc_ptr dt;
1157 u16 index = selector >> 3;
dde7e6d1 1158 ulong addr;
120df890 1159
7b105ca2 1160 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1161
35d3d4a1
AK		 1162 if (dt.size < index * 8 + 7)
1163 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1164
7b105ca2
TY		 1165 addr = dt.address + index * 8;
1166 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1167 &ctxt->exception);
dde7e6d1 1168}
ef65c889 1169
dde7e6d1
AK		 1170/* allowed just for 8 bytes segments */
1171static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1172 u16 selector, struct desc_struct *desc)
1173{
1174 struct desc_ptr dt;
1175 u16 index = selector >> 3;
dde7e6d1 1176 ulong addr;
6aa8b732 1177
7b105ca2 1178 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1179
35d3d4a1
AK		 1180 if (dt.size < index * 8 + 7)
1181 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1182
dde7e6d1 1183 addr = dt.address + index * 8;
7b105ca2
TY		 1184 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1185 &ctxt->exception);
dde7e6d1 1186}
c7e75a3d 1187
5601d05b 1188/* Does not support long mode */
dde7e6d1 1189static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1190 u16 selector, int seg)
1191{
1192 struct desc_struct seg_desc;
1193 u8 dpl, rpl, cpl;
1194 unsigned err_vec = GP_VECTOR;
1195 u32 err_code = 0;
1196 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1197 int ret;
69f55cb1 1198
dde7e6d1 1199 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1200
dde7e6d1
AK		 1201 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1202 || ctxt->mode == X86EMUL_MODE_REAL) {
1203 /* set real mode segment descriptor */
1204 set_desc_base(&seg_desc, selector << 4);
1205 set_desc_limit(&seg_desc, 0xffff);
1206 seg_desc.type = 3;
1207 seg_desc.p = 1;
1208 seg_desc.s = 1;
1209 goto load;
1210 }
1211
1212 /* NULL selector is not valid for TR, CS and SS */
1213 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1214 && null_selector)
1215 goto exception;
1216
1217 /* TR should be in GDT only */
1218 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1219 goto exception;
1220
1221 if (null_selector) /* for NULL selector skip all following checks */
1222 goto load;
1223
7b105ca2 1224 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1225 if (ret != X86EMUL_CONTINUE)
1226 return ret;
1227
1228 err_code = selector & 0xfffc;
1229 err_vec = GP_VECTOR;
1230
1231 /* can't load system descriptor into segment selecor */
1232 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1233 goto exception;
1234
1235 if (!seg_desc.p) {
1236 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1237 goto exception;
1238 }
1239
1240 rpl = selector & 3;
1241 dpl = seg_desc.dpl;
7b105ca2 1242 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1243
1244 switch (seg) {
1245 case VCPU_SREG_SS:
1246 /*
1247 * segment is not a writable data segment or segment
1248 * selector's RPL != CPL or segment selector's RPL != CPL
1249 */
1250 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1251 goto exception;
6aa8b732 1252 break;
dde7e6d1
AK		 1253 case VCPU_SREG_CS:
1254 if (!(seg_desc.type & 8))
1255 goto exception;
1256
1257 if (seg_desc.type & 4) {
1258 /* conforming */
1259 if (dpl > cpl)
1260 goto exception;
1261 } else {
1262 /* nonconforming */
1263 if (rpl > cpl || dpl != cpl)
1264 goto exception;
1265 }
1266 /* CS(RPL) <- CPL */
1267 selector = (selector & 0xfffc) | cpl;
6aa8b732 1268 break;
dde7e6d1
AK		 1269 case VCPU_SREG_TR:
1270 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1271 goto exception;
1272 break;
1273 case VCPU_SREG_LDTR:
1274 if (seg_desc.s || seg_desc.type != 2)
1275 goto exception;
1276 break;
1277 default: /* DS, ES, FS, or GS */
4e62417b 1278 /*
dde7e6d1
AK		 1279 * segment is not a data or readable code segment or
1280 * ((segment is a data or nonconforming code segment)
1281 * and (both RPL and CPL > DPL))
4e62417b 1282 */
dde7e6d1
AK		 1283 if ((seg_desc.type & 0xa) == 0x8 ||
1284 (((seg_desc.type & 0xc) != 0xc) &&
1285 (rpl > dpl && cpl > dpl)))
1286 goto exception;
6aa8b732 1287 break;
dde7e6d1
AK		 1288 }
1289
1290 if (seg_desc.s) {
1291 /* mark segment as accessed */
1292 seg_desc.type |= 1;
7b105ca2 1293 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1294 if (ret != X86EMUL_CONTINUE)
1295 return ret;
1296 }
1297load:
7b105ca2 1298 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1299 return X86EMUL_CONTINUE;
1300exception:
1301 emulate_exception(ctxt, err_vec, err_code, true);
1302 return X86EMUL_PROPAGATE_FAULT;
1303}
1304
31be40b3
WY		 1305static void write_register_operand(struct operand *op)
1306{
1307 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1308 switch (op->bytes) {
1309 case 1:
1310 *(u8 *)op->addr.reg = (u8)op->val;
1311 break;
1312 case 2:
1313 *(u16 *)op->addr.reg = (u16)op->val;
1314 break;
1315 case 4:
1316 *op->addr.reg = (u32)op->val;
1317 break; /* 64b: zero-extend */
1318 case 8:
1319 *op->addr.reg = op->val;
1320 break;
1321 }
1322}
1323
adddcecf 1324static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1325{
1326 int rc;
dde7e6d1 1327
9dac77fa 1328 switch (ctxt->dst.type) {
dde7e6d1 1329 case OP_REG:
9dac77fa 1330 write_register_operand(&ctxt->dst);
6aa8b732 1331 break;
dde7e6d1 1332 case OP_MEM:
9dac77fa 1333 if (ctxt->lock_prefix)
3ca3ac4d 1334 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1335 ctxt->dst.addr.mem,
1336 &ctxt->dst.orig_val,
1337 &ctxt->dst.val,
1338 ctxt->dst.bytes);
341de7e3 1339 else
3ca3ac4d 1340 rc = segmented_write(ctxt,
9dac77fa
AK		 1341 ctxt->dst.addr.mem,
1342 &ctxt->dst.val,
1343 ctxt->dst.bytes);
dde7e6d1
AK		 1344 if (rc != X86EMUL_CONTINUE)
1345 return rc;
a682e354 1346 break;
1253791d 1347 case OP_XMM:
9dac77fa 1348 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1349 break;
dde7e6d1
AK		 1350 case OP_NONE:
1351 /* no writeback */
414e6277 1352 break;
dde7e6d1 1353 default:
414e6277 1354 break;
6aa8b732 1355 }
dde7e6d1
AK		 1356 return X86EMUL_CONTINUE;
1357}
6aa8b732 1358
4487b3b4 1359static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1360{
4179bb02 1361 struct segmented_address addr;
0dc8d10f 1362
9dac77fa
AK		 1363 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1364 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1365 addr.seg = VCPU_SREG_SS;
1366
1367 /* Disable writeback. */
9dac77fa
AK		 1368 ctxt->dst.type = OP_NONE;
1369 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1370}
69f55cb1 1371
dde7e6d1 1372static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1373 void *dest, int len)
1374{
dde7e6d1 1375 int rc;
90de84f5 1376 struct segmented_address addr;
8b4caf66 1377
9dac77fa 1378 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1379 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1380 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1381 if (rc != X86EMUL_CONTINUE)
1382 return rc;
1383
9dac77fa 1384 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1385 return rc;
8b4caf66
LV		 1386}
1387
c54fe504
TY		 1388static int em_pop(struct x86_emulate_ctxt *ctxt)
1389{
9dac77fa 1390 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1391}
1392
dde7e6d1 1393static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1394 void *dest, int len)
9de41573
GN		 1395{
1396 int rc;
dde7e6d1
AK		 1397 unsigned long val, change_mask;
1398 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1399 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1400
3b9be3bf 1401 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1402 if (rc != X86EMUL_CONTINUE)
1403 return rc;
9de41573 1404
dde7e6d1
AK		 1405 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1406 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1407
dde7e6d1
AK		 1408 switch(ctxt->mode) {
1409 case X86EMUL_MODE_PROT64:
1410 case X86EMUL_MODE_PROT32:
1411 case X86EMUL_MODE_PROT16:
1412 if (cpl == 0)
1413 change_mask |= EFLG_IOPL;
1414 if (cpl <= iopl)
1415 change_mask |= EFLG_IF;
1416 break;
1417 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1418 if (iopl < 3)
1419 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1420 change_mask |= EFLG_IF;
1421 break;
1422 default: /* real mode */
1423 change_mask |= (EFLG_IOPL | EFLG_IF);
1424 break;
9de41573 1425 }
dde7e6d1
AK		 1426
1427 *(unsigned long *)dest =
1428 (ctxt->eflags & ~change_mask) | (val & change_mask);
1429
1430 return rc;
9de41573
GN		 1431}
1432
62aaa2f0
TY		 1433static int em_popf(struct x86_emulate_ctxt *ctxt)
1434{
9dac77fa
AK		 1435 ctxt->dst.type = OP_REG;
1436 ctxt->dst.addr.reg = &ctxt->eflags;
1437 ctxt->dst.bytes = ctxt->op_bytes;
1438 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1439}
1440
7b105ca2 1441static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
7b262e90 1442{
9dac77fa 1443 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1444
4487b3b4 1445 return em_push(ctxt);
7b262e90
GN		 1446}
1447
7b105ca2 1448static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
38ba30ba 1449{
dde7e6d1
AK		 1450 unsigned long selector;
1451 int rc;
38ba30ba 1452
9dac77fa 1453 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1454 if (rc != X86EMUL_CONTINUE)
1455 return rc;
1456
7b105ca2 1457 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1458 return rc;
38ba30ba
GN		 1459}
1460
b96a7fad 1461static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1462{
9dac77fa 1463 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1464 int rc = X86EMUL_CONTINUE;
1465 int reg = VCPU_REGS_RAX;
38ba30ba 1466
dde7e6d1
AK		 1467 while (reg <= VCPU_REGS_RDI) {
1468 (reg == VCPU_REGS_RSP) ?
9dac77fa 1469 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1470
4487b3b4 1471 rc = em_push(ctxt);
dde7e6d1
AK		 1472 if (rc != X86EMUL_CONTINUE)
1473 return rc;
38ba30ba 1474
dde7e6d1 1475 ++reg;
38ba30ba 1476 }
38ba30ba 1477
dde7e6d1 1478 return rc;
38ba30ba
GN		 1479}
1480
62aaa2f0
TY		 1481static int em_pushf(struct x86_emulate_ctxt *ctxt)
1482{
9dac77fa 1483 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1484 return em_push(ctxt);
1485}
1486
b96a7fad 1487static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1488{
dde7e6d1
AK		 1489 int rc = X86EMUL_CONTINUE;
1490 int reg = VCPU_REGS_RDI;
38ba30ba 1491
dde7e6d1
AK		 1492 while (reg >= VCPU_REGS_RAX) {
1493 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1494 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1495 ctxt->op_bytes);
dde7e6d1
AK		 1496 --reg;
1497 }
38ba30ba 1498
9dac77fa 1499 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1500 if (rc != X86EMUL_CONTINUE)
1501 break;
1502 --reg;
38ba30ba 1503 }
dde7e6d1 1504 return rc;
38ba30ba
GN		 1505}
1506
7b105ca2 1507int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1508{
7b105ca2 1509 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1510 int rc;
6e154e56
MG		 1511 struct desc_ptr dt;
1512 gva_t cs_addr;
1513 gva_t eip_addr;
1514 u16 cs, eip;
6e154e56
MG		 1515
1516 /* TODO: Add limit checks */
9dac77fa 1517 ctxt->src.val = ctxt->eflags;
4487b3b4 1518 rc = em_push(ctxt);
5c56e1cf
AK		 1519 if (rc != X86EMUL_CONTINUE)
1520 return rc;
6e154e56
MG		 1521
1522 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1523
9dac77fa 1524 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1525 rc = em_push(ctxt);
5c56e1cf
AK		 1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
6e154e56 1528
9dac77fa 1529 ctxt->src.val = ctxt->_eip;
4487b3b4 1530 rc = em_push(ctxt);
5c56e1cf
AK		 1531 if (rc != X86EMUL_CONTINUE)
1532 return rc;
1533
4bff1e86 1534 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1535
1536 eip_addr = dt.address + (irq << 2);
1537 cs_addr = dt.address + (irq << 2) + 2;
1538
0f65dd70 1539 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1540 if (rc != X86EMUL_CONTINUE)
1541 return rc;
1542
0f65dd70 1543 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1544 if (rc != X86EMUL_CONTINUE)
1545 return rc;
1546
7b105ca2 1547 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1548 if (rc != X86EMUL_CONTINUE)
1549 return rc;
1550
9dac77fa 1551 ctxt->_eip = eip;
6e154e56
MG		 1552
1553 return rc;
1554}
1555
7b105ca2 1556static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1557{
1558 switch(ctxt->mode) {
1559 case X86EMUL_MODE_REAL:
7b105ca2 1560 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1561 case X86EMUL_MODE_VM86:
1562 case X86EMUL_MODE_PROT16:
1563 case X86EMUL_MODE_PROT32:
1564 case X86EMUL_MODE_PROT64:
1565 default:
1566 /* Protected mode interrupts unimplemented yet */
1567 return X86EMUL_UNHANDLEABLE;
1568 }
1569}
1570
7b105ca2 1571static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1572{
dde7e6d1
AK		 1573 int rc = X86EMUL_CONTINUE;
1574 unsigned long temp_eip = 0;
1575 unsigned long temp_eflags = 0;
1576 unsigned long cs = 0;
1577 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1578 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1579 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1580 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1581
dde7e6d1 1582 /* TODO: Add stack limit check */
38ba30ba 1583
9dac77fa 1584 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1585
dde7e6d1
AK		 1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
38ba30ba 1588
35d3d4a1
AK		 1589 if (temp_eip & ~0xffff)
1590 return emulate_gp(ctxt, 0);
38ba30ba 1591
9dac77fa 1592 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1593
dde7e6d1
AK		 1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
38ba30ba 1596
9dac77fa 1597 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1598
dde7e6d1
AK		 1599 if (rc != X86EMUL_CONTINUE)
1600 return rc;
38ba30ba 1601
7b105ca2 1602 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1603
dde7e6d1
AK		 1604 if (rc != X86EMUL_CONTINUE)
1605 return rc;
38ba30ba 1606
9dac77fa 1607 ctxt->_eip = temp_eip;
38ba30ba 1608
38ba30ba 1609
9dac77fa 1610 if (ctxt->op_bytes == 4)
dde7e6d1 1611 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1612 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1613 ctxt->eflags &= ~0xffff;
1614 ctxt->eflags |= temp_eflags;
38ba30ba 1615 }
dde7e6d1
AK		 1616
1617 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1618 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1619
1620 return rc;
38ba30ba
GN		 1621}
1622
e01991e7 1623static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1624{
dde7e6d1
AK		 1625 switch(ctxt->mode) {
1626 case X86EMUL_MODE_REAL:
7b105ca2 1627 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1628 case X86EMUL_MODE_VM86:
1629 case X86EMUL_MODE_PROT16:
1630 case X86EMUL_MODE_PROT32:
1631 case X86EMUL_MODE_PROT64:
c37eda13 1632 default:
dde7e6d1
AK		 1633 /* iret from protected mode unimplemented yet */
1634 return X86EMUL_UNHANDLEABLE;
c37eda13 1635 }
c37eda13
WY		 1636}
1637
d2f62766
TY		 1638static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1639{
d2f62766
TY		 1640 int rc;
1641 unsigned short sel;
1642
9dac77fa 1643 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1644
7b105ca2 1645 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1646 if (rc != X86EMUL_CONTINUE)
1647 return rc;
1648
9dac77fa
AK		 1649 ctxt->_eip = 0;
1650 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1651 return X86EMUL_CONTINUE;
1652}
1653
51187683 1654static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1655{
9dac77fa 1656 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1657}
1658
51187683 1659static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1660{
9dac77fa 1661 switch (ctxt->modrm_reg) {
8cdbd2c9 1662 case 0: /* rol */
a31b9cea 1663 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1664 break;
1665 case 1: /* ror */
a31b9cea 1666 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1667 break;
1668 case 2: /* rcl */
a31b9cea 1669 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1670 break;
1671 case 3: /* rcr */
a31b9cea 1672 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1673 break;
1674 case 4: /* sal/shl */
1675 case 6: /* sal/shl */
a31b9cea 1676 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1677 break;
1678 case 5: /* shr */
a31b9cea 1679 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1680 break;
1681 case 7: /* sar */
a31b9cea 1682 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1683 break;
1684 }
51187683 1685 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1686}
1687
3329ece1
AK		 1688static int em_not(struct x86_emulate_ctxt *ctxt)
1689{
1690 ctxt->dst.val = ~ctxt->dst.val;
1691 return X86EMUL_CONTINUE;
1692}
1693
1694static int em_neg(struct x86_emulate_ctxt *ctxt)
1695{
1696 emulate_1op(ctxt, "neg");
1697 return X86EMUL_CONTINUE;
1698}
1699
1700static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1701{
1702 u8 ex = 0;
1703
1704 emulate_1op_rax_rdx(ctxt, "mul", ex);
1705 return X86EMUL_CONTINUE;
1706}
1707
1708static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1709{
1710 u8 ex = 0;
1711
1712 emulate_1op_rax_rdx(ctxt, "imul", ex);
1713 return X86EMUL_CONTINUE;
1714}
1715
1716static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1717{
34d1f490 1718 u8 de = 0;
8cdbd2c9 1719
3329ece1
AK		 1720 emulate_1op_rax_rdx(ctxt, "div", de);
1721 if (de)
1722 return emulate_de(ctxt);
1723 return X86EMUL_CONTINUE;
1724}
1725
1726static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1727{
1728 u8 de = 0;
1729
1730 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1731 if (de)
1732 return emulate_de(ctxt);
8c5eee30 1733 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1734}
1735
51187683 1736static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1737{
4179bb02 1738 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1739
9dac77fa 1740 switch (ctxt->modrm_reg) {
8cdbd2c9 1741 case 0: /* inc */
d1eef45d 1742 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1743 break;
1744 case 1: /* dec */
d1eef45d 1745 emulate_1op(ctxt, "dec");
8cdbd2c9 1746 break;
d19292e4
MG		 1747 case 2: /* call near abs */ {
1748 long int old_eip;
9dac77fa
AK		 1749 old_eip = ctxt->_eip;
1750 ctxt->_eip = ctxt->src.val;
1751 ctxt->src.val = old_eip;
4487b3b4 1752 rc = em_push(ctxt);
d19292e4
MG		 1753 break;
1754 }
8cdbd2c9 1755 case 4: /* jmp abs */
9dac77fa 1756 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1757 break;
d2f62766
TY		 1758 case 5: /* jmp far */
1759 rc = em_jmp_far(ctxt);
1760 break;
8cdbd2c9 1761 case 6: /* push */
4487b3b4 1762 rc = em_push(ctxt);
8cdbd2c9 1763 break;
8cdbd2c9 1764 }
4179bb02 1765 return rc;
8cdbd2c9
LV		 1766}
1767
51187683 1768static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1769{
9dac77fa 1770 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1771
9dac77fa
AK		 1772 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1773 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1774 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1775 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1776 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1777 } else {
9dac77fa
AK		 1778 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1779 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1780
05f086f8 1781 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1782 }
1b30eaa8 1783 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1784}
1785
ebda02c2
TY		 1786static int em_ret(struct x86_emulate_ctxt *ctxt)
1787{
9dac77fa
AK		 1788 ctxt->dst.type = OP_REG;
1789 ctxt->dst.addr.reg = &ctxt->_eip;
1790 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1791 return em_pop(ctxt);
1792}
1793
e01991e7 1794static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1795{
a77ab5ea
AK		 1796 int rc;
1797 unsigned long cs;
1798
9dac77fa 1799 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1800 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1801 return rc;
9dac77fa
AK		 1802 if (ctxt->op_bytes == 4)
1803 ctxt->_eip = (u32)ctxt->_eip;
1804 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1805 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1806 return rc;
7b105ca2 1807 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1808 return rc;
1809}
1810
7b105ca2 1811static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
09b5f4d3 1812{
09b5f4d3
WY		 1813 unsigned short sel;
1814 int rc;
1815
9dac77fa 1816 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1817
7b105ca2 1818 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1819 if (rc != X86EMUL_CONTINUE)
1820 return rc;
1821
9dac77fa 1822 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1823 return rc;
1824}
1825
7b105ca2 1826static void
e66bb2cc 1827setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1828 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1829{
1aa36616
AK		 1830 u16 selector;
1831
79168fd1 1832 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1833 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1834 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1835
1836 cs->l = 0; /* will be adjusted later */
79168fd1 1837 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1838 cs->g = 1; /* 4kb granularity */
79168fd1 1839 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1840 cs->type = 0x0b; /* Read, Execute, Accessed */
1841 cs->s = 1;
1842 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1843 cs->p = 1;
1844 cs->d = 1;
e66bb2cc 1845
79168fd1
GN		 1846 set_desc_base(ss, 0); /* flat segment */
1847 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1848 ss->g = 1; /* 4kb granularity */
1849 ss->s = 1;
1850 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1851 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1852 ss->dpl = 0;
79168fd1 1853 ss->p = 1;
e66bb2cc
AP		 1854}
1855
e01991e7 1856static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1857{
7b105ca2 1858 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1859 struct desc_struct cs, ss;
e66bb2cc 1860 u64 msr_data;
79168fd1 1861 u16 cs_sel, ss_sel;
c2ad2bb3 1862 u64 efer = 0;
e66bb2cc
AP		 1863
1864 /* syscall is not available in real mode */
2e901c4c 1865 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1866 ctxt->mode == X86EMUL_MODE_VM86)
1867 return emulate_ud(ctxt);
e66bb2cc 1868
c2ad2bb3 1869 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1870 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1871
717746e3 1872 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1873 msr_data >>= 32;
79168fd1
GN		 1874 cs_sel = (u16)(msr_data & 0xfffc);
1875 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1876
c2ad2bb3 1877 if (efer & EFER_LMA) {
79168fd1 1878 cs.d = 0;
e66bb2cc
AP		 1879 cs.l = 1;
1880 }
1aa36616
AK		 1881 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1882 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1883
9dac77fa 1884 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1885 if (efer & EFER_LMA) {
e66bb2cc 1886#ifdef CONFIG_X86_64
9dac77fa 1887 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1888
717746e3 1889 ops->get_msr(ctxt,
3fb1b5db
GN		 1890 ctxt->mode == X86EMUL_MODE_PROT64 ?
1891 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1892 ctxt->_eip = msr_data;
e66bb2cc 1893
717746e3 1894 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1895 ctxt->eflags &= ~(msr_data | EFLG_RF);
1896#endif
1897 } else {
1898 /* legacy mode */
717746e3 1899 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1900 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1901
1902 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1903 }
1904
e54cfa97 1905 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1906}
1907
e01991e7 1908static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1909{
7b105ca2 1910 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1911 struct desc_struct cs, ss;
8c604352 1912 u64 msr_data;
79168fd1 1913 u16 cs_sel, ss_sel;
c2ad2bb3 1914 u64 efer = 0;
8c604352 1915
7b105ca2 1916 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1917 /* inject #GP if in real mode */
35d3d4a1
AK		 1918 if (ctxt->mode == X86EMUL_MODE_REAL)
1919 return emulate_gp(ctxt, 0);
8c604352
AP		 1920
1921 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1922 * Therefore, we inject an #UD.
1923 */
35d3d4a1
AK		 1924 if (ctxt->mode == X86EMUL_MODE_PROT64)
1925 return emulate_ud(ctxt);
8c604352 1926
7b105ca2 1927 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1928
717746e3 1929 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1930 switch (ctxt->mode) {
1931 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1932 if ((msr_data & 0xfffc) == 0x0)
1933 return emulate_gp(ctxt, 0);
8c604352
AP		 1934 break;
1935 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1936 if (msr_data == 0x0)
1937 return emulate_gp(ctxt, 0);
8c604352
AP		 1938 break;
1939 }
1940
1941 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1942 cs_sel = (u16)msr_data;
1943 cs_sel &= ~SELECTOR_RPL_MASK;
1944 ss_sel = cs_sel + 8;
1945 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1946 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1947 cs.d = 0;
8c604352
AP		 1948 cs.l = 1;
1949 }
1950
1aa36616
AK		 1951 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1952 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1953
717746e3 1954 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1955 ctxt->_eip = msr_data;
8c604352 1956
717746e3 1957 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1958 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1959
e54cfa97 1960 return X86EMUL_CONTINUE;
8c604352
AP		 1961}
1962
e01991e7 1963static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1964{
7b105ca2 1965 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1966 struct desc_struct cs, ss;
4668f050
AP		 1967 u64 msr_data;
1968 int usermode;
1249b96e 1969 u16 cs_sel = 0, ss_sel = 0;
4668f050 1970
a0044755
GN		 1971 /* inject #GP if in real mode or Virtual 8086 mode */
1972 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1973 ctxt->mode == X86EMUL_MODE_VM86)
1974 return emulate_gp(ctxt, 0);
4668f050 1975
7b105ca2 1976 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 1977
9dac77fa 1978 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 1979 usermode = X86EMUL_MODE_PROT64;
1980 else
1981 usermode = X86EMUL_MODE_PROT32;
1982
1983 cs.dpl = 3;
1984 ss.dpl = 3;
717746e3 1985 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1986 switch (usermode) {
1987 case X86EMUL_MODE_PROT32:
79168fd1 1988 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1989 if ((msr_data & 0xfffc) == 0x0)
1990 return emulate_gp(ctxt, 0);
79168fd1 1991 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1992 break;
1993 case X86EMUL_MODE_PROT64:
79168fd1 1994 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1995 if (msr_data == 0x0)
1996 return emulate_gp(ctxt, 0);
79168fd1
GN		 1997 ss_sel = cs_sel + 8;
1998 cs.d = 0;
4668f050
AP		 1999 cs.l = 1;
2000 break;
2001 }
79168fd1
GN		 2002 cs_sel |= SELECTOR_RPL_MASK;
2003 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2004
1aa36616
AK		 2005 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2006 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2007
9dac77fa
AK		 2008 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2009 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2010
e54cfa97 2011 return X86EMUL_CONTINUE;
4668f050
AP		 2012}
2013
7b105ca2 2014static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2015{
2016 int iopl;
2017 if (ctxt->mode == X86EMUL_MODE_REAL)
2018 return false;
2019 if (ctxt->mode == X86EMUL_MODE_VM86)
2020 return true;
2021 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2022 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2023}
2024
2025static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2026 u16 port, u16 len)
2027{
7b105ca2 2028 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2029 struct desc_struct tr_seg;
5601d05b 2030 u32 base3;
f850e2e6 2031 int r;
1aa36616 2032 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2033 unsigned mask = (1 << len) - 1;
5601d05b 2034 unsigned long base;
f850e2e6 2035
1aa36616 2036 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2037 if (!tr_seg.p)
f850e2e6 2038 return false;
79168fd1 2039 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2040 return false;
5601d05b
GN		 2041 base = get_desc_base(&tr_seg);
2042#ifdef CONFIG_X86_64
2043 base |= ((u64)base3) << 32;
2044#endif
0f65dd70 2045 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2046 if (r != X86EMUL_CONTINUE)
2047 return false;
79168fd1 2048 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2049 return false;
0f65dd70 2050 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2051 if (r != X86EMUL_CONTINUE)
2052 return false;
2053 if ((perm >> bit_idx) & mask)
2054 return false;
2055 return true;
2056}
2057
2058static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2059 u16 port, u16 len)
2060{
4fc40f07
GN		 2061 if (ctxt->perm_ok)
2062 return true;
2063
7b105ca2
TY		 2064 if (emulator_bad_iopl(ctxt))
2065 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2066 return false;
4fc40f07
GN		 2067
2068 ctxt->perm_ok = true;
2069
f850e2e6
GN		 2070 return true;
2071}
2072
38ba30ba 2073static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2074 struct tss_segment_16 *tss)
2075{
9dac77fa 2076 tss->ip = ctxt->_eip;
38ba30ba 2077 tss->flag = ctxt->eflags;
9dac77fa
AK		 2078 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2079 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2080 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2081 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2082 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2083 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2084 tss->si = ctxt->regs[VCPU_REGS_RSI];
2085 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2086
1aa36616
AK		 2087 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2088 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2089 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2090 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2091 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2092}
2093
2094static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2095 struct tss_segment_16 *tss)
2096{
38ba30ba
GN		 2097 int ret;
2098
9dac77fa 2099 ctxt->_eip = tss->ip;
38ba30ba 2100 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2101 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2102 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2103 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2104 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2105 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2106 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2107 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2108 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2109
2110 /*
2111 * SDM says that segment selectors are loaded before segment
2112 * descriptors
2113 */
1aa36616
AK		 2114 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2115 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2116 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2117 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2118 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2119
2120 /*
2121 * Now load segment descriptors. If fault happenes at this stage
2122 * it is handled in a context of new task
2123 */
7b105ca2 2124 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2125 if (ret != X86EMUL_CONTINUE)
2126 return ret;
7b105ca2 2127 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
7b105ca2 2130 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
7b105ca2 2133 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
7b105ca2 2136 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2137 if (ret != X86EMUL_CONTINUE)
2138 return ret;
2139
2140 return X86EMUL_CONTINUE;
2141}
2142
2143static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2144 u16 tss_selector, u16 old_tss_sel,
2145 ulong old_tss_base, struct desc_struct *new_desc)
2146{
7b105ca2 2147 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2148 struct tss_segment_16 tss_seg;
2149 int ret;
bcc55cba 2150 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2151
0f65dd70 2152 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2153 &ctxt->exception);
db297e3d 2154 if (ret != X86EMUL_CONTINUE)
38ba30ba 2155 /* FIXME: need to provide precise fault address */
38ba30ba 2156 return ret;
38ba30ba 2157
7b105ca2 2158 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2159
0f65dd70 2160 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2161 &ctxt->exception);
db297e3d 2162 if (ret != X86EMUL_CONTINUE)
38ba30ba 2163 /* FIXME: need to provide precise fault address */
38ba30ba 2164 return ret;
38ba30ba 2165
0f65dd70 2166 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2167 &ctxt->exception);
db297e3d 2168 if (ret != X86EMUL_CONTINUE)
38ba30ba 2169 /* FIXME: need to provide precise fault address */
38ba30ba 2170 return ret;
38ba30ba
GN		 2171
2172 if (old_tss_sel != 0xffff) {
2173 tss_seg.prev_task_link = old_tss_sel;
2174
0f65dd70 2175 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2176 &tss_seg.prev_task_link,
2177 sizeof tss_seg.prev_task_link,
0f65dd70 2178 &ctxt->exception);
db297e3d 2179 if (ret != X86EMUL_CONTINUE)
38ba30ba 2180 /* FIXME: need to provide precise fault address */
38ba30ba 2181 return ret;
38ba30ba
GN		 2182 }
2183
7b105ca2 2184 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2185}
2186
2187static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2188 struct tss_segment_32 *tss)
2189{
7b105ca2 2190 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2191 tss->eip = ctxt->_eip;
38ba30ba 2192 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2193 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2194 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2195 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2196 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2197 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2198 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2199 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2200 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2201
1aa36616
AK		 2202 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2203 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2204 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2205 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2206 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2207 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2208 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2209}
2210
2211static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2212 struct tss_segment_32 *tss)
2213{
38ba30ba
GN		 2214 int ret;
2215
7b105ca2 2216 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2217 return emulate_gp(ctxt, 0);
9dac77fa 2218 ctxt->_eip = tss->eip;
38ba30ba 2219 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2220 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2221 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2222 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2223 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2224 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2225 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2226 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2227 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2228
2229 /*
2230 * SDM says that segment selectors are loaded before segment
2231 * descriptors
2232 */
1aa36616
AK		 2233 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2234 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2235 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2236 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2237 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2238 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2239 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2240
2241 /*
2242 * Now load segment descriptors. If fault happenes at this stage
2243 * it is handled in a context of new task
2244 */
7b105ca2 2245 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2246 if (ret != X86EMUL_CONTINUE)
2247 return ret;
7b105ca2 2248 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2249 if (ret != X86EMUL_CONTINUE)
2250 return ret;
7b105ca2 2251 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2252 if (ret != X86EMUL_CONTINUE)
2253 return ret;
7b105ca2 2254 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2255 if (ret != X86EMUL_CONTINUE)
2256 return ret;
7b105ca2 2257 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2258 if (ret != X86EMUL_CONTINUE)
2259 return ret;
7b105ca2 2260 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2261 if (ret != X86EMUL_CONTINUE)
2262 return ret;
7b105ca2 2263 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2264 if (ret != X86EMUL_CONTINUE)
2265 return ret;
2266
2267 return X86EMUL_CONTINUE;
2268}
2269
2270static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2271 u16 tss_selector, u16 old_tss_sel,
2272 ulong old_tss_base, struct desc_struct *new_desc)
2273{
7b105ca2 2274 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2275 struct tss_segment_32 tss_seg;
2276 int ret;
bcc55cba 2277 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2278
0f65dd70 2279 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2280 &ctxt->exception);
db297e3d 2281 if (ret != X86EMUL_CONTINUE)
38ba30ba 2282 /* FIXME: need to provide precise fault address */
38ba30ba 2283 return ret;
38ba30ba 2284
7b105ca2 2285 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2286
0f65dd70 2287 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2288 &ctxt->exception);
db297e3d 2289 if (ret != X86EMUL_CONTINUE)
38ba30ba 2290 /* FIXME: need to provide precise fault address */
38ba30ba 2291 return ret;
38ba30ba 2292
0f65dd70 2293 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2294 &ctxt->exception);
db297e3d 2295 if (ret != X86EMUL_CONTINUE)
38ba30ba 2296 /* FIXME: need to provide precise fault address */
38ba30ba 2297 return ret;
38ba30ba
GN		 2298
2299 if (old_tss_sel != 0xffff) {
2300 tss_seg.prev_task_link = old_tss_sel;
2301
0f65dd70 2302 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2303 &tss_seg.prev_task_link,
2304 sizeof tss_seg.prev_task_link,
0f65dd70 2305 &ctxt->exception);
db297e3d 2306 if (ret != X86EMUL_CONTINUE)
38ba30ba 2307 /* FIXME: need to provide precise fault address */
38ba30ba 2308 return ret;
38ba30ba
GN		 2309 }
2310
7b105ca2 2311 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2312}
2313
2314static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2315 u16 tss_selector, int reason,
2316 bool has_error_code, u32 error_code)
38ba30ba 2317{
7b105ca2 2318 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2319 struct desc_struct curr_tss_desc, next_tss_desc;
2320 int ret;
1aa36616 2321 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2322 ulong old_tss_base =
4bff1e86 2323 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2324 u32 desc_limit;
38ba30ba
GN		 2325
2326 /* FIXME: old_tss_base == ~0 ? */
2327
7b105ca2 2328 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2329 if (ret != X86EMUL_CONTINUE)
2330 return ret;
7b105ca2 2331 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2332 if (ret != X86EMUL_CONTINUE)
2333 return ret;
2334
2335 /* FIXME: check that next_tss_desc is tss */
2336
2337 if (reason != TASK_SWITCH_IRET) {
2338 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2339 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2340 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2341 }
2342
ceffb459
GN		 2343 desc_limit = desc_limit_scaled(&next_tss_desc);
2344 if (!next_tss_desc.p ||
2345 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2346 desc_limit < 0x2b)) {
54b8486f 2347 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2348 return X86EMUL_PROPAGATE_FAULT;
2349 }
2350
2351 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2352 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2353 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2354 }
2355
2356 if (reason == TASK_SWITCH_IRET)
2357 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2358
2359 /* set back link to prev task only if NT bit is set in eflags
2360 note that old_tss_sel is not used afetr this point */
2361 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2362 old_tss_sel = 0xffff;
2363
2364 if (next_tss_desc.type & 8)
7b105ca2 2365 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2366 old_tss_base, &next_tss_desc);
2367 else
7b105ca2 2368 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2369 old_tss_base, &next_tss_desc);
0760d448
JK		 2370 if (ret != X86EMUL_CONTINUE)
2371 return ret;
38ba30ba
GN		 2372
2373 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2374 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2375
2376 if (reason != TASK_SWITCH_IRET) {
2377 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2378 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2379 }
2380
717746e3 2381 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2382 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2383
e269fb21 2384 if (has_error_code) {
9dac77fa
AK		 2385 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2386 ctxt->lock_prefix = 0;
2387 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2388 ret = em_push(ctxt);
e269fb21
JK		 2389 }
2390
38ba30ba
GN		 2391 return ret;
2392}
2393
2394int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2395 u16 tss_selector, int reason,
2396 bool has_error_code, u32 error_code)
38ba30ba 2397{
38ba30ba
GN		 2398 int rc;
2399
9dac77fa
AK		 2400 ctxt->_eip = ctxt->eip;
2401 ctxt->dst.type = OP_NONE;
38ba30ba 2402
7b105ca2 2403 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2404 has_error_code, error_code);
38ba30ba 2405
4179bb02 2406 if (rc == X86EMUL_CONTINUE)
9dac77fa 2407 ctxt->eip = ctxt->_eip;
38ba30ba 2408
a0c0ab2f 2409 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2410}
2411
90de84f5 2412static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2413 int reg, struct operand *op)
a682e354 2414{
a682e354
GN		 2415 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2416
9dac77fa
AK		 2417 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2418 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2419 op->addr.mem.seg = seg;
a682e354
GN		 2420}
2421
7af04fc0
AK		 2422static int em_das(struct x86_emulate_ctxt *ctxt)
2423{
7af04fc0
AK		 2424 u8 al, old_al;
2425 bool af, cf, old_cf;
2426
2427 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2428 al = ctxt->dst.val;
7af04fc0
AK		 2429
2430 old_al = al;
2431 old_cf = cf;
2432 cf = false;
2433 af = ctxt->eflags & X86_EFLAGS_AF;
2434 if ((al & 0x0f) > 9 || af) {
2435 al -= 6;
2436 cf = old_cf | (al >= 250);
2437 af = true;
2438 } else {
2439 af = false;
2440 }
2441 if (old_al > 0x99 || old_cf) {
2442 al -= 0x60;
2443 cf = true;
2444 }
2445
9dac77fa 2446 ctxt->dst.val = al;
7af04fc0 2447 /* Set PF, ZF, SF */
9dac77fa
AK		 2448 ctxt->src.type = OP_IMM;
2449 ctxt->src.val = 0;
2450 ctxt->src.bytes = 1;
a31b9cea 2451 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2452 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2453 if (cf)
2454 ctxt->eflags |= X86_EFLAGS_CF;
2455 if (af)
2456 ctxt->eflags |= X86_EFLAGS_AF;
2457 return X86EMUL_CONTINUE;
2458}
2459
0ef753b8
AK		 2460static int em_call_far(struct x86_emulate_ctxt *ctxt)
2461{
0ef753b8
AK		 2462 u16 sel, old_cs;
2463 ulong old_eip;
2464 int rc;
2465
1aa36616 2466 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2467 old_eip = ctxt->_eip;
0ef753b8 2468
9dac77fa 2469 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2470 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2471 return X86EMUL_CONTINUE;
2472
9dac77fa
AK		 2473 ctxt->_eip = 0;
2474 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2475
9dac77fa 2476 ctxt->src.val = old_cs;
4487b3b4 2477 rc = em_push(ctxt);
0ef753b8
AK		 2478 if (rc != X86EMUL_CONTINUE)
2479 return rc;
2480
9dac77fa 2481 ctxt->src.val = old_eip;
4487b3b4 2482 return em_push(ctxt);
0ef753b8
AK		 2483}
2484
40ece7c7
AK		 2485static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2486{
40ece7c7
AK		 2487 int rc;
2488
9dac77fa
AK		 2489 ctxt->dst.type = OP_REG;
2490 ctxt->dst.addr.reg = &ctxt->_eip;
2491 ctxt->dst.bytes = ctxt->op_bytes;
2492 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2493 if (rc != X86EMUL_CONTINUE)
2494 return rc;
9dac77fa 2495 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2496 return X86EMUL_CONTINUE;
2497}
2498
d67fc27a
TY		 2499static int em_add(struct x86_emulate_ctxt *ctxt)
2500{
a31b9cea 2501 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2502 return X86EMUL_CONTINUE;
2503}
2504
2505static int em_or(struct x86_emulate_ctxt *ctxt)
2506{
a31b9cea 2507 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2508 return X86EMUL_CONTINUE;
2509}
2510
2511static int em_adc(struct x86_emulate_ctxt *ctxt)
2512{
a31b9cea 2513 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2514 return X86EMUL_CONTINUE;
2515}
2516
2517static int em_sbb(struct x86_emulate_ctxt *ctxt)
2518{
a31b9cea 2519 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2520 return X86EMUL_CONTINUE;
2521}
2522
2523static int em_and(struct x86_emulate_ctxt *ctxt)
2524{
a31b9cea 2525 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2526 return X86EMUL_CONTINUE;
2527}
2528
2529static int em_sub(struct x86_emulate_ctxt *ctxt)
2530{
a31b9cea 2531 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2532 return X86EMUL_CONTINUE;
2533}
2534
2535static int em_xor(struct x86_emulate_ctxt *ctxt)
2536{
a31b9cea 2537 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2538 return X86EMUL_CONTINUE;
2539}
2540
2541static int em_cmp(struct x86_emulate_ctxt *ctxt)
2542{
a31b9cea 2543 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2544 /* Disable writeback. */
9dac77fa 2545 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2546 return X86EMUL_CONTINUE;
2547}
2548
9f21ca59
TY		 2549static int em_test(struct x86_emulate_ctxt *ctxt)
2550{
a31b9cea 2551 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2552 /* Disable writeback. */
2553 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2554 return X86EMUL_CONTINUE;
2555}
2556
e4f973ae
TY		 2557static int em_xchg(struct x86_emulate_ctxt *ctxt)
2558{
e4f973ae 2559 /* Write back the register source. */
9dac77fa
AK		 2560 ctxt->src.val = ctxt->dst.val;
2561 write_register_operand(&ctxt->src);
e4f973ae
TY		 2562
2563 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2564 ctxt->dst.val = ctxt->src.orig_val;
2565 ctxt->lock_prefix = 1;
e4f973ae
TY		 2566 return X86EMUL_CONTINUE;
2567}
2568
5c82aa29 2569static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2570{
a31b9cea 2571 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2572 return X86EMUL_CONTINUE;
2573}
2574
5c82aa29
AK		 2575static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2576{
9dac77fa 2577 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2578 return em_imul(ctxt);
2579}
2580
61429142
AK		 2581static int em_cwd(struct x86_emulate_ctxt *ctxt)
2582{
9dac77fa
AK		 2583 ctxt->dst.type = OP_REG;
2584 ctxt->dst.bytes = ctxt->src.bytes;
2585 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2586 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2587
2588 return X86EMUL_CONTINUE;
2589}
2590
48bb5d3c
AK		 2591static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2592{
48bb5d3c
AK		 2593 u64 tsc = 0;
2594
717746e3 2595 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2596 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2597 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2598 return X86EMUL_CONTINUE;
2599}
2600
b9eac5f4
AK		 2601static int em_mov(struct x86_emulate_ctxt *ctxt)
2602{
9dac77fa 2603 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2604 return X86EMUL_CONTINUE;
2605}
2606
1bd5f469
TY		 2607static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2608{
9dac77fa 2609 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2610 return emulate_ud(ctxt);
2611
9dac77fa 2612 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2613 return X86EMUL_CONTINUE;
2614}
2615
2616static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2617{
9dac77fa 2618 u16 sel = ctxt->src.val;
1bd5f469 2619
9dac77fa 2620 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2621 return emulate_ud(ctxt);
2622
9dac77fa 2623 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2624 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2625
2626 /* Disable writeback. */
9dac77fa
AK		 2627 ctxt->dst.type = OP_NONE;
2628 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2629}
2630
aa97bb48
AK		 2631static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2632{
9dac77fa 2633 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2634 return X86EMUL_CONTINUE;
2635}
2636
38503911
AK		 2637static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2638{
9fa088f4
AK		 2639 int rc;
2640 ulong linear;
2641
9dac77fa 2642 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2643 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2644 ctxt->ops->invlpg(ctxt, linear);
38503911 2645 /* Disable writeback. */
9dac77fa 2646 ctxt->dst.type = OP_NONE;
38503911
AK		 2647 return X86EMUL_CONTINUE;
2648}
2649
2d04a05b
AK		 2650static int em_clts(struct x86_emulate_ctxt *ctxt)
2651{
2652 ulong cr0;
2653
2654 cr0 = ctxt->ops->get_cr(ctxt, 0);
2655 cr0 &= ~X86_CR0_TS;
2656 ctxt->ops->set_cr(ctxt, 0, cr0);
2657 return X86EMUL_CONTINUE;
2658}
2659
26d05cc7
AK		 2660static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2661{
26d05cc7
AK		 2662 int rc;
2663
9dac77fa 2664 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2665 return X86EMUL_UNHANDLEABLE;
2666
2667 rc = ctxt->ops->fix_hypercall(ctxt);
2668 if (rc != X86EMUL_CONTINUE)
2669 return rc;
2670
2671 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2672 ctxt->_eip = ctxt->eip;
26d05cc7 2673 /* Disable writeback. */
9dac77fa 2674 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2675 return X86EMUL_CONTINUE;
2676}
2677
2678static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2679{
26d05cc7
AK		 2680 struct desc_ptr desc_ptr;
2681 int rc;
2682
9dac77fa 2683 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2684 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2685 ctxt->op_bytes);
26d05cc7
AK		 2686 if (rc != X86EMUL_CONTINUE)
2687 return rc;
2688 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2689 /* Disable writeback. */
9dac77fa 2690 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2691 return X86EMUL_CONTINUE;
2692}
2693
5ef39c71 2694static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2695{
26d05cc7
AK		 2696 int rc;
2697
5ef39c71
AK		 2698 rc = ctxt->ops->fix_hypercall(ctxt);
2699
26d05cc7 2700 /* Disable writeback. */
9dac77fa 2701 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2702 return rc;
2703}
2704
2705static int em_lidt(struct x86_emulate_ctxt *ctxt)
2706{
26d05cc7
AK		 2707 struct desc_ptr desc_ptr;
2708 int rc;
2709
9dac77fa 2710 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2711 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2712 ctxt->op_bytes);
26d05cc7
AK		 2713 if (rc != X86EMUL_CONTINUE)
2714 return rc;
2715 ctxt->ops->set_idt(ctxt, &desc_ptr);
2716 /* Disable writeback. */
9dac77fa 2717 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2718 return X86EMUL_CONTINUE;
2719}
2720
2721static int em_smsw(struct x86_emulate_ctxt *ctxt)
2722{
9dac77fa
AK		 2723 ctxt->dst.bytes = 2;
2724 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2725 return X86EMUL_CONTINUE;
2726}
2727
2728static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2729{
26d05cc7 2730 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2731 | (ctxt->src.val & 0x0f));
2732 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2733 return X86EMUL_CONTINUE;
2734}
2735
d06e03ad
TY		 2736static int em_loop(struct x86_emulate_ctxt *ctxt)
2737{
9dac77fa
AK		 2738 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2739 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2740 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2741 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2742
2743 return X86EMUL_CONTINUE;
2744}
2745
2746static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2747{
9dac77fa
AK		 2748 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2749 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2750
2751 return X86EMUL_CONTINUE;
2752}
2753
f411e6cd
TY		 2754static int em_cli(struct x86_emulate_ctxt *ctxt)
2755{
2756 if (emulator_bad_iopl(ctxt))
2757 return emulate_gp(ctxt, 0);
2758
2759 ctxt->eflags &= ~X86_EFLAGS_IF;
2760 return X86EMUL_CONTINUE;
2761}
2762
2763static int em_sti(struct x86_emulate_ctxt *ctxt)
2764{
2765 if (emulator_bad_iopl(ctxt))
2766 return emulate_gp(ctxt, 0);
2767
2768 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2769 ctxt->eflags |= X86_EFLAGS_IF;
2770 return X86EMUL_CONTINUE;
2771}
2772
cfec82cb
JR		 2773static bool valid_cr(int nr)
2774{
2775 switch (nr) {
2776 case 0:
2777 case 2 ... 4:
2778 case 8:
2779 return true;
2780 default:
2781 return false;
2782 }
2783}
2784
2785static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2786{
9dac77fa 2787 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2788 return emulate_ud(ctxt);
2789
2790 return X86EMUL_CONTINUE;
2791}
2792
2793static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2794{
9dac77fa
AK		 2795 u64 new_val = ctxt->src.val64;
2796 int cr = ctxt->modrm_reg;
c2ad2bb3 2797 u64 efer = 0;
cfec82cb
JR		 2798
2799 static u64 cr_reserved_bits[] = {
2800 0xffffffff00000000ULL,
2801 0, 0, 0, /* CR3 checked later */
2802 CR4_RESERVED_BITS,
2803 0, 0, 0,
2804 CR8_RESERVED_BITS,
2805 };
2806
2807 if (!valid_cr(cr))
2808 return emulate_ud(ctxt);
2809
2810 if (new_val & cr_reserved_bits[cr])
2811 return emulate_gp(ctxt, 0);
2812
2813 switch (cr) {
2814 case 0: {
c2ad2bb3 2815 u64 cr4;
cfec82cb
JR		 2816 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2817 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2818 return emulate_gp(ctxt, 0);
2819
717746e3
AK		 2820 cr4 = ctxt->ops->get_cr(ctxt, 4);
2821 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2822
2823 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2824 !(cr4 & X86_CR4_PAE))
2825 return emulate_gp(ctxt, 0);
2826
2827 break;
2828 }
2829 case 3: {
2830 u64 rsvd = 0;
2831
c2ad2bb3
AK		 2832 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2833 if (efer & EFER_LMA)
cfec82cb 2834 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2835 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2836 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2837 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2838 rsvd = CR3_NONPAE_RESERVED_BITS;
2839
2840 if (new_val & rsvd)
2841 return emulate_gp(ctxt, 0);
2842
2843 break;
2844 }
2845 case 4: {
c2ad2bb3 2846 u64 cr4;
cfec82cb 2847
717746e3
AK		 2848 cr4 = ctxt->ops->get_cr(ctxt, 4);
2849 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2850
2851 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2852 return emulate_gp(ctxt, 0);
2853
2854 break;
2855 }
2856 }
2857
2858 return X86EMUL_CONTINUE;
2859}
2860
3b88e41a
JR		 2861static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2862{
2863 unsigned long dr7;
2864
717746e3 2865 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2866
2867 /* Check if DR7.Global_Enable is set */
2868 return dr7 & (1 << 13);
2869}
2870
2871static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2872{
9dac77fa 2873 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2874 u64 cr4;
2875
2876 if (dr > 7)
2877 return emulate_ud(ctxt);
2878
717746e3 2879 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2880 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2881 return emulate_ud(ctxt);
2882
2883 if (check_dr7_gd(ctxt))
2884 return emulate_db(ctxt);
2885
2886 return X86EMUL_CONTINUE;
2887}
2888
2889static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2890{
9dac77fa
AK		 2891 u64 new_val = ctxt->src.val64;
2892 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2893
2894 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2895 return emulate_gp(ctxt, 0);
2896
2897 return check_dr_read(ctxt);
2898}
2899
01de8b09
JR		 2900static int check_svme(struct x86_emulate_ctxt *ctxt)
2901{
2902 u64 efer;
2903
717746e3 2904 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2905
2906 if (!(efer & EFER_SVME))
2907 return emulate_ud(ctxt);
2908
2909 return X86EMUL_CONTINUE;
2910}
2911
2912static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2913{
9dac77fa 2914 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 2915
2916 /* Valid physical address? */
d4224449 2917 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2918 return emulate_gp(ctxt, 0);
2919
2920 return check_svme(ctxt);
2921}
2922
d7eb8203
JR		 2923static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2924{
717746e3 2925 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2926
717746e3 2927 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2928 return emulate_ud(ctxt);
2929
2930 return X86EMUL_CONTINUE;
2931}
2932
8061252e
JR		 2933static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2934{
717746e3 2935 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 2936 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 2937
717746e3 2938 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2939 (rcx > 3))
2940 return emulate_gp(ctxt, 0);
2941
2942 return X86EMUL_CONTINUE;
2943}
2944
f6511935
JR		 2945static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2946{
9dac77fa
AK		 2947 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
2948 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 2949 return emulate_gp(ctxt, 0);
2950
2951 return X86EMUL_CONTINUE;
2952}
2953
2954static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2955{
9dac77fa
AK		 2956 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
2957 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 2958 return emulate_gp(ctxt, 0);
2959
2960 return X86EMUL_CONTINUE;
2961}
2962
73fba5f4 2963#define D(_y) { .flags = (_y) }
c4f035c6 2964#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2965#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2966 .check_perm = (_p) }
73fba5f4 2967#define N D(0)
01de8b09 2968#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2969#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2970#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2971#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2972#define II(_f, _e, _i) \
2973 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2974#define IIP(_f, _e, _i, _p) \
2975 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2976 .check_perm = (_p) }
aa97bb48 2977#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2978
8d8f4e9f 2979#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2980#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2981#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2982
d67fc27a
TY		 2983#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
2984 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
2985 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 2986
d7eb8203
JR		 2987static struct opcode group7_rm1[] = {
2988 DI(SrcNone | ModRM | Priv, monitor),
2989 DI(SrcNone | ModRM | Priv, mwait),
2990 N, N, N, N, N, N,
2991};
2992
01de8b09
JR		 2993static struct opcode group7_rm3[] = {
2994 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 2995 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 2996 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2997 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2998 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2999 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3000 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3001 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3002};
6230f7fc 3003
d7eb8203
JR		 3004static struct opcode group7_rm7[] = {
3005 N,
3006 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3007 N, N, N, N, N, N,
3008};
d67fc27a 3009
73fba5f4 3010static struct opcode group1[] = {
d67fc27a
TY		 3011 I(Lock, em_add),
3012 I(Lock, em_or),
3013 I(Lock, em_adc),
3014 I(Lock, em_sbb),
3015 I(Lock, em_and),
3016 I(Lock, em_sub),
3017 I(Lock, em_xor),
3018 I(0, em_cmp),
73fba5f4
AK		 3019};
3020
3021static struct opcode group1A[] = {
3022 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3023};
3024
3025static struct opcode group3[] = {
3329ece1
AK		 3026 I(DstMem | SrcImm | ModRM, em_test),
3027 I(DstMem | SrcImm | ModRM, em_test),
3028 I(DstMem | SrcNone | ModRM | Lock, em_not),
3029 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3030 I(SrcMem | ModRM, em_mul_ex),
3031 I(SrcMem | ModRM, em_imul_ex),
3032 I(SrcMem | ModRM, em_div_ex),
3033 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3034};
3035
3036static struct opcode group4[] = {
3037 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3038 N, N, N, N, N, N,
3039};
3040
3041static struct opcode group5[] = {
3042 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3043 D(SrcMem | ModRM | Stack),
3044 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3045 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3046 D(SrcMem | ModRM | Stack), N,
3047};
3048
dee6bb70
JR		 3049static struct opcode group6[] = {
3050 DI(ModRM | Prot, sldt),
3051 DI(ModRM | Prot, str),
3052 DI(ModRM | Prot | Priv, lldt),
3053 DI(ModRM | Prot | Priv, ltr),
3054 N, N, N, N,
3055};
3056
73fba5f4 3057static struct group_dual group7 = { {
dee6bb70
JR		 3058 DI(ModRM | Mov | DstMem | Priv, sgdt),
3059 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3060 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3061 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3062 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3063 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3064 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3065}, {
5ef39c71
AK		 3066 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3067 EXT(0, group7_rm1),
01de8b09 3068 N, EXT(0, group7_rm3),
5ef39c71
AK		 3069 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3070 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3071} };
3072
3073static struct opcode group8[] = {
3074 N, N, N, N,
3075 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3076 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3077};
3078
3079static struct group_dual group9 = { {
3080 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3081}, {
3082 N, N, N, N, N, N, N, N,
3083} };
3084
a4d4a7c1
AK		 3085static struct opcode group11[] = {
3086 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3087};
3088
aa97bb48
AK		 3089static struct gprefix pfx_0f_6f_0f_7f = {
3090 N, N, N, I(Sse, em_movdqu),
3091};
3092
73fba5f4
AK		 3093static struct opcode opcode_table[256] = {
3094 /* 0x00 - 0x07 */
d67fc27a 3095 I6ALU(Lock, em_add),
73fba5f4
AK		 3096 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3097 /* 0x08 - 0x0F */
d67fc27a 3098 I6ALU(Lock, em_or),
73fba5f4
AK		 3099 D(ImplicitOps | Stack | No64), N,
3100 /* 0x10 - 0x17 */
d67fc27a 3101 I6ALU(Lock, em_adc),
73fba5f4
AK		 3102 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3103 /* 0x18 - 0x1F */
d67fc27a 3104 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3105 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3106 /* 0x20 - 0x27 */
d67fc27a 3107 I6ALU(Lock, em_and), N, N,
73fba5f4 3108 /* 0x28 - 0x2F */
d67fc27a 3109 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3110 /* 0x30 - 0x37 */
d67fc27a 3111 I6ALU(Lock, em_xor), N, N,
73fba5f4 3112 /* 0x38 - 0x3F */
d67fc27a 3113 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3114 /* 0x40 - 0x4F */
3115 X16(D(DstReg)),
3116 /* 0x50 - 0x57 */
63540382 3117 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3118 /* 0x58 - 0x5F */
c54fe504 3119 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3120 /* 0x60 - 0x67 */
b96a7fad
TY		 3121 I(ImplicitOps | Stack | No64, em_pusha),
3122 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3123 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3124 N, N, N, N,
3125 /* 0x68 - 0x6F */
d46164db
AK		 3126 I(SrcImm | Mov | Stack, em_push),
3127 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3128 I(SrcImmByte | Mov | Stack, em_push),
3129 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3130 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3131 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3132 /* 0x70 - 0x7F */
3133 X16(D(SrcImmByte)),
3134 /* 0x80 - 0x87 */
3135 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3136 G(DstMem | SrcImm | ModRM | Group, group1),
3137 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3138 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3139 I2bv(DstMem | SrcReg | ModRM, em_test),
e4f973ae 3140 I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
73fba5f4 3141 /* 0x88 - 0x8F */
b9eac5f4
AK		 3142 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3143 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
1bd5f469
TY		 3144 I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
3145 D(ModRM | SrcMem | NoAccess | DstReg),
3146 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3147 G(0, group1A),
73fba5f4 3148 /* 0x90 - 0x97 */
bf608f88 3149 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3150 /* 0x98 - 0x9F */
61429142 3151 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3152 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3153 II(ImplicitOps | Stack, em_pushf, pushf),
3154 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3155 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3156 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3157 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3158 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3159 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3160 /* 0xA8 - 0xAF */
9f21ca59 3161 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3162 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3163 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3164 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3165 /* 0xB0 - 0xB7 */
b9eac5f4 3166 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3167 /* 0xB8 - 0xBF */
b9eac5f4 3168 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3169 /* 0xC0 - 0xC7 */
d2c6c7ad 3170 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3171 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3172 I(ImplicitOps | Stack, em_ret),
09b5f4d3 3173 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3174 G(ByteOp, group11), G(0, group11),
73fba5f4 3175 /* 0xC8 - 0xCF */
db5b0762 3176 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3177 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3178 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3179 /* 0xD0 - 0xD7 */
d2c6c7ad 3180 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3181 N, N, N, N,
3182 /* 0xD8 - 0xDF */
3183 N, N, N, N, N, N, N, N,
3184 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3185 X3(I(SrcImmByte, em_loop)),
3186 I(SrcImmByte, em_jcxz),
f6511935
JR		 3187 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3188 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3189 /* 0xE8 - 0xEF */
3190 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
db5b0762 3191 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
221192bd
MT		 3192 D2bvIP(SrcDX | DstAcc, in, check_perm_in),
3193 D2bvIP(SrcAcc | DstDX, out, check_perm_out),
73fba5f4 3194 /* 0xF0 - 0xF7 */
bf608f88 3195 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3196 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3197 G(ByteOp, group3), G(0, group3),
73fba5f4 3198 /* 0xF8 - 0xFF */
f411e6cd
TY		 3199 D(ImplicitOps), D(ImplicitOps),
3200 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3201 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3202};
3203
3204static struct opcode twobyte_table[256] = {
3205 /* 0x00 - 0x0F */
dee6bb70 3206 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3207 N, I(ImplicitOps | VendorSpecific, em_syscall),
3208 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3209 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3210 N, D(ImplicitOps | ModRM), N, N,
3211 /* 0x10 - 0x1F */
3212 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3213 /* 0x20 - 0x2F */
cfec82cb 3214 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3215 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3216 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3217 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3218 N, N, N, N,
3219 N, N, N, N, N, N, N, N,
3220 /* 0x30 - 0x3F */
8061252e
JR		 3221 DI(ImplicitOps | Priv, wrmsr),
3222 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3223 DI(ImplicitOps | Priv, rdmsr),
3224 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3225 I(ImplicitOps | VendorSpecific, em_sysenter),
3226 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3227 N, N,
73fba5f4
AK		 3228 N, N, N, N, N, N, N, N,
3229 /* 0x40 - 0x4F */
3230 X16(D(DstReg | SrcMem | ModRM | Mov)),
3231 /* 0x50 - 0x5F */
3232 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3233 /* 0x60 - 0x6F */
aa97bb48
AK		 3234 N, N, N, N,
3235 N, N, N, N,
3236 N, N, N, N,
3237 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3238 /* 0x70 - 0x7F */
aa97bb48
AK		 3239 N, N, N, N,
3240 N, N, N, N,
3241 N, N, N, N,
3242 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3243 /* 0x80 - 0x8F */
3244 X16(D(SrcImm)),
3245 /* 0x90 - 0x9F */
ee45b58e 3246 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3247 /* 0xA0 - 0xA7 */
3248 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3249 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3250 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3251 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3252 /* 0xA8 - 0xAF */
3253 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3254 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3255 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3256 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3257 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3258 /* 0xB0 - 0xB7 */
739ae406 3259 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3260 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3261 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3262 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3263 /* 0xB8 - 0xBF */
3264 N, N,
ba7ff2b7 3265 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3266 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3267 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3268 /* 0xC0 - 0xCF */
739ae406 3269 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3270 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3271 N, N, N, GD(0, &group9),
3272 N, N, N, N, N, N, N, N,
3273 /* 0xD0 - 0xDF */
3274 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3275 /* 0xE0 - 0xEF */
3276 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3277 /* 0xF0 - 0xFF */
3278 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3279};
3280
3281#undef D
3282#undef N
3283#undef G
3284#undef GD
3285#undef I
aa97bb48 3286#undef GP
01de8b09 3287#undef EXT
73fba5f4 3288
8d8f4e9f 3289#undef D2bv
f6511935 3290#undef D2bvIP
8d8f4e9f 3291#undef I2bv
d67fc27a 3292#undef I6ALU
8d8f4e9f 3293
9dac77fa 3294static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3295{
3296 unsigned size;
3297
9dac77fa 3298 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3299 if (size == 8)
3300 size = 4;
3301 return size;
3302}
3303
3304static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3305 unsigned size, bool sign_extension)
3306{
39f21ee5
AK		 3307 int rc = X86EMUL_CONTINUE;
3308
3309 op->type = OP_IMM;
3310 op->bytes = size;
9dac77fa 3311 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3312 /* NB. Immediates are sign-extended as necessary. */
3313 switch (op->bytes) {
3314 case 1:
e85a1085 3315 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3316 break;
3317 case 2:
e85a1085 3318 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3319 break;
3320 case 4:
e85a1085 3321 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3322 break;
3323 }
3324 if (!sign_extension) {
3325 switch (op->bytes) {
3326 case 1:
3327 op->val &= 0xff;
3328 break;
3329 case 2:
3330 op->val &= 0xffff;
3331 break;
3332 case 4:
3333 op->val &= 0xffffffff;
3334 break;
3335 }
3336 }
3337done:
3338 return rc;
3339}
3340
a9945549
AK		 3341static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3342 unsigned d)
3343{
3344 int rc = X86EMUL_CONTINUE;
3345
3346 switch (d) {
3347 case OpReg:
3348 decode_register_operand(ctxt, op,
5217973e 3349 op == &ctxt->dst &&
a9945549
AK		 3350 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3351 break;
3352 case OpImmUByte:
608aabe3 3353 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3354 break;
3355 case OpMem:
3356 case OpMem64:
3357 *op = ctxt->memop;
3358 ctxt->memopp = op;
3359 if (d == OpMem64)
3360 op->bytes = 8;
3361 else
3362 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3363 if (ctxt->d & BitOp)
3364 fetch_bit_operand(ctxt);
3365 op->orig_val = op->val;
3366 break;
3367 case OpAcc:
3368 op->type = OP_REG;
3369 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3370 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3371 fetch_register_operand(op);
3372 op->orig_val = op->val;
3373 break;
3374 case OpDI:
3375 op->type = OP_MEM;
3376 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3377 op->addr.mem.ea =
3378 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3379 op->addr.mem.seg = VCPU_SREG_ES;
3380 op->val = 0;
3381 break;
3382 case OpDX:
3383 op->type = OP_REG;
3384 op->bytes = 2;
3385 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3386 fetch_register_operand(op);
3387 break;
4dd6a57d
AK		 3388 case OpCL:
3389 op->bytes = 1;
3390 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3391 break;
3392 case OpImmByte:
3393 rc = decode_imm(ctxt, op, 1, true);
3394 break;
3395 case OpOne:
3396 op->bytes = 1;
3397 op->val = 1;
3398 break;
3399 case OpImm:
3400 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3401 break;
a9945549
AK		 3402 case OpImplicit:
3403 /* Special instructions do their own operand decoding. */
3404 default:
3405 op->type = OP_NONE; /* Disable writeback. */
3406 break;
3407 }
3408
3409done:
3410 return rc;
3411}
3412
ef5d75cc 3413int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3414{
dde7e6d1
AK		 3415 int rc = X86EMUL_CONTINUE;
3416 int mode = ctxt->mode;
46561646 3417 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3418 bool op_prefix = false;
46561646 3419 struct opcode opcode;
dde7e6d1 3420
f09ed83e
AK		 3421 ctxt->memop.type = OP_NONE;
3422 ctxt->memopp = NULL;
9dac77fa
AK		 3423 ctxt->_eip = ctxt->eip;
3424 ctxt->fetch.start = ctxt->_eip;
3425 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3426 if (insn_len > 0)
9dac77fa 3427 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3428
3429 switch (mode) {
3430 case X86EMUL_MODE_REAL:
3431 case X86EMUL_MODE_VM86:
3432 case X86EMUL_MODE_PROT16:
3433 def_op_bytes = def_ad_bytes = 2;
3434 break;
3435 case X86EMUL_MODE_PROT32:
3436 def_op_bytes = def_ad_bytes = 4;
3437 break;
3438#ifdef CONFIG_X86_64
3439 case X86EMUL_MODE_PROT64:
3440 def_op_bytes = 4;
3441 def_ad_bytes = 8;
3442 break;
3443#endif
3444 default:
1d2887e2 3445 return EMULATION_FAILED;
dde7e6d1
AK		 3446 }
3447
9dac77fa
AK		 3448 ctxt->op_bytes = def_op_bytes;
3449 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3450
3451 /* Legacy prefixes. */
3452 for (;;) {
e85a1085 3453 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3454 case 0x66: /* operand-size override */
0d7cdee8 3455 op_prefix = true;
dde7e6d1 3456 /* switch between 2/4 bytes */
9dac77fa 3457 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3458 break;
3459 case 0x67: /* address-size override */
3460 if (mode == X86EMUL_MODE_PROT64)
3461 /* switch between 4/8 bytes */
9dac77fa 3462 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3463 else
3464 /* switch between 2/4 bytes */
9dac77fa 3465 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3466 break;
3467 case 0x26: /* ES override */
3468 case 0x2e: /* CS override */
3469 case 0x36: /* SS override */
3470 case 0x3e: /* DS override */
9dac77fa 3471 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3472 break;
3473 case 0x64: /* FS override */
3474 case 0x65: /* GS override */
9dac77fa 3475 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3476 break;
3477 case 0x40 ... 0x4f: /* REX */
3478 if (mode != X86EMUL_MODE_PROT64)
3479 goto done_prefixes;
9dac77fa 3480 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3481 continue;
3482 case 0xf0: /* LOCK */
9dac77fa 3483 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3484 break;
3485 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3486 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3487 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3488 break;
3489 default:
3490 goto done_prefixes;
3491 }
3492
3493 /* Any legacy prefix after a REX prefix nullifies its effect. */
3494
9dac77fa 3495 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3496 }
3497
3498done_prefixes:
3499
3500 /* REX prefix. */
9dac77fa
AK		 3501 if (ctxt->rex_prefix & 8)
3502 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3503
3504 /* Opcode byte(s). */
9dac77fa 3505 opcode = opcode_table[ctxt->b];
d3ad6243 3506 /* Two-byte opcode? */
9dac77fa
AK		 3507 if (ctxt->b == 0x0f) {
3508 ctxt->twobyte = 1;
e85a1085 3509 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3510 opcode = twobyte_table[ctxt->b];
dde7e6d1 3511 }
9dac77fa 3512 ctxt->d = opcode.flags;
dde7e6d1 3513
9dac77fa
AK		 3514 while (ctxt->d & GroupMask) {
3515 switch (ctxt->d & GroupMask) {
46561646 3516 case Group:
e85a1085 3517 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3518 --ctxt->_eip;
3519 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3520 opcode = opcode.u.group[goffset];
3521 break;
3522 case GroupDual:
e85a1085 3523 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3524 --ctxt->_eip;
3525 goffset = (ctxt->modrm >> 3) & 7;
3526 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3527 opcode = opcode.u.gdual->mod3[goffset];
3528 else
3529 opcode = opcode.u.gdual->mod012[goffset];
3530 break;
3531 case RMExt:
9dac77fa 3532 goffset = ctxt->modrm & 7;
01de8b09 3533 opcode = opcode.u.group[goffset];
46561646
AK		 3534 break;
3535 case Prefix:
9dac77fa 3536 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3537 return EMULATION_FAILED;
9dac77fa 3538 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3539 switch (simd_prefix) {
3540 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3541 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3542 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3543 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3544 }
3545 break;
3546 default:
1d2887e2 3547 return EMULATION_FAILED;
0d7cdee8 3548 }
46561646 3549
b1ea50b2 3550 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3551 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3552 }
3553
9dac77fa
AK		 3554 ctxt->execute = opcode.u.execute;
3555 ctxt->check_perm = opcode.check_perm;
3556 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3557
3558 /* Unrecognised? */
9dac77fa 3559 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3560 return EMULATION_FAILED;
dde7e6d1 3561
9dac77fa 3562 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3563 return EMULATION_FAILED;
d867162c 3564
9dac77fa
AK		 3565 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3566 ctxt->op_bytes = 8;
dde7e6d1 3567
9dac77fa 3568 if (ctxt->d & Op3264) {
7f9b4b75 3569 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3570 ctxt->op_bytes = 8;
7f9b4b75 3571 else
9dac77fa 3572 ctxt->op_bytes = 4;
7f9b4b75
AK		 3573 }
3574
9dac77fa
AK		 3575 if (ctxt->d & Sse)
3576 ctxt->op_bytes = 16;
1253791d 3577
dde7e6d1 3578 /* ModRM and SIB bytes. */
9dac77fa 3579 if (ctxt->d & ModRM) {
f09ed83e 3580 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3581 if (!ctxt->has_seg_override)
3582 set_seg_override(ctxt, ctxt->modrm_seg);
3583 } else if (ctxt->d & MemAbs)
f09ed83e 3584 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3585 if (rc != X86EMUL_CONTINUE)
3586 goto done;
3587
9dac77fa
AK		 3588 if (!ctxt->has_seg_override)
3589 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3590
f09ed83e 3591 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3592
f09ed83e
AK		 3593 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3594 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3595
dde7e6d1
AK		 3596 /*
3597 * Decode and fetch the source operand: register, memory
3598 * or immediate.
3599 */
9dac77fa 3600 switch (ctxt->d & SrcMask) {
dde7e6d1
AK		 3601 case SrcNone:
3602 break;
3603 case SrcReg:
9dac77fa 3604 decode_register_operand(ctxt, &ctxt->src, 0);
dde7e6d1
AK		 3605 break;
3606 case SrcMem16:
f09ed83e 3607 ctxt->memop.bytes = 2;
dde7e6d1
AK		 3608 goto srcmem_common;
3609 case SrcMem32:
f09ed83e 3610 ctxt->memop.bytes = 4;
dde7e6d1
AK		 3611 goto srcmem_common;
3612 case SrcMem:
f09ed83e 3613 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dde7e6d1 3614 srcmem_common:
f09ed83e
AK		 3615 ctxt->src = ctxt->memop;
3616 ctxt->memopp = &ctxt->src;
dde7e6d1 3617 break;
b250e605 3618 case SrcImmU16:
9dac77fa 3619 rc = decode_imm(ctxt, &ctxt->src, 2, false);
39f21ee5 3620 break;
dde7e6d1 3621 case SrcImm:
9dac77fa 3622 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
39f21ee5 3623 break;
dde7e6d1 3624 case SrcImmU:
9dac77fa 3625 rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
dde7e6d1
AK		 3626 break;
3627 case SrcImmByte:
9dac77fa 3628 rc = decode_imm(ctxt, &ctxt->src, 1, true);
39f21ee5 3629 break;
dde7e6d1 3630 case SrcImmUByte:
9dac77fa 3631 rc = decode_imm(ctxt, &ctxt->src, 1, false);
dde7e6d1
AK		 3632 break;
3633 case SrcAcc:
9dac77fa
AK		 3634 ctxt->src.type = OP_REG;
3635 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3636 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3637 fetch_register_operand(&ctxt->src);
dde7e6d1
AK		 3638 break;
3639 case SrcOne:
9dac77fa
AK		 3640 ctxt->src.bytes = 1;
3641 ctxt->src.val = 1;
dde7e6d1
AK		 3642 break;
3643 case SrcSI:
9dac77fa
AK		 3644 ctxt->src.type = OP_MEM;
3645 ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3646 ctxt->src.addr.mem.ea =
3647 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3648 ctxt->src.addr.mem.seg = seg_override(ctxt);
3649 ctxt->src.val = 0;
dde7e6d1
AK		 3650 break;
3651 case SrcImmFAddr:
9dac77fa
AK		 3652 ctxt->src.type = OP_IMM;
3653 ctxt->src.addr.mem.ea = ctxt->_eip;
3654 ctxt->src.bytes = ctxt->op_bytes + 2;
807941b1 3655 insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
dde7e6d1
AK		 3656 break;
3657 case SrcMemFAddr:
f09ed83e 3658 ctxt->memop.bytes = ctxt->op_bytes + 2;
2dbd0dd7 3659 goto srcmem_common;
dde7e6d1 3660 break;
221192bd 3661 case SrcDX:
9dac77fa
AK		 3662 ctxt->src.type = OP_REG;
3663 ctxt->src.bytes = 2;
3664 ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3665 fetch_register_operand(&ctxt->src);
221192bd 3666 break;
dde7e6d1
AK		 3667 }
3668
39f21ee5
AK		 3669 if (rc != X86EMUL_CONTINUE)
3670 goto done;
3671
dde7e6d1
AK		 3672 /*
3673 * Decode and fetch the second source operand: register, memory
3674 * or immediate.
3675 */
4dd6a57d 3676 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3677 if (rc != X86EMUL_CONTINUE)
3678 goto done;
3679
dde7e6d1 3680 /* Decode and fetch the destination operand: register or memory. */
a9945549 3681 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3682
3683done:
f09ed83e
AK		 3684 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3685 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3686
1d2887e2 3687 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3688}
3689
3e2f65d5
GN		 3690static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3691{
3e2f65d5
GN		 3692 /* The second termination condition only applies for REPE
3693 * and REPNE. Test if the repeat string operation prefix is
3694 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3695 * corresponding termination condition according to:
3696 * - if REPE/REPZ and ZF = 0 then done
3697 * - if REPNE/REPNZ and ZF = 1 then done
3698 */
9dac77fa
AK		 3699 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3700 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3701 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3702 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3703 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3704 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3705 return true;
3706
3707 return false;
3708}
3709
7b105ca2 3710int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3711{
9aabc88f 3712 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3713 u64 msr_data;
1b30eaa8 3714 int rc = X86EMUL_CONTINUE;
9dac77fa 3715 int saved_dst_type = ctxt->dst.type;
8b4caf66 3716
9dac77fa 3717 ctxt->mem_read.pos = 0;
310b5d30 3718
9dac77fa 3719 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3720 rc = emulate_ud(ctxt);
1161624f
GN		 3721 goto done;
3722 }
3723
d380a5e4 3724 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3725 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3726 rc = emulate_ud(ctxt);
d380a5e4
GN		 3727 goto done;
3728 }
3729
9dac77fa 3730 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3731 rc = emulate_ud(ctxt);
081bca0e
AK		 3732 goto done;
3733 }
3734
9dac77fa 3735 if ((ctxt->d & Sse)
717746e3
AK		 3736 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3737 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3738 rc = emulate_ud(ctxt);
3739 goto done;
3740 }
3741
9dac77fa 3742 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3743 rc = emulate_nm(ctxt);
3744 goto done;
3745 }
3746
9dac77fa
AK		 3747 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3748 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3749 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3750 if (rc != X86EMUL_CONTINUE)
3751 goto done;
3752 }
3753
e92805ac 3754 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3755 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3756 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3757 goto done;
3758 }
3759
8ea7d6ae 3760 /* Instruction can only be executed in protected mode */
9dac77fa 3761 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3762 rc = emulate_ud(ctxt);
3763 goto done;
3764 }
3765
d09beabd 3766 /* Do instruction specific permission checks */
9dac77fa
AK		 3767 if (ctxt->check_perm) {
3768 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3769 if (rc != X86EMUL_CONTINUE)
3770 goto done;
3771 }
3772
9dac77fa
AK		 3773 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3774 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3775 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3776 if (rc != X86EMUL_CONTINUE)
3777 goto done;
3778 }
3779
9dac77fa 3780 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3781 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3782 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3783 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3784 goto done;
3785 }
b9fa9d6b
AK		 3786 }
3787
9dac77fa
AK		 3788 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3789 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3790 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3791 if (rc != X86EMUL_CONTINUE)
8b4caf66 3792 goto done;
9dac77fa 3793 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3794 }
3795
9dac77fa
AK		 3796 if (ctxt->src2.type == OP_MEM) {
3797 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3798 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3799 if (rc != X86EMUL_CONTINUE)
3800 goto done;
3801 }
3802
9dac77fa 3803 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3804 goto special_insn;
3805
3806
9dac77fa 3807 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3808 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3809 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3810 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3811 if (rc != X86EMUL_CONTINUE)
3812 goto done;
038e51de 3813 }
9dac77fa 3814 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3815
018a98db
AK		 3816special_insn:
3817
9dac77fa
AK		 3818 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3819 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3820 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3821 if (rc != X86EMUL_CONTINUE)
3822 goto done;
3823 }
3824
9dac77fa
AK		 3825 if (ctxt->execute) {
3826 rc = ctxt->execute(ctxt);
ef65c889
AK		 3827 if (rc != X86EMUL_CONTINUE)
3828 goto done;
3829 goto writeback;
3830 }
3831
9dac77fa 3832 if (ctxt->twobyte)
6aa8b732
AK		 3833 goto twobyte_insn;
3834
9dac77fa 3835 switch (ctxt->b) {
0934ac9d 3836 case 0x06: /* push es */
7b105ca2 3837 rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
0934ac9d
MG		 3838 break;
3839 case 0x07: /* pop es */
7b105ca2 3840 rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
0934ac9d 3841 break;
0934ac9d 3842 case 0x0e: /* push cs */
7b105ca2 3843 rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
0934ac9d 3844 break;
0934ac9d 3845 case 0x16: /* push ss */
7b105ca2 3846 rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
0934ac9d
MG		 3847 break;
3848 case 0x17: /* pop ss */
7b105ca2 3849 rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
0934ac9d 3850 break;
0934ac9d 3851 case 0x1e: /* push ds */
7b105ca2 3852 rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
0934ac9d
MG		 3853 break;
3854 case 0x1f: /* pop ds */
7b105ca2 3855 rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
0934ac9d 3856 break;
33615aa9 3857 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3858 emulate_1op(ctxt, "inc");
33615aa9
AK		 3859 break;
3860 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3861 emulate_1op(ctxt, "dec");
33615aa9 3862 break;
6aa8b732 3863 case 0x63: /* movsxd */
8b4caf66 3864 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3865 goto cannot_emulate;
9dac77fa 3866 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3867 break;
018a98db
AK		 3868 case 0x6c: /* insb */
3869 case 0x6d: /* insw/insd */
9dac77fa 3870 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3871 goto do_io_in;
018a98db
AK		 3872 case 0x6e: /* outsb */
3873 case 0x6f: /* outsw/outsd */
9dac77fa 3874 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
a13a63fa 3875 goto do_io_out;
7972995b 3876 break;
b2833e3c 3877 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3878 if (test_cc(ctxt->b, ctxt->eflags))
3879 jmp_rel(ctxt, ctxt->src.val);
018a98db 3880 break;
7e0b54b1 3881 case 0x8d: /* lea r16/r32, m */
9dac77fa 3882 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3883 break;
6aa8b732 3884 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3885 rc = em_grp1a(ctxt);
6aa8b732 3886 break;
3d9e77df 3887 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3888 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3889 break;
e4f973ae
TY		 3890 rc = em_xchg(ctxt);
3891 break;
e8b6fa70 3892 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3893 switch (ctxt->op_bytes) {
3894 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3895 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3896 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3897 }
3898 break;
018a98db 3899 case 0xc0 ... 0xc1:
51187683 3900 rc = em_grp2(ctxt);
018a98db 3901 break;
09b5f4d3 3902 case 0xc4: /* les */
7b105ca2 3903 rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
09b5f4d3
WY		 3904 break;
3905 case 0xc5: /* lds */
7b105ca2 3906 rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
09b5f4d3 3907 break;
6e154e56 3908 case 0xcc: /* int3 */
5c5df76b
TY		 3909 rc = emulate_int(ctxt, 3);
3910 break;
6e154e56 3911 case 0xcd: /* int n */
9dac77fa 3912 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3913 break;
3914 case 0xce: /* into */
5c5df76b
TY		 3915 if (ctxt->eflags & EFLG_OF)
3916 rc = emulate_int(ctxt, 4);
6e154e56 3917 break;
018a98db 3918 case 0xd0 ... 0xd1: /* Grp2 */
51187683 3919 rc = em_grp2(ctxt);
018a98db
AK		 3920 break;
3921 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 3922 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 3923 rc = em_grp2(ctxt);
018a98db 3924 break;
a6a3034c
MG		 3925 case 0xe4: /* inb */
3926 case 0xe5: /* in */
cf8f70bf 3927 goto do_io_in;
a6a3034c
MG		 3928 case 0xe6: /* outb */
3929 case 0xe7: /* out */
cf8f70bf 3930 goto do_io_out;
1a52e051 3931 case 0xe8: /* call (near) */ {
9dac77fa
AK		 3932 long int rel = ctxt->src.val;
3933 ctxt->src.val = (unsigned long) ctxt->_eip;
3934 jmp_rel(ctxt, rel);
4487b3b4 3935 rc = em_push(ctxt);
8cdbd2c9 3936 break;
1a52e051
NK		 3937 }
3938 case 0xe9: /* jmp rel */
db5b0762 3939 case 0xeb: /* jmp rel short */
9dac77fa
AK		 3940 jmp_rel(ctxt, ctxt->src.val);
3941 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3942 break;
a6a3034c
MG		 3943 case 0xec: /* in al,dx */
3944 case 0xed: /* in (e/r)ax,dx */
cf8f70bf 3945 do_io_in:
9dac77fa
AK		 3946 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3947 &ctxt->dst.val))
cf8f70bf
GN		 3948 goto done; /* IO is needed */
3949 break;
ce7a0ad3
WY		 3950 case 0xee: /* out dx,al */
3951 case 0xef: /* out dx,(e/r)ax */
cf8f70bf 3952 do_io_out:
9dac77fa
AK		 3953 ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3954 &ctxt->src.val, 1);
3955 ctxt->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3956 break;
111de5d6 3957 case 0xf4: /* hlt */
6c3287f7 3958 ctxt->ops->halt(ctxt);
19fdfa0d 3959 break;
111de5d6
AK		 3960 case 0xf5: /* cmc */
3961 /* complement carry flag from eflags reg */
3962 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 3963 break;
3964 case 0xf8: /* clc */
3965 ctxt->eflags &= ~EFLG_CF;
111de5d6 3966 break;
8744aa9a
MG		 3967 case 0xf9: /* stc */
3968 ctxt->eflags |= EFLG_CF;
3969 break;
fb4616f4
MG		 3970 case 0xfc: /* cld */
3971 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3972 break;
3973 case 0xfd: /* std */
3974 ctxt->eflags |= EFLG_DF;
fb4616f4 3975 break;
ea79849d 3976 case 0xfe: /* Grp4 */
51187683 3977 rc = em_grp45(ctxt);
018a98db 3978 break;
ea79849d 3979 case 0xff: /* Grp5 */
51187683
TY		 3980 rc = em_grp45(ctxt);
3981 break;
91269b8f
AK		 3982 default:
3983 goto cannot_emulate;
6aa8b732 3984 }
018a98db 3985
7d9ddaed
AK		 3986 if (rc != X86EMUL_CONTINUE)
3987 goto done;
3988
018a98db 3989writeback:
adddcecf 3990 rc = writeback(ctxt);
1b30eaa8 3991 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3992 goto done;
3993
5cd21917
GN		 3994 /*
3995 * restore dst type in case the decoding will be reused
3996 * (happens for string instruction )
3997 */
9dac77fa 3998 ctxt->dst.type = saved_dst_type;
5cd21917 3999
9dac77fa
AK		 4000 if ((ctxt->d & SrcMask) == SrcSI)
4001 string_addr_inc(ctxt, seg_override(ctxt),
4002 VCPU_REGS_RSI, &ctxt->src);
a682e354 4003
9dac77fa 4004 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4005 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4006 &ctxt->dst);
d9271123 4007
9dac77fa
AK		 4008 if (ctxt->rep_prefix && (ctxt->d & String)) {
4009 struct read_cache *r = &ctxt->io_read;
4010 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4011
d2ddd1c4
GN		 4012 if (!string_insn_completed(ctxt)) {
4013 /*
4014 * Re-enter guest when pio read ahead buffer is empty
4015 * or, if it is not used, after each 1024 iteration.
4016 */
9dac77fa 4017 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4018 (r->end == 0 || r->end != r->pos)) {
4019 /*
4020 * Reset read cache. Usually happens before
4021 * decode, but since instruction is restarted
4022 * we have to do it here.
4023 */
9dac77fa 4024 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4025 return EMULATION_RESTART;
4026 }
4027 goto done; /* skip rip writeback */
0fa6ccbd 4028 }
5cd21917 4029 }
d2ddd1c4 4030
9dac77fa 4031 ctxt->eip = ctxt->_eip;
018a98db
AK		 4032
4033done:
da9cb575
AK		 4034 if (rc == X86EMUL_PROPAGATE_FAULT)
4035 ctxt->have_exception = true;
775fde86
JR		 4036 if (rc == X86EMUL_INTERCEPTED)
4037 return EMULATION_INTERCEPTED;
4038
d2ddd1c4 4039 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4040
4041twobyte_insn:
9dac77fa 4042 switch (ctxt->b) {
018a98db 4043 case 0x09: /* wbinvd */
cfb22375 4044 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4045 break;
4046 case 0x08: /* invd */
018a98db
AK		 4047 case 0x0d: /* GrpP (prefetch) */
4048 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4049 break;
4050 case 0x20: /* mov cr, reg */
9dac77fa 4051 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4052 break;
6aa8b732 4053 case 0x21: /* mov from dr to reg */
9dac77fa 4054 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4055 break;
018a98db 4056 case 0x22: /* mov reg, cr */
9dac77fa 4057 if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
54b8486f 4058 emulate_gp(ctxt, 0);
da9cb575 4059 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4060 goto done;
4061 }
9dac77fa 4062 ctxt->dst.type = OP_NONE;
018a98db 4063 break;
6aa8b732 4064 case 0x23: /* mov from reg to dr */
9dac77fa 4065 if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
338dbc97 4066 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4067 ~0ULL : ~0U)) < 0) {
338dbc97 4068 /* #UD condition is already handled by the code above */
54b8486f 4069 emulate_gp(ctxt, 0);
da9cb575 4070 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4071 goto done;
4072 }
4073
9dac77fa 4074 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4075 break;
018a98db
AK		 4076 case 0x30:
4077 /* wrmsr */
9dac77fa
AK		 4078 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4079 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4080 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4081 emulate_gp(ctxt, 0);
da9cb575 4082 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4083 goto done;
018a98db
AK		 4084 }
4085 rc = X86EMUL_CONTINUE;
018a98db
AK		 4086 break;
4087 case 0x32:
4088 /* rdmsr */
9dac77fa 4089 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4090 emulate_gp(ctxt, 0);
da9cb575 4091 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4092 goto done;
018a98db 4093 } else {
9dac77fa
AK		 4094 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4095 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4096 }
4097 rc = X86EMUL_CONTINUE;
018a98db 4098 break;
6aa8b732 4099 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4100 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4101 if (!test_cc(ctxt->b, ctxt->eflags))
4102 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4103 break;
b2833e3c 4104 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4105 if (test_cc(ctxt->b, ctxt->eflags))
4106 jmp_rel(ctxt, ctxt->src.val);
018a98db 4107 break;
ee45b58e 4108 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4109 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4110 break;
0934ac9d 4111 case 0xa0: /* push fs */
7b105ca2 4112 rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
0934ac9d
MG		 4113 break;
4114 case 0xa1: /* pop fs */
7b105ca2 4115 rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
0934ac9d 4116 break;
7de75248
NK		 4117 case 0xa3:
4118 bt: /* bt */
9dac77fa 4119 ctxt->dst.type = OP_NONE;
e4e03ded 4120 /* only subword offset */
9dac77fa 4121 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
a31b9cea 4122 emulate_2op_SrcV_nobyte(ctxt, "bt");
7de75248 4123 break;
9bf8ea42
GT		 4124 case 0xa4: /* shld imm8, r, r/m */
4125 case 0xa5: /* shld cl, r, r/m */
761441b9 4126 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4127 break;
0934ac9d 4128 case 0xa8: /* push gs */
7b105ca2 4129 rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
0934ac9d
MG		 4130 break;
4131 case 0xa9: /* pop gs */
7b105ca2 4132 rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
0934ac9d 4133 break;
7de75248
NK		 4134 case 0xab:
4135 bts: /* bts */
a31b9cea 4136 emulate_2op_SrcV_nobyte(ctxt, "bts");
7de75248 4137 break;
9bf8ea42
GT		 4138 case 0xac: /* shrd imm8, r, r/m */
4139 case 0xad: /* shrd cl, r, r/m */
761441b9 4140 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4141 break;
2a7c5b8b
GC		 4142 case 0xae: /* clflush */
4143 break;
6aa8b732
AK		 4144 case 0xb0 ... 0xb1: /* cmpxchg */
4145 /*
4146 * Save real source value, then compare EAX against
4147 * destination.
4148 */
9dac77fa
AK		 4149 ctxt->src.orig_val = ctxt->src.val;
4150 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4151 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4152 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4153 /* Success: write back to memory. */
9dac77fa 4154 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4155 } else {
4156 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4157 ctxt->dst.type = OP_REG;
4158 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4159 }
4160 break;
09b5f4d3 4161 case 0xb2: /* lss */
7b105ca2 4162 rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
09b5f4d3 4163 break;
6aa8b732
AK		 4164 case 0xb3:
4165 btr: /* btr */
a31b9cea 4166 emulate_2op_SrcV_nobyte(ctxt, "btr");
6aa8b732 4167 break;
09b5f4d3 4168 case 0xb4: /* lfs */
7b105ca2 4169 rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
09b5f4d3
WY		 4170 break;
4171 case 0xb5: /* lgs */
7b105ca2 4172 rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
09b5f4d3 4173 break;
6aa8b732 4174 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4175 ctxt->dst.bytes = ctxt->op_bytes;
4176 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4177 : (u16) ctxt->src.val;
6aa8b732 4178 break;
6aa8b732 4179 case 0xba: /* Grp8 */
9dac77fa 4180 switch (ctxt->modrm_reg & 3) {
6aa8b732
AK		 4181 case 0:
4182 goto bt;
4183 case 1:
4184 goto bts;
4185 case 2:
4186 goto btr;
4187 case 3:
4188 goto btc;
4189 }
4190 break;
7de75248
NK		 4191 case 0xbb:
4192 btc: /* btc */
a31b9cea 4193 emulate_2op_SrcV_nobyte(ctxt, "btc");
7de75248 4194 break;
d9574a25
WY		 4195 case 0xbc: { /* bsf */
4196 u8 zf;
4197 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4198 : "=r"(ctxt->dst.val), "=q"(zf)
4199 : "r"(ctxt->src.val));
d9574a25
WY		 4200 ctxt->eflags &= ~X86_EFLAGS_ZF;
4201 if (zf) {
4202 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4203 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4204 }
4205 break;
4206 }
4207 case 0xbd: { /* bsr */
4208 u8 zf;
4209 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4210 : "=r"(ctxt->dst.val), "=q"(zf)
4211 : "r"(ctxt->src.val));
d9574a25
WY		 4212 ctxt->eflags &= ~X86_EFLAGS_ZF;
4213 if (zf) {
4214 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4215 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4216 }
4217 break;
4218 }
6aa8b732 4219 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4220 ctxt->dst.bytes = ctxt->op_bytes;
4221 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4222 (s16) ctxt->src.val;
6aa8b732 4223 break;
92f738a5 4224 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4225 emulate_2op_SrcV(ctxt, "add");
92f738a5 4226 /* Write back the register source. */
9dac77fa
AK		 4227 ctxt->src.val = ctxt->dst.orig_val;
4228 write_register_operand(&ctxt->src);
92f738a5 4229 break;
a012e65a 4230 case 0xc3: /* movnti */
9dac77fa
AK		 4231 ctxt->dst.bytes = ctxt->op_bytes;
4232 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4233 (u64) ctxt->src.val;
a012e65a 4234 break;
6aa8b732 4235 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4236 rc = em_grp9(ctxt);
8cdbd2c9 4237 break;
91269b8f
AK		 4238 default:
4239 goto cannot_emulate;
6aa8b732 4240 }
7d9ddaed
AK		 4241
4242 if (rc != X86EMUL_CONTINUE)
4243 goto done;
4244
6aa8b732
AK		 4245 goto writeback;
4246
4247cannot_emulate:
a0c0ab2f 4248 return EMULATION_FAILED;
6aa8b732 4249}
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