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KVM: x86 emulator: add get_cached_segment_base() callback to x86_emulate_ops
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
38ba30ba 36#include "tss.h"
e99f0507 37
6aa8b732
AK		 38/*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47/* Operand sizes: 8-bit operands or specified/overridden size. */
48#define ByteOp (1<<0) /* 8-bit operands. */
49/* Destination operand type. */
50#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51#define DstReg (2<<1) /* Register operand. */
52#define DstMem (3<<1) /* Memory operand. */
9c9fddd0 53#define DstAcc (4<<1) /* Destination Accumulator */
a682e354 54#define DstDI (5<<1) /* Destination is in ES:(E)DI */
6550e1f1 55#define DstMem64 (6<<1) /* 64bit memory operand */
9c9fddd0 56#define DstMask (7<<1)
6aa8b732 57/* Source operand type. */
9c9fddd0
GT		 58#define SrcNone (0<<4) /* No source operand. */
59#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
60#define SrcReg (1<<4) /* Register operand. */
61#define SrcMem (2<<4) /* Memory operand. */
62#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
63#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
64#define SrcImm (5<<4) /* Immediate operand. */
65#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 66#define SrcOne (7<<4) /* Implied '1' */
341de7e3 67#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 68#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 69#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 70#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
71#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
341de7e3 72#define SrcMask (0xf<<4)
6aa8b732 73/* Generic ModRM decode. */
341de7e3 74#define ModRM (1<<8)
6aa8b732 75/* Destination is only written; never read. */
341de7e3
GN		 76#define Mov (1<<9)
77#define BitOp (1<<10)
78#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 79#define String (1<<12) /* String instruction (rep capable) */
80#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 81#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
82#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
83#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 84/* Misc flags */
d380a5e4 85#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 86#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 87#define No64 (1<<28)
0dc8d10f
GT		 88/* Source 2 operand type */
89#define Src2None (0<<29)
90#define Src2CL (1<<29)
91#define Src2ImmByte (2<<29)
92#define Src2One (3<<29)
93#define Src2Mask (7<<29)
6aa8b732 94
43bb19cd 95enum {
1d6ad207 96 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 97 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 98 Group8, Group9,
43bb19cd
AK		 99};
100
45ed60b3 101static u32 opcode_table[256] = {
6aa8b732 102 /* 0x00 - 0x07 */
d380a5e4 103 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 105 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 106 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 107 /* 0x08 - 0x0F */
d380a5e4 108 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 110 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
111 ImplicitOps | Stack | No64, 0,
6aa8b732 112 /* 0x10 - 0x17 */
d380a5e4 113 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 115 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 116 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 117 /* 0x18 - 0x1F */
d380a5e4 118 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 120 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 121 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 122 /* 0x20 - 0x27 */
d380a5e4 123 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 124 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 125 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 126 /* 0x28 - 0x2F */
d380a5e4 127 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 128 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
129 0, 0, 0, 0,
130 /* 0x30 - 0x37 */
d380a5e4 131 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 132 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
133 0, 0, 0, 0,
134 /* 0x38 - 0x3F */
135 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
136 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 137 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
138 0, 0,
d77a2507 139 /* 0x40 - 0x47 */
33615aa9 140 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 141 /* 0x48 - 0x4F */
33615aa9 142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 143 /* 0x50 - 0x57 */
6e3d5dfb
AK		 144 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
145 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 146 /* 0x58 - 0x5F */
6e3d5dfb
AK		 147 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
148 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 149 /* 0x60 - 0x67 */
abcf14b5
MG		 150 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
151 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 152 0, 0, 0, 0,
153 /* 0x68 - 0x6F */
91ed7a0e 154 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 155 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
156 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
55bebde4 157 /* 0x70 - 0x77 */
b2833e3c
GN		 158 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
159 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 160 /* 0x78 - 0x7F */
b2833e3c
GN		 161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
162 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 163 /* 0x80 - 0x87 */
1d6ad207
AK		 164 Group | Group1_80, Group | Group1_81,
165 Group | Group1_82, Group | Group1_83,
6aa8b732 166 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 167 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 168 /* 0x88 - 0x8F */
169 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
170 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 171 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
054fe9f6 172 ImplicitOps | SrcMem | ModRM, Group | Group1A,
b13354f8
MG		 173 /* 0x90 - 0x97 */
174 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
175 /* 0x98 - 0x9F */
414e6277 176 0, 0, SrcImmFAddr | No64, 0,
0654169e 177 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 178 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 179 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
180 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
a682e354
GN		 181 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
182 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 183 /* 0xA8 - 0xAF */
a682e354
GN		 184 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
185 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
186 ByteOp | DstDI | String, DstDI | String,
a5e2e82b
MG		 187 /* 0xB0 - 0xB7 */
188 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
189 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 /* 0xB8 - 0xBF */
193 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
194 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 197 /* 0xC0 - 0xC7 */
d9413cd7 198 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 199 0, ImplicitOps | Stack, 0, 0,
d9413cd7 200 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 201 /* 0xC8 - 0xCF */
e637b823 202 0, 0, 0, ImplicitOps | Stack,
d8769fed 203 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 204 /* 0xD0 - 0xD7 */
205 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
206 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
207 0, 0, 0, 0,
208 /* 0xD8 - 0xDF */
209 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 210 /* 0xE0 - 0xE7 */
a6a3034c 211 0, 0, 0, 0,
cf8f70bf
GN		 212 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
213 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 214 /* 0xE8 - 0xEF */
d53c4777 215 SrcImm | Stack, SrcImm | ImplicitOps,
414e6277 216 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 217 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
218 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 219 /* 0xF0 - 0xF7 */
220 0, 0, 0, 0,
e92805ac 221 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 222 /* 0xF8 - 0xFF */
b284be57 223 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 224 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 225};
226
45ed60b3 227static u32 twobyte_table[256] = {
6aa8b732 228 /* 0x00 - 0x0F */
e92805ac
GN		 229 0, Group | GroupDual | Group7, 0, 0,
230 0, ImplicitOps, ImplicitOps | Priv, 0,
231 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
232 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 233 /* 0x10 - 0x1F */
234 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x20 - 0x2F */
e92805ac
GN		 236 ModRM | ImplicitOps | Priv, ModRM | Priv,
237 ModRM | ImplicitOps | Priv, ModRM | Priv,
238 0, 0, 0, 0,
6aa8b732
AK		 239 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0x30 - 0x3F */
e92805ac
GN		 241 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
242 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 243 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 244 /* 0x40 - 0x47 */
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 /* 0x48 - 0x4F */
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 /* 0x50 - 0x5F */
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
256 /* 0x60 - 0x6F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x70 - 0x7F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x80 - 0x8F */
b2833e3c
GN		 261 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
262 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 263 /* 0x90 - 0x9F */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xA0 - 0xA7 */
0934ac9d
MG		 266 ImplicitOps | Stack, ImplicitOps | Stack,
267 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 268 DstMem | SrcReg | Src2ImmByte | ModRM,
269 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 270 /* 0xA8 - 0xAF */
0934ac9d 271 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 272 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 273 DstMem | SrcReg | Src2ImmByte | ModRM,
274 DstMem | SrcReg | Src2CL | ModRM,
275 ModRM, 0,
6aa8b732 276 /* 0xB0 - 0xB7 */
d380a5e4
GN		 277 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
278 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 279 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
280 DstReg | SrcMem16 | ModRM | Mov,
281 /* 0xB8 - 0xBF */
d380a5e4
GN		 282 0, 0,
283 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 284 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
285 DstReg | SrcMem16 | ModRM | Mov,
286 /* 0xC0 - 0xCF */
60a29d4e
GN		 287 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
288 0, 0, 0, Group | GroupDual | Group9,
a012e65a 289 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 290 /* 0xD0 - 0xDF */
291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
292 /* 0xE0 - 0xEF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xF0 - 0xFF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
296};
297
45ed60b3 298static u32 group_table[] = {
1d6ad207 299 [Group1_80*8] =
d380a5e4
GN		 300 ByteOp | DstMem | SrcImm | ModRM | Lock,
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 308 [Group1_81*8] =
d380a5e4
GN		 309 DstMem | SrcImm | ModRM | Lock,
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM,
1d6ad207 317 [Group1_82*8] =
e424e191
GN		 318 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 326 [Group1_83*8] =
d380a5e4
GN		 327 DstMem | SrcImmByte | ModRM | Lock,
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 335 [Group1A*8] =
336 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 337 [Group3_Byte*8] =
338 ByteOp | SrcImm | DstMem | ModRM, 0,
339 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
340 0, 0, 0, 0,
341 [Group3*8] =
41afa025 342 DstMem | SrcImm | ModRM, 0,
6eb06cb2 343 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 344 0, 0, 0, 0,
fd60754e
AK		 345 [Group4*8] =
346 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
347 0, 0, 0, 0, 0, 0,
348 [Group5*8] =
d19292e4
MG		 349 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
350 SrcMem | ModRM | Stack, 0,
414e6277 351 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
ea79849d 352 SrcMem | ModRM | Stack, 0,
d95058a1 353 [Group7*8] =
e92805ac 354 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 355 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 356 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 357 [Group8*8] =
358 0, 0, 0, 0,
d380a5e4
GN		 359 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
360 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 361 [Group9*8] =
6550e1f1 362 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 363};
364
45ed60b3 365static u32 group2_table[] = {
d95058a1 366 [Group7*8] =
835e6b80 367 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 368 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 369 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 370 [Group9*8] =
371 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 372};
373
6aa8b732 374/* EFLAGS bit definitions. */
d4c6a154
GN		 375#define EFLG_ID (1<<21)
376#define EFLG_VIP (1<<20)
377#define EFLG_VIF (1<<19)
378#define EFLG_AC (1<<18)
b1d86143
AP		 379#define EFLG_VM (1<<17)
380#define EFLG_RF (1<<16)
d4c6a154
GN		 381#define EFLG_IOPL (3<<12)
382#define EFLG_NT (1<<14)
6aa8b732
AK		 383#define EFLG_OF (1<<11)
384#define EFLG_DF (1<<10)
b1d86143 385#define EFLG_IF (1<<9)
d4c6a154 386#define EFLG_TF (1<<8)
6aa8b732
AK		 387#define EFLG_SF (1<<7)
388#define EFLG_ZF (1<<6)
389#define EFLG_AF (1<<4)
390#define EFLG_PF (1<<2)
391#define EFLG_CF (1<<0)
392
393/*
394 * Instruction emulation:
395 * Most instructions are emulated directly via a fragment of inline assembly
396 * code. This allows us to save/restore EFLAGS and thus very easily pick up
397 * any modified flags.
398 */
399
05b3e0c2 400#if defined(CONFIG_X86_64)
6aa8b732
AK		 401#define _LO32 "k" /* force 32-bit operand */
402#define _STK "%%rsp" /* stack pointer */
403#elif defined(__i386__)
404#define _LO32 "" /* force 32-bit operand */
405#define _STK "%%esp" /* stack pointer */
406#endif
407
408/*
409 * These EFLAGS bits are restored from saved value during emulation, and
410 * any changes are written back to the saved value after emulation.
411 */
412#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
413
414/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 415#define _PRE_EFLAGS(_sav, _msk, _tmp) \
416 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
417 "movl %"_sav",%"_LO32 _tmp"; " \
418 "push %"_tmp"; " \
419 "push %"_tmp"; " \
420 "movl %"_msk",%"_LO32 _tmp"; " \
421 "andl %"_LO32 _tmp",("_STK"); " \
422 "pushf; " \
423 "notl %"_LO32 _tmp"; " \
424 "andl %"_LO32 _tmp",("_STK"); " \
425 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
426 "pop %"_tmp"; " \
427 "orl %"_LO32 _tmp",("_STK"); " \
428 "popf; " \
429 "pop %"_sav"; "
6aa8b732
AK		 430
431/* After executing instruction: write-back necessary bits in EFLAGS. */
432#define _POST_EFLAGS(_sav, _msk, _tmp) \
433 /* _sav |= EFLAGS & _msk; */ \
434 "pushf; " \
435 "pop %"_tmp"; " \
436 "andl %"_msk",%"_LO32 _tmp"; " \
437 "orl %"_LO32 _tmp",%"_sav"; "
438
dda96d8f
AK		 439#ifdef CONFIG_X86_64
440#define ON64(x) x
441#else
442#define ON64(x)
443#endif
444
6b7ad61f
AK		 445#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
446 do { \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "4", "2") \
449 _op _suffix " %"_x"3,%1; " \
450 _POST_EFLAGS("0", "4", "2") \
451 : "=m" (_eflags), "=m" ((_dst).val), \
452 "=&r" (_tmp) \
453 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 454 } while (0)
6b7ad61f
AK		 455
456
6aa8b732
AK		 457/* Raw emulation: instruction has two explicit operands. */
458#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 459 do { \
460 unsigned long _tmp; \
461 \
462 switch ((_dst).bytes) { \
463 case 2: \
464 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
465 break; \
466 case 4: \
467 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
468 break; \
469 case 8: \
470 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
471 break; \
472 } \
6aa8b732
AK		 473 } while (0)
474
475#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
476 do { \
6b7ad61f 477 unsigned long _tmp; \
d77c26fc 478 switch ((_dst).bytes) { \
6aa8b732 479 case 1: \
6b7ad61f 480 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 481 break; \
482 default: \
483 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
484 _wx, _wy, _lx, _ly, _qx, _qy); \
485 break; \
486 } \
487 } while (0)
488
489/* Source operand is byte-sized and may be restricted to just %cl. */
490#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
491 __emulate_2op(_op, _src, _dst, _eflags, \
492 "b", "c", "b", "c", "b", "c", "b", "c")
493
494/* Source operand is byte, word, long or quad sized. */
495#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
496 __emulate_2op(_op, _src, _dst, _eflags, \
497 "b", "q", "w", "r", _LO32, "r", "", "r")
498
499/* Source operand is word, long or quad sized. */
500#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
501 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
502 "w", "r", _LO32, "r", "", "r")
503
d175226a
GT		 504/* Instruction has three operands and one operand is stored in ECX register */
505#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
506 do { \
507 unsigned long _tmp; \
508 _type _clv = (_cl).val; \
509 _type _srcv = (_src).val; \
510 _type _dstv = (_dst).val; \
511 \
512 __asm__ __volatile__ ( \
513 _PRE_EFLAGS("0", "5", "2") \
514 _op _suffix " %4,%1 \n" \
515 _POST_EFLAGS("0", "5", "2") \
516 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
517 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
518 ); \
519 \
520 (_cl).val = (unsigned long) _clv; \
521 (_src).val = (unsigned long) _srcv; \
522 (_dst).val = (unsigned long) _dstv; \
523 } while (0)
524
525#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
526 do { \
527 switch ((_dst).bytes) { \
528 case 2: \
529 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
530 "w", unsigned short); \
531 break; \
532 case 4: \
533 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
534 "l", unsigned int); \
535 break; \
536 case 8: \
537 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
538 "q", unsigned long)); \
539 break; \
540 } \
541 } while (0)
542
dda96d8f 543#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 544 do { \
545 unsigned long _tmp; \
546 \
dda96d8f
AK		 547 __asm__ __volatile__ ( \
548 _PRE_EFLAGS("0", "3", "2") \
549 _op _suffix " %1; " \
550 _POST_EFLAGS("0", "3", "2") \
551 : "=m" (_eflags), "+m" ((_dst).val), \
552 "=&r" (_tmp) \
553 : "i" (EFLAGS_MASK)); \
554 } while (0)
555
556/* Instruction has only one explicit operand (no source operand). */
557#define emulate_1op(_op, _dst, _eflags) \
558 do { \
d77c26fc 559 switch ((_dst).bytes) { \
dda96d8f
AK		 560 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
561 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
562 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
563 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 564 } \
565 } while (0)
566
6aa8b732
AK		 567/* Fetch next part of the instruction being emulated. */
568#define insn_fetch(_type, _size, _eip) \
569({ unsigned long _x; \
62266869 570 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 571 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 572 goto done; \
573 (_eip) += (_size); \
574 (_type)_x; \
575})
576
414e6277
GN		 577#define insn_fetch_arr(_arr, _size, _eip) \
578({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
579 if (rc != X86EMUL_CONTINUE) \
580 goto done; \
581 (_eip) += (_size); \
582})
583
ddcb2885
HH		 584static inline unsigned long ad_mask(struct decode_cache *c)
585{
586 return (1UL << (c->ad_bytes << 3)) - 1;
587}
588
6aa8b732 589/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 590static inline unsigned long
591address_mask(struct decode_cache *c, unsigned long reg)
592{
593 if (c->ad_bytes == sizeof(unsigned long))
594 return reg;
595 else
596 return reg & ad_mask(c);
597}
598
599static inline unsigned long
600register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
601{
602 return base + address_mask(c, reg);
603}
604
7a957275
HH		 605static inline void
606register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
607{
608 if (c->ad_bytes == sizeof(unsigned long))
609 *reg += inc;
610 else
611 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
612}
6aa8b732 613
7a957275
HH		 614static inline void jmp_rel(struct decode_cache *c, int rel)
615{
616 register_address_increment(c, &c->eip, rel);
617}
098c937b 618
7a5b56df
AK		 619static void set_seg_override(struct decode_cache *c, int seg)
620{
621 c->has_seg_override = true;
622 c->seg_override = seg;
623}
624
625static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
626{
627 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
628 return 0;
629
630 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
631}
632
633static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
634 struct decode_cache *c)
635{
636 if (!c->has_seg_override)
637 return 0;
638
639 return seg_base(ctxt, c->seg_override);
640}
641
642static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
643{
644 return seg_base(ctxt, VCPU_SREG_ES);
645}
646
647static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
648{
649 return seg_base(ctxt, VCPU_SREG_SS);
650}
651
62266869
AK		 652static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
653 struct x86_emulate_ops *ops,
2fb53ad8 654 unsigned long eip, u8 *dest)
62266869
AK		 655{
656 struct fetch_cache *fc = &ctxt->decode.fetch;
657 int rc;
2fb53ad8 658 int size, cur_size;
62266869 659
2fb53ad8
AK		 660 if (eip == fc->end) {
661 cur_size = fc->end - fc->start;
662 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
663 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
664 size, ctxt->vcpu, NULL);
3e2815e9 665 if (rc != X86EMUL_CONTINUE)
62266869 666 return rc;
2fb53ad8 667 fc->end += size;
62266869 668 }
2fb53ad8 669 *dest = fc->data[eip - fc->start];
3e2815e9 670 return X86EMUL_CONTINUE;
62266869
AK		 671}
672
673static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
674 struct x86_emulate_ops *ops,
675 unsigned long eip, void *dest, unsigned size)
676{
3e2815e9 677 int rc;
62266869 678
eb3c79e6 679 /* x86 instructions are limited to 15 bytes. */
063db061 680 if (eip + size - ctxt->eip > 15)
eb3c79e6 681 return X86EMUL_UNHANDLEABLE;
62266869
AK		 682 while (size--) {
683 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 684 if (rc != X86EMUL_CONTINUE)
62266869
AK		 685 return rc;
686 }
3e2815e9 687 return X86EMUL_CONTINUE;
62266869
AK		 688}
689
1e3c5cb0
RR		 690/*
691 * Given the 'reg' portion of a ModRM byte, and a register block, return a
692 * pointer into the block that addresses the relevant register.
693 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
694 */
695static void *decode_register(u8 modrm_reg, unsigned long *regs,
696 int highbyte_regs)
6aa8b732
AK		 697{
698 void *p;
699
700 p = &regs[modrm_reg];
701 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
702 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
703 return p;
704}
705
706static int read_descriptor(struct x86_emulate_ctxt *ctxt,
707 struct x86_emulate_ops *ops,
708 void *ptr,
709 u16 *size, unsigned long *address, int op_bytes)
710{
711 int rc;
712
713 if (op_bytes == 2)
714 op_bytes = 3;
715 *address = 0;
cebff02b 716 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 717 ctxt->vcpu, NULL);
1b30eaa8 718 if (rc != X86EMUL_CONTINUE)
6aa8b732 719 return rc;
cebff02b 720 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 721 ctxt->vcpu, NULL);
6aa8b732
AK		 722 return rc;
723}
724
bbe9abbd
NK		 725static int test_cc(unsigned int condition, unsigned int flags)
726{
727 int rc = 0;
728
729 switch ((condition & 15) >> 1) {
730 case 0: /* o */
731 rc |= (flags & EFLG_OF);
732 break;
733 case 1: /* b/c/nae */
734 rc |= (flags & EFLG_CF);
735 break;
736 case 2: /* z/e */
737 rc |= (flags & EFLG_ZF);
738 break;
739 case 3: /* be/na */
740 rc |= (flags & (EFLG_CF|EFLG_ZF));
741 break;
742 case 4: /* s */
743 rc |= (flags & EFLG_SF);
744 break;
745 case 5: /* p/pe */
746 rc |= (flags & EFLG_PF);
747 break;
748 case 7: /* le/ng */
749 rc |= (flags & EFLG_ZF);
750 /* fall through */
751 case 6: /* l/nge */
752 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
753 break;
754 }
755
756 /* Odd condition identifiers (lsb == 1) have inverted sense. */
757 return (!!rc ^ (condition & 1));
758}
759
3c118e24
AK		 760static void decode_register_operand(struct operand *op,
761 struct decode_cache *c,
3c118e24
AK		 762 int inhibit_bytereg)
763{
33615aa9 764 unsigned reg = c->modrm_reg;
9f1ef3f8 765 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 766
767 if (!(c->d & ModRM))
768 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 769 op->type = OP_REG;
770 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 771 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 772 op->val = *(u8 *)op->ptr;
773 op->bytes = 1;
774 } else {
33615aa9 775 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 776 op->bytes = c->op_bytes;
777 switch (op->bytes) {
778 case 2:
779 op->val = *(u16 *)op->ptr;
780 break;
781 case 4:
782 op->val = *(u32 *)op->ptr;
783 break;
784 case 8:
785 op->val = *(u64 *) op->ptr;
786 break;
787 }
788 }
789 op->orig_val = op->val;
790}
791
1c73ef66
AK		 792static int decode_modrm(struct x86_emulate_ctxt *ctxt,
793 struct x86_emulate_ops *ops)
794{
795 struct decode_cache *c = &ctxt->decode;
796 u8 sib;
f5b4edcd 797 int index_reg = 0, base_reg = 0, scale;
3e2815e9 798 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 799
800 if (c->rex_prefix) {
801 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
802 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
803 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
804 }
805
806 c->modrm = insn_fetch(u8, 1, c->eip);
807 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
808 c->modrm_reg |= (c->modrm & 0x38) >> 3;
809 c->modrm_rm |= (c->modrm & 0x07);
810 c->modrm_ea = 0;
811 c->use_modrm_ea = 1;
812
813 if (c->modrm_mod == 3) {
107d6d2e
AK		 814 c->modrm_ptr = decode_register(c->modrm_rm,
815 c->regs, c->d & ByteOp);
816 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 817 return rc;
818 }
819
820 if (c->ad_bytes == 2) {
821 unsigned bx = c->regs[VCPU_REGS_RBX];
822 unsigned bp = c->regs[VCPU_REGS_RBP];
823 unsigned si = c->regs[VCPU_REGS_RSI];
824 unsigned di = c->regs[VCPU_REGS_RDI];
825
826 /* 16-bit ModR/M decode. */
827 switch (c->modrm_mod) {
828 case 0:
829 if (c->modrm_rm == 6)
830 c->modrm_ea += insn_fetch(u16, 2, c->eip);
831 break;
832 case 1:
833 c->modrm_ea += insn_fetch(s8, 1, c->eip);
834 break;
835 case 2:
836 c->modrm_ea += insn_fetch(u16, 2, c->eip);
837 break;
838 }
839 switch (c->modrm_rm) {
840 case 0:
841 c->modrm_ea += bx + si;
842 break;
843 case 1:
844 c->modrm_ea += bx + di;
845 break;
846 case 2:
847 c->modrm_ea += bp + si;
848 break;
849 case 3:
850 c->modrm_ea += bp + di;
851 break;
852 case 4:
853 c->modrm_ea += si;
854 break;
855 case 5:
856 c->modrm_ea += di;
857 break;
858 case 6:
859 if (c->modrm_mod != 0)
860 c->modrm_ea += bp;
861 break;
862 case 7:
863 c->modrm_ea += bx;
864 break;
865 }
866 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
867 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 868 if (!c->has_seg_override)
869 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 870 c->modrm_ea = (u16)c->modrm_ea;
871 } else {
872 /* 32/64-bit ModR/M decode. */
84411d85 873 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 874 sib = insn_fetch(u8, 1, c->eip);
875 index_reg |= (sib >> 3) & 7;
876 base_reg |= sib & 7;
877 scale = sib >> 6;
878
dc71d0f1
AK		 879 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
880 c->modrm_ea += insn_fetch(s32, 4, c->eip);
881 else
1c73ef66 882 c->modrm_ea += c->regs[base_reg];
dc71d0f1 883 if (index_reg != 4)
1c73ef66 884 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 885 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
886 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 887 c->rip_relative = 1;
84411d85 888 } else
1c73ef66 889 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 890 switch (c->modrm_mod) {
891 case 0:
892 if (c->modrm_rm == 5)
893 c->modrm_ea += insn_fetch(s32, 4, c->eip);
894 break;
895 case 1:
896 c->modrm_ea += insn_fetch(s8, 1, c->eip);
897 break;
898 case 2:
899 c->modrm_ea += insn_fetch(s32, 4, c->eip);
900 break;
901 }
902 }
1c73ef66
AK		 903done:
904 return rc;
905}
906
907static int decode_abs(struct x86_emulate_ctxt *ctxt,
908 struct x86_emulate_ops *ops)
909{
910 struct decode_cache *c = &ctxt->decode;
3e2815e9 911 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 912
913 switch (c->ad_bytes) {
914 case 2:
915 c->modrm_ea = insn_fetch(u16, 2, c->eip);
916 break;
917 case 4:
918 c->modrm_ea = insn_fetch(u32, 4, c->eip);
919 break;
920 case 8:
921 c->modrm_ea = insn_fetch(u64, 8, c->eip);
922 break;
923 }
924done:
925 return rc;
926}
927
6aa8b732 928int
8b4caf66 929x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 930{
e4e03ded 931 struct decode_cache *c = &ctxt->decode;
3e2815e9 932 int rc = X86EMUL_CONTINUE;
6aa8b732 933 int mode = ctxt->mode;
e09d082c 934 int def_op_bytes, def_ad_bytes, group;
6aa8b732 935
6aa8b732 936
5cd21917
GN		 937 /* we cannot decode insn before we complete previous rep insn */
938 WARN_ON(ctxt->restart);
939
940 /* Shadow copy of register state. Committed on successful emulation. */
e4e03ded 941 memset(c, 0, sizeof(struct decode_cache));
063db061 942 c->eip = ctxt->eip;
2fb53ad8 943 c->fetch.start = c->fetch.end = c->eip;
7a5b56df 944 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 945 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 946
947 switch (mode) {
948 case X86EMUL_MODE_REAL:
a0044755 949 case X86EMUL_MODE_VM86:
6aa8b732 950 case X86EMUL_MODE_PROT16:
f21b8bf4 951 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 952 break;
953 case X86EMUL_MODE_PROT32:
f21b8bf4 954 def_op_bytes = def_ad_bytes = 4;
6aa8b732 955 break;
05b3e0c2 956#ifdef CONFIG_X86_64
6aa8b732 957 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 958 def_op_bytes = 4;
959 def_ad_bytes = 8;
6aa8b732
AK		 960 break;
961#endif
962 default:
963 return -1;
964 }
965
f21b8bf4
AK		 966 c->op_bytes = def_op_bytes;
967 c->ad_bytes = def_ad_bytes;
968
6aa8b732 969 /* Legacy prefixes. */
b4c6abfe 970 for (;;) {
e4e03ded 971 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 972 case 0x66: /* operand-size override */
f21b8bf4
AK		 973 /* switch between 2/4 bytes */
974 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 975 break;
976 case 0x67: /* address-size override */
977 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 978 /* switch between 4/8 bytes */
f21b8bf4 979 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 980 else
e4e03ded 981 /* switch between 2/4 bytes */
f21b8bf4 982 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 983 break;
7a5b56df 984 case 0x26: /* ES override */
6aa8b732 985 case 0x2e: /* CS override */
7a5b56df 986 case 0x36: /* SS override */
6aa8b732 987 case 0x3e: /* DS override */
7a5b56df 988 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 989 break;
990 case 0x64: /* FS override */
6aa8b732 991 case 0x65: /* GS override */
7a5b56df 992 set_seg_override(c, c->b & 7);
6aa8b732 993 break;
b4c6abfe
LV		 994 case 0x40 ... 0x4f: /* REX */
995 if (mode != X86EMUL_MODE_PROT64)
996 goto done_prefixes;
33615aa9 997 c->rex_prefix = c->b;
b4c6abfe 998 continue;
6aa8b732 999 case 0xf0: /* LOCK */
e4e03ded 1000 c->lock_prefix = 1;
6aa8b732 1001 break;
ae6200ba 1002 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1003 c->rep_prefix = REPNE_PREFIX;
1004 break;
6aa8b732 1005 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1006 c->rep_prefix = REPE_PREFIX;
6aa8b732 1007 break;
6aa8b732
AK		 1008 default:
1009 goto done_prefixes;
1010 }
b4c6abfe
LV		 1011
1012 /* Any legacy prefix after a REX prefix nullifies its effect. */
1013
33615aa9 1014 c->rex_prefix = 0;
6aa8b732
AK		 1015 }
1016
1017done_prefixes:
1018
1019 /* REX prefix. */
1c73ef66 1020 if (c->rex_prefix)
33615aa9 1021 if (c->rex_prefix & 8)
e4e03ded 1022 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1023
1024 /* Opcode byte(s). */
e4e03ded
LV		 1025 c->d = opcode_table[c->b];
1026 if (c->d == 0) {
6aa8b732 1027 /* Two-byte opcode? */
e4e03ded
LV		 1028 if (c->b == 0x0f) {
1029 c->twobyte = 1;
1030 c->b = insn_fetch(u8, 1, c->eip);
1031 c->d = twobyte_table[c->b];
6aa8b732 1032 }
e09d082c 1033 }
6aa8b732 1034
e09d082c
AK		 1035 if (c->d & Group) {
1036 group = c->d & GroupMask;
1037 c->modrm = insn_fetch(u8, 1, c->eip);
1038 --c->eip;
1039
1040 group = (group << 3) + ((c->modrm >> 3) & 7);
1041 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1042 c->d = group2_table[group];
1043 else
1044 c->d = group_table[group];
1045 }
1046
1047 /* Unrecognised? */
1048 if (c->d == 0) {
1049 DPRINTF("Cannot emulate %02x\n", c->b);
1050 return -1;
6aa8b732
AK		 1051 }
1052
6e3d5dfb
AK		 1053 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1054 c->op_bytes = 8;
1055
6aa8b732 1056 /* ModRM and SIB bytes. */
1c73ef66
AK		 1057 if (c->d & ModRM)
1058 rc = decode_modrm(ctxt, ops);
1059 else if (c->d & MemAbs)
1060 rc = decode_abs(ctxt, ops);
3e2815e9 1061 if (rc != X86EMUL_CONTINUE)
1c73ef66 1062 goto done;
6aa8b732 1063
7a5b56df
AK		 1064 if (!c->has_seg_override)
1065 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1066
7a5b56df
AK		 1067 if (!(!c->twobyte && c->b == 0x8d))
1068 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1069
1070 if (c->ad_bytes != 8)
1071 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1072
1073 if (c->rip_relative)
1074 c->modrm_ea += c->eip;
1075
6aa8b732
AK		 1076 /*
1077 * Decode and fetch the source operand: register, memory
1078 * or immediate.
1079 */
e4e03ded 1080 switch (c->d & SrcMask) {
6aa8b732
AK		 1081 case SrcNone:
1082 break;
1083 case SrcReg:
9f1ef3f8 1084 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1085 break;
1086 case SrcMem16:
e4e03ded 1087 c->src.bytes = 2;
6aa8b732
AK		 1088 goto srcmem_common;
1089 case SrcMem32:
e4e03ded 1090 c->src.bytes = 4;
6aa8b732
AK		 1091 goto srcmem_common;
1092 case SrcMem:
e4e03ded
LV		 1093 c->src.bytes = (c->d & ByteOp) ? 1 :
1094 c->op_bytes;
b85b9ee9 1095 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1096 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1097 break;
d77c26fc 1098 srcmem_common:
4e62417b
AJ		 1099 /*
1100 * For instructions with a ModR/M byte, switch to register
1101 * access if Mod = 3.
1102 */
e4e03ded
LV		 1103 if ((c->d & ModRM) && c->modrm_mod == 3) {
1104 c->src.type = OP_REG;
66b85505 1105 c->src.val = c->modrm_val;
107d6d2e 1106 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1107 break;
1108 }
e4e03ded 1109 c->src.type = OP_MEM;
69f55cb1
GN		 1110 c->src.ptr = (unsigned long *)c->modrm_ea;
1111 c->src.val = 0;
6aa8b732
AK		 1112 break;
1113 case SrcImm:
c9eaf20f 1114 case SrcImmU:
e4e03ded
LV		 1115 c->src.type = OP_IMM;
1116 c->src.ptr = (unsigned long *)c->eip;
1117 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1118 if (c->src.bytes == 8)
1119 c->src.bytes = 4;
6aa8b732 1120 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1121 switch (c->src.bytes) {
6aa8b732 1122 case 1:
e4e03ded 1123 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1124 break;
1125 case 2:
e4e03ded 1126 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1127 break;
1128 case 4:
e4e03ded 1129 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1130 break;
1131 }
c9eaf20f
AK		 1132 if ((c->d & SrcMask) == SrcImmU) {
1133 switch (c->src.bytes) {
1134 case 1:
1135 c->src.val &= 0xff;
1136 break;
1137 case 2:
1138 c->src.val &= 0xffff;
1139 break;
1140 case 4:
1141 c->src.val &= 0xffffffff;
1142 break;
1143 }
1144 }
6aa8b732
AK		 1145 break;
1146 case SrcImmByte:
341de7e3 1147 case SrcImmUByte:
e4e03ded
LV		 1148 c->src.type = OP_IMM;
1149 c->src.ptr = (unsigned long *)c->eip;
1150 c->src.bytes = 1;
341de7e3
GN		 1151 if ((c->d & SrcMask) == SrcImmByte)
1152 c->src.val = insn_fetch(s8, 1, c->eip);
1153 else
1154 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1155 break;
bfcadf83
GT		 1156 case SrcOne:
1157 c->src.bytes = 1;
1158 c->src.val = 1;
1159 break;
a682e354
GN		 1160 case SrcSI:
1161 c->src.type = OP_MEM;
1162 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1163 c->src.ptr = (unsigned long *)
1164 register_address(c, seg_override_base(ctxt, c),
1165 c->regs[VCPU_REGS_RSI]);
1166 c->src.val = 0;
1167 break;
414e6277
GN		 1168 case SrcImmFAddr:
1169 c->src.type = OP_IMM;
1170 c->src.ptr = (unsigned long *)c->eip;
1171 c->src.bytes = c->op_bytes + 2;
1172 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1173 break;
1174 case SrcMemFAddr:
1175 c->src.type = OP_MEM;
1176 c->src.ptr = (unsigned long *)c->modrm_ea;
1177 c->src.bytes = c->op_bytes + 2;
1178 break;
6aa8b732
AK		 1179 }
1180
0dc8d10f
GT		 1181 /*
1182 * Decode and fetch the second source operand: register, memory
1183 * or immediate.
1184 */
1185 switch (c->d & Src2Mask) {
1186 case Src2None:
1187 break;
1188 case Src2CL:
1189 c->src2.bytes = 1;
1190 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1191 break;
1192 case Src2ImmByte:
1193 c->src2.type = OP_IMM;
1194 c->src2.ptr = (unsigned long *)c->eip;
1195 c->src2.bytes = 1;
1196 c->src2.val = insn_fetch(u8, 1, c->eip);
1197 break;
1198 case Src2One:
1199 c->src2.bytes = 1;
1200 c->src2.val = 1;
1201 break;
1202 }
1203
038e51de 1204 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1205 switch (c->d & DstMask) {
038e51de
AK		 1206 case ImplicitOps:
1207 /* Special instructions do their own operand decoding. */
8b4caf66 1208 return 0;
038e51de 1209 case DstReg:
9f1ef3f8 1210 decode_register_operand(&c->dst, c,
3c118e24 1211 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1212 break;
1213 case DstMem:
6550e1f1 1214 case DstMem64:
e4e03ded 1215 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1216 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1217 c->dst.type = OP_REG;
66b85505 1218 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1219 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1220 break;
1221 }
8b4caf66 1222 c->dst.type = OP_MEM;
69f55cb1 1223 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1224 if ((c->d & DstMask) == DstMem64)
1225 c->dst.bytes = 8;
1226 else
1227 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1228 c->dst.val = 0;
1229 if (c->d & BitOp) {
1230 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1231
1232 c->dst.ptr = (void *)c->dst.ptr +
1233 (c->src.val & mask) / 8;
1234 }
8b4caf66 1235 break;
9c9fddd0
GT		 1236 case DstAcc:
1237 c->dst.type = OP_REG;
d6d367d6 1238 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1239 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1240 switch (c->dst.bytes) {
9c9fddd0
GT		 1241 case 1:
1242 c->dst.val = *(u8 *)c->dst.ptr;
1243 break;
1244 case 2:
1245 c->dst.val = *(u16 *)c->dst.ptr;
1246 break;
1247 case 4:
1248 c->dst.val = *(u32 *)c->dst.ptr;
1249 break;
d6d367d6
GN		 1250 case 8:
1251 c->dst.val = *(u64 *)c->dst.ptr;
1252 break;
9c9fddd0
GT		 1253 }
1254 c->dst.orig_val = c->dst.val;
1255 break;
a682e354
GN		 1256 case DstDI:
1257 c->dst.type = OP_MEM;
1258 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1259 c->dst.ptr = (unsigned long *)
1260 register_address(c, es_base(ctxt),
1261 c->regs[VCPU_REGS_RDI]);
1262 c->dst.val = 0;
1263 break;
8b4caf66
LV		 1264 }
1265
1266done:
1267 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1268}
1269
9de41573
GN		 1270static int read_emulated(struct x86_emulate_ctxt *ctxt,
1271 struct x86_emulate_ops *ops,
1272 unsigned long addr, void *dest, unsigned size)
1273{
1274 int rc;
1275 struct read_cache *mc = &ctxt->decode.mem_read;
1276
1277 while (size) {
1278 int n = min(size, 8u);
1279 size -= n;
1280 if (mc->pos < mc->end)
1281 goto read_cached;
1282
1283 rc = ops->read_emulated(addr, mc->data + mc->end, n, ctxt->vcpu);
1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
1286 mc->end += n;
1287
1288 read_cached:
1289 memcpy(dest, mc->data + mc->pos, n);
1290 mc->pos += n;
1291 dest += n;
1292 addr += n;
1293 }
1294 return X86EMUL_CONTINUE;
1295}
1296
7b262e90
GN		 1297static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1298 struct x86_emulate_ops *ops,
1299 unsigned int size, unsigned short port,
1300 void *dest)
1301{
1302 struct read_cache *rc = &ctxt->decode.io_read;
1303
1304 if (rc->pos == rc->end) { /* refill pio read ahead */
1305 struct decode_cache *c = &ctxt->decode;
1306 unsigned int in_page, n;
1307 unsigned int count = c->rep_prefix ?
1308 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1309 in_page = (ctxt->eflags & EFLG_DF) ?
1310 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1311 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1312 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1313 count);
1314 if (n == 0)
1315 n = 1;
1316 rc->pos = rc->end = 0;
1317 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1318 return 0;
1319 rc->end = n * size;
1320 }
1321
1322 memcpy(dest, rc->data + rc->pos, size);
1323 rc->pos += size;
1324 return 1;
1325}
1326
38ba30ba
GN		 1327static u32 desc_limit_scaled(struct desc_struct *desc)
1328{
1329 u32 limit = get_desc_limit(desc);
1330
1331 return desc->g ? (limit << 12) | 0xfff : limit;
1332}
1333
1334static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops,
1336 u16 selector, struct desc_ptr *dt)
1337{
1338 if (selector & 1 << 2) {
1339 struct desc_struct desc;
1340 memset (dt, 0, sizeof *dt);
1341 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1342 return;
1343
1344 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1345 dt->address = get_desc_base(&desc);
1346 } else
1347 ops->get_gdt(dt, ctxt->vcpu);
1348}
1349
1350/* allowed just for 8 bytes segments */
1351static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1352 struct x86_emulate_ops *ops,
1353 u16 selector, struct desc_struct *desc)
1354{
1355 struct desc_ptr dt;
1356 u16 index = selector >> 3;
1357 int ret;
1358 u32 err;
1359 ulong addr;
1360
1361 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1362
1363 if (dt.size < index * 8 + 7) {
1364 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1365 return X86EMUL_PROPAGATE_FAULT;
1366 }
1367 addr = dt.address + index * 8;
1368 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1369 if (ret == X86EMUL_PROPAGATE_FAULT)
1370 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1371
1372 return ret;
1373}
1374
1375/* allowed just for 8 bytes segments */
1376static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1377 struct x86_emulate_ops *ops,
1378 u16 selector, struct desc_struct *desc)
1379{
1380 struct desc_ptr dt;
1381 u16 index = selector >> 3;
1382 u32 err;
1383 ulong addr;
1384 int ret;
1385
1386 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1387
1388 if (dt.size < index * 8 + 7) {
1389 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1390 return X86EMUL_PROPAGATE_FAULT;
1391 }
1392
1393 addr = dt.address + index * 8;
1394 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1395 if (ret == X86EMUL_PROPAGATE_FAULT)
1396 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1397
1398 return ret;
1399}
1400
1401static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1402 struct x86_emulate_ops *ops,
1403 u16 selector, int seg)
1404{
1405 struct desc_struct seg_desc;
1406 u8 dpl, rpl, cpl;
1407 unsigned err_vec = GP_VECTOR;
1408 u32 err_code = 0;
1409 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1410 int ret;
1411
1412 memset(&seg_desc, 0, sizeof seg_desc);
1413
1414 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1415 || ctxt->mode == X86EMUL_MODE_REAL) {
1416 /* set real mode segment descriptor */
1417 set_desc_base(&seg_desc, selector << 4);
1418 set_desc_limit(&seg_desc, 0xffff);
1419 seg_desc.type = 3;
1420 seg_desc.p = 1;
1421 seg_desc.s = 1;
1422 goto load;
1423 }
1424
1425 /* NULL selector is not valid for TR, CS and SS */
1426 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1427 && null_selector)
1428 goto exception;
1429
1430 /* TR should be in GDT only */
1431 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1432 goto exception;
1433
1434 if (null_selector) /* for NULL selector skip all following checks */
1435 goto load;
1436
1437 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1438 if (ret != X86EMUL_CONTINUE)
1439 return ret;
1440
1441 err_code = selector & 0xfffc;
1442 err_vec = GP_VECTOR;
1443
1444 /* can't load system descriptor into segment selecor */
1445 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1446 goto exception;
1447
1448 if (!seg_desc.p) {
1449 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1450 goto exception;
1451 }
1452
1453 rpl = selector & 3;
1454 dpl = seg_desc.dpl;
1455 cpl = ops->cpl(ctxt->vcpu);
1456
1457 switch (seg) {
1458 case VCPU_SREG_SS:
1459 /*
1460 * segment is not a writable data segment or segment
1461 * selector's RPL != CPL or segment selector's RPL != CPL
1462 */
1463 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1464 goto exception;
1465 break;
1466 case VCPU_SREG_CS:
1467 if (!(seg_desc.type & 8))
1468 goto exception;
1469
1470 if (seg_desc.type & 4) {
1471 /* conforming */
1472 if (dpl > cpl)
1473 goto exception;
1474 } else {
1475 /* nonconforming */
1476 if (rpl > cpl || dpl != cpl)
1477 goto exception;
1478 }
1479 /* CS(RPL) <- CPL */
1480 selector = (selector & 0xfffc) | cpl;
1481 break;
1482 case VCPU_SREG_TR:
1483 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1484 goto exception;
1485 break;
1486 case VCPU_SREG_LDTR:
1487 if (seg_desc.s || seg_desc.type != 2)
1488 goto exception;
1489 break;
1490 default: /* DS, ES, FS, or GS */
1491 /*
1492 * segment is not a data or readable code segment or
1493 * ((segment is a data or nonconforming code segment)
1494 * and (both RPL and CPL > DPL))
1495 */
1496 if ((seg_desc.type & 0xa) == 0x8 ||
1497 (((seg_desc.type & 0xc) != 0xc) &&
1498 (rpl > dpl && cpl > dpl)))
1499 goto exception;
1500 break;
1501 }
1502
1503 if (seg_desc.s) {
1504 /* mark segment as accessed */
1505 seg_desc.type |= 1;
1506 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1507 if (ret != X86EMUL_CONTINUE)
1508 return ret;
1509 }
1510load:
1511 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1512 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1513 return X86EMUL_CONTINUE;
1514exception:
1515 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1516 return X86EMUL_PROPAGATE_FAULT;
1517}
1518
8cdbd2c9
LV		 1519static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1520{
1521 struct decode_cache *c = &ctxt->decode;
1522
1523 c->dst.type = OP_MEM;
1524 c->dst.bytes = c->op_bytes;
1525 c->dst.val = c->src.val;
7a957275 1526 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1527 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1528 c->regs[VCPU_REGS_RSP]);
1529}
1530
faa5a3ae 1531static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1532 struct x86_emulate_ops *ops,
1533 void *dest, int len)
8cdbd2c9
LV		 1534{
1535 struct decode_cache *c = &ctxt->decode;
1536 int rc;
1537
9de41573
GN		 1538 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt),
1539 c->regs[VCPU_REGS_RSP]),
1540 dest, len);
b60d513c 1541 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1542 return rc;
1543
350f69dc 1544 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1545 return rc;
1546}
8cdbd2c9 1547
d4c6a154
GN		 1548static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1549 struct x86_emulate_ops *ops,
1550 void *dest, int len)
1551{
1552 int rc;
1553 unsigned long val, change_mask;
1554 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1555 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1556
1557 rc = emulate_pop(ctxt, ops, &val, len);
1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560
1561 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1562 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1563
1564 switch(ctxt->mode) {
1565 case X86EMUL_MODE_PROT64:
1566 case X86EMUL_MODE_PROT32:
1567 case X86EMUL_MODE_PROT16:
1568 if (cpl == 0)
1569 change_mask |= EFLG_IOPL;
1570 if (cpl <= iopl)
1571 change_mask |= EFLG_IF;
1572 break;
1573 case X86EMUL_MODE_VM86:
1574 if (iopl < 3) {
1575 kvm_inject_gp(ctxt->vcpu, 0);
1576 return X86EMUL_PROPAGATE_FAULT;
1577 }
1578 change_mask |= EFLG_IF;
1579 break;
1580 default: /* real mode */
1581 change_mask |= (EFLG_IOPL | EFLG_IF);
1582 break;
1583 }
1584
1585 *(unsigned long *)dest =
1586 (ctxt->eflags & ~change_mask) | (val & change_mask);
1587
1588 return rc;
1589}
1590
0934ac9d
MG		 1591static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1592{
1593 struct decode_cache *c = &ctxt->decode;
1594 struct kvm_segment segment;
1595
1596 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1597
1598 c->src.val = segment.selector;
1599 emulate_push(ctxt);
1600}
1601
1602static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1603 struct x86_emulate_ops *ops, int seg)
1604{
1605 struct decode_cache *c = &ctxt->decode;
1606 unsigned long selector;
1607 int rc;
1608
1609 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1610 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1611 return rc;
1612
2e873022 1613 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1614 return rc;
1615}
1616
abcf14b5
MG		 1617static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1618{
1619 struct decode_cache *c = &ctxt->decode;
1620 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1621 int reg = VCPU_REGS_RAX;
1622
1623 while (reg <= VCPU_REGS_RDI) {
1624 (reg == VCPU_REGS_RSP) ?
1625 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1626
1627 emulate_push(ctxt);
1628 ++reg;
1629 }
1630}
1631
1632static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1633 struct x86_emulate_ops *ops)
1634{
1635 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1636 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1637 int reg = VCPU_REGS_RDI;
1638
1639 while (reg >= VCPU_REGS_RAX) {
1640 if (reg == VCPU_REGS_RSP) {
1641 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1642 c->op_bytes);
1643 --reg;
1644 }
1645
1646 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1647 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1648 break;
1649 --reg;
1650 }
1651 return rc;
1652}
1653
faa5a3ae
AK		 1654static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1655 struct x86_emulate_ops *ops)
1656{
1657 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1658
1b30eaa8 1659 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1660}
1661
05f086f8 1662static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1663{
05f086f8 1664 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1665 switch (c->modrm_reg) {
1666 case 0: /* rol */
05f086f8 1667 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1668 break;
1669 case 1: /* ror */
05f086f8 1670 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1671 break;
1672 case 2: /* rcl */
05f086f8 1673 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1674 break;
1675 case 3: /* rcr */
05f086f8 1676 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1677 break;
1678 case 4: /* sal/shl */
1679 case 6: /* sal/shl */
05f086f8 1680 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1681 break;
1682 case 5: /* shr */
05f086f8 1683 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1684 break;
1685 case 7: /* sar */
05f086f8 1686 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1687 break;
1688 }
1689}
1690
1691static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1692 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1693{
1694 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1695
1696 switch (c->modrm_reg) {
1697 case 0 ... 1: /* test */
05f086f8 1698 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1699 break;
1700 case 2: /* not */
1701 c->dst.val = ~c->dst.val;
1702 break;
1703 case 3: /* neg */
05f086f8 1704 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1705 break;
1706 default:
aca06a83 1707 return 0;
8cdbd2c9 1708 }
aca06a83 1709 return 1;
8cdbd2c9
LV		 1710}
1711
1712static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1713 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1714{
1715 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1716
1717 switch (c->modrm_reg) {
1718 case 0: /* inc */
05f086f8 1719 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1720 break;
1721 case 1: /* dec */
05f086f8 1722 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1723 break;
d19292e4
MG		 1724 case 2: /* call near abs */ {
1725 long int old_eip;
1726 old_eip = c->eip;
1727 c->eip = c->src.val;
1728 c->src.val = old_eip;
1729 emulate_push(ctxt);
1730 break;
1731 }
8cdbd2c9 1732 case 4: /* jmp abs */
fd60754e 1733 c->eip = c->src.val;
8cdbd2c9
LV		 1734 break;
1735 case 6: /* push */
fd60754e 1736 emulate_push(ctxt);
8cdbd2c9 1737 break;
8cdbd2c9 1738 }
1b30eaa8 1739 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1740}
1741
1742static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1743 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1744{
1745 struct decode_cache *c = &ctxt->decode;
6550e1f1 1746 u64 old = c->dst.orig_val;
8cdbd2c9
LV		 1747
1748 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1749 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1750
1751 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1752 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1753 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1754 } else {
6550e1f1 1755 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
8cdbd2c9
LV		 1756 (u32) c->regs[VCPU_REGS_RBX];
1757
05f086f8 1758 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1759 }
1b30eaa8 1760 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1761}
1762
a77ab5ea
AK		 1763static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1764 struct x86_emulate_ops *ops)
1765{
1766 struct decode_cache *c = &ctxt->decode;
1767 int rc;
1768 unsigned long cs;
1769
1770 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1771 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1772 return rc;
1773 if (c->op_bytes == 4)
1774 c->eip = (u32)c->eip;
1775 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1776 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1777 return rc;
2e873022 1778 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1779 return rc;
1780}
1781
8cdbd2c9
LV		 1782static inline int writeback(struct x86_emulate_ctxt *ctxt,
1783 struct x86_emulate_ops *ops)
1784{
1785 int rc;
1786 struct decode_cache *c = &ctxt->decode;
1787
1788 switch (c->dst.type) {
1789 case OP_REG:
1790 /* The 4-byte case *is* correct:
1791 * in 64-bit mode we zero-extend.
1792 */
1793 switch (c->dst.bytes) {
1794 case 1:
1795 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1796 break;
1797 case 2:
1798 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1799 break;
1800 case 4:
1801 *c->dst.ptr = (u32)c->dst.val;
1802 break; /* 64b: zero-ext */
1803 case 8:
1804 *c->dst.ptr = c->dst.val;
1805 break;
1806 }
1807 break;
1808 case OP_MEM:
1809 if (c->lock_prefix)
1810 rc = ops->cmpxchg_emulated(
1811 (unsigned long)c->dst.ptr,
1812 &c->dst.orig_val,
1813 &c->dst.val,
1814 c->dst.bytes,
1815 ctxt->vcpu);
1816 else
1817 rc = ops->write_emulated(
1818 (unsigned long)c->dst.ptr,
1819 &c->dst.val,
1820 c->dst.bytes,
1821 ctxt->vcpu);
b60d513c 1822 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1823 return rc;
a01af5ec
LV		 1824 break;
1825 case OP_NONE:
1826 /* no writeback */
1827 break;
8cdbd2c9
LV		 1828 default:
1829 break;
1830 }
1b30eaa8 1831 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1832}
1833
a3f9d398 1834static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1835{
1836 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1837 /*
1838 * an sti; sti; sequence only disable interrupts for the first
1839 * instruction. So, if the last instruction, be it emulated or
1840 * not, left the system with the INT_STI flag enabled, it
1841 * means that the last instruction is an sti. We should not
1842 * leave the flag on in this case. The same goes for mov ss
1843 */
1844 if (!(int_shadow & mask))
1845 ctxt->interruptibility = mask;
1846}
1847
e66bb2cc
AP		 1848static inline void
1849setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1850 struct kvm_segment *cs, struct kvm_segment *ss)
1851{
1852 memset(cs, 0, sizeof(struct kvm_segment));
1853 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1854 memset(ss, 0, sizeof(struct kvm_segment));
1855
1856 cs->l = 0; /* will be adjusted later */
1857 cs->base = 0; /* flat segment */
1858 cs->g = 1; /* 4kb granularity */
1859 cs->limit = 0xffffffff; /* 4GB limit */
1860 cs->type = 0x0b; /* Read, Execute, Accessed */
1861 cs->s = 1;
1862 cs->dpl = 0; /* will be adjusted later */
1863 cs->present = 1;
1864 cs->db = 1;
1865
1866 ss->unusable = 0;
1867 ss->base = 0; /* flat segment */
1868 ss->limit = 0xffffffff; /* 4GB limit */
1869 ss->g = 1; /* 4kb granularity */
1870 ss->s = 1;
1871 ss->type = 0x03; /* Read/Write, Accessed */
1872 ss->db = 1; /* 32bit stack segment */
1873 ss->dpl = 0;
1874 ss->present = 1;
1875}
1876
1877static int
3fb1b5db 1878emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1879{
1880 struct decode_cache *c = &ctxt->decode;
1881 struct kvm_segment cs, ss;
1882 u64 msr_data;
1883
1884 /* syscall is not available in real mode */
2e901c4c
GN		 1885 if (ctxt->mode == X86EMUL_MODE_REAL ||
1886 ctxt->mode == X86EMUL_MODE_VM86) {
1887 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1888 return X86EMUL_PROPAGATE_FAULT;
1889 }
e66bb2cc
AP		 1890
1891 setup_syscalls_segments(ctxt, &cs, &ss);
1892
3fb1b5db 1893 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1894 msr_data >>= 32;
1895 cs.selector = (u16)(msr_data & 0xfffc);
1896 ss.selector = (u16)(msr_data + 8);
1897
1898 if (is_long_mode(ctxt->vcpu)) {
1899 cs.db = 0;
1900 cs.l = 1;
1901 }
1902 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1903 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1904
1905 c->regs[VCPU_REGS_RCX] = c->eip;
1906 if (is_long_mode(ctxt->vcpu)) {
1907#ifdef CONFIG_X86_64
1908 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1909
3fb1b5db
GN		 1910 ops->get_msr(ctxt->vcpu,
1911 ctxt->mode == X86EMUL_MODE_PROT64 ?
1912 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1913 c->eip = msr_data;
1914
3fb1b5db 1915 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1916 ctxt->eflags &= ~(msr_data | EFLG_RF);
1917#endif
1918 } else {
1919 /* legacy mode */
3fb1b5db 1920 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1921 c->eip = (u32)msr_data;
1922
1923 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1924 }
1925
e54cfa97 1926 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1927}
1928
8c604352 1929static int
3fb1b5db 1930emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1931{
1932 struct decode_cache *c = &ctxt->decode;
1933 struct kvm_segment cs, ss;
1934 u64 msr_data;
1935
a0044755
GN		 1936 /* inject #GP if in real mode */
1937 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352 1938 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1939 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1940 }
1941
1942 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1943 * Therefore, we inject an #UD.
1944 */
2e901c4c
GN		 1945 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1946 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1947 return X86EMUL_PROPAGATE_FAULT;
1948 }
8c604352
AP		 1949
1950 setup_syscalls_segments(ctxt, &cs, &ss);
1951
3fb1b5db 1952 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1953 switch (ctxt->mode) {
1954 case X86EMUL_MODE_PROT32:
1955 if ((msr_data & 0xfffc) == 0x0) {
1956 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1957 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1958 }
1959 break;
1960 case X86EMUL_MODE_PROT64:
1961 if (msr_data == 0x0) {
1962 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1963 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1964 }
1965 break;
1966 }
1967
1968 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1969 cs.selector = (u16)msr_data;
1970 cs.selector &= ~SELECTOR_RPL_MASK;
1971 ss.selector = cs.selector + 8;
1972 ss.selector &= ~SELECTOR_RPL_MASK;
1973 if (ctxt->mode == X86EMUL_MODE_PROT64
1974 || is_long_mode(ctxt->vcpu)) {
1975 cs.db = 0;
1976 cs.l = 1;
1977 }
1978
1979 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1980 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1981
3fb1b5db 1982 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1983 c->eip = msr_data;
1984
3fb1b5db 1985 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1986 c->regs[VCPU_REGS_RSP] = msr_data;
1987
e54cfa97 1988 return X86EMUL_CONTINUE;
8c604352
AP		 1989}
1990
4668f050 1991static int
3fb1b5db 1992emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1993{
1994 struct decode_cache *c = &ctxt->decode;
1995 struct kvm_segment cs, ss;
1996 u64 msr_data;
1997 int usermode;
1998
a0044755
GN		 1999 /* inject #GP if in real mode or Virtual 8086 mode */
2000 if (ctxt->mode == X86EMUL_MODE_REAL ||
2001 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050 2002 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 2003 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2004 }
2005
4668f050
AP		 2006 setup_syscalls_segments(ctxt, &cs, &ss);
2007
2008 if ((c->rex_prefix & 0x8) != 0x0)
2009 usermode = X86EMUL_MODE_PROT64;
2010 else
2011 usermode = X86EMUL_MODE_PROT32;
2012
2013 cs.dpl = 3;
2014 ss.dpl = 3;
3fb1b5db 2015 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2016 switch (usermode) {
2017 case X86EMUL_MODE_PROT32:
2018 cs.selector = (u16)(msr_data + 16);
2019 if ((msr_data & 0xfffc) == 0x0) {
2020 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 2021 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2022 }
2023 ss.selector = (u16)(msr_data + 24);
2024 break;
2025 case X86EMUL_MODE_PROT64:
2026 cs.selector = (u16)(msr_data + 32);
2027 if (msr_data == 0x0) {
2028 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 2029 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2030 }
2031 ss.selector = cs.selector + 8;
2032 cs.db = 0;
2033 cs.l = 1;
2034 break;
2035 }
2036 cs.selector |= SELECTOR_RPL_MASK;
2037 ss.selector |= SELECTOR_RPL_MASK;
2038
2039 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
2040 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
2041
2042 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
2043 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
2044
e54cfa97 2045 return X86EMUL_CONTINUE;
4668f050
AP		 2046}
2047
9c537244
GN		 2048static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2049 struct x86_emulate_ops *ops)
f850e2e6
GN		 2050{
2051 int iopl;
2052 if (ctxt->mode == X86EMUL_MODE_REAL)
2053 return false;
2054 if (ctxt->mode == X86EMUL_MODE_VM86)
2055 return true;
2056 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2057 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2058}
2059
2060static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2061 struct x86_emulate_ops *ops,
2062 u16 port, u16 len)
2063{
2064 struct kvm_segment tr_seg;
2065 int r;
2066 u16 io_bitmap_ptr;
2067 u8 perm, bit_idx = port & 0x7;
2068 unsigned mask = (1 << len) - 1;
2069
2070 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
2071 if (tr_seg.unusable)
2072 return false;
2073 if (tr_seg.limit < 103)
2074 return false;
2075 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
2076 NULL);
2077 if (r != X86EMUL_CONTINUE)
2078 return false;
2079 if (io_bitmap_ptr + port/8 > tr_seg.limit)
2080 return false;
2081 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
2082 ctxt->vcpu, NULL);
2083 if (r != X86EMUL_CONTINUE)
2084 return false;
2085 if ((perm >> bit_idx) & mask)
2086 return false;
2087 return true;
2088}
2089
2090static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2091 struct x86_emulate_ops *ops,
2092 u16 port, u16 len)
2093{
9c537244 2094 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2095 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2096 return false;
2097 return true;
2098}
2099
38ba30ba
GN		 2100static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2101 struct x86_emulate_ops *ops,
2102 struct tss_segment_16 *tss)
2103{
2104 struct decode_cache *c = &ctxt->decode;
2105
2106 tss->ip = c->eip;
2107 tss->flag = ctxt->eflags;
2108 tss->ax = c->regs[VCPU_REGS_RAX];
2109 tss->cx = c->regs[VCPU_REGS_RCX];
2110 tss->dx = c->regs[VCPU_REGS_RDX];
2111 tss->bx = c->regs[VCPU_REGS_RBX];
2112 tss->sp = c->regs[VCPU_REGS_RSP];
2113 tss->bp = c->regs[VCPU_REGS_RBP];
2114 tss->si = c->regs[VCPU_REGS_RSI];
2115 tss->di = c->regs[VCPU_REGS_RDI];
2116
2117 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2118 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2119 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2120 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2121 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2122}
2123
2124static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2125 struct x86_emulate_ops *ops,
2126 struct tss_segment_16 *tss)
2127{
2128 struct decode_cache *c = &ctxt->decode;
2129 int ret;
2130
2131 c->eip = tss->ip;
2132 ctxt->eflags = tss->flag | 2;
2133 c->regs[VCPU_REGS_RAX] = tss->ax;
2134 c->regs[VCPU_REGS_RCX] = tss->cx;
2135 c->regs[VCPU_REGS_RDX] = tss->dx;
2136 c->regs[VCPU_REGS_RBX] = tss->bx;
2137 c->regs[VCPU_REGS_RSP] = tss->sp;
2138 c->regs[VCPU_REGS_RBP] = tss->bp;
2139 c->regs[VCPU_REGS_RSI] = tss->si;
2140 c->regs[VCPU_REGS_RDI] = tss->di;
2141
2142 /*
2143 * SDM says that segment selectors are loaded before segment
2144 * descriptors
2145 */
2146 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2147 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2148 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2149 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2150 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2151
2152 /*
2153 * Now load segment descriptors. If fault happenes at this stage
2154 * it is handled in a context of new task
2155 */
2156 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2157 if (ret != X86EMUL_CONTINUE)
2158 return ret;
2159 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2160 if (ret != X86EMUL_CONTINUE)
2161 return ret;
2162 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2163 if (ret != X86EMUL_CONTINUE)
2164 return ret;
2165 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2166 if (ret != X86EMUL_CONTINUE)
2167 return ret;
2168 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2169 if (ret != X86EMUL_CONTINUE)
2170 return ret;
2171
2172 return X86EMUL_CONTINUE;
2173}
2174
2175static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2176 struct x86_emulate_ops *ops,
2177 u16 tss_selector, u16 old_tss_sel,
2178 ulong old_tss_base, struct desc_struct *new_desc)
2179{
2180 struct tss_segment_16 tss_seg;
2181 int ret;
2182 u32 err, new_tss_base = get_desc_base(new_desc);
2183
2184 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2185 &err);
2186 if (ret == X86EMUL_PROPAGATE_FAULT) {
2187 /* FIXME: need to provide precise fault address */
2188 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2189 return ret;
2190 }
2191
2192 save_state_to_tss16(ctxt, ops, &tss_seg);
2193
2194 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2195 &err);
2196 if (ret == X86EMUL_PROPAGATE_FAULT) {
2197 /* FIXME: need to provide precise fault address */
2198 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2199 return ret;
2200 }
2201
2202 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2203 &err);
2204 if (ret == X86EMUL_PROPAGATE_FAULT) {
2205 /* FIXME: need to provide precise fault address */
2206 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2207 return ret;
2208 }
2209
2210 if (old_tss_sel != 0xffff) {
2211 tss_seg.prev_task_link = old_tss_sel;
2212
2213 ret = ops->write_std(new_tss_base,
2214 &tss_seg.prev_task_link,
2215 sizeof tss_seg.prev_task_link,
2216 ctxt->vcpu, &err);
2217 if (ret == X86EMUL_PROPAGATE_FAULT) {
2218 /* FIXME: need to provide precise fault address */
2219 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2220 return ret;
2221 }
2222 }
2223
2224 return load_state_from_tss16(ctxt, ops, &tss_seg);
2225}
2226
2227static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2228 struct x86_emulate_ops *ops,
2229 struct tss_segment_32 *tss)
2230{
2231 struct decode_cache *c = &ctxt->decode;
2232
2233 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2234 tss->eip = c->eip;
2235 tss->eflags = ctxt->eflags;
2236 tss->eax = c->regs[VCPU_REGS_RAX];
2237 tss->ecx = c->regs[VCPU_REGS_RCX];
2238 tss->edx = c->regs[VCPU_REGS_RDX];
2239 tss->ebx = c->regs[VCPU_REGS_RBX];
2240 tss->esp = c->regs[VCPU_REGS_RSP];
2241 tss->ebp = c->regs[VCPU_REGS_RBP];
2242 tss->esi = c->regs[VCPU_REGS_RSI];
2243 tss->edi = c->regs[VCPU_REGS_RDI];
2244
2245 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2246 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2247 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2248 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2249 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2250 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2251 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2252}
2253
2254static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2255 struct x86_emulate_ops *ops,
2256 struct tss_segment_32 *tss)
2257{
2258 struct decode_cache *c = &ctxt->decode;
2259 int ret;
2260
2261 ops->set_cr(3, tss->cr3, ctxt->vcpu);
2262 c->eip = tss->eip;
2263 ctxt->eflags = tss->eflags | 2;
2264 c->regs[VCPU_REGS_RAX] = tss->eax;
2265 c->regs[VCPU_REGS_RCX] = tss->ecx;
2266 c->regs[VCPU_REGS_RDX] = tss->edx;
2267 c->regs[VCPU_REGS_RBX] = tss->ebx;
2268 c->regs[VCPU_REGS_RSP] = tss->esp;
2269 c->regs[VCPU_REGS_RBP] = tss->ebp;
2270 c->regs[VCPU_REGS_RSI] = tss->esi;
2271 c->regs[VCPU_REGS_RDI] = tss->edi;
2272
2273 /*
2274 * SDM says that segment selectors are loaded before segment
2275 * descriptors
2276 */
2277 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2278 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2279 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2280 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2281 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2282 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2283 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2284
2285 /*
2286 * Now load segment descriptors. If fault happenes at this stage
2287 * it is handled in a context of new task
2288 */
2289 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2290 if (ret != X86EMUL_CONTINUE)
2291 return ret;
2292 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2293 if (ret != X86EMUL_CONTINUE)
2294 return ret;
2295 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2296 if (ret != X86EMUL_CONTINUE)
2297 return ret;
2298 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2299 if (ret != X86EMUL_CONTINUE)
2300 return ret;
2301 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2302 if (ret != X86EMUL_CONTINUE)
2303 return ret;
2304 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2305 if (ret != X86EMUL_CONTINUE)
2306 return ret;
2307 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2308 if (ret != X86EMUL_CONTINUE)
2309 return ret;
2310
2311 return X86EMUL_CONTINUE;
2312}
2313
2314static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2315 struct x86_emulate_ops *ops,
2316 u16 tss_selector, u16 old_tss_sel,
2317 ulong old_tss_base, struct desc_struct *new_desc)
2318{
2319 struct tss_segment_32 tss_seg;
2320 int ret;
2321 u32 err, new_tss_base = get_desc_base(new_desc);
2322
2323 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2324 &err);
2325 if (ret == X86EMUL_PROPAGATE_FAULT) {
2326 /* FIXME: need to provide precise fault address */
2327 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2328 return ret;
2329 }
2330
2331 save_state_to_tss32(ctxt, ops, &tss_seg);
2332
2333 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2334 &err);
2335 if (ret == X86EMUL_PROPAGATE_FAULT) {
2336 /* FIXME: need to provide precise fault address */
2337 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2338 return ret;
2339 }
2340
2341 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2342 &err);
2343 if (ret == X86EMUL_PROPAGATE_FAULT) {
2344 /* FIXME: need to provide precise fault address */
2345 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2346 return ret;
2347 }
2348
2349 if (old_tss_sel != 0xffff) {
2350 tss_seg.prev_task_link = old_tss_sel;
2351
2352 ret = ops->write_std(new_tss_base,
2353 &tss_seg.prev_task_link,
2354 sizeof tss_seg.prev_task_link,
2355 ctxt->vcpu, &err);
2356 if (ret == X86EMUL_PROPAGATE_FAULT) {
2357 /* FIXME: need to provide precise fault address */
2358 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2359 return ret;
2360 }
2361 }
2362
2363 return load_state_from_tss32(ctxt, ops, &tss_seg);
2364}
2365
2366static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2367 struct x86_emulate_ops *ops,
2368 u16 tss_selector, int reason,
2369 bool has_error_code, u32 error_code)
38ba30ba
GN		 2370{
2371 struct desc_struct curr_tss_desc, next_tss_desc;
2372 int ret;
2373 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2374 ulong old_tss_base =
5951c442 2375 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2376 u32 desc_limit;
38ba30ba
GN		 2377
2378 /* FIXME: old_tss_base == ~0 ? */
2379
2380 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2381 if (ret != X86EMUL_CONTINUE)
2382 return ret;
2383 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2384 if (ret != X86EMUL_CONTINUE)
2385 return ret;
2386
2387 /* FIXME: check that next_tss_desc is tss */
2388
2389 if (reason != TASK_SWITCH_IRET) {
2390 if ((tss_selector & 3) > next_tss_desc.dpl ||
2391 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2392 kvm_inject_gp(ctxt->vcpu, 0);
2393 return X86EMUL_PROPAGATE_FAULT;
2394 }
2395 }
2396
ceffb459
GN		 2397 desc_limit = desc_limit_scaled(&next_tss_desc);
2398 if (!next_tss_desc.p ||
2399 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2400 desc_limit < 0x2b)) {
38ba30ba
GN		 2401 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2402 tss_selector & 0xfffc);
2403 return X86EMUL_PROPAGATE_FAULT;
2404 }
2405
2406 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2407 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2408 write_segment_descriptor(ctxt, ops, old_tss_sel,
2409 &curr_tss_desc);
2410 }
2411
2412 if (reason == TASK_SWITCH_IRET)
2413 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2414
2415 /* set back link to prev task only if NT bit is set in eflags
2416 note that old_tss_sel is not used afetr this point */
2417 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2418 old_tss_sel = 0xffff;
2419
2420 if (next_tss_desc.type & 8)
2421 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2422 old_tss_base, &next_tss_desc);
2423 else
2424 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2425 old_tss_base, &next_tss_desc);
0760d448
JK		 2426 if (ret != X86EMUL_CONTINUE)
2427 return ret;
38ba30ba
GN		 2428
2429 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2430 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2431
2432 if (reason != TASK_SWITCH_IRET) {
2433 next_tss_desc.type |= (1 << 1); /* set busy flag */
2434 write_segment_descriptor(ctxt, ops, tss_selector,
2435 &next_tss_desc);
2436 }
2437
2438 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2439 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2440 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2441
e269fb21
JK		 2442 if (has_error_code) {
2443 struct decode_cache *c = &ctxt->decode;
2444
2445 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2446 c->lock_prefix = 0;
2447 c->src.val = (unsigned long) error_code;
2448 emulate_push(ctxt);
2449 }
2450
38ba30ba
GN		 2451 return ret;
2452}
2453
2454int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2455 struct x86_emulate_ops *ops,
e269fb21
JK		 2456 u16 tss_selector, int reason,
2457 bool has_error_code, u32 error_code)
38ba30ba
GN		 2458{
2459 struct decode_cache *c = &ctxt->decode;
2460 int rc;
2461
2462 memset(c, 0, sizeof(struct decode_cache));
2463 c->eip = ctxt->eip;
2464 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
e269fb21 2465 c->dst.type = OP_NONE;
38ba30ba 2466
e269fb21
JK		 2467 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2468 has_error_code, error_code);
38ba30ba
GN		 2469
2470 if (rc == X86EMUL_CONTINUE) {
2471 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
2472 kvm_rip_write(ctxt->vcpu, c->eip);
e269fb21 2473 rc = writeback(ctxt, ops);
38ba30ba
GN		 2474 }
2475
19d04437 2476 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2477}
2478
a682e354 2479static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2480 int reg, struct operand *op)
a682e354
GN		 2481{
2482 struct decode_cache *c = &ctxt->decode;
2483 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2484
d9271123
GN		 2485 register_address_increment(c, &c->regs[reg], df * op->bytes);
2486 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2487}
2488
8b4caf66 2489int
1be3aa47 2490x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2491{
8b4caf66 2492 u64 msr_data;
8b4caf66 2493 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2494 int rc = X86EMUL_CONTINUE;
5cd21917 2495 int saved_dst_type = c->dst.type;
8b4caf66 2496
310b5d30 2497 ctxt->interruptibility = 0;
9de41573 2498 ctxt->decode.mem_read.pos = 0;
310b5d30 2499
3427318f
LV		 2500 /* Shadow copy of register state. Committed on successful emulation.
2501 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
2502 * modify them.
2503 */
2504
ad312c7c 2505 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f 2506
1161624f
GN		 2507 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2508 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2509 goto done;
2510 }
2511
d380a5e4 2512 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2513 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
d380a5e4
GN		 2514 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2515 goto done;
2516 }
2517
e92805ac 2518 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2519 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
e92805ac
GN		 2520 kvm_inject_gp(ctxt->vcpu, 0);
2521 goto done;
2522 }
2523
b9fa9d6b 2524 if (c->rep_prefix && (c->d & String)) {
5cd21917 2525 ctxt->restart = true;
b9fa9d6b 2526 /* All REP prefixes have the same first termination condition */
c73e197b 2527 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2528 string_done:
2529 ctxt->restart = false;
5fdbf976 2530 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 2531 goto done;
2532 }
2533 /* The second termination condition only applies for REPE
2534 * and REPNE. Test if the repeat string operation prefix is
2535 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2536 * corresponding termination condition according to:
2537 * - if REPE/REPZ and ZF = 0 then done
2538 * - if REPNE/REPNZ and ZF = 1 then done
2539 */
2540 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2541 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2542 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2543 ((ctxt->eflags & EFLG_ZF) == 0))
2544 goto string_done;
b9fa9d6b 2545 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2546 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2547 goto string_done;
b9fa9d6b 2548 }
063db061 2549 c->eip = ctxt->eip;
b9fa9d6b
AK		 2550 }
2551
8b4caf66 2552 if (c->src.type == OP_MEM) {
9de41573 2553 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2554 c->src.valptr, c->src.bytes);
b60d513c 2555 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 2556 goto done;
2557 c->src.orig_val = c->src.val;
2558 }
2559
e35b7b9c 2560 if (c->src2.type == OP_MEM) {
9de41573
GN		 2561 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2562 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2563 if (rc != X86EMUL_CONTINUE)
2564 goto done;
2565 }
2566
8b4caf66
LV		 2567 if ((c->d & DstMask) == ImplicitOps)
2568 goto special_insn;
2569
2570
69f55cb1
GN		 2571 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2572 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2573 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2574 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2575 if (rc != X86EMUL_CONTINUE)
2576 goto done;
038e51de 2577 }
e4e03ded 2578 c->dst.orig_val = c->dst.val;
038e51de 2579
018a98db
AK		 2580special_insn:
2581
e4e03ded 2582 if (c->twobyte)
6aa8b732
AK		 2583 goto twobyte_insn;
2584
e4e03ded 2585 switch (c->b) {
6aa8b732
AK		 2586 case 0x00 ... 0x05:
2587 add: /* add */
05f086f8 2588 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2589 break;
0934ac9d 2590 case 0x06: /* push es */
0934ac9d
MG		 2591 emulate_push_sreg(ctxt, VCPU_SREG_ES);
2592 break;
2593 case 0x07: /* pop es */
0934ac9d 2594 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2595 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2596 goto done;
2597 break;
6aa8b732
AK		 2598 case 0x08 ... 0x0d:
2599 or: /* or */
05f086f8 2600 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2601 break;
0934ac9d 2602 case 0x0e: /* push cs */
0934ac9d
MG		 2603 emulate_push_sreg(ctxt, VCPU_SREG_CS);
2604 break;
6aa8b732
AK		 2605 case 0x10 ... 0x15:
2606 adc: /* adc */
05f086f8 2607 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2608 break;
0934ac9d 2609 case 0x16: /* push ss */
0934ac9d
MG		 2610 emulate_push_sreg(ctxt, VCPU_SREG_SS);
2611 break;
2612 case 0x17: /* pop ss */
0934ac9d 2613 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2614 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2615 goto done;
2616 break;
6aa8b732
AK		 2617 case 0x18 ... 0x1d:
2618 sbb: /* sbb */
05f086f8 2619 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2620 break;
0934ac9d 2621 case 0x1e: /* push ds */
0934ac9d
MG		 2622 emulate_push_sreg(ctxt, VCPU_SREG_DS);
2623 break;
2624 case 0x1f: /* pop ds */
0934ac9d 2625 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2626 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2627 goto done;
2628 break;
aa3a816b 2629 case 0x20 ... 0x25:
6aa8b732 2630 and: /* and */
05f086f8 2631 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2632 break;
2633 case 0x28 ... 0x2d:
2634 sub: /* sub */
05f086f8 2635 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2636 break;
2637 case 0x30 ... 0x35:
2638 xor: /* xor */
05f086f8 2639 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2640 break;
2641 case 0x38 ... 0x3d:
2642 cmp: /* cmp */
05f086f8 2643 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2644 break;
33615aa9
AK		 2645 case 0x40 ... 0x47: /* inc r16/r32 */
2646 emulate_1op("inc", c->dst, ctxt->eflags);
2647 break;
2648 case 0x48 ... 0x4f: /* dec r16/r32 */
2649 emulate_1op("dec", c->dst, ctxt->eflags);
2650 break;
2651 case 0x50 ... 0x57: /* push reg */
2786b014 2652 emulate_push(ctxt);
33615aa9
AK		 2653 break;
2654 case 0x58 ... 0x5f: /* pop reg */
2655 pop_instruction:
350f69dc 2656 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2657 if (rc != X86EMUL_CONTINUE)
33615aa9 2658 goto done;
33615aa9 2659 break;
abcf14b5
MG		 2660 case 0x60: /* pusha */
2661 emulate_pusha(ctxt);
2662 break;
2663 case 0x61: /* popa */
2664 rc = emulate_popa(ctxt, ops);
1b30eaa8 2665 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2666 goto done;
2667 break;
6aa8b732 2668 case 0x63: /* movsxd */
8b4caf66 2669 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2670 goto cannot_emulate;
e4e03ded 2671 c->dst.val = (s32) c->src.val;
6aa8b732 2672 break;
91ed7a0e 2673 case 0x68: /* push imm */
018a98db 2674 case 0x6a: /* push imm8 */
018a98db
AK		 2675 emulate_push(ctxt);
2676 break;
2677 case 0x6c: /* insb */
2678 case 0x6d: /* insw/insd */
7972995b 2679 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2680 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2681 c->dst.bytes)) {
f850e2e6
GN		 2682 kvm_inject_gp(ctxt->vcpu, 0);
2683 goto done;
2684 }
7b262e90
GN		 2685 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2686 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2687 goto done; /* IO is needed, skip writeback */
2688 break;
018a98db
AK		 2689 case 0x6e: /* outsb */
2690 case 0x6f: /* outsw/outsd */
7972995b 2691 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2692 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2693 c->src.bytes)) {
f850e2e6
GN		 2694 kvm_inject_gp(ctxt->vcpu, 0);
2695 goto done;
2696 }
7972995b
GN		 2697 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2698 &c->src.val, 1, ctxt->vcpu);
2699
2700 c->dst.type = OP_NONE; /* nothing to writeback */
2701 break;
b2833e3c 2702 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2703 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2704 jmp_rel(c, c->src.val);
018a98db 2705 break;
6aa8b732 2706 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2707 switch (c->modrm_reg) {
6aa8b732
AK		 2708 case 0:
2709 goto add;
2710 case 1:
2711 goto or;
2712 case 2:
2713 goto adc;
2714 case 3:
2715 goto sbb;
2716 case 4:
2717 goto and;
2718 case 5:
2719 goto sub;
2720 case 6:
2721 goto xor;
2722 case 7:
2723 goto cmp;
2724 }
2725 break;
2726 case 0x84 ... 0x85:
05f086f8 2727 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2728 break;
2729 case 0x86 ... 0x87: /* xchg */
b13354f8 2730 xchg:
6aa8b732 2731 /* Write back the register source. */
e4e03ded 2732 switch (c->dst.bytes) {
6aa8b732 2733 case 1:
e4e03ded 2734 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2735 break;
2736 case 2:
e4e03ded 2737 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2738 break;
2739 case 4:
e4e03ded 2740 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2741 break; /* 64b reg: zero-extend */
2742 case 8:
e4e03ded 2743 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2744 break;
2745 }
2746 /*
2747 * Write back the memory destination with implicit LOCK
2748 * prefix.
2749 */
e4e03ded
LV		 2750 c->dst.val = c->src.val;
2751 c->lock_prefix = 1;
6aa8b732 2752 break;
6aa8b732 2753 case 0x88 ... 0x8b: /* mov */
7de75248 2754 goto mov;
38d5bc6d
GT		 2755 case 0x8c: { /* mov r/m, sreg */
2756 struct kvm_segment segreg;
2757
5e3ae6c5 2758 if (c->modrm_reg <= VCPU_SREG_GS)
38d5bc6d
GT		 2759 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2760 else {
5e3ae6c5
GN		 2761 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2762 goto done;
38d5bc6d
GT		 2763 }
2764 c->dst.val = segreg.selector;
2765 break;
2766 }
7e0b54b1 2767 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2768 c->dst.val = c->modrm_ea;
7e0b54b1 2769 break;
4257198a
GT		 2770 case 0x8e: { /* mov seg, r/m16 */
2771 uint16_t sel;
4257198a
GT		 2772
2773 sel = c->src.val;
8b9f4414 2774
c697518a
GN		 2775 if (c->modrm_reg == VCPU_SREG_CS ||
2776 c->modrm_reg > VCPU_SREG_GS) {
8b9f4414
GN		 2777 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2778 goto done;
2779 }
2780
310b5d30 2781 if (c->modrm_reg == VCPU_SREG_SS)
48005f64 2782 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS);
310b5d30 2783
2e873022 2784 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2785
2786 c->dst.type = OP_NONE; /* Disable writeback. */
2787 break;
2788 }
6aa8b732 2789 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2790 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2791 if (rc != X86EMUL_CONTINUE)
6aa8b732 2792 goto done;
6aa8b732 2793 break;
b13354f8 2794 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2795 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2796 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2797 break;
2798 }
2799 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2800 c->src.type = OP_REG;
2801 c->src.bytes = c->op_bytes;
b13354f8
MG		 2802 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2803 c->src.val = *(c->src.ptr);
2804 goto xchg;
fd2a7608 2805 case 0x9c: /* pushf */
05f086f8 2806 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2807 emulate_push(ctxt);
2808 break;
535eabcf 2809 case 0x9d: /* popf */
2b48cc75 2810 c->dst.type = OP_REG;
05f086f8 2811 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2812 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2813 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2814 if (rc != X86EMUL_CONTINUE)
2815 goto done;
2816 break;
018a98db
AK		 2817 case 0xa0 ... 0xa1: /* mov */
2818 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2819 c->dst.val = c->src.val;
2820 break;
2821 case 0xa2 ... 0xa3: /* mov */
2822 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2823 break;
6aa8b732 2824 case 0xa4 ... 0xa5: /* movs */
a682e354 2825 goto mov;
6aa8b732 2826 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2827 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2828 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2829 goto cmp;
6aa8b732 2830 case 0xaa ... 0xab: /* stos */
e4e03ded 2831 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2832 break;
2833 case 0xac ... 0xad: /* lods */
a682e354 2834 goto mov;
6aa8b732
AK		 2835 case 0xae ... 0xaf: /* scas */
2836 DPRINTF("Urk! I don't handle SCAS.\n");
2837 goto cannot_emulate;
a5e2e82b 2838 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2839 goto mov;
018a98db
AK		 2840 case 0xc0 ... 0xc1:
2841 emulate_grp2(ctxt);
2842 break;
111de5d6 2843 case 0xc3: /* ret */
cf5de4f8 2844 c->dst.type = OP_REG;
111de5d6 2845 c->dst.ptr = &c->eip;
cf5de4f8 2846 c->dst.bytes = c->op_bytes;
111de5d6 2847 goto pop_instruction;
018a98db
AK		 2848 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2849 mov:
2850 c->dst.val = c->src.val;
2851 break;
a77ab5ea
AK		 2852 case 0xcb: /* ret far */
2853 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2854 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2855 goto done;
2856 break;
018a98db
AK		 2857 case 0xd0 ... 0xd1: /* Grp2 */
2858 c->src.val = 1;
2859 emulate_grp2(ctxt);
2860 break;
2861 case 0xd2 ... 0xd3: /* Grp2 */
2862 c->src.val = c->regs[VCPU_REGS_RCX];
2863 emulate_grp2(ctxt);
2864 break;
a6a3034c
MG		 2865 case 0xe4: /* inb */
2866 case 0xe5: /* in */
cf8f70bf 2867 goto do_io_in;
a6a3034c
MG		 2868 case 0xe6: /* outb */
2869 case 0xe7: /* out */
cf8f70bf 2870 goto do_io_out;
1a52e051 2871 case 0xe8: /* call (near) */ {
d53c4777 2872 long int rel = c->src.val;
e4e03ded 2873 c->src.val = (unsigned long) c->eip;
7a957275 2874 jmp_rel(c, rel);
8cdbd2c9
LV		 2875 emulate_push(ctxt);
2876 break;
1a52e051
NK		 2877 }
2878 case 0xe9: /* jmp rel */
954cd36f 2879 goto jmp;
414e6277
GN		 2880 case 0xea: { /* jmp far */
2881 unsigned short sel;
ea79849d 2882 jump_far:
414e6277
GN		 2883 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2884
2885 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2886 goto done;
954cd36f 2887
414e6277
GN		 2888 c->eip = 0;
2889 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2890 break;
414e6277 2891 }
954cd36f
GT		 2892 case 0xeb:
2893 jmp: /* jmp rel short */
7a957275 2894 jmp_rel(c, c->src.val);
a01af5ec 2895 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2896 break;
a6a3034c
MG		 2897 case 0xec: /* in al,dx */
2898 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2899 c->src.val = c->regs[VCPU_REGS_RDX];
2900 do_io_in:
2901 c->dst.bytes = min(c->dst.bytes, 4u);
2902 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2903 kvm_inject_gp(ctxt->vcpu, 0);
2904 goto done;
2905 }
7b262e90
GN		 2906 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2907 &c->dst.val))
cf8f70bf
GN		 2908 goto done; /* IO is needed */
2909 break;
a6a3034c
MG		 2910 case 0xee: /* out al,dx */
2911 case 0xef: /* out (e/r)ax,dx */
cf8f70bf
GN		 2912 c->src.val = c->regs[VCPU_REGS_RDX];
2913 do_io_out:
2914 c->dst.bytes = min(c->dst.bytes, 4u);
2915 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
f850e2e6
GN		 2916 kvm_inject_gp(ctxt->vcpu, 0);
2917 goto done;
2918 }
cf8f70bf
GN		 2919 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2920 ctxt->vcpu);
2921 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2922 break;
111de5d6 2923 case 0xf4: /* hlt */
ad312c7c 2924 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2925 break;
111de5d6
AK		 2926 case 0xf5: /* cmc */
2927 /* complement carry flag from eflags reg */
2928 ctxt->eflags ^= EFLG_CF;
2929 c->dst.type = OP_NONE; /* Disable writeback. */
2930 break;
018a98db 2931 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2932 if (!emulate_grp3(ctxt, ops))
2933 goto cannot_emulate;
018a98db 2934 break;
111de5d6
AK		 2935 case 0xf8: /* clc */
2936 ctxt->eflags &= ~EFLG_CF;
2937 c->dst.type = OP_NONE; /* Disable writeback. */
2938 break;
2939 case 0xfa: /* cli */
9c537244 2940 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2941 kvm_inject_gp(ctxt->vcpu, 0);
2942 else {
2943 ctxt->eflags &= ~X86_EFLAGS_IF;
2944 c->dst.type = OP_NONE; /* Disable writeback. */
2945 }
111de5d6
AK		 2946 break;
2947 case 0xfb: /* sti */
9c537244 2948 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2949 kvm_inject_gp(ctxt->vcpu, 0);
2950 else {
48005f64 2951 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI);
f850e2e6
GN		 2952 ctxt->eflags |= X86_EFLAGS_IF;
2953 c->dst.type = OP_NONE; /* Disable writeback. */
2954 }
111de5d6 2955 break;
fb4616f4
MG		 2956 case 0xfc: /* cld */
2957 ctxt->eflags &= ~EFLG_DF;
2958 c->dst.type = OP_NONE; /* Disable writeback. */
2959 break;
2960 case 0xfd: /* std */
2961 ctxt->eflags |= EFLG_DF;
2962 c->dst.type = OP_NONE; /* Disable writeback. */
2963 break;
ea79849d
GN		 2964 case 0xfe: /* Grp4 */
2965 grp45:
018a98db 2966 rc = emulate_grp45(ctxt, ops);
1b30eaa8 2967 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2968 goto done;
2969 break;
ea79849d
GN		 2970 case 0xff: /* Grp5 */
2971 if (c->modrm_reg == 5)
2972 goto jump_far;
2973 goto grp45;
6aa8b732 2974 }
018a98db
AK		 2975
2976writeback:
2977 rc = writeback(ctxt, ops);
1b30eaa8 2978 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2979 goto done;
2980
5cd21917
GN		 2981 /*
2982 * restore dst type in case the decoding will be reused
2983 * (happens for string instruction )
2984 */
2985 c->dst.type = saved_dst_type;
2986
a682e354
GN		 2987 if ((c->d & SrcMask) == SrcSI)
2988 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI,
d9271123 2989 &c->src);
a682e354
GN		 2990
2991 if ((c->d & DstMask) == DstDI)
d9271123
GN		 2992 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst);
2993
5cd21917 2994 if (c->rep_prefix && (c->d & String)) {
7b262e90 2995 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 2996 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 2997 /*
2998 * Re-enter guest when pio read ahead buffer is empty or,
2999 * if it is not used, after each 1024 iteration.
3000 */
3001 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3002 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3003 ctxt->restart = false;
3004 }
9de41573
GN		 3005 /*
3006 * reset read cache here in case string instruction is restared
3007 * without decoding
3008 */
3009 ctxt->decode.mem_read.end = 0;
018a98db 3010 /* Commit shadow register state. */
ad312c7c 3011 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 3012 kvm_rip_write(ctxt->vcpu, c->eip);
482ac18a 3013 ops->set_rflags(ctxt->vcpu, ctxt->eflags);
018a98db
AK		 3014
3015done:
cb404fe0 3016 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3017
3018twobyte_insn:
e4e03ded 3019 switch (c->b) {
6aa8b732 3020 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3021 switch (c->modrm_reg) {
6aa8b732
AK		 3022 u16 size;
3023 unsigned long address;
3024
aca7f966 3025 case 0: /* vmcall */
e4e03ded 3026 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3027 goto cannot_emulate;
3028
7aa81cc0 3029 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3030 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3031 goto done;
3032
33e3885d 3033 /* Let the processor re-execute the fixed hypercall */
063db061 3034 c->eip = ctxt->eip;
16286d08
AK		 3035 /* Disable writeback. */
3036 c->dst.type = OP_NONE;
aca7f966 3037 break;
6aa8b732 3038 case 2: /* lgdt */
e4e03ded
LV		 3039 rc = read_descriptor(ctxt, ops, c->src.ptr,
3040 &size, &address, c->op_bytes);
1b30eaa8 3041 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3042 goto done;
3043 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3044 /* Disable writeback. */
3045 c->dst.type = OP_NONE;
6aa8b732 3046 break;
aca7f966 3047 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3048 if (c->modrm_mod == 3) {
3049 switch (c->modrm_rm) {
3050 case 1:
3051 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3052 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3053 goto done;
3054 break;
3055 default:
3056 goto cannot_emulate;
3057 }
aca7f966 3058 } else {
e4e03ded 3059 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3060 &size, &address,
e4e03ded 3061 c->op_bytes);
1b30eaa8 3062 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3063 goto done;
3064 realmode_lidt(ctxt->vcpu, size, address);
3065 }
16286d08
AK		 3066 /* Disable writeback. */
3067 c->dst.type = OP_NONE;
6aa8b732
AK		 3068 break;
3069 case 4: /* smsw */
16286d08 3070 c->dst.bytes = 2;
52a46617 3071 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3072 break;
3073 case 6: /* lmsw */
93a152be
GN		 3074 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3075 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3076 c->dst.type = OP_NONE;
6aa8b732 3077 break;
6e1e5ffe
GN		 3078 case 5: /* not defined */
3079 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3080 goto done;
6aa8b732 3081 case 7: /* invlpg*/
69f55cb1 3082 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3083 /* Disable writeback. */
3084 c->dst.type = OP_NONE;
6aa8b732
AK		 3085 break;
3086 default:
3087 goto cannot_emulate;
3088 }
3089 break;
e99f0507 3090 case 0x05: /* syscall */
3fb1b5db 3091 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3092 if (rc != X86EMUL_CONTINUE)
3093 goto done;
e66bb2cc
AP		 3094 else
3095 goto writeback;
e99f0507 3096 break;
018a98db
AK		 3097 case 0x06:
3098 emulate_clts(ctxt->vcpu);
3099 c->dst.type = OP_NONE;
3100 break;
3101 case 0x08: /* invd */
3102 case 0x09: /* wbinvd */
3103 case 0x0d: /* GrpP (prefetch) */
3104 case 0x18: /* Grp16 (prefetch/nop) */
3105 c->dst.type = OP_NONE;
3106 break;
3107 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3108 switch (c->modrm_reg) {
3109 case 1:
3110 case 5 ... 7:
3111 case 9 ... 15:
3112 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3113 goto done;
3114 }
52a46617 3115 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3116 c->dst.type = OP_NONE; /* no writeback */
3117 break;
6aa8b732 3118 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3119 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3120 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3121 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3122 goto done;
3123 }
35aa5375 3124 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3125 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3126 break;
018a98db 3127 case 0x22: /* mov reg, cr */
52a46617 3128 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu);
018a98db
AK		 3129 c->dst.type = OP_NONE;
3130 break;
6aa8b732 3131 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3132 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3133 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3134 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3135 goto done;
3136 }
35aa5375
GN		 3137
3138 ops->set_dr(c->modrm_reg,c->regs[c->modrm_rm] &
3139 ((ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U),
3140 ctxt->vcpu);
a01af5ec 3141 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3142 break;
018a98db
AK		 3143 case 0x30:
3144 /* wrmsr */
3145 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3146 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3147 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
c1a5d4f9 3148 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3149 goto done;
018a98db
AK		 3150 }
3151 rc = X86EMUL_CONTINUE;
3152 c->dst.type = OP_NONE;
3153 break;
3154 case 0x32:
3155 /* rdmsr */
3fb1b5db 3156 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
c1a5d4f9 3157 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3158 goto done;
018a98db
AK		 3159 } else {
3160 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3161 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3162 }
3163 rc = X86EMUL_CONTINUE;
3164 c->dst.type = OP_NONE;
3165 break;
e99f0507 3166 case 0x34: /* sysenter */
3fb1b5db 3167 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3168 if (rc != X86EMUL_CONTINUE)
3169 goto done;
8c604352
AP		 3170 else
3171 goto writeback;
e99f0507
AP		 3172 break;
3173 case 0x35: /* sysexit */
3fb1b5db 3174 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3175 if (rc != X86EMUL_CONTINUE)
3176 goto done;
4668f050
AP		 3177 else
3178 goto writeback;
e99f0507 3179 break;
6aa8b732 3180 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3181 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3182 if (!test_cc(c->b, ctxt->eflags))
3183 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3184 break;
b2833e3c 3185 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3186 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3187 jmp_rel(c, c->src.val);
018a98db
AK		 3188 c->dst.type = OP_NONE;
3189 break;
0934ac9d
MG		 3190 case 0xa0: /* push fs */
3191 emulate_push_sreg(ctxt, VCPU_SREG_FS);
3192 break;
3193 case 0xa1: /* pop fs */
3194 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3195 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3196 goto done;
3197 break;
7de75248
NK		 3198 case 0xa3:
3199 bt: /* bt */
e4f8e039 3200 c->dst.type = OP_NONE;
e4e03ded
LV		 3201 /* only subword offset */
3202 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3203 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3204 break;
9bf8ea42
GT		 3205 case 0xa4: /* shld imm8, r, r/m */
3206 case 0xa5: /* shld cl, r, r/m */
3207 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3208 break;
0934ac9d
MG		 3209 case 0xa8: /* push gs */
3210 emulate_push_sreg(ctxt, VCPU_SREG_GS);
3211 break;
3212 case 0xa9: /* pop gs */
3213 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3214 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3215 goto done;
3216 break;
7de75248
NK		 3217 case 0xab:
3218 bts: /* bts */
e4e03ded
LV		 3219 /* only subword offset */
3220 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3221 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3222 break;
9bf8ea42
GT		 3223 case 0xac: /* shrd imm8, r, r/m */
3224 case 0xad: /* shrd cl, r, r/m */
3225 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3226 break;
2a7c5b8b
GC		 3227 case 0xae: /* clflush */
3228 break;
6aa8b732
AK		 3229 case 0xb0 ... 0xb1: /* cmpxchg */
3230 /*
3231 * Save real source value, then compare EAX against
3232 * destination.
3233 */
e4e03ded
LV		 3234 c->src.orig_val = c->src.val;
3235 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3236 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3237 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3238 /* Success: write back to memory. */
e4e03ded 3239 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3240 } else {
3241 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3242 c->dst.type = OP_REG;
3243 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3244 }
3245 break;
6aa8b732
AK		 3246 case 0xb3:
3247 btr: /* btr */
e4e03ded
LV		 3248 /* only subword offset */
3249 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3250 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3251 break;
6aa8b732 3252 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3253 c->dst.bytes = c->op_bytes;
3254 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3255 : (u16) c->src.val;
6aa8b732 3256 break;
6aa8b732 3257 case 0xba: /* Grp8 */
e4e03ded 3258 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3259 case 0:
3260 goto bt;
3261 case 1:
3262 goto bts;
3263 case 2:
3264 goto btr;
3265 case 3:
3266 goto btc;
3267 }
3268 break;
7de75248
NK		 3269 case 0xbb:
3270 btc: /* btc */
e4e03ded
LV		 3271 /* only subword offset */
3272 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3273 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3274 break;
6aa8b732 3275 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3276 c->dst.bytes = c->op_bytes;
3277 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3278 (s16) c->src.val;
6aa8b732 3279 break;
a012e65a 3280 case 0xc3: /* movnti */
e4e03ded
LV		 3281 c->dst.bytes = c->op_bytes;
3282 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3283 (u64) c->src.val;
a012e65a 3284 break;
6aa8b732 3285 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3286 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3287 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3288 goto done;
3289 break;
6aa8b732
AK		 3290 }
3291 goto writeback;
3292
3293cannot_emulate:
e4e03ded 3294 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3295 return -1;
3296}
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