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KVM: emulate: avoid repeated calls to do_insn_fetch_bytes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
6aa8b732 167
820207c8 168#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 169
d0e53325
AK		 170#define X2(x...) x, x
171#define X3(x...) X2(x), x
172#define X4(x...) X2(x), X2(x)
173#define X5(x...) X4(x), x
174#define X6(x...) X4(x), X2(x)
175#define X7(x...) X4(x), X3(x)
176#define X8(x...) X4(x), X4(x)
177#define X16(x...) X8(x), X8(x)
83babbca 178
e28bbd44
AK		 179#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
180#define FASTOP_SIZE 8
181
182/*
183 * fastop functions have a special calling convention:
184 *
017da7b6
AK		 185 * dst: rax (in/out)
186 * src: rdx (in/out)
e28bbd44
AK		 187 * src2: rcx (in)
188 * flags: rflags (in/out)
b8c0b6ae 189 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 190 *
191 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
192 * different operand sizes can be reached by calculation, rather than a jump
193 * table (which would be bigger than the code).
194 *
195 * fastop functions are declared as taking a never-defined fastop parameter,
196 * so they can't be called from C directly.
197 */
198
199struct fastop;
200
d65b1dee 201struct opcode {
b1ea50b2
AK		 202 u64 flags : 56;
203 u64 intercept : 8;
120df890 204 union {
ef65c889 205 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 206 const struct opcode *group;
207 const struct group_dual *gdual;
208 const struct gprefix *gprefix;
045a282c 209 const struct escape *esc;
e28bbd44 210 void (*fastop)(struct fastop *fake);
120df890 211 } u;
d09beabd 212 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 213};
214
215struct group_dual {
216 struct opcode mod012[8];
217 struct opcode mod3[8];
d65b1dee
AK		 218};
219
0d7cdee8
AK		 220struct gprefix {
221 struct opcode pfx_no;
222 struct opcode pfx_66;
223 struct opcode pfx_f2;
224 struct opcode pfx_f3;
225};
226
045a282c
GN		 227struct escape {
228 struct opcode op[8];
229 struct opcode high[64];
230};
231
6aa8b732 232/* EFLAGS bit definitions. */
d4c6a154
GN		 233#define EFLG_ID (1<<21)
234#define EFLG_VIP (1<<20)
235#define EFLG_VIF (1<<19)
236#define EFLG_AC (1<<18)
b1d86143
AP		 237#define EFLG_VM (1<<17)
238#define EFLG_RF (1<<16)
d4c6a154
GN		 239#define EFLG_IOPL (3<<12)
240#define EFLG_NT (1<<14)
6aa8b732
AK		 241#define EFLG_OF (1<<11)
242#define EFLG_DF (1<<10)
b1d86143 243#define EFLG_IF (1<<9)
d4c6a154 244#define EFLG_TF (1<<8)
6aa8b732
AK		 245#define EFLG_SF (1<<7)
246#define EFLG_ZF (1<<6)
247#define EFLG_AF (1<<4)
248#define EFLG_PF (1<<2)
249#define EFLG_CF (1<<0)
250
62bd430e
MG		 251#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
252#define EFLG_RESERVED_ONE_MASK 2
253
dd856efa
AK		 254static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
255{
256 if (!(ctxt->regs_valid & (1 << nr))) {
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
259 }
260 return ctxt->_regs[nr];
261}
262
263static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->regs_dirty |= 1 << nr;
267 return &ctxt->_regs[nr];
268}
269
270static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
271{
272 reg_read(ctxt, nr);
273 return reg_write(ctxt, nr);
274}
275
276static void writeback_registers(struct x86_emulate_ctxt *ctxt)
277{
278 unsigned reg;
279
280 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
281 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
282}
283
284static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
285{
286 ctxt->regs_dirty = 0;
287 ctxt->regs_valid = 0;
288}
289
6aa8b732
AK		 290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
dda96d8f
AK		 296#ifdef CONFIG_X86_64
297#define ON64(x) x
298#else
299#define ON64(x)
300#endif
301
4d758349
AK		 302static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
303
b7d491e7
AK		 304#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
305#define FOP_RET "ret \n\t"
306
307#define FOP_START(op) \
308 extern void em_##op(struct fastop *fake); \
309 asm(".pushsection .text, \"ax\" \n\t" \
310 ".global em_" #op " \n\t" \
311 FOP_ALIGN \
312 "em_" #op ": \n\t"
313
314#define FOP_END \
315 ".popsection")
316
0bdea068
AK		 317#define FOPNOP() FOP_ALIGN FOP_RET
318
b7d491e7 319#define FOP1E(op, dst) \
b8c0b6ae
AK		 320 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
321
322#define FOP1EEX(op, dst) \
323 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 324
325#define FASTOP1(op) \
326 FOP_START(op) \
327 FOP1E(op##b, al) \
328 FOP1E(op##w, ax) \
329 FOP1E(op##l, eax) \
330 ON64(FOP1E(op##q, rax)) \
331 FOP_END
332
b9fa409b
AK		 333/* 1-operand, using src2 (for MUL/DIV r/m) */
334#define FASTOP1SRC2(op, name) \
335 FOP_START(name) \
336 FOP1E(op, cl) \
337 FOP1E(op, cx) \
338 FOP1E(op, ecx) \
339 ON64(FOP1E(op, rcx)) \
340 FOP_END
341
b8c0b6ae
AK		 342/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
343#define FASTOP1SRC2EX(op, name) \
344 FOP_START(name) \
345 FOP1EEX(op, cl) \
346 FOP1EEX(op, cx) \
347 FOP1EEX(op, ecx) \
348 ON64(FOP1EEX(op, rcx)) \
349 FOP_END
350
f7857f35
AK		 351#define FOP2E(op, dst, src) \
352 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
353
354#define FASTOP2(op) \
355 FOP_START(op) \
017da7b6
AK		 356 FOP2E(op##b, al, dl) \
357 FOP2E(op##w, ax, dx) \
358 FOP2E(op##l, eax, edx) \
359 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 360 FOP_END
361
11c363ba
AK		 362/* 2 operand, word only */
363#define FASTOP2W(op) \
364 FOP_START(op) \
365 FOPNOP() \
017da7b6
AK		 366 FOP2E(op##w, ax, dx) \
367 FOP2E(op##l, eax, edx) \
368 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 369 FOP_END
370
007a3b54
AK		 371/* 2 operand, src is CL */
372#define FASTOP2CL(op) \
373 FOP_START(op) \
374 FOP2E(op##b, al, cl) \
375 FOP2E(op##w, ax, cl) \
376 FOP2E(op##l, eax, cl) \
377 ON64(FOP2E(op##q, rax, cl)) \
378 FOP_END
379
0bdea068
AK		 380#define FOP3E(op, dst, src, src2) \
381 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
382
383/* 3-operand, word-only, src2=cl */
384#define FASTOP3WCL(op) \
385 FOP_START(op) \
386 FOPNOP() \
017da7b6
AK		 387 FOP3E(op##w, ax, dx, cl) \
388 FOP3E(op##l, eax, edx, cl) \
389 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 390 FOP_END
391
9ae9feba
AK		 392/* Special case for SETcc - 1 instruction per cc */
393#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
394
b8c0b6ae
AK		 395asm(".global kvm_fastop_exception \n"
396 "kvm_fastop_exception: xor %esi, %esi; ret");
397
9ae9feba
AK		 398FOP_START(setcc)
399FOP_SETCC(seto)
400FOP_SETCC(setno)
401FOP_SETCC(setc)
402FOP_SETCC(setnc)
403FOP_SETCC(setz)
404FOP_SETCC(setnz)
405FOP_SETCC(setbe)
406FOP_SETCC(setnbe)
407FOP_SETCC(sets)
408FOP_SETCC(setns)
409FOP_SETCC(setp)
410FOP_SETCC(setnp)
411FOP_SETCC(setl)
412FOP_SETCC(setnl)
413FOP_SETCC(setle)
414FOP_SETCC(setnle)
415FOP_END;
416
326f578f
PB		 417FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
418FOP_END;
419
8a76d7f2
JR		 420static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
421 enum x86_intercept intercept,
422 enum x86_intercept_stage stage)
423{
424 struct x86_instruction_info info = {
425 .intercept = intercept,
9dac77fa
AK		 426 .rep_prefix = ctxt->rep_prefix,
427 .modrm_mod = ctxt->modrm_mod,
428 .modrm_reg = ctxt->modrm_reg,
429 .modrm_rm = ctxt->modrm_rm,
430 .src_val = ctxt->src.val64,
6cbc5f5a 431 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 432 .src_bytes = ctxt->src.bytes,
433 .dst_bytes = ctxt->dst.bytes,
434 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 435 .next_rip = ctxt->eip,
436 };
437
2953538e 438 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 439}
440
f47cfa31
AK		 441static void assign_masked(ulong *dest, ulong src, ulong mask)
442{
443 *dest = (*dest & ~mask) | (src & mask);
444}
445
9dac77fa 446static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 447{
9dac77fa 448 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 449}
450
f47cfa31
AK		 451static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
452{
453 u16 sel;
454 struct desc_struct ss;
455
456 if (ctxt->mode == X86EMUL_MODE_PROT64)
457 return ~0UL;
458 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
459 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
460}
461
612e89f0
AK		 462static int stack_size(struct x86_emulate_ctxt *ctxt)
463{
464 return (__fls(stack_mask(ctxt)) + 1) >> 3;
465}
466
6aa8b732 467/* Access/update address held in a register, based on addressing mode. */
e4706772 468static inline unsigned long
9dac77fa 469address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 470{
9dac77fa 471 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 472 return reg;
473 else
9dac77fa 474 return reg & ad_mask(ctxt);
e4706772
HH		 475}
476
477static inline unsigned long
9dac77fa 478register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 479{
9dac77fa 480 return address_mask(ctxt, reg);
e4706772
HH		 481}
482
5ad105e5
AK		 483static void masked_increment(ulong *reg, ulong mask, int inc)
484{
485 assign_masked(reg, *reg + inc, mask);
486}
487
7a957275 488static inline void
9dac77fa 489register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 490{
5ad105e5
AK		 491 ulong mask;
492
9dac77fa 493 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 494 mask = ~0UL;
7a957275 495 else
5ad105e5
AK		 496 mask = ad_mask(ctxt);
497 masked_increment(reg, mask, inc);
498}
499
500static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
501{
dd856efa 502 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 503}
6aa8b732 504
9dac77fa 505static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 506{
9dac77fa 507 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 508}
098c937b 509
56697687
AK		 510static u32 desc_limit_scaled(struct desc_struct *desc)
511{
512 u32 limit = get_desc_limit(desc);
513
514 return desc->g ? (limit << 12) | 0xfff : limit;
515}
516
7b105ca2 517static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 518{
519 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
520 return 0;
521
7b105ca2 522 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 523}
524
35d3d4a1
AK		 525static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
526 u32 error, bool valid)
54b8486f 527{
da9cb575
AK		 528 ctxt->exception.vector = vec;
529 ctxt->exception.error_code = error;
530 ctxt->exception.error_code_valid = valid;
35d3d4a1 531 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 532}
533
3b88e41a
JR		 534static int emulate_db(struct x86_emulate_ctxt *ctxt)
535{
536 return emulate_exception(ctxt, DB_VECTOR, 0, false);
537}
538
35d3d4a1 539static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 540{
35d3d4a1 541 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 542}
543
618ff15d
AK		 544static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
545{
546 return emulate_exception(ctxt, SS_VECTOR, err, true);
547}
548
35d3d4a1 549static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 550{
35d3d4a1 551 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 552}
553
35d3d4a1 554static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 555{
35d3d4a1 556 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 557}
558
34d1f490
AK		 559static int emulate_de(struct x86_emulate_ctxt *ctxt)
560{
35d3d4a1 561 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 562}
563
1253791d
AK		 564static int emulate_nm(struct x86_emulate_ctxt *ctxt)
565{
566 return emulate_exception(ctxt, NM_VECTOR, 0, false);
567}
568
1aa36616
AK		 569static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
570{
571 u16 selector;
572 struct desc_struct desc;
573
574 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
575 return selector;
576}
577
578static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
579 unsigned seg)
580{
581 u16 dummy;
582 u32 base3;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
586 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
587}
588
1c11b376
AK		 589/*
590 * x86 defines three classes of vector instructions: explicitly
591 * aligned, explicitly unaligned, and the rest, which change behaviour
592 * depending on whether they're AVX encoded or not.
593 *
594 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
595 * subject to the same check.
596 */
597static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
598{
599 if (likely(size < 16))
600 return false;
601
602 if (ctxt->d & Aligned)
603 return true;
604 else if (ctxt->d & Unaligned)
605 return false;
606 else if (ctxt->d & Avx)
607 return false;
608 else
609 return true;
610}
611
3d9b938e 612static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 613 struct segmented_address addr,
3d9b938e 614 unsigned size, bool write, bool fetch,
52fd8b44
AK		 615 ulong *linear)
616{
618ff15d
AK		 617 struct desc_struct desc;
618 bool usable;
52fd8b44 619 ulong la;
618ff15d 620 u32 lim;
1aa36616 621 u16 sel;
3a78a4f4 622 unsigned cpl;
52fd8b44 623
7b105ca2 624 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 625 switch (ctxt->mode) {
618ff15d
AK		 626 case X86EMUL_MODE_PROT64:
627 if (((signed long)la << 16) >> 16 != la)
628 return emulate_gp(ctxt, 0);
629 break;
630 default:
1aa36616
AK		 631 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
632 addr.seg);
618ff15d
AK		 633 if (!usable)
634 goto bad;
58b7825b
GN		 635 /* code segment in protected mode or read-only data segment */
636 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
637 || !(desc.type & 2)) && write)
618ff15d
AK		 638 goto bad;
639 /* unreadable code segment */
3d9b938e 640 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 641 goto bad;
642 lim = desc_limit_scaled(&desc);
643 if ((desc.type & 8) || !(desc.type & 4)) {
644 /* expand-up segment */
645 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
646 goto bad;
647 } else {
fc058680 648 /* expand-down segment */
618ff15d
AK		 649 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
650 goto bad;
651 lim = desc.d ? 0xffffffff : 0xffff;
652 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
653 goto bad;
654 }
717746e3 655 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 656 if (!(desc.type & 8)) {
657 /* data segment */
658 if (cpl > desc.dpl)
659 goto bad;
660 } else if ((desc.type & 8) && !(desc.type & 4)) {
661 /* nonconforming code segment */
662 if (cpl != desc.dpl)
663 goto bad;
664 } else if ((desc.type & 8) && (desc.type & 4)) {
665 /* conforming code segment */
666 if (cpl < desc.dpl)
667 goto bad;
668 }
669 break;
670 }
9dac77fa 671 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 672 la &= (u32)-1;
1c11b376
AK		 673 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
674 return emulate_gp(ctxt, 0);
52fd8b44
AK		 675 *linear = la;
676 return X86EMUL_CONTINUE;
618ff15d
AK		 677bad:
678 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 679 return emulate_ss(ctxt, sel);
618ff15d 680 else
0afbe2f8 681 return emulate_gp(ctxt, sel);
52fd8b44
AK		 682}
683
3d9b938e
NE		 684static int linearize(struct x86_emulate_ctxt *ctxt,
685 struct segmented_address addr,
686 unsigned size, bool write,
687 ulong *linear)
688{
689 return __linearize(ctxt, addr, size, write, false, linear);
690}
691
692
3ca3ac4d
AK		 693static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
694 struct segmented_address addr,
695 void *data,
696 unsigned size)
697{
9fa088f4
AK		 698 int rc;
699 ulong linear;
700
83b8795a 701 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 702 if (rc != X86EMUL_CONTINUE)
703 return rc;
0f65dd70 704 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 705}
706
807941b1 707/*
285ca9e9 708 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 709 * boundary if they are not in fetch_cache yet.
710 */
5cfc7e0f 711static int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 712{
9dac77fa 713 struct fetch_cache *fc = &ctxt->fetch;
62266869 714 int rc;
2fb53ad8 715 int size, cur_size;
285ca9e9
PB		 716 unsigned long linear;
717
718 struct segmented_address addr = { .seg = VCPU_SREG_CS,
719 .ea = fc->end };
720 cur_size = fc->end - fc->start;
721 size = min(15UL - cur_size,
722 PAGE_SIZE - offset_in_page(fc->end));
5cfc7e0f
PB		 723
724 /*
725 * One instruction can only straddle two pages,
726 * and one has been loaded at the beginning of
727 * x86_decode_insn. So, if not enough bytes
728 * still, we must have hit the 15-byte boundary.
729 */
730 if (unlikely(size < op_size))
285ca9e9
PB		 731 return X86EMUL_UNHANDLEABLE;
732 rc = __linearize(ctxt, addr, size, false, true, &linear);
733 if (unlikely(rc != X86EMUL_CONTINUE))
734 return rc;
735 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
736 size, &ctxt->exception);
737 if (unlikely(rc != X86EMUL_CONTINUE))
738 return rc;
739 fc->end += size;
3e2815e9 740 return X86EMUL_CONTINUE;
62266869
AK		 741}
742
743static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
285ca9e9 744 void *__dest, unsigned size)
62266869 745{
285ca9e9
PB		 746 struct fetch_cache *fc = &ctxt->fetch;
747 u8 *dest = __dest;
748 u8 *src = &fc->data[ctxt->_eip - fc->start];
62266869 749
5cfc7e0f
PB		 750 /* We have to be careful about overflow! */
751 if (unlikely(ctxt->_eip > fc->end - size)) {
752 int rc = do_insn_fetch_bytes(ctxt, size);
753 if (rc != X86EMUL_CONTINUE)
754 return rc;
755 }
756
62266869 757 while (size--) {
285ca9e9
PB		 758 *dest++ = *src++;
759 ctxt->_eip++;
760 continue;
62266869 761 }
3e2815e9 762 return X86EMUL_CONTINUE;
62266869
AK		 763}
764
67cbc90d 765/* Fetch next part of the instruction being emulated. */
e85a1085 766#define insn_fetch(_type, _ctxt) \
67cbc90d 767({ unsigned long _x; \
e85a1085 768 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 769 if (rc != X86EMUL_CONTINUE) \
770 goto done; \
67cbc90d
TY		 771 (_type)_x; \
772})
773
807941b1
TY		 774#define insn_fetch_arr(_arr, _size, _ctxt) \
775({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 776 if (rc != X86EMUL_CONTINUE) \
777 goto done; \
67cbc90d
TY		 778})
779
1e3c5cb0
RR		 780/*
781 * Given the 'reg' portion of a ModRM byte, and a register block, return a
782 * pointer into the block that addresses the relevant register.
783 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
784 */
dd856efa 785static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 786 int byteop)
6aa8b732
AK		 787{
788 void *p;
aa9ac1a6 789 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 790
6aa8b732 791 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 792 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
793 else
794 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 795 return p;
796}
797
798static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 799 struct segmented_address addr,
6aa8b732
AK		 800 u16 *size, unsigned long *address, int op_bytes)
801{
802 int rc;
803
804 if (op_bytes == 2)
805 op_bytes = 3;
806 *address = 0;
3ca3ac4d 807 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 808 if (rc != X86EMUL_CONTINUE)
6aa8b732 809 return rc;
30b31ab6 810 addr.ea += 2;
3ca3ac4d 811 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 812 return rc;
813}
814
34b77652
AK		 815FASTOP2(add);
816FASTOP2(or);
817FASTOP2(adc);
818FASTOP2(sbb);
819FASTOP2(and);
820FASTOP2(sub);
821FASTOP2(xor);
822FASTOP2(cmp);
823FASTOP2(test);
824
b9fa409b
AK		 825FASTOP1SRC2(mul, mul_ex);
826FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 827FASTOP1SRC2EX(div, div_ex);
828FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 829
34b77652
AK		 830FASTOP3WCL(shld);
831FASTOP3WCL(shrd);
832
833FASTOP2W(imul);
834
835FASTOP1(not);
836FASTOP1(neg);
837FASTOP1(inc);
838FASTOP1(dec);
839
840FASTOP2CL(rol);
841FASTOP2CL(ror);
842FASTOP2CL(rcl);
843FASTOP2CL(rcr);
844FASTOP2CL(shl);
845FASTOP2CL(shr);
846FASTOP2CL(sar);
847
848FASTOP2W(bsf);
849FASTOP2W(bsr);
850FASTOP2W(bt);
851FASTOP2W(bts);
852FASTOP2W(btr);
853FASTOP2W(btc);
854
e47a5f5f
AK		 855FASTOP2(xadd);
856
9ae9feba 857static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 858{
9ae9feba
AK		 859 u8 rc;
860 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 861
9ae9feba 862 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 863 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 864 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
865 return rc;
bbe9abbd
NK		 866}
867
91ff3cb4
AK		 868static void fetch_register_operand(struct operand *op)
869{
870 switch (op->bytes) {
871 case 1:
872 op->val = *(u8 *)op->addr.reg;
873 break;
874 case 2:
875 op->val = *(u16 *)op->addr.reg;
876 break;
877 case 4:
878 op->val = *(u32 *)op->addr.reg;
879 break;
880 case 8:
881 op->val = *(u64 *)op->addr.reg;
882 break;
883 }
884}
885
1253791d
AK		 886static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
887{
888 ctxt->ops->get_fpu(ctxt);
889 switch (reg) {
89a87c67
MK		 890 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
891 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
892 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
893 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
894 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
895 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
896 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
897 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 898#ifdef CONFIG_X86_64
89a87c67
MK		 899 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
900 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
901 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
902 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
903 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
904 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
905 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
906 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 907#endif
908 default: BUG();
909 }
910 ctxt->ops->put_fpu(ctxt);
911}
912
913static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
914 int reg)
915{
916 ctxt->ops->get_fpu(ctxt);
917 switch (reg) {
89a87c67
MK		 918 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
919 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
920 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
921 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
922 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
923 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
924 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
925 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 926#ifdef CONFIG_X86_64
89a87c67
MK		 927 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
928 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
929 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
930 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
931 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
932 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
933 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
934 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 935#endif
936 default: BUG();
937 }
938 ctxt->ops->put_fpu(ctxt);
939}
940
cbe2c9d3
AK		 941static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
942{
943 ctxt->ops->get_fpu(ctxt);
944 switch (reg) {
945 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
946 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
947 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
948 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
949 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
950 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
951 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
952 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
953 default: BUG();
954 }
955 ctxt->ops->put_fpu(ctxt);
956}
957
958static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
959{
960 ctxt->ops->get_fpu(ctxt);
961 switch (reg) {
962 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
963 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
964 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
965 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
966 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
967 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
968 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
969 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
970 default: BUG();
971 }
972 ctxt->ops->put_fpu(ctxt);
973}
974
045a282c
GN		 975static int em_fninit(struct x86_emulate_ctxt *ctxt)
976{
977 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
978 return emulate_nm(ctxt);
979
980 ctxt->ops->get_fpu(ctxt);
981 asm volatile("fninit");
982 ctxt->ops->put_fpu(ctxt);
983 return X86EMUL_CONTINUE;
984}
985
986static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
987{
988 u16 fcw;
989
990 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
991 return emulate_nm(ctxt);
992
993 ctxt->ops->get_fpu(ctxt);
994 asm volatile("fnstcw %0": "+m"(fcw));
995 ctxt->ops->put_fpu(ctxt);
996
997 /* force 2 byte destination */
998 ctxt->dst.bytes = 2;
999 ctxt->dst.val = fcw;
1000
1001 return X86EMUL_CONTINUE;
1002}
1003
1004static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1005{
1006 u16 fsw;
1007
1008 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1009 return emulate_nm(ctxt);
1010
1011 ctxt->ops->get_fpu(ctxt);
1012 asm volatile("fnstsw %0": "+m"(fsw));
1013 ctxt->ops->put_fpu(ctxt);
1014
1015 /* force 2 byte destination */
1016 ctxt->dst.bytes = 2;
1017 ctxt->dst.val = fsw;
1018
1019 return X86EMUL_CONTINUE;
1020}
1021
1253791d 1022static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1023 struct operand *op)
3c118e24 1024{
9dac77fa 1025 unsigned reg = ctxt->modrm_reg;
33615aa9 1026
9dac77fa
AK		 1027 if (!(ctxt->d & ModRM))
1028 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1029
9dac77fa 1030 if (ctxt->d & Sse) {
1253791d
AK		 1031 op->type = OP_XMM;
1032 op->bytes = 16;
1033 op->addr.xmm = reg;
1034 read_sse_reg(ctxt, &op->vec_val, reg);
1035 return;
1036 }
cbe2c9d3
AK		 1037 if (ctxt->d & Mmx) {
1038 reg &= 7;
1039 op->type = OP_MM;
1040 op->bytes = 8;
1041 op->addr.mm = reg;
1042 return;
1043 }
1253791d 1044
3c118e24 1045 op->type = OP_REG;
6d4d85ec
GN		 1046 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1047 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1048
91ff3cb4 1049 fetch_register_operand(op);
3c118e24
AK		 1050 op->orig_val = op->val;
1051}
1052
a6e3407b
AK		 1053static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1054{
1055 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1056 ctxt->modrm_seg = VCPU_SREG_SS;
1057}
1058
1c73ef66 1059static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1060 struct operand *op)
1c73ef66 1061{
1c73ef66 1062 u8 sib;
02357bdc 1063 int index_reg, base_reg, scale;
3e2815e9 1064 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1065 ulong modrm_ea = 0;
1c73ef66 1066
02357bdc
BD		 1067 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1068 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1069 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1070
02357bdc 1071 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1072 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1073 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1074 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1075
9b88ae99 1076 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1077 op->type = OP_REG;
9dac77fa 1078 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1079 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1080 ctxt->d & ByteOp);
9dac77fa 1081 if (ctxt->d & Sse) {
1253791d
AK		 1082 op->type = OP_XMM;
1083 op->bytes = 16;
9dac77fa
AK		 1084 op->addr.xmm = ctxt->modrm_rm;
1085 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1086 return rc;
1087 }
cbe2c9d3
AK		 1088 if (ctxt->d & Mmx) {
1089 op->type = OP_MM;
1090 op->bytes = 8;
bdc90722 1091 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1092 return rc;
1093 }
2dbd0dd7 1094 fetch_register_operand(op);
1c73ef66
AK		 1095 return rc;
1096 }
1097
2dbd0dd7
AK		 1098 op->type = OP_MEM;
1099
9dac77fa 1100 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1101 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1102 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1103 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1104 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1105
1106 /* 16-bit ModR/M decode. */
9dac77fa 1107 switch (ctxt->modrm_mod) {
1c73ef66 1108 case 0:
9dac77fa 1109 if (ctxt->modrm_rm == 6)
e85a1085 1110 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1111 break;
1112 case 1:
e85a1085 1113 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1114 break;
1115 case 2:
e85a1085 1116 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1117 break;
1118 }
9dac77fa 1119 switch (ctxt->modrm_rm) {
1c73ef66 1120 case 0:
2dbd0dd7 1121 modrm_ea += bx + si;
1c73ef66
AK		 1122 break;
1123 case 1:
2dbd0dd7 1124 modrm_ea += bx + di;
1c73ef66
AK		 1125 break;
1126 case 2:
2dbd0dd7 1127 modrm_ea += bp + si;
1c73ef66
AK		 1128 break;
1129 case 3:
2dbd0dd7 1130 modrm_ea += bp + di;
1c73ef66
AK		 1131 break;
1132 case 4:
2dbd0dd7 1133 modrm_ea += si;
1c73ef66
AK		 1134 break;
1135 case 5:
2dbd0dd7 1136 modrm_ea += di;
1c73ef66
AK		 1137 break;
1138 case 6:
9dac77fa 1139 if (ctxt->modrm_mod != 0)
2dbd0dd7 1140 modrm_ea += bp;
1c73ef66
AK		 1141 break;
1142 case 7:
2dbd0dd7 1143 modrm_ea += bx;
1c73ef66
AK		 1144 break;
1145 }
9dac77fa
AK		 1146 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1147 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1148 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1149 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1150 } else {
1151 /* 32/64-bit ModR/M decode. */
9dac77fa 1152 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1153 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1154 index_reg |= (sib >> 3) & 7;
1155 base_reg |= sib & 7;
1156 scale = sib >> 6;
1157
9dac77fa 1158 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1159 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1160 else {
dd856efa 1161 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1162 adjust_modrm_seg(ctxt, base_reg);
1163 }
dc71d0f1 1164 if (index_reg != 4)
dd856efa 1165 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1166 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1167 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1168 ctxt->rip_relative = 1;
a6e3407b
AK		 1169 } else {
1170 base_reg = ctxt->modrm_rm;
dd856efa 1171 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1172 adjust_modrm_seg(ctxt, base_reg);
1173 }
9dac77fa 1174 switch (ctxt->modrm_mod) {
1c73ef66 1175 case 0:
9dac77fa 1176 if (ctxt->modrm_rm == 5)
e85a1085 1177 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1178 break;
1179 case 1:
e85a1085 1180 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1181 break;
1182 case 2:
e85a1085 1183 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1184 break;
1185 }
1186 }
90de84f5 1187 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1188 if (ctxt->ad_bytes != 8)
1189 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1190
1c73ef66
AK		 1191done:
1192 return rc;
1193}
1194
1195static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1196 struct operand *op)
1c73ef66 1197{
3e2815e9 1198 int rc = X86EMUL_CONTINUE;
1c73ef66 1199
2dbd0dd7 1200 op->type = OP_MEM;
9dac77fa 1201 switch (ctxt->ad_bytes) {
1c73ef66 1202 case 2:
e85a1085 1203 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1204 break;
1205 case 4:
e85a1085 1206 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1207 break;
1208 case 8:
e85a1085 1209 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1210 break;
1211 }
1212done:
1213 return rc;
1214}
1215
9dac77fa 1216static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1217{
7129eeca 1218 long sv = 0, mask;
35c843c4 1219
9dac77fa 1220 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1221 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1222
9dac77fa
AK		 1223 if (ctxt->src.bytes == 2)
1224 sv = (s16)ctxt->src.val & (s16)mask;
1225 else if (ctxt->src.bytes == 4)
1226 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1227 else
1228 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1229
9dac77fa 1230 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1231 }
ba7ff2b7
WY		 1232
1233 /* only subword offset */
9dac77fa 1234 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1235}
1236
dde7e6d1 1237static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1238 unsigned long addr, void *dest, unsigned size)
6aa8b732 1239{
dde7e6d1 1240 int rc;
9dac77fa 1241 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1242
f23b070e
XG		 1243 if (mc->pos < mc->end)
1244 goto read_cached;
6aa8b732 1245
f23b070e
XG		 1246 WARN_ON((mc->end + size) >= sizeof(mc->data));
1247
1248 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1249 &ctxt->exception);
1250 if (rc != X86EMUL_CONTINUE)
1251 return rc;
1252
1253 mc->end += size;
1254
1255read_cached:
1256 memcpy(dest, mc->data + mc->pos, size);
1257 mc->pos += size;
dde7e6d1
AK		 1258 return X86EMUL_CONTINUE;
1259}
6aa8b732 1260
3ca3ac4d
AK		 1261static int segmented_read(struct x86_emulate_ctxt *ctxt,
1262 struct segmented_address addr,
1263 void *data,
1264 unsigned size)
1265{
9fa088f4
AK		 1266 int rc;
1267 ulong linear;
1268
83b8795a 1269 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
7b105ca2 1272 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1273}
1274
1275static int segmented_write(struct x86_emulate_ctxt *ctxt,
1276 struct segmented_address addr,
1277 const void *data,
1278 unsigned size)
1279{
9fa088f4
AK		 1280 int rc;
1281 ulong linear;
1282
83b8795a 1283 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
0f65dd70
AK		 1286 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1287 &ctxt->exception);
3ca3ac4d
AK		 1288}
1289
1290static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1291 struct segmented_address addr,
1292 const void *orig_data, const void *data,
1293 unsigned size)
1294{
9fa088f4
AK		 1295 int rc;
1296 ulong linear;
1297
83b8795a 1298 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
0f65dd70
AK		 1301 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1302 size, &ctxt->exception);
3ca3ac4d
AK		 1303}
1304
dde7e6d1 1305static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1306 unsigned int size, unsigned short port,
1307 void *dest)
1308{
9dac77fa 1309 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1310
dde7e6d1 1311 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1312 unsigned int in_page, n;
9dac77fa 1313 unsigned int count = ctxt->rep_prefix ?
dd856efa 1314 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1315 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1316 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1317 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1318 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1319 count);
1320 if (n == 0)
1321 n = 1;
1322 rc->pos = rc->end = 0;
7b105ca2 1323 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1324 return 0;
1325 rc->end = n * size;
6aa8b732
AK		 1326 }
1327
e6e39f04
NA		 1328 if (ctxt->rep_prefix && (ctxt->d & String) &&
1329 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1330 ctxt->dst.data = rc->data + rc->pos;
1331 ctxt->dst.type = OP_MEM_STR;
1332 ctxt->dst.count = (rc->end - rc->pos) / size;
1333 rc->pos = rc->end;
1334 } else {
1335 memcpy(dest, rc->data + rc->pos, size);
1336 rc->pos += size;
1337 }
dde7e6d1
AK		 1338 return 1;
1339}
6aa8b732 1340
7f3d35fd
KW		 1341static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1342 u16 index, struct desc_struct *desc)
1343{
1344 struct desc_ptr dt;
1345 ulong addr;
1346
1347 ctxt->ops->get_idt(ctxt, &dt);
1348
1349 if (dt.size < index * 8 + 7)
1350 return emulate_gp(ctxt, index << 3 | 0x2);
1351
1352 addr = dt.address + index * 8;
1353 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1354 &ctxt->exception);
1355}
1356
dde7e6d1 1357static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1358 u16 selector, struct desc_ptr *dt)
1359{
0225fb50 1360 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1361 u32 base3 = 0;
7b105ca2 1362
dde7e6d1
AK		 1363 if (selector & 1 << 2) {
1364 struct desc_struct desc;
1aa36616
AK		 1365 u16 sel;
1366
dde7e6d1 1367 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1368 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1369 VCPU_SREG_LDTR))
dde7e6d1 1370 return;
e09d082c 1371
dde7e6d1 1372 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1373 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1374 } else
4bff1e86 1375 ops->get_gdt(ctxt, dt);
dde7e6d1 1376}
120df890 1377
dde7e6d1
AK		 1378/* allowed just for 8 bytes segments */
1379static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1380 u16 selector, struct desc_struct *desc,
1381 ulong *desc_addr_p)
dde7e6d1
AK		 1382{
1383 struct desc_ptr dt;
1384 u16 index = selector >> 3;
dde7e6d1 1385 ulong addr;
120df890 1386
7b105ca2 1387 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1388
35d3d4a1
AK		 1389 if (dt.size < index * 8 + 7)
1390 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1391
e919464b 1392 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1393 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1394 &ctxt->exception);
dde7e6d1 1395}
ef65c889 1396
dde7e6d1
AK		 1397/* allowed just for 8 bytes segments */
1398static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1399 u16 selector, struct desc_struct *desc)
1400{
1401 struct desc_ptr dt;
1402 u16 index = selector >> 3;
dde7e6d1 1403 ulong addr;
6aa8b732 1404
7b105ca2 1405 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1406
35d3d4a1
AK		 1407 if (dt.size < index * 8 + 7)
1408 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1409
dde7e6d1 1410 addr = dt.address + index * 8;
7b105ca2
TY		 1411 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1412 &ctxt->exception);
dde7e6d1 1413}
c7e75a3d 1414
5601d05b 1415/* Does not support long mode */
2356aaeb 1416static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1417 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1418{
869be99c 1419 struct desc_struct seg_desc, old_desc;
2356aaeb 1420 u8 dpl, rpl;
dde7e6d1
AK		 1421 unsigned err_vec = GP_VECTOR;
1422 u32 err_code = 0;
1423 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1424 ulong desc_addr;
dde7e6d1 1425 int ret;
03ebebeb 1426 u16 dummy;
e37a75a1 1427 u32 base3 = 0;
69f55cb1 1428
dde7e6d1 1429 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1430
f8da94e9
KW		 1431 if (ctxt->mode == X86EMUL_MODE_REAL) {
1432 /* set real mode segment descriptor (keep limit etc. for
1433 * unreal mode) */
03ebebeb 1434 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1435 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1436 goto load;
f8da94e9
KW		 1437 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1438 /* VM86 needs a clean new segment descriptor */
1439 set_desc_base(&seg_desc, selector << 4);
1440 set_desc_limit(&seg_desc, 0xffff);
1441 seg_desc.type = 3;
1442 seg_desc.p = 1;
1443 seg_desc.s = 1;
1444 seg_desc.dpl = 3;
1445 goto load;
dde7e6d1
AK		 1446 }
1447
79d5b4c3 1448 rpl = selector & 3;
79d5b4c3
AK		 1449
1450 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1451 if ((seg == VCPU_SREG_CS
1452 || (seg == VCPU_SREG_SS
1453 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1454 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1455 && null_selector)
1456 goto exception;
1457
1458 /* TR should be in GDT only */
1459 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1460 goto exception;
1461
1462 if (null_selector) /* for NULL selector skip all following checks */
1463 goto load;
1464
e919464b 1465 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1466 if (ret != X86EMUL_CONTINUE)
1467 return ret;
1468
1469 err_code = selector & 0xfffc;
1470 err_vec = GP_VECTOR;
1471
fc058680 1472 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1473 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1474 goto exception;
1475
1476 if (!seg_desc.p) {
1477 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1478 goto exception;
1479 }
1480
dde7e6d1 1481 dpl = seg_desc.dpl;
dde7e6d1
AK		 1482
1483 switch (seg) {
1484 case VCPU_SREG_SS:
1485 /*
1486 * segment is not a writable data segment or segment
1487 * selector's RPL != CPL or segment selector's RPL != CPL
1488 */
1489 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1490 goto exception;
6aa8b732 1491 break;
dde7e6d1 1492 case VCPU_SREG_CS:
5045b468
PB		 1493 if (in_task_switch && rpl != dpl)
1494 goto exception;
1495
dde7e6d1
AK		 1496 if (!(seg_desc.type & 8))
1497 goto exception;
1498
1499 if (seg_desc.type & 4) {
1500 /* conforming */
1501 if (dpl > cpl)
1502 goto exception;
1503 } else {
1504 /* nonconforming */
1505 if (rpl > cpl || dpl != cpl)
1506 goto exception;
1507 }
1508 /* CS(RPL) <- CPL */
1509 selector = (selector & 0xfffc) | cpl;
6aa8b732 1510 break;
dde7e6d1
AK		 1511 case VCPU_SREG_TR:
1512 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1513 goto exception;
869be99c
AK		 1514 old_desc = seg_desc;
1515 seg_desc.type |= 2; /* busy */
1516 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1517 sizeof(seg_desc), &ctxt->exception);
1518 if (ret != X86EMUL_CONTINUE)
1519 return ret;
dde7e6d1
AK		 1520 break;
1521 case VCPU_SREG_LDTR:
1522 if (seg_desc.s || seg_desc.type != 2)
1523 goto exception;
1524 break;
1525 default: /* DS, ES, FS, or GS */
4e62417b 1526 /*
dde7e6d1
AK		 1527 * segment is not a data or readable code segment or
1528 * ((segment is a data or nonconforming code segment)
1529 * and (both RPL and CPL > DPL))
4e62417b 1530 */
dde7e6d1
AK		 1531 if ((seg_desc.type & 0xa) == 0x8 ||
1532 (((seg_desc.type & 0xc) != 0xc) &&
1533 (rpl > dpl && cpl > dpl)))
1534 goto exception;
6aa8b732 1535 break;
dde7e6d1
AK		 1536 }
1537
1538 if (seg_desc.s) {
1539 /* mark segment as accessed */
1540 seg_desc.type |= 1;
7b105ca2 1541 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1542 if (ret != X86EMUL_CONTINUE)
1543 return ret;
e37a75a1
NA		 1544 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1545 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1546 sizeof(base3), &ctxt->exception);
1547 if (ret != X86EMUL_CONTINUE)
1548 return ret;
dde7e6d1
AK		 1549 }
1550load:
e37a75a1 1551 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1552 return X86EMUL_CONTINUE;
1553exception:
1554 emulate_exception(ctxt, err_vec, err_code, true);
1555 return X86EMUL_PROPAGATE_FAULT;
1556}
1557
2356aaeb
PB		 1558static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1559 u16 selector, int seg)
1560{
1561 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1562 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1563}
1564
31be40b3
WY		 1565static void write_register_operand(struct operand *op)
1566{
1567 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1568 switch (op->bytes) {
1569 case 1:
1570 *(u8 *)op->addr.reg = (u8)op->val;
1571 break;
1572 case 2:
1573 *(u16 *)op->addr.reg = (u16)op->val;
1574 break;
1575 case 4:
1576 *op->addr.reg = (u32)op->val;
1577 break; /* 64b: zero-extend */
1578 case 8:
1579 *op->addr.reg = op->val;
1580 break;
1581 }
1582}
1583
fb32b1ed 1584static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1585{
fb32b1ed 1586 switch (op->type) {
dde7e6d1 1587 case OP_REG:
fb32b1ed 1588 write_register_operand(op);
6aa8b732 1589 break;
dde7e6d1 1590 case OP_MEM:
9dac77fa 1591 if (ctxt->lock_prefix)
f5f87dfb
PB		 1592 return segmented_cmpxchg(ctxt,
1593 op->addr.mem,
1594 &op->orig_val,
1595 &op->val,
1596 op->bytes);
1597 else
1598 return segmented_write(ctxt,
fb32b1ed 1599 op->addr.mem,
fb32b1ed
AK		 1600 &op->val,
1601 op->bytes);
a682e354 1602 break;
b3356bf0 1603 case OP_MEM_STR:
f5f87dfb
PB		 1604 return segmented_write(ctxt,
1605 op->addr.mem,
1606 op->data,
1607 op->bytes * op->count);
b3356bf0 1608 break;
1253791d 1609 case OP_XMM:
fb32b1ed 1610 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1611 break;
cbe2c9d3 1612 case OP_MM:
fb32b1ed 1613 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1614 break;
dde7e6d1
AK		 1615 case OP_NONE:
1616 /* no writeback */
414e6277 1617 break;
dde7e6d1 1618 default:
414e6277 1619 break;
6aa8b732 1620 }
dde7e6d1
AK		 1621 return X86EMUL_CONTINUE;
1622}
6aa8b732 1623
51ddff50 1624static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1625{
4179bb02 1626 struct segmented_address addr;
0dc8d10f 1627
5ad105e5 1628 rsp_increment(ctxt, -bytes);
dd856efa 1629 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1630 addr.seg = VCPU_SREG_SS;
1631
51ddff50
AK		 1632 return segmented_write(ctxt, addr, data, bytes);
1633}
1634
1635static int em_push(struct x86_emulate_ctxt *ctxt)
1636{
4179bb02 1637 /* Disable writeback. */
9dac77fa 1638 ctxt->dst.type = OP_NONE;
51ddff50 1639 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1640}
69f55cb1 1641
dde7e6d1 1642static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1643 void *dest, int len)
1644{
dde7e6d1 1645 int rc;
90de84f5 1646 struct segmented_address addr;
8b4caf66 1647
dd856efa 1648 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1649 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1650 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1651 if (rc != X86EMUL_CONTINUE)
1652 return rc;
1653
5ad105e5 1654 rsp_increment(ctxt, len);
dde7e6d1 1655 return rc;
8b4caf66
LV		 1656}
1657
c54fe504
TY		 1658static int em_pop(struct x86_emulate_ctxt *ctxt)
1659{
9dac77fa 1660 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1661}
1662
dde7e6d1 1663static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1664 void *dest, int len)
9de41573
GN		 1665{
1666 int rc;
dde7e6d1
AK		 1667 unsigned long val, change_mask;
1668 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1669 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1670
3b9be3bf 1671 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1672 if (rc != X86EMUL_CONTINUE)
1673 return rc;
9de41573 1674
dde7e6d1
AK		 1675 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1676 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1677
dde7e6d1
AK		 1678 switch(ctxt->mode) {
1679 case X86EMUL_MODE_PROT64:
1680 case X86EMUL_MODE_PROT32:
1681 case X86EMUL_MODE_PROT16:
1682 if (cpl == 0)
1683 change_mask |= EFLG_IOPL;
1684 if (cpl <= iopl)
1685 change_mask |= EFLG_IF;
1686 break;
1687 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1688 if (iopl < 3)
1689 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1690 change_mask |= EFLG_IF;
1691 break;
1692 default: /* real mode */
1693 change_mask |= (EFLG_IOPL | EFLG_IF);
1694 break;
9de41573 1695 }
dde7e6d1
AK		 1696
1697 *(unsigned long *)dest =
1698 (ctxt->eflags & ~change_mask) | (val & change_mask);
1699
1700 return rc;
9de41573
GN		 1701}
1702
62aaa2f0
TY		 1703static int em_popf(struct x86_emulate_ctxt *ctxt)
1704{
9dac77fa
AK		 1705 ctxt->dst.type = OP_REG;
1706 ctxt->dst.addr.reg = &ctxt->eflags;
1707 ctxt->dst.bytes = ctxt->op_bytes;
1708 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1709}
1710
612e89f0
AK		 1711static int em_enter(struct x86_emulate_ctxt *ctxt)
1712{
1713 int rc;
1714 unsigned frame_size = ctxt->src.val;
1715 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1716 ulong rbp;
612e89f0
AK		 1717
1718 if (nesting_level)
1719 return X86EMUL_UNHANDLEABLE;
1720
dd856efa
AK		 1721 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1722 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1723 if (rc != X86EMUL_CONTINUE)
1724 return rc;
dd856efa 1725 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1726 stack_mask(ctxt));
dd856efa
AK		 1727 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1728 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1729 stack_mask(ctxt));
1730 return X86EMUL_CONTINUE;
1731}
1732
f47cfa31
AK		 1733static int em_leave(struct x86_emulate_ctxt *ctxt)
1734{
dd856efa 1735 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1736 stack_mask(ctxt));
dd856efa 1737 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1738}
1739
1cd196ea 1740static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1741{
1cd196ea
AK		 1742 int seg = ctxt->src2.val;
1743
9dac77fa 1744 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1745
4487b3b4 1746 return em_push(ctxt);
7b262e90
GN		 1747}
1748
1cd196ea 1749static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1750{
1cd196ea 1751 int seg = ctxt->src2.val;
dde7e6d1
AK		 1752 unsigned long selector;
1753 int rc;
38ba30ba 1754
9dac77fa 1755 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1756 if (rc != X86EMUL_CONTINUE)
1757 return rc;
1758
a5457e7b
PB		 1759 if (ctxt->modrm_reg == VCPU_SREG_SS)
1760 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1761
7b105ca2 1762 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1763 return rc;
38ba30ba
GN		 1764}
1765
b96a7fad 1766static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1767{
dd856efa 1768 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1769 int rc = X86EMUL_CONTINUE;
1770 int reg = VCPU_REGS_RAX;
38ba30ba 1771
dde7e6d1
AK		 1772 while (reg <= VCPU_REGS_RDI) {
1773 (reg == VCPU_REGS_RSP) ?
dd856efa 1774 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1775
4487b3b4 1776 rc = em_push(ctxt);
dde7e6d1
AK		 1777 if (rc != X86EMUL_CONTINUE)
1778 return rc;
38ba30ba 1779
dde7e6d1 1780 ++reg;
38ba30ba 1781 }
38ba30ba 1782
dde7e6d1 1783 return rc;
38ba30ba
GN		 1784}
1785
62aaa2f0
TY		 1786static int em_pushf(struct x86_emulate_ctxt *ctxt)
1787{
9dac77fa 1788 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1789 return em_push(ctxt);
1790}
1791
b96a7fad 1792static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1793{
dde7e6d1
AK		 1794 int rc = X86EMUL_CONTINUE;
1795 int reg = VCPU_REGS_RDI;
38ba30ba 1796
dde7e6d1
AK		 1797 while (reg >= VCPU_REGS_RAX) {
1798 if (reg == VCPU_REGS_RSP) {
5ad105e5 1799 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1800 --reg;
1801 }
38ba30ba 1802
dd856efa 1803 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1804 if (rc != X86EMUL_CONTINUE)
1805 break;
1806 --reg;
38ba30ba 1807 }
dde7e6d1 1808 return rc;
38ba30ba
GN		 1809}
1810
dd856efa 1811static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1812{
0225fb50 1813 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1814 int rc;
6e154e56
MG		 1815 struct desc_ptr dt;
1816 gva_t cs_addr;
1817 gva_t eip_addr;
1818 u16 cs, eip;
6e154e56
MG		 1819
1820 /* TODO: Add limit checks */
9dac77fa 1821 ctxt->src.val = ctxt->eflags;
4487b3b4 1822 rc = em_push(ctxt);
5c56e1cf
AK		 1823 if (rc != X86EMUL_CONTINUE)
1824 return rc;
6e154e56
MG		 1825
1826 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1827
9dac77fa 1828 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1829 rc = em_push(ctxt);
5c56e1cf
AK		 1830 if (rc != X86EMUL_CONTINUE)
1831 return rc;
6e154e56 1832
9dac77fa 1833 ctxt->src.val = ctxt->_eip;
4487b3b4 1834 rc = em_push(ctxt);
5c56e1cf
AK		 1835 if (rc != X86EMUL_CONTINUE)
1836 return rc;
1837
4bff1e86 1838 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1839
1840 eip_addr = dt.address + (irq << 2);
1841 cs_addr = dt.address + (irq << 2) + 2;
1842
0f65dd70 1843 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1844 if (rc != X86EMUL_CONTINUE)
1845 return rc;
1846
0f65dd70 1847 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1848 if (rc != X86EMUL_CONTINUE)
1849 return rc;
1850
7b105ca2 1851 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1852 if (rc != X86EMUL_CONTINUE)
1853 return rc;
1854
9dac77fa 1855 ctxt->_eip = eip;
6e154e56
MG		 1856
1857 return rc;
1858}
1859
dd856efa
AK		 1860int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1861{
1862 int rc;
1863
1864 invalidate_registers(ctxt);
1865 rc = __emulate_int_real(ctxt, irq);
1866 if (rc == X86EMUL_CONTINUE)
1867 writeback_registers(ctxt);
1868 return rc;
1869}
1870
7b105ca2 1871static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1872{
1873 switch(ctxt->mode) {
1874 case X86EMUL_MODE_REAL:
dd856efa 1875 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1876 case X86EMUL_MODE_VM86:
1877 case X86EMUL_MODE_PROT16:
1878 case X86EMUL_MODE_PROT32:
1879 case X86EMUL_MODE_PROT64:
1880 default:
1881 /* Protected mode interrupts unimplemented yet */
1882 return X86EMUL_UNHANDLEABLE;
1883 }
1884}
1885
7b105ca2 1886static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1887{
dde7e6d1
AK		 1888 int rc = X86EMUL_CONTINUE;
1889 unsigned long temp_eip = 0;
1890 unsigned long temp_eflags = 0;
1891 unsigned long cs = 0;
1892 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1893 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1894 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1895 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1896
dde7e6d1 1897 /* TODO: Add stack limit check */
38ba30ba 1898
9dac77fa 1899 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1900
dde7e6d1
AK		 1901 if (rc != X86EMUL_CONTINUE)
1902 return rc;
38ba30ba 1903
35d3d4a1
AK		 1904 if (temp_eip & ~0xffff)
1905 return emulate_gp(ctxt, 0);
38ba30ba 1906
9dac77fa 1907 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1908
dde7e6d1
AK		 1909 if (rc != X86EMUL_CONTINUE)
1910 return rc;
38ba30ba 1911
9dac77fa 1912 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1913
dde7e6d1
AK		 1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
38ba30ba 1916
7b105ca2 1917 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1918
dde7e6d1
AK		 1919 if (rc != X86EMUL_CONTINUE)
1920 return rc;
38ba30ba 1921
9dac77fa 1922 ctxt->_eip = temp_eip;
38ba30ba 1923
38ba30ba 1924
9dac77fa 1925 if (ctxt->op_bytes == 4)
dde7e6d1 1926 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1927 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1928 ctxt->eflags &= ~0xffff;
1929 ctxt->eflags |= temp_eflags;
38ba30ba 1930 }
dde7e6d1
AK		 1931
1932 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1933 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1934
1935 return rc;
38ba30ba
GN		 1936}
1937
e01991e7 1938static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1939{
dde7e6d1
AK		 1940 switch(ctxt->mode) {
1941 case X86EMUL_MODE_REAL:
7b105ca2 1942 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1943 case X86EMUL_MODE_VM86:
1944 case X86EMUL_MODE_PROT16:
1945 case X86EMUL_MODE_PROT32:
1946 case X86EMUL_MODE_PROT64:
c37eda13 1947 default:
dde7e6d1
AK		 1948 /* iret from protected mode unimplemented yet */
1949 return X86EMUL_UNHANDLEABLE;
c37eda13 1950 }
c37eda13
WY		 1951}
1952
d2f62766
TY		 1953static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1954{
d2f62766
TY		 1955 int rc;
1956 unsigned short sel;
1957
9dac77fa 1958 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1959
7b105ca2 1960 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1961 if (rc != X86EMUL_CONTINUE)
1962 return rc;
1963
9dac77fa
AK		 1964 ctxt->_eip = 0;
1965 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1966 return X86EMUL_CONTINUE;
1967}
1968
51187683 1969static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1970{
4179bb02 1971 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1972
9dac77fa 1973 switch (ctxt->modrm_reg) {
d19292e4
MG		 1974 case 2: /* call near abs */ {
1975 long int old_eip;
9dac77fa
AK		 1976 old_eip = ctxt->_eip;
1977 ctxt->_eip = ctxt->src.val;
1978 ctxt->src.val = old_eip;
4487b3b4 1979 rc = em_push(ctxt);
d19292e4
MG		 1980 break;
1981 }
8cdbd2c9 1982 case 4: /* jmp abs */
9dac77fa 1983 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1984 break;
d2f62766
TY		 1985 case 5: /* jmp far */
1986 rc = em_jmp_far(ctxt);
1987 break;
8cdbd2c9 1988 case 6: /* push */
4487b3b4 1989 rc = em_push(ctxt);
8cdbd2c9 1990 break;
8cdbd2c9 1991 }
4179bb02 1992 return rc;
8cdbd2c9
LV		 1993}
1994
e0dac408 1995static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1996{
9dac77fa 1997 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1998
aaa05f24
NA		 1999 if (ctxt->dst.bytes == 16)
2000 return X86EMUL_UNHANDLEABLE;
2001
dd856efa
AK		 2002 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2003 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2004 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2005 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2006 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2007 } else {
dd856efa
AK		 2008 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2009 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2010
05f086f8 2011 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2012 }
1b30eaa8 2013 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2014}
2015
ebda02c2
TY		 2016static int em_ret(struct x86_emulate_ctxt *ctxt)
2017{
9dac77fa
AK		 2018 ctxt->dst.type = OP_REG;
2019 ctxt->dst.addr.reg = &ctxt->_eip;
2020 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2021 return em_pop(ctxt);
2022}
2023
e01991e7 2024static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2025{
a77ab5ea
AK		 2026 int rc;
2027 unsigned long cs;
9e8919ae 2028 int cpl = ctxt->ops->cpl(ctxt);
a77ab5ea 2029
9dac77fa 2030 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2031 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2032 return rc;
9dac77fa
AK		 2033 if (ctxt->op_bytes == 4)
2034 ctxt->_eip = (u32)ctxt->_eip;
2035 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2036 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2037 return rc;
9e8919ae
NA		 2038 /* Outer-privilege level return is not implemented */
2039 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2040 return X86EMUL_UNHANDLEABLE;
7b105ca2 2041 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2042 return rc;
2043}
2044
3261107e
BR		 2045static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2046{
2047 int rc;
2048
2049 rc = em_ret_far(ctxt);
2050 if (rc != X86EMUL_CONTINUE)
2051 return rc;
2052 rsp_increment(ctxt, ctxt->src.val);
2053 return X86EMUL_CONTINUE;
2054}
2055
e940b5c2
TY		 2056static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2057{
2058 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2059 ctxt->dst.orig_val = ctxt->dst.val;
2060 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2061 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2062 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2063 fastop(ctxt, em_cmp);
e940b5c2
TY		 2064
2065 if (ctxt->eflags & EFLG_ZF) {
2066 /* Success: write back to memory. */
2067 ctxt->dst.val = ctxt->src.orig_val;
2068 } else {
2069 /* Failure: write the value we saw to EAX. */
2070 ctxt->dst.type = OP_REG;
dd856efa 2071 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2072 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2073 }
2074 return X86EMUL_CONTINUE;
2075}
2076
d4b4325f 2077static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2078{
d4b4325f 2079 int seg = ctxt->src2.val;
09b5f4d3
WY		 2080 unsigned short sel;
2081 int rc;
2082
9dac77fa 2083 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2084
7b105ca2 2085 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2086 if (rc != X86EMUL_CONTINUE)
2087 return rc;
2088
9dac77fa 2089 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2090 return rc;
2091}
2092
7b105ca2 2093static void
e66bb2cc 2094setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2095 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2096{
e66bb2cc 2097 cs->l = 0; /* will be adjusted later */
79168fd1 2098 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2099 cs->g = 1; /* 4kb granularity */
79168fd1 2100 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2101 cs->type = 0x0b; /* Read, Execute, Accessed */
2102 cs->s = 1;
2103 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2104 cs->p = 1;
2105 cs->d = 1;
99245b50 2106 cs->avl = 0;
e66bb2cc 2107
79168fd1
GN		 2108 set_desc_base(ss, 0); /* flat segment */
2109 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2110 ss->g = 1; /* 4kb granularity */
2111 ss->s = 1;
2112 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2113 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2114 ss->dpl = 0;
79168fd1 2115 ss->p = 1;
99245b50
GN		 2116 ss->l = 0;
2117 ss->avl = 0;
e66bb2cc
AP		 2118}
2119
1a18a69b
AK		 2120static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2121{
2122 u32 eax, ebx, ecx, edx;
2123
2124 eax = ecx = 0;
0017f93a
AK		 2125 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2126 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2127 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2128 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2129}
2130
c2226fc9
SB		 2131static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2132{
0225fb50 2133 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2134 u32 eax, ebx, ecx, edx;
2135
2136 /*
2137 * syscall should always be enabled in longmode - so only become
2138 * vendor specific (cpuid) if other modes are active...
2139 */
2140 if (ctxt->mode == X86EMUL_MODE_PROT64)
2141 return true;
2142
2143 eax = 0x00000000;
2144 ecx = 0x00000000;
0017f93a
AK		 2145 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2146 /*
2147 * Intel ("GenuineIntel")
2148 * remark: Intel CPUs only support "syscall" in 64bit
2149 * longmode. Also an 64bit guest with a
2150 * 32bit compat-app running will #UD !! While this
2151 * behaviour can be fixed (by emulating) into AMD
2152 * response - CPUs of AMD can't behave like Intel.
2153 */
2154 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2155 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2156 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2157 return false;
2158
2159 /* AMD ("AuthenticAMD") */
2160 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2161 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2162 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2163 return true;
2164
2165 /* AMD ("AMDisbetter!") */
2166 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2167 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2168 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2169 return true;
c2226fc9
SB		 2170
2171 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2172 return false;
2173}
2174
e01991e7 2175static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2176{
0225fb50 2177 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2178 struct desc_struct cs, ss;
e66bb2cc 2179 u64 msr_data;
79168fd1 2180 u16 cs_sel, ss_sel;
c2ad2bb3 2181 u64 efer = 0;
e66bb2cc
AP		 2182
2183 /* syscall is not available in real mode */
2e901c4c 2184 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2185 ctxt->mode == X86EMUL_MODE_VM86)
2186 return emulate_ud(ctxt);
e66bb2cc 2187
c2226fc9
SB		 2188 if (!(em_syscall_is_enabled(ctxt)))
2189 return emulate_ud(ctxt);
2190
c2ad2bb3 2191 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2192 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2193
c2226fc9
SB		 2194 if (!(efer & EFER_SCE))
2195 return emulate_ud(ctxt);
2196
717746e3 2197 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2198 msr_data >>= 32;
79168fd1
GN		 2199 cs_sel = (u16)(msr_data & 0xfffc);
2200 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2201
c2ad2bb3 2202 if (efer & EFER_LMA) {
79168fd1 2203 cs.d = 0;
e66bb2cc
AP		 2204 cs.l = 1;
2205 }
1aa36616
AK		 2206 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2207 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2208
dd856efa 2209 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2210 if (efer & EFER_LMA) {
e66bb2cc 2211#ifdef CONFIG_X86_64
dd856efa 2212 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2213
717746e3 2214 ops->get_msr(ctxt,
3fb1b5db
GN		 2215 ctxt->mode == X86EMUL_MODE_PROT64 ?
2216 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2217 ctxt->_eip = msr_data;
e66bb2cc 2218
717746e3 2219 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2220 ctxt->eflags &= ~(msr_data | EFLG_RF);
2221#endif
2222 } else {
2223 /* legacy mode */
717746e3 2224 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2225 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2226
2227 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2228 }
2229
e54cfa97 2230 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2231}
2232
e01991e7 2233static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2234{
0225fb50 2235 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2236 struct desc_struct cs, ss;
8c604352 2237 u64 msr_data;
79168fd1 2238 u16 cs_sel, ss_sel;
c2ad2bb3 2239 u64 efer = 0;
8c604352 2240
7b105ca2 2241 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2242 /* inject #GP if in real mode */
35d3d4a1
AK		 2243 if (ctxt->mode == X86EMUL_MODE_REAL)
2244 return emulate_gp(ctxt, 0);
8c604352 2245
1a18a69b
AK		 2246 /*
2247 * Not recognized on AMD in compat mode (but is recognized in legacy
2248 * mode).
2249 */
2250 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2251 && !vendor_intel(ctxt))
2252 return emulate_ud(ctxt);
2253
8c604352
AP		 2254 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2255 * Therefore, we inject an #UD.
2256 */
35d3d4a1
AK		 2257 if (ctxt->mode == X86EMUL_MODE_PROT64)
2258 return emulate_ud(ctxt);
8c604352 2259
7b105ca2 2260 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2261
717746e3 2262 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2263 switch (ctxt->mode) {
2264 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2265 if ((msr_data & 0xfffc) == 0x0)
2266 return emulate_gp(ctxt, 0);
8c604352
AP		 2267 break;
2268 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2269 if (msr_data == 0x0)
2270 return emulate_gp(ctxt, 0);
8c604352 2271 break;
9d1b39a9
GN		 2272 default:
2273 break;
8c604352
AP		 2274 }
2275
2276 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2277 cs_sel = (u16)msr_data;
2278 cs_sel &= ~SELECTOR_RPL_MASK;
2279 ss_sel = cs_sel + 8;
2280 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2281 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2282 cs.d = 0;
8c604352
AP		 2283 cs.l = 1;
2284 }
2285
1aa36616
AK		 2286 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2287 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2288
717746e3 2289 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2290 ctxt->_eip = msr_data;
8c604352 2291
717746e3 2292 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2293 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2294
e54cfa97 2295 return X86EMUL_CONTINUE;
8c604352
AP		 2296}
2297
e01991e7 2298static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2299{
0225fb50 2300 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2301 struct desc_struct cs, ss;
4668f050
AP		 2302 u64 msr_data;
2303 int usermode;
1249b96e 2304 u16 cs_sel = 0, ss_sel = 0;
4668f050 2305
a0044755
GN		 2306 /* inject #GP if in real mode or Virtual 8086 mode */
2307 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2308 ctxt->mode == X86EMUL_MODE_VM86)
2309 return emulate_gp(ctxt, 0);
4668f050 2310
7b105ca2 2311 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2312
9dac77fa 2313 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2314 usermode = X86EMUL_MODE_PROT64;
2315 else
2316 usermode = X86EMUL_MODE_PROT32;
2317
2318 cs.dpl = 3;
2319 ss.dpl = 3;
717746e3 2320 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2321 switch (usermode) {
2322 case X86EMUL_MODE_PROT32:
79168fd1 2323 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2324 if ((msr_data & 0xfffc) == 0x0)
2325 return emulate_gp(ctxt, 0);
79168fd1 2326 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2327 break;
2328 case X86EMUL_MODE_PROT64:
79168fd1 2329 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2330 if (msr_data == 0x0)
2331 return emulate_gp(ctxt, 0);
79168fd1
GN		 2332 ss_sel = cs_sel + 8;
2333 cs.d = 0;
4668f050
AP		 2334 cs.l = 1;
2335 break;
2336 }
79168fd1
GN		 2337 cs_sel |= SELECTOR_RPL_MASK;
2338 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2339
1aa36616
AK		 2340 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2341 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2342
dd856efa
AK		 2343 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2344 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2345
e54cfa97 2346 return X86EMUL_CONTINUE;
4668f050
AP		 2347}
2348
7b105ca2 2349static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2350{
2351 int iopl;
2352 if (ctxt->mode == X86EMUL_MODE_REAL)
2353 return false;
2354 if (ctxt->mode == X86EMUL_MODE_VM86)
2355 return true;
2356 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2357 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2358}
2359
2360static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2361 u16 port, u16 len)
2362{
0225fb50 2363 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2364 struct desc_struct tr_seg;
5601d05b 2365 u32 base3;
f850e2e6 2366 int r;
1aa36616 2367 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2368 unsigned mask = (1 << len) - 1;
5601d05b 2369 unsigned long base;
f850e2e6 2370
1aa36616 2371 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2372 if (!tr_seg.p)
f850e2e6 2373 return false;
79168fd1 2374 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2375 return false;
5601d05b
GN		 2376 base = get_desc_base(&tr_seg);
2377#ifdef CONFIG_X86_64
2378 base |= ((u64)base3) << 32;
2379#endif
0f65dd70 2380 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2381 if (r != X86EMUL_CONTINUE)
2382 return false;
79168fd1 2383 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2384 return false;
0f65dd70 2385 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2386 if (r != X86EMUL_CONTINUE)
2387 return false;
2388 if ((perm >> bit_idx) & mask)
2389 return false;
2390 return true;
2391}
2392
2393static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2394 u16 port, u16 len)
2395{
4fc40f07
GN		 2396 if (ctxt->perm_ok)
2397 return true;
2398
7b105ca2
TY		 2399 if (emulator_bad_iopl(ctxt))
2400 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2401 return false;
4fc40f07
GN		 2402
2403 ctxt->perm_ok = true;
2404
f850e2e6
GN		 2405 return true;
2406}
2407
38ba30ba 2408static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2409 struct tss_segment_16 *tss)
2410{
9dac77fa 2411 tss->ip = ctxt->_eip;
38ba30ba 2412 tss->flag = ctxt->eflags;
dd856efa
AK		 2413 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2414 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2415 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2416 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2417 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2418 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2419 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2420 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2421
1aa36616
AK		 2422 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2423 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2424 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2425 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2426 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2427}
2428
2429static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2430 struct tss_segment_16 *tss)
2431{
38ba30ba 2432 int ret;
2356aaeb 2433 u8 cpl;
38ba30ba 2434
9dac77fa 2435 ctxt->_eip = tss->ip;
38ba30ba 2436 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2437 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2438 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2439 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2440 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2441 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2442 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2443 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2444 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2445
2446 /*
2447 * SDM says that segment selectors are loaded before segment
2448 * descriptors
2449 */
1aa36616
AK		 2450 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2451 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2452 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2453 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2454 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2455
2356aaeb
PB		 2456 cpl = tss->cs & 3;
2457
38ba30ba 2458 /*
fc058680 2459 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2460 * it is handled in a context of new task
2461 */
5045b468 2462 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2463 if (ret != X86EMUL_CONTINUE)
2464 return ret;
5045b468 2465 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2466 if (ret != X86EMUL_CONTINUE)
2467 return ret;
5045b468 2468 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2469 if (ret != X86EMUL_CONTINUE)
2470 return ret;
5045b468 2471 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2472 if (ret != X86EMUL_CONTINUE)
2473 return ret;
5045b468 2474 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2475 if (ret != X86EMUL_CONTINUE)
2476 return ret;
2477
2478 return X86EMUL_CONTINUE;
2479}
2480
2481static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2482 u16 tss_selector, u16 old_tss_sel,
2483 ulong old_tss_base, struct desc_struct *new_desc)
2484{
0225fb50 2485 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2486 struct tss_segment_16 tss_seg;
2487 int ret;
bcc55cba 2488 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2489
0f65dd70 2490 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2491 &ctxt->exception);
db297e3d 2492 if (ret != X86EMUL_CONTINUE)
38ba30ba 2493 /* FIXME: need to provide precise fault address */
38ba30ba 2494 return ret;
38ba30ba 2495
7b105ca2 2496 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2497
0f65dd70 2498 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2499 &ctxt->exception);
db297e3d 2500 if (ret != X86EMUL_CONTINUE)
38ba30ba 2501 /* FIXME: need to provide precise fault address */
38ba30ba 2502 return ret;
38ba30ba 2503
0f65dd70 2504 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2505 &ctxt->exception);
db297e3d 2506 if (ret != X86EMUL_CONTINUE)
38ba30ba 2507 /* FIXME: need to provide precise fault address */
38ba30ba 2508 return ret;
38ba30ba
GN		 2509
2510 if (old_tss_sel != 0xffff) {
2511 tss_seg.prev_task_link = old_tss_sel;
2512
0f65dd70 2513 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2514 &tss_seg.prev_task_link,
2515 sizeof tss_seg.prev_task_link,
0f65dd70 2516 &ctxt->exception);
db297e3d 2517 if (ret != X86EMUL_CONTINUE)
38ba30ba 2518 /* FIXME: need to provide precise fault address */
38ba30ba 2519 return ret;
38ba30ba
GN		 2520 }
2521
7b105ca2 2522 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2523}
2524
2525static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2526 struct tss_segment_32 *tss)
2527{
5c7411e2 2528 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2529 tss->eip = ctxt->_eip;
38ba30ba 2530 tss->eflags = ctxt->eflags;
dd856efa
AK		 2531 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2532 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2533 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2534 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2535 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2536 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2537 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2538 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2539
1aa36616
AK		 2540 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2541 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2542 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2543 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2544 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2545 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2546}
2547
2548static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2549 struct tss_segment_32 *tss)
2550{
38ba30ba 2551 int ret;
2356aaeb 2552 u8 cpl;
38ba30ba 2553
7b105ca2 2554 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2555 return emulate_gp(ctxt, 0);
9dac77fa 2556 ctxt->_eip = tss->eip;
38ba30ba 2557 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2558
2559 /* General purpose registers */
dd856efa
AK		 2560 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2561 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2562 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2563 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2564 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2565 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2566 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2567 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2568
2569 /*
2570 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2571 * descriptors. This is important because CPL checks will
2572 * use CS.RPL.
38ba30ba 2573 */
1aa36616
AK		 2574 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2575 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2576 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2577 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2578 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2579 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2580 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2581
4cee4798
KW		 2582 /*
2583 * If we're switching between Protected Mode and VM86, we need to make
2584 * sure to update the mode before loading the segment descriptors so
2585 * that the selectors are interpreted correctly.
4cee4798 2586 */
2356aaeb 2587 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2588 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2589 cpl = 3;
2590 } else {
4cee4798 2591 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2592 cpl = tss->cs & 3;
2593 }
4cee4798 2594
38ba30ba
GN		 2595 /*
2596 * Now load segment descriptors. If fault happenes at this stage
2597 * it is handled in a context of new task
2598 */
5045b468 2599 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2600 if (ret != X86EMUL_CONTINUE)
2601 return ret;
5045b468 2602 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2603 if (ret != X86EMUL_CONTINUE)
2604 return ret;
5045b468 2605 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2606 if (ret != X86EMUL_CONTINUE)
2607 return ret;
5045b468 2608 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2609 if (ret != X86EMUL_CONTINUE)
2610 return ret;
5045b468 2611 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2612 if (ret != X86EMUL_CONTINUE)
2613 return ret;
5045b468 2614 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2615 if (ret != X86EMUL_CONTINUE)
2616 return ret;
5045b468 2617 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2618 if (ret != X86EMUL_CONTINUE)
2619 return ret;
2620
2621 return X86EMUL_CONTINUE;
2622}
2623
2624static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2625 u16 tss_selector, u16 old_tss_sel,
2626 ulong old_tss_base, struct desc_struct *new_desc)
2627{
0225fb50 2628 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2629 struct tss_segment_32 tss_seg;
2630 int ret;
bcc55cba 2631 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2632 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2633 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2634
0f65dd70 2635 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2636 &ctxt->exception);
db297e3d 2637 if (ret != X86EMUL_CONTINUE)
38ba30ba 2638 /* FIXME: need to provide precise fault address */
38ba30ba 2639 return ret;
38ba30ba 2640
7b105ca2 2641 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2642
5c7411e2
NA		 2643 /* Only GP registers and segment selectors are saved */
2644 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2645 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2646 if (ret != X86EMUL_CONTINUE)
38ba30ba 2647 /* FIXME: need to provide precise fault address */
38ba30ba 2648 return ret;
38ba30ba 2649
0f65dd70 2650 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2651 &ctxt->exception);
db297e3d 2652 if (ret != X86EMUL_CONTINUE)
38ba30ba 2653 /* FIXME: need to provide precise fault address */
38ba30ba 2654 return ret;
38ba30ba
GN		 2655
2656 if (old_tss_sel != 0xffff) {
2657 tss_seg.prev_task_link = old_tss_sel;
2658
0f65dd70 2659 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2660 &tss_seg.prev_task_link,
2661 sizeof tss_seg.prev_task_link,
0f65dd70 2662 &ctxt->exception);
db297e3d 2663 if (ret != X86EMUL_CONTINUE)
38ba30ba 2664 /* FIXME: need to provide precise fault address */
38ba30ba 2665 return ret;
38ba30ba
GN		 2666 }
2667
7b105ca2 2668 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2669}
2670
2671static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2672 u16 tss_selector, int idt_index, int reason,
e269fb21 2673 bool has_error_code, u32 error_code)
38ba30ba 2674{
0225fb50 2675 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2676 struct desc_struct curr_tss_desc, next_tss_desc;
2677 int ret;
1aa36616 2678 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2679 ulong old_tss_base =
4bff1e86 2680 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2681 u32 desc_limit;
e919464b 2682 ulong desc_addr;
38ba30ba
GN		 2683
2684 /* FIXME: old_tss_base == ~0 ? */
2685
e919464b 2686 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2687 if (ret != X86EMUL_CONTINUE)
2688 return ret;
e919464b 2689 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2690 if (ret != X86EMUL_CONTINUE)
2691 return ret;
2692
2693 /* FIXME: check that next_tss_desc is tss */
2694
7f3d35fd
KW		 2695 /*
2696 * Check privileges. The three cases are task switch caused by...
2697 *
2698 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2699 * 2. Exception/IRQ/iret: No check is performed
fc058680 2700 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2701 */
2702 if (reason == TASK_SWITCH_GATE) {
2703 if (idt_index != -1) {
2704 /* Software interrupts */
2705 struct desc_struct task_gate_desc;
2706 int dpl;
2707
2708 ret = read_interrupt_descriptor(ctxt, idt_index,
2709 &task_gate_desc);
2710 if (ret != X86EMUL_CONTINUE)
2711 return ret;
2712
2713 dpl = task_gate_desc.dpl;
2714 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2715 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2716 }
2717 } else if (reason != TASK_SWITCH_IRET) {
2718 int dpl = next_tss_desc.dpl;
2719 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2720 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2721 }
2722
7f3d35fd 2723
ceffb459
GN		 2724 desc_limit = desc_limit_scaled(&next_tss_desc);
2725 if (!next_tss_desc.p ||
2726 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2727 desc_limit < 0x2b)) {
54b8486f 2728 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2729 return X86EMUL_PROPAGATE_FAULT;
2730 }
2731
2732 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2733 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2734 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2735 }
2736
2737 if (reason == TASK_SWITCH_IRET)
2738 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2739
2740 /* set back link to prev task only if NT bit is set in eflags
fc058680 2741 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2742 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2743 old_tss_sel = 0xffff;
2744
2745 if (next_tss_desc.type & 8)
7b105ca2 2746 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2747 old_tss_base, &next_tss_desc);
2748 else
7b105ca2 2749 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2750 old_tss_base, &next_tss_desc);
0760d448
JK		 2751 if (ret != X86EMUL_CONTINUE)
2752 return ret;
38ba30ba
GN		 2753
2754 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2755 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2756
2757 if (reason != TASK_SWITCH_IRET) {
2758 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2759 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2760 }
2761
717746e3 2762 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2763 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2764
e269fb21 2765 if (has_error_code) {
9dac77fa
AK		 2766 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2767 ctxt->lock_prefix = 0;
2768 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2769 ret = em_push(ctxt);
e269fb21
JK		 2770 }
2771
38ba30ba
GN		 2772 return ret;
2773}
2774
2775int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2776 u16 tss_selector, int idt_index, int reason,
e269fb21 2777 bool has_error_code, u32 error_code)
38ba30ba 2778{
38ba30ba
GN		 2779 int rc;
2780
dd856efa 2781 invalidate_registers(ctxt);
9dac77fa
AK		 2782 ctxt->_eip = ctxt->eip;
2783 ctxt->dst.type = OP_NONE;
38ba30ba 2784
7f3d35fd 2785 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2786 has_error_code, error_code);
38ba30ba 2787
dd856efa 2788 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2789 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2790 writeback_registers(ctxt);
2791 }
38ba30ba 2792
a0c0ab2f 2793 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2794}
2795
f3bd64c6
GN		 2796static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2797 struct operand *op)
a682e354 2798{
b3356bf0 2799 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2800
dd856efa
AK		 2801 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2802 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2803}
2804
7af04fc0
AK		 2805static int em_das(struct x86_emulate_ctxt *ctxt)
2806{
7af04fc0
AK		 2807 u8 al, old_al;
2808 bool af, cf, old_cf;
2809
2810 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2811 al = ctxt->dst.val;
7af04fc0
AK		 2812
2813 old_al = al;
2814 old_cf = cf;
2815 cf = false;
2816 af = ctxt->eflags & X86_EFLAGS_AF;
2817 if ((al & 0x0f) > 9 || af) {
2818 al -= 6;
2819 cf = old_cf | (al >= 250);
2820 af = true;
2821 } else {
2822 af = false;
2823 }
2824 if (old_al > 0x99 || old_cf) {
2825 al -= 0x60;
2826 cf = true;
2827 }
2828
9dac77fa 2829 ctxt->dst.val = al;
7af04fc0 2830 /* Set PF, ZF, SF */
9dac77fa
AK		 2831 ctxt->src.type = OP_IMM;
2832 ctxt->src.val = 0;
2833 ctxt->src.bytes = 1;
158de57f 2834 fastop(ctxt, em_or);
7af04fc0
AK		 2835 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2836 if (cf)
2837 ctxt->eflags |= X86_EFLAGS_CF;
2838 if (af)
2839 ctxt->eflags |= X86_EFLAGS_AF;
2840 return X86EMUL_CONTINUE;
2841}
2842
a035d5c6
PB		 2843static int em_aam(struct x86_emulate_ctxt *ctxt)
2844{
2845 u8 al, ah;
2846
2847 if (ctxt->src.val == 0)
2848 return emulate_de(ctxt);
2849
2850 al = ctxt->dst.val & 0xff;
2851 ah = al / ctxt->src.val;
2852 al %= ctxt->src.val;
2853
2854 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2855
2856 /* Set PF, ZF, SF */
2857 ctxt->src.type = OP_IMM;
2858 ctxt->src.val = 0;
2859 ctxt->src.bytes = 1;
2860 fastop(ctxt, em_or);
2861
2862 return X86EMUL_CONTINUE;
2863}
2864
7f662273
GN		 2865static int em_aad(struct x86_emulate_ctxt *ctxt)
2866{
2867 u8 al = ctxt->dst.val & 0xff;
2868 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2869
2870 al = (al + (ah * ctxt->src.val)) & 0xff;
2871
2872 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2873
f583c29b
GN		 2874 /* Set PF, ZF, SF */
2875 ctxt->src.type = OP_IMM;
2876 ctxt->src.val = 0;
2877 ctxt->src.bytes = 1;
2878 fastop(ctxt, em_or);
7f662273
GN		 2879
2880 return X86EMUL_CONTINUE;
2881}
2882
d4ddafcd
TY		 2883static int em_call(struct x86_emulate_ctxt *ctxt)
2884{
2885 long rel = ctxt->src.val;
2886
2887 ctxt->src.val = (unsigned long)ctxt->_eip;
2888 jmp_rel(ctxt, rel);
2889 return em_push(ctxt);
2890}
2891
0ef753b8
AK		 2892static int em_call_far(struct x86_emulate_ctxt *ctxt)
2893{
0ef753b8
AK		 2894 u16 sel, old_cs;
2895 ulong old_eip;
2896 int rc;
2897
1aa36616 2898 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2899 old_eip = ctxt->_eip;
0ef753b8 2900
9dac77fa 2901 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2902 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2903 return X86EMUL_CONTINUE;
2904
9dac77fa
AK		 2905 ctxt->_eip = 0;
2906 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2907
9dac77fa 2908 ctxt->src.val = old_cs;
4487b3b4 2909 rc = em_push(ctxt);
0ef753b8
AK		 2910 if (rc != X86EMUL_CONTINUE)
2911 return rc;
2912
9dac77fa 2913 ctxt->src.val = old_eip;
4487b3b4 2914 return em_push(ctxt);
0ef753b8
AK		 2915}
2916
40ece7c7
AK		 2917static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2918{
40ece7c7
AK		 2919 int rc;
2920
9dac77fa
AK		 2921 ctxt->dst.type = OP_REG;
2922 ctxt->dst.addr.reg = &ctxt->_eip;
2923 ctxt->dst.bytes = ctxt->op_bytes;
2924 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2925 if (rc != X86EMUL_CONTINUE)
2926 return rc;
5ad105e5 2927 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2928 return X86EMUL_CONTINUE;
2929}
2930
e4f973ae
TY		 2931static int em_xchg(struct x86_emulate_ctxt *ctxt)
2932{
e4f973ae 2933 /* Write back the register source. */
9dac77fa
AK		 2934 ctxt->src.val = ctxt->dst.val;
2935 write_register_operand(&ctxt->src);
e4f973ae
TY		 2936
2937 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2938 ctxt->dst.val = ctxt->src.orig_val;
2939 ctxt->lock_prefix = 1;
e4f973ae
TY		 2940 return X86EMUL_CONTINUE;
2941}
2942
5c82aa29
AK		 2943static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2944{
9dac77fa 2945 ctxt->dst.val = ctxt->src2.val;
4d758349 2946 return fastop(ctxt, em_imul);
5c82aa29
AK		 2947}
2948
61429142
AK		 2949static int em_cwd(struct x86_emulate_ctxt *ctxt)
2950{
9dac77fa
AK		 2951 ctxt->dst.type = OP_REG;
2952 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2953 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2954 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2955
2956 return X86EMUL_CONTINUE;
2957}
2958
48bb5d3c
AK		 2959static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2960{
48bb5d3c
AK		 2961 u64 tsc = 0;
2962
717746e3 2963 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2964 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2965 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2966 return X86EMUL_CONTINUE;
2967}
2968
222d21aa
AK		 2969static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2970{
2971 u64 pmc;
2972
dd856efa 2973 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2974 return emulate_gp(ctxt, 0);
dd856efa
AK		 2975 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2976 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2977 return X86EMUL_CONTINUE;
2978}
2979
b9eac5f4
AK		 2980static int em_mov(struct x86_emulate_ctxt *ctxt)
2981{
54cfdb3e 2982 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 2983 return X86EMUL_CONTINUE;
2984}
2985
84cffe49
BP		 2986#define FFL(x) bit(X86_FEATURE_##x)
2987
2988static int em_movbe(struct x86_emulate_ctxt *ctxt)
2989{
2990 u32 ebx, ecx, edx, eax = 1;
2991 u16 tmp;
2992
2993 /*
2994 * Check MOVBE is set in the guest-visible CPUID leaf.
2995 */
2996 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2997 if (!(ecx & FFL(MOVBE)))
2998 return emulate_ud(ctxt);
2999
3000 switch (ctxt->op_bytes) {
3001 case 2:
3002 /*
3003 * From MOVBE definition: "...When the operand size is 16 bits,
3004 * the upper word of the destination register remains unchanged
3005 * ..."
3006 *
3007 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3008 * rules so we have to do the operation almost per hand.
3009 */
3010 tmp = (u16)ctxt->src.val;
3011 ctxt->dst.val &= ~0xffffUL;
3012 ctxt->dst.val |= (unsigned long)swab16(tmp);
3013 break;
3014 case 4:
3015 ctxt->dst.val = swab32((u32)ctxt->src.val);
3016 break;
3017 case 8:
3018 ctxt->dst.val = swab64(ctxt->src.val);
3019 break;
3020 default:
3021 return X86EMUL_PROPAGATE_FAULT;
3022 }
3023 return X86EMUL_CONTINUE;
3024}
3025
bc00f8d2
TY		 3026static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3027{
3028 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3029 return emulate_gp(ctxt, 0);
3030
3031 /* Disable writeback. */
3032 ctxt->dst.type = OP_NONE;
3033 return X86EMUL_CONTINUE;
3034}
3035
3036static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3037{
3038 unsigned long val;
3039
3040 if (ctxt->mode == X86EMUL_MODE_PROT64)
3041 val = ctxt->src.val & ~0ULL;
3042 else
3043 val = ctxt->src.val & ~0U;
3044
3045 /* #UD condition is already handled. */
3046 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3047 return emulate_gp(ctxt, 0);
3048
3049 /* Disable writeback. */
3050 ctxt->dst.type = OP_NONE;
3051 return X86EMUL_CONTINUE;
3052}
3053
e1e210b0
TY		 3054static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3055{
3056 u64 msr_data;
3057
dd856efa
AK		 3058 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3059 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3060 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3061 return emulate_gp(ctxt, 0);
3062
3063 return X86EMUL_CONTINUE;
3064}
3065
3066static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3067{
3068 u64 msr_data;
3069
dd856efa 3070 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3071 return emulate_gp(ctxt, 0);
3072
dd856efa
AK		 3073 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3074 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3075 return X86EMUL_CONTINUE;
3076}
3077
1bd5f469
TY		 3078static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3079{
9dac77fa 3080 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3081 return emulate_ud(ctxt);
3082
9dac77fa 3083 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3084 return X86EMUL_CONTINUE;
3085}
3086
3087static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3088{
9dac77fa 3089 u16 sel = ctxt->src.val;
1bd5f469 3090
9dac77fa 3091 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3092 return emulate_ud(ctxt);
3093
9dac77fa 3094 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3095 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3096
3097 /* Disable writeback. */
9dac77fa
AK		 3098 ctxt->dst.type = OP_NONE;
3099 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3100}
3101
a14e579f
AK		 3102static int em_lldt(struct x86_emulate_ctxt *ctxt)
3103{
3104 u16 sel = ctxt->src.val;
3105
3106 /* Disable writeback. */
3107 ctxt->dst.type = OP_NONE;
3108 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3109}
3110
80890006
AK		 3111static int em_ltr(struct x86_emulate_ctxt *ctxt)
3112{
3113 u16 sel = ctxt->src.val;
3114
3115 /* Disable writeback. */
3116 ctxt->dst.type = OP_NONE;
3117 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3118}
3119
38503911
AK		 3120static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3121{
9fa088f4
AK		 3122 int rc;
3123 ulong linear;
3124
9dac77fa 3125 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3126 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3127 ctxt->ops->invlpg(ctxt, linear);
38503911 3128 /* Disable writeback. */
9dac77fa 3129 ctxt->dst.type = OP_NONE;
38503911
AK		 3130 return X86EMUL_CONTINUE;
3131}
3132
2d04a05b
AK		 3133static int em_clts(struct x86_emulate_ctxt *ctxt)
3134{
3135 ulong cr0;
3136
3137 cr0 = ctxt->ops->get_cr(ctxt, 0);
3138 cr0 &= ~X86_CR0_TS;
3139 ctxt->ops->set_cr(ctxt, 0, cr0);
3140 return X86EMUL_CONTINUE;
3141}
3142
26d05cc7
AK		 3143static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3144{
26d05cc7
AK		 3145 int rc;
3146
9dac77fa 3147 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3148 return X86EMUL_UNHANDLEABLE;
3149
3150 rc = ctxt->ops->fix_hypercall(ctxt);
3151 if (rc != X86EMUL_CONTINUE)
3152 return rc;
3153
3154 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3155 ctxt->_eip = ctxt->eip;
26d05cc7 3156 /* Disable writeback. */
9dac77fa 3157 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3158 return X86EMUL_CONTINUE;
3159}
3160
96051572
AK		 3161static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3162 void (*get)(struct x86_emulate_ctxt *ctxt,
3163 struct desc_ptr *ptr))
3164{
3165 struct desc_ptr desc_ptr;
3166
3167 if (ctxt->mode == X86EMUL_MODE_PROT64)
3168 ctxt->op_bytes = 8;
3169 get(ctxt, &desc_ptr);
3170 if (ctxt->op_bytes == 2) {
3171 ctxt->op_bytes = 4;
3172 desc_ptr.address &= 0x00ffffff;
3173 }
3174 /* Disable writeback. */
3175 ctxt->dst.type = OP_NONE;
3176 return segmented_write(ctxt, ctxt->dst.addr.mem,
3177 &desc_ptr, 2 + ctxt->op_bytes);
3178}
3179
3180static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3181{
3182 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3183}
3184
3185static int em_sidt(struct x86_emulate_ctxt *ctxt)
3186{
3187 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3188}
3189
26d05cc7
AK		 3190static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3191{
26d05cc7
AK		 3192 struct desc_ptr desc_ptr;
3193 int rc;
3194
510425ff
AK		 3195 if (ctxt->mode == X86EMUL_MODE_PROT64)
3196 ctxt->op_bytes = 8;
9dac77fa 3197 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3198 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3199 ctxt->op_bytes);
26d05cc7
AK		 3200 if (rc != X86EMUL_CONTINUE)
3201 return rc;
3202 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3203 /* Disable writeback. */
9dac77fa 3204 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3205 return X86EMUL_CONTINUE;
3206}
3207
5ef39c71 3208static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3209{
26d05cc7
AK		 3210 int rc;
3211
5ef39c71
AK		 3212 rc = ctxt->ops->fix_hypercall(ctxt);
3213
26d05cc7 3214 /* Disable writeback. */
9dac77fa 3215 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3216 return rc;
3217}
3218
3219static int em_lidt(struct x86_emulate_ctxt *ctxt)
3220{
26d05cc7
AK		 3221 struct desc_ptr desc_ptr;
3222 int rc;
3223
510425ff
AK		 3224 if (ctxt->mode == X86EMUL_MODE_PROT64)
3225 ctxt->op_bytes = 8;
9dac77fa 3226 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3227 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3228 ctxt->op_bytes);
26d05cc7
AK		 3229 if (rc != X86EMUL_CONTINUE)
3230 return rc;
3231 ctxt->ops->set_idt(ctxt, &desc_ptr);
3232 /* Disable writeback. */
9dac77fa 3233 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3234 return X86EMUL_CONTINUE;
3235}
3236
3237static int em_smsw(struct x86_emulate_ctxt *ctxt)
3238{
32e94d06
NA		 3239 if (ctxt->dst.type == OP_MEM)
3240 ctxt->dst.bytes = 2;
9dac77fa 3241 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3242 return X86EMUL_CONTINUE;
3243}
3244
3245static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3246{
26d05cc7 3247 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3248 | (ctxt->src.val & 0x0f));
3249 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3250 return X86EMUL_CONTINUE;
3251}
3252
d06e03ad
TY		 3253static int em_loop(struct x86_emulate_ctxt *ctxt)
3254{
dd856efa
AK		 3255 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3256 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3257 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3258 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3259
3260 return X86EMUL_CONTINUE;
3261}
3262
3263static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3264{
dd856efa 3265 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3266 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3267
3268 return X86EMUL_CONTINUE;
3269}
3270
d7841a4b
TY		 3271static int em_in(struct x86_emulate_ctxt *ctxt)
3272{
3273 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3274 &ctxt->dst.val))
3275 return X86EMUL_IO_NEEDED;
3276
3277 return X86EMUL_CONTINUE;
3278}
3279
3280static int em_out(struct x86_emulate_ctxt *ctxt)
3281{
3282 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3283 &ctxt->src.val, 1);
3284 /* Disable writeback. */
3285 ctxt->dst.type = OP_NONE;
3286 return X86EMUL_CONTINUE;
3287}
3288
f411e6cd
TY		 3289static int em_cli(struct x86_emulate_ctxt *ctxt)
3290{
3291 if (emulator_bad_iopl(ctxt))
3292 return emulate_gp(ctxt, 0);
3293
3294 ctxt->eflags &= ~X86_EFLAGS_IF;
3295 return X86EMUL_CONTINUE;
3296}
3297
3298static int em_sti(struct x86_emulate_ctxt *ctxt)
3299{
3300 if (emulator_bad_iopl(ctxt))
3301 return emulate_gp(ctxt, 0);
3302
3303 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3304 ctxt->eflags |= X86_EFLAGS_IF;
3305 return X86EMUL_CONTINUE;
3306}
3307
6d6eede4
AK		 3308static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3309{
3310 u32 eax, ebx, ecx, edx;
3311
dd856efa
AK		 3312 eax = reg_read(ctxt, VCPU_REGS_RAX);
3313 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3314 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3315 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3316 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3317 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3318 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3319 return X86EMUL_CONTINUE;
3320}
3321
98f73630
PB		 3322static int em_sahf(struct x86_emulate_ctxt *ctxt)
3323{
3324 u32 flags;
3325
3326 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3327 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3328
3329 ctxt->eflags &= ~0xffUL;
3330 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3331 return X86EMUL_CONTINUE;
3332}
3333
2dd7caa0
AK		 3334static int em_lahf(struct x86_emulate_ctxt *ctxt)
3335{
dd856efa
AK		 3336 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3337 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3338 return X86EMUL_CONTINUE;
3339}
3340
9299836e
AK		 3341static int em_bswap(struct x86_emulate_ctxt *ctxt)
3342{
3343 switch (ctxt->op_bytes) {
3344#ifdef CONFIG_X86_64
3345 case 8:
3346 asm("bswap %0" : "+r"(ctxt->dst.val));
3347 break;
3348#endif
3349 default:
3350 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3351 break;
3352 }
3353 return X86EMUL_CONTINUE;
3354}
3355
cfec82cb
JR		 3356static bool valid_cr(int nr)
3357{
3358 switch (nr) {
3359 case 0:
3360 case 2 ... 4:
3361 case 8:
3362 return true;
3363 default:
3364 return false;
3365 }
3366}
3367
3368static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3369{
9dac77fa 3370 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3371 return emulate_ud(ctxt);
3372
3373 return X86EMUL_CONTINUE;
3374}
3375
3376static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3377{
9dac77fa
AK		 3378 u64 new_val = ctxt->src.val64;
3379 int cr = ctxt->modrm_reg;
c2ad2bb3 3380 u64 efer = 0;
cfec82cb
JR		 3381
3382 static u64 cr_reserved_bits[] = {
3383 0xffffffff00000000ULL,
3384 0, 0, 0, /* CR3 checked later */
3385 CR4_RESERVED_BITS,
3386 0, 0, 0,
3387 CR8_RESERVED_BITS,
3388 };
3389
3390 if (!valid_cr(cr))
3391 return emulate_ud(ctxt);
3392
3393 if (new_val & cr_reserved_bits[cr])
3394 return emulate_gp(ctxt, 0);
3395
3396 switch (cr) {
3397 case 0: {
c2ad2bb3 3398 u64 cr4;
cfec82cb
JR		 3399 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3400 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3401 return emulate_gp(ctxt, 0);
3402
717746e3
AK		 3403 cr4 = ctxt->ops->get_cr(ctxt, 4);
3404 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3405
3406 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3407 !(cr4 & X86_CR4_PAE))
3408 return emulate_gp(ctxt, 0);
3409
3410 break;
3411 }
3412 case 3: {
3413 u64 rsvd = 0;
3414
c2ad2bb3
AK		 3415 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3416 if (efer & EFER_LMA)
cfec82cb 3417 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3418
3419 if (new_val & rsvd)
3420 return emulate_gp(ctxt, 0);
3421
3422 break;
3423 }
3424 case 4: {
717746e3 3425 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3426
3427 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3428 return emulate_gp(ctxt, 0);
3429
3430 break;
3431 }
3432 }
3433
3434 return X86EMUL_CONTINUE;
3435}
3436
3b88e41a
JR		 3437static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3438{
3439 unsigned long dr7;
3440
717746e3 3441 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3442
3443 /* Check if DR7.Global_Enable is set */
3444 return dr7 & (1 << 13);
3445}
3446
3447static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3448{
9dac77fa 3449 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3450 u64 cr4;
3451
3452 if (dr > 7)
3453 return emulate_ud(ctxt);
3454
717746e3 3455 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3456 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3457 return emulate_ud(ctxt);
3458
3459 if (check_dr7_gd(ctxt))
3460 return emulate_db(ctxt);
3461
3462 return X86EMUL_CONTINUE;
3463}
3464
3465static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3466{
9dac77fa
AK		 3467 u64 new_val = ctxt->src.val64;
3468 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3469
3470 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3471 return emulate_gp(ctxt, 0);
3472
3473 return check_dr_read(ctxt);
3474}
3475
01de8b09
JR		 3476static int check_svme(struct x86_emulate_ctxt *ctxt)
3477{
3478 u64 efer;
3479
717746e3 3480 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3481
3482 if (!(efer & EFER_SVME))
3483 return emulate_ud(ctxt);
3484
3485 return X86EMUL_CONTINUE;
3486}
3487
3488static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3489{
dd856efa 3490 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3491
3492 /* Valid physical address? */
d4224449 3493 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3494 return emulate_gp(ctxt, 0);
3495
3496 return check_svme(ctxt);
3497}
3498
d7eb8203
JR		 3499static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3500{
717746e3 3501 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3502
717746e3 3503 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3504 return emulate_ud(ctxt);
3505
3506 return X86EMUL_CONTINUE;
3507}
3508
8061252e
JR		 3509static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3510{
717746e3 3511 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3512 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3513
717746e3 3514 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3515 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3516 return emulate_gp(ctxt, 0);
3517
3518 return X86EMUL_CONTINUE;
3519}
3520
f6511935
JR		 3521static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3522{
9dac77fa
AK		 3523 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3524 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3525 return emulate_gp(ctxt, 0);
3526
3527 return X86EMUL_CONTINUE;
3528}
3529
3530static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3531{
9dac77fa
AK		 3532 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3533 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3534 return emulate_gp(ctxt, 0);
3535
3536 return X86EMUL_CONTINUE;
3537}
3538
73fba5f4 3539#define D(_y) { .flags = (_y) }
d40a6898
PB		 3540#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3541#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3542 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3543#define N D(NotImpl)
01de8b09 3544#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3545#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3546#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3547#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3548#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3549#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3550#define II(_f, _e, _i) \
d40a6898 3551 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3552#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3553 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3554 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3555#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3556
8d8f4e9f 3557#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3558#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3559#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3560#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3561#define I2bvIP(_f, _e, _i, _p) \
3562 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3563
fb864fbc
AK		 3564#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3565 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3566 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3567
fd0a0d82 3568static const struct opcode group7_rm1[] = {
1c2545be
TY		 3569 DI(SrcNone | Priv, monitor),
3570 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3571 N, N, N, N, N, N,
3572};
3573
fd0a0d82 3574static const struct opcode group7_rm3[] = {
1c2545be 3575 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3576 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3577 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3578 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3579 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3580 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3581 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3582 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3583};
6230f7fc 3584
fd0a0d82 3585static const struct opcode group7_rm7[] = {
d7eb8203 3586 N,
1c2545be 3587 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3588 N, N, N, N, N, N,
3589};
d67fc27a 3590
fd0a0d82 3591static const struct opcode group1[] = {
fb864fbc
AK		 3592 F(Lock, em_add),
3593 F(Lock | PageTable, em_or),
3594 F(Lock, em_adc),
3595 F(Lock, em_sbb),
3596 F(Lock | PageTable, em_and),
3597 F(Lock, em_sub),
3598 F(Lock, em_xor),
3599 F(NoWrite, em_cmp),
73fba5f4
AK		 3600};
3601
fd0a0d82 3602static const struct opcode group1A[] = {
1c2545be 3603 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3604};
3605
007a3b54
AK		 3606static const struct opcode group2[] = {
3607 F(DstMem | ModRM, em_rol),
3608 F(DstMem | ModRM, em_ror),
3609 F(DstMem | ModRM, em_rcl),
3610 F(DstMem | ModRM, em_rcr),
3611 F(DstMem | ModRM, em_shl),
3612 F(DstMem | ModRM, em_shr),
3613 F(DstMem | ModRM, em_shl),
3614 F(DstMem | ModRM, em_sar),
3615};
3616
fd0a0d82 3617static const struct opcode group3[] = {
fb864fbc
AK		 3618 F(DstMem | SrcImm | NoWrite, em_test),
3619 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3620 F(DstMem | SrcNone | Lock, em_not),
3621 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3622 F(DstXacc | Src2Mem, em_mul_ex),
3623 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3624 F(DstXacc | Src2Mem, em_div_ex),
3625 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3626};
3627
fd0a0d82 3628static const struct opcode group4[] = {
95413dc4
AK		 3629 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3630 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3631 N, N, N, N, N, N,
3632};
3633
fd0a0d82 3634static const struct opcode group5[] = {
95413dc4
AK		 3635 F(DstMem | SrcNone | Lock, em_inc),
3636 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3637 I(SrcMem | Stack, em_grp45),
3638 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3639 I(SrcMem | Stack, em_grp45),
3640 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3641 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3642};
3643
fd0a0d82 3644static const struct opcode group6[] = {
1c2545be
TY		 3645 DI(Prot, sldt),
3646 DI(Prot, str),
a14e579f 3647 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3648 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3649 N, N, N, N,
3650};
3651
fd0a0d82 3652static const struct group_dual group7 = { {
606b1c3e
NA		 3653 II(Mov | DstMem, em_sgdt, sgdt),
3654 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3655 II(SrcMem | Priv, em_lgdt, lgdt),
3656 II(SrcMem | Priv, em_lidt, lidt),
3657 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3658 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3659 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3660}, {
b51e974f 3661 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3662 EXT(0, group7_rm1),
01de8b09 3663 N, EXT(0, group7_rm3),
1c2545be
TY		 3664 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3665 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3666 EXT(0, group7_rm7),
73fba5f4
AK		 3667} };
3668
fd0a0d82 3669static const struct opcode group8[] = {
73fba5f4 3670 N, N, N, N,
11c363ba
AK		 3671 F(DstMem | SrcImmByte | NoWrite, em_bt),
3672 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3673 F(DstMem | SrcImmByte | Lock, em_btr),
3674 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3675};
3676
fd0a0d82 3677static const struct group_dual group9 = { {
1c2545be 3678 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3679}, {
3680 N, N, N, N, N, N, N, N,
3681} };
3682
fd0a0d82 3683static const struct opcode group11[] = {
1c2545be 3684 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3685 X7(D(Undefined)),
a4d4a7c1
AK		 3686};
3687
fd0a0d82 3688static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3689 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3690};
3691
fd0a0d82 3692static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3693 I(0, em_mov), N, N, N,
3694};
3695
27ce8258 3696static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3697 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3698};
3699
045a282c
GN		 3700static const struct escape escape_d9 = { {
3701 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3702}, {
3703 /* 0xC0 - 0xC7 */
3704 N, N, N, N, N, N, N, N,
3705 /* 0xC8 - 0xCF */
3706 N, N, N, N, N, N, N, N,
3707 /* 0xD0 - 0xC7 */
3708 N, N, N, N, N, N, N, N,
3709 /* 0xD8 - 0xDF */
3710 N, N, N, N, N, N, N, N,
3711 /* 0xE0 - 0xE7 */
3712 N, N, N, N, N, N, N, N,
3713 /* 0xE8 - 0xEF */
3714 N, N, N, N, N, N, N, N,
3715 /* 0xF0 - 0xF7 */
3716 N, N, N, N, N, N, N, N,
3717 /* 0xF8 - 0xFF */
3718 N, N, N, N, N, N, N, N,
3719} };
3720
3721static const struct escape escape_db = { {
3722 N, N, N, N, N, N, N, N,
3723}, {
3724 /* 0xC0 - 0xC7 */
3725 N, N, N, N, N, N, N, N,
3726 /* 0xC8 - 0xCF */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xD0 - 0xC7 */
3729 N, N, N, N, N, N, N, N,
3730 /* 0xD8 - 0xDF */
3731 N, N, N, N, N, N, N, N,
3732 /* 0xE0 - 0xE7 */
3733 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3734 /* 0xE8 - 0xEF */
3735 N, N, N, N, N, N, N, N,
3736 /* 0xF0 - 0xF7 */
3737 N, N, N, N, N, N, N, N,
3738 /* 0xF8 - 0xFF */
3739 N, N, N, N, N, N, N, N,
3740} };
3741
3742static const struct escape escape_dd = { {
3743 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3744}, {
3745 /* 0xC0 - 0xC7 */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xC8 - 0xCF */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xD0 - 0xC7 */
3750 N, N, N, N, N, N, N, N,
3751 /* 0xD8 - 0xDF */
3752 N, N, N, N, N, N, N, N,
3753 /* 0xE0 - 0xE7 */
3754 N, N, N, N, N, N, N, N,
3755 /* 0xE8 - 0xEF */
3756 N, N, N, N, N, N, N, N,
3757 /* 0xF0 - 0xF7 */
3758 N, N, N, N, N, N, N, N,
3759 /* 0xF8 - 0xFF */
3760 N, N, N, N, N, N, N, N,
3761} };
3762
fd0a0d82 3763static const struct opcode opcode_table[256] = {
73fba5f4 3764 /* 0x00 - 0x07 */
fb864fbc 3765 F6ALU(Lock, em_add),
1cd196ea
AK		 3766 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3767 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3768 /* 0x08 - 0x0F */
fb864fbc 3769 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3770 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3771 N,
73fba5f4 3772 /* 0x10 - 0x17 */
fb864fbc 3773 F6ALU(Lock, em_adc),
1cd196ea
AK		 3774 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3775 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3776 /* 0x18 - 0x1F */
fb864fbc 3777 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3778 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3779 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3780 /* 0x20 - 0x27 */
fb864fbc 3781 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3782 /* 0x28 - 0x2F */
fb864fbc 3783 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3784 /* 0x30 - 0x37 */
fb864fbc 3785 F6ALU(Lock, em_xor), N, N,
73fba5f4 3786 /* 0x38 - 0x3F */
fb864fbc 3787 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3788 /* 0x40 - 0x4F */
95413dc4 3789 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3790 /* 0x50 - 0x57 */
63540382 3791 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3792 /* 0x58 - 0x5F */
c54fe504 3793 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3794 /* 0x60 - 0x67 */
b96a7fad
TY		 3795 I(ImplicitOps | Stack | No64, em_pusha),
3796 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3797 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3798 N, N, N, N,
3799 /* 0x68 - 0x6F */
d46164db
AK		 3800 I(SrcImm | Mov | Stack, em_push),
3801 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3802 I(SrcImmByte | Mov | Stack, em_push),
3803 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3804 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3805 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3806 /* 0x70 - 0x7F */
3807 X16(D(SrcImmByte)),
3808 /* 0x80 - 0x87 */
1c2545be
TY		 3809 G(ByteOp | DstMem | SrcImm, group1),
3810 G(DstMem | SrcImm, group1),
3811 G(ByteOp | DstMem | SrcImm | No64, group1),
3812 G(DstMem | SrcImmByte, group1),
fb864fbc 3813 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3814 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3815 /* 0x88 - 0x8F */
d5ae7ce8 3816 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3817 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3818 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3819 D(ModRM | SrcMem | NoAccess | DstReg),
3820 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3821 G(0, group1A),
73fba5f4 3822 /* 0x90 - 0x97 */
bf608f88 3823 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3824 /* 0x98 - 0x9F */
61429142 3825 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3826 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3827 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3828 II(ImplicitOps | Stack, em_popf, popf),
3829 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3830 /* 0xA0 - 0xA7 */
b9eac5f4 3831 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3832 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3833 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3834 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3835 /* 0xA8 - 0xAF */
fb864fbc 3836 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3837 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3838 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3839 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3840 /* 0xB0 - 0xB7 */
b9eac5f4 3841 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3842 /* 0xB8 - 0xBF */
5e2c6883 3843 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3844 /* 0xC0 - 0xC7 */
007a3b54 3845 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3846 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3847 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3848 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3849 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3850 G(ByteOp, group11), G(0, group11),
73fba5f4 3851 /* 0xC8 - 0xCF */
612e89f0 3852 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3853 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3854 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3855 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3856 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3857 /* 0xD0 - 0xD7 */
007a3b54
AK		 3858 G(Src2One | ByteOp, group2), G(Src2One, group2),
3859 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3860 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3861 I(DstAcc | SrcImmUByte | No64, em_aad),
3862 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3863 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3864 /* 0xD8 - 0xDF */
045a282c 3865 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3866 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3867 X3(I(SrcImmByte, em_loop)),
3868 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3869 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3870 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3871 /* 0xE8 - 0xEF */
d4ddafcd 3872 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3873 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3874 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3875 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3876 /* 0xF0 - 0xF7 */
bf608f88 3877 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3878 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3879 G(ByteOp, group3), G(0, group3),
73fba5f4 3880 /* 0xF8 - 0xFF */
f411e6cd
TY		 3881 D(ImplicitOps), D(ImplicitOps),
3882 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3883 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3884};
3885
fd0a0d82 3886static const struct opcode twobyte_table[256] = {
73fba5f4 3887 /* 0x00 - 0x0F */
dee6bb70 3888 G(0, group6), GD(0, &group7), N, N,
b51e974f 3889 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3890 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3891 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3892 N, D(ImplicitOps | ModRM), N, N,
3893 /* 0x10 - 0x1F */
103f98ea
PB		 3894 N, N, N, N, N, N, N, N,
3895 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3896 /* 0x20 - 0x2F */
9b88ae99
NA		 3897 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3898 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3899 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3900 check_cr_write),
3901 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3902 check_dr_write),
73fba5f4 3903 N, N, N, N,
27ce8258
IM		 3904 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3905 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3906 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3907 N, N, N, N,
73fba5f4 3908 /* 0x30 - 0x3F */
e1e210b0 3909 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3910 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3911 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3912 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3913 I(ImplicitOps | EmulateOnUD, em_sysenter),
3914 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3915 N, N,
73fba5f4
AK		 3916 N, N, N, N, N, N, N, N,
3917 /* 0x40 - 0x4F */
140bad89 3918 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 3919 /* 0x50 - 0x5F */
3920 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3921 /* 0x60 - 0x6F */
aa97bb48
AK		 3922 N, N, N, N,
3923 N, N, N, N,
3924 N, N, N, N,
3925 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3926 /* 0x70 - 0x7F */
aa97bb48
AK		 3927 N, N, N, N,
3928 N, N, N, N,
3929 N, N, N, N,
3930 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3931 /* 0x80 - 0x8F */
3932 X16(D(SrcImm)),
3933 /* 0x90 - 0x9F */
ee45b58e 3934 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3935 /* 0xA0 - 0xA7 */
1cd196ea 3936 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3937 II(ImplicitOps, em_cpuid, cpuid),
3938 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3939 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3940 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3941 /* 0xA8 - 0xAF */
1cd196ea 3942 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3943 DI(ImplicitOps, rsm),
11c363ba 3944 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3945 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3946 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3947 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3948 /* 0xB0 - 0xB7 */
e940b5c2 3949 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3950 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3951 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3952 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3953 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3954 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3955 /* 0xB8 - 0xBF */
3956 N, N,
ce7faab2 3957 G(BitOp, group8),
11c363ba
AK		 3958 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3959 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3960 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3961 /* 0xC0 - 0xC7 */
e47a5f5f 3962 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3963 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3964 N, N, N, GD(0, &group9),
9299836e
AK		 3965 /* 0xC8 - 0xCF */
3966 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3967 /* 0xD0 - 0xDF */
3968 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3969 /* 0xE0 - 0xEF */
3970 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3971 /* 0xF0 - 0xFF */
3972 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3973};
3974
0bc5eedb 3975static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3976 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3977};
3978
3979static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3980 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3981};
3982
3983/*
3984 * Insns below are selected by the prefix which indexed by the third opcode
3985 * byte.
3986 */
3987static const struct opcode opcode_map_0f_38[256] = {
3988 /* 0x00 - 0x7f */
3989 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3990 /* 0x80 - 0xef */
3991 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3992 /* 0xf0 - 0xf1 */
3993 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3994 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3995 /* 0xf2 - 0xff */
3996 N, N, X4(N), X8(N)
0bc5eedb
BP		 3997};
3998
73fba5f4
AK		 3999#undef D
4000#undef N
4001#undef G
4002#undef GD
4003#undef I
aa97bb48 4004#undef GP
01de8b09 4005#undef EXT
73fba5f4 4006
8d8f4e9f 4007#undef D2bv
f6511935 4008#undef D2bvIP
8d8f4e9f 4009#undef I2bv
d7841a4b 4010#undef I2bvIP
d67fc27a 4011#undef I6ALU
8d8f4e9f 4012
9dac77fa 4013static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4014{
4015 unsigned size;
4016
9dac77fa 4017 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4018 if (size == 8)
4019 size = 4;
4020 return size;
4021}
4022
4023static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4024 unsigned size, bool sign_extension)
4025{
39f21ee5
AK		 4026 int rc = X86EMUL_CONTINUE;
4027
4028 op->type = OP_IMM;
4029 op->bytes = size;
9dac77fa 4030 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4031 /* NB. Immediates are sign-extended as necessary. */
4032 switch (op->bytes) {
4033 case 1:
e85a1085 4034 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4035 break;
4036 case 2:
e85a1085 4037 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4038 break;
4039 case 4:
e85a1085 4040 op->val = insn_fetch(s32, ctxt);
39f21ee5 4041 break;
5e2c6883
NA		 4042 case 8:
4043 op->val = insn_fetch(s64, ctxt);
4044 break;
39f21ee5
AK		 4045 }
4046 if (!sign_extension) {
4047 switch (op->bytes) {
4048 case 1:
4049 op->val &= 0xff;
4050 break;
4051 case 2:
4052 op->val &= 0xffff;
4053 break;
4054 case 4:
4055 op->val &= 0xffffffff;
4056 break;
4057 }
4058 }
4059done:
4060 return rc;
4061}
4062
a9945549
AK		 4063static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4064 unsigned d)
4065{
4066 int rc = X86EMUL_CONTINUE;
4067
4068 switch (d) {
4069 case OpReg:
2adb5ad9 4070 decode_register_operand(ctxt, op);
a9945549
AK		 4071 break;
4072 case OpImmUByte:
608aabe3 4073 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4074 break;
4075 case OpMem:
41ddf978 4076 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4077 mem_common:
4078 *op = ctxt->memop;
4079 ctxt->memopp = op;
96888977 4080 if (ctxt->d & BitOp)
a9945549
AK		 4081 fetch_bit_operand(ctxt);
4082 op->orig_val = op->val;
4083 break;
41ddf978 4084 case OpMem64:
aaa05f24 4085 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4086 goto mem_common;
a9945549
AK		 4087 case OpAcc:
4088 op->type = OP_REG;
4089 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4090 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4091 fetch_register_operand(op);
4092 op->orig_val = op->val;
4093 break;
820207c8
AK		 4094 case OpAccLo:
4095 op->type = OP_REG;
4096 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4097 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4098 fetch_register_operand(op);
4099 op->orig_val = op->val;
4100 break;
4101 case OpAccHi:
4102 if (ctxt->d & ByteOp) {
4103 op->type = OP_NONE;
4104 break;
4105 }
4106 op->type = OP_REG;
4107 op->bytes = ctxt->op_bytes;
4108 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4109 fetch_register_operand(op);
4110 op->orig_val = op->val;
4111 break;
a9945549
AK		 4112 case OpDI:
4113 op->type = OP_MEM;
4114 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4115 op->addr.mem.ea =
dd856efa 4116 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4117 op->addr.mem.seg = VCPU_SREG_ES;
4118 op->val = 0;
b3356bf0 4119 op->count = 1;
a9945549
AK		 4120 break;
4121 case OpDX:
4122 op->type = OP_REG;
4123 op->bytes = 2;
dd856efa 4124 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4125 fetch_register_operand(op);
4126 break;
4dd6a57d
AK		 4127 case OpCL:
4128 op->bytes = 1;
dd856efa 4129 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4130 break;
4131 case OpImmByte:
4132 rc = decode_imm(ctxt, op, 1, true);
4133 break;
4134 case OpOne:
4135 op->bytes = 1;
4136 op->val = 1;
4137 break;
4138 case OpImm:
4139 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4140 break;
5e2c6883
NA		 4141 case OpImm64:
4142 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4143 break;
28867cee
AK		 4144 case OpMem8:
4145 ctxt->memop.bytes = 1;
660696d1 4146 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4147 ctxt->memop.addr.reg = decode_register(ctxt,
4148 ctxt->modrm_rm, true);
660696d1
GN		 4149 fetch_register_operand(&ctxt->memop);
4150 }
28867cee 4151 goto mem_common;
0fe59128
AK		 4152 case OpMem16:
4153 ctxt->memop.bytes = 2;
4154 goto mem_common;
4155 case OpMem32:
4156 ctxt->memop.bytes = 4;
4157 goto mem_common;
4158 case OpImmU16:
4159 rc = decode_imm(ctxt, op, 2, false);
4160 break;
4161 case OpImmU:
4162 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4163 break;
4164 case OpSI:
4165 op->type = OP_MEM;
4166 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4167 op->addr.mem.ea =
dd856efa 4168 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4169 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4170 op->val = 0;
b3356bf0 4171 op->count = 1;
0fe59128 4172 break;
7fa57952
PB		 4173 case OpXLat:
4174 op->type = OP_MEM;
4175 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4176 op->addr.mem.ea =
4177 register_address(ctxt,
4178 reg_read(ctxt, VCPU_REGS_RBX) +
4179 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4180 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4181 op->val = 0;
4182 break;
0fe59128
AK		 4183 case OpImmFAddr:
4184 op->type = OP_IMM;
4185 op->addr.mem.ea = ctxt->_eip;
4186 op->bytes = ctxt->op_bytes + 2;
4187 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4188 break;
4189 case OpMemFAddr:
4190 ctxt->memop.bytes = ctxt->op_bytes + 2;
4191 goto mem_common;
c191a7a0
AK		 4192 case OpES:
4193 op->val = VCPU_SREG_ES;
4194 break;
4195 case OpCS:
4196 op->val = VCPU_SREG_CS;
4197 break;
4198 case OpSS:
4199 op->val = VCPU_SREG_SS;
4200 break;
4201 case OpDS:
4202 op->val = VCPU_SREG_DS;
4203 break;
4204 case OpFS:
4205 op->val = VCPU_SREG_FS;
4206 break;
4207 case OpGS:
4208 op->val = VCPU_SREG_GS;
4209 break;
a9945549
AK		 4210 case OpImplicit:
4211 /* Special instructions do their own operand decoding. */
4212 default:
4213 op->type = OP_NONE; /* Disable writeback. */
4214 break;
4215 }
4216
4217done:
4218 return rc;
4219}
4220
ef5d75cc 4221int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4222{
dde7e6d1
AK		 4223 int rc = X86EMUL_CONTINUE;
4224 int mode = ctxt->mode;
46561646 4225 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4226 bool op_prefix = false;
573e80fe 4227 bool has_seg_override = false;
46561646 4228 struct opcode opcode;
dde7e6d1 4229
f09ed83e
AK		 4230 ctxt->memop.type = OP_NONE;
4231 ctxt->memopp = NULL;
9dac77fa
AK		 4232 ctxt->_eip = ctxt->eip;
4233 ctxt->fetch.start = ctxt->_eip;
4234 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4235 ctxt->opcode_len = 1;
dc25e89e 4236 if (insn_len > 0)
9dac77fa 4237 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4238 else {
5cfc7e0f 4239 rc = do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4240 if (rc != X86EMUL_CONTINUE)
4241 return rc;
4242 }
dde7e6d1
AK		 4243
4244 switch (mode) {
4245 case X86EMUL_MODE_REAL:
4246 case X86EMUL_MODE_VM86:
4247 case X86EMUL_MODE_PROT16:
4248 def_op_bytes = def_ad_bytes = 2;
4249 break;
4250 case X86EMUL_MODE_PROT32:
4251 def_op_bytes = def_ad_bytes = 4;
4252 break;
4253#ifdef CONFIG_X86_64
4254 case X86EMUL_MODE_PROT64:
4255 def_op_bytes = 4;
4256 def_ad_bytes = 8;
4257 break;
4258#endif
4259 default:
1d2887e2 4260 return EMULATION_FAILED;
dde7e6d1
AK		 4261 }
4262
9dac77fa
AK		 4263 ctxt->op_bytes = def_op_bytes;
4264 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4265
4266 /* Legacy prefixes. */
4267 for (;;) {
e85a1085 4268 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4269 case 0x66: /* operand-size override */
0d7cdee8 4270 op_prefix = true;
dde7e6d1 4271 /* switch between 2/4 bytes */
9dac77fa 4272 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4273 break;
4274 case 0x67: /* address-size override */
4275 if (mode == X86EMUL_MODE_PROT64)
4276 /* switch between 4/8 bytes */
9dac77fa 4277 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4278 else
4279 /* switch between 2/4 bytes */
9dac77fa 4280 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4281 break;
4282 case 0x26: /* ES override */
4283 case 0x2e: /* CS override */
4284 case 0x36: /* SS override */
4285 case 0x3e: /* DS override */
573e80fe
BD		 4286 has_seg_override = true;
4287 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4288 break;
4289 case 0x64: /* FS override */
4290 case 0x65: /* GS override */
573e80fe
BD		 4291 has_seg_override = true;
4292 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4293 break;
4294 case 0x40 ... 0x4f: /* REX */
4295 if (mode != X86EMUL_MODE_PROT64)
4296 goto done_prefixes;
9dac77fa 4297 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4298 continue;
4299 case 0xf0: /* LOCK */
9dac77fa 4300 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4301 break;
4302 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4303 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4304 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4305 break;
4306 default:
4307 goto done_prefixes;
4308 }
4309
4310 /* Any legacy prefix after a REX prefix nullifies its effect. */
4311
9dac77fa 4312 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4313 }
4314
4315done_prefixes:
4316
4317 /* REX prefix. */
9dac77fa
AK		 4318 if (ctxt->rex_prefix & 8)
4319 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4320
4321 /* Opcode byte(s). */
9dac77fa 4322 opcode = opcode_table[ctxt->b];
d3ad6243 4323 /* Two-byte opcode? */
9dac77fa 4324 if (ctxt->b == 0x0f) {
1ce19dc1 4325 ctxt->opcode_len = 2;
e85a1085 4326 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4327 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4328
4329 /* 0F_38 opcode map */
4330 if (ctxt->b == 0x38) {
4331 ctxt->opcode_len = 3;
4332 ctxt->b = insn_fetch(u8, ctxt);
4333 opcode = opcode_map_0f_38[ctxt->b];
4334 }
dde7e6d1 4335 }
9dac77fa 4336 ctxt->d = opcode.flags;
dde7e6d1 4337
9f4260e7
TY		 4338 if (ctxt->d & ModRM)
4339 ctxt->modrm = insn_fetch(u8, ctxt);
4340
7fe864dc
NA		 4341 /* vex-prefix instructions are not implemented */
4342 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4343 (mode == X86EMUL_MODE_PROT64 ||
4344 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4345 ctxt->d = NotImpl;
4346 }
4347
9dac77fa
AK		 4348 while (ctxt->d & GroupMask) {
4349 switch (ctxt->d & GroupMask) {
46561646 4350 case Group:
9dac77fa 4351 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4352 opcode = opcode.u.group[goffset];
4353 break;
4354 case GroupDual:
9dac77fa
AK		 4355 goffset = (ctxt->modrm >> 3) & 7;
4356 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4357 opcode = opcode.u.gdual->mod3[goffset];
4358 else
4359 opcode = opcode.u.gdual->mod012[goffset];
4360 break;
4361 case RMExt:
9dac77fa 4362 goffset = ctxt->modrm & 7;
01de8b09 4363 opcode = opcode.u.group[goffset];
46561646
AK		 4364 break;
4365 case Prefix:
9dac77fa 4366 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4367 return EMULATION_FAILED;
9dac77fa 4368 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4369 switch (simd_prefix) {
4370 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4371 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4372 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4373 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4374 }
4375 break;
045a282c
GN		 4376 case Escape:
4377 if (ctxt->modrm > 0xbf)
4378 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4379 else
4380 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4381 break;
46561646 4382 default:
1d2887e2 4383 return EMULATION_FAILED;
0d7cdee8 4384 }
46561646 4385
b1ea50b2 4386 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4387 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4388 }
4389
e24186e0
PB		 4390 /* Unrecognised? */
4391 if (ctxt->d == 0)
4392 return EMULATION_FAILED;
4393
9dac77fa 4394 ctxt->execute = opcode.u.execute;
dde7e6d1 4395
d40a6898
PB		 4396 if (unlikely(ctxt->d &
4397 (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
4398 /*
4399 * These are copied unconditionally here, and checked unconditionally
4400 * in x86_emulate_insn.
4401 */
4402 ctxt->check_perm = opcode.check_perm;
4403 ctxt->intercept = opcode.intercept;
dde7e6d1 4404
d40a6898
PB		 4405 if (ctxt->d & NotImpl)
4406 return EMULATION_FAILED;
d867162c 4407
d40a6898
PB		 4408 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
4409 return EMULATION_FAILED;
dde7e6d1 4410
d40a6898 4411 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
9dac77fa 4412 ctxt->op_bytes = 8;
7f9b4b75 4413
d40a6898
PB		 4414 if (ctxt->d & Op3264) {
4415 if (mode == X86EMUL_MODE_PROT64)
4416 ctxt->op_bytes = 8;
4417 else
4418 ctxt->op_bytes = 4;
4419 }
4420
4421 if (ctxt->d & Sse)
4422 ctxt->op_bytes = 16;
4423 else if (ctxt->d & Mmx)
4424 ctxt->op_bytes = 8;
4425 }
1253791d 4426
dde7e6d1 4427 /* ModRM and SIB bytes. */
9dac77fa 4428 if (ctxt->d & ModRM) {
f09ed83e 4429 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4430 if (!has_seg_override) {
4431 has_seg_override = true;
4432 ctxt->seg_override = ctxt->modrm_seg;
4433 }
9dac77fa 4434 } else if (ctxt->d & MemAbs)
f09ed83e 4435 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4436 if (rc != X86EMUL_CONTINUE)
4437 goto done;
4438
573e80fe
BD		 4439 if (!has_seg_override)
4440 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4441
573e80fe 4442 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4443
dde7e6d1
AK		 4444 /*
4445 * Decode and fetch the source operand: register, memory
4446 * or immediate.
4447 */
0fe59128 4448 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4449 if (rc != X86EMUL_CONTINUE)
4450 goto done;
4451
dde7e6d1
AK		 4452 /*
4453 * Decode and fetch the second source operand: register, memory
4454 * or immediate.
4455 */
4dd6a57d 4456 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4457 if (rc != X86EMUL_CONTINUE)
4458 goto done;
4459
dde7e6d1 4460 /* Decode and fetch the destination operand: register or memory. */
a9945549 4461 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4462
4463done:
41061cdb 4464 if (ctxt->rip_relative)
f09ed83e 4465 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4466
1d2887e2 4467 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4468}
4469
1cb3f3ae
XG		 4470bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4471{
4472 return ctxt->d & PageTable;
4473}
4474
3e2f65d5
GN		 4475static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4476{
3e2f65d5
GN		 4477 /* The second termination condition only applies for REPE
4478 * and REPNE. Test if the repeat string operation prefix is
4479 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4480 * corresponding termination condition according to:
4481 * - if REPE/REPZ and ZF = 0 then done
4482 * - if REPNE/REPNZ and ZF = 1 then done
4483 */
9dac77fa
AK		 4484 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4485 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4486 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4487 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4488 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4489 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4490 return true;
4491
4492 return false;
4493}
4494
cbe2c9d3
AK		 4495static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4496{
4497 bool fault = false;
4498
4499 ctxt->ops->get_fpu(ctxt);
4500 asm volatile("1: fwait \n\t"
4501 "2: \n\t"
4502 ".pushsection .fixup,\"ax\" \n\t"
4503 "3: \n\t"
4504 "movb $1, %[fault] \n\t"
4505 "jmp 2b \n\t"
4506 ".popsection \n\t"
4507 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4508 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4509 ctxt->ops->put_fpu(ctxt);
4510
4511 if (unlikely(fault))
4512 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4513
4514 return X86EMUL_CONTINUE;
4515}
4516
4517static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4518 struct operand *op)
4519{
4520 if (op->type == OP_MM)
4521 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4522}
4523
e28bbd44
AK		 4524static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4525{
4526 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4527 if (!(ctxt->d & ByteOp))
4528 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4529 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4530 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4531 [fastop]"+S"(fop)
4532 : "c"(ctxt->src2.val));
e28bbd44 4533 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4534 if (!fop) /* exception is returned in fop variable */
4535 return emulate_de(ctxt);
e28bbd44
AK		 4536 return X86EMUL_CONTINUE;
4537}
dd856efa 4538
1498507a
BD		 4539void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4540{
573e80fe
BD		 4541 memset(&ctxt->rip_relative, 0,
4542 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4543
1498507a
BD		 4544 ctxt->io_read.pos = 0;
4545 ctxt->io_read.end = 0;
1498507a
BD		 4546 ctxt->mem_read.end = 0;
4547}
4548
7b105ca2 4549int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4550{
0225fb50 4551 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4552 int rc = X86EMUL_CONTINUE;
9dac77fa 4553 int saved_dst_type = ctxt->dst.type;
8b4caf66 4554
9dac77fa 4555 ctxt->mem_read.pos = 0;
310b5d30 4556
e24186e0
PB		 4557 /* LOCK prefix is allowed only with some instructions */
4558 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4559 rc = emulate_ud(ctxt);
1161624f
GN		 4560 goto done;
4561 }
4562
e24186e0 4563 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4564 rc = emulate_ud(ctxt);
d380a5e4
GN		 4565 goto done;
4566 }
4567
d40a6898
PB		 4568 if (unlikely(ctxt->d &
4569 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4570 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4571 (ctxt->d & Undefined)) {
4572 rc = emulate_ud(ctxt);
4573 goto done;
4574 }
1253791d 4575
d40a6898
PB		 4576 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4577 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4578 rc = emulate_ud(ctxt);
cbe2c9d3 4579 goto done;
d40a6898 4580 }
cbe2c9d3 4581
d40a6898
PB		 4582 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4583 rc = emulate_nm(ctxt);
c4f035c6 4584 goto done;
d40a6898 4585 }
c4f035c6 4586
d40a6898
PB		 4587 if (ctxt->d & Mmx) {
4588 rc = flush_pending_x87_faults(ctxt);
4589 if (rc != X86EMUL_CONTINUE)
4590 goto done;
4591 /*
4592 * Now that we know the fpu is exception safe, we can fetch
4593 * operands from it.
4594 */
4595 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4596 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4597 if (!(ctxt->d & Mov))
4598 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4599 }
e92805ac 4600
685bbf4a 4601 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4602 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4603 X86_ICPT_PRE_EXCEPT);
4604 if (rc != X86EMUL_CONTINUE)
4605 goto done;
4606 }
8ea7d6ae 4607
d40a6898
PB		 4608 /* Privileged instruction can be executed only in CPL=0 */
4609 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4610 rc = emulate_gp(ctxt, 0);
d09beabd 4611 goto done;
d40a6898 4612 }
d09beabd 4613
d40a6898
PB		 4614 /* Instruction can only be executed in protected mode */
4615 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4616 rc = emulate_ud(ctxt);
c4f035c6 4617 goto done;
d40a6898 4618 }
c4f035c6 4619
d40a6898 4620 /* Do instruction specific permission checks */
685bbf4a 4621 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4622 rc = ctxt->check_perm(ctxt);
4623 if (rc != X86EMUL_CONTINUE)
4624 goto done;
4625 }
4626
685bbf4a 4627 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4628 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4629 X86_ICPT_POST_EXCEPT);
4630 if (rc != X86EMUL_CONTINUE)
4631 goto done;
4632 }
4633
4634 if (ctxt->rep_prefix && (ctxt->d & String)) {
4635 /* All REP prefixes have the same first termination condition */
4636 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4637 ctxt->eip = ctxt->_eip;
4638 goto done;
4639 }
b9fa9d6b 4640 }
b9fa9d6b
AK		 4641 }
4642
9dac77fa
AK		 4643 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4644 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4645 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4646 if (rc != X86EMUL_CONTINUE)
8b4caf66 4647 goto done;
9dac77fa 4648 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4649 }
4650
9dac77fa
AK		 4651 if (ctxt->src2.type == OP_MEM) {
4652 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4653 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4654 if (rc != X86EMUL_CONTINUE)
4655 goto done;
4656 }
4657
9dac77fa 4658 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4659 goto special_insn;
4660
4661
9dac77fa 4662 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4663 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4664 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4665 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4666 if (rc != X86EMUL_CONTINUE)
4667 goto done;
038e51de 4668 }
9dac77fa 4669 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4670
018a98db
AK		 4671special_insn:
4672
685bbf4a 4673 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4674 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4675 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4676 if (rc != X86EMUL_CONTINUE)
4677 goto done;
4678 }
4679
9dac77fa 4680 if (ctxt->execute) {
e28bbd44
AK		 4681 if (ctxt->d & Fastop) {
4682 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4683 rc = fastop(ctxt, fop);
4684 if (rc != X86EMUL_CONTINUE)
4685 goto done;
4686 goto writeback;
4687 }
9dac77fa 4688 rc = ctxt->execute(ctxt);
ef65c889
AK		 4689 if (rc != X86EMUL_CONTINUE)
4690 goto done;
4691 goto writeback;
4692 }
4693
1ce19dc1 4694 if (ctxt->opcode_len == 2)
6aa8b732 4695 goto twobyte_insn;
0bc5eedb
BP		 4696 else if (ctxt->opcode_len == 3)
4697 goto threebyte_insn;
6aa8b732 4698
9dac77fa 4699 switch (ctxt->b) {
6aa8b732 4700 case 0x63: /* movsxd */
8b4caf66 4701 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4702 goto cannot_emulate;
9dac77fa 4703 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4704 break;
b2833e3c 4705 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4706 if (test_cc(ctxt->b, ctxt->eflags))
4707 jmp_rel(ctxt, ctxt->src.val);
018a98db 4708 break;
7e0b54b1 4709 case 0x8d: /* lea r16/r32, m */
9dac77fa 4710 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4711 break;
3d9e77df 4712 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4713 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4714 ctxt->dst.type = OP_NONE;
4715 else
4716 rc = em_xchg(ctxt);
e4f973ae 4717 break;
e8b6fa70 4718 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4719 switch (ctxt->op_bytes) {
4720 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4721 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4722 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4723 }
4724 break;
6e154e56 4725 case 0xcc: /* int3 */
5c5df76b
TY		 4726 rc = emulate_int(ctxt, 3);
4727 break;
6e154e56 4728 case 0xcd: /* int n */
9dac77fa 4729 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4730 break;
4731 case 0xce: /* into */
5c5df76b
TY		 4732 if (ctxt->eflags & EFLG_OF)
4733 rc = emulate_int(ctxt, 4);
6e154e56 4734 break;
1a52e051 4735 case 0xe9: /* jmp rel */
db5b0762 4736 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4737 jmp_rel(ctxt, ctxt->src.val);
4738 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4739 break;
111de5d6 4740 case 0xf4: /* hlt */
6c3287f7 4741 ctxt->ops->halt(ctxt);
19fdfa0d 4742 break;
111de5d6
AK		 4743 case 0xf5: /* cmc */
4744 /* complement carry flag from eflags reg */
4745 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4746 break;
4747 case 0xf8: /* clc */
4748 ctxt->eflags &= ~EFLG_CF;
111de5d6 4749 break;
8744aa9a
MG		 4750 case 0xf9: /* stc */
4751 ctxt->eflags |= EFLG_CF;
4752 break;
fb4616f4
MG		 4753 case 0xfc: /* cld */
4754 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4755 break;
4756 case 0xfd: /* std */
4757 ctxt->eflags |= EFLG_DF;
fb4616f4 4758 break;
91269b8f
AK		 4759 default:
4760 goto cannot_emulate;
6aa8b732 4761 }
018a98db 4762
7d9ddaed
AK		 4763 if (rc != X86EMUL_CONTINUE)
4764 goto done;
4765
018a98db 4766writeback:
fb32b1ed
AK		 4767 if (ctxt->d & SrcWrite) {
4768 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4769 rc = writeback(ctxt, &ctxt->src);
4770 if (rc != X86EMUL_CONTINUE)
4771 goto done;
4772 }
ee212297
NA		 4773 if (!(ctxt->d & NoWrite)) {
4774 rc = writeback(ctxt, &ctxt->dst);
4775 if (rc != X86EMUL_CONTINUE)
4776 goto done;
4777 }
018a98db 4778
5cd21917
GN		 4779 /*
4780 * restore dst type in case the decoding will be reused
4781 * (happens for string instruction )
4782 */
9dac77fa 4783 ctxt->dst.type = saved_dst_type;
5cd21917 4784
9dac77fa 4785 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4786 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4787
9dac77fa 4788 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4789 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4790
9dac77fa 4791 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4792 unsigned int count;
9dac77fa 4793 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4794 if ((ctxt->d & SrcMask) == SrcSI)
4795 count = ctxt->src.count;
4796 else
4797 count = ctxt->dst.count;
4798 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4799 -count);
3e2f65d5 4800
d2ddd1c4
GN		 4801 if (!string_insn_completed(ctxt)) {
4802 /*
4803 * Re-enter guest when pio read ahead buffer is empty
4804 * or, if it is not used, after each 1024 iteration.
4805 */
dd856efa 4806 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4807 (r->end == 0 || r->end != r->pos)) {
4808 /*
4809 * Reset read cache. Usually happens before
4810 * decode, but since instruction is restarted
4811 * we have to do it here.
4812 */
9dac77fa 4813 ctxt->mem_read.end = 0;
dd856efa 4814 writeback_registers(ctxt);
d2ddd1c4
GN		 4815 return EMULATION_RESTART;
4816 }
4817 goto done; /* skip rip writeback */
0fa6ccbd 4818 }
5cd21917 4819 }
d2ddd1c4 4820
9dac77fa 4821 ctxt->eip = ctxt->_eip;
018a98db
AK		 4822
4823done:
da9cb575
AK		 4824 if (rc == X86EMUL_PROPAGATE_FAULT)
4825 ctxt->have_exception = true;
775fde86
JR		 4826 if (rc == X86EMUL_INTERCEPTED)
4827 return EMULATION_INTERCEPTED;
4828
dd856efa
AK		 4829 if (rc == X86EMUL_CONTINUE)
4830 writeback_registers(ctxt);
4831
d2ddd1c4 4832 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4833
4834twobyte_insn:
9dac77fa 4835 switch (ctxt->b) {
018a98db 4836 case 0x09: /* wbinvd */
cfb22375 4837 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4838 break;
4839 case 0x08: /* invd */
018a98db
AK		 4840 case 0x0d: /* GrpP (prefetch) */
4841 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4842 case 0x1f: /* nop */
018a98db
AK		 4843 break;
4844 case 0x20: /* mov cr, reg */
9dac77fa 4845 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4846 break;
6aa8b732 4847 case 0x21: /* mov from dr to reg */
9dac77fa 4848 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4849 break;
6aa8b732 4850 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 4851 if (test_cc(ctxt->b, ctxt->eflags))
4852 ctxt->dst.val = ctxt->src.val;
4853 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
4854 ctxt->op_bytes != 4)
9dac77fa 4855 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4856 break;
b2833e3c 4857 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4858 if (test_cc(ctxt->b, ctxt->eflags))
4859 jmp_rel(ctxt, ctxt->src.val);
018a98db 4860 break;
ee45b58e 4861 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4862 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4863 break;
2a7c5b8b
GC		 4864 case 0xae: /* clflush */
4865 break;
6aa8b732 4866 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4867 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4868 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4869 : (u16) ctxt->src.val;
6aa8b732 4870 break;
6aa8b732 4871 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4872 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4873 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4874 (s16) ctxt->src.val;
6aa8b732 4875 break;
a012e65a 4876 case 0xc3: /* movnti */
9dac77fa 4877 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4878 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4879 (u32) ctxt->src.val;
a012e65a 4880 break;
91269b8f
AK		 4881 default:
4882 goto cannot_emulate;
6aa8b732 4883 }
7d9ddaed 4884
0bc5eedb
BP		 4885threebyte_insn:
4886
7d9ddaed
AK		 4887 if (rc != X86EMUL_CONTINUE)
4888 goto done;
4889
6aa8b732
AK		 4890 goto writeback;
4891
4892cannot_emulate:
a0c0ab2f 4893 return EMULATION_FAILED;
6aa8b732 4894}
dd856efa
AK		 4895
4896void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4897{
4898 invalidate_registers(ctxt);
4899}
4900
4901void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4902{
4903 writeback_registers(ctxt);
4904}
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