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KVM: Activate fpu on clts
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
e99f0507
AP		 35#include "mmu.h" /* for is_long_mode() */
36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed
MG		 78/* Misc flags */
79#define No64 (1<<28)
0dc8d10f
GT		 80/* Source 2 operand type */
81#define Src2None (0<<29)
82#define Src2CL (1<<29)
83#define Src2ImmByte (2<<29)
84#define Src2One (3<<29)
a5f868bd 85#define Src2Imm16 (4<<29)
0dc8d10f 86#define Src2Mask (7<<29)
6aa8b732 87
43bb19cd 88enum {
1d6ad207 89 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 90 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 91};
92
45ed60b3 93static u32 opcode_table[256] = {
6aa8b732
AK		 94 /* 0x00 - 0x07 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 97 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 98 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 99 /* 0x08 - 0x0F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 102 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
103 ImplicitOps | Stack | No64, 0,
6aa8b732
AK		 104 /* 0x10 - 0x17 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 109 /* 0x18 - 0x1F */
110 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 113 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 114 /* 0x20 - 0x27 */
115 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 117 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 118 /* 0x28 - 0x2F */
119 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
120 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
121 0, 0, 0, 0,
122 /* 0x30 - 0x37 */
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
125 0, 0, 0, 0,
126 /* 0x38 - 0x3F */
127 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
128 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 129 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
130 0, 0,
d77a2507 131 /* 0x40 - 0x47 */
33615aa9 132 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 133 /* 0x48 - 0x4F */
33615aa9 134 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 135 /* 0x50 - 0x57 */
6e3d5dfb
AK		 136 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
137 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 138 /* 0x58 - 0x5F */
6e3d5dfb
AK		 139 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
140 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 141 /* 0x60 - 0x67 */
abcf14b5
MG		 142 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
143 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 144 0, 0, 0, 0,
145 /* 0x68 - 0x6F */
91ed7a0e 146 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 147 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
148 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 149 /* 0x70 - 0x77 */
b2833e3c
GN		 150 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 152 /* 0x78 - 0x7F */
b2833e3c
GN		 153 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
154 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 155 /* 0x80 - 0x87 */
1d6ad207
AK		 156 Group | Group1_80, Group | Group1_81,
157 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 158 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
159 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
160 /* 0x88 - 0x8F */
161 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
162 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 163 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 164 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 165 /* 0x90 - 0x97 */
166 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
167 /* 0x98 - 0x9F */
d8769fed 168 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 169 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 170 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 171 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
172 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 173 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
174 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 175 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 176 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
177 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
178 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 179 /* 0xB0 - 0xB7 */
180 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 /* 0xB8 - 0xBF */
185 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 189 /* 0xC0 - 0xC7 */
d9413cd7 190 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 191 0, ImplicitOps | Stack, 0, 0,
d9413cd7 192 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 193 /* 0xC8 - 0xCF */
e637b823 194 0, 0, 0, ImplicitOps | Stack,
d8769fed 195 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 196 /* 0xD0 - 0xD7 */
197 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
198 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
199 0, 0, 0, 0,
200 /* 0xD8 - 0xDF */
201 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 202 /* 0xE0 - 0xE7 */
a6a3034c 203 0, 0, 0, 0,
84ce66a6
GN		 204 ByteOp | SrcImmUByte, SrcImmUByte,
205 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 206 /* 0xE8 - 0xEF */
d53c4777 207 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 208 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 209 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
210 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 211 /* 0xF0 - 0xF7 */
212 0, 0, 0, 0,
7d858a19 213 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 214 /* 0xF8 - 0xFF */
b284be57 215 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 216 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 217};
218
45ed60b3 219static u32 twobyte_table[256] = {
6aa8b732 220 /* 0x00 - 0x0F */
e99f0507 221 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
651a3e29 222 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 223 /* 0x10 - 0x1F */
224 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x20 - 0x2F */
226 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
227 0, 0, 0, 0, 0, 0, 0, 0,
228 /* 0x30 - 0x3F */
e99f0507
AP		 229 ImplicitOps, 0, ImplicitOps, 0,
230 ImplicitOps, ImplicitOps, 0, 0,
231 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 232 /* 0x40 - 0x47 */
233 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 /* 0x48 - 0x4F */
238 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 /* 0x50 - 0x5F */
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
244 /* 0x60 - 0x6F */
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
246 /* 0x70 - 0x7F */
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
248 /* 0x80 - 0x8F */
b2833e3c
GN		 249 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
250 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 251 /* 0x90 - 0x9F */
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
253 /* 0xA0 - 0xA7 */
0934ac9d
MG		 254 ImplicitOps | Stack, ImplicitOps | Stack,
255 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 256 DstMem | SrcReg | Src2ImmByte | ModRM,
257 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 258 /* 0xA8 - 0xAF */
0934ac9d
MG		 259 ImplicitOps | Stack, ImplicitOps | Stack,
260 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 261 DstMem | SrcReg | Src2ImmByte | ModRM,
262 DstMem | SrcReg | Src2CL | ModRM,
263 ModRM, 0,
6aa8b732
AK		 264 /* 0xB0 - 0xB7 */
265 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 266 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 267 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
268 DstReg | SrcMem16 | ModRM | Mov,
269 /* 0xB8 - 0xBF */
038e51de 270 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 271 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
272 DstReg | SrcMem16 | ModRM | Mov,
273 /* 0xC0 - 0xCF */
a012e65a
SY		 274 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
275 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 276 /* 0xD0 - 0xDF */
277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
278 /* 0xE0 - 0xEF */
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
280 /* 0xF0 - 0xFF */
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
282};
283
45ed60b3 284static u32 group_table[] = {
1d6ad207
AK		 285 [Group1_80*8] =
286 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
287 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
288 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
289 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
290 [Group1_81*8] =
291 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
292 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
293 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
294 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
295 [Group1_82*8] =
296 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
297 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
298 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
299 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
300 [Group1_83*8] =
301 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
302 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
303 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
304 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 305 [Group1A*8] =
306 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 307 [Group3_Byte*8] =
308 ByteOp | SrcImm | DstMem | ModRM, 0,
309 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
310 0, 0, 0, 0,
311 [Group3*8] =
41afa025 312 DstMem | SrcImm | ModRM, 0,
6eb06cb2 313 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 314 0, 0, 0, 0,
fd60754e
AK		 315 [Group4*8] =
316 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
317 0, 0, 0, 0, 0, 0,
318 [Group5*8] =
d19292e4
MG		 319 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
320 SrcMem | ModRM | Stack, 0,
ef46f18e 321 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 322 [Group7*8] =
323 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 324 SrcNone | ModRM | DstMem | Mov, 0,
325 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 326};
327
45ed60b3 328static u32 group2_table[] = {
d95058a1 329 [Group7*8] =
fbce554e 330 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 331 SrcNone | ModRM | DstMem | Mov, 0,
332 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 333};
334
6aa8b732 335/* EFLAGS bit definitions. */
b1d86143
AP		 336#define EFLG_VM (1<<17)
337#define EFLG_RF (1<<16)
6aa8b732
AK		 338#define EFLG_OF (1<<11)
339#define EFLG_DF (1<<10)
b1d86143 340#define EFLG_IF (1<<9)
6aa8b732
AK		 341#define EFLG_SF (1<<7)
342#define EFLG_ZF (1<<6)
343#define EFLG_AF (1<<4)
344#define EFLG_PF (1<<2)
345#define EFLG_CF (1<<0)
346
347/*
348 * Instruction emulation:
349 * Most instructions are emulated directly via a fragment of inline assembly
350 * code. This allows us to save/restore EFLAGS and thus very easily pick up
351 * any modified flags.
352 */
353
05b3e0c2 354#if defined(CONFIG_X86_64)
6aa8b732
AK		 355#define _LO32 "k" /* force 32-bit operand */
356#define _STK "%%rsp" /* stack pointer */
357#elif defined(__i386__)
358#define _LO32 "" /* force 32-bit operand */
359#define _STK "%%esp" /* stack pointer */
360#endif
361
362/*
363 * These EFLAGS bits are restored from saved value during emulation, and
364 * any changes are written back to the saved value after emulation.
365 */
366#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
367
368/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 369#define _PRE_EFLAGS(_sav, _msk, _tmp) \
370 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
371 "movl %"_sav",%"_LO32 _tmp"; " \
372 "push %"_tmp"; " \
373 "push %"_tmp"; " \
374 "movl %"_msk",%"_LO32 _tmp"; " \
375 "andl %"_LO32 _tmp",("_STK"); " \
376 "pushf; " \
377 "notl %"_LO32 _tmp"; " \
378 "andl %"_LO32 _tmp",("_STK"); " \
379 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
380 "pop %"_tmp"; " \
381 "orl %"_LO32 _tmp",("_STK"); " \
382 "popf; " \
383 "pop %"_sav"; "
6aa8b732
AK		 384
385/* After executing instruction: write-back necessary bits in EFLAGS. */
386#define _POST_EFLAGS(_sav, _msk, _tmp) \
387 /* _sav |= EFLAGS & _msk; */ \
388 "pushf; " \
389 "pop %"_tmp"; " \
390 "andl %"_msk",%"_LO32 _tmp"; " \
391 "orl %"_LO32 _tmp",%"_sav"; "
392
dda96d8f
AK		 393#ifdef CONFIG_X86_64
394#define ON64(x) x
395#else
396#define ON64(x)
397#endif
398
6b7ad61f
AK		 399#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
400 do { \
401 __asm__ __volatile__ ( \
402 _PRE_EFLAGS("0", "4", "2") \
403 _op _suffix " %"_x"3,%1; " \
404 _POST_EFLAGS("0", "4", "2") \
405 : "=m" (_eflags), "=m" ((_dst).val), \
406 "=&r" (_tmp) \
407 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 408 } while (0)
6b7ad61f
AK		 409
410
6aa8b732
AK		 411/* Raw emulation: instruction has two explicit operands. */
412#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 413 do { \
414 unsigned long _tmp; \
415 \
416 switch ((_dst).bytes) { \
417 case 2: \
418 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
419 break; \
420 case 4: \
421 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
422 break; \
423 case 8: \
424 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
425 break; \
426 } \
6aa8b732
AK		 427 } while (0)
428
429#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
430 do { \
6b7ad61f 431 unsigned long _tmp; \
d77c26fc 432 switch ((_dst).bytes) { \
6aa8b732 433 case 1: \
6b7ad61f 434 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 435 break; \
436 default: \
437 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
438 _wx, _wy, _lx, _ly, _qx, _qy); \
439 break; \
440 } \
441 } while (0)
442
443/* Source operand is byte-sized and may be restricted to just %cl. */
444#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
445 __emulate_2op(_op, _src, _dst, _eflags, \
446 "b", "c", "b", "c", "b", "c", "b", "c")
447
448/* Source operand is byte, word, long or quad sized. */
449#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
450 __emulate_2op(_op, _src, _dst, _eflags, \
451 "b", "q", "w", "r", _LO32, "r", "", "r")
452
453/* Source operand is word, long or quad sized. */
454#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
455 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
456 "w", "r", _LO32, "r", "", "r")
457
d175226a
GT		 458/* Instruction has three operands and one operand is stored in ECX register */
459#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
460 do { \
461 unsigned long _tmp; \
462 _type _clv = (_cl).val; \
463 _type _srcv = (_src).val; \
464 _type _dstv = (_dst).val; \
465 \
466 __asm__ __volatile__ ( \
467 _PRE_EFLAGS("0", "5", "2") \
468 _op _suffix " %4,%1 \n" \
469 _POST_EFLAGS("0", "5", "2") \
470 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
471 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
472 ); \
473 \
474 (_cl).val = (unsigned long) _clv; \
475 (_src).val = (unsigned long) _srcv; \
476 (_dst).val = (unsigned long) _dstv; \
477 } while (0)
478
479#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
480 do { \
481 switch ((_dst).bytes) { \
482 case 2: \
483 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
484 "w", unsigned short); \
485 break; \
486 case 4: \
487 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
488 "l", unsigned int); \
489 break; \
490 case 8: \
491 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
492 "q", unsigned long)); \
493 break; \
494 } \
495 } while (0)
496
dda96d8f 497#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 498 do { \
499 unsigned long _tmp; \
500 \
dda96d8f
AK		 501 __asm__ __volatile__ ( \
502 _PRE_EFLAGS("0", "3", "2") \
503 _op _suffix " %1; " \
504 _POST_EFLAGS("0", "3", "2") \
505 : "=m" (_eflags), "+m" ((_dst).val), \
506 "=&r" (_tmp) \
507 : "i" (EFLAGS_MASK)); \
508 } while (0)
509
510/* Instruction has only one explicit operand (no source operand). */
511#define emulate_1op(_op, _dst, _eflags) \
512 do { \
d77c26fc 513 switch ((_dst).bytes) { \
dda96d8f
AK		 514 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
515 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
516 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
517 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 518 } \
519 } while (0)
520
6aa8b732
AK		 521/* Fetch next part of the instruction being emulated. */
522#define insn_fetch(_type, _size, _eip) \
523({ unsigned long _x; \
62266869 524 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 525 if (rc != 0) \
6aa8b732
AK		 526 goto done; \
527 (_eip) += (_size); \
528 (_type)_x; \
529})
530
ddcb2885
HH		 531static inline unsigned long ad_mask(struct decode_cache *c)
532{
533 return (1UL << (c->ad_bytes << 3)) - 1;
534}
535
6aa8b732 536/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 537static inline unsigned long
538address_mask(struct decode_cache *c, unsigned long reg)
539{
540 if (c->ad_bytes == sizeof(unsigned long))
541 return reg;
542 else
543 return reg & ad_mask(c);
544}
545
546static inline unsigned long
547register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
548{
549 return base + address_mask(c, reg);
550}
551
7a957275
HH		 552static inline void
553register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
554{
555 if (c->ad_bytes == sizeof(unsigned long))
556 *reg += inc;
557 else
558 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
559}
6aa8b732 560
7a957275
HH		 561static inline void jmp_rel(struct decode_cache *c, int rel)
562{
563 register_address_increment(c, &c->eip, rel);
564}
098c937b 565
7a5b56df
AK		 566static void set_seg_override(struct decode_cache *c, int seg)
567{
568 c->has_seg_override = true;
569 c->seg_override = seg;
570}
571
572static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
573{
574 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
575 return 0;
576
577 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
578}
579
580static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
581 struct decode_cache *c)
582{
583 if (!c->has_seg_override)
584 return 0;
585
586 return seg_base(ctxt, c->seg_override);
587}
588
589static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
590{
591 return seg_base(ctxt, VCPU_SREG_ES);
592}
593
594static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
595{
596 return seg_base(ctxt, VCPU_SREG_SS);
597}
598
62266869
AK		 599static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
600 struct x86_emulate_ops *ops,
601 unsigned long linear, u8 *dest)
602{
603 struct fetch_cache *fc = &ctxt->decode.fetch;
604 int rc;
605 int size;
606
607 if (linear < fc->start || linear >= fc->end) {
608 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
609 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
610 if (rc)
611 return rc;
612 fc->start = linear;
613 fc->end = linear + size;
614 }
615 *dest = fc->data[linear - fc->start];
616 return 0;
617}
618
619static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
620 struct x86_emulate_ops *ops,
621 unsigned long eip, void *dest, unsigned size)
622{
623 int rc = 0;
624
eb3c79e6
AK		 625 /* x86 instructions are limited to 15 bytes. */
626 if (eip + size - ctxt->decode.eip_orig > 15)
627 return X86EMUL_UNHANDLEABLE;
62266869
AK		 628 eip += ctxt->cs_base;
629 while (size--) {
630 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
631 if (rc)
632 return rc;
633 }
634 return 0;
635}
636
1e3c5cb0
RR		 637/*
638 * Given the 'reg' portion of a ModRM byte, and a register block, return a
639 * pointer into the block that addresses the relevant register.
640 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
641 */
642static void *decode_register(u8 modrm_reg, unsigned long *regs,
643 int highbyte_regs)
6aa8b732
AK		 644{
645 void *p;
646
647 p = &regs[modrm_reg];
648 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
649 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
650 return p;
651}
652
653static int read_descriptor(struct x86_emulate_ctxt *ctxt,
654 struct x86_emulate_ops *ops,
655 void *ptr,
656 u16 *size, unsigned long *address, int op_bytes)
657{
658 int rc;
659
660 if (op_bytes == 2)
661 op_bytes = 3;
662 *address = 0;
cebff02b
LV		 663 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
664 ctxt->vcpu);
6aa8b732
AK		 665 if (rc)
666 return rc;
cebff02b
LV		 667 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
668 ctxt->vcpu);
6aa8b732
AK		 669 return rc;
670}
671
bbe9abbd
NK		 672static int test_cc(unsigned int condition, unsigned int flags)
673{
674 int rc = 0;
675
676 switch ((condition & 15) >> 1) {
677 case 0: /* o */
678 rc |= (flags & EFLG_OF);
679 break;
680 case 1: /* b/c/nae */
681 rc |= (flags & EFLG_CF);
682 break;
683 case 2: /* z/e */
684 rc |= (flags & EFLG_ZF);
685 break;
686 case 3: /* be/na */
687 rc |= (flags & (EFLG_CF|EFLG_ZF));
688 break;
689 case 4: /* s */
690 rc |= (flags & EFLG_SF);
691 break;
692 case 5: /* p/pe */
693 rc |= (flags & EFLG_PF);
694 break;
695 case 7: /* le/ng */
696 rc |= (flags & EFLG_ZF);
697 /* fall through */
698 case 6: /* l/nge */
699 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
700 break;
701 }
702
703 /* Odd condition identifiers (lsb == 1) have inverted sense. */
704 return (!!rc ^ (condition & 1));
705}
706
3c118e24
AK		 707static void decode_register_operand(struct operand *op,
708 struct decode_cache *c,
3c118e24
AK		 709 int inhibit_bytereg)
710{
33615aa9 711 unsigned reg = c->modrm_reg;
9f1ef3f8 712 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 713
714 if (!(c->d & ModRM))
715 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 716 op->type = OP_REG;
717 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 718 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 719 op->val = *(u8 *)op->ptr;
720 op->bytes = 1;
721 } else {
33615aa9 722 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 723 op->bytes = c->op_bytes;
724 switch (op->bytes) {
725 case 2:
726 op->val = *(u16 *)op->ptr;
727 break;
728 case 4:
729 op->val = *(u32 *)op->ptr;
730 break;
731 case 8:
732 op->val = *(u64 *) op->ptr;
733 break;
734 }
735 }
736 op->orig_val = op->val;
737}
738
1c73ef66
AK		 739static int decode_modrm(struct x86_emulate_ctxt *ctxt,
740 struct x86_emulate_ops *ops)
741{
742 struct decode_cache *c = &ctxt->decode;
743 u8 sib;
f5b4edcd 744 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 745 int rc = 0;
746
747 if (c->rex_prefix) {
748 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
749 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
750 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
751 }
752
753 c->modrm = insn_fetch(u8, 1, c->eip);
754 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
755 c->modrm_reg |= (c->modrm & 0x38) >> 3;
756 c->modrm_rm |= (c->modrm & 0x07);
757 c->modrm_ea = 0;
758 c->use_modrm_ea = 1;
759
760 if (c->modrm_mod == 3) {
107d6d2e
AK		 761 c->modrm_ptr = decode_register(c->modrm_rm,
762 c->regs, c->d & ByteOp);
763 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 764 return rc;
765 }
766
767 if (c->ad_bytes == 2) {
768 unsigned bx = c->regs[VCPU_REGS_RBX];
769 unsigned bp = c->regs[VCPU_REGS_RBP];
770 unsigned si = c->regs[VCPU_REGS_RSI];
771 unsigned di = c->regs[VCPU_REGS_RDI];
772
773 /* 16-bit ModR/M decode. */
774 switch (c->modrm_mod) {
775 case 0:
776 if (c->modrm_rm == 6)
777 c->modrm_ea += insn_fetch(u16, 2, c->eip);
778 break;
779 case 1:
780 c->modrm_ea += insn_fetch(s8, 1, c->eip);
781 break;
782 case 2:
783 c->modrm_ea += insn_fetch(u16, 2, c->eip);
784 break;
785 }
786 switch (c->modrm_rm) {
787 case 0:
788 c->modrm_ea += bx + si;
789 break;
790 case 1:
791 c->modrm_ea += bx + di;
792 break;
793 case 2:
794 c->modrm_ea += bp + si;
795 break;
796 case 3:
797 c->modrm_ea += bp + di;
798 break;
799 case 4:
800 c->modrm_ea += si;
801 break;
802 case 5:
803 c->modrm_ea += di;
804 break;
805 case 6:
806 if (c->modrm_mod != 0)
807 c->modrm_ea += bp;
808 break;
809 case 7:
810 c->modrm_ea += bx;
811 break;
812 }
813 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
814 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 815 if (!c->has_seg_override)
816 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 817 c->modrm_ea = (u16)c->modrm_ea;
818 } else {
819 /* 32/64-bit ModR/M decode. */
84411d85 820 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 821 sib = insn_fetch(u8, 1, c->eip);
822 index_reg |= (sib >> 3) & 7;
823 base_reg |= sib & 7;
824 scale = sib >> 6;
825
dc71d0f1
AK		 826 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
827 c->modrm_ea += insn_fetch(s32, 4, c->eip);
828 else
1c73ef66 829 c->modrm_ea += c->regs[base_reg];
dc71d0f1 830 if (index_reg != 4)
1c73ef66 831 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 832 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
833 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 834 c->rip_relative = 1;
84411d85 835 } else
1c73ef66 836 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 837 switch (c->modrm_mod) {
838 case 0:
839 if (c->modrm_rm == 5)
840 c->modrm_ea += insn_fetch(s32, 4, c->eip);
841 break;
842 case 1:
843 c->modrm_ea += insn_fetch(s8, 1, c->eip);
844 break;
845 case 2:
846 c->modrm_ea += insn_fetch(s32, 4, c->eip);
847 break;
848 }
849 }
1c73ef66
AK		 850done:
851 return rc;
852}
853
854static int decode_abs(struct x86_emulate_ctxt *ctxt,
855 struct x86_emulate_ops *ops)
856{
857 struct decode_cache *c = &ctxt->decode;
858 int rc = 0;
859
860 switch (c->ad_bytes) {
861 case 2:
862 c->modrm_ea = insn_fetch(u16, 2, c->eip);
863 break;
864 case 4:
865 c->modrm_ea = insn_fetch(u32, 4, c->eip);
866 break;
867 case 8:
868 c->modrm_ea = insn_fetch(u64, 8, c->eip);
869 break;
870 }
871done:
872 return rc;
873}
874
6aa8b732 875int
8b4caf66 876x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 877{
e4e03ded 878 struct decode_cache *c = &ctxt->decode;
6aa8b732 879 int rc = 0;
6aa8b732 880 int mode = ctxt->mode;
e09d082c 881 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 882
883 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 884
e4e03ded 885 memset(c, 0, sizeof(struct decode_cache));
eb3c79e6 886 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
7a5b56df 887 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 888 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 889
890 switch (mode) {
891 case X86EMUL_MODE_REAL:
892 case X86EMUL_MODE_PROT16:
f21b8bf4 893 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 894 break;
895 case X86EMUL_MODE_PROT32:
f21b8bf4 896 def_op_bytes = def_ad_bytes = 4;
6aa8b732 897 break;
05b3e0c2 898#ifdef CONFIG_X86_64
6aa8b732 899 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 900 def_op_bytes = 4;
901 def_ad_bytes = 8;
6aa8b732
AK		 902 break;
903#endif
904 default:
905 return -1;
906 }
907
f21b8bf4
AK		 908 c->op_bytes = def_op_bytes;
909 c->ad_bytes = def_ad_bytes;
910
6aa8b732 911 /* Legacy prefixes. */
b4c6abfe 912 for (;;) {
e4e03ded 913 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 914 case 0x66: /* operand-size override */
f21b8bf4
AK		 915 /* switch between 2/4 bytes */
916 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 917 break;
918 case 0x67: /* address-size override */
919 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 920 /* switch between 4/8 bytes */
f21b8bf4 921 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 922 else
e4e03ded 923 /* switch between 2/4 bytes */
f21b8bf4 924 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 925 break;
7a5b56df 926 case 0x26: /* ES override */
6aa8b732 927 case 0x2e: /* CS override */
7a5b56df 928 case 0x36: /* SS override */
6aa8b732 929 case 0x3e: /* DS override */
7a5b56df 930 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 931 break;
932 case 0x64: /* FS override */
6aa8b732 933 case 0x65: /* GS override */
7a5b56df 934 set_seg_override(c, c->b & 7);
6aa8b732 935 break;
b4c6abfe
LV		 936 case 0x40 ... 0x4f: /* REX */
937 if (mode != X86EMUL_MODE_PROT64)
938 goto done_prefixes;
33615aa9 939 c->rex_prefix = c->b;
b4c6abfe 940 continue;
6aa8b732 941 case 0xf0: /* LOCK */
e4e03ded 942 c->lock_prefix = 1;
6aa8b732 943 break;
ae6200ba 944 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 945 c->rep_prefix = REPNE_PREFIX;
946 break;
6aa8b732 947 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 948 c->rep_prefix = REPE_PREFIX;
6aa8b732 949 break;
6aa8b732
AK		 950 default:
951 goto done_prefixes;
952 }
b4c6abfe
LV		 953
954 /* Any legacy prefix after a REX prefix nullifies its effect. */
955
33615aa9 956 c->rex_prefix = 0;
6aa8b732
AK		 957 }
958
959done_prefixes:
960
961 /* REX prefix. */
1c73ef66 962 if (c->rex_prefix)
33615aa9 963 if (c->rex_prefix & 8)
e4e03ded 964 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 965
966 /* Opcode byte(s). */
e4e03ded
LV		 967 c->d = opcode_table[c->b];
968 if (c->d == 0) {
6aa8b732 969 /* Two-byte opcode? */
e4e03ded
LV		 970 if (c->b == 0x0f) {
971 c->twobyte = 1;
972 c->b = insn_fetch(u8, 1, c->eip);
973 c->d = twobyte_table[c->b];
6aa8b732 974 }
e09d082c 975 }
6aa8b732 976
d8769fed
MG		 977 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
978 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
979 return -1;
980 }
981
e09d082c
AK		 982 if (c->d & Group) {
983 group = c->d & GroupMask;
984 c->modrm = insn_fetch(u8, 1, c->eip);
985 --c->eip;
986
987 group = (group << 3) + ((c->modrm >> 3) & 7);
988 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
989 c->d = group2_table[group];
990 else
991 c->d = group_table[group];
992 }
993
994 /* Unrecognised? */
995 if (c->d == 0) {
996 DPRINTF("Cannot emulate %02x\n", c->b);
997 return -1;
6aa8b732
AK		 998 }
999
6e3d5dfb
AK		 1000 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1001 c->op_bytes = 8;
1002
6aa8b732 1003 /* ModRM and SIB bytes. */
1c73ef66
AK		 1004 if (c->d & ModRM)
1005 rc = decode_modrm(ctxt, ops);
1006 else if (c->d & MemAbs)
1007 rc = decode_abs(ctxt, ops);
1008 if (rc)
1009 goto done;
6aa8b732 1010
7a5b56df
AK		 1011 if (!c->has_seg_override)
1012 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1013
7a5b56df
AK		 1014 if (!(!c->twobyte && c->b == 0x8d))
1015 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1016
1017 if (c->ad_bytes != 8)
1018 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1019 /*
1020 * Decode and fetch the source operand: register, memory
1021 * or immediate.
1022 */
e4e03ded 1023 switch (c->d & SrcMask) {
6aa8b732
AK		 1024 case SrcNone:
1025 break;
1026 case SrcReg:
9f1ef3f8 1027 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1028 break;
1029 case SrcMem16:
e4e03ded 1030 c->src.bytes = 2;
6aa8b732
AK		 1031 goto srcmem_common;
1032 case SrcMem32:
e4e03ded 1033 c->src.bytes = 4;
6aa8b732
AK		 1034 goto srcmem_common;
1035 case SrcMem:
e4e03ded
LV		 1036 c->src.bytes = (c->d & ByteOp) ? 1 :
1037 c->op_bytes;
b85b9ee9 1038 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1039 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1040 break;
d77c26fc 1041 srcmem_common:
4e62417b
AJ		 1042 /*
1043 * For instructions with a ModR/M byte, switch to register
1044 * access if Mod = 3.
1045 */
e4e03ded
LV		 1046 if ((c->d & ModRM) && c->modrm_mod == 3) {
1047 c->src.type = OP_REG;
66b85505 1048 c->src.val = c->modrm_val;
107d6d2e 1049 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1050 break;
1051 }
e4e03ded 1052 c->src.type = OP_MEM;
6aa8b732
AK		 1053 break;
1054 case SrcImm:
c9eaf20f 1055 case SrcImmU:
e4e03ded
LV		 1056 c->src.type = OP_IMM;
1057 c->src.ptr = (unsigned long *)c->eip;
1058 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1059 if (c->src.bytes == 8)
1060 c->src.bytes = 4;
6aa8b732 1061 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1062 switch (c->src.bytes) {
6aa8b732 1063 case 1:
e4e03ded 1064 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1065 break;
1066 case 2:
e4e03ded 1067 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1068 break;
1069 case 4:
e4e03ded 1070 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1071 break;
1072 }
c9eaf20f
AK		 1073 if ((c->d & SrcMask) == SrcImmU) {
1074 switch (c->src.bytes) {
1075 case 1:
1076 c->src.val &= 0xff;
1077 break;
1078 case 2:
1079 c->src.val &= 0xffff;
1080 break;
1081 case 4:
1082 c->src.val &= 0xffffffff;
1083 break;
1084 }
1085 }
6aa8b732
AK		 1086 break;
1087 case SrcImmByte:
341de7e3 1088 case SrcImmUByte:
e4e03ded
LV		 1089 c->src.type = OP_IMM;
1090 c->src.ptr = (unsigned long *)c->eip;
1091 c->src.bytes = 1;
341de7e3
GN		 1092 if ((c->d & SrcMask) == SrcImmByte)
1093 c->src.val = insn_fetch(s8, 1, c->eip);
1094 else
1095 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1096 break;
bfcadf83
GT		 1097 case SrcOne:
1098 c->src.bytes = 1;
1099 c->src.val = 1;
1100 break;
6aa8b732
AK		 1101 }
1102
0dc8d10f
GT		 1103 /*
1104 * Decode and fetch the second source operand: register, memory
1105 * or immediate.
1106 */
1107 switch (c->d & Src2Mask) {
1108 case Src2None:
1109 break;
1110 case Src2CL:
1111 c->src2.bytes = 1;
1112 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1113 break;
1114 case Src2ImmByte:
1115 c->src2.type = OP_IMM;
1116 c->src2.ptr = (unsigned long *)c->eip;
1117 c->src2.bytes = 1;
1118 c->src2.val = insn_fetch(u8, 1, c->eip);
1119 break;
a5f868bd
GN		 1120 case Src2Imm16:
1121 c->src2.type = OP_IMM;
1122 c->src2.ptr = (unsigned long *)c->eip;
1123 c->src2.bytes = 2;
1124 c->src2.val = insn_fetch(u16, 2, c->eip);
1125 break;
0dc8d10f
GT		 1126 case Src2One:
1127 c->src2.bytes = 1;
1128 c->src2.val = 1;
1129 break;
1130 }
1131
038e51de 1132 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1133 switch (c->d & DstMask) {
038e51de
AK		 1134 case ImplicitOps:
1135 /* Special instructions do their own operand decoding. */
8b4caf66 1136 return 0;
038e51de 1137 case DstReg:
9f1ef3f8 1138 decode_register_operand(&c->dst, c,
3c118e24 1139 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1140 break;
1141 case DstMem:
e4e03ded 1142 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1143 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1144 c->dst.type = OP_REG;
66b85505 1145 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1146 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1147 break;
1148 }
8b4caf66
LV		 1149 c->dst.type = OP_MEM;
1150 break;
9c9fddd0
GT		 1151 case DstAcc:
1152 c->dst.type = OP_REG;
1153 c->dst.bytes = c->op_bytes;
1154 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1155 switch (c->op_bytes) {
1156 case 1:
1157 c->dst.val = *(u8 *)c->dst.ptr;
1158 break;
1159 case 2:
1160 c->dst.val = *(u16 *)c->dst.ptr;
1161 break;
1162 case 4:
1163 c->dst.val = *(u32 *)c->dst.ptr;
1164 break;
1165 }
1166 c->dst.orig_val = c->dst.val;
1167 break;
8b4caf66
LV		 1168 }
1169
f5b4edcd
AK		 1170 if (c->rip_relative)
1171 c->modrm_ea += c->eip;
1172
8b4caf66
LV		 1173done:
1174 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1175}
1176
8cdbd2c9
LV		 1177static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1178{
1179 struct decode_cache *c = &ctxt->decode;
1180
1181 c->dst.type = OP_MEM;
1182 c->dst.bytes = c->op_bytes;
1183 c->dst.val = c->src.val;
7a957275 1184 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1185 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1186 c->regs[VCPU_REGS_RSP]);
1187}
1188
faa5a3ae 1189static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1190 struct x86_emulate_ops *ops,
1191 void *dest, int len)
8cdbd2c9
LV		 1192{
1193 struct decode_cache *c = &ctxt->decode;
1194 int rc;
1195
781d0edc
AK		 1196 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1197 c->regs[VCPU_REGS_RSP]),
350f69dc 1198 dest, len, ctxt->vcpu);
b60d513c 1199 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1200 return rc;
1201
350f69dc 1202 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1203 return rc;
1204}
8cdbd2c9 1205
0934ac9d
MG		 1206static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1207{
1208 struct decode_cache *c = &ctxt->decode;
1209 struct kvm_segment segment;
1210
1211 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1212
1213 c->src.val = segment.selector;
1214 emulate_push(ctxt);
1215}
1216
1217static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1218 struct x86_emulate_ops *ops, int seg)
1219{
1220 struct decode_cache *c = &ctxt->decode;
1221 unsigned long selector;
1222 int rc;
1223
1224 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1225 if (rc != 0)
1226 return rc;
1227
1228 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1229 return rc;
1230}
1231
abcf14b5
MG		 1232static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1233{
1234 struct decode_cache *c = &ctxt->decode;
1235 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1236 int reg = VCPU_REGS_RAX;
1237
1238 while (reg <= VCPU_REGS_RDI) {
1239 (reg == VCPU_REGS_RSP) ?
1240 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1241
1242 emulate_push(ctxt);
1243 ++reg;
1244 }
1245}
1246
1247static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1248 struct x86_emulate_ops *ops)
1249{
1250 struct decode_cache *c = &ctxt->decode;
1251 int rc = 0;
1252 int reg = VCPU_REGS_RDI;
1253
1254 while (reg >= VCPU_REGS_RAX) {
1255 if (reg == VCPU_REGS_RSP) {
1256 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1257 c->op_bytes);
1258 --reg;
1259 }
1260
1261 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1262 if (rc != 0)
1263 break;
1264 --reg;
1265 }
1266 return rc;
1267}
1268
faa5a3ae
AK		 1269static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1270 struct x86_emulate_ops *ops)
1271{
1272 struct decode_cache *c = &ctxt->decode;
1273 int rc;
1274
350f69dc 1275 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1276 if (rc != 0)
1277 return rc;
8cdbd2c9
LV		 1278 return 0;
1279}
1280
05f086f8 1281static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1282{
05f086f8 1283 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1284 switch (c->modrm_reg) {
1285 case 0: /* rol */
05f086f8 1286 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1287 break;
1288 case 1: /* ror */
05f086f8 1289 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1290 break;
1291 case 2: /* rcl */
05f086f8 1292 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1293 break;
1294 case 3: /* rcr */
05f086f8 1295 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1296 break;
1297 case 4: /* sal/shl */
1298 case 6: /* sal/shl */
05f086f8 1299 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1300 break;
1301 case 5: /* shr */
05f086f8 1302 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1303 break;
1304 case 7: /* sar */
05f086f8 1305 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1306 break;
1307 }
1308}
1309
1310static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1311 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1312{
1313 struct decode_cache *c = &ctxt->decode;
1314 int rc = 0;
1315
1316 switch (c->modrm_reg) {
1317 case 0 ... 1: /* test */
05f086f8 1318 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1319 break;
1320 case 2: /* not */
1321 c->dst.val = ~c->dst.val;
1322 break;
1323 case 3: /* neg */
05f086f8 1324 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1325 break;
1326 default:
1327 DPRINTF("Cannot emulate %02x\n", c->b);
1328 rc = X86EMUL_UNHANDLEABLE;
1329 break;
1330 }
8cdbd2c9
LV		 1331 return rc;
1332}
1333
1334static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1335 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1336{
1337 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1338
1339 switch (c->modrm_reg) {
1340 case 0: /* inc */
05f086f8 1341 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1342 break;
1343 case 1: /* dec */
05f086f8 1344 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1345 break;
d19292e4
MG		 1346 case 2: /* call near abs */ {
1347 long int old_eip;
1348 old_eip = c->eip;
1349 c->eip = c->src.val;
1350 c->src.val = old_eip;
1351 emulate_push(ctxt);
1352 break;
1353 }
8cdbd2c9 1354 case 4: /* jmp abs */
fd60754e 1355 c->eip = c->src.val;
8cdbd2c9
LV		 1356 break;
1357 case 6: /* push */
fd60754e 1358 emulate_push(ctxt);
8cdbd2c9 1359 break;
8cdbd2c9
LV		 1360 }
1361 return 0;
1362}
1363
1364static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1365 struct x86_emulate_ops *ops,
e8d8d7fe 1366 unsigned long memop)
8cdbd2c9
LV		 1367{
1368 struct decode_cache *c = &ctxt->decode;
1369 u64 old, new;
1370 int rc;
1371
e8d8d7fe 1372 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1373 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1374 return rc;
1375
1376 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1377 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1378
1379 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1380 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1381 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1382
1383 } else {
1384 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1385 (u32) c->regs[VCPU_REGS_RBX];
1386
e8d8d7fe 1387 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1388 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1389 return rc;
05f086f8 1390 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1391 }
1392 return 0;
1393}
1394
a77ab5ea
AK		 1395static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1396 struct x86_emulate_ops *ops)
1397{
1398 struct decode_cache *c = &ctxt->decode;
1399 int rc;
1400 unsigned long cs;
1401
1402 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1403 if (rc)
1404 return rc;
1405 if (c->op_bytes == 4)
1406 c->eip = (u32)c->eip;
1407 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1408 if (rc)
1409 return rc;
1410 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1411 return rc;
1412}
1413
8cdbd2c9
LV		 1414static inline int writeback(struct x86_emulate_ctxt *ctxt,
1415 struct x86_emulate_ops *ops)
1416{
1417 int rc;
1418 struct decode_cache *c = &ctxt->decode;
1419
1420 switch (c->dst.type) {
1421 case OP_REG:
1422 /* The 4-byte case *is* correct:
1423 * in 64-bit mode we zero-extend.
1424 */
1425 switch (c->dst.bytes) {
1426 case 1:
1427 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1428 break;
1429 case 2:
1430 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1431 break;
1432 case 4:
1433 *c->dst.ptr = (u32)c->dst.val;
1434 break; /* 64b: zero-ext */
1435 case 8:
1436 *c->dst.ptr = c->dst.val;
1437 break;
1438 }
1439 break;
1440 case OP_MEM:
1441 if (c->lock_prefix)
1442 rc = ops->cmpxchg_emulated(
1443 (unsigned long)c->dst.ptr,
1444 &c->dst.orig_val,
1445 &c->dst.val,
1446 c->dst.bytes,
1447 ctxt->vcpu);
1448 else
1449 rc = ops->write_emulated(
1450 (unsigned long)c->dst.ptr,
1451 &c->dst.val,
1452 c->dst.bytes,
1453 ctxt->vcpu);
b60d513c 1454 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1455 return rc;
a01af5ec
LV		 1456 break;
1457 case OP_NONE:
1458 /* no writeback */
1459 break;
8cdbd2c9
LV		 1460 default:
1461 break;
1462 }
1463 return 0;
1464}
1465
a3f9d398 1466static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1467{
1468 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1469 /*
1470 * an sti; sti; sequence only disable interrupts for the first
1471 * instruction. So, if the last instruction, be it emulated or
1472 * not, left the system with the INT_STI flag enabled, it
1473 * means that the last instruction is an sti. We should not
1474 * leave the flag on in this case. The same goes for mov ss
1475 */
1476 if (!(int_shadow & mask))
1477 ctxt->interruptibility = mask;
1478}
1479
e66bb2cc
AP		 1480static inline void
1481setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1482 struct kvm_segment *cs, struct kvm_segment *ss)
1483{
1484 memset(cs, 0, sizeof(struct kvm_segment));
1485 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1486 memset(ss, 0, sizeof(struct kvm_segment));
1487
1488 cs->l = 0; /* will be adjusted later */
1489 cs->base = 0; /* flat segment */
1490 cs->g = 1; /* 4kb granularity */
1491 cs->limit = 0xffffffff; /* 4GB limit */
1492 cs->type = 0x0b; /* Read, Execute, Accessed */
1493 cs->s = 1;
1494 cs->dpl = 0; /* will be adjusted later */
1495 cs->present = 1;
1496 cs->db = 1;
1497
1498 ss->unusable = 0;
1499 ss->base = 0; /* flat segment */
1500 ss->limit = 0xffffffff; /* 4GB limit */
1501 ss->g = 1; /* 4kb granularity */
1502 ss->s = 1;
1503 ss->type = 0x03; /* Read/Write, Accessed */
1504 ss->db = 1; /* 32bit stack segment */
1505 ss->dpl = 0;
1506 ss->present = 1;
1507}
1508
1509static int
1510emulate_syscall(struct x86_emulate_ctxt *ctxt)
1511{
1512 struct decode_cache *c = &ctxt->decode;
1513 struct kvm_segment cs, ss;
1514 u64 msr_data;
1515
1516 /* syscall is not available in real mode */
1517 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
4d4ec087 1518 || !kvm_read_cr0_bits(ctxt->vcpu, X86_CR0_PE))
e66bb2cc
AP		 1519 return -1;
1520
1521 setup_syscalls_segments(ctxt, &cs, &ss);
1522
1523 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1524 msr_data >>= 32;
1525 cs.selector = (u16)(msr_data & 0xfffc);
1526 ss.selector = (u16)(msr_data + 8);
1527
1528 if (is_long_mode(ctxt->vcpu)) {
1529 cs.db = 0;
1530 cs.l = 1;
1531 }
1532 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1533 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1534
1535 c->regs[VCPU_REGS_RCX] = c->eip;
1536 if (is_long_mode(ctxt->vcpu)) {
1537#ifdef CONFIG_X86_64
1538 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1539
1540 kvm_x86_ops->get_msr(ctxt->vcpu,
1541 ctxt->mode == X86EMUL_MODE_PROT64 ?
1542 MSR_LSTAR : MSR_CSTAR, &msr_data);
1543 c->eip = msr_data;
1544
1545 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1546 ctxt->eflags &= ~(msr_data | EFLG_RF);
1547#endif
1548 } else {
1549 /* legacy mode */
1550 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1551 c->eip = (u32)msr_data;
1552
1553 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1554 }
1555
1556 return 0;
1557}
1558
8c604352
AP		 1559static int
1560emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1561{
1562 struct decode_cache *c = &ctxt->decode;
1563 struct kvm_segment cs, ss;
1564 u64 msr_data;
1565
1566 /* inject #UD if LOCK prefix is used */
1567 if (c->lock_prefix)
1568 return -1;
1569
1570 /* inject #GP if in real mode or paging is disabled */
1571 if (ctxt->mode == X86EMUL_MODE_REAL ||
4d4ec087 1572 !kvm_read_cr0_bits(ctxt->vcpu, X86_CR0_PE)) {
8c604352
AP		 1573 kvm_inject_gp(ctxt->vcpu, 0);
1574 return -1;
1575 }
1576
1577 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1578 * Therefore, we inject an #UD.
1579 */
1580 if (ctxt->mode == X86EMUL_MODE_PROT64)
1581 return -1;
1582
1583 setup_syscalls_segments(ctxt, &cs, &ss);
1584
1585 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1586 switch (ctxt->mode) {
1587 case X86EMUL_MODE_PROT32:
1588 if ((msr_data & 0xfffc) == 0x0) {
1589 kvm_inject_gp(ctxt->vcpu, 0);
1590 return -1;
1591 }
1592 break;
1593 case X86EMUL_MODE_PROT64:
1594 if (msr_data == 0x0) {
1595 kvm_inject_gp(ctxt->vcpu, 0);
1596 return -1;
1597 }
1598 break;
1599 }
1600
1601 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1602 cs.selector = (u16)msr_data;
1603 cs.selector &= ~SELECTOR_RPL_MASK;
1604 ss.selector = cs.selector + 8;
1605 ss.selector &= ~SELECTOR_RPL_MASK;
1606 if (ctxt->mode == X86EMUL_MODE_PROT64
1607 || is_long_mode(ctxt->vcpu)) {
1608 cs.db = 0;
1609 cs.l = 1;
1610 }
1611
1612 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1613 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1614
1615 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1616 c->eip = msr_data;
1617
1618 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1619 c->regs[VCPU_REGS_RSP] = msr_data;
1620
1621 return 0;
1622}
1623
4668f050
AP		 1624static int
1625emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1626{
1627 struct decode_cache *c = &ctxt->decode;
1628 struct kvm_segment cs, ss;
1629 u64 msr_data;
1630 int usermode;
1631
1632 /* inject #UD if LOCK prefix is used */
1633 if (c->lock_prefix)
1634 return -1;
1635
1636 /* inject #GP if in real mode or paging is disabled */
1637 if (ctxt->mode == X86EMUL_MODE_REAL
4d4ec087 1638 || !kvm_read_cr0_bits(ctxt->vcpu, X86_CR0_PE)) {
4668f050
AP		 1639 kvm_inject_gp(ctxt->vcpu, 0);
1640 return -1;
1641 }
1642
1643 /* sysexit must be called from CPL 0 */
1644 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1645 kvm_inject_gp(ctxt->vcpu, 0);
1646 return -1;
1647 }
1648
1649 setup_syscalls_segments(ctxt, &cs, &ss);
1650
1651 if ((c->rex_prefix & 0x8) != 0x0)
1652 usermode = X86EMUL_MODE_PROT64;
1653 else
1654 usermode = X86EMUL_MODE_PROT32;
1655
1656 cs.dpl = 3;
1657 ss.dpl = 3;
1658 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1659 switch (usermode) {
1660 case X86EMUL_MODE_PROT32:
1661 cs.selector = (u16)(msr_data + 16);
1662 if ((msr_data & 0xfffc) == 0x0) {
1663 kvm_inject_gp(ctxt->vcpu, 0);
1664 return -1;
1665 }
1666 ss.selector = (u16)(msr_data + 24);
1667 break;
1668 case X86EMUL_MODE_PROT64:
1669 cs.selector = (u16)(msr_data + 32);
1670 if (msr_data == 0x0) {
1671 kvm_inject_gp(ctxt->vcpu, 0);
1672 return -1;
1673 }
1674 ss.selector = cs.selector + 8;
1675 cs.db = 0;
1676 cs.l = 1;
1677 break;
1678 }
1679 cs.selector |= SELECTOR_RPL_MASK;
1680 ss.selector |= SELECTOR_RPL_MASK;
1681
1682 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1683 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1684
1685 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1686 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1687
1688 return 0;
1689}
1690
8b4caf66 1691int
1be3aa47 1692x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1693{
e8d8d7fe 1694 unsigned long memop = 0;
8b4caf66 1695 u64 msr_data;
3427318f 1696 unsigned long saved_eip = 0;
8b4caf66 1697 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1698 unsigned int port;
1699 int io_dir_in;
1be3aa47 1700 int rc = 0;
8b4caf66 1701
310b5d30
GC		 1702 ctxt->interruptibility = 0;
1703
3427318f
LV		 1704 /* Shadow copy of register state. Committed on successful emulation.
1705 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1706 * modify them.
1707 */
1708
ad312c7c 1709 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1710 saved_eip = c->eip;
1711
c7e75a3d 1712 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1713 memop = c->modrm_ea;
8b4caf66 1714
b9fa9d6b
AK		 1715 if (c->rep_prefix && (c->d & String)) {
1716 /* All REP prefixes have the same first termination condition */
1717 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1718 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1719 goto done;
1720 }
1721 /* The second termination condition only applies for REPE
1722 * and REPNE. Test if the repeat string operation prefix is
1723 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1724 * corresponding termination condition according to:
1725 * - if REPE/REPZ and ZF = 0 then done
1726 * - if REPNE/REPNZ and ZF = 1 then done
1727 */
1728 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1729 (c->b == 0xae) || (c->b == 0xaf)) {
1730 if ((c->rep_prefix == REPE_PREFIX) &&
1731 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1732 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1733 goto done;
1734 }
1735 if ((c->rep_prefix == REPNE_PREFIX) &&
1736 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1737 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1738 goto done;
1739 }
1740 }
1741 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1742 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1743 }
1744
8b4caf66 1745 if (c->src.type == OP_MEM) {
e8d8d7fe 1746 c->src.ptr = (unsigned long *)memop;
8b4caf66 1747 c->src.val = 0;
d77c26fc
MD		 1748 rc = ops->read_emulated((unsigned long)c->src.ptr,
1749 &c->src.val,
1750 c->src.bytes,
1751 ctxt->vcpu);
b60d513c 1752 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 1753 goto done;
1754 c->src.orig_val = c->src.val;
1755 }
1756
1757 if ((c->d & DstMask) == ImplicitOps)
1758 goto special_insn;
1759
1760
1761 if (c->dst.type == OP_MEM) {
e8d8d7fe 1762 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1763 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1764 c->dst.val = 0;
e4e03ded
LV		 1765 if (c->d & BitOp) {
1766 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1767
e4e03ded
LV		 1768 c->dst.ptr = (void *)c->dst.ptr +
1769 (c->src.val & mask) / 8;
038e51de 1770 }
b60d513c
TY		 1771 if (!(c->d & Mov)) {
1772 /* optimisation - avoid slow emulated read */
1773 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1774 &c->dst.val,
1775 c->dst.bytes,
1776 ctxt->vcpu);
1777 if (rc != X86EMUL_CONTINUE)
1778 goto done;
1779 }
038e51de 1780 }
e4e03ded 1781 c->dst.orig_val = c->dst.val;
038e51de 1782
018a98db
AK		 1783special_insn:
1784
e4e03ded 1785 if (c->twobyte)
6aa8b732
AK		 1786 goto twobyte_insn;
1787
e4e03ded 1788 switch (c->b) {
6aa8b732
AK		 1789 case 0x00 ... 0x05:
1790 add: /* add */
05f086f8 1791 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1792 break;
0934ac9d 1793 case 0x06: /* push es */
0934ac9d
MG		 1794 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1795 break;
1796 case 0x07: /* pop es */
0934ac9d
MG		 1797 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1798 if (rc != 0)
1799 goto done;
1800 break;
6aa8b732
AK		 1801 case 0x08 ... 0x0d:
1802 or: /* or */
05f086f8 1803 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1804 break;
0934ac9d 1805 case 0x0e: /* push cs */
0934ac9d
MG		 1806 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1807 break;
6aa8b732
AK		 1808 case 0x10 ... 0x15:
1809 adc: /* adc */
05f086f8 1810 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1811 break;
0934ac9d 1812 case 0x16: /* push ss */
0934ac9d
MG		 1813 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1814 break;
1815 case 0x17: /* pop ss */
0934ac9d
MG		 1816 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1817 if (rc != 0)
1818 goto done;
1819 break;
6aa8b732
AK		 1820 case 0x18 ... 0x1d:
1821 sbb: /* sbb */
05f086f8 1822 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1823 break;
0934ac9d 1824 case 0x1e: /* push ds */
0934ac9d
MG		 1825 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1826 break;
1827 case 0x1f: /* pop ds */
0934ac9d
MG		 1828 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1829 if (rc != 0)
1830 goto done;
1831 break;
aa3a816b 1832 case 0x20 ... 0x25:
6aa8b732 1833 and: /* and */
05f086f8 1834 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1835 break;
1836 case 0x28 ... 0x2d:
1837 sub: /* sub */
05f086f8 1838 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1839 break;
1840 case 0x30 ... 0x35:
1841 xor: /* xor */
05f086f8 1842 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1843 break;
1844 case 0x38 ... 0x3d:
1845 cmp: /* cmp */
05f086f8 1846 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1847 break;
33615aa9
AK		 1848 case 0x40 ... 0x47: /* inc r16/r32 */
1849 emulate_1op("inc", c->dst, ctxt->eflags);
1850 break;
1851 case 0x48 ... 0x4f: /* dec r16/r32 */
1852 emulate_1op("dec", c->dst, ctxt->eflags);
1853 break;
1854 case 0x50 ... 0x57: /* push reg */
2786b014 1855 emulate_push(ctxt);
33615aa9
AK		 1856 break;
1857 case 0x58 ... 0x5f: /* pop reg */
1858 pop_instruction:
350f69dc 1859 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1860 if (rc != 0)
33615aa9 1861 goto done;
33615aa9 1862 break;
abcf14b5
MG		 1863 case 0x60: /* pusha */
1864 emulate_pusha(ctxt);
1865 break;
1866 case 0x61: /* popa */
1867 rc = emulate_popa(ctxt, ops);
1868 if (rc != 0)
1869 goto done;
1870 break;
6aa8b732 1871 case 0x63: /* movsxd */
8b4caf66 1872 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1873 goto cannot_emulate;
e4e03ded 1874 c->dst.val = (s32) c->src.val;
6aa8b732 1875 break;
91ed7a0e 1876 case 0x68: /* push imm */
018a98db 1877 case 0x6a: /* push imm8 */
018a98db
AK		 1878 emulate_push(ctxt);
1879 break;
1880 case 0x6c: /* insb */
1881 case 0x6d: /* insw/insd */
851ba692 1882 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1883 1,
1884 (c->d & ByteOp) ? 1 : c->op_bytes,
1885 c->rep_prefix ?
e4706772 1886 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1887 (ctxt->eflags & EFLG_DF),
7a5b56df 1888 register_address(c, es_base(ctxt),
018a98db
AK		 1889 c->regs[VCPU_REGS_RDI]),
1890 c->rep_prefix,
1891 c->regs[VCPU_REGS_RDX]) == 0) {
1892 c->eip = saved_eip;
1893 return -1;
1894 }
1895 return 0;
1896 case 0x6e: /* outsb */
1897 case 0x6f: /* outsw/outsd */
851ba692 1898 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1899 0,
1900 (c->d & ByteOp) ? 1 : c->op_bytes,
1901 c->rep_prefix ?
e4706772 1902 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1903 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1904 register_address(c,
1905 seg_override_base(ctxt, c),
018a98db
AK		 1906 c->regs[VCPU_REGS_RSI]),
1907 c->rep_prefix,
1908 c->regs[VCPU_REGS_RDX]) == 0) {
1909 c->eip = saved_eip;
1910 return -1;
1911 }
1912 return 0;
b2833e3c 1913 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1914 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1915 jmp_rel(c, c->src.val);
018a98db 1916 break;
6aa8b732 1917 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1918 switch (c->modrm_reg) {
6aa8b732
AK		 1919 case 0:
1920 goto add;
1921 case 1:
1922 goto or;
1923 case 2:
1924 goto adc;
1925 case 3:
1926 goto sbb;
1927 case 4:
1928 goto and;
1929 case 5:
1930 goto sub;
1931 case 6:
1932 goto xor;
1933 case 7:
1934 goto cmp;
1935 }
1936 break;
1937 case 0x84 ... 0x85:
05f086f8 1938 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1939 break;
1940 case 0x86 ... 0x87: /* xchg */
b13354f8 1941 xchg:
6aa8b732 1942 /* Write back the register source. */
e4e03ded 1943 switch (c->dst.bytes) {
6aa8b732 1944 case 1:
e4e03ded 1945 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1946 break;
1947 case 2:
e4e03ded 1948 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1949 break;
1950 case 4:
e4e03ded 1951 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1952 break; /* 64b reg: zero-extend */
1953 case 8:
e4e03ded 1954 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1955 break;
1956 }
1957 /*
1958 * Write back the memory destination with implicit LOCK
1959 * prefix.
1960 */
e4e03ded
LV		 1961 c->dst.val = c->src.val;
1962 c->lock_prefix = 1;
6aa8b732 1963 break;
6aa8b732 1964 case 0x88 ... 0x8b: /* mov */
7de75248 1965 goto mov;
38d5bc6d
GT		 1966 case 0x8c: { /* mov r/m, sreg */
1967 struct kvm_segment segreg;
1968
1969 if (c->modrm_reg <= 5)
1970 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1971 else {
1972 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1973 c->modrm);
1974 goto cannot_emulate;
1975 }
1976 c->dst.val = segreg.selector;
1977 break;
1978 }
7e0b54b1 1979 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1980 c->dst.val = c->modrm_ea;
7e0b54b1 1981 break;
4257198a
GT		 1982 case 0x8e: { /* mov seg, r/m16 */
1983 uint16_t sel;
1984 int type_bits;
1985 int err;
1986
1987 sel = c->src.val;
310b5d30
GC		 1988 if (c->modrm_reg == VCPU_SREG_SS)
1989 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1990
4257198a
GT		 1991 if (c->modrm_reg <= 5) {
1992 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1993 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1994 type_bits, c->modrm_reg);
1995 } else {
1996 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1997 c->modrm);
1998 goto cannot_emulate;
1999 }
2000
2001 if (err < 0)
2002 goto cannot_emulate;
2003
2004 c->dst.type = OP_NONE; /* Disable writeback. */
2005 break;
2006 }
6aa8b732 2007 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 2008 rc = emulate_grp1a(ctxt, ops);
2009 if (rc != 0)
6aa8b732 2010 goto done;
6aa8b732 2011 break;
b13354f8
MG		 2012 case 0x90: /* nop / xchg r8,rax */
2013 if (!(c->rex_prefix & 1)) { /* nop */
2014 c->dst.type = OP_NONE;
2015 break;
2016 }
2017 case 0x91 ... 0x97: /* xchg reg,rax */
2018 c->src.type = c->dst.type = OP_REG;
2019 c->src.bytes = c->dst.bytes = c->op_bytes;
2020 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2021 c->src.val = *(c->src.ptr);
2022 goto xchg;
fd2a7608 2023 case 0x9c: /* pushf */
05f086f8 2024 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2025 emulate_push(ctxt);
2026 break;
535eabcf 2027 case 0x9d: /* popf */
2b48cc75 2028 c->dst.type = OP_REG;
05f086f8 2029 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2030 c->dst.bytes = c->op_bytes;
535eabcf 2031 goto pop_instruction;
018a98db
AK		 2032 case 0xa0 ... 0xa1: /* mov */
2033 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2034 c->dst.val = c->src.val;
2035 break;
2036 case 0xa2 ... 0xa3: /* mov */
2037 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2038 break;
6aa8b732 2039 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2040 c->dst.type = OP_MEM;
2041 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2042 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2043 es_base(ctxt),
e4e03ded 2044 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2045 rc = ops->read_emulated(register_address(c,
2046 seg_override_base(ctxt, c),
2047 c->regs[VCPU_REGS_RSI]),
e4e03ded 2048 &c->dst.val,
b60d513c
TY		 2049 c->dst.bytes, ctxt->vcpu);
2050 if (rc != X86EMUL_CONTINUE)
6aa8b732 2051 goto done;
7a957275 2052 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2053 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2054 : c->dst.bytes);
7a957275 2055 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2056 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2057 : c->dst.bytes);
6aa8b732
AK		 2058 break;
2059 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2060 c->src.type = OP_NONE; /* Disable writeback. */
2061 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2062 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2063 seg_override_base(ctxt, c),
d7e5117a 2064 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2065 rc = ops->read_emulated((unsigned long)c->src.ptr,
2066 &c->src.val,
2067 c->src.bytes,
2068 ctxt->vcpu);
2069 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2070 goto done;
2071
2072 c->dst.type = OP_NONE; /* Disable writeback. */
2073 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2074 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2075 es_base(ctxt),
d7e5117a 2076 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2077 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2078 &c->dst.val,
2079 c->dst.bytes,
2080 ctxt->vcpu);
2081 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2082 goto done;
2083
2084 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2085
2086 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2087
7a957275 2088 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2089 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2090 : c->src.bytes);
7a957275 2091 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2092 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2093 : c->dst.bytes);
2094
2095 break;
6aa8b732 2096 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2097 c->dst.type = OP_MEM;
2098 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2099 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2100 es_base(ctxt),
a7e6c88a 2101 c->regs[VCPU_REGS_RDI]);
e4e03ded 2102 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2103 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2104 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2105 : c->dst.bytes);
6aa8b732
AK		 2106 break;
2107 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2108 c->dst.type = OP_REG;
2109 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2110 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2111 rc = ops->read_emulated(register_address(c,
2112 seg_override_base(ctxt, c),
2113 c->regs[VCPU_REGS_RSI]),
2114 &c->dst.val,
2115 c->dst.bytes,
2116 ctxt->vcpu);
2117 if (rc != X86EMUL_CONTINUE)
6aa8b732 2118 goto done;
7a957275 2119 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2120 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2121 : c->dst.bytes);
6aa8b732
AK		 2122 break;
2123 case 0xae ... 0xaf: /* scas */
2124 DPRINTF("Urk! I don't handle SCAS.\n");
2125 goto cannot_emulate;
a5e2e82b 2126 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2127 goto mov;
018a98db
AK		 2128 case 0xc0 ... 0xc1:
2129 emulate_grp2(ctxt);
2130 break;
111de5d6 2131 case 0xc3: /* ret */
cf5de4f8 2132 c->dst.type = OP_REG;
111de5d6 2133 c->dst.ptr = &c->eip;
cf5de4f8 2134 c->dst.bytes = c->op_bytes;
111de5d6 2135 goto pop_instruction;
018a98db
AK		 2136 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2137 mov:
2138 c->dst.val = c->src.val;
2139 break;
a77ab5ea
AK		 2140 case 0xcb: /* ret far */
2141 rc = emulate_ret_far(ctxt, ops);
2142 if (rc)
2143 goto done;
2144 break;
018a98db
AK		 2145 case 0xd0 ... 0xd1: /* Grp2 */
2146 c->src.val = 1;
2147 emulate_grp2(ctxt);
2148 break;
2149 case 0xd2 ... 0xd3: /* Grp2 */
2150 c->src.val = c->regs[VCPU_REGS_RCX];
2151 emulate_grp2(ctxt);
2152 break;
a6a3034c
MG		 2153 case 0xe4: /* inb */
2154 case 0xe5: /* in */
84ce66a6 2155 port = c->src.val;
a6a3034c
MG		 2156 io_dir_in = 1;
2157 goto do_io;
2158 case 0xe6: /* outb */
2159 case 0xe7: /* out */
84ce66a6 2160 port = c->src.val;
a6a3034c
MG		 2161 io_dir_in = 0;
2162 goto do_io;
1a52e051 2163 case 0xe8: /* call (near) */ {
d53c4777 2164 long int rel = c->src.val;
e4e03ded 2165 c->src.val = (unsigned long) c->eip;
7a957275 2166 jmp_rel(c, rel);
8cdbd2c9
LV		 2167 emulate_push(ctxt);
2168 break;
1a52e051
NK		 2169 }
2170 case 0xe9: /* jmp rel */
954cd36f 2171 goto jmp;
782b877c
GN		 2172 case 0xea: /* jmp far */
2173 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2174 VCPU_SREG_CS) < 0) {
954cd36f
GT		 2175 DPRINTF("jmp far: Failed to load CS descriptor\n");
2176 goto cannot_emulate;
2177 }
2178
782b877c 2179 c->eip = c->src.val;
954cd36f 2180 break;
954cd36f
GT		 2181 case 0xeb:
2182 jmp: /* jmp rel short */
7a957275 2183 jmp_rel(c, c->src.val);
a01af5ec 2184 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2185 break;
a6a3034c
MG		 2186 case 0xec: /* in al,dx */
2187 case 0xed: /* in (e/r)ax,dx */
2188 port = c->regs[VCPU_REGS_RDX];
2189 io_dir_in = 1;
2190 goto do_io;
2191 case 0xee: /* out al,dx */
2192 case 0xef: /* out (e/r)ax,dx */
2193 port = c->regs[VCPU_REGS_RDX];
2194 io_dir_in = 0;
851ba692 2195 do_io: if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2196 (c->d & ByteOp) ? 1 : c->op_bytes,
2197 port) != 0) {
2198 c->eip = saved_eip;
2199 goto cannot_emulate;
2200 }
e93f36bc 2201 break;
111de5d6 2202 case 0xf4: /* hlt */
ad312c7c 2203 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2204 break;
111de5d6
AK		 2205 case 0xf5: /* cmc */
2206 /* complement carry flag from eflags reg */
2207 ctxt->eflags ^= EFLG_CF;
2208 c->dst.type = OP_NONE; /* Disable writeback. */
2209 break;
018a98db
AK		 2210 case 0xf6 ... 0xf7: /* Grp3 */
2211 rc = emulate_grp3(ctxt, ops);
2212 if (rc != 0)
2213 goto done;
2214 break;
111de5d6
AK		 2215 case 0xf8: /* clc */
2216 ctxt->eflags &= ~EFLG_CF;
2217 c->dst.type = OP_NONE; /* Disable writeback. */
2218 break;
2219 case 0xfa: /* cli */
2220 ctxt->eflags &= ~X86_EFLAGS_IF;
2221 c->dst.type = OP_NONE; /* Disable writeback. */
2222 break;
2223 case 0xfb: /* sti */
310b5d30 2224 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
111de5d6
AK		 2225 ctxt->eflags |= X86_EFLAGS_IF;
2226 c->dst.type = OP_NONE; /* Disable writeback. */
2227 break;
fb4616f4
MG		 2228 case 0xfc: /* cld */
2229 ctxt->eflags &= ~EFLG_DF;
2230 c->dst.type = OP_NONE; /* Disable writeback. */
2231 break;
2232 case 0xfd: /* std */
2233 ctxt->eflags |= EFLG_DF;
2234 c->dst.type = OP_NONE; /* Disable writeback. */
2235 break;
018a98db
AK		 2236 case 0xfe ... 0xff: /* Grp4/Grp5 */
2237 rc = emulate_grp45(ctxt, ops);
2238 if (rc != 0)
2239 goto done;
2240 break;
6aa8b732 2241 }
018a98db
AK		 2242
2243writeback:
2244 rc = writeback(ctxt, ops);
2245 if (rc != 0)
2246 goto done;
2247
2248 /* Commit shadow register state. */
ad312c7c 2249 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2250 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2251
2252done:
2253 if (rc == X86EMUL_UNHANDLEABLE) {
2254 c->eip = saved_eip;
2255 return -1;
2256 }
2257 return 0;
6aa8b732
AK		 2258
2259twobyte_insn:
e4e03ded 2260 switch (c->b) {
6aa8b732 2261 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2262 switch (c->modrm_reg) {
6aa8b732
AK		 2263 u16 size;
2264 unsigned long address;
2265
aca7f966 2266 case 0: /* vmcall */
e4e03ded 2267 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2268 goto cannot_emulate;
2269
7aa81cc0
AL		 2270 rc = kvm_fix_hypercall(ctxt->vcpu);
2271 if (rc)
2272 goto done;
2273
33e3885d 2274 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2275 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2276 /* Disable writeback. */
2277 c->dst.type = OP_NONE;
aca7f966 2278 break;
6aa8b732 2279 case 2: /* lgdt */
e4e03ded
LV		 2280 rc = read_descriptor(ctxt, ops, c->src.ptr,
2281 &size, &address, c->op_bytes);
6aa8b732
AK		 2282 if (rc)
2283 goto done;
2284 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2285 /* Disable writeback. */
2286 c->dst.type = OP_NONE;
6aa8b732 2287 break;
aca7f966 2288 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2289 if (c->modrm_mod == 3) {
2290 switch (c->modrm_rm) {
2291 case 1:
2292 rc = kvm_fix_hypercall(ctxt->vcpu);
2293 if (rc)
2294 goto done;
2295 break;
2296 default:
2297 goto cannot_emulate;
2298 }
aca7f966 2299 } else {
e4e03ded 2300 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2301 &size, &address,
e4e03ded 2302 c->op_bytes);
aca7f966
AL		 2303 if (rc)
2304 goto done;
2305 realmode_lidt(ctxt->vcpu, size, address);
2306 }
16286d08
AK		 2307 /* Disable writeback. */
2308 c->dst.type = OP_NONE;
6aa8b732
AK		 2309 break;
2310 case 4: /* smsw */
16286d08
AK		 2311 c->dst.bytes = 2;
2312 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2313 break;
2314 case 6: /* lmsw */
16286d08
AK		 2315 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2316 &ctxt->eflags);
dc7457ea 2317 c->dst.type = OP_NONE;
6aa8b732
AK		 2318 break;
2319 case 7: /* invlpg*/
e8d8d7fe 2320 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2321 /* Disable writeback. */
2322 c->dst.type = OP_NONE;
6aa8b732
AK		 2323 break;
2324 default:
2325 goto cannot_emulate;
2326 }
2327 break;
e99f0507 2328 case 0x05: /* syscall */
e66bb2cc
AP		 2329 if (emulate_syscall(ctxt) == -1)
2330 goto cannot_emulate;
2331 else
2332 goto writeback;
e99f0507 2333 break;
018a98db
AK		 2334 case 0x06:
2335 emulate_clts(ctxt->vcpu);
2336 c->dst.type = OP_NONE;
2337 break;
2338 case 0x08: /* invd */
2339 case 0x09: /* wbinvd */
2340 case 0x0d: /* GrpP (prefetch) */
2341 case 0x18: /* Grp16 (prefetch/nop) */
2342 c->dst.type = OP_NONE;
2343 break;
2344 case 0x20: /* mov cr, reg */
2345 if (c->modrm_mod != 3)
2346 goto cannot_emulate;
2347 c->regs[c->modrm_rm] =
2348 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2349 c->dst.type = OP_NONE; /* no writeback */
2350 break;
6aa8b732 2351 case 0x21: /* mov from dr to reg */
e4e03ded 2352 if (c->modrm_mod != 3)
6aa8b732 2353 goto cannot_emulate;
8cdbd2c9 2354 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2355 if (rc)
2356 goto cannot_emulate;
2357 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2358 break;
018a98db
AK		 2359 case 0x22: /* mov reg, cr */
2360 if (c->modrm_mod != 3)
2361 goto cannot_emulate;
2362 realmode_set_cr(ctxt->vcpu,
2363 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2364 c->dst.type = OP_NONE;
2365 break;
6aa8b732 2366 case 0x23: /* mov from reg to dr */
e4e03ded 2367 if (c->modrm_mod != 3)
6aa8b732 2368 goto cannot_emulate;
e4e03ded
LV		 2369 rc = emulator_set_dr(ctxt, c->modrm_reg,
2370 c->regs[c->modrm_rm]);
a01af5ec
LV		 2371 if (rc)
2372 goto cannot_emulate;
2373 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2374 break;
018a98db
AK		 2375 case 0x30:
2376 /* wrmsr */
2377 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2378 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2379 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2380 if (rc) {
c1a5d4f9 2381 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2382 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2383 }
2384 rc = X86EMUL_CONTINUE;
2385 c->dst.type = OP_NONE;
2386 break;
2387 case 0x32:
2388 /* rdmsr */
2389 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2390 if (rc) {
c1a5d4f9 2391 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2392 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2393 } else {
2394 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2395 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2396 }
2397 rc = X86EMUL_CONTINUE;
2398 c->dst.type = OP_NONE;
2399 break;
e99f0507 2400 case 0x34: /* sysenter */
8c604352
AP		 2401 if (emulate_sysenter(ctxt) == -1)
2402 goto cannot_emulate;
2403 else
2404 goto writeback;
e99f0507
AP		 2405 break;
2406 case 0x35: /* sysexit */
4668f050
AP		 2407 if (emulate_sysexit(ctxt) == -1)
2408 goto cannot_emulate;
2409 else
2410 goto writeback;
e99f0507 2411 break;
6aa8b732 2412 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2413 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2414 if (!test_cc(c->b, ctxt->eflags))
2415 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2416 break;
b2833e3c 2417 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2418 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2419 jmp_rel(c, c->src.val);
018a98db
AK		 2420 c->dst.type = OP_NONE;
2421 break;
0934ac9d
MG		 2422 case 0xa0: /* push fs */
2423 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2424 break;
2425 case 0xa1: /* pop fs */
2426 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2427 if (rc != 0)
2428 goto done;
2429 break;
7de75248
NK		 2430 case 0xa3:
2431 bt: /* bt */
e4f8e039 2432 c->dst.type = OP_NONE;
e4e03ded
LV		 2433 /* only subword offset */
2434 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2435 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2436 break;
9bf8ea42
GT		 2437 case 0xa4: /* shld imm8, r, r/m */
2438 case 0xa5: /* shld cl, r, r/m */
2439 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2440 break;
0934ac9d
MG		 2441 case 0xa8: /* push gs */
2442 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2443 break;
2444 case 0xa9: /* pop gs */
2445 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2446 if (rc != 0)
2447 goto done;
2448 break;
7de75248
NK		 2449 case 0xab:
2450 bts: /* bts */
e4e03ded
LV		 2451 /* only subword offset */
2452 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2453 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2454 break;
9bf8ea42
GT		 2455 case 0xac: /* shrd imm8, r, r/m */
2456 case 0xad: /* shrd cl, r, r/m */
2457 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2458 break;
2a7c5b8b
GC		 2459 case 0xae: /* clflush */
2460 break;
6aa8b732
AK		 2461 case 0xb0 ... 0xb1: /* cmpxchg */
2462 /*
2463 * Save real source value, then compare EAX against
2464 * destination.
2465 */
e4e03ded
LV		 2466 c->src.orig_val = c->src.val;
2467 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2468 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2469 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2470 /* Success: write back to memory. */
e4e03ded 2471 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2472 } else {
2473 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2474 c->dst.type = OP_REG;
2475 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2476 }
2477 break;
6aa8b732
AK		 2478 case 0xb3:
2479 btr: /* btr */
e4e03ded
LV		 2480 /* only subword offset */
2481 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2482 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2483 break;
6aa8b732 2484 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2485 c->dst.bytes = c->op_bytes;
2486 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2487 : (u16) c->src.val;
6aa8b732 2488 break;
6aa8b732 2489 case 0xba: /* Grp8 */
e4e03ded 2490 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2491 case 0:
2492 goto bt;
2493 case 1:
2494 goto bts;
2495 case 2:
2496 goto btr;
2497 case 3:
2498 goto btc;
2499 }
2500 break;
7de75248
NK		 2501 case 0xbb:
2502 btc: /* btc */
e4e03ded
LV		 2503 /* only subword offset */
2504 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2505 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2506 break;
6aa8b732 2507 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2508 c->dst.bytes = c->op_bytes;
2509 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2510 (s16) c->src.val;
6aa8b732 2511 break;
a012e65a 2512 case 0xc3: /* movnti */
e4e03ded
LV		 2513 c->dst.bytes = c->op_bytes;
2514 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2515 (u64) c->src.val;
a012e65a 2516 break;
6aa8b732 2517 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2518 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2519 if (rc != 0)
2520 goto done;
018a98db 2521 c->dst.type = OP_NONE;
8cdbd2c9 2522 break;
6aa8b732
AK		 2523 }
2524 goto writeback;
2525
2526cannot_emulate:
e4e03ded 2527 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2528 c->eip = saved_eip;
6aa8b732
AK		 2529 return -1;
2530}
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