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KVM: x86 emulator: reserve group code 0
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
2ce49536 49#define ByteOp (1<<16) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
2ce49536
AK		 51#define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<17) /* Register operand. */
53#define DstMem (3<<17) /* Memory operand. */
54#define DstAcc (4<<17) /* Destination Accumulator */
55#define DstDI (5<<17) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<17) /* 64bit memory operand */
57#define DstMask (7<<17)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
2ce49536 85#define GroupMask 0x0f /* Group number stored in bits 0:3 */
d8769fed 86/* Misc flags */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
96#define Src2Mask (7<<29)
6aa8b732 97
ea9ef04e
AK		 98#define X2(x) x, x
99#define X3(x) X2(x), x
83babbca 100#define X4(x) X2(x), X2(x)
ea9ef04e 101#define X5(x) X4(x), x
83babbca
AK		 102#define X6(x) X4(x), X2(x)
103#define X7(x) X4(x), X3(x)
104#define X8(x) X4(x), X4(x)
105#define X16(x) X8(x), X8(x)
106
43bb19cd 107enum {
793d5a8d 108 NoGrp, Group1, Group1A, Group3, Group4, Group5, Group7, Group8, Group9,
43bb19cd
AK		 109};
110
d65b1dee
AK		 111struct opcode {
112 u32 flags;
113};
114
fd853310
AK		 115#define D(_y) { .flags = (_y) }
116#define N D(0)
117
42a1c520
AK		 118static struct opcode group_table[] = {
119 [Group1*8] =
120 X7(D(Lock)), N,
121 [Group1A*8] =
122 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
123 [Group3*8] =
124 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
125 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
126 X4(D(Undefined)),
127 [Group4*8] =
128 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
129 N, N, N, N, N, N,
130 [Group5*8] =
131 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
132 D(SrcMem | ModRM | Stack), N,
133 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
134 D(SrcMem | ModRM | Stack), N,
135 [Group7*8] =
136 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
137 D(SrcNone | ModRM | DstMem | Mov), N,
138 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
139 [Group8*8] =
140 N, N, N, N,
141 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
142 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
143 [Group9*8] =
144 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
145};
146
147static struct opcode group2_table[] = {
148 [Group7*8] =
149 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
150 D(SrcNone | ModRM | DstMem | Mov), N,
151 D(SrcMem16 | ModRM | Mov | Priv), N,
152 [Group9*8] =
153 N, N, N, N, N, N, N, N,
154};
155
d65b1dee 156static struct opcode opcode_table[256] = {
6aa8b732 157 /* 0x00 - 0x07 */
fd853310
AK		 158 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
159 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
160 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
161 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 162 /* 0x08 - 0x0F */
fd853310
AK		 163 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
164 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
165 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
166 D(ImplicitOps | Stack | No64), N,
6aa8b732 167 /* 0x10 - 0x17 */
fd853310
AK		 168 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
169 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
170 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
171 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 172 /* 0x18 - 0x1F */
fd853310
AK		 173 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
174 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
175 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
176 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
6aa8b732 177 /* 0x20 - 0x27 */
fd853310
AK		 178 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
179 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
180 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 181 /* 0x28 - 0x2F */
fd853310
AK		 182 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
183 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
184 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 185 /* 0x30 - 0x37 */
fd853310
AK		 186 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
187 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
188 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
6aa8b732 189 /* 0x38 - 0x3F */
fd853310
AK		 190 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
191 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
192 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
193 N, N,
749358a6 194 /* 0x40 - 0x4F */
fd853310 195 X16(D(DstReg)),
7f0aaee0 196 /* 0x50 - 0x57 */
fd853310 197 X8(D(SrcReg | Stack)),
7f0aaee0 198 /* 0x58 - 0x5F */
fd853310 199 X8(D(DstReg | Stack)),
7d316911 200 /* 0x60 - 0x67 */
fd853310
AK		 201 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
202 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
203 N, N, N, N,
7d316911 204 /* 0x68 - 0x6F */
fd853310
AK		 205 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
206 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
207 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
b3ab3405 208 /* 0x70 - 0x7F */
fd853310 209 X16(D(SrcImmByte)),
6aa8b732 210 /* 0x80 - 0x87 */
fd853310
AK		 211 D(ByteOp | DstMem | SrcImm | ModRM | Group | Group1),
212 D(DstMem | SrcImm | ModRM | Group | Group1),
213 D(ByteOp | DstMem | SrcImm | ModRM | No64 | Group | Group1),
214 D(DstMem | SrcImmByte | ModRM | Group | Group1),
215 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
216 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
6aa8b732 217 /* 0x88 - 0x8F */
fd853310
AK		 218 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
219 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
220 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
221 D(ImplicitOps | SrcMem16 | ModRM), D(Group | Group1A),
b13354f8 222 /* 0x90 - 0x97 */
fd853310 223 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
b13354f8 224 /* 0x98 - 0x9F */
fd853310
AK		 225 N, N, D(SrcImmFAddr | No64), N,
226 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
6aa8b732 227 /* 0xA0 - 0xA7 */
fd853310
AK		 228 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
229 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
230 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
231 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
6aa8b732 232 /* 0xA8 - 0xAF */
fd853310
AK		 233 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
234 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
235 D(ByteOp | DstDI | String), D(DstDI | String),
a5e2e82b 236 /* 0xB0 - 0xB7 */
fd853310 237 X8(D(ByteOp | DstReg | SrcImm | Mov)),
a5e2e82b 238 /* 0xB8 - 0xBF */
fd853310 239 X8(D(DstReg | SrcImm | Mov)),
6aa8b732 240 /* 0xC0 - 0xC7 */
fd853310
AK		 241 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
242 N, D(ImplicitOps | Stack), N, N,
243 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
6aa8b732 244 /* 0xC8 - 0xCF */
fd853310
AK		 245 N, N, N, D(ImplicitOps | Stack),
246 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
6aa8b732 247 /* 0xD0 - 0xD7 */
fd853310
AK		 248 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
249 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
250 N, N, N, N,
6aa8b732 251 /* 0xD8 - 0xDF */
fd853310 252 N, N, N, N, N, N, N, N,
098c937b 253 /* 0xE0 - 0xE7 */
fd853310
AK		 254 N, N, N, N,
255 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
256 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
098c937b 257 /* 0xE8 - 0xEF */
fd853310
AK		 258 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
259 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
260 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
261 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
6aa8b732 262 /* 0xF0 - 0xF7 */
fd853310
AK		 263 N, N, N, N,
264 D(ImplicitOps | Priv), D(ImplicitOps), D(ByteOp | Group | Group3), D(Group | Group3),
6aa8b732 265 /* 0xF8 - 0xFF */
fd853310
AK		 266 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
267 D(ImplicitOps), D(ImplicitOps), D(Group | Group4), D(Group | Group5),
6aa8b732
AK		 268};
269
d65b1dee 270static struct opcode twobyte_table[256] = {
6aa8b732 271 /* 0x00 - 0x0F */
fd853310
AK		 272 N, D(Group | GroupDual | Group7), N, N,
273 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
274 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
275 N, D(ImplicitOps | ModRM), N, N,
6aa8b732 276 /* 0x10 - 0x1F */
fd853310 277 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
6aa8b732 278 /* 0x20 - 0x2F */
fd853310
AK		 279 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
280 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
281 N, N, N, N,
282 N, N, N, N, N, N, N, N,
6aa8b732 283 /* 0x30 - 0x3F */
fd853310
AK		 284 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
285 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
286 N, N, N, N, N, N, N, N,
be8eacdd 287 /* 0x40 - 0x4F */
fd853310 288 X16(D(DstReg | SrcMem | ModRM | Mov)),
6aa8b732 289 /* 0x50 - 0x5F */
fd853310 290 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 291 /* 0x60 - 0x6F */
fd853310 292 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 293 /* 0x70 - 0x7F */
fd853310 294 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 295 /* 0x80 - 0x8F */
fd853310 296 X16(D(SrcImm)),
6aa8b732 297 /* 0x90 - 0x9F */
fd853310 298 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 299 /* 0xA0 - 0xA7 */
fd853310
AK		 300 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
301 N, D(DstMem | SrcReg | ModRM | BitOp),
302 D(DstMem | SrcReg | Src2ImmByte | ModRM),
303 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
6aa8b732 304 /* 0xA8 - 0xAF */
fd853310
AK		 305 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
306 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
307 D(DstMem | SrcReg | Src2ImmByte | ModRM),
308 D(DstMem | SrcReg | Src2CL | ModRM),
309 D(ModRM), N,
6aa8b732 310 /* 0xB0 - 0xB7 */
fd853310
AK		 311 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
312 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
313 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
314 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 315 /* 0xB8 - 0xBF */
fd853310
AK		 316 N, N,
317 D(Group | Group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
318 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
319 D(DstReg | SrcMem16 | ModRM | Mov),
6aa8b732 320 /* 0xC0 - 0xCF */
fd853310
AK		 321 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
322 N, N, N, D(Group | GroupDual | Group9),
323 N, N, N, N, N, N, N, N,
6aa8b732 324 /* 0xD0 - 0xDF */
fd853310 325 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 326 /* 0xE0 - 0xEF */
fd853310 327 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
6aa8b732 328 /* 0xF0 - 0xFF */
fd853310 329 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
6aa8b732
AK		 330};
331
fd853310
AK		 332#undef D
333#undef N
334
6aa8b732 335/* EFLAGS bit definitions. */
d4c6a154
GN		 336#define EFLG_ID (1<<21)
337#define EFLG_VIP (1<<20)
338#define EFLG_VIF (1<<19)
339#define EFLG_AC (1<<18)
b1d86143
AP		 340#define EFLG_VM (1<<17)
341#define EFLG_RF (1<<16)
d4c6a154
GN		 342#define EFLG_IOPL (3<<12)
343#define EFLG_NT (1<<14)
6aa8b732
AK		 344#define EFLG_OF (1<<11)
345#define EFLG_DF (1<<10)
b1d86143 346#define EFLG_IF (1<<9)
d4c6a154 347#define EFLG_TF (1<<8)
6aa8b732
AK		 348#define EFLG_SF (1<<7)
349#define EFLG_ZF (1<<6)
350#define EFLG_AF (1<<4)
351#define EFLG_PF (1<<2)
352#define EFLG_CF (1<<0)
353
62bd430e
MG		 354#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
355#define EFLG_RESERVED_ONE_MASK 2
356
6aa8b732
AK		 357/*
358 * Instruction emulation:
359 * Most instructions are emulated directly via a fragment of inline assembly
360 * code. This allows us to save/restore EFLAGS and thus very easily pick up
361 * any modified flags.
362 */
363
05b3e0c2 364#if defined(CONFIG_X86_64)
6aa8b732
AK		 365#define _LO32 "k" /* force 32-bit operand */
366#define _STK "%%rsp" /* stack pointer */
367#elif defined(__i386__)
368#define _LO32 "" /* force 32-bit operand */
369#define _STK "%%esp" /* stack pointer */
370#endif
371
372/*
373 * These EFLAGS bits are restored from saved value during emulation, and
374 * any changes are written back to the saved value after emulation.
375 */
376#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
377
378/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 379#define _PRE_EFLAGS(_sav, _msk, _tmp) \
380 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
381 "movl %"_sav",%"_LO32 _tmp"; " \
382 "push %"_tmp"; " \
383 "push %"_tmp"; " \
384 "movl %"_msk",%"_LO32 _tmp"; " \
385 "andl %"_LO32 _tmp",("_STK"); " \
386 "pushf; " \
387 "notl %"_LO32 _tmp"; " \
388 "andl %"_LO32 _tmp",("_STK"); " \
389 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
390 "pop %"_tmp"; " \
391 "orl %"_LO32 _tmp",("_STK"); " \
392 "popf; " \
393 "pop %"_sav"; "
6aa8b732
AK		 394
395/* After executing instruction: write-back necessary bits in EFLAGS. */
396#define _POST_EFLAGS(_sav, _msk, _tmp) \
397 /* _sav |= EFLAGS & _msk; */ \
398 "pushf; " \
399 "pop %"_tmp"; " \
400 "andl %"_msk",%"_LO32 _tmp"; " \
401 "orl %"_LO32 _tmp",%"_sav"; "
402
dda96d8f
AK		 403#ifdef CONFIG_X86_64
404#define ON64(x) x
405#else
406#define ON64(x)
407#endif
408
6b7ad61f
AK		 409#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
410 do { \
411 __asm__ __volatile__ ( \
412 _PRE_EFLAGS("0", "4", "2") \
413 _op _suffix " %"_x"3,%1; " \
414 _POST_EFLAGS("0", "4", "2") \
415 : "=m" (_eflags), "=m" ((_dst).val), \
416 "=&r" (_tmp) \
417 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 418 } while (0)
6b7ad61f
AK		 419
420
6aa8b732
AK		 421/* Raw emulation: instruction has two explicit operands. */
422#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 423 do { \
424 unsigned long _tmp; \
425 \
426 switch ((_dst).bytes) { \
427 case 2: \
428 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
429 break; \
430 case 4: \
431 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
432 break; \
433 case 8: \
434 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
435 break; \
436 } \
6aa8b732
AK		 437 } while (0)
438
439#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
440 do { \
6b7ad61f 441 unsigned long _tmp; \
d77c26fc 442 switch ((_dst).bytes) { \
6aa8b732 443 case 1: \
6b7ad61f 444 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 445 break; \
446 default: \
447 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
448 _wx, _wy, _lx, _ly, _qx, _qy); \
449 break; \
450 } \
451 } while (0)
452
453/* Source operand is byte-sized and may be restricted to just %cl. */
454#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
455 __emulate_2op(_op, _src, _dst, _eflags, \
456 "b", "c", "b", "c", "b", "c", "b", "c")
457
458/* Source operand is byte, word, long or quad sized. */
459#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
460 __emulate_2op(_op, _src, _dst, _eflags, \
461 "b", "q", "w", "r", _LO32, "r", "", "r")
462
463/* Source operand is word, long or quad sized. */
464#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
465 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
466 "w", "r", _LO32, "r", "", "r")
467
d175226a
GT		 468/* Instruction has three operands and one operand is stored in ECX register */
469#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
470 do { \
471 unsigned long _tmp; \
472 _type _clv = (_cl).val; \
473 _type _srcv = (_src).val; \
474 _type _dstv = (_dst).val; \
475 \
476 __asm__ __volatile__ ( \
477 _PRE_EFLAGS("0", "5", "2") \
478 _op _suffix " %4,%1 \n" \
479 _POST_EFLAGS("0", "5", "2") \
480 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
481 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
482 ); \
483 \
484 (_cl).val = (unsigned long) _clv; \
485 (_src).val = (unsigned long) _srcv; \
486 (_dst).val = (unsigned long) _dstv; \
487 } while (0)
488
489#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
490 do { \
491 switch ((_dst).bytes) { \
492 case 2: \
493 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
494 "w", unsigned short); \
495 break; \
496 case 4: \
497 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
498 "l", unsigned int); \
499 break; \
500 case 8: \
501 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
502 "q", unsigned long)); \
503 break; \
504 } \
505 } while (0)
506
dda96d8f 507#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 508 do { \
509 unsigned long _tmp; \
510 \
dda96d8f
AK		 511 __asm__ __volatile__ ( \
512 _PRE_EFLAGS("0", "3", "2") \
513 _op _suffix " %1; " \
514 _POST_EFLAGS("0", "3", "2") \
515 : "=m" (_eflags), "+m" ((_dst).val), \
516 "=&r" (_tmp) \
517 : "i" (EFLAGS_MASK)); \
518 } while (0)
519
520/* Instruction has only one explicit operand (no source operand). */
521#define emulate_1op(_op, _dst, _eflags) \
522 do { \
d77c26fc 523 switch ((_dst).bytes) { \
dda96d8f
AK		 524 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
525 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
526 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
527 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 528 } \
529 } while (0)
530
6aa8b732
AK		 531/* Fetch next part of the instruction being emulated. */
532#define insn_fetch(_type, _size, _eip) \
533({ unsigned long _x; \
62266869 534 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 535 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 536 goto done; \
537 (_eip) += (_size); \
538 (_type)_x; \
539})
540
414e6277
GN		 541#define insn_fetch_arr(_arr, _size, _eip) \
542({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
543 if (rc != X86EMUL_CONTINUE) \
544 goto done; \
545 (_eip) += (_size); \
546})
547
ddcb2885
HH		 548static inline unsigned long ad_mask(struct decode_cache *c)
549{
550 return (1UL << (c->ad_bytes << 3)) - 1;
551}
552
6aa8b732 553/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 554static inline unsigned long
555address_mask(struct decode_cache *c, unsigned long reg)
556{
557 if (c->ad_bytes == sizeof(unsigned long))
558 return reg;
559 else
560 return reg & ad_mask(c);
561}
562
563static inline unsigned long
564register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
565{
566 return base + address_mask(c, reg);
567}
568
7a957275
HH		 569static inline void
570register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
571{
572 if (c->ad_bytes == sizeof(unsigned long))
573 *reg += inc;
574 else
575 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
576}
6aa8b732 577
7a957275
HH		 578static inline void jmp_rel(struct decode_cache *c, int rel)
579{
580 register_address_increment(c, &c->eip, rel);
581}
098c937b 582
7a5b56df
AK		 583static void set_seg_override(struct decode_cache *c, int seg)
584{
585 c->has_seg_override = true;
586 c->seg_override = seg;
587}
588
79168fd1
GN		 589static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
590 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 591{
592 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
593 return 0;
594
79168fd1 595 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 596}
597
598static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 599 struct x86_emulate_ops *ops,
7a5b56df
AK		 600 struct decode_cache *c)
601{
602 if (!c->has_seg_override)
603 return 0;
604
79168fd1 605 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 606}
607
79168fd1
GN		 608static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
609 struct x86_emulate_ops *ops)
7a5b56df 610{
79168fd1 611 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 612}
613
79168fd1
GN		 614static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
615 struct x86_emulate_ops *ops)
7a5b56df 616{
79168fd1 617 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 618}
619
54b8486f
GN		 620static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
621 u32 error, bool valid)
622{
623 ctxt->exception = vec;
624 ctxt->error_code = error;
625 ctxt->error_code_valid = valid;
626 ctxt->restart = false;
627}
628
629static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
630{
631 emulate_exception(ctxt, GP_VECTOR, err, true);
632}
633
634static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
635 int err)
636{
637 ctxt->cr2 = addr;
638 emulate_exception(ctxt, PF_VECTOR, err, true);
639}
640
641static void emulate_ud(struct x86_emulate_ctxt *ctxt)
642{
643 emulate_exception(ctxt, UD_VECTOR, 0, false);
644}
645
646static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
647{
648 emulate_exception(ctxt, TS_VECTOR, err, true);
649}
650
62266869
AK		 651static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
2fb53ad8 653 unsigned long eip, u8 *dest)
62266869
AK		 654{
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
2fb53ad8 657 int size, cur_size;
62266869 658
2fb53ad8
AK		 659 if (eip == fc->end) {
660 cur_size = fc->end - fc->start;
661 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
662 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
663 size, ctxt->vcpu, NULL);
3e2815e9 664 if (rc != X86EMUL_CONTINUE)
62266869 665 return rc;
2fb53ad8 666 fc->end += size;
62266869 667 }
2fb53ad8 668 *dest = fc->data[eip - fc->start];
3e2815e9 669 return X86EMUL_CONTINUE;
62266869
AK		 670}
671
672static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
674 unsigned long eip, void *dest, unsigned size)
675{
3e2815e9 676 int rc;
62266869 677
eb3c79e6 678 /* x86 instructions are limited to 15 bytes. */
063db061 679 if (eip + size - ctxt->eip > 15)
eb3c79e6 680 return X86EMUL_UNHANDLEABLE;
62266869
AK		 681 while (size--) {
682 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 683 if (rc != X86EMUL_CONTINUE)
62266869
AK		 684 return rc;
685 }
3e2815e9 686 return X86EMUL_CONTINUE;
62266869
AK		 687}
688
1e3c5cb0
RR		 689/*
690 * Given the 'reg' portion of a ModRM byte, and a register block, return a
691 * pointer into the block that addresses the relevant register.
692 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
693 */
694static void *decode_register(u8 modrm_reg, unsigned long *regs,
695 int highbyte_regs)
6aa8b732
AK		 696{
697 void *p;
698
699 p = &regs[modrm_reg];
700 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
701 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
702 return p;
703}
704
705static int read_descriptor(struct x86_emulate_ctxt *ctxt,
706 struct x86_emulate_ops *ops,
707 void *ptr,
708 u16 *size, unsigned long *address, int op_bytes)
709{
710 int rc;
711
712 if (op_bytes == 2)
713 op_bytes = 3;
714 *address = 0;
cebff02b 715 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 716 ctxt->vcpu, NULL);
1b30eaa8 717 if (rc != X86EMUL_CONTINUE)
6aa8b732 718 return rc;
cebff02b 719 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 720 ctxt->vcpu, NULL);
6aa8b732
AK		 721 return rc;
722}
723
bbe9abbd
NK		 724static int test_cc(unsigned int condition, unsigned int flags)
725{
726 int rc = 0;
727
728 switch ((condition & 15) >> 1) {
729 case 0: /* o */
730 rc |= (flags & EFLG_OF);
731 break;
732 case 1: /* b/c/nae */
733 rc |= (flags & EFLG_CF);
734 break;
735 case 2: /* z/e */
736 rc |= (flags & EFLG_ZF);
737 break;
738 case 3: /* be/na */
739 rc |= (flags & (EFLG_CF|EFLG_ZF));
740 break;
741 case 4: /* s */
742 rc |= (flags & EFLG_SF);
743 break;
744 case 5: /* p/pe */
745 rc |= (flags & EFLG_PF);
746 break;
747 case 7: /* le/ng */
748 rc |= (flags & EFLG_ZF);
749 /* fall through */
750 case 6: /* l/nge */
751 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
752 break;
753 }
754
755 /* Odd condition identifiers (lsb == 1) have inverted sense. */
756 return (!!rc ^ (condition & 1));
757}
758
3c118e24
AK		 759static void decode_register_operand(struct operand *op,
760 struct decode_cache *c,
3c118e24
AK		 761 int inhibit_bytereg)
762{
33615aa9 763 unsigned reg = c->modrm_reg;
9f1ef3f8 764 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 765
766 if (!(c->d & ModRM))
767 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 768 op->type = OP_REG;
769 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 770 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 771 op->val = *(u8 *)op->ptr;
772 op->bytes = 1;
773 } else {
33615aa9 774 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 775 op->bytes = c->op_bytes;
776 switch (op->bytes) {
777 case 2:
778 op->val = *(u16 *)op->ptr;
779 break;
780 case 4:
781 op->val = *(u32 *)op->ptr;
782 break;
783 case 8:
784 op->val = *(u64 *) op->ptr;
785 break;
786 }
787 }
788 op->orig_val = op->val;
789}
790
1c73ef66
AK		 791static int decode_modrm(struct x86_emulate_ctxt *ctxt,
792 struct x86_emulate_ops *ops)
793{
794 struct decode_cache *c = &ctxt->decode;
795 u8 sib;
f5b4edcd 796 int index_reg = 0, base_reg = 0, scale;
3e2815e9 797 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 798
799 if (c->rex_prefix) {
800 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
801 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
802 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
803 }
804
805 c->modrm = insn_fetch(u8, 1, c->eip);
806 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
807 c->modrm_reg |= (c->modrm & 0x38) >> 3;
808 c->modrm_rm |= (c->modrm & 0x07);
809 c->modrm_ea = 0;
810 c->use_modrm_ea = 1;
811
812 if (c->modrm_mod == 3) {
107d6d2e
AK		 813 c->modrm_ptr = decode_register(c->modrm_rm,
814 c->regs, c->d & ByteOp);
815 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 816 return rc;
817 }
818
819 if (c->ad_bytes == 2) {
820 unsigned bx = c->regs[VCPU_REGS_RBX];
821 unsigned bp = c->regs[VCPU_REGS_RBP];
822 unsigned si = c->regs[VCPU_REGS_RSI];
823 unsigned di = c->regs[VCPU_REGS_RDI];
824
825 /* 16-bit ModR/M decode. */
826 switch (c->modrm_mod) {
827 case 0:
828 if (c->modrm_rm == 6)
829 c->modrm_ea += insn_fetch(u16, 2, c->eip);
830 break;
831 case 1:
832 c->modrm_ea += insn_fetch(s8, 1, c->eip);
833 break;
834 case 2:
835 c->modrm_ea += insn_fetch(u16, 2, c->eip);
836 break;
837 }
838 switch (c->modrm_rm) {
839 case 0:
840 c->modrm_ea += bx + si;
841 break;
842 case 1:
843 c->modrm_ea += bx + di;
844 break;
845 case 2:
846 c->modrm_ea += bp + si;
847 break;
848 case 3:
849 c->modrm_ea += bp + di;
850 break;
851 case 4:
852 c->modrm_ea += si;
853 break;
854 case 5:
855 c->modrm_ea += di;
856 break;
857 case 6:
858 if (c->modrm_mod != 0)
859 c->modrm_ea += bp;
860 break;
861 case 7:
862 c->modrm_ea += bx;
863 break;
864 }
865 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
866 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 867 if (!c->has_seg_override)
868 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 869 c->modrm_ea = (u16)c->modrm_ea;
870 } else {
871 /* 32/64-bit ModR/M decode. */
84411d85 872 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 873 sib = insn_fetch(u8, 1, c->eip);
874 index_reg |= (sib >> 3) & 7;
875 base_reg |= sib & 7;
876 scale = sib >> 6;
877
dc71d0f1
AK		 878 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
879 c->modrm_ea += insn_fetch(s32, 4, c->eip);
880 else
1c73ef66 881 c->modrm_ea += c->regs[base_reg];
dc71d0f1 882 if (index_reg != 4)
1c73ef66 883 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 884 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
885 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 886 c->rip_relative = 1;
84411d85 887 } else
1c73ef66 888 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 889 switch (c->modrm_mod) {
890 case 0:
891 if (c->modrm_rm == 5)
892 c->modrm_ea += insn_fetch(s32, 4, c->eip);
893 break;
894 case 1:
895 c->modrm_ea += insn_fetch(s8, 1, c->eip);
896 break;
897 case 2:
898 c->modrm_ea += insn_fetch(s32, 4, c->eip);
899 break;
900 }
901 }
1c73ef66
AK		 902done:
903 return rc;
904}
905
906static int decode_abs(struct x86_emulate_ctxt *ctxt,
907 struct x86_emulate_ops *ops)
908{
909 struct decode_cache *c = &ctxt->decode;
3e2815e9 910 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 911
912 switch (c->ad_bytes) {
913 case 2:
914 c->modrm_ea = insn_fetch(u16, 2, c->eip);
915 break;
916 case 4:
917 c->modrm_ea = insn_fetch(u32, 4, c->eip);
918 break;
919 case 8:
920 c->modrm_ea = insn_fetch(u64, 8, c->eip);
921 break;
922 }
923done:
924 return rc;
925}
926
6aa8b732 927int
8b4caf66 928x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 929{
e4e03ded 930 struct decode_cache *c = &ctxt->decode;
3e2815e9 931 int rc = X86EMUL_CONTINUE;
6aa8b732 932 int mode = ctxt->mode;
52811d7d 933 int def_op_bytes, def_ad_bytes, group, dual;
6aa8b732 934
6aa8b732 935
5cd21917
GN		 936 /* we cannot decode insn before we complete previous rep insn */
937 WARN_ON(ctxt->restart);
938
063db061 939 c->eip = ctxt->eip;
2fb53ad8 940 c->fetch.start = c->fetch.end = c->eip;
79168fd1 941 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 942
943 switch (mode) {
944 case X86EMUL_MODE_REAL:
a0044755 945 case X86EMUL_MODE_VM86:
6aa8b732 946 case X86EMUL_MODE_PROT16:
f21b8bf4 947 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 948 break;
949 case X86EMUL_MODE_PROT32:
f21b8bf4 950 def_op_bytes = def_ad_bytes = 4;
6aa8b732 951 break;
05b3e0c2 952#ifdef CONFIG_X86_64
6aa8b732 953 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 954 def_op_bytes = 4;
955 def_ad_bytes = 8;
6aa8b732
AK		 956 break;
957#endif
958 default:
959 return -1;
960 }
961
f21b8bf4
AK		 962 c->op_bytes = def_op_bytes;
963 c->ad_bytes = def_ad_bytes;
964
6aa8b732 965 /* Legacy prefixes. */
b4c6abfe 966 for (;;) {
e4e03ded 967 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 968 case 0x66: /* operand-size override */
f21b8bf4
AK		 969 /* switch between 2/4 bytes */
970 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 971 break;
972 case 0x67: /* address-size override */
973 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 974 /* switch between 4/8 bytes */
f21b8bf4 975 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 976 else
e4e03ded 977 /* switch between 2/4 bytes */
f21b8bf4 978 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 979 break;
7a5b56df 980 case 0x26: /* ES override */
6aa8b732 981 case 0x2e: /* CS override */
7a5b56df 982 case 0x36: /* SS override */
6aa8b732 983 case 0x3e: /* DS override */
7a5b56df 984 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 985 break;
986 case 0x64: /* FS override */
6aa8b732 987 case 0x65: /* GS override */
7a5b56df 988 set_seg_override(c, c->b & 7);
6aa8b732 989 break;
b4c6abfe
LV		 990 case 0x40 ... 0x4f: /* REX */
991 if (mode != X86EMUL_MODE_PROT64)
992 goto done_prefixes;
33615aa9 993 c->rex_prefix = c->b;
b4c6abfe 994 continue;
6aa8b732 995 case 0xf0: /* LOCK */
e4e03ded 996 c->lock_prefix = 1;
6aa8b732 997 break;
ae6200ba 998 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 999 c->rep_prefix = REPNE_PREFIX;
1000 break;
6aa8b732 1001 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1002 c->rep_prefix = REPE_PREFIX;
6aa8b732 1003 break;
6aa8b732
AK		 1004 default:
1005 goto done_prefixes;
1006 }
b4c6abfe
LV		 1007
1008 /* Any legacy prefix after a REX prefix nullifies its effect. */
1009
33615aa9 1010 c->rex_prefix = 0;
6aa8b732
AK		 1011 }
1012
1013done_prefixes:
1014
1015 /* REX prefix. */
1c73ef66 1016 if (c->rex_prefix)
33615aa9 1017 if (c->rex_prefix & 8)
e4e03ded 1018 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1019
1020 /* Opcode byte(s). */
d65b1dee 1021 c->d = opcode_table[c->b].flags;
e4e03ded 1022 if (c->d == 0) {
6aa8b732 1023 /* Two-byte opcode? */
e4e03ded
LV		 1024 if (c->b == 0x0f) {
1025 c->twobyte = 1;
1026 c->b = insn_fetch(u8, 1, c->eip);
d65b1dee 1027 c->d = twobyte_table[c->b].flags;
6aa8b732 1028 }
e09d082c 1029 }
6aa8b732 1030
e09d082c
AK		 1031 if (c->d & Group) {
1032 group = c->d & GroupMask;
52811d7d 1033 dual = c->d & GroupDual;
e09d082c
AK		 1034 c->modrm = insn_fetch(u8, 1, c->eip);
1035 --c->eip;
1036
1037 group = (group << 3) + ((c->modrm >> 3) & 7);
52811d7d
AK		 1038 c->d &= ~(Group | GroupDual | GroupMask);
1039 if (dual && (c->modrm >> 6) == 3)
d65b1dee 1040 c->d |= group2_table[group].flags;
e09d082c 1041 else
d65b1dee 1042 c->d |= group_table[group].flags;
e09d082c
AK		 1043 }
1044
1045 /* Unrecognised? */
047a4818 1046 if (c->d == 0 || (c->d & Undefined)) {
e09d082c
AK		 1047 DPRINTF("Cannot emulate %02x\n", c->b);
1048 return -1;
6aa8b732
AK		 1049 }
1050
6e3d5dfb
AK		 1051 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1052 c->op_bytes = 8;
1053
6aa8b732 1054 /* ModRM and SIB bytes. */
1c73ef66
AK		 1055 if (c->d & ModRM)
1056 rc = decode_modrm(ctxt, ops);
1057 else if (c->d & MemAbs)
1058 rc = decode_abs(ctxt, ops);
3e2815e9 1059 if (rc != X86EMUL_CONTINUE)
1c73ef66 1060 goto done;
6aa8b732 1061
7a5b56df
AK		 1062 if (!c->has_seg_override)
1063 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1064
7a5b56df 1065 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1066 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1067
1068 if (c->ad_bytes != 8)
1069 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1070
1071 if (c->rip_relative)
1072 c->modrm_ea += c->eip;
1073
6aa8b732
AK		 1074 /*
1075 * Decode and fetch the source operand: register, memory
1076 * or immediate.
1077 */
e4e03ded 1078 switch (c->d & SrcMask) {
6aa8b732
AK		 1079 case SrcNone:
1080 break;
1081 case SrcReg:
9f1ef3f8 1082 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1083 break;
1084 case SrcMem16:
e4e03ded 1085 c->src.bytes = 2;
6aa8b732
AK		 1086 goto srcmem_common;
1087 case SrcMem32:
e4e03ded 1088 c->src.bytes = 4;
6aa8b732
AK		 1089 goto srcmem_common;
1090 case SrcMem:
e4e03ded
LV		 1091 c->src.bytes = (c->d & ByteOp) ? 1 :
1092 c->op_bytes;
b85b9ee9 1093 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1094 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1095 break;
d77c26fc 1096 srcmem_common:
4e62417b
AJ		 1097 /*
1098 * For instructions with a ModR/M byte, switch to register
1099 * access if Mod = 3.
1100 */
e4e03ded
LV		 1101 if ((c->d & ModRM) && c->modrm_mod == 3) {
1102 c->src.type = OP_REG;
66b85505 1103 c->src.val = c->modrm_val;
107d6d2e 1104 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1105 break;
1106 }
e4e03ded 1107 c->src.type = OP_MEM;
69f55cb1
GN		 1108 c->src.ptr = (unsigned long *)c->modrm_ea;
1109 c->src.val = 0;
6aa8b732
AK		 1110 break;
1111 case SrcImm:
c9eaf20f 1112 case SrcImmU:
e4e03ded
LV		 1113 c->src.type = OP_IMM;
1114 c->src.ptr = (unsigned long *)c->eip;
1115 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1116 if (c->src.bytes == 8)
1117 c->src.bytes = 4;
6aa8b732 1118 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1119 switch (c->src.bytes) {
6aa8b732 1120 case 1:
e4e03ded 1121 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1122 break;
1123 case 2:
e4e03ded 1124 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1125 break;
1126 case 4:
e4e03ded 1127 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1128 break;
1129 }
c9eaf20f
AK		 1130 if ((c->d & SrcMask) == SrcImmU) {
1131 switch (c->src.bytes) {
1132 case 1:
1133 c->src.val &= 0xff;
1134 break;
1135 case 2:
1136 c->src.val &= 0xffff;
1137 break;
1138 case 4:
1139 c->src.val &= 0xffffffff;
1140 break;
1141 }
1142 }
6aa8b732
AK		 1143 break;
1144 case SrcImmByte:
341de7e3 1145 case SrcImmUByte:
e4e03ded
LV		 1146 c->src.type = OP_IMM;
1147 c->src.ptr = (unsigned long *)c->eip;
1148 c->src.bytes = 1;
341de7e3
GN		 1149 if ((c->d & SrcMask) == SrcImmByte)
1150 c->src.val = insn_fetch(s8, 1, c->eip);
1151 else
1152 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1153 break;
5d55f299
WY		 1154 case SrcAcc:
1155 c->src.type = OP_REG;
1156 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1157 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1158 switch (c->src.bytes) {
1159 case 1:
1160 c->src.val = *(u8 *)c->src.ptr;
1161 break;
1162 case 2:
1163 c->src.val = *(u16 *)c->src.ptr;
1164 break;
1165 case 4:
1166 c->src.val = *(u32 *)c->src.ptr;
1167 break;
1168 case 8:
1169 c->src.val = *(u64 *)c->src.ptr;
1170 break;
1171 }
1172 break;
bfcadf83
GT		 1173 case SrcOne:
1174 c->src.bytes = 1;
1175 c->src.val = 1;
1176 break;
a682e354
GN		 1177 case SrcSI:
1178 c->src.type = OP_MEM;
1179 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1180 c->src.ptr = (unsigned long *)
79168fd1 1181 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1182 c->regs[VCPU_REGS_RSI]);
1183 c->src.val = 0;
1184 break;
414e6277
GN		 1185 case SrcImmFAddr:
1186 c->src.type = OP_IMM;
1187 c->src.ptr = (unsigned long *)c->eip;
1188 c->src.bytes = c->op_bytes + 2;
1189 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1190 break;
1191 case SrcMemFAddr:
1192 c->src.type = OP_MEM;
1193 c->src.ptr = (unsigned long *)c->modrm_ea;
1194 c->src.bytes = c->op_bytes + 2;
1195 break;
6aa8b732
AK		 1196 }
1197
0dc8d10f
GT		 1198 /*
1199 * Decode and fetch the second source operand: register, memory
1200 * or immediate.
1201 */
1202 switch (c->d & Src2Mask) {
1203 case Src2None:
1204 break;
1205 case Src2CL:
1206 c->src2.bytes = 1;
1207 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1208 break;
1209 case Src2ImmByte:
1210 c->src2.type = OP_IMM;
1211 c->src2.ptr = (unsigned long *)c->eip;
1212 c->src2.bytes = 1;
1213 c->src2.val = insn_fetch(u8, 1, c->eip);
1214 break;
1215 case Src2One:
1216 c->src2.bytes = 1;
1217 c->src2.val = 1;
1218 break;
1219 }
1220
038e51de 1221 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1222 switch (c->d & DstMask) {
038e51de
AK		 1223 case ImplicitOps:
1224 /* Special instructions do their own operand decoding. */
8b4caf66 1225 return 0;
038e51de 1226 case DstReg:
9f1ef3f8 1227 decode_register_operand(&c->dst, c,
3c118e24 1228 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1229 break;
1230 case DstMem:
6550e1f1 1231 case DstMem64:
e4e03ded 1232 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1233 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1234 c->dst.type = OP_REG;
66b85505 1235 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1236 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1237 break;
1238 }
8b4caf66 1239 c->dst.type = OP_MEM;
69f55cb1 1240 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1241 if ((c->d & DstMask) == DstMem64)
1242 c->dst.bytes = 8;
1243 else
1244 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1245 c->dst.val = 0;
1246 if (c->d & BitOp) {
1247 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1248
1249 c->dst.ptr = (void *)c->dst.ptr +
1250 (c->src.val & mask) / 8;
1251 }
8b4caf66 1252 break;
9c9fddd0
GT		 1253 case DstAcc:
1254 c->dst.type = OP_REG;
d6d367d6 1255 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1256 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1257 switch (c->dst.bytes) {
9c9fddd0
GT		 1258 case 1:
1259 c->dst.val = *(u8 *)c->dst.ptr;
1260 break;
1261 case 2:
1262 c->dst.val = *(u16 *)c->dst.ptr;
1263 break;
1264 case 4:
1265 c->dst.val = *(u32 *)c->dst.ptr;
1266 break;
d6d367d6
GN		 1267 case 8:
1268 c->dst.val = *(u64 *)c->dst.ptr;
1269 break;
9c9fddd0
GT		 1270 }
1271 c->dst.orig_val = c->dst.val;
1272 break;
a682e354
GN		 1273 case DstDI:
1274 c->dst.type = OP_MEM;
1275 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1276 c->dst.ptr = (unsigned long *)
79168fd1 1277 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1278 c->regs[VCPU_REGS_RDI]);
1279 c->dst.val = 0;
1280 break;
8b4caf66
LV		 1281 }
1282
1283done:
1284 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1285}
1286
9de41573
GN		 1287static int read_emulated(struct x86_emulate_ctxt *ctxt,
1288 struct x86_emulate_ops *ops,
1289 unsigned long addr, void *dest, unsigned size)
1290{
1291 int rc;
1292 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1293 u32 err;
9de41573
GN		 1294
1295 while (size) {
1296 int n = min(size, 8u);
1297 size -= n;
1298 if (mc->pos < mc->end)
1299 goto read_cached;
1300
8fe681e9
GN		 1301 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1302 ctxt->vcpu);
1303 if (rc == X86EMUL_PROPAGATE_FAULT)
54b8486f 1304 emulate_pf(ctxt, addr, err);
9de41573
GN		 1305 if (rc != X86EMUL_CONTINUE)
1306 return rc;
1307 mc->end += n;
1308
1309 read_cached:
1310 memcpy(dest, mc->data + mc->pos, n);
1311 mc->pos += n;
1312 dest += n;
1313 addr += n;
1314 }
1315 return X86EMUL_CONTINUE;
1316}
1317
7b262e90
GN		 1318static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1319 struct x86_emulate_ops *ops,
1320 unsigned int size, unsigned short port,
1321 void *dest)
1322{
1323 struct read_cache *rc = &ctxt->decode.io_read;
1324
1325 if (rc->pos == rc->end) { /* refill pio read ahead */
1326 struct decode_cache *c = &ctxt->decode;
1327 unsigned int in_page, n;
1328 unsigned int count = c->rep_prefix ?
1329 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1330 in_page = (ctxt->eflags & EFLG_DF) ?
1331 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1332 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1333 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1334 count);
1335 if (n == 0)
1336 n = 1;
1337 rc->pos = rc->end = 0;
1338 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1339 return 0;
1340 rc->end = n * size;
1341 }
1342
1343 memcpy(dest, rc->data + rc->pos, size);
1344 rc->pos += size;
1345 return 1;
1346}
1347
38ba30ba
GN		 1348static u32 desc_limit_scaled(struct desc_struct *desc)
1349{
1350 u32 limit = get_desc_limit(desc);
1351
1352 return desc->g ? (limit << 12) | 0xfff : limit;
1353}
1354
1355static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1356 struct x86_emulate_ops *ops,
1357 u16 selector, struct desc_ptr *dt)
1358{
1359 if (selector & 1 << 2) {
1360 struct desc_struct desc;
1361 memset (dt, 0, sizeof *dt);
1362 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1363 return;
1364
1365 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1366 dt->address = get_desc_base(&desc);
1367 } else
1368 ops->get_gdt(dt, ctxt->vcpu);
1369}
1370
1371/* allowed just for 8 bytes segments */
1372static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1373 struct x86_emulate_ops *ops,
1374 u16 selector, struct desc_struct *desc)
1375{
1376 struct desc_ptr dt;
1377 u16 index = selector >> 3;
1378 int ret;
1379 u32 err;
1380 ulong addr;
1381
1382 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1383
1384 if (dt.size < index * 8 + 7) {
54b8486f 1385 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1386 return X86EMUL_PROPAGATE_FAULT;
1387 }
1388 addr = dt.address + index * 8;
1389 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1390 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1391 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1392
1393 return ret;
1394}
1395
1396/* allowed just for 8 bytes segments */
1397static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1398 struct x86_emulate_ops *ops,
1399 u16 selector, struct desc_struct *desc)
1400{
1401 struct desc_ptr dt;
1402 u16 index = selector >> 3;
1403 u32 err;
1404 ulong addr;
1405 int ret;
1406
1407 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1408
1409 if (dt.size < index * 8 + 7) {
54b8486f 1410 emulate_gp(ctxt, selector & 0xfffc);
38ba30ba
GN		 1411 return X86EMUL_PROPAGATE_FAULT;
1412 }
1413
1414 addr = dt.address + index * 8;
1415 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1416 if (ret == X86EMUL_PROPAGATE_FAULT)
54b8486f 1417 emulate_pf(ctxt, addr, err);
38ba30ba
GN		 1418
1419 return ret;
1420}
1421
1422static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1423 struct x86_emulate_ops *ops,
1424 u16 selector, int seg)
1425{
1426 struct desc_struct seg_desc;
1427 u8 dpl, rpl, cpl;
1428 unsigned err_vec = GP_VECTOR;
1429 u32 err_code = 0;
1430 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1431 int ret;
1432
1433 memset(&seg_desc, 0, sizeof seg_desc);
1434
1435 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1436 || ctxt->mode == X86EMUL_MODE_REAL) {
1437 /* set real mode segment descriptor */
1438 set_desc_base(&seg_desc, selector << 4);
1439 set_desc_limit(&seg_desc, 0xffff);
1440 seg_desc.type = 3;
1441 seg_desc.p = 1;
1442 seg_desc.s = 1;
1443 goto load;
1444 }
1445
1446 /* NULL selector is not valid for TR, CS and SS */
1447 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1448 && null_selector)
1449 goto exception;
1450
1451 /* TR should be in GDT only */
1452 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1453 goto exception;
1454
1455 if (null_selector) /* for NULL selector skip all following checks */
1456 goto load;
1457
1458 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1459 if (ret != X86EMUL_CONTINUE)
1460 return ret;
1461
1462 err_code = selector & 0xfffc;
1463 err_vec = GP_VECTOR;
1464
1465 /* can't load system descriptor into segment selecor */
1466 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1467 goto exception;
1468
1469 if (!seg_desc.p) {
1470 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1471 goto exception;
1472 }
1473
1474 rpl = selector & 3;
1475 dpl = seg_desc.dpl;
1476 cpl = ops->cpl(ctxt->vcpu);
1477
1478 switch (seg) {
1479 case VCPU_SREG_SS:
1480 /*
1481 * segment is not a writable data segment or segment
1482 * selector's RPL != CPL or segment selector's RPL != CPL
1483 */
1484 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1485 goto exception;
1486 break;
1487 case VCPU_SREG_CS:
1488 if (!(seg_desc.type & 8))
1489 goto exception;
1490
1491 if (seg_desc.type & 4) {
1492 /* conforming */
1493 if (dpl > cpl)
1494 goto exception;
1495 } else {
1496 /* nonconforming */
1497 if (rpl > cpl || dpl != cpl)
1498 goto exception;
1499 }
1500 /* CS(RPL) <- CPL */
1501 selector = (selector & 0xfffc) | cpl;
1502 break;
1503 case VCPU_SREG_TR:
1504 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1505 goto exception;
1506 break;
1507 case VCPU_SREG_LDTR:
1508 if (seg_desc.s || seg_desc.type != 2)
1509 goto exception;
1510 break;
1511 default: /* DS, ES, FS, or GS */
1512 /*
1513 * segment is not a data or readable code segment or
1514 * ((segment is a data or nonconforming code segment)
1515 * and (both RPL and CPL > DPL))
1516 */
1517 if ((seg_desc.type & 0xa) == 0x8 ||
1518 (((seg_desc.type & 0xc) != 0xc) &&
1519 (rpl > dpl && cpl > dpl)))
1520 goto exception;
1521 break;
1522 }
1523
1524 if (seg_desc.s) {
1525 /* mark segment as accessed */
1526 seg_desc.type |= 1;
1527 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1528 if (ret != X86EMUL_CONTINUE)
1529 return ret;
1530 }
1531load:
1532 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1533 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1534 return X86EMUL_CONTINUE;
1535exception:
54b8486f 1536 emulate_exception(ctxt, err_vec, err_code, true);
38ba30ba
GN		 1537 return X86EMUL_PROPAGATE_FAULT;
1538}
1539
c37eda13
WY		 1540static inline int writeback(struct x86_emulate_ctxt *ctxt,
1541 struct x86_emulate_ops *ops)
1542{
1543 int rc;
1544 struct decode_cache *c = &ctxt->decode;
1545 u32 err;
1546
1547 switch (c->dst.type) {
1548 case OP_REG:
1549 /* The 4-byte case *is* correct:
1550 * in 64-bit mode we zero-extend.
1551 */
1552 switch (c->dst.bytes) {
1553 case 1:
1554 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1555 break;
1556 case 2:
1557 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1558 break;
1559 case 4:
1560 *c->dst.ptr = (u32)c->dst.val;
1561 break; /* 64b: zero-ext */
1562 case 8:
1563 *c->dst.ptr = c->dst.val;
1564 break;
1565 }
1566 break;
1567 case OP_MEM:
1568 if (c->lock_prefix)
1569 rc = ops->cmpxchg_emulated(
1570 (unsigned long)c->dst.ptr,
1571 &c->dst.orig_val,
1572 &c->dst.val,
1573 c->dst.bytes,
1574 &err,
1575 ctxt->vcpu);
1576 else
1577 rc = ops->write_emulated(
1578 (unsigned long)c->dst.ptr,
1579 &c->dst.val,
1580 c->dst.bytes,
1581 &err,
1582 ctxt->vcpu);
1583 if (rc == X86EMUL_PROPAGATE_FAULT)
1584 emulate_pf(ctxt,
1585 (unsigned long)c->dst.ptr, err);
1586 if (rc != X86EMUL_CONTINUE)
1587 return rc;
1588 break;
1589 case OP_NONE:
1590 /* no writeback */
1591 break;
1592 default:
1593 break;
1594 }
1595 return X86EMUL_CONTINUE;
1596}
1597
79168fd1
GN		 1598static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1599 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1600{
1601 struct decode_cache *c = &ctxt->decode;
1602
1603 c->dst.type = OP_MEM;
1604 c->dst.bytes = c->op_bytes;
1605 c->dst.val = c->src.val;
7a957275 1606 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1607 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1608 c->regs[VCPU_REGS_RSP]);
1609}
1610
faa5a3ae 1611static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1612 struct x86_emulate_ops *ops,
1613 void *dest, int len)
8cdbd2c9
LV		 1614{
1615 struct decode_cache *c = &ctxt->decode;
1616 int rc;
1617
79168fd1 1618 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1619 c->regs[VCPU_REGS_RSP]),
1620 dest, len);
b60d513c 1621 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1622 return rc;
1623
350f69dc 1624 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1625 return rc;
1626}
8cdbd2c9 1627
d4c6a154
GN		 1628static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1629 struct x86_emulate_ops *ops,
1630 void *dest, int len)
1631{
1632 int rc;
1633 unsigned long val, change_mask;
1634 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1635 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1636
1637 rc = emulate_pop(ctxt, ops, &val, len);
1638 if (rc != X86EMUL_CONTINUE)
1639 return rc;
1640
1641 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1642 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1643
1644 switch(ctxt->mode) {
1645 case X86EMUL_MODE_PROT64:
1646 case X86EMUL_MODE_PROT32:
1647 case X86EMUL_MODE_PROT16:
1648 if (cpl == 0)
1649 change_mask |= EFLG_IOPL;
1650 if (cpl <= iopl)
1651 change_mask |= EFLG_IF;
1652 break;
1653 case X86EMUL_MODE_VM86:
1654 if (iopl < 3) {
54b8486f 1655 emulate_gp(ctxt, 0);
d4c6a154
GN		 1656 return X86EMUL_PROPAGATE_FAULT;
1657 }
1658 change_mask |= EFLG_IF;
1659 break;
1660 default: /* real mode */
1661 change_mask |= (EFLG_IOPL | EFLG_IF);
1662 break;
1663 }
1664
1665 *(unsigned long *)dest =
1666 (ctxt->eflags & ~change_mask) | (val & change_mask);
1667
1668 return rc;
1669}
1670
79168fd1
GN		 1671static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1672 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1673{
1674 struct decode_cache *c = &ctxt->decode;
0934ac9d 1675
79168fd1 1676 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1677
79168fd1 1678 emulate_push(ctxt, ops);
0934ac9d
MG		 1679}
1680
1681static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1682 struct x86_emulate_ops *ops, int seg)
1683{
1684 struct decode_cache *c = &ctxt->decode;
1685 unsigned long selector;
1686 int rc;
1687
1688 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1689 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1690 return rc;
1691
2e873022 1692 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1693 return rc;
1694}
1695
c37eda13 1696static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
79168fd1 1697 struct x86_emulate_ops *ops)
abcf14b5
MG		 1698{
1699 struct decode_cache *c = &ctxt->decode;
1700 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
c37eda13 1701 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1702 int reg = VCPU_REGS_RAX;
1703
1704 while (reg <= VCPU_REGS_RDI) {
1705 (reg == VCPU_REGS_RSP) ?
1706 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1707
79168fd1 1708 emulate_push(ctxt, ops);
c37eda13
WY		 1709
1710 rc = writeback(ctxt, ops);
1711 if (rc != X86EMUL_CONTINUE)
1712 return rc;
1713
abcf14b5
MG		 1714 ++reg;
1715 }
c37eda13
WY		 1716
1717 /* Disable writeback. */
1718 c->dst.type = OP_NONE;
1719
1720 return rc;
abcf14b5
MG		 1721}
1722
1723static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1724 struct x86_emulate_ops *ops)
1725{
1726 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1727 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1728 int reg = VCPU_REGS_RDI;
1729
1730 while (reg >= VCPU_REGS_RAX) {
1731 if (reg == VCPU_REGS_RSP) {
1732 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1733 c->op_bytes);
1734 --reg;
1735 }
1736
1737 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1738 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1739 break;
1740 --reg;
1741 }
1742 return rc;
1743}
1744
62bd430e
MG		 1745static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1746 struct x86_emulate_ops *ops)
1747{
1748 struct decode_cache *c = &ctxt->decode;
1749 int rc = X86EMUL_CONTINUE;
1750 unsigned long temp_eip = 0;
1751 unsigned long temp_eflags = 0;
1752 unsigned long cs = 0;
1753 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1754 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1755 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1756 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1757
1758 /* TODO: Add stack limit check */
1759
1760 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1761
1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
1764
1765 if (temp_eip & ~0xffff) {
1766 emulate_gp(ctxt, 0);
1767 return X86EMUL_PROPAGATE_FAULT;
1768 }
1769
1770 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1771
1772 if (rc != X86EMUL_CONTINUE)
1773 return rc;
1774
1775 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1776
1777 if (rc != X86EMUL_CONTINUE)
1778 return rc;
1779
1780 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1781
1782 if (rc != X86EMUL_CONTINUE)
1783 return rc;
1784
1785 c->eip = temp_eip;
1786
1787
1788 if (c->op_bytes == 4)
1789 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1790 else if (c->op_bytes == 2) {
1791 ctxt->eflags &= ~0xffff;
1792 ctxt->eflags |= temp_eflags;
1793 }
1794
1795 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1796 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1797
1798 return rc;
1799}
1800
1801static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1802 struct x86_emulate_ops* ops)
1803{
1804 switch(ctxt->mode) {
1805 case X86EMUL_MODE_REAL:
1806 return emulate_iret_real(ctxt, ops);
1807 case X86EMUL_MODE_VM86:
1808 case X86EMUL_MODE_PROT16:
1809 case X86EMUL_MODE_PROT32:
1810 case X86EMUL_MODE_PROT64:
1811 default:
1812 /* iret from protected mode unimplemented yet */
1813 return X86EMUL_UNHANDLEABLE;
1814 }
1815}
1816
faa5a3ae
AK		 1817static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1818 struct x86_emulate_ops *ops)
1819{
1820 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1821
1b30eaa8 1822 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1823}
1824
05f086f8 1825static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1826{
05f086f8 1827 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1828 switch (c->modrm_reg) {
1829 case 0: /* rol */
05f086f8 1830 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1831 break;
1832 case 1: /* ror */
05f086f8 1833 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1834 break;
1835 case 2: /* rcl */
05f086f8 1836 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1837 break;
1838 case 3: /* rcr */
05f086f8 1839 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1840 break;
1841 case 4: /* sal/shl */
1842 case 6: /* sal/shl */
05f086f8 1843 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1844 break;
1845 case 5: /* shr */
05f086f8 1846 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1847 break;
1848 case 7: /* sar */
05f086f8 1849 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1850 break;
1851 }
1852}
1853
1854static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1855 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1856{
1857 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1858
1859 switch (c->modrm_reg) {
1860 case 0 ... 1: /* test */
05f086f8 1861 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1862 break;
1863 case 2: /* not */
1864 c->dst.val = ~c->dst.val;
1865 break;
1866 case 3: /* neg */
05f086f8 1867 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1868 break;
1869 default:
aca06a83 1870 return 0;
8cdbd2c9 1871 }
aca06a83 1872 return 1;
8cdbd2c9
LV		 1873}
1874
1875static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1876 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1877{
1878 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1879
1880 switch (c->modrm_reg) {
1881 case 0: /* inc */
05f086f8 1882 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1883 break;
1884 case 1: /* dec */
05f086f8 1885 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1886 break;
d19292e4
MG		 1887 case 2: /* call near abs */ {
1888 long int old_eip;
1889 old_eip = c->eip;
1890 c->eip = c->src.val;
1891 c->src.val = old_eip;
79168fd1 1892 emulate_push(ctxt, ops);
d19292e4
MG		 1893 break;
1894 }
8cdbd2c9 1895 case 4: /* jmp abs */
fd60754e 1896 c->eip = c->src.val;
8cdbd2c9
LV		 1897 break;
1898 case 6: /* push */
79168fd1 1899 emulate_push(ctxt, ops);
8cdbd2c9 1900 break;
8cdbd2c9 1901 }
1b30eaa8 1902 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1903}
1904
1905static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1906 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1907{
1908 struct decode_cache *c = &ctxt->decode;
16518d5a 1909 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1910
1911 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1912 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1913 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1914 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1915 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1916 } else {
16518d5a
AK		 1917 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1918 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1919
05f086f8 1920 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1921 }
1b30eaa8 1922 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1923}
1924
a77ab5ea
AK		 1925static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1926 struct x86_emulate_ops *ops)
1927{
1928 struct decode_cache *c = &ctxt->decode;
1929 int rc;
1930 unsigned long cs;
1931
1932 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1933 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1934 return rc;
1935 if (c->op_bytes == 4)
1936 c->eip = (u32)c->eip;
1937 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1938 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1939 return rc;
2e873022 1940 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1941 return rc;
1942}
1943
e66bb2cc
AP		 1944static inline void
1945setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1946 struct x86_emulate_ops *ops, struct desc_struct *cs,
1947 struct desc_struct *ss)
e66bb2cc 1948{
79168fd1
GN		 1949 memset(cs, 0, sizeof(struct desc_struct));
1950 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1951 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1952
1953 cs->l = 0; /* will be adjusted later */
79168fd1 1954 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1955 cs->g = 1; /* 4kb granularity */
79168fd1 1956 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1957 cs->type = 0x0b; /* Read, Execute, Accessed */
1958 cs->s = 1;
1959 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1960 cs->p = 1;
1961 cs->d = 1;
e66bb2cc 1962
79168fd1
GN		 1963 set_desc_base(ss, 0); /* flat segment */
1964 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1965 ss->g = 1; /* 4kb granularity */
1966 ss->s = 1;
1967 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1968 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1969 ss->dpl = 0;
79168fd1 1970 ss->p = 1;
e66bb2cc
AP		 1971}
1972
1973static int
3fb1b5db 1974emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1975{
1976 struct decode_cache *c = &ctxt->decode;
79168fd1 1977 struct desc_struct cs, ss;
e66bb2cc 1978 u64 msr_data;
79168fd1 1979 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1980
1981 /* syscall is not available in real mode */
2e901c4c
GN		 1982 if (ctxt->mode == X86EMUL_MODE_REAL ||
1983 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1984 emulate_ud(ctxt);
2e901c4c
GN		 1985 return X86EMUL_PROPAGATE_FAULT;
1986 }
e66bb2cc 1987
79168fd1 1988 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1989
3fb1b5db 1990 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1991 msr_data >>= 32;
79168fd1
GN		 1992 cs_sel = (u16)(msr_data & 0xfffc);
1993 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1994
1995 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1996 cs.d = 0;
e66bb2cc
AP		 1997 cs.l = 1;
1998 }
79168fd1
GN		 1999 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2000 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2001 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2002 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 2003
2004 c->regs[VCPU_REGS_RCX] = c->eip;
2005 if (is_long_mode(ctxt->vcpu)) {
2006#ifdef CONFIG_X86_64
2007 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2008
3fb1b5db
GN		 2009 ops->get_msr(ctxt->vcpu,
2010 ctxt->mode == X86EMUL_MODE_PROT64 ?
2011 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 2012 c->eip = msr_data;
2013
3fb1b5db 2014 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2015 ctxt->eflags &= ~(msr_data | EFLG_RF);
2016#endif
2017 } else {
2018 /* legacy mode */
3fb1b5db 2019 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 2020 c->eip = (u32)msr_data;
2021
2022 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2023 }
2024
e54cfa97 2025 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2026}
2027
8c604352 2028static int
3fb1b5db 2029emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 2030{
2031 struct decode_cache *c = &ctxt->decode;
79168fd1 2032 struct desc_struct cs, ss;
8c604352 2033 u64 msr_data;
79168fd1 2034 u16 cs_sel, ss_sel;
8c604352 2035
a0044755
GN		 2036 /* inject #GP if in real mode */
2037 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 2038 emulate_gp(ctxt, 0);
2e901c4c 2039 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2040 }
2041
2042 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2043 * Therefore, we inject an #UD.
2044 */
2e901c4c 2045 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 2046 emulate_ud(ctxt);
2e901c4c
GN		 2047 return X86EMUL_PROPAGATE_FAULT;
2048 }
8c604352 2049
79168fd1 2050 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 2051
3fb1b5db 2052 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2053 switch (ctxt->mode) {
2054 case X86EMUL_MODE_PROT32:
2055 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2056 emulate_gp(ctxt, 0);
e54cfa97 2057 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2058 }
2059 break;
2060 case X86EMUL_MODE_PROT64:
2061 if (msr_data == 0x0) {
54b8486f 2062 emulate_gp(ctxt, 0);
e54cfa97 2063 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 2064 }
2065 break;
2066 }
2067
2068 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2069 cs_sel = (u16)msr_data;
2070 cs_sel &= ~SELECTOR_RPL_MASK;
2071 ss_sel = cs_sel + 8;
2072 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 2073 if (ctxt->mode == X86EMUL_MODE_PROT64
2074 || is_long_mode(ctxt->vcpu)) {
79168fd1 2075 cs.d = 0;
8c604352
AP		 2076 cs.l = 1;
2077 }
2078
79168fd1
GN		 2079 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2080 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2081 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2082 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 2083
3fb1b5db 2084 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 2085 c->eip = msr_data;
2086
3fb1b5db 2087 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 2088 c->regs[VCPU_REGS_RSP] = msr_data;
2089
e54cfa97 2090 return X86EMUL_CONTINUE;
8c604352
AP		 2091}
2092
4668f050 2093static int
3fb1b5db 2094emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 2095{
2096 struct decode_cache *c = &ctxt->decode;
79168fd1 2097 struct desc_struct cs, ss;
4668f050
AP		 2098 u64 msr_data;
2099 int usermode;
79168fd1 2100 u16 cs_sel, ss_sel;
4668f050 2101
a0044755
GN		 2102 /* inject #GP if in real mode or Virtual 8086 mode */
2103 if (ctxt->mode == X86EMUL_MODE_REAL ||
2104 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 2105 emulate_gp(ctxt, 0);
2e901c4c 2106 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2107 }
2108
79168fd1 2109 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2110
2111 if ((c->rex_prefix & 0x8) != 0x0)
2112 usermode = X86EMUL_MODE_PROT64;
2113 else
2114 usermode = X86EMUL_MODE_PROT32;
2115
2116 cs.dpl = 3;
2117 ss.dpl = 3;
3fb1b5db 2118 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2119 switch (usermode) {
2120 case X86EMUL_MODE_PROT32:
79168fd1 2121 cs_sel = (u16)(msr_data + 16);
4668f050 2122 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 2123 emulate_gp(ctxt, 0);
e54cfa97 2124 return X86EMUL_PROPAGATE_FAULT;
4668f050 2125 }
79168fd1 2126 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2127 break;
2128 case X86EMUL_MODE_PROT64:
79168fd1 2129 cs_sel = (u16)(msr_data + 32);
4668f050 2130 if (msr_data == 0x0) {
54b8486f 2131 emulate_gp(ctxt, 0);
e54cfa97 2132 return X86EMUL_PROPAGATE_FAULT;
4668f050 2133 }
79168fd1
GN		 2134 ss_sel = cs_sel + 8;
2135 cs.d = 0;
4668f050
AP		 2136 cs.l = 1;
2137 break;
2138 }
79168fd1
GN		 2139 cs_sel |= SELECTOR_RPL_MASK;
2140 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2141
79168fd1
GN		 2142 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2143 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2144 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2145 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2146
bdb475a3
GN		 2147 c->eip = c->regs[VCPU_REGS_RDX];
2148 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2149
e54cfa97 2150 return X86EMUL_CONTINUE;
4668f050
AP		 2151}
2152
9c537244
GN		 2153static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2154 struct x86_emulate_ops *ops)
f850e2e6
GN		 2155{
2156 int iopl;
2157 if (ctxt->mode == X86EMUL_MODE_REAL)
2158 return false;
2159 if (ctxt->mode == X86EMUL_MODE_VM86)
2160 return true;
2161 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2162 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2163}
2164
2165static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2166 struct x86_emulate_ops *ops,
2167 u16 port, u16 len)
2168{
79168fd1 2169 struct desc_struct tr_seg;
f850e2e6
GN		 2170 int r;
2171 u16 io_bitmap_ptr;
2172 u8 perm, bit_idx = port & 0x7;
2173 unsigned mask = (1 << len) - 1;
2174
79168fd1
GN		 2175 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2176 if (!tr_seg.p)
f850e2e6 2177 return false;
79168fd1 2178 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2179 return false;
79168fd1
GN		 2180 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2181 ctxt->vcpu, NULL);
f850e2e6
GN		 2182 if (r != X86EMUL_CONTINUE)
2183 return false;
79168fd1 2184 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2185 return false;
79168fd1
GN		 2186 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2187 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2188 if (r != X86EMUL_CONTINUE)
2189 return false;
2190 if ((perm >> bit_idx) & mask)
2191 return false;
2192 return true;
2193}
2194
2195static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2196 struct x86_emulate_ops *ops,
2197 u16 port, u16 len)
2198{
9c537244 2199 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2200 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2201 return false;
2202 return true;
2203}
2204
38ba30ba
GN		 2205static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2206 struct x86_emulate_ops *ops,
2207 struct tss_segment_16 *tss)
2208{
2209 struct decode_cache *c = &ctxt->decode;
2210
2211 tss->ip = c->eip;
2212 tss->flag = ctxt->eflags;
2213 tss->ax = c->regs[VCPU_REGS_RAX];
2214 tss->cx = c->regs[VCPU_REGS_RCX];
2215 tss->dx = c->regs[VCPU_REGS_RDX];
2216 tss->bx = c->regs[VCPU_REGS_RBX];
2217 tss->sp = c->regs[VCPU_REGS_RSP];
2218 tss->bp = c->regs[VCPU_REGS_RBP];
2219 tss->si = c->regs[VCPU_REGS_RSI];
2220 tss->di = c->regs[VCPU_REGS_RDI];
2221
2222 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2223 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2224 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2225 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2226 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2227}
2228
2229static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2230 struct x86_emulate_ops *ops,
2231 struct tss_segment_16 *tss)
2232{
2233 struct decode_cache *c = &ctxt->decode;
2234 int ret;
2235
2236 c->eip = tss->ip;
2237 ctxt->eflags = tss->flag | 2;
2238 c->regs[VCPU_REGS_RAX] = tss->ax;
2239 c->regs[VCPU_REGS_RCX] = tss->cx;
2240 c->regs[VCPU_REGS_RDX] = tss->dx;
2241 c->regs[VCPU_REGS_RBX] = tss->bx;
2242 c->regs[VCPU_REGS_RSP] = tss->sp;
2243 c->regs[VCPU_REGS_RBP] = tss->bp;
2244 c->regs[VCPU_REGS_RSI] = tss->si;
2245 c->regs[VCPU_REGS_RDI] = tss->di;
2246
2247 /*
2248 * SDM says that segment selectors are loaded before segment
2249 * descriptors
2250 */
2251 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2252 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2253 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2254 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2255 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2256
2257 /*
2258 * Now load segment descriptors. If fault happenes at this stage
2259 * it is handled in a context of new task
2260 */
2261 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2262 if (ret != X86EMUL_CONTINUE)
2263 return ret;
2264 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2265 if (ret != X86EMUL_CONTINUE)
2266 return ret;
2267 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2268 if (ret != X86EMUL_CONTINUE)
2269 return ret;
2270 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2271 if (ret != X86EMUL_CONTINUE)
2272 return ret;
2273 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2274 if (ret != X86EMUL_CONTINUE)
2275 return ret;
2276
2277 return X86EMUL_CONTINUE;
2278}
2279
2280static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2281 struct x86_emulate_ops *ops,
2282 u16 tss_selector, u16 old_tss_sel,
2283 ulong old_tss_base, struct desc_struct *new_desc)
2284{
2285 struct tss_segment_16 tss_seg;
2286 int ret;
2287 u32 err, new_tss_base = get_desc_base(new_desc);
2288
2289 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2290 &err);
2291 if (ret == X86EMUL_PROPAGATE_FAULT) {
2292 /* FIXME: need to provide precise fault address */
54b8486f 2293 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2294 return ret;
2295 }
2296
2297 save_state_to_tss16(ctxt, ops, &tss_seg);
2298
2299 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2300 &err);
2301 if (ret == X86EMUL_PROPAGATE_FAULT) {
2302 /* FIXME: need to provide precise fault address */
54b8486f 2303 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2304 return ret;
2305 }
2306
2307 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2308 &err);
2309 if (ret == X86EMUL_PROPAGATE_FAULT) {
2310 /* FIXME: need to provide precise fault address */
54b8486f 2311 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2312 return ret;
2313 }
2314
2315 if (old_tss_sel != 0xffff) {
2316 tss_seg.prev_task_link = old_tss_sel;
2317
2318 ret = ops->write_std(new_tss_base,
2319 &tss_seg.prev_task_link,
2320 sizeof tss_seg.prev_task_link,
2321 ctxt->vcpu, &err);
2322 if (ret == X86EMUL_PROPAGATE_FAULT) {
2323 /* FIXME: need to provide precise fault address */
54b8486f 2324 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2325 return ret;
2326 }
2327 }
2328
2329 return load_state_from_tss16(ctxt, ops, &tss_seg);
2330}
2331
2332static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2333 struct x86_emulate_ops *ops,
2334 struct tss_segment_32 *tss)
2335{
2336 struct decode_cache *c = &ctxt->decode;
2337
2338 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2339 tss->eip = c->eip;
2340 tss->eflags = ctxt->eflags;
2341 tss->eax = c->regs[VCPU_REGS_RAX];
2342 tss->ecx = c->regs[VCPU_REGS_RCX];
2343 tss->edx = c->regs[VCPU_REGS_RDX];
2344 tss->ebx = c->regs[VCPU_REGS_RBX];
2345 tss->esp = c->regs[VCPU_REGS_RSP];
2346 tss->ebp = c->regs[VCPU_REGS_RBP];
2347 tss->esi = c->regs[VCPU_REGS_RSI];
2348 tss->edi = c->regs[VCPU_REGS_RDI];
2349
2350 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2351 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2352 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2353 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2354 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2355 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2356 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2357}
2358
2359static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2360 struct x86_emulate_ops *ops,
2361 struct tss_segment_32 *tss)
2362{
2363 struct decode_cache *c = &ctxt->decode;
2364 int ret;
2365
0f12244f 2366 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 2367 emulate_gp(ctxt, 0);
0f12244f
GN		 2368 return X86EMUL_PROPAGATE_FAULT;
2369 }
38ba30ba
GN		 2370 c->eip = tss->eip;
2371 ctxt->eflags = tss->eflags | 2;
2372 c->regs[VCPU_REGS_RAX] = tss->eax;
2373 c->regs[VCPU_REGS_RCX] = tss->ecx;
2374 c->regs[VCPU_REGS_RDX] = tss->edx;
2375 c->regs[VCPU_REGS_RBX] = tss->ebx;
2376 c->regs[VCPU_REGS_RSP] = tss->esp;
2377 c->regs[VCPU_REGS_RBP] = tss->ebp;
2378 c->regs[VCPU_REGS_RSI] = tss->esi;
2379 c->regs[VCPU_REGS_RDI] = tss->edi;
2380
2381 /*
2382 * SDM says that segment selectors are loaded before segment
2383 * descriptors
2384 */
2385 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2386 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2387 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2388 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2389 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2390 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2391 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2392
2393 /*
2394 * Now load segment descriptors. If fault happenes at this stage
2395 * it is handled in a context of new task
2396 */
2397 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2398 if (ret != X86EMUL_CONTINUE)
2399 return ret;
2400 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2401 if (ret != X86EMUL_CONTINUE)
2402 return ret;
2403 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2404 if (ret != X86EMUL_CONTINUE)
2405 return ret;
2406 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2407 if (ret != X86EMUL_CONTINUE)
2408 return ret;
2409 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2410 if (ret != X86EMUL_CONTINUE)
2411 return ret;
2412 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2413 if (ret != X86EMUL_CONTINUE)
2414 return ret;
2415 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2416 if (ret != X86EMUL_CONTINUE)
2417 return ret;
2418
2419 return X86EMUL_CONTINUE;
2420}
2421
2422static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2423 struct x86_emulate_ops *ops,
2424 u16 tss_selector, u16 old_tss_sel,
2425 ulong old_tss_base, struct desc_struct *new_desc)
2426{
2427 struct tss_segment_32 tss_seg;
2428 int ret;
2429 u32 err, new_tss_base = get_desc_base(new_desc);
2430
2431 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2432 &err);
2433 if (ret == X86EMUL_PROPAGATE_FAULT) {
2434 /* FIXME: need to provide precise fault address */
54b8486f 2435 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2436 return ret;
2437 }
2438
2439 save_state_to_tss32(ctxt, ops, &tss_seg);
2440
2441 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2442 &err);
2443 if (ret == X86EMUL_PROPAGATE_FAULT) {
2444 /* FIXME: need to provide precise fault address */
54b8486f 2445 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 2446 return ret;
2447 }
2448
2449 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2450 &err);
2451 if (ret == X86EMUL_PROPAGATE_FAULT) {
2452 /* FIXME: need to provide precise fault address */
54b8486f 2453 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2454 return ret;
2455 }
2456
2457 if (old_tss_sel != 0xffff) {
2458 tss_seg.prev_task_link = old_tss_sel;
2459
2460 ret = ops->write_std(new_tss_base,
2461 &tss_seg.prev_task_link,
2462 sizeof tss_seg.prev_task_link,
2463 ctxt->vcpu, &err);
2464 if (ret == X86EMUL_PROPAGATE_FAULT) {
2465 /* FIXME: need to provide precise fault address */
54b8486f 2466 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 2467 return ret;
2468 }
2469 }
2470
2471 return load_state_from_tss32(ctxt, ops, &tss_seg);
2472}
2473
2474static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2475 struct x86_emulate_ops *ops,
2476 u16 tss_selector, int reason,
2477 bool has_error_code, u32 error_code)
38ba30ba
GN		 2478{
2479 struct desc_struct curr_tss_desc, next_tss_desc;
2480 int ret;
2481 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2482 ulong old_tss_base =
5951c442 2483 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2484 u32 desc_limit;
38ba30ba
GN		 2485
2486 /* FIXME: old_tss_base == ~0 ? */
2487
2488 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2489 if (ret != X86EMUL_CONTINUE)
2490 return ret;
2491 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2492 if (ret != X86EMUL_CONTINUE)
2493 return ret;
2494
2495 /* FIXME: check that next_tss_desc is tss */
2496
2497 if (reason != TASK_SWITCH_IRET) {
2498 if ((tss_selector & 3) > next_tss_desc.dpl ||
2499 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 2500 emulate_gp(ctxt, 0);
38ba30ba
GN		 2501 return X86EMUL_PROPAGATE_FAULT;
2502 }
2503 }
2504
ceffb459
GN		 2505 desc_limit = desc_limit_scaled(&next_tss_desc);
2506 if (!next_tss_desc.p ||
2507 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2508 desc_limit < 0x2b)) {
54b8486f 2509 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2510 return X86EMUL_PROPAGATE_FAULT;
2511 }
2512
2513 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2514 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2515 write_segment_descriptor(ctxt, ops, old_tss_sel,
2516 &curr_tss_desc);
2517 }
2518
2519 if (reason == TASK_SWITCH_IRET)
2520 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2521
2522 /* set back link to prev task only if NT bit is set in eflags
2523 note that old_tss_sel is not used afetr this point */
2524 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2525 old_tss_sel = 0xffff;
2526
2527 if (next_tss_desc.type & 8)
2528 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2529 old_tss_base, &next_tss_desc);
2530 else
2531 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2532 old_tss_base, &next_tss_desc);
0760d448
JK		 2533 if (ret != X86EMUL_CONTINUE)
2534 return ret;
38ba30ba
GN		 2535
2536 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2537 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2538
2539 if (reason != TASK_SWITCH_IRET) {
2540 next_tss_desc.type |= (1 << 1); /* set busy flag */
2541 write_segment_descriptor(ctxt, ops, tss_selector,
2542 &next_tss_desc);
2543 }
2544
2545 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2546 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2547 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2548
e269fb21
JK		 2549 if (has_error_code) {
2550 struct decode_cache *c = &ctxt->decode;
2551
2552 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2553 c->lock_prefix = 0;
2554 c->src.val = (unsigned long) error_code;
79168fd1 2555 emulate_push(ctxt, ops);
e269fb21
JK		 2556 }
2557
38ba30ba
GN		 2558 return ret;
2559}
2560
2561int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2562 struct x86_emulate_ops *ops,
e269fb21
JK		 2563 u16 tss_selector, int reason,
2564 bool has_error_code, u32 error_code)
38ba30ba
GN		 2565{
2566 struct decode_cache *c = &ctxt->decode;
2567 int rc;
2568
38ba30ba 2569 c->eip = ctxt->eip;
e269fb21 2570 c->dst.type = OP_NONE;
38ba30ba 2571
e269fb21
JK		 2572 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2573 has_error_code, error_code);
38ba30ba
GN		 2574
2575 if (rc == X86EMUL_CONTINUE) {
e269fb21 2576 rc = writeback(ctxt, ops);
95c55886
GN		 2577 if (rc == X86EMUL_CONTINUE)
2578 ctxt->eip = c->eip;
38ba30ba
GN		 2579 }
2580
19d04437 2581 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2582}
2583
a682e354 2584static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2585 int reg, struct operand *op)
a682e354
GN		 2586{
2587 struct decode_cache *c = &ctxt->decode;
2588 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2589
d9271123
GN		 2590 register_address_increment(c, &c->regs[reg], df * op->bytes);
2591 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2592}
2593
8b4caf66 2594int
1be3aa47 2595x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2596{
8b4caf66 2597 u64 msr_data;
8b4caf66 2598 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2599 int rc = X86EMUL_CONTINUE;
5cd21917 2600 int saved_dst_type = c->dst.type;
8b4caf66 2601
9de41573 2602 ctxt->decode.mem_read.pos = 0;
310b5d30 2603
1161624f 2604 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2605 emulate_ud(ctxt);
1161624f
GN		 2606 goto done;
2607 }
2608
d380a5e4 2609 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2610 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2611 emulate_ud(ctxt);
d380a5e4
GN		 2612 goto done;
2613 }
2614
e92805ac 2615 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2616 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2617 emulate_gp(ctxt, 0);
e92805ac
GN		 2618 goto done;
2619 }
2620
b9fa9d6b 2621 if (c->rep_prefix && (c->d & String)) {
5cd21917 2622 ctxt->restart = true;
b9fa9d6b 2623 /* All REP prefixes have the same first termination condition */
c73e197b 2624 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2625 string_done:
2626 ctxt->restart = false;
95c55886 2627 ctxt->eip = c->eip;
b9fa9d6b
AK		 2628 goto done;
2629 }
2630 /* The second termination condition only applies for REPE
2631 * and REPNE. Test if the repeat string operation prefix is
2632 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2633 * corresponding termination condition according to:
2634 * - if REPE/REPZ and ZF = 0 then done
2635 * - if REPNE/REPNZ and ZF = 1 then done
2636 */
2637 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2638 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2639 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2640 ((ctxt->eflags & EFLG_ZF) == 0))
2641 goto string_done;
b9fa9d6b 2642 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2643 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2644 goto string_done;
b9fa9d6b 2645 }
063db061 2646 c->eip = ctxt->eip;
b9fa9d6b
AK		 2647 }
2648
8b4caf66 2649 if (c->src.type == OP_MEM) {
9de41573 2650 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2651 c->src.valptr, c->src.bytes);
b60d513c 2652 if (rc != X86EMUL_CONTINUE)
8b4caf66 2653 goto done;
16518d5a 2654 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2655 }
2656
e35b7b9c 2657 if (c->src2.type == OP_MEM) {
9de41573
GN		 2658 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2659 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2660 if (rc != X86EMUL_CONTINUE)
2661 goto done;
2662 }
2663
8b4caf66
LV		 2664 if ((c->d & DstMask) == ImplicitOps)
2665 goto special_insn;
2666
2667
69f55cb1
GN		 2668 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2669 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2670 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2671 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2672 if (rc != X86EMUL_CONTINUE)
2673 goto done;
038e51de 2674 }
e4e03ded 2675 c->dst.orig_val = c->dst.val;
038e51de 2676
018a98db
AK		 2677special_insn:
2678
e4e03ded 2679 if (c->twobyte)
6aa8b732
AK		 2680 goto twobyte_insn;
2681
e4e03ded 2682 switch (c->b) {
6aa8b732
AK		 2683 case 0x00 ... 0x05:
2684 add: /* add */
05f086f8 2685 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2686 break;
0934ac9d 2687 case 0x06: /* push es */
79168fd1 2688 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2689 break;
2690 case 0x07: /* pop es */
0934ac9d 2691 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2692 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2693 goto done;
2694 break;
6aa8b732
AK		 2695 case 0x08 ... 0x0d:
2696 or: /* or */
05f086f8 2697 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2698 break;
0934ac9d 2699 case 0x0e: /* push cs */
79168fd1 2700 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2701 break;
6aa8b732
AK		 2702 case 0x10 ... 0x15:
2703 adc: /* adc */
05f086f8 2704 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2705 break;
0934ac9d 2706 case 0x16: /* push ss */
79168fd1 2707 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2708 break;
2709 case 0x17: /* pop ss */
0934ac9d 2710 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2711 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2712 goto done;
2713 break;
6aa8b732
AK		 2714 case 0x18 ... 0x1d:
2715 sbb: /* sbb */
05f086f8 2716 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2717 break;
0934ac9d 2718 case 0x1e: /* push ds */
79168fd1 2719 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2720 break;
2721 case 0x1f: /* pop ds */
0934ac9d 2722 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2723 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2724 goto done;
2725 break;
aa3a816b 2726 case 0x20 ... 0x25:
6aa8b732 2727 and: /* and */
05f086f8 2728 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2729 break;
2730 case 0x28 ... 0x2d:
2731 sub: /* sub */
05f086f8 2732 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2733 break;
2734 case 0x30 ... 0x35:
2735 xor: /* xor */
05f086f8 2736 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2737 break;
2738 case 0x38 ... 0x3d:
2739 cmp: /* cmp */
05f086f8 2740 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2741 break;
33615aa9
AK		 2742 case 0x40 ... 0x47: /* inc r16/r32 */
2743 emulate_1op("inc", c->dst, ctxt->eflags);
2744 break;
2745 case 0x48 ... 0x4f: /* dec r16/r32 */
2746 emulate_1op("dec", c->dst, ctxt->eflags);
2747 break;
2748 case 0x50 ... 0x57: /* push reg */
79168fd1 2749 emulate_push(ctxt, ops);
33615aa9
AK		 2750 break;
2751 case 0x58 ... 0x5f: /* pop reg */
2752 pop_instruction:
350f69dc 2753 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2754 if (rc != X86EMUL_CONTINUE)
33615aa9 2755 goto done;
33615aa9 2756 break;
abcf14b5 2757 case 0x60: /* pusha */
c37eda13
WY		 2758 rc = emulate_pusha(ctxt, ops);
2759 if (rc != X86EMUL_CONTINUE)
2760 goto done;
abcf14b5
MG		 2761 break;
2762 case 0x61: /* popa */
2763 rc = emulate_popa(ctxt, ops);
1b30eaa8 2764 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2765 goto done;
2766 break;
6aa8b732 2767 case 0x63: /* movsxd */
8b4caf66 2768 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2769 goto cannot_emulate;
e4e03ded 2770 c->dst.val = (s32) c->src.val;
6aa8b732 2771 break;
91ed7a0e 2772 case 0x68: /* push imm */
018a98db 2773 case 0x6a: /* push imm8 */
79168fd1 2774 emulate_push(ctxt, ops);
018a98db
AK		 2775 break;
2776 case 0x6c: /* insb */
2777 case 0x6d: /* insw/insd */
7972995b 2778 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2779 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2780 c->dst.bytes)) {
54b8486f 2781 emulate_gp(ctxt, 0);
f850e2e6
GN		 2782 goto done;
2783 }
7b262e90
GN		 2784 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2785 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2786 goto done; /* IO is needed, skip writeback */
2787 break;
018a98db
AK		 2788 case 0x6e: /* outsb */
2789 case 0x6f: /* outsw/outsd */
7972995b 2790 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2791 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2792 c->src.bytes)) {
54b8486f 2793 emulate_gp(ctxt, 0);
f850e2e6
GN		 2794 goto done;
2795 }
7972995b
GN		 2796 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2797 &c->src.val, 1, ctxt->vcpu);
2798
2799 c->dst.type = OP_NONE; /* nothing to writeback */
2800 break;
b2833e3c 2801 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2802 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2803 jmp_rel(c, c->src.val);
018a98db 2804 break;
6aa8b732 2805 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2806 switch (c->modrm_reg) {
6aa8b732
AK		 2807 case 0:
2808 goto add;
2809 case 1:
2810 goto or;
2811 case 2:
2812 goto adc;
2813 case 3:
2814 goto sbb;
2815 case 4:
2816 goto and;
2817 case 5:
2818 goto sub;
2819 case 6:
2820 goto xor;
2821 case 7:
2822 goto cmp;
2823 }
2824 break;
2825 case 0x84 ... 0x85:
dfb507c4 2826 test:
05f086f8 2827 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2828 break;
2829 case 0x86 ... 0x87: /* xchg */
b13354f8 2830 xchg:
6aa8b732 2831 /* Write back the register source. */
e4e03ded 2832 switch (c->dst.bytes) {
6aa8b732 2833 case 1:
e4e03ded 2834 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2835 break;
2836 case 2:
e4e03ded 2837 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2838 break;
2839 case 4:
e4e03ded 2840 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2841 break; /* 64b reg: zero-extend */
2842 case 8:
e4e03ded 2843 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2844 break;
2845 }
2846 /*
2847 * Write back the memory destination with implicit LOCK
2848 * prefix.
2849 */
e4e03ded
LV		 2850 c->dst.val = c->src.val;
2851 c->lock_prefix = 1;
6aa8b732 2852 break;
6aa8b732 2853 case 0x88 ... 0x8b: /* mov */
7de75248 2854 goto mov;
79168fd1
GN		 2855 case 0x8c: /* mov r/m, sreg */
2856 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2857 emulate_ud(ctxt);
5e3ae6c5 2858 goto done;
38d5bc6d 2859 }
79168fd1 2860 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2861 break;
7e0b54b1 2862 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2863 c->dst.val = c->modrm_ea;
7e0b54b1 2864 break;
4257198a
GT		 2865 case 0x8e: { /* mov seg, r/m16 */
2866 uint16_t sel;
4257198a
GT		 2867
2868 sel = c->src.val;
8b9f4414 2869
c697518a
GN		 2870 if (c->modrm_reg == VCPU_SREG_CS ||
2871 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2872 emulate_ud(ctxt);
8b9f4414
GN		 2873 goto done;
2874 }
2875
310b5d30 2876 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2877 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2878
2e873022 2879 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2880
2881 c->dst.type = OP_NONE; /* Disable writeback. */
2882 break;
2883 }
6aa8b732 2884 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2885 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2886 if (rc != X86EMUL_CONTINUE)
6aa8b732 2887 goto done;
6aa8b732 2888 break;
b13354f8 2889 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2890 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2891 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2892 break;
2893 }
2894 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2895 c->src.type = OP_REG;
2896 c->src.bytes = c->op_bytes;
b13354f8
MG		 2897 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2898 c->src.val = *(c->src.ptr);
2899 goto xchg;
fd2a7608 2900 case 0x9c: /* pushf */
05f086f8 2901 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2902 emulate_push(ctxt, ops);
8cdbd2c9 2903 break;
535eabcf 2904 case 0x9d: /* popf */
2b48cc75 2905 c->dst.type = OP_REG;
05f086f8 2906 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2907 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2908 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2909 if (rc != X86EMUL_CONTINUE)
2910 goto done;
2911 break;
5d55f299 2912 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2913 case 0xa4 ... 0xa5: /* movs */
a682e354 2914 goto mov;
6aa8b732 2915 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2916 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2917 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2918 goto cmp;
dfb507c4
MG		 2919 case 0xa8 ... 0xa9: /* test ax, imm */
2920 goto test;
6aa8b732 2921 case 0xaa ... 0xab: /* stos */
e4e03ded 2922 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2923 break;
2924 case 0xac ... 0xad: /* lods */
a682e354 2925 goto mov;
6aa8b732
AK		 2926 case 0xae ... 0xaf: /* scas */
2927 DPRINTF("Urk! I don't handle SCAS.\n");
2928 goto cannot_emulate;
a5e2e82b 2929 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2930 goto mov;
018a98db
AK		 2931 case 0xc0 ... 0xc1:
2932 emulate_grp2(ctxt);
2933 break;
111de5d6 2934 case 0xc3: /* ret */
cf5de4f8 2935 c->dst.type = OP_REG;
111de5d6 2936 c->dst.ptr = &c->eip;
cf5de4f8 2937 c->dst.bytes = c->op_bytes;
111de5d6 2938 goto pop_instruction;
018a98db
AK		 2939 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2940 mov:
2941 c->dst.val = c->src.val;
2942 break;
a77ab5ea
AK		 2943 case 0xcb: /* ret far */
2944 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2945 if (rc != X86EMUL_CONTINUE)
2946 goto done;
2947 break;
2948 case 0xcf: /* iret */
2949 rc = emulate_iret(ctxt, ops);
2950
1b30eaa8 2951 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2952 goto done;
2953 break;
018a98db
AK		 2954 case 0xd0 ... 0xd1: /* Grp2 */
2955 c->src.val = 1;
2956 emulate_grp2(ctxt);
2957 break;
2958 case 0xd2 ... 0xd3: /* Grp2 */
2959 c->src.val = c->regs[VCPU_REGS_RCX];
2960 emulate_grp2(ctxt);
2961 break;
a6a3034c
MG		 2962 case 0xe4: /* inb */
2963 case 0xe5: /* in */
cf8f70bf 2964 goto do_io_in;
a6a3034c
MG		 2965 case 0xe6: /* outb */
2966 case 0xe7: /* out */
cf8f70bf 2967 goto do_io_out;
1a52e051 2968 case 0xe8: /* call (near) */ {
d53c4777 2969 long int rel = c->src.val;
e4e03ded 2970 c->src.val = (unsigned long) c->eip;
7a957275 2971 jmp_rel(c, rel);
79168fd1 2972 emulate_push(ctxt, ops);
8cdbd2c9 2973 break;
1a52e051
NK		 2974 }
2975 case 0xe9: /* jmp rel */
954cd36f 2976 goto jmp;
414e6277
GN		 2977 case 0xea: { /* jmp far */
2978 unsigned short sel;
ea79849d 2979 jump_far:
414e6277
GN		 2980 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2981
2982 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2983 goto done;
954cd36f 2984
414e6277
GN		 2985 c->eip = 0;
2986 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2987 break;
414e6277 2988 }
954cd36f
GT		 2989 case 0xeb:
2990 jmp: /* jmp rel short */
7a957275 2991 jmp_rel(c, c->src.val);
a01af5ec 2992 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2993 break;
a6a3034c
MG		 2994 case 0xec: /* in al,dx */
2995 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2996 c->src.val = c->regs[VCPU_REGS_RDX];
2997 do_io_in:
2998 c->dst.bytes = min(c->dst.bytes, 4u);
2999 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3000 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3001 goto done;
3002 }
7b262e90
GN		 3003 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3004 &c->dst.val))
cf8f70bf
GN		 3005 goto done; /* IO is needed */
3006 break;
ce7a0ad3
WY		 3007 case 0xee: /* out dx,al */
3008 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3009 c->src.val = c->regs[VCPU_REGS_RDX];
3010 do_io_out:
3011 c->dst.bytes = min(c->dst.bytes, 4u);
3012 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3013 emulate_gp(ctxt, 0);
f850e2e6
GN		 3014 goto done;
3015 }
cf8f70bf
GN		 3016 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3017 ctxt->vcpu);
3018 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3019 break;
111de5d6 3020 case 0xf4: /* hlt */
ad312c7c 3021 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3022 break;
111de5d6
AK		 3023 case 0xf5: /* cmc */
3024 /* complement carry flag from eflags reg */
3025 ctxt->eflags ^= EFLG_CF;
3026 c->dst.type = OP_NONE; /* Disable writeback. */
3027 break;
018a98db 3028 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3029 if (!emulate_grp3(ctxt, ops))
3030 goto cannot_emulate;
018a98db 3031 break;
111de5d6
AK		 3032 case 0xf8: /* clc */
3033 ctxt->eflags &= ~EFLG_CF;
3034 c->dst.type = OP_NONE; /* Disable writeback. */
3035 break;
3036 case 0xfa: /* cli */
07cbc6c1 3037 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3038 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3039 goto done;
3040 } else {
f850e2e6
GN		 3041 ctxt->eflags &= ~X86_EFLAGS_IF;
3042 c->dst.type = OP_NONE; /* Disable writeback. */
3043 }
111de5d6
AK		 3044 break;
3045 case 0xfb: /* sti */
07cbc6c1 3046 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3047 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3048 goto done;
3049 } else {
95cb2295 3050 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3051 ctxt->eflags |= X86_EFLAGS_IF;
3052 c->dst.type = OP_NONE; /* Disable writeback. */
3053 }
111de5d6 3054 break;
fb4616f4
MG		 3055 case 0xfc: /* cld */
3056 ctxt->eflags &= ~EFLG_DF;
3057 c->dst.type = OP_NONE; /* Disable writeback. */
3058 break;
3059 case 0xfd: /* std */
3060 ctxt->eflags |= EFLG_DF;
3061 c->dst.type = OP_NONE; /* Disable writeback. */
3062 break;
ea79849d
GN		 3063 case 0xfe: /* Grp4 */
3064 grp45:
018a98db 3065 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3066 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3067 goto done;
3068 break;
ea79849d
GN		 3069 case 0xff: /* Grp5 */
3070 if (c->modrm_reg == 5)
3071 goto jump_far;
3072 goto grp45;
91269b8f
AK		 3073 default:
3074 goto cannot_emulate;
6aa8b732 3075 }
018a98db
AK		 3076
3077writeback:
3078 rc = writeback(ctxt, ops);
1b30eaa8 3079 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3080 goto done;
3081
5cd21917
GN		 3082 /*
3083 * restore dst type in case the decoding will be reused
3084 * (happens for string instruction )
3085 */
3086 c->dst.type = saved_dst_type;
3087
a682e354 3088 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3089 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3090 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3091
3092 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3093 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3094 &c->dst);
d9271123 3095
5cd21917 3096 if (c->rep_prefix && (c->d & String)) {
7b262e90 3097 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3098 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3099 /*
3100 * Re-enter guest when pio read ahead buffer is empty or,
3101 * if it is not used, after each 1024 iteration.
3102 */
3103 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3104 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3105 ctxt->restart = false;
3106 }
9de41573
GN		 3107 /*
3108 * reset read cache here in case string instruction is restared
3109 * without decoding
3110 */
3111 ctxt->decode.mem_read.end = 0;
95c55886 3112 ctxt->eip = c->eip;
018a98db
AK		 3113
3114done:
cb404fe0 3115 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3116
3117twobyte_insn:
e4e03ded 3118 switch (c->b) {
6aa8b732 3119 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3120 switch (c->modrm_reg) {
6aa8b732
AK		 3121 u16 size;
3122 unsigned long address;
3123
aca7f966 3124 case 0: /* vmcall */
e4e03ded 3125 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3126 goto cannot_emulate;
3127
7aa81cc0 3128 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3129 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3130 goto done;
3131
33e3885d 3132 /* Let the processor re-execute the fixed hypercall */
063db061 3133 c->eip = ctxt->eip;
16286d08
AK		 3134 /* Disable writeback. */
3135 c->dst.type = OP_NONE;
aca7f966 3136 break;
6aa8b732 3137 case 2: /* lgdt */
e4e03ded
LV		 3138 rc = read_descriptor(ctxt, ops, c->src.ptr,
3139 &size, &address, c->op_bytes);
1b30eaa8 3140 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3141 goto done;
3142 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3143 /* Disable writeback. */
3144 c->dst.type = OP_NONE;
6aa8b732 3145 break;
aca7f966 3146 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3147 if (c->modrm_mod == 3) {
3148 switch (c->modrm_rm) {
3149 case 1:
3150 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3151 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3152 goto done;
3153 break;
3154 default:
3155 goto cannot_emulate;
3156 }
aca7f966 3157 } else {
e4e03ded 3158 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3159 &size, &address,
e4e03ded 3160 c->op_bytes);
1b30eaa8 3161 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3162 goto done;
3163 realmode_lidt(ctxt->vcpu, size, address);
3164 }
16286d08
AK		 3165 /* Disable writeback. */
3166 c->dst.type = OP_NONE;
6aa8b732
AK		 3167 break;
3168 case 4: /* smsw */
16286d08 3169 c->dst.bytes = 2;
52a46617 3170 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3171 break;
3172 case 6: /* lmsw */
93a152be
GN		 3173 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3174 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3175 c->dst.type = OP_NONE;
6aa8b732 3176 break;
6e1e5ffe 3177 case 5: /* not defined */
54b8486f 3178 emulate_ud(ctxt);
6e1e5ffe 3179 goto done;
6aa8b732 3180 case 7: /* invlpg*/
69f55cb1 3181 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3182 /* Disable writeback. */
3183 c->dst.type = OP_NONE;
6aa8b732
AK		 3184 break;
3185 default:
3186 goto cannot_emulate;
3187 }
3188 break;
e99f0507 3189 case 0x05: /* syscall */
3fb1b5db 3190 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3191 if (rc != X86EMUL_CONTINUE)
3192 goto done;
e66bb2cc
AP		 3193 else
3194 goto writeback;
e99f0507 3195 break;
018a98db
AK		 3196 case 0x06:
3197 emulate_clts(ctxt->vcpu);
3198 c->dst.type = OP_NONE;
3199 break;
018a98db 3200 case 0x09: /* wbinvd */
f5f48ee1
SY		 3201 kvm_emulate_wbinvd(ctxt->vcpu);
3202 c->dst.type = OP_NONE;
3203 break;
3204 case 0x08: /* invd */
018a98db
AK		 3205 case 0x0d: /* GrpP (prefetch) */
3206 case 0x18: /* Grp16 (prefetch/nop) */
3207 c->dst.type = OP_NONE;
3208 break;
3209 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3210 switch (c->modrm_reg) {
3211 case 1:
3212 case 5 ... 7:
3213 case 9 ... 15:
54b8486f 3214 emulate_ud(ctxt);
6aebfa6e
GN		 3215 goto done;
3216 }
52a46617 3217 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3218 c->dst.type = OP_NONE; /* no writeback */
3219 break;
6aa8b732 3220 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3221 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3222 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3223 emulate_ud(ctxt);
1e470be5
GN		 3224 goto done;
3225 }
35aa5375 3226 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3227 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3228 break;
018a98db 3229 case 0x22: /* mov reg, cr */
0f12244f 3230 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3231 emulate_gp(ctxt, 0);
0f12244f
GN		 3232 goto done;
3233 }
018a98db
AK		 3234 c->dst.type = OP_NONE;
3235 break;
6aa8b732 3236 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3237 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3238 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3239 emulate_ud(ctxt);
1e470be5
GN		 3240 goto done;
3241 }
35aa5375 3242
338dbc97
GN		 3243 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3244 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3245 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3246 /* #UD condition is already handled by the code above */
54b8486f 3247 emulate_gp(ctxt, 0);
338dbc97
GN		 3248 goto done;
3249 }
3250
a01af5ec 3251 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3252 break;
018a98db
AK		 3253 case 0x30:
3254 /* wrmsr */
3255 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3256 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3257 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3258 emulate_gp(ctxt, 0);
fd525365 3259 goto done;
018a98db
AK		 3260 }
3261 rc = X86EMUL_CONTINUE;
3262 c->dst.type = OP_NONE;
3263 break;
3264 case 0x32:
3265 /* rdmsr */
3fb1b5db 3266 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3267 emulate_gp(ctxt, 0);
fd525365 3268 goto done;
018a98db
AK		 3269 } else {
3270 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3271 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3272 }
3273 rc = X86EMUL_CONTINUE;
3274 c->dst.type = OP_NONE;
3275 break;
e99f0507 3276 case 0x34: /* sysenter */
3fb1b5db 3277 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3278 if (rc != X86EMUL_CONTINUE)
3279 goto done;
8c604352
AP		 3280 else
3281 goto writeback;
e99f0507
AP		 3282 break;
3283 case 0x35: /* sysexit */
3fb1b5db 3284 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3285 if (rc != X86EMUL_CONTINUE)
3286 goto done;
4668f050
AP		 3287 else
3288 goto writeback;
e99f0507 3289 break;
6aa8b732 3290 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3291 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3292 if (!test_cc(c->b, ctxt->eflags))
3293 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3294 break;
b2833e3c 3295 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3296 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3297 jmp_rel(c, c->src.val);
018a98db
AK		 3298 c->dst.type = OP_NONE;
3299 break;
0934ac9d 3300 case 0xa0: /* push fs */
79168fd1 3301 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3302 break;
3303 case 0xa1: /* pop fs */
3304 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3305 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3306 goto done;
3307 break;
7de75248
NK		 3308 case 0xa3:
3309 bt: /* bt */
e4f8e039 3310 c->dst.type = OP_NONE;
e4e03ded
LV		 3311 /* only subword offset */
3312 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3313 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3314 break;
9bf8ea42
GT		 3315 case 0xa4: /* shld imm8, r, r/m */
3316 case 0xa5: /* shld cl, r, r/m */
3317 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3318 break;
0934ac9d 3319 case 0xa8: /* push gs */
79168fd1 3320 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3321 break;
3322 case 0xa9: /* pop gs */
3323 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3324 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3325 goto done;
3326 break;
7de75248
NK		 3327 case 0xab:
3328 bts: /* bts */
e4e03ded
LV		 3329 /* only subword offset */
3330 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3331 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3332 break;
9bf8ea42
GT		 3333 case 0xac: /* shrd imm8, r, r/m */
3334 case 0xad: /* shrd cl, r, r/m */
3335 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3336 break;
2a7c5b8b
GC		 3337 case 0xae: /* clflush */
3338 break;
6aa8b732
AK		 3339 case 0xb0 ... 0xb1: /* cmpxchg */
3340 /*
3341 * Save real source value, then compare EAX against
3342 * destination.
3343 */
e4e03ded
LV		 3344 c->src.orig_val = c->src.val;
3345 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3346 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3347 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3348 /* Success: write back to memory. */
e4e03ded 3349 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3350 } else {
3351 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3352 c->dst.type = OP_REG;
3353 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3354 }
3355 break;
6aa8b732
AK		 3356 case 0xb3:
3357 btr: /* btr */
e4e03ded
LV		 3358 /* only subword offset */
3359 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3360 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3361 break;
6aa8b732 3362 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3363 c->dst.bytes = c->op_bytes;
3364 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3365 : (u16) c->src.val;
6aa8b732 3366 break;
6aa8b732 3367 case 0xba: /* Grp8 */
e4e03ded 3368 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3369 case 0:
3370 goto bt;
3371 case 1:
3372 goto bts;
3373 case 2:
3374 goto btr;
3375 case 3:
3376 goto btc;
3377 }
3378 break;
7de75248
NK		 3379 case 0xbb:
3380 btc: /* btc */
e4e03ded
LV		 3381 /* only subword offset */
3382 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3383 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3384 break;
6aa8b732 3385 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3386 c->dst.bytes = c->op_bytes;
3387 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3388 (s16) c->src.val;
6aa8b732 3389 break;
a012e65a 3390 case 0xc3: /* movnti */
e4e03ded
LV		 3391 c->dst.bytes = c->op_bytes;
3392 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3393 (u64) c->src.val;
a012e65a 3394 break;
6aa8b732 3395 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3396 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3397 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3398 goto done;
3399 break;
91269b8f
AK		 3400 default:
3401 goto cannot_emulate;
6aa8b732
AK		 3402 }
3403 goto writeback;
3404
3405cannot_emulate:
e4e03ded 3406 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3407 return -1;
3408}
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