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KVM: x86 emulator: allow loading null SS in long mode
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
9dac77fa 436static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 437{
9dac77fa 438 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 439}
440
6aa8b732 441/* Access/update address held in a register, based on addressing mode. */
e4706772 442static inline unsigned long
9dac77fa 443address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 444{
9dac77fa 445 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 446 return reg;
447 else
9dac77fa 448 return reg & ad_mask(ctxt);
e4706772
HH		 449}
450
451static inline unsigned long
9dac77fa 452register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 453{
9dac77fa 454 return address_mask(ctxt, reg);
e4706772
HH		 455}
456
7a957275 457static inline void
9dac77fa 458register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 459{
9dac77fa 460 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 461 *reg += inc;
462 else
9dac77fa 463 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 464}
6aa8b732 465
9dac77fa 466static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 467{
9dac77fa 468 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 469}
098c937b 470
56697687
AK		 471static u32 desc_limit_scaled(struct desc_struct *desc)
472{
473 u32 limit = get_desc_limit(desc);
474
475 return desc->g ? (limit << 12) | 0xfff : limit;
476}
477
9dac77fa 478static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 479{
9dac77fa
AK		 480 ctxt->has_seg_override = true;
481 ctxt->seg_override = seg;
7a5b56df
AK		 482}
483
7b105ca2 484static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 485{
486 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
487 return 0;
488
7b105ca2 489 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 490}
491
9dac77fa 492static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 493{
9dac77fa 494 if (!ctxt->has_seg_override)
7a5b56df
AK		 495 return 0;
496
9dac77fa 497 return ctxt->seg_override;
7a5b56df
AK		 498}
499
35d3d4a1
AK		 500static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
501 u32 error, bool valid)
54b8486f 502{
da9cb575
AK		 503 ctxt->exception.vector = vec;
504 ctxt->exception.error_code = error;
505 ctxt->exception.error_code_valid = valid;
35d3d4a1 506 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 507}
508
3b88e41a
JR		 509static int emulate_db(struct x86_emulate_ctxt *ctxt)
510{
511 return emulate_exception(ctxt, DB_VECTOR, 0, false);
512}
513
35d3d4a1 514static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 515{
35d3d4a1 516 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 517}
518
618ff15d
AK		 519static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
520{
521 return emulate_exception(ctxt, SS_VECTOR, err, true);
522}
523
35d3d4a1 524static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 525{
35d3d4a1 526 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 527}
528
35d3d4a1 529static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 530{
35d3d4a1 531 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 532}
533
34d1f490
AK		 534static int emulate_de(struct x86_emulate_ctxt *ctxt)
535{
35d3d4a1 536 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 537}
538
1253791d
AK		 539static int emulate_nm(struct x86_emulate_ctxt *ctxt)
540{
541 return emulate_exception(ctxt, NM_VECTOR, 0, false);
542}
543
1aa36616
AK		 544static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
545{
546 u16 selector;
547 struct desc_struct desc;
548
549 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
550 return selector;
551}
552
553static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
554 unsigned seg)
555{
556 u16 dummy;
557 u32 base3;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
561 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
562}
563
1c11b376
AK		 564/*
565 * x86 defines three classes of vector instructions: explicitly
566 * aligned, explicitly unaligned, and the rest, which change behaviour
567 * depending on whether they're AVX encoded or not.
568 *
569 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
570 * subject to the same check.
571 */
572static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
573{
574 if (likely(size < 16))
575 return false;
576
577 if (ctxt->d & Aligned)
578 return true;
579 else if (ctxt->d & Unaligned)
580 return false;
581 else if (ctxt->d & Avx)
582 return false;
583 else
584 return true;
585}
586
3d9b938e 587static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 588 struct segmented_address addr,
3d9b938e 589 unsigned size, bool write, bool fetch,
52fd8b44
AK		 590 ulong *linear)
591{
618ff15d
AK		 592 struct desc_struct desc;
593 bool usable;
52fd8b44 594 ulong la;
618ff15d 595 u32 lim;
1aa36616 596 u16 sel;
618ff15d 597 unsigned cpl, rpl;
52fd8b44 598
7b105ca2 599 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 600 switch (ctxt->mode) {
601 case X86EMUL_MODE_REAL:
602 break;
603 case X86EMUL_MODE_PROT64:
604 if (((signed long)la << 16) >> 16 != la)
605 return emulate_gp(ctxt, 0);
606 break;
607 default:
1aa36616
AK		 608 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
609 addr.seg);
618ff15d
AK		 610 if (!usable)
611 goto bad;
612 /* code segment or read-only data segment */
613 if (((desc.type & 8) || !(desc.type & 2)) && write)
614 goto bad;
615 /* unreadable code segment */
3d9b938e 616 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 617 goto bad;
618 lim = desc_limit_scaled(&desc);
619 if ((desc.type & 8) || !(desc.type & 4)) {
620 /* expand-up segment */
621 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
622 goto bad;
623 } else {
624 /* exapand-down segment */
625 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
626 goto bad;
627 lim = desc.d ? 0xffffffff : 0xffff;
628 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
629 goto bad;
630 }
717746e3 631 cpl = ctxt->ops->cpl(ctxt);
1aa36616 632 rpl = sel & 3;
618ff15d
AK		 633 cpl = max(cpl, rpl);
634 if (!(desc.type & 8)) {
635 /* data segment */
636 if (cpl > desc.dpl)
637 goto bad;
638 } else if ((desc.type & 8) && !(desc.type & 4)) {
639 /* nonconforming code segment */
640 if (cpl != desc.dpl)
641 goto bad;
642 } else if ((desc.type & 8) && (desc.type & 4)) {
643 /* conforming code segment */
644 if (cpl < desc.dpl)
645 goto bad;
646 }
647 break;
648 }
9dac77fa 649 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 650 la &= (u32)-1;
1c11b376
AK		 651 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
652 return emulate_gp(ctxt, 0);
52fd8b44
AK		 653 *linear = la;
654 return X86EMUL_CONTINUE;
618ff15d
AK		 655bad:
656 if (addr.seg == VCPU_SREG_SS)
657 return emulate_ss(ctxt, addr.seg);
658 else
659 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 660}
661
3d9b938e
NE		 662static int linearize(struct x86_emulate_ctxt *ctxt,
663 struct segmented_address addr,
664 unsigned size, bool write,
665 ulong *linear)
666{
667 return __linearize(ctxt, addr, size, write, false, linear);
668}
669
670
3ca3ac4d
AK		 671static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
672 struct segmented_address addr,
673 void *data,
674 unsigned size)
675{
9fa088f4
AK		 676 int rc;
677 ulong linear;
678
83b8795a 679 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 680 if (rc != X86EMUL_CONTINUE)
681 return rc;
0f65dd70 682 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 683}
684
807941b1
TY		 685/*
686 * Fetch the next byte of the instruction being emulated which is pointed to
687 * by ctxt->_eip, then increment ctxt->_eip.
688 *
689 * Also prefetch the remaining bytes of the instruction without crossing page
690 * boundary if they are not in fetch_cache yet.
691 */
692static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 693{
9dac77fa 694 struct fetch_cache *fc = &ctxt->fetch;
62266869 695 int rc;
2fb53ad8 696 int size, cur_size;
62266869 697
807941b1 698 if (ctxt->_eip == fc->end) {
3d9b938e 699 unsigned long linear;
807941b1
TY		 700 struct segmented_address addr = { .seg = VCPU_SREG_CS,
701 .ea = ctxt->_eip };
2fb53ad8 702 cur_size = fc->end - fc->start;
807941b1
TY		 703 size = min(15UL - cur_size,
704 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 705 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 706 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 707 return rc;
ef5d75cc
TY		 708 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
709 size, &ctxt->exception);
7d88bb48 710 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 711 return rc;
2fb53ad8 712 fc->end += size;
62266869 713 }
807941b1
TY		 714 *dest = fc->data[ctxt->_eip - fc->start];
715 ctxt->_eip++;
3e2815e9 716 return X86EMUL_CONTINUE;
62266869
AK		 717}
718
719static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 720 void *dest, unsigned size)
62266869 721{
3e2815e9 722 int rc;
62266869 723
eb3c79e6 724 /* x86 instructions are limited to 15 bytes. */
7d88bb48 725 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 726 return X86EMUL_UNHANDLEABLE;
62266869 727 while (size--) {
807941b1 728 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 729 if (rc != X86EMUL_CONTINUE)
62266869
AK		 730 return rc;
731 }
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK		 733}
734
67cbc90d 735/* Fetch next part of the instruction being emulated. */
e85a1085 736#define insn_fetch(_type, _ctxt) \
67cbc90d 737({ unsigned long _x; \
e85a1085 738 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 739 if (rc != X86EMUL_CONTINUE) \
740 goto done; \
67cbc90d
TY		 741 (_type)_x; \
742})
743
807941b1
TY		 744#define insn_fetch_arr(_arr, _size, _ctxt) \
745({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 746 if (rc != X86EMUL_CONTINUE) \
747 goto done; \
67cbc90d
TY		 748})
749
1e3c5cb0
RR		 750/*
751 * Given the 'reg' portion of a ModRM byte, and a register block, return a
752 * pointer into the block that addresses the relevant register.
753 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
754 */
755static void *decode_register(u8 modrm_reg, unsigned long *regs,
756 int highbyte_regs)
6aa8b732
AK		 757{
758 void *p;
759
760 p = &regs[modrm_reg];
761 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
762 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
763 return p;
764}
765
766static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 767 struct segmented_address addr,
6aa8b732
AK		 768 u16 *size, unsigned long *address, int op_bytes)
769{
770 int rc;
771
772 if (op_bytes == 2)
773 op_bytes = 3;
774 *address = 0;
3ca3ac4d 775 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 776 if (rc != X86EMUL_CONTINUE)
6aa8b732 777 return rc;
30b31ab6 778 addr.ea += 2;
3ca3ac4d 779 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 780 return rc;
781}
782
bbe9abbd
NK		 783static int test_cc(unsigned int condition, unsigned int flags)
784{
785 int rc = 0;
786
787 switch ((condition & 15) >> 1) {
788 case 0: /* o */
789 rc |= (flags & EFLG_OF);
790 break;
791 case 1: /* b/c/nae */
792 rc |= (flags & EFLG_CF);
793 break;
794 case 2: /* z/e */
795 rc |= (flags & EFLG_ZF);
796 break;
797 case 3: /* be/na */
798 rc |= (flags & (EFLG_CF|EFLG_ZF));
799 break;
800 case 4: /* s */
801 rc |= (flags & EFLG_SF);
802 break;
803 case 5: /* p/pe */
804 rc |= (flags & EFLG_PF);
805 break;
806 case 7: /* le/ng */
807 rc |= (flags & EFLG_ZF);
808 /* fall through */
809 case 6: /* l/nge */
810 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
811 break;
812 }
813
814 /* Odd condition identifiers (lsb == 1) have inverted sense. */
815 return (!!rc ^ (condition & 1));
816}
817
91ff3cb4
AK		 818static void fetch_register_operand(struct operand *op)
819{
820 switch (op->bytes) {
821 case 1:
822 op->val = *(u8 *)op->addr.reg;
823 break;
824 case 2:
825 op->val = *(u16 *)op->addr.reg;
826 break;
827 case 4:
828 op->val = *(u32 *)op->addr.reg;
829 break;
830 case 8:
831 op->val = *(u64 *)op->addr.reg;
832 break;
833 }
834}
835
1253791d
AK		 836static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
837{
838 ctxt->ops->get_fpu(ctxt);
839 switch (reg) {
840 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
841 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
842 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
843 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
844 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
845 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
846 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
847 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
848#ifdef CONFIG_X86_64
849 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
850 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
851 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
852 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
853 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
854 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
855 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
856 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
857#endif
858 default: BUG();
859 }
860 ctxt->ops->put_fpu(ctxt);
861}
862
863static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
864 int reg)
865{
866 ctxt->ops->get_fpu(ctxt);
867 switch (reg) {
868 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
869 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
870 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
871 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
872 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
873 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
874 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
875 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
876#ifdef CONFIG_X86_64
877 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
878 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
879 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
880 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
881 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
882 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
883 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
884 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
885#endif
886 default: BUG();
887 }
888 ctxt->ops->put_fpu(ctxt);
889}
890
cbe2c9d3
AK		 891static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
892{
893 ctxt->ops->get_fpu(ctxt);
894 switch (reg) {
895 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
896 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
897 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
898 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
899 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
900 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
901 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
902 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
903 default: BUG();
904 }
905 ctxt->ops->put_fpu(ctxt);
906}
907
908static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
909{
910 ctxt->ops->get_fpu(ctxt);
911 switch (reg) {
912 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
913 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
914 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
915 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
916 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
917 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
918 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
919 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
920 default: BUG();
921 }
922 ctxt->ops->put_fpu(ctxt);
923}
924
1253791d 925static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 926 struct operand *op)
3c118e24 927{
9dac77fa
AK		 928 unsigned reg = ctxt->modrm_reg;
929 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 930
9dac77fa
AK		 931 if (!(ctxt->d & ModRM))
932 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 933
9dac77fa 934 if (ctxt->d & Sse) {
1253791d
AK		 935 op->type = OP_XMM;
936 op->bytes = 16;
937 op->addr.xmm = reg;
938 read_sse_reg(ctxt, &op->vec_val, reg);
939 return;
940 }
cbe2c9d3
AK		 941 if (ctxt->d & Mmx) {
942 reg &= 7;
943 op->type = OP_MM;
944 op->bytes = 8;
945 op->addr.mm = reg;
946 return;
947 }
1253791d 948
3c118e24 949 op->type = OP_REG;
2adb5ad9 950 if (ctxt->d & ByteOp) {
9dac77fa 951 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 952 op->bytes = 1;
953 } else {
9dac77fa
AK		 954 op->addr.reg = decode_register(reg, ctxt->regs, 0);
955 op->bytes = ctxt->op_bytes;
3c118e24 956 }
91ff3cb4 957 fetch_register_operand(op);
3c118e24
AK		 958 op->orig_val = op->val;
959}
960
1c73ef66 961static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 962 struct operand *op)
1c73ef66 963{
1c73ef66 964 u8 sib;
f5b4edcd 965 int index_reg = 0, base_reg = 0, scale;
3e2815e9 966 int rc = X86EMUL_CONTINUE;
2dbd0dd7 967 ulong modrm_ea = 0;
1c73ef66 968
9dac77fa
AK		 969 if (ctxt->rex_prefix) {
970 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
971 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
972 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 973 }
974
9dac77fa
AK		 975 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
976 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
977 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
978 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 979
9dac77fa 980 if (ctxt->modrm_mod == 3) {
2dbd0dd7 981 op->type = OP_REG;
9dac77fa
AK		 982 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
983 op->addr.reg = decode_register(ctxt->modrm_rm,
984 ctxt->regs, ctxt->d & ByteOp);
985 if (ctxt->d & Sse) {
1253791d
AK		 986 op->type = OP_XMM;
987 op->bytes = 16;
9dac77fa
AK		 988 op->addr.xmm = ctxt->modrm_rm;
989 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 990 return rc;
991 }
cbe2c9d3
AK		 992 if (ctxt->d & Mmx) {
993 op->type = OP_MM;
994 op->bytes = 8;
995 op->addr.xmm = ctxt->modrm_rm & 7;
996 return rc;
997 }
2dbd0dd7 998 fetch_register_operand(op);
1c73ef66
AK		 999 return rc;
1000 }
1001
2dbd0dd7
AK		 1002 op->type = OP_MEM;
1003
9dac77fa
AK		 1004 if (ctxt->ad_bytes == 2) {
1005 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1006 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1007 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1008 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1009
1010 /* 16-bit ModR/M decode. */
9dac77fa 1011 switch (ctxt->modrm_mod) {
1c73ef66 1012 case 0:
9dac77fa 1013 if (ctxt->modrm_rm == 6)
e85a1085 1014 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1015 break;
1016 case 1:
e85a1085 1017 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1018 break;
1019 case 2:
e85a1085 1020 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1021 break;
1022 }
9dac77fa 1023 switch (ctxt->modrm_rm) {
1c73ef66 1024 case 0:
2dbd0dd7 1025 modrm_ea += bx + si;
1c73ef66
AK		 1026 break;
1027 case 1:
2dbd0dd7 1028 modrm_ea += bx + di;
1c73ef66
AK		 1029 break;
1030 case 2:
2dbd0dd7 1031 modrm_ea += bp + si;
1c73ef66
AK		 1032 break;
1033 case 3:
2dbd0dd7 1034 modrm_ea += bp + di;
1c73ef66
AK		 1035 break;
1036 case 4:
2dbd0dd7 1037 modrm_ea += si;
1c73ef66
AK		 1038 break;
1039 case 5:
2dbd0dd7 1040 modrm_ea += di;
1c73ef66
AK		 1041 break;
1042 case 6:
9dac77fa 1043 if (ctxt->modrm_mod != 0)
2dbd0dd7 1044 modrm_ea += bp;
1c73ef66
AK		 1045 break;
1046 case 7:
2dbd0dd7 1047 modrm_ea += bx;
1c73ef66
AK		 1048 break;
1049 }
9dac77fa
AK		 1050 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1051 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1052 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1053 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1054 } else {
1055 /* 32/64-bit ModR/M decode. */
9dac77fa 1056 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1057 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1058 index_reg |= (sib >> 3) & 7;
1059 base_reg |= sib & 7;
1060 scale = sib >> 6;
1061
9dac77fa 1062 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1063 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 1064 else
9dac77fa 1065 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 1066 if (index_reg != 4)
9dac77fa
AK		 1067 modrm_ea += ctxt->regs[index_reg] << scale;
1068 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1069 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1070 ctxt->rip_relative = 1;
84411d85 1071 } else
9dac77fa
AK		 1072 modrm_ea += ctxt->regs[ctxt->modrm_rm];
1073 switch (ctxt->modrm_mod) {
1c73ef66 1074 case 0:
9dac77fa 1075 if (ctxt->modrm_rm == 5)
e85a1085 1076 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1077 break;
1078 case 1:
e85a1085 1079 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1080 break;
1081 case 2:
e85a1085 1082 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1083 break;
1084 }
1085 }
90de84f5 1086 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1087done:
1088 return rc;
1089}
1090
1091static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1092 struct operand *op)
1c73ef66 1093{
3e2815e9 1094 int rc = X86EMUL_CONTINUE;
1c73ef66 1095
2dbd0dd7 1096 op->type = OP_MEM;
9dac77fa 1097 switch (ctxt->ad_bytes) {
1c73ef66 1098 case 2:
e85a1085 1099 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1100 break;
1101 case 4:
e85a1085 1102 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1103 break;
1104 case 8:
e85a1085 1105 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1106 break;
1107 }
1108done:
1109 return rc;
1110}
1111
9dac77fa 1112static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1113{
7129eeca 1114 long sv = 0, mask;
35c843c4 1115
9dac77fa
AK		 1116 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1117 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1118
9dac77fa
AK		 1119 if (ctxt->src.bytes == 2)
1120 sv = (s16)ctxt->src.val & (s16)mask;
1121 else if (ctxt->src.bytes == 4)
1122 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1123
9dac77fa 1124 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1125 }
ba7ff2b7
WY		 1126
1127 /* only subword offset */
9dac77fa 1128 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1129}
1130
dde7e6d1 1131static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1132 unsigned long addr, void *dest, unsigned size)
6aa8b732 1133{
dde7e6d1 1134 int rc;
9dac77fa 1135 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1136
dde7e6d1
AK		 1137 while (size) {
1138 int n = min(size, 8u);
1139 size -= n;
1140 if (mc->pos < mc->end)
1141 goto read_cached;
5cd21917 1142
7b105ca2
TY		 1143 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1144 &ctxt->exception);
dde7e6d1
AK		 1145 if (rc != X86EMUL_CONTINUE)
1146 return rc;
1147 mc->end += n;
6aa8b732 1148
dde7e6d1
AK		 1149 read_cached:
1150 memcpy(dest, mc->data + mc->pos, n);
1151 mc->pos += n;
1152 dest += n;
1153 addr += n;
6aa8b732 1154 }
dde7e6d1
AK		 1155 return X86EMUL_CONTINUE;
1156}
6aa8b732 1157
3ca3ac4d
AK		 1158static int segmented_read(struct x86_emulate_ctxt *ctxt,
1159 struct segmented_address addr,
1160 void *data,
1161 unsigned size)
1162{
9fa088f4
AK		 1163 int rc;
1164 ulong linear;
1165
83b8795a 1166 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1167 if (rc != X86EMUL_CONTINUE)
1168 return rc;
7b105ca2 1169 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1170}
1171
1172static int segmented_write(struct x86_emulate_ctxt *ctxt,
1173 struct segmented_address addr,
1174 const void *data,
1175 unsigned size)
1176{
9fa088f4
AK		 1177 int rc;
1178 ulong linear;
1179
83b8795a 1180 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1181 if (rc != X86EMUL_CONTINUE)
1182 return rc;
0f65dd70
AK		 1183 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1184 &ctxt->exception);
3ca3ac4d
AK		 1185}
1186
1187static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1188 struct segmented_address addr,
1189 const void *orig_data, const void *data,
1190 unsigned size)
1191{
9fa088f4
AK		 1192 int rc;
1193 ulong linear;
1194
83b8795a 1195 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1196 if (rc != X86EMUL_CONTINUE)
1197 return rc;
0f65dd70
AK		 1198 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1199 size, &ctxt->exception);
3ca3ac4d
AK		 1200}
1201
dde7e6d1 1202static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1203 unsigned int size, unsigned short port,
1204 void *dest)
1205{
9dac77fa 1206 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1207
dde7e6d1 1208 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1209 unsigned int in_page, n;
9dac77fa
AK		 1210 unsigned int count = ctxt->rep_prefix ?
1211 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1212 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1213 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1214 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1215 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1216 count);
1217 if (n == 0)
1218 n = 1;
1219 rc->pos = rc->end = 0;
7b105ca2 1220 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1221 return 0;
1222 rc->end = n * size;
6aa8b732
AK		 1223 }
1224
dde7e6d1
AK		 1225 memcpy(dest, rc->data + rc->pos, size);
1226 rc->pos += size;
1227 return 1;
1228}
6aa8b732 1229
7f3d35fd
KW		 1230static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1231 u16 index, struct desc_struct *desc)
1232{
1233 struct desc_ptr dt;
1234 ulong addr;
1235
1236 ctxt->ops->get_idt(ctxt, &dt);
1237
1238 if (dt.size < index * 8 + 7)
1239 return emulate_gp(ctxt, index << 3 | 0x2);
1240
1241 addr = dt.address + index * 8;
1242 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1243 &ctxt->exception);
1244}
1245
dde7e6d1 1246static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1247 u16 selector, struct desc_ptr *dt)
1248{
7b105ca2
TY		 1249 struct x86_emulate_ops *ops = ctxt->ops;
1250
dde7e6d1
AK		 1251 if (selector & 1 << 2) {
1252 struct desc_struct desc;
1aa36616
AK		 1253 u16 sel;
1254
dde7e6d1 1255 memset (dt, 0, sizeof *dt);
1aa36616 1256 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1257 return;
e09d082c 1258
dde7e6d1
AK		 1259 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1260 dt->address = get_desc_base(&desc);
1261 } else
4bff1e86 1262 ops->get_gdt(ctxt, dt);
dde7e6d1 1263}
120df890 1264
dde7e6d1
AK		 1265/* allowed just for 8 bytes segments */
1266static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1267 u16 selector, struct desc_struct *desc)
1268{
1269 struct desc_ptr dt;
1270 u16 index = selector >> 3;
dde7e6d1 1271 ulong addr;
120df890 1272
7b105ca2 1273 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1274
35d3d4a1
AK		 1275 if (dt.size < index * 8 + 7)
1276 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1277
7b105ca2
TY		 1278 addr = dt.address + index * 8;
1279 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1280 &ctxt->exception);
dde7e6d1 1281}
ef65c889 1282
dde7e6d1
AK		 1283/* allowed just for 8 bytes segments */
1284static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1285 u16 selector, struct desc_struct *desc)
1286{
1287 struct desc_ptr dt;
1288 u16 index = selector >> 3;
dde7e6d1 1289 ulong addr;
6aa8b732 1290
7b105ca2 1291 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1292
35d3d4a1
AK		 1293 if (dt.size < index * 8 + 7)
1294 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1295
dde7e6d1 1296 addr = dt.address + index * 8;
7b105ca2
TY		 1297 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1298 &ctxt->exception);
dde7e6d1 1299}
c7e75a3d 1300
5601d05b 1301/* Does not support long mode */
dde7e6d1 1302static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1303 u16 selector, int seg)
1304{
1305 struct desc_struct seg_desc;
1306 u8 dpl, rpl, cpl;
1307 unsigned err_vec = GP_VECTOR;
1308 u32 err_code = 0;
1309 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1310 int ret;
69f55cb1 1311
dde7e6d1 1312 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1313
dde7e6d1
AK		 1314 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1315 || ctxt->mode == X86EMUL_MODE_REAL) {
1316 /* set real mode segment descriptor */
1317 set_desc_base(&seg_desc, selector << 4);
1318 set_desc_limit(&seg_desc, 0xffff);
1319 seg_desc.type = 3;
1320 seg_desc.p = 1;
1321 seg_desc.s = 1;
66b0ab8f
KW		 1322 if (ctxt->mode == X86EMUL_MODE_VM86)
1323 seg_desc.dpl = 3;
dde7e6d1
AK		 1324 goto load;
1325 }
1326
79d5b4c3
AK		 1327 rpl = selector & 3;
1328 cpl = ctxt->ops->cpl(ctxt);
1329
1330 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1331 if ((seg == VCPU_SREG_CS
1332 || (seg == VCPU_SREG_SS
1333 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1334 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1335 && null_selector)
1336 goto exception;
1337
1338 /* TR should be in GDT only */
1339 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1340 goto exception;
1341
1342 if (null_selector) /* for NULL selector skip all following checks */
1343 goto load;
1344
7b105ca2 1345 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1346 if (ret != X86EMUL_CONTINUE)
1347 return ret;
1348
1349 err_code = selector & 0xfffc;
1350 err_vec = GP_VECTOR;
1351
1352 /* can't load system descriptor into segment selecor */
1353 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1354 goto exception;
1355
1356 if (!seg_desc.p) {
1357 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1358 goto exception;
1359 }
1360
dde7e6d1 1361 dpl = seg_desc.dpl;
dde7e6d1
AK		 1362
1363 switch (seg) {
1364 case VCPU_SREG_SS:
1365 /*
1366 * segment is not a writable data segment or segment
1367 * selector's RPL != CPL or segment selector's RPL != CPL
1368 */
1369 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1370 goto exception;
6aa8b732 1371 break;
dde7e6d1
AK		 1372 case VCPU_SREG_CS:
1373 if (!(seg_desc.type & 8))
1374 goto exception;
1375
1376 if (seg_desc.type & 4) {
1377 /* conforming */
1378 if (dpl > cpl)
1379 goto exception;
1380 } else {
1381 /* nonconforming */
1382 if (rpl > cpl || dpl != cpl)
1383 goto exception;
1384 }
1385 /* CS(RPL) <- CPL */
1386 selector = (selector & 0xfffc) | cpl;
6aa8b732 1387 break;
dde7e6d1
AK		 1388 case VCPU_SREG_TR:
1389 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1390 goto exception;
1391 break;
1392 case VCPU_SREG_LDTR:
1393 if (seg_desc.s || seg_desc.type != 2)
1394 goto exception;
1395 break;
1396 default: /* DS, ES, FS, or GS */
4e62417b 1397 /*
dde7e6d1
AK		 1398 * segment is not a data or readable code segment or
1399 * ((segment is a data or nonconforming code segment)
1400 * and (both RPL and CPL > DPL))
4e62417b 1401 */
dde7e6d1
AK		 1402 if ((seg_desc.type & 0xa) == 0x8 ||
1403 (((seg_desc.type & 0xc) != 0xc) &&
1404 (rpl > dpl && cpl > dpl)))
1405 goto exception;
6aa8b732 1406 break;
dde7e6d1
AK		 1407 }
1408
1409 if (seg_desc.s) {
1410 /* mark segment as accessed */
1411 seg_desc.type |= 1;
7b105ca2 1412 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1413 if (ret != X86EMUL_CONTINUE)
1414 return ret;
1415 }
1416load:
7b105ca2 1417 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1418 return X86EMUL_CONTINUE;
1419exception:
1420 emulate_exception(ctxt, err_vec, err_code, true);
1421 return X86EMUL_PROPAGATE_FAULT;
1422}
1423
31be40b3
WY		 1424static void write_register_operand(struct operand *op)
1425{
1426 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1427 switch (op->bytes) {
1428 case 1:
1429 *(u8 *)op->addr.reg = (u8)op->val;
1430 break;
1431 case 2:
1432 *(u16 *)op->addr.reg = (u16)op->val;
1433 break;
1434 case 4:
1435 *op->addr.reg = (u32)op->val;
1436 break; /* 64b: zero-extend */
1437 case 8:
1438 *op->addr.reg = op->val;
1439 break;
1440 }
1441}
1442
adddcecf 1443static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1444{
1445 int rc;
dde7e6d1 1446
9dac77fa 1447 switch (ctxt->dst.type) {
dde7e6d1 1448 case OP_REG:
9dac77fa 1449 write_register_operand(&ctxt->dst);
6aa8b732 1450 break;
dde7e6d1 1451 case OP_MEM:
9dac77fa 1452 if (ctxt->lock_prefix)
3ca3ac4d 1453 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1454 ctxt->dst.addr.mem,
1455 &ctxt->dst.orig_val,
1456 &ctxt->dst.val,
1457 ctxt->dst.bytes);
341de7e3 1458 else
3ca3ac4d 1459 rc = segmented_write(ctxt,
9dac77fa
AK		 1460 ctxt->dst.addr.mem,
1461 &ctxt->dst.val,
1462 ctxt->dst.bytes);
dde7e6d1
AK		 1463 if (rc != X86EMUL_CONTINUE)
1464 return rc;
a682e354 1465 break;
1253791d 1466 case OP_XMM:
9dac77fa 1467 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1468 break;
cbe2c9d3
AK		 1469 case OP_MM:
1470 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1471 break;
dde7e6d1
AK		 1472 case OP_NONE:
1473 /* no writeback */
414e6277 1474 break;
dde7e6d1 1475 default:
414e6277 1476 break;
6aa8b732 1477 }
dde7e6d1
AK		 1478 return X86EMUL_CONTINUE;
1479}
6aa8b732 1480
4487b3b4 1481static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1482{
4179bb02 1483 struct segmented_address addr;
0dc8d10f 1484
9dac77fa
AK		 1485 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1486 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1487 addr.seg = VCPU_SREG_SS;
1488
1489 /* Disable writeback. */
9dac77fa
AK		 1490 ctxt->dst.type = OP_NONE;
1491 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1492}
69f55cb1 1493
dde7e6d1 1494static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1495 void *dest, int len)
1496{
dde7e6d1 1497 int rc;
90de84f5 1498 struct segmented_address addr;
8b4caf66 1499
9dac77fa 1500 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1501 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1502 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1503 if (rc != X86EMUL_CONTINUE)
1504 return rc;
1505
9dac77fa 1506 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1507 return rc;
8b4caf66
LV		 1508}
1509
c54fe504
TY		 1510static int em_pop(struct x86_emulate_ctxt *ctxt)
1511{
9dac77fa 1512 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1513}
1514
dde7e6d1 1515static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1516 void *dest, int len)
9de41573
GN		 1517{
1518 int rc;
dde7e6d1
AK		 1519 unsigned long val, change_mask;
1520 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1521 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1522
3b9be3bf 1523 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1524 if (rc != X86EMUL_CONTINUE)
1525 return rc;
9de41573 1526
dde7e6d1
AK		 1527 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1528 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1529
dde7e6d1
AK		 1530 switch(ctxt->mode) {
1531 case X86EMUL_MODE_PROT64:
1532 case X86EMUL_MODE_PROT32:
1533 case X86EMUL_MODE_PROT16:
1534 if (cpl == 0)
1535 change_mask |= EFLG_IOPL;
1536 if (cpl <= iopl)
1537 change_mask |= EFLG_IF;
1538 break;
1539 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1540 if (iopl < 3)
1541 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1542 change_mask |= EFLG_IF;
1543 break;
1544 default: /* real mode */
1545 change_mask |= (EFLG_IOPL | EFLG_IF);
1546 break;
9de41573 1547 }
dde7e6d1
AK		 1548
1549 *(unsigned long *)dest =
1550 (ctxt->eflags & ~change_mask) | (val & change_mask);
1551
1552 return rc;
9de41573
GN		 1553}
1554
62aaa2f0
TY		 1555static int em_popf(struct x86_emulate_ctxt *ctxt)
1556{
9dac77fa
AK		 1557 ctxt->dst.type = OP_REG;
1558 ctxt->dst.addr.reg = &ctxt->eflags;
1559 ctxt->dst.bytes = ctxt->op_bytes;
1560 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1561}
1562
1cd196ea 1563static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1564{
1cd196ea
AK		 1565 int seg = ctxt->src2.val;
1566
9dac77fa 1567 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1568
4487b3b4 1569 return em_push(ctxt);
7b262e90
GN		 1570}
1571
1cd196ea 1572static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1573{
1cd196ea 1574 int seg = ctxt->src2.val;
dde7e6d1
AK		 1575 unsigned long selector;
1576 int rc;
38ba30ba 1577
9dac77fa 1578 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1579 if (rc != X86EMUL_CONTINUE)
1580 return rc;
1581
7b105ca2 1582 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1583 return rc;
38ba30ba
GN		 1584}
1585
b96a7fad 1586static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1587{
9dac77fa 1588 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1589 int rc = X86EMUL_CONTINUE;
1590 int reg = VCPU_REGS_RAX;
38ba30ba 1591
dde7e6d1
AK		 1592 while (reg <= VCPU_REGS_RDI) {
1593 (reg == VCPU_REGS_RSP) ?
9dac77fa 1594 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1595
4487b3b4 1596 rc = em_push(ctxt);
dde7e6d1
AK		 1597 if (rc != X86EMUL_CONTINUE)
1598 return rc;
38ba30ba 1599
dde7e6d1 1600 ++reg;
38ba30ba 1601 }
38ba30ba 1602
dde7e6d1 1603 return rc;
38ba30ba
GN		 1604}
1605
62aaa2f0
TY		 1606static int em_pushf(struct x86_emulate_ctxt *ctxt)
1607{
9dac77fa 1608 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1609 return em_push(ctxt);
1610}
1611
b96a7fad 1612static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1613{
dde7e6d1
AK		 1614 int rc = X86EMUL_CONTINUE;
1615 int reg = VCPU_REGS_RDI;
38ba30ba 1616
dde7e6d1
AK		 1617 while (reg >= VCPU_REGS_RAX) {
1618 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1619 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1620 ctxt->op_bytes);
dde7e6d1
AK		 1621 --reg;
1622 }
38ba30ba 1623
9dac77fa 1624 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1625 if (rc != X86EMUL_CONTINUE)
1626 break;
1627 --reg;
38ba30ba 1628 }
dde7e6d1 1629 return rc;
38ba30ba
GN		 1630}
1631
7b105ca2 1632int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1633{
7b105ca2 1634 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1635 int rc;
6e154e56
MG		 1636 struct desc_ptr dt;
1637 gva_t cs_addr;
1638 gva_t eip_addr;
1639 u16 cs, eip;
6e154e56
MG		 1640
1641 /* TODO: Add limit checks */
9dac77fa 1642 ctxt->src.val = ctxt->eflags;
4487b3b4 1643 rc = em_push(ctxt);
5c56e1cf
AK		 1644 if (rc != X86EMUL_CONTINUE)
1645 return rc;
6e154e56
MG		 1646
1647 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1648
9dac77fa 1649 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1650 rc = em_push(ctxt);
5c56e1cf
AK		 1651 if (rc != X86EMUL_CONTINUE)
1652 return rc;
6e154e56 1653
9dac77fa 1654 ctxt->src.val = ctxt->_eip;
4487b3b4 1655 rc = em_push(ctxt);
5c56e1cf
AK		 1656 if (rc != X86EMUL_CONTINUE)
1657 return rc;
1658
4bff1e86 1659 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1660
1661 eip_addr = dt.address + (irq << 2);
1662 cs_addr = dt.address + (irq << 2) + 2;
1663
0f65dd70 1664 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1665 if (rc != X86EMUL_CONTINUE)
1666 return rc;
1667
0f65dd70 1668 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1669 if (rc != X86EMUL_CONTINUE)
1670 return rc;
1671
7b105ca2 1672 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1673 if (rc != X86EMUL_CONTINUE)
1674 return rc;
1675
9dac77fa 1676 ctxt->_eip = eip;
6e154e56
MG		 1677
1678 return rc;
1679}
1680
7b105ca2 1681static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1682{
1683 switch(ctxt->mode) {
1684 case X86EMUL_MODE_REAL:
7b105ca2 1685 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1686 case X86EMUL_MODE_VM86:
1687 case X86EMUL_MODE_PROT16:
1688 case X86EMUL_MODE_PROT32:
1689 case X86EMUL_MODE_PROT64:
1690 default:
1691 /* Protected mode interrupts unimplemented yet */
1692 return X86EMUL_UNHANDLEABLE;
1693 }
1694}
1695
7b105ca2 1696static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1697{
dde7e6d1
AK		 1698 int rc = X86EMUL_CONTINUE;
1699 unsigned long temp_eip = 0;
1700 unsigned long temp_eflags = 0;
1701 unsigned long cs = 0;
1702 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1703 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1704 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1705 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1706
dde7e6d1 1707 /* TODO: Add stack limit check */
38ba30ba 1708
9dac77fa 1709 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1710
dde7e6d1
AK		 1711 if (rc != X86EMUL_CONTINUE)
1712 return rc;
38ba30ba 1713
35d3d4a1
AK		 1714 if (temp_eip & ~0xffff)
1715 return emulate_gp(ctxt, 0);
38ba30ba 1716
9dac77fa 1717 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1718
dde7e6d1
AK		 1719 if (rc != X86EMUL_CONTINUE)
1720 return rc;
38ba30ba 1721
9dac77fa 1722 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1723
dde7e6d1
AK		 1724 if (rc != X86EMUL_CONTINUE)
1725 return rc;
38ba30ba 1726
7b105ca2 1727 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1728
dde7e6d1
AK		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
38ba30ba 1731
9dac77fa 1732 ctxt->_eip = temp_eip;
38ba30ba 1733
38ba30ba 1734
9dac77fa 1735 if (ctxt->op_bytes == 4)
dde7e6d1 1736 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1737 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1738 ctxt->eflags &= ~0xffff;
1739 ctxt->eflags |= temp_eflags;
38ba30ba 1740 }
dde7e6d1
AK		 1741
1742 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1743 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1744
1745 return rc;
38ba30ba
GN		 1746}
1747
e01991e7 1748static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1749{
dde7e6d1
AK		 1750 switch(ctxt->mode) {
1751 case X86EMUL_MODE_REAL:
7b105ca2 1752 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1753 case X86EMUL_MODE_VM86:
1754 case X86EMUL_MODE_PROT16:
1755 case X86EMUL_MODE_PROT32:
1756 case X86EMUL_MODE_PROT64:
c37eda13 1757 default:
dde7e6d1
AK		 1758 /* iret from protected mode unimplemented yet */
1759 return X86EMUL_UNHANDLEABLE;
c37eda13 1760 }
c37eda13
WY		 1761}
1762
d2f62766
TY		 1763static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1764{
d2f62766
TY		 1765 int rc;
1766 unsigned short sel;
1767
9dac77fa 1768 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1769
7b105ca2 1770 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1771 if (rc != X86EMUL_CONTINUE)
1772 return rc;
1773
9dac77fa
AK		 1774 ctxt->_eip = 0;
1775 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1776 return X86EMUL_CONTINUE;
1777}
1778
51187683 1779static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1780{
9dac77fa 1781 switch (ctxt->modrm_reg) {
8cdbd2c9 1782 case 0: /* rol */
a31b9cea 1783 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1784 break;
1785 case 1: /* ror */
a31b9cea 1786 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1787 break;
1788 case 2: /* rcl */
a31b9cea 1789 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1790 break;
1791 case 3: /* rcr */
a31b9cea 1792 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1793 break;
1794 case 4: /* sal/shl */
1795 case 6: /* sal/shl */
a31b9cea 1796 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1797 break;
1798 case 5: /* shr */
a31b9cea 1799 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1800 break;
1801 case 7: /* sar */
a31b9cea 1802 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1803 break;
1804 }
51187683 1805 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1806}
1807
3329ece1
AK		 1808static int em_not(struct x86_emulate_ctxt *ctxt)
1809{
1810 ctxt->dst.val = ~ctxt->dst.val;
1811 return X86EMUL_CONTINUE;
1812}
1813
1814static int em_neg(struct x86_emulate_ctxt *ctxt)
1815{
1816 emulate_1op(ctxt, "neg");
1817 return X86EMUL_CONTINUE;
1818}
1819
1820static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1821{
1822 u8 ex = 0;
1823
1824 emulate_1op_rax_rdx(ctxt, "mul", ex);
1825 return X86EMUL_CONTINUE;
1826}
1827
1828static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1829{
1830 u8 ex = 0;
1831
1832 emulate_1op_rax_rdx(ctxt, "imul", ex);
1833 return X86EMUL_CONTINUE;
1834}
1835
1836static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1837{
34d1f490 1838 u8 de = 0;
8cdbd2c9 1839
3329ece1
AK		 1840 emulate_1op_rax_rdx(ctxt, "div", de);
1841 if (de)
1842 return emulate_de(ctxt);
1843 return X86EMUL_CONTINUE;
1844}
1845
1846static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1847{
1848 u8 de = 0;
1849
1850 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1851 if (de)
1852 return emulate_de(ctxt);
8c5eee30 1853 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1854}
1855
51187683 1856static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1857{
4179bb02 1858 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1859
9dac77fa 1860 switch (ctxt->modrm_reg) {
8cdbd2c9 1861 case 0: /* inc */
d1eef45d 1862 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1863 break;
1864 case 1: /* dec */
d1eef45d 1865 emulate_1op(ctxt, "dec");
8cdbd2c9 1866 break;
d19292e4
MG		 1867 case 2: /* call near abs */ {
1868 long int old_eip;
9dac77fa
AK		 1869 old_eip = ctxt->_eip;
1870 ctxt->_eip = ctxt->src.val;
1871 ctxt->src.val = old_eip;
4487b3b4 1872 rc = em_push(ctxt);
d19292e4
MG		 1873 break;
1874 }
8cdbd2c9 1875 case 4: /* jmp abs */
9dac77fa 1876 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1877 break;
d2f62766
TY		 1878 case 5: /* jmp far */
1879 rc = em_jmp_far(ctxt);
1880 break;
8cdbd2c9 1881 case 6: /* push */
4487b3b4 1882 rc = em_push(ctxt);
8cdbd2c9 1883 break;
8cdbd2c9 1884 }
4179bb02 1885 return rc;
8cdbd2c9
LV		 1886}
1887
e0dac408 1888static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1889{
9dac77fa 1890 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1891
9dac77fa
AK		 1892 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1893 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1894 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1895 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1896 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1897 } else {
9dac77fa
AK		 1898 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1899 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1900
05f086f8 1901 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1902 }
1b30eaa8 1903 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1904}
1905
ebda02c2
TY		 1906static int em_ret(struct x86_emulate_ctxt *ctxt)
1907{
9dac77fa
AK		 1908 ctxt->dst.type = OP_REG;
1909 ctxt->dst.addr.reg = &ctxt->_eip;
1910 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1911 return em_pop(ctxt);
1912}
1913
e01991e7 1914static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1915{
a77ab5ea
AK		 1916 int rc;
1917 unsigned long cs;
1918
9dac77fa 1919 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1920 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1921 return rc;
9dac77fa
AK		 1922 if (ctxt->op_bytes == 4)
1923 ctxt->_eip = (u32)ctxt->_eip;
1924 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1925 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1926 return rc;
7b105ca2 1927 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1928 return rc;
1929}
1930
e940b5c2
TY		 1931static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1932{
1933 /* Save real source value, then compare EAX against destination. */
1934 ctxt->src.orig_val = ctxt->src.val;
1935 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1936 emulate_2op_SrcV(ctxt, "cmp");
1937
1938 if (ctxt->eflags & EFLG_ZF) {
1939 /* Success: write back to memory. */
1940 ctxt->dst.val = ctxt->src.orig_val;
1941 } else {
1942 /* Failure: write the value we saw to EAX. */
1943 ctxt->dst.type = OP_REG;
1944 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1945 }
1946 return X86EMUL_CONTINUE;
1947}
1948
d4b4325f 1949static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1950{
d4b4325f 1951 int seg = ctxt->src2.val;
09b5f4d3
WY		 1952 unsigned short sel;
1953 int rc;
1954
9dac77fa 1955 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1956
7b105ca2 1957 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1958 if (rc != X86EMUL_CONTINUE)
1959 return rc;
1960
9dac77fa 1961 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1962 return rc;
1963}
1964
7b105ca2 1965static void
e66bb2cc 1966setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1967 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1968{
1aa36616
AK		 1969 u16 selector;
1970
79168fd1 1971 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1972 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1973 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1974
1975 cs->l = 0; /* will be adjusted later */
79168fd1 1976 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1977 cs->g = 1; /* 4kb granularity */
79168fd1 1978 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1979 cs->type = 0x0b; /* Read, Execute, Accessed */
1980 cs->s = 1;
1981 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1982 cs->p = 1;
1983 cs->d = 1;
e66bb2cc 1984
79168fd1
GN		 1985 set_desc_base(ss, 0); /* flat segment */
1986 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1987 ss->g = 1; /* 4kb granularity */
1988 ss->s = 1;
1989 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1990 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1991 ss->dpl = 0;
79168fd1 1992 ss->p = 1;
e66bb2cc
AP		 1993}
1994
1a18a69b
AK		 1995static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
1996{
1997 u32 eax, ebx, ecx, edx;
1998
1999 eax = ecx = 0;
0017f93a
AK		 2000 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2001 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2002 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2003 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2004}
2005
c2226fc9
SB		 2006static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2007{
2008 struct x86_emulate_ops *ops = ctxt->ops;
2009 u32 eax, ebx, ecx, edx;
2010
2011 /*
2012 * syscall should always be enabled in longmode - so only become
2013 * vendor specific (cpuid) if other modes are active...
2014 */
2015 if (ctxt->mode == X86EMUL_MODE_PROT64)
2016 return true;
2017
2018 eax = 0x00000000;
2019 ecx = 0x00000000;
0017f93a
AK		 2020 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2021 /*
2022 * Intel ("GenuineIntel")
2023 * remark: Intel CPUs only support "syscall" in 64bit
2024 * longmode. Also an 64bit guest with a
2025 * 32bit compat-app running will #UD !! While this
2026 * behaviour can be fixed (by emulating) into AMD
2027 * response - CPUs of AMD can't behave like Intel.
2028 */
2029 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2030 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2031 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2032 return false;
2033
2034 /* AMD ("AuthenticAMD") */
2035 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2036 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2037 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2038 return true;
2039
2040 /* AMD ("AMDisbetter!") */
2041 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2042 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2043 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2044 return true;
c2226fc9
SB		 2045
2046 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2047 return false;
2048}
2049
e01991e7 2050static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2051{
7b105ca2 2052 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2053 struct desc_struct cs, ss;
e66bb2cc 2054 u64 msr_data;
79168fd1 2055 u16 cs_sel, ss_sel;
c2ad2bb3 2056 u64 efer = 0;
e66bb2cc
AP		 2057
2058 /* syscall is not available in real mode */
2e901c4c 2059 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2060 ctxt->mode == X86EMUL_MODE_VM86)
2061 return emulate_ud(ctxt);
e66bb2cc 2062
c2226fc9
SB		 2063 if (!(em_syscall_is_enabled(ctxt)))
2064 return emulate_ud(ctxt);
2065
c2ad2bb3 2066 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2067 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2068
c2226fc9
SB		 2069 if (!(efer & EFER_SCE))
2070 return emulate_ud(ctxt);
2071
717746e3 2072 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2073 msr_data >>= 32;
79168fd1
GN		 2074 cs_sel = (u16)(msr_data & 0xfffc);
2075 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2076
c2ad2bb3 2077 if (efer & EFER_LMA) {
79168fd1 2078 cs.d = 0;
e66bb2cc
AP		 2079 cs.l = 1;
2080 }
1aa36616
AK		 2081 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2082 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2083
9dac77fa 2084 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2085 if (efer & EFER_LMA) {
e66bb2cc 2086#ifdef CONFIG_X86_64
9dac77fa 2087 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2088
717746e3 2089 ops->get_msr(ctxt,
3fb1b5db
GN		 2090 ctxt->mode == X86EMUL_MODE_PROT64 ?
2091 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2092 ctxt->_eip = msr_data;
e66bb2cc 2093
717746e3 2094 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2095 ctxt->eflags &= ~(msr_data | EFLG_RF);
2096#endif
2097 } else {
2098 /* legacy mode */
717746e3 2099 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2100 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2101
2102 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2103 }
2104
e54cfa97 2105 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2106}
2107
e01991e7 2108static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2109{
7b105ca2 2110 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2111 struct desc_struct cs, ss;
8c604352 2112 u64 msr_data;
79168fd1 2113 u16 cs_sel, ss_sel;
c2ad2bb3 2114 u64 efer = 0;
8c604352 2115
7b105ca2 2116 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2117 /* inject #GP if in real mode */
35d3d4a1
AK		 2118 if (ctxt->mode == X86EMUL_MODE_REAL)
2119 return emulate_gp(ctxt, 0);
8c604352 2120
1a18a69b
AK		 2121 /*
2122 * Not recognized on AMD in compat mode (but is recognized in legacy
2123 * mode).
2124 */
2125 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2126 && !vendor_intel(ctxt))
2127 return emulate_ud(ctxt);
2128
8c604352
AP		 2129 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2130 * Therefore, we inject an #UD.
2131 */
35d3d4a1
AK		 2132 if (ctxt->mode == X86EMUL_MODE_PROT64)
2133 return emulate_ud(ctxt);
8c604352 2134
7b105ca2 2135 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2136
717746e3 2137 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2138 switch (ctxt->mode) {
2139 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2140 if ((msr_data & 0xfffc) == 0x0)
2141 return emulate_gp(ctxt, 0);
8c604352
AP		 2142 break;
2143 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2144 if (msr_data == 0x0)
2145 return emulate_gp(ctxt, 0);
8c604352
AP		 2146 break;
2147 }
2148
2149 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2150 cs_sel = (u16)msr_data;
2151 cs_sel &= ~SELECTOR_RPL_MASK;
2152 ss_sel = cs_sel + 8;
2153 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2154 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2155 cs.d = 0;
8c604352
AP		 2156 cs.l = 1;
2157 }
2158
1aa36616
AK		 2159 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2160 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2161
717746e3 2162 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2163 ctxt->_eip = msr_data;
8c604352 2164
717746e3 2165 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2166 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2167
e54cfa97 2168 return X86EMUL_CONTINUE;
8c604352
AP		 2169}
2170
e01991e7 2171static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2172{
7b105ca2 2173 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2174 struct desc_struct cs, ss;
4668f050
AP		 2175 u64 msr_data;
2176 int usermode;
1249b96e 2177 u16 cs_sel = 0, ss_sel = 0;
4668f050 2178
a0044755
GN		 2179 /* inject #GP if in real mode or Virtual 8086 mode */
2180 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2181 ctxt->mode == X86EMUL_MODE_VM86)
2182 return emulate_gp(ctxt, 0);
4668f050 2183
7b105ca2 2184 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2185
9dac77fa 2186 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2187 usermode = X86EMUL_MODE_PROT64;
2188 else
2189 usermode = X86EMUL_MODE_PROT32;
2190
2191 cs.dpl = 3;
2192 ss.dpl = 3;
717746e3 2193 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2194 switch (usermode) {
2195 case X86EMUL_MODE_PROT32:
79168fd1 2196 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2197 if ((msr_data & 0xfffc) == 0x0)
2198 return emulate_gp(ctxt, 0);
79168fd1 2199 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2200 break;
2201 case X86EMUL_MODE_PROT64:
79168fd1 2202 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2203 if (msr_data == 0x0)
2204 return emulate_gp(ctxt, 0);
79168fd1
GN		 2205 ss_sel = cs_sel + 8;
2206 cs.d = 0;
4668f050
AP		 2207 cs.l = 1;
2208 break;
2209 }
79168fd1
GN		 2210 cs_sel |= SELECTOR_RPL_MASK;
2211 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2212
1aa36616
AK		 2213 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2214 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2215
9dac77fa
AK		 2216 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2217 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2218
e54cfa97 2219 return X86EMUL_CONTINUE;
4668f050
AP		 2220}
2221
7b105ca2 2222static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2223{
2224 int iopl;
2225 if (ctxt->mode == X86EMUL_MODE_REAL)
2226 return false;
2227 if (ctxt->mode == X86EMUL_MODE_VM86)
2228 return true;
2229 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2230 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2231}
2232
2233static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2234 u16 port, u16 len)
2235{
7b105ca2 2236 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2237 struct desc_struct tr_seg;
5601d05b 2238 u32 base3;
f850e2e6 2239 int r;
1aa36616 2240 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2241 unsigned mask = (1 << len) - 1;
5601d05b 2242 unsigned long base;
f850e2e6 2243
1aa36616 2244 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2245 if (!tr_seg.p)
f850e2e6 2246 return false;
79168fd1 2247 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2248 return false;
5601d05b
GN		 2249 base = get_desc_base(&tr_seg);
2250#ifdef CONFIG_X86_64
2251 base |= ((u64)base3) << 32;
2252#endif
0f65dd70 2253 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2254 if (r != X86EMUL_CONTINUE)
2255 return false;
79168fd1 2256 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2257 return false;
0f65dd70 2258 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2259 if (r != X86EMUL_CONTINUE)
2260 return false;
2261 if ((perm >> bit_idx) & mask)
2262 return false;
2263 return true;
2264}
2265
2266static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2267 u16 port, u16 len)
2268{
4fc40f07
GN		 2269 if (ctxt->perm_ok)
2270 return true;
2271
7b105ca2
TY		 2272 if (emulator_bad_iopl(ctxt))
2273 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2274 return false;
4fc40f07
GN		 2275
2276 ctxt->perm_ok = true;
2277
f850e2e6
GN		 2278 return true;
2279}
2280
38ba30ba 2281static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2282 struct tss_segment_16 *tss)
2283{
9dac77fa 2284 tss->ip = ctxt->_eip;
38ba30ba 2285 tss->flag = ctxt->eflags;
9dac77fa
AK		 2286 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2287 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2288 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2289 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2290 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2291 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2292 tss->si = ctxt->regs[VCPU_REGS_RSI];
2293 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2294
1aa36616
AK		 2295 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2296 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2297 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2298 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2299 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2300}
2301
2302static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2303 struct tss_segment_16 *tss)
2304{
38ba30ba
GN		 2305 int ret;
2306
9dac77fa 2307 ctxt->_eip = tss->ip;
38ba30ba 2308 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2309 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2310 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2311 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2312 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2313 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2314 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2315 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2316 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2317
2318 /*
2319 * SDM says that segment selectors are loaded before segment
2320 * descriptors
2321 */
1aa36616
AK		 2322 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2323 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2324 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2325 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2326 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2327
2328 /*
2329 * Now load segment descriptors. If fault happenes at this stage
2330 * it is handled in a context of new task
2331 */
7b105ca2 2332 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2333 if (ret != X86EMUL_CONTINUE)
2334 return ret;
7b105ca2 2335 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2336 if (ret != X86EMUL_CONTINUE)
2337 return ret;
7b105ca2 2338 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2339 if (ret != X86EMUL_CONTINUE)
2340 return ret;
7b105ca2 2341 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2342 if (ret != X86EMUL_CONTINUE)
2343 return ret;
7b105ca2 2344 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2345 if (ret != X86EMUL_CONTINUE)
2346 return ret;
2347
2348 return X86EMUL_CONTINUE;
2349}
2350
2351static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2352 u16 tss_selector, u16 old_tss_sel,
2353 ulong old_tss_base, struct desc_struct *new_desc)
2354{
7b105ca2 2355 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2356 struct tss_segment_16 tss_seg;
2357 int ret;
bcc55cba 2358 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2359
0f65dd70 2360 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2361 &ctxt->exception);
db297e3d 2362 if (ret != X86EMUL_CONTINUE)
38ba30ba 2363 /* FIXME: need to provide precise fault address */
38ba30ba 2364 return ret;
38ba30ba 2365
7b105ca2 2366 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2367
0f65dd70 2368 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2369 &ctxt->exception);
db297e3d 2370 if (ret != X86EMUL_CONTINUE)
38ba30ba 2371 /* FIXME: need to provide precise fault address */
38ba30ba 2372 return ret;
38ba30ba 2373
0f65dd70 2374 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2375 &ctxt->exception);
db297e3d 2376 if (ret != X86EMUL_CONTINUE)
38ba30ba 2377 /* FIXME: need to provide precise fault address */
38ba30ba 2378 return ret;
38ba30ba
GN		 2379
2380 if (old_tss_sel != 0xffff) {
2381 tss_seg.prev_task_link = old_tss_sel;
2382
0f65dd70 2383 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2384 &tss_seg.prev_task_link,
2385 sizeof tss_seg.prev_task_link,
0f65dd70 2386 &ctxt->exception);
db297e3d 2387 if (ret != X86EMUL_CONTINUE)
38ba30ba 2388 /* FIXME: need to provide precise fault address */
38ba30ba 2389 return ret;
38ba30ba
GN		 2390 }
2391
7b105ca2 2392 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2393}
2394
2395static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2396 struct tss_segment_32 *tss)
2397{
7b105ca2 2398 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2399 tss->eip = ctxt->_eip;
38ba30ba 2400 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2401 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2402 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2403 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2404 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2405 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2406 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2407 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2408 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2409
1aa36616
AK		 2410 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2411 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2412 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2413 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2414 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2415 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2416 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2417}
2418
2419static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2420 struct tss_segment_32 *tss)
2421{
38ba30ba
GN		 2422 int ret;
2423
7b105ca2 2424 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2425 return emulate_gp(ctxt, 0);
9dac77fa 2426 ctxt->_eip = tss->eip;
38ba30ba 2427 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2428
2429 /* General purpose registers */
9dac77fa
AK		 2430 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2431 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2432 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2433 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2434 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2435 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2436 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2437 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2438
2439 /*
2440 * SDM says that segment selectors are loaded before segment
2441 * descriptors
2442 */
1aa36616
AK		 2443 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2444 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2445 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2446 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2447 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2448 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2449 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2450
4cee4798
KW		 2451 /*
2452 * If we're switching between Protected Mode and VM86, we need to make
2453 * sure to update the mode before loading the segment descriptors so
2454 * that the selectors are interpreted correctly.
2455 *
2456 * Need to get rflags to the vcpu struct immediately because it
2457 * influences the CPL which is checked at least when loading the segment
2458 * descriptors and when pushing an error code to the new kernel stack.
2459 *
2460 * TODO Introduce a separate ctxt->ops->set_cpl callback
2461 */
2462 if (ctxt->eflags & X86_EFLAGS_VM)
2463 ctxt->mode = X86EMUL_MODE_VM86;
2464 else
2465 ctxt->mode = X86EMUL_MODE_PROT32;
2466
2467 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2468
38ba30ba
GN		 2469 /*
2470 * Now load segment descriptors. If fault happenes at this stage
2471 * it is handled in a context of new task
2472 */
7b105ca2 2473 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
7b105ca2 2476 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2477 if (ret != X86EMUL_CONTINUE)
2478 return ret;
7b105ca2 2479 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2480 if (ret != X86EMUL_CONTINUE)
2481 return ret;
7b105ca2 2482 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2483 if (ret != X86EMUL_CONTINUE)
2484 return ret;
7b105ca2 2485 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2486 if (ret != X86EMUL_CONTINUE)
2487 return ret;
7b105ca2 2488 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2489 if (ret != X86EMUL_CONTINUE)
2490 return ret;
7b105ca2 2491 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2492 if (ret != X86EMUL_CONTINUE)
2493 return ret;
2494
2495 return X86EMUL_CONTINUE;
2496}
2497
2498static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2499 u16 tss_selector, u16 old_tss_sel,
2500 ulong old_tss_base, struct desc_struct *new_desc)
2501{
7b105ca2 2502 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2503 struct tss_segment_32 tss_seg;
2504 int ret;
bcc55cba 2505 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2506
0f65dd70 2507 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2508 &ctxt->exception);
db297e3d 2509 if (ret != X86EMUL_CONTINUE)
38ba30ba 2510 /* FIXME: need to provide precise fault address */
38ba30ba 2511 return ret;
38ba30ba 2512
7b105ca2 2513 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2514
0f65dd70 2515 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2516 &ctxt->exception);
db297e3d 2517 if (ret != X86EMUL_CONTINUE)
38ba30ba 2518 /* FIXME: need to provide precise fault address */
38ba30ba 2519 return ret;
38ba30ba 2520
0f65dd70 2521 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2522 &ctxt->exception);
db297e3d 2523 if (ret != X86EMUL_CONTINUE)
38ba30ba 2524 /* FIXME: need to provide precise fault address */
38ba30ba 2525 return ret;
38ba30ba
GN		 2526
2527 if (old_tss_sel != 0xffff) {
2528 tss_seg.prev_task_link = old_tss_sel;
2529
0f65dd70 2530 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2531 &tss_seg.prev_task_link,
2532 sizeof tss_seg.prev_task_link,
0f65dd70 2533 &ctxt->exception);
db297e3d 2534 if (ret != X86EMUL_CONTINUE)
38ba30ba 2535 /* FIXME: need to provide precise fault address */
38ba30ba 2536 return ret;
38ba30ba
GN		 2537 }
2538
7b105ca2 2539 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2540}
2541
2542static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2543 u16 tss_selector, int idt_index, int reason,
e269fb21 2544 bool has_error_code, u32 error_code)
38ba30ba 2545{
7b105ca2 2546 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2547 struct desc_struct curr_tss_desc, next_tss_desc;
2548 int ret;
1aa36616 2549 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2550 ulong old_tss_base =
4bff1e86 2551 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2552 u32 desc_limit;
38ba30ba
GN		 2553
2554 /* FIXME: old_tss_base == ~0 ? */
2555
7b105ca2 2556 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2557 if (ret != X86EMUL_CONTINUE)
2558 return ret;
7b105ca2 2559 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2560 if (ret != X86EMUL_CONTINUE)
2561 return ret;
2562
2563 /* FIXME: check that next_tss_desc is tss */
2564
7f3d35fd
KW		 2565 /*
2566 * Check privileges. The three cases are task switch caused by...
2567 *
2568 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2569 * 2. Exception/IRQ/iret: No check is performed
2570 * 3. jmp/call to TSS: Check agains DPL of the TSS
2571 */
2572 if (reason == TASK_SWITCH_GATE) {
2573 if (idt_index != -1) {
2574 /* Software interrupts */
2575 struct desc_struct task_gate_desc;
2576 int dpl;
2577
2578 ret = read_interrupt_descriptor(ctxt, idt_index,
2579 &task_gate_desc);
2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
2582
2583 dpl = task_gate_desc.dpl;
2584 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2585 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2586 }
2587 } else if (reason != TASK_SWITCH_IRET) {
2588 int dpl = next_tss_desc.dpl;
2589 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2590 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2591 }
2592
7f3d35fd 2593
ceffb459
GN		 2594 desc_limit = desc_limit_scaled(&next_tss_desc);
2595 if (!next_tss_desc.p ||
2596 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2597 desc_limit < 0x2b)) {
54b8486f 2598 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2599 return X86EMUL_PROPAGATE_FAULT;
2600 }
2601
2602 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2603 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2604 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2605 }
2606
2607 if (reason == TASK_SWITCH_IRET)
2608 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2609
2610 /* set back link to prev task only if NT bit is set in eflags
2611 note that old_tss_sel is not used afetr this point */
2612 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2613 old_tss_sel = 0xffff;
2614
2615 if (next_tss_desc.type & 8)
7b105ca2 2616 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2617 old_tss_base, &next_tss_desc);
2618 else
7b105ca2 2619 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2620 old_tss_base, &next_tss_desc);
0760d448
JK		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
38ba30ba
GN		 2623
2624 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2625 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2626
2627 if (reason != TASK_SWITCH_IRET) {
2628 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2629 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2630 }
2631
717746e3 2632 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2633 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2634
e269fb21 2635 if (has_error_code) {
9dac77fa
AK		 2636 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2637 ctxt->lock_prefix = 0;
2638 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2639 ret = em_push(ctxt);
e269fb21
JK		 2640 }
2641
38ba30ba
GN		 2642 return ret;
2643}
2644
2645int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2646 u16 tss_selector, int idt_index, int reason,
e269fb21 2647 bool has_error_code, u32 error_code)
38ba30ba 2648{
38ba30ba
GN		 2649 int rc;
2650
9dac77fa
AK		 2651 ctxt->_eip = ctxt->eip;
2652 ctxt->dst.type = OP_NONE;
38ba30ba 2653
7f3d35fd 2654 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2655 has_error_code, error_code);
38ba30ba 2656
4179bb02 2657 if (rc == X86EMUL_CONTINUE)
9dac77fa 2658 ctxt->eip = ctxt->_eip;
38ba30ba 2659
a0c0ab2f 2660 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2661}
2662
90de84f5 2663static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2664 int reg, struct operand *op)
a682e354 2665{
a682e354
GN		 2666 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2667
9dac77fa
AK		 2668 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2669 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2670 op->addr.mem.seg = seg;
a682e354
GN		 2671}
2672
7af04fc0
AK		 2673static int em_das(struct x86_emulate_ctxt *ctxt)
2674{
7af04fc0
AK		 2675 u8 al, old_al;
2676 bool af, cf, old_cf;
2677
2678 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2679 al = ctxt->dst.val;
7af04fc0
AK		 2680
2681 old_al = al;
2682 old_cf = cf;
2683 cf = false;
2684 af = ctxt->eflags & X86_EFLAGS_AF;
2685 if ((al & 0x0f) > 9 || af) {
2686 al -= 6;
2687 cf = old_cf | (al >= 250);
2688 af = true;
2689 } else {
2690 af = false;
2691 }
2692 if (old_al > 0x99 || old_cf) {
2693 al -= 0x60;
2694 cf = true;
2695 }
2696
9dac77fa 2697 ctxt->dst.val = al;
7af04fc0 2698 /* Set PF, ZF, SF */
9dac77fa
AK		 2699 ctxt->src.type = OP_IMM;
2700 ctxt->src.val = 0;
2701 ctxt->src.bytes = 1;
a31b9cea 2702 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2703 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2704 if (cf)
2705 ctxt->eflags |= X86_EFLAGS_CF;
2706 if (af)
2707 ctxt->eflags |= X86_EFLAGS_AF;
2708 return X86EMUL_CONTINUE;
2709}
2710
d4ddafcd
TY		 2711static int em_call(struct x86_emulate_ctxt *ctxt)
2712{
2713 long rel = ctxt->src.val;
2714
2715 ctxt->src.val = (unsigned long)ctxt->_eip;
2716 jmp_rel(ctxt, rel);
2717 return em_push(ctxt);
2718}
2719
0ef753b8
AK		 2720static int em_call_far(struct x86_emulate_ctxt *ctxt)
2721{
0ef753b8
AK		 2722 u16 sel, old_cs;
2723 ulong old_eip;
2724 int rc;
2725
1aa36616 2726 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2727 old_eip = ctxt->_eip;
0ef753b8 2728
9dac77fa 2729 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2730 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2731 return X86EMUL_CONTINUE;
2732
9dac77fa
AK		 2733 ctxt->_eip = 0;
2734 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2735
9dac77fa 2736 ctxt->src.val = old_cs;
4487b3b4 2737 rc = em_push(ctxt);
0ef753b8
AK		 2738 if (rc != X86EMUL_CONTINUE)
2739 return rc;
2740
9dac77fa 2741 ctxt->src.val = old_eip;
4487b3b4 2742 return em_push(ctxt);
0ef753b8
AK		 2743}
2744
40ece7c7
AK		 2745static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2746{
40ece7c7
AK		 2747 int rc;
2748
9dac77fa
AK		 2749 ctxt->dst.type = OP_REG;
2750 ctxt->dst.addr.reg = &ctxt->_eip;
2751 ctxt->dst.bytes = ctxt->op_bytes;
2752 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2753 if (rc != X86EMUL_CONTINUE)
2754 return rc;
9dac77fa 2755 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2756 return X86EMUL_CONTINUE;
2757}
2758
d67fc27a
TY		 2759static int em_add(struct x86_emulate_ctxt *ctxt)
2760{
a31b9cea 2761 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2762 return X86EMUL_CONTINUE;
2763}
2764
2765static int em_or(struct x86_emulate_ctxt *ctxt)
2766{
a31b9cea 2767 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2768 return X86EMUL_CONTINUE;
2769}
2770
2771static int em_adc(struct x86_emulate_ctxt *ctxt)
2772{
a31b9cea 2773 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2774 return X86EMUL_CONTINUE;
2775}
2776
2777static int em_sbb(struct x86_emulate_ctxt *ctxt)
2778{
a31b9cea 2779 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2780 return X86EMUL_CONTINUE;
2781}
2782
2783static int em_and(struct x86_emulate_ctxt *ctxt)
2784{
a31b9cea 2785 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2786 return X86EMUL_CONTINUE;
2787}
2788
2789static int em_sub(struct x86_emulate_ctxt *ctxt)
2790{
a31b9cea 2791 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2792 return X86EMUL_CONTINUE;
2793}
2794
2795static int em_xor(struct x86_emulate_ctxt *ctxt)
2796{
a31b9cea 2797 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2798 return X86EMUL_CONTINUE;
2799}
2800
2801static int em_cmp(struct x86_emulate_ctxt *ctxt)
2802{
a31b9cea 2803 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2804 /* Disable writeback. */
9dac77fa 2805 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2806 return X86EMUL_CONTINUE;
2807}
2808
9f21ca59
TY		 2809static int em_test(struct x86_emulate_ctxt *ctxt)
2810{
a31b9cea 2811 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2812 /* Disable writeback. */
2813 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2814 return X86EMUL_CONTINUE;
2815}
2816
e4f973ae
TY		 2817static int em_xchg(struct x86_emulate_ctxt *ctxt)
2818{
e4f973ae 2819 /* Write back the register source. */
9dac77fa
AK		 2820 ctxt->src.val = ctxt->dst.val;
2821 write_register_operand(&ctxt->src);
e4f973ae
TY		 2822
2823 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2824 ctxt->dst.val = ctxt->src.orig_val;
2825 ctxt->lock_prefix = 1;
e4f973ae
TY		 2826 return X86EMUL_CONTINUE;
2827}
2828
5c82aa29 2829static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2830{
a31b9cea 2831 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2832 return X86EMUL_CONTINUE;
2833}
2834
5c82aa29
AK		 2835static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2836{
9dac77fa 2837 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2838 return em_imul(ctxt);
2839}
2840
61429142
AK		 2841static int em_cwd(struct x86_emulate_ctxt *ctxt)
2842{
9dac77fa
AK		 2843 ctxt->dst.type = OP_REG;
2844 ctxt->dst.bytes = ctxt->src.bytes;
2845 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2846 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2847
2848 return X86EMUL_CONTINUE;
2849}
2850
48bb5d3c
AK		 2851static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2852{
48bb5d3c
AK		 2853 u64 tsc = 0;
2854
717746e3 2855 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2856 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2857 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2858 return X86EMUL_CONTINUE;
2859}
2860
222d21aa
AK		 2861static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2862{
2863 u64 pmc;
2864
2865 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2866 return emulate_gp(ctxt, 0);
2867 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2868 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2869 return X86EMUL_CONTINUE;
2870}
2871
b9eac5f4
AK		 2872static int em_mov(struct x86_emulate_ctxt *ctxt)
2873{
49597d81 2874 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2875 return X86EMUL_CONTINUE;
2876}
2877
bc00f8d2
TY		 2878static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2879{
2880 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2881 return emulate_gp(ctxt, 0);
2882
2883 /* Disable writeback. */
2884 ctxt->dst.type = OP_NONE;
2885 return X86EMUL_CONTINUE;
2886}
2887
2888static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2889{
2890 unsigned long val;
2891
2892 if (ctxt->mode == X86EMUL_MODE_PROT64)
2893 val = ctxt->src.val & ~0ULL;
2894 else
2895 val = ctxt->src.val & ~0U;
2896
2897 /* #UD condition is already handled. */
2898 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2899 return emulate_gp(ctxt, 0);
2900
2901 /* Disable writeback. */
2902 ctxt->dst.type = OP_NONE;
2903 return X86EMUL_CONTINUE;
2904}
2905
e1e210b0
TY		 2906static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2907{
2908 u64 msr_data;
2909
2910 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2911 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2912 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2913 return emulate_gp(ctxt, 0);
2914
2915 return X86EMUL_CONTINUE;
2916}
2917
2918static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2919{
2920 u64 msr_data;
2921
2922 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2923 return emulate_gp(ctxt, 0);
2924
2925 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2926 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2927 return X86EMUL_CONTINUE;
2928}
2929
1bd5f469
TY		 2930static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2931{
9dac77fa 2932 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2933 return emulate_ud(ctxt);
2934
9dac77fa 2935 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2936 return X86EMUL_CONTINUE;
2937}
2938
2939static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2940{
9dac77fa 2941 u16 sel = ctxt->src.val;
1bd5f469 2942
9dac77fa 2943 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2944 return emulate_ud(ctxt);
2945
9dac77fa 2946 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2947 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2948
2949 /* Disable writeback. */
9dac77fa
AK		 2950 ctxt->dst.type = OP_NONE;
2951 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2952}
2953
38503911
AK		 2954static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2955{
9fa088f4
AK		 2956 int rc;
2957 ulong linear;
2958
9dac77fa 2959 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2960 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2961 ctxt->ops->invlpg(ctxt, linear);
38503911 2962 /* Disable writeback. */
9dac77fa 2963 ctxt->dst.type = OP_NONE;
38503911
AK		 2964 return X86EMUL_CONTINUE;
2965}
2966
2d04a05b
AK		 2967static int em_clts(struct x86_emulate_ctxt *ctxt)
2968{
2969 ulong cr0;
2970
2971 cr0 = ctxt->ops->get_cr(ctxt, 0);
2972 cr0 &= ~X86_CR0_TS;
2973 ctxt->ops->set_cr(ctxt, 0, cr0);
2974 return X86EMUL_CONTINUE;
2975}
2976
26d05cc7
AK		 2977static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2978{
26d05cc7
AK		 2979 int rc;
2980
9dac77fa 2981 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2982 return X86EMUL_UNHANDLEABLE;
2983
2984 rc = ctxt->ops->fix_hypercall(ctxt);
2985 if (rc != X86EMUL_CONTINUE)
2986 return rc;
2987
2988 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2989 ctxt->_eip = ctxt->eip;
26d05cc7 2990 /* Disable writeback. */
9dac77fa 2991 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2992 return X86EMUL_CONTINUE;
2993}
2994
2995static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2996{
26d05cc7
AK		 2997 struct desc_ptr desc_ptr;
2998 int rc;
2999
9dac77fa 3000 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3001 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3002 ctxt->op_bytes);
26d05cc7
AK		 3003 if (rc != X86EMUL_CONTINUE)
3004 return rc;
3005 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3006 /* Disable writeback. */
9dac77fa 3007 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3008 return X86EMUL_CONTINUE;
3009}
3010
5ef39c71 3011static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3012{
26d05cc7
AK		 3013 int rc;
3014
5ef39c71
AK		 3015 rc = ctxt->ops->fix_hypercall(ctxt);
3016
26d05cc7 3017 /* Disable writeback. */
9dac77fa 3018 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3019 return rc;
3020}
3021
3022static int em_lidt(struct x86_emulate_ctxt *ctxt)
3023{
26d05cc7
AK		 3024 struct desc_ptr desc_ptr;
3025 int rc;
3026
9dac77fa 3027 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3028 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3029 ctxt->op_bytes);
26d05cc7
AK		 3030 if (rc != X86EMUL_CONTINUE)
3031 return rc;
3032 ctxt->ops->set_idt(ctxt, &desc_ptr);
3033 /* Disable writeback. */
9dac77fa 3034 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3035 return X86EMUL_CONTINUE;
3036}
3037
3038static int em_smsw(struct x86_emulate_ctxt *ctxt)
3039{
9dac77fa
AK		 3040 ctxt->dst.bytes = 2;
3041 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3042 return X86EMUL_CONTINUE;
3043}
3044
3045static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3046{
26d05cc7 3047 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3048 | (ctxt->src.val & 0x0f));
3049 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3050 return X86EMUL_CONTINUE;
3051}
3052
d06e03ad
TY		 3053static int em_loop(struct x86_emulate_ctxt *ctxt)
3054{
9dac77fa
AK		 3055 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3056 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3057 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3058 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3059
3060 return X86EMUL_CONTINUE;
3061}
3062
3063static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3064{
9dac77fa
AK		 3065 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3066 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3067
3068 return X86EMUL_CONTINUE;
3069}
3070
d7841a4b
TY		 3071static int em_in(struct x86_emulate_ctxt *ctxt)
3072{
3073 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3074 &ctxt->dst.val))
3075 return X86EMUL_IO_NEEDED;
3076
3077 return X86EMUL_CONTINUE;
3078}
3079
3080static int em_out(struct x86_emulate_ctxt *ctxt)
3081{
3082 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3083 &ctxt->src.val, 1);
3084 /* Disable writeback. */
3085 ctxt->dst.type = OP_NONE;
3086 return X86EMUL_CONTINUE;
3087}
3088
f411e6cd
TY		 3089static int em_cli(struct x86_emulate_ctxt *ctxt)
3090{
3091 if (emulator_bad_iopl(ctxt))
3092 return emulate_gp(ctxt, 0);
3093
3094 ctxt->eflags &= ~X86_EFLAGS_IF;
3095 return X86EMUL_CONTINUE;
3096}
3097
3098static int em_sti(struct x86_emulate_ctxt *ctxt)
3099{
3100 if (emulator_bad_iopl(ctxt))
3101 return emulate_gp(ctxt, 0);
3102
3103 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3104 ctxt->eflags |= X86_EFLAGS_IF;
3105 return X86EMUL_CONTINUE;
3106}
3107
ce7faab2
TY		 3108static int em_bt(struct x86_emulate_ctxt *ctxt)
3109{
3110 /* Disable writeback. */
3111 ctxt->dst.type = OP_NONE;
3112 /* only subword offset */
3113 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3114
3115 emulate_2op_SrcV_nobyte(ctxt, "bt");
3116 return X86EMUL_CONTINUE;
3117}
3118
3119static int em_bts(struct x86_emulate_ctxt *ctxt)
3120{
3121 emulate_2op_SrcV_nobyte(ctxt, "bts");
3122 return X86EMUL_CONTINUE;
3123}
3124
3125static int em_btr(struct x86_emulate_ctxt *ctxt)
3126{
3127 emulate_2op_SrcV_nobyte(ctxt, "btr");
3128 return X86EMUL_CONTINUE;
3129}
3130
3131static int em_btc(struct x86_emulate_ctxt *ctxt)
3132{
3133 emulate_2op_SrcV_nobyte(ctxt, "btc");
3134 return X86EMUL_CONTINUE;
3135}
3136
ff227392
TY		 3137static int em_bsf(struct x86_emulate_ctxt *ctxt)
3138{
d54e4237 3139 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3140 return X86EMUL_CONTINUE;
3141}
3142
3143static int em_bsr(struct x86_emulate_ctxt *ctxt)
3144{
d54e4237 3145 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3146 return X86EMUL_CONTINUE;
3147}
3148
6d6eede4
AK		 3149static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3150{
3151 u32 eax, ebx, ecx, edx;
3152
3153 eax = ctxt->regs[VCPU_REGS_RAX];
3154 ecx = ctxt->regs[VCPU_REGS_RCX];
3155 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3156 ctxt->regs[VCPU_REGS_RAX] = eax;
3157 ctxt->regs[VCPU_REGS_RBX] = ebx;
3158 ctxt->regs[VCPU_REGS_RCX] = ecx;
3159 ctxt->regs[VCPU_REGS_RDX] = edx;
3160 return X86EMUL_CONTINUE;
3161}
3162
cfec82cb
JR		 3163static bool valid_cr(int nr)
3164{
3165 switch (nr) {
3166 case 0:
3167 case 2 ... 4:
3168 case 8:
3169 return true;
3170 default:
3171 return false;
3172 }
3173}
3174
3175static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3176{
9dac77fa 3177 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3178 return emulate_ud(ctxt);
3179
3180 return X86EMUL_CONTINUE;
3181}
3182
3183static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3184{
9dac77fa
AK		 3185 u64 new_val = ctxt->src.val64;
3186 int cr = ctxt->modrm_reg;
c2ad2bb3 3187 u64 efer = 0;
cfec82cb
JR		 3188
3189 static u64 cr_reserved_bits[] = {
3190 0xffffffff00000000ULL,
3191 0, 0, 0, /* CR3 checked later */
3192 CR4_RESERVED_BITS,
3193 0, 0, 0,
3194 CR8_RESERVED_BITS,
3195 };
3196
3197 if (!valid_cr(cr))
3198 return emulate_ud(ctxt);
3199
3200 if (new_val & cr_reserved_bits[cr])
3201 return emulate_gp(ctxt, 0);
3202
3203 switch (cr) {
3204 case 0: {
c2ad2bb3 3205 u64 cr4;
cfec82cb
JR		 3206 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3207 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3208 return emulate_gp(ctxt, 0);
3209
717746e3
AK		 3210 cr4 = ctxt->ops->get_cr(ctxt, 4);
3211 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3212
3213 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3214 !(cr4 & X86_CR4_PAE))
3215 return emulate_gp(ctxt, 0);
3216
3217 break;
3218 }
3219 case 3: {
3220 u64 rsvd = 0;
3221
c2ad2bb3
AK		 3222 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3223 if (efer & EFER_LMA)
cfec82cb 3224 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3225 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3226 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3227 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3228 rsvd = CR3_NONPAE_RESERVED_BITS;
3229
3230 if (new_val & rsvd)
3231 return emulate_gp(ctxt, 0);
3232
3233 break;
3234 }
3235 case 4: {
717746e3 3236 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3237
3238 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3239 return emulate_gp(ctxt, 0);
3240
3241 break;
3242 }
3243 }
3244
3245 return X86EMUL_CONTINUE;
3246}
3247
3b88e41a
JR		 3248static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3249{
3250 unsigned long dr7;
3251
717746e3 3252 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3253
3254 /* Check if DR7.Global_Enable is set */
3255 return dr7 & (1 << 13);
3256}
3257
3258static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3259{
9dac77fa 3260 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3261 u64 cr4;
3262
3263 if (dr > 7)
3264 return emulate_ud(ctxt);
3265
717746e3 3266 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3267 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3268 return emulate_ud(ctxt);
3269
3270 if (check_dr7_gd(ctxt))
3271 return emulate_db(ctxt);
3272
3273 return X86EMUL_CONTINUE;
3274}
3275
3276static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3277{
9dac77fa
AK		 3278 u64 new_val = ctxt->src.val64;
3279 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3280
3281 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3282 return emulate_gp(ctxt, 0);
3283
3284 return check_dr_read(ctxt);
3285}
3286
01de8b09
JR		 3287static int check_svme(struct x86_emulate_ctxt *ctxt)
3288{
3289 u64 efer;
3290
717746e3 3291 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3292
3293 if (!(efer & EFER_SVME))
3294 return emulate_ud(ctxt);
3295
3296 return X86EMUL_CONTINUE;
3297}
3298
3299static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3300{
9dac77fa 3301 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3302
3303 /* Valid physical address? */
d4224449 3304 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3305 return emulate_gp(ctxt, 0);
3306
3307 return check_svme(ctxt);
3308}
3309
d7eb8203
JR		 3310static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3311{
717746e3 3312 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3313
717746e3 3314 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3315 return emulate_ud(ctxt);
3316
3317 return X86EMUL_CONTINUE;
3318}
3319
8061252e
JR		 3320static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3321{
717746e3 3322 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3323 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3324
717746e3 3325 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3326 (rcx > 3))
3327 return emulate_gp(ctxt, 0);
3328
3329 return X86EMUL_CONTINUE;
3330}
3331
f6511935
JR		 3332static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3333{
9dac77fa
AK		 3334 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3335 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3336 return emulate_gp(ctxt, 0);
3337
3338 return X86EMUL_CONTINUE;
3339}
3340
3341static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3342{
9dac77fa
AK		 3343 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3344 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3345 return emulate_gp(ctxt, 0);
3346
3347 return X86EMUL_CONTINUE;
3348}
3349
73fba5f4 3350#define D(_y) { .flags = (_y) }
c4f035c6 3351#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3352#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3353 .check_perm = (_p) }
73fba5f4 3354#define N D(0)
01de8b09 3355#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3356#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3357#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3358#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3359#define II(_f, _e, _i) \
3360 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3361#define IIP(_f, _e, _i, _p) \
3362 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3363 .check_perm = (_p) }
aa97bb48 3364#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3365
8d8f4e9f 3366#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3367#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3368#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3369#define I2bvIP(_f, _e, _i, _p) \
3370 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3371
d67fc27a
TY		 3372#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3373 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3374 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3375
d7eb8203 3376static struct opcode group7_rm1[] = {
1c2545be
TY		 3377 DI(SrcNone | Priv, monitor),
3378 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3379 N, N, N, N, N, N,
3380};
3381
01de8b09 3382static struct opcode group7_rm3[] = {
1c2545be
TY		 3383 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3384 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3385 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3386 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3387 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3388 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3389 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3390 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3391};
6230f7fc 3392
d7eb8203
JR		 3393static struct opcode group7_rm7[] = {
3394 N,
1c2545be 3395 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3396 N, N, N, N, N, N,
3397};
d67fc27a 3398
73fba5f4 3399static struct opcode group1[] = {
d67fc27a 3400 I(Lock, em_add),
d5ae7ce8 3401 I(Lock | PageTable, em_or),
d67fc27a
TY		 3402 I(Lock, em_adc),
3403 I(Lock, em_sbb),
d5ae7ce8 3404 I(Lock | PageTable, em_and),
d67fc27a
TY		 3405 I(Lock, em_sub),
3406 I(Lock, em_xor),
3407 I(0, em_cmp),
73fba5f4
AK		 3408};
3409
3410static struct opcode group1A[] = {
1c2545be 3411 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3412};
3413
3414static struct opcode group3[] = {
1c2545be
TY		 3415 I(DstMem | SrcImm, em_test),
3416 I(DstMem | SrcImm, em_test),
3417 I(DstMem | SrcNone | Lock, em_not),
3418 I(DstMem | SrcNone | Lock, em_neg),
3419 I(SrcMem, em_mul_ex),
3420 I(SrcMem, em_imul_ex),
3421 I(SrcMem, em_div_ex),
3422 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3423};
3424
3425static struct opcode group4[] = {
1c2545be
TY		 3426 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3427 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3428 N, N, N, N, N, N,
3429};
3430
3431static struct opcode group5[] = {
1c2545be
TY		 3432 I(DstMem | SrcNone | Lock, em_grp45),
3433 I(DstMem | SrcNone | Lock, em_grp45),
3434 I(SrcMem | Stack, em_grp45),
3435 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3436 I(SrcMem | Stack, em_grp45),
3437 I(SrcMemFAddr | ImplicitOps, em_grp45),
3438 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3439};
3440
dee6bb70 3441static struct opcode group6[] = {
1c2545be
TY		 3442 DI(Prot, sldt),
3443 DI(Prot, str),
3444 DI(Prot | Priv, lldt),
3445 DI(Prot | Priv, ltr),
dee6bb70
JR		 3446 N, N, N, N,
3447};
3448
73fba5f4 3449static struct group_dual group7 = { {
1c2545be
TY		 3450 DI(Mov | DstMem | Priv, sgdt),
3451 DI(Mov | DstMem | Priv, sidt),
3452 II(SrcMem | Priv, em_lgdt, lgdt),
3453 II(SrcMem | Priv, em_lidt, lidt),
3454 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3455 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3456 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3457}, {
1c2545be 3458 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3459 EXT(0, group7_rm1),
01de8b09 3460 N, EXT(0, group7_rm3),
1c2545be
TY		 3461 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3462 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3463 EXT(0, group7_rm7),
73fba5f4
AK		 3464} };
3465
3466static struct opcode group8[] = {
3467 N, N, N, N,
1c2545be
TY		 3468 I(DstMem | SrcImmByte, em_bt),
3469 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3470 I(DstMem | SrcImmByte | Lock, em_btr),
3471 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3472};
3473
3474static struct group_dual group9 = { {
1c2545be 3475 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3476}, {
3477 N, N, N, N, N, N, N, N,
3478} };
3479
a4d4a7c1 3480static struct opcode group11[] = {
1c2545be 3481 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3482 X7(D(Undefined)),
a4d4a7c1
AK		 3483};
3484
aa97bb48 3485static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3486 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3487};
3488
3e114eb4
AK		 3489static struct gprefix pfx_vmovntpx = {
3490 I(0, em_mov), N, N, N,
3491};
3492
73fba5f4
AK		 3493static struct opcode opcode_table[256] = {
3494 /* 0x00 - 0x07 */
d67fc27a 3495 I6ALU(Lock, em_add),
1cd196ea
AK		 3496 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3497 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3498 /* 0x08 - 0x0F */
d5ae7ce8 3499 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3500 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3501 N,
73fba5f4 3502 /* 0x10 - 0x17 */
d67fc27a 3503 I6ALU(Lock, em_adc),
1cd196ea
AK		 3504 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3505 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3506 /* 0x18 - 0x1F */
d67fc27a 3507 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3508 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3509 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3510 /* 0x20 - 0x27 */
d5ae7ce8 3511 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3512 /* 0x28 - 0x2F */
d67fc27a 3513 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3514 /* 0x30 - 0x37 */
d67fc27a 3515 I6ALU(Lock, em_xor), N, N,
73fba5f4 3516 /* 0x38 - 0x3F */
d67fc27a 3517 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3518 /* 0x40 - 0x4F */
3519 X16(D(DstReg)),
3520 /* 0x50 - 0x57 */
63540382 3521 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3522 /* 0x58 - 0x5F */
c54fe504 3523 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3524 /* 0x60 - 0x67 */
b96a7fad
TY		 3525 I(ImplicitOps | Stack | No64, em_pusha),
3526 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3527 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3528 N, N, N, N,
3529 /* 0x68 - 0x6F */
d46164db
AK		 3530 I(SrcImm | Mov | Stack, em_push),
3531 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3532 I(SrcImmByte | Mov | Stack, em_push),
3533 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3534 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3535 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3536 /* 0x70 - 0x7F */
3537 X16(D(SrcImmByte)),
3538 /* 0x80 - 0x87 */
1c2545be
TY		 3539 G(ByteOp | DstMem | SrcImm, group1),
3540 G(DstMem | SrcImm, group1),
3541 G(ByteOp | DstMem | SrcImm | No64, group1),
3542 G(DstMem | SrcImmByte, group1),
9f21ca59 3543 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3544 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3545 /* 0x88 - 0x8F */
d5ae7ce8 3546 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3547 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3548 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3549 D(ModRM | SrcMem | NoAccess | DstReg),
3550 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3551 G(0, group1A),
73fba5f4 3552 /* 0x90 - 0x97 */
bf608f88 3553 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3554 /* 0x98 - 0x9F */
61429142 3555 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3556 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3557 II(ImplicitOps | Stack, em_pushf, pushf),
3558 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3559 /* 0xA0 - 0xA7 */
b9eac5f4 3560 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3561 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3562 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3563 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3564 /* 0xA8 - 0xAF */
9f21ca59 3565 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3566 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3567 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3568 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3569 /* 0xB0 - 0xB7 */
b9eac5f4 3570 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3571 /* 0xB8 - 0xBF */
b9eac5f4 3572 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3573 /* 0xC0 - 0xC7 */
d2c6c7ad 3574 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3575 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3576 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3577 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3578 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3579 G(ByteOp, group11), G(0, group11),
73fba5f4 3580 /* 0xC8 - 0xCF */
db5b0762 3581 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3582 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3583 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3584 /* 0xD0 - 0xD7 */
d2c6c7ad 3585 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3586 N, N, N, N,
3587 /* 0xD8 - 0xDF */
3588 N, N, N, N, N, N, N, N,
3589 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3590 X3(I(SrcImmByte, em_loop)),
3591 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3592 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3593 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3594 /* 0xE8 - 0xEF */
d4ddafcd 3595 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3596 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3597 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3598 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3599 /* 0xF0 - 0xF7 */
bf608f88 3600 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3601 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3602 G(ByteOp, group3), G(0, group3),
73fba5f4 3603 /* 0xF8 - 0xFF */
f411e6cd
TY		 3604 D(ImplicitOps), D(ImplicitOps),
3605 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3606 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3607};
3608
3609static struct opcode twobyte_table[256] = {
3610 /* 0x00 - 0x0F */
dee6bb70 3611 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3612 N, I(ImplicitOps | VendorSpecific, em_syscall),
3613 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3614 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3615 N, D(ImplicitOps | ModRM), N, N,
3616 /* 0x10 - 0x1F */
3617 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3618 /* 0x20 - 0x2F */
cfec82cb 3619 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3620 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3621 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3622 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3623 N, N, N, N,
3e114eb4
AK		 3624 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3625 N, N, N, N,
73fba5f4 3626 /* 0x30 - 0x3F */
e1e210b0 3627 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3628 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3629 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3630 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3631 I(ImplicitOps | VendorSpecific, em_sysenter),
3632 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3633 N, N,
73fba5f4
AK		 3634 N, N, N, N, N, N, N, N,
3635 /* 0x40 - 0x4F */
3636 X16(D(DstReg | SrcMem | ModRM | Mov)),
3637 /* 0x50 - 0x5F */
3638 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3639 /* 0x60 - 0x6F */
aa97bb48
AK		 3640 N, N, N, N,
3641 N, N, N, N,
3642 N, N, N, N,
3643 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3644 /* 0x70 - 0x7F */
aa97bb48
AK		 3645 N, N, N, N,
3646 N, N, N, N,
3647 N, N, N, N,
3648 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3649 /* 0x80 - 0x8F */
3650 X16(D(SrcImm)),
3651 /* 0x90 - 0x9F */
ee45b58e 3652 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3653 /* 0xA0 - 0xA7 */
1cd196ea 3654 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3655 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3656 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3657 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3658 /* 0xA8 - 0xAF */
1cd196ea 3659 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3660 DI(ImplicitOps, rsm),
ce7faab2 3661 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3662 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3663 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3664 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3665 /* 0xB0 - 0xB7 */
e940b5c2 3666 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3667 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3668 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3669 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3670 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3671 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3672 /* 0xB8 - 0xBF */
3673 N, N,
ce7faab2
TY		 3674 G(BitOp, group8),
3675 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3676 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3677 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3678 /* 0xC0 - 0xCF */
739ae406 3679 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3680 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3681 N, N, N, GD(0, &group9),
3682 N, N, N, N, N, N, N, N,
3683 /* 0xD0 - 0xDF */
3684 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3685 /* 0xE0 - 0xEF */
3686 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3687 /* 0xF0 - 0xFF */
3688 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3689};
3690
3691#undef D
3692#undef N
3693#undef G
3694#undef GD
3695#undef I
aa97bb48 3696#undef GP
01de8b09 3697#undef EXT
73fba5f4 3698
8d8f4e9f 3699#undef D2bv
f6511935 3700#undef D2bvIP
8d8f4e9f 3701#undef I2bv
d7841a4b 3702#undef I2bvIP
d67fc27a 3703#undef I6ALU
8d8f4e9f 3704
9dac77fa 3705static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3706{
3707 unsigned size;
3708
9dac77fa 3709 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3710 if (size == 8)
3711 size = 4;
3712 return size;
3713}
3714
3715static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3716 unsigned size, bool sign_extension)
3717{
39f21ee5
AK		 3718 int rc = X86EMUL_CONTINUE;
3719
3720 op->type = OP_IMM;
3721 op->bytes = size;
9dac77fa 3722 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3723 /* NB. Immediates are sign-extended as necessary. */
3724 switch (op->bytes) {
3725 case 1:
e85a1085 3726 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3727 break;
3728 case 2:
e85a1085 3729 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3730 break;
3731 case 4:
e85a1085 3732 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3733 break;
3734 }
3735 if (!sign_extension) {
3736 switch (op->bytes) {
3737 case 1:
3738 op->val &= 0xff;
3739 break;
3740 case 2:
3741 op->val &= 0xffff;
3742 break;
3743 case 4:
3744 op->val &= 0xffffffff;
3745 break;
3746 }
3747 }
3748done:
3749 return rc;
3750}
3751
a9945549
AK		 3752static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3753 unsigned d)
3754{
3755 int rc = X86EMUL_CONTINUE;
3756
3757 switch (d) {
3758 case OpReg:
2adb5ad9 3759 decode_register_operand(ctxt, op);
a9945549
AK		 3760 break;
3761 case OpImmUByte:
608aabe3 3762 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3763 break;
3764 case OpMem:
41ddf978 3765 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3766 mem_common:
3767 *op = ctxt->memop;
3768 ctxt->memopp = op;
3769 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3770 fetch_bit_operand(ctxt);
3771 op->orig_val = op->val;
3772 break;
41ddf978
AK		 3773 case OpMem64:
3774 ctxt->memop.bytes = 8;
3775 goto mem_common;
a9945549
AK		 3776 case OpAcc:
3777 op->type = OP_REG;
3778 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3779 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3780 fetch_register_operand(op);
3781 op->orig_val = op->val;
3782 break;
3783 case OpDI:
3784 op->type = OP_MEM;
3785 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3786 op->addr.mem.ea =
3787 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3788 op->addr.mem.seg = VCPU_SREG_ES;
3789 op->val = 0;
3790 break;
3791 case OpDX:
3792 op->type = OP_REG;
3793 op->bytes = 2;
3794 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3795 fetch_register_operand(op);
3796 break;
4dd6a57d
AK		 3797 case OpCL:
3798 op->bytes = 1;
3799 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3800 break;
3801 case OpImmByte:
3802 rc = decode_imm(ctxt, op, 1, true);
3803 break;
3804 case OpOne:
3805 op->bytes = 1;
3806 op->val = 1;
3807 break;
3808 case OpImm:
3809 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3810 break;
28867cee
AK		 3811 case OpMem8:
3812 ctxt->memop.bytes = 1;
3813 goto mem_common;
0fe59128
AK		 3814 case OpMem16:
3815 ctxt->memop.bytes = 2;
3816 goto mem_common;
3817 case OpMem32:
3818 ctxt->memop.bytes = 4;
3819 goto mem_common;
3820 case OpImmU16:
3821 rc = decode_imm(ctxt, op, 2, false);
3822 break;
3823 case OpImmU:
3824 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3825 break;
3826 case OpSI:
3827 op->type = OP_MEM;
3828 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3829 op->addr.mem.ea =
3830 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3831 op->addr.mem.seg = seg_override(ctxt);
3832 op->val = 0;
3833 break;
3834 case OpImmFAddr:
3835 op->type = OP_IMM;
3836 op->addr.mem.ea = ctxt->_eip;
3837 op->bytes = ctxt->op_bytes + 2;
3838 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3839 break;
3840 case OpMemFAddr:
3841 ctxt->memop.bytes = ctxt->op_bytes + 2;
3842 goto mem_common;
c191a7a0
AK		 3843 case OpES:
3844 op->val = VCPU_SREG_ES;
3845 break;
3846 case OpCS:
3847 op->val = VCPU_SREG_CS;
3848 break;
3849 case OpSS:
3850 op->val = VCPU_SREG_SS;
3851 break;
3852 case OpDS:
3853 op->val = VCPU_SREG_DS;
3854 break;
3855 case OpFS:
3856 op->val = VCPU_SREG_FS;
3857 break;
3858 case OpGS:
3859 op->val = VCPU_SREG_GS;
3860 break;
a9945549
AK		 3861 case OpImplicit:
3862 /* Special instructions do their own operand decoding. */
3863 default:
3864 op->type = OP_NONE; /* Disable writeback. */
3865 break;
3866 }
3867
3868done:
3869 return rc;
3870}
3871
ef5d75cc 3872int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3873{
dde7e6d1
AK		 3874 int rc = X86EMUL_CONTINUE;
3875 int mode = ctxt->mode;
46561646 3876 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3877 bool op_prefix = false;
46561646 3878 struct opcode opcode;
dde7e6d1 3879
f09ed83e
AK		 3880 ctxt->memop.type = OP_NONE;
3881 ctxt->memopp = NULL;
9dac77fa
AK		 3882 ctxt->_eip = ctxt->eip;
3883 ctxt->fetch.start = ctxt->_eip;
3884 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3885 if (insn_len > 0)
9dac77fa 3886 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3887
3888 switch (mode) {
3889 case X86EMUL_MODE_REAL:
3890 case X86EMUL_MODE_VM86:
3891 case X86EMUL_MODE_PROT16:
3892 def_op_bytes = def_ad_bytes = 2;
3893 break;
3894 case X86EMUL_MODE_PROT32:
3895 def_op_bytes = def_ad_bytes = 4;
3896 break;
3897#ifdef CONFIG_X86_64
3898 case X86EMUL_MODE_PROT64:
3899 def_op_bytes = 4;
3900 def_ad_bytes = 8;
3901 break;
3902#endif
3903 default:
1d2887e2 3904 return EMULATION_FAILED;
dde7e6d1
AK		 3905 }
3906
9dac77fa
AK		 3907 ctxt->op_bytes = def_op_bytes;
3908 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3909
3910 /* Legacy prefixes. */
3911 for (;;) {
e85a1085 3912 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3913 case 0x66: /* operand-size override */
0d7cdee8 3914 op_prefix = true;
dde7e6d1 3915 /* switch between 2/4 bytes */
9dac77fa 3916 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3917 break;
3918 case 0x67: /* address-size override */
3919 if (mode == X86EMUL_MODE_PROT64)
3920 /* switch between 4/8 bytes */
9dac77fa 3921 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3922 else
3923 /* switch between 2/4 bytes */
9dac77fa 3924 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3925 break;
3926 case 0x26: /* ES override */
3927 case 0x2e: /* CS override */
3928 case 0x36: /* SS override */
3929 case 0x3e: /* DS override */
9dac77fa 3930 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3931 break;
3932 case 0x64: /* FS override */
3933 case 0x65: /* GS override */
9dac77fa 3934 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3935 break;
3936 case 0x40 ... 0x4f: /* REX */
3937 if (mode != X86EMUL_MODE_PROT64)
3938 goto done_prefixes;
9dac77fa 3939 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3940 continue;
3941 case 0xf0: /* LOCK */
9dac77fa 3942 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3943 break;
3944 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3945 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3946 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3947 break;
3948 default:
3949 goto done_prefixes;
3950 }
3951
3952 /* Any legacy prefix after a REX prefix nullifies its effect. */
3953
9dac77fa 3954 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3955 }
3956
3957done_prefixes:
3958
3959 /* REX prefix. */
9dac77fa
AK		 3960 if (ctxt->rex_prefix & 8)
3961 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3962
3963 /* Opcode byte(s). */
9dac77fa 3964 opcode = opcode_table[ctxt->b];
d3ad6243 3965 /* Two-byte opcode? */
9dac77fa
AK		 3966 if (ctxt->b == 0x0f) {
3967 ctxt->twobyte = 1;
e85a1085 3968 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3969 opcode = twobyte_table[ctxt->b];
dde7e6d1 3970 }
9dac77fa 3971 ctxt->d = opcode.flags;
dde7e6d1 3972
9f4260e7
TY		 3973 if (ctxt->d & ModRM)
3974 ctxt->modrm = insn_fetch(u8, ctxt);
3975
9dac77fa
AK		 3976 while (ctxt->d & GroupMask) {
3977 switch (ctxt->d & GroupMask) {
46561646 3978 case Group:
9dac77fa 3979 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3980 opcode = opcode.u.group[goffset];
3981 break;
3982 case GroupDual:
9dac77fa
AK		 3983 goffset = (ctxt->modrm >> 3) & 7;
3984 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3985 opcode = opcode.u.gdual->mod3[goffset];
3986 else
3987 opcode = opcode.u.gdual->mod012[goffset];
3988 break;
3989 case RMExt:
9dac77fa 3990 goffset = ctxt->modrm & 7;
01de8b09 3991 opcode = opcode.u.group[goffset];
46561646
AK		 3992 break;
3993 case Prefix:
9dac77fa 3994 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3995 return EMULATION_FAILED;
9dac77fa 3996 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3997 switch (simd_prefix) {
3998 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3999 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4000 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4001 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4002 }
4003 break;
4004 default:
1d2887e2 4005 return EMULATION_FAILED;
0d7cdee8 4006 }
46561646 4007
b1ea50b2 4008 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4009 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4010 }
4011
9dac77fa
AK		 4012 ctxt->execute = opcode.u.execute;
4013 ctxt->check_perm = opcode.check_perm;
4014 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4015
4016 /* Unrecognised? */
9dac77fa 4017 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4018 return EMULATION_FAILED;
dde7e6d1 4019
9dac77fa 4020 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4021 return EMULATION_FAILED;
d867162c 4022
9dac77fa
AK		 4023 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4024 ctxt->op_bytes = 8;
dde7e6d1 4025
9dac77fa 4026 if (ctxt->d & Op3264) {
7f9b4b75 4027 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4028 ctxt->op_bytes = 8;
7f9b4b75 4029 else
9dac77fa 4030 ctxt->op_bytes = 4;
7f9b4b75
AK		 4031 }
4032
9dac77fa
AK		 4033 if (ctxt->d & Sse)
4034 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4035 else if (ctxt->d & Mmx)
4036 ctxt->op_bytes = 8;
1253791d 4037
dde7e6d1 4038 /* ModRM and SIB bytes. */
9dac77fa 4039 if (ctxt->d & ModRM) {
f09ed83e 4040 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4041 if (!ctxt->has_seg_override)
4042 set_seg_override(ctxt, ctxt->modrm_seg);
4043 } else if (ctxt->d & MemAbs)
f09ed83e 4044 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4045 if (rc != X86EMUL_CONTINUE)
4046 goto done;
4047
9dac77fa
AK		 4048 if (!ctxt->has_seg_override)
4049 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4050
f09ed83e 4051 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4052
f09ed83e
AK		 4053 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4054 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4055
dde7e6d1
AK		 4056 /*
4057 * Decode and fetch the source operand: register, memory
4058 * or immediate.
4059 */
0fe59128 4060 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4061 if (rc != X86EMUL_CONTINUE)
4062 goto done;
4063
dde7e6d1
AK		 4064 /*
4065 * Decode and fetch the second source operand: register, memory
4066 * or immediate.
4067 */
4dd6a57d 4068 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4069 if (rc != X86EMUL_CONTINUE)
4070 goto done;
4071
dde7e6d1 4072 /* Decode and fetch the destination operand: register or memory. */
a9945549 4073 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4074
4075done:
f09ed83e
AK		 4076 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4077 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4078
1d2887e2 4079 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4080}
4081
1cb3f3ae
XG		 4082bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4083{
4084 return ctxt->d & PageTable;
4085}
4086
3e2f65d5
GN		 4087static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4088{
3e2f65d5
GN		 4089 /* The second termination condition only applies for REPE
4090 * and REPNE. Test if the repeat string operation prefix is
4091 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4092 * corresponding termination condition according to:
4093 * - if REPE/REPZ and ZF = 0 then done
4094 * - if REPNE/REPNZ and ZF = 1 then done
4095 */
9dac77fa
AK		 4096 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4097 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4098 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4099 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4100 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4101 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4102 return true;
4103
4104 return false;
4105}
4106
cbe2c9d3
AK		 4107static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4108{
4109 bool fault = false;
4110
4111 ctxt->ops->get_fpu(ctxt);
4112 asm volatile("1: fwait \n\t"
4113 "2: \n\t"
4114 ".pushsection .fixup,\"ax\" \n\t"
4115 "3: \n\t"
4116 "movb $1, %[fault] \n\t"
4117 "jmp 2b \n\t"
4118 ".popsection \n\t"
4119 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4120 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4121 ctxt->ops->put_fpu(ctxt);
4122
4123 if (unlikely(fault))
4124 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4125
4126 return X86EMUL_CONTINUE;
4127}
4128
4129static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4130 struct operand *op)
4131{
4132 if (op->type == OP_MM)
4133 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4134}
4135
7b105ca2 4136int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4137{
9aabc88f 4138 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4139 int rc = X86EMUL_CONTINUE;
9dac77fa 4140 int saved_dst_type = ctxt->dst.type;
8b4caf66 4141
9dac77fa 4142 ctxt->mem_read.pos = 0;
310b5d30 4143
9dac77fa 4144 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4145 rc = emulate_ud(ctxt);
1161624f
GN		 4146 goto done;
4147 }
4148
d380a5e4 4149 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4150 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4151 rc = emulate_ud(ctxt);
d380a5e4
GN		 4152 goto done;
4153 }
4154
9dac77fa 4155 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4156 rc = emulate_ud(ctxt);
081bca0e
AK		 4157 goto done;
4158 }
4159
cbe2c9d3
AK		 4160 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4161 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4162 rc = emulate_ud(ctxt);
4163 goto done;
4164 }
4165
cbe2c9d3 4166 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4167 rc = emulate_nm(ctxt);
4168 goto done;
4169 }
4170
cbe2c9d3
AK		 4171 if (ctxt->d & Mmx) {
4172 rc = flush_pending_x87_faults(ctxt);
4173 if (rc != X86EMUL_CONTINUE)
4174 goto done;
4175 /*
4176 * Now that we know the fpu is exception safe, we can fetch
4177 * operands from it.
4178 */
4179 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4180 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4181 if (!(ctxt->d & Mov))
4182 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4183 }
4184
9dac77fa
AK		 4185 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4186 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4187 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4188 if (rc != X86EMUL_CONTINUE)
4189 goto done;
4190 }
4191
e92805ac 4192 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4193 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4194 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4195 goto done;
4196 }
4197
8ea7d6ae 4198 /* Instruction can only be executed in protected mode */
9dac77fa 4199 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4200 rc = emulate_ud(ctxt);
4201 goto done;
4202 }
4203
d09beabd 4204 /* Do instruction specific permission checks */
9dac77fa
AK		 4205 if (ctxt->check_perm) {
4206 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4207 if (rc != X86EMUL_CONTINUE)
4208 goto done;
4209 }
4210
9dac77fa
AK		 4211 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4212 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4213 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4214 if (rc != X86EMUL_CONTINUE)
4215 goto done;
4216 }
4217
9dac77fa 4218 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4219 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4220 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4221 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4222 goto done;
4223 }
b9fa9d6b
AK		 4224 }
4225
9dac77fa
AK		 4226 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4227 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4228 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4229 if (rc != X86EMUL_CONTINUE)
8b4caf66 4230 goto done;
9dac77fa 4231 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4232 }
4233
9dac77fa
AK		 4234 if (ctxt->src2.type == OP_MEM) {
4235 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4236 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4237 if (rc != X86EMUL_CONTINUE)
4238 goto done;
4239 }
4240
9dac77fa 4241 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4242 goto special_insn;
4243
4244
9dac77fa 4245 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4246 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4247 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4248 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4249 if (rc != X86EMUL_CONTINUE)
4250 goto done;
038e51de 4251 }
9dac77fa 4252 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4253
018a98db
AK		 4254special_insn:
4255
9dac77fa
AK		 4256 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4257 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4258 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4259 if (rc != X86EMUL_CONTINUE)
4260 goto done;
4261 }
4262
9dac77fa
AK		 4263 if (ctxt->execute) {
4264 rc = ctxt->execute(ctxt);
ef65c889
AK		 4265 if (rc != X86EMUL_CONTINUE)
4266 goto done;
4267 goto writeback;
4268 }
4269
9dac77fa 4270 if (ctxt->twobyte)
6aa8b732
AK		 4271 goto twobyte_insn;
4272
9dac77fa 4273 switch (ctxt->b) {
33615aa9 4274 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4275 emulate_1op(ctxt, "inc");
33615aa9
AK		 4276 break;
4277 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4278 emulate_1op(ctxt, "dec");
33615aa9 4279 break;
6aa8b732 4280 case 0x63: /* movsxd */
8b4caf66 4281 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4282 goto cannot_emulate;
9dac77fa 4283 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4284 break;
b2833e3c 4285 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4286 if (test_cc(ctxt->b, ctxt->eflags))
4287 jmp_rel(ctxt, ctxt->src.val);
018a98db 4288 break;
7e0b54b1 4289 case 0x8d: /* lea r16/r32, m */
9dac77fa 4290 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4291 break;
3d9e77df 4292 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4293 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4294 break;
e4f973ae
TY		 4295 rc = em_xchg(ctxt);
4296 break;
e8b6fa70 4297 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4298 switch (ctxt->op_bytes) {
4299 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4300 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4301 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4302 }
4303 break;
018a98db 4304 case 0xc0 ... 0xc1:
51187683 4305 rc = em_grp2(ctxt);
018a98db 4306 break;
6e154e56 4307 case 0xcc: /* int3 */
5c5df76b
TY		 4308 rc = emulate_int(ctxt, 3);
4309 break;
6e154e56 4310 case 0xcd: /* int n */
9dac77fa 4311 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4312 break;
4313 case 0xce: /* into */
5c5df76b
TY		 4314 if (ctxt->eflags & EFLG_OF)
4315 rc = emulate_int(ctxt, 4);
6e154e56 4316 break;
018a98db 4317 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4318 rc = em_grp2(ctxt);
018a98db
AK		 4319 break;
4320 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4321 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4322 rc = em_grp2(ctxt);
018a98db 4323 break;
1a52e051 4324 case 0xe9: /* jmp rel */
db5b0762 4325 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4326 jmp_rel(ctxt, ctxt->src.val);
4327 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4328 break;
111de5d6 4329 case 0xf4: /* hlt */
6c3287f7 4330 ctxt->ops->halt(ctxt);
19fdfa0d 4331 break;
111de5d6
AK		 4332 case 0xf5: /* cmc */
4333 /* complement carry flag from eflags reg */
4334 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4335 break;
4336 case 0xf8: /* clc */
4337 ctxt->eflags &= ~EFLG_CF;
111de5d6 4338 break;
8744aa9a
MG		 4339 case 0xf9: /* stc */
4340 ctxt->eflags |= EFLG_CF;
4341 break;
fb4616f4
MG		 4342 case 0xfc: /* cld */
4343 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4344 break;
4345 case 0xfd: /* std */
4346 ctxt->eflags |= EFLG_DF;
fb4616f4 4347 break;
91269b8f
AK		 4348 default:
4349 goto cannot_emulate;
6aa8b732 4350 }
018a98db 4351
7d9ddaed
AK		 4352 if (rc != X86EMUL_CONTINUE)
4353 goto done;
4354
018a98db 4355writeback:
adddcecf 4356 rc = writeback(ctxt);
1b30eaa8 4357 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4358 goto done;
4359
5cd21917
GN		 4360 /*
4361 * restore dst type in case the decoding will be reused
4362 * (happens for string instruction )
4363 */
9dac77fa 4364 ctxt->dst.type = saved_dst_type;
5cd21917 4365
9dac77fa
AK		 4366 if ((ctxt->d & SrcMask) == SrcSI)
4367 string_addr_inc(ctxt, seg_override(ctxt),
4368 VCPU_REGS_RSI, &ctxt->src);
a682e354 4369
9dac77fa 4370 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4371 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4372 &ctxt->dst);
d9271123 4373
9dac77fa
AK		 4374 if (ctxt->rep_prefix && (ctxt->d & String)) {
4375 struct read_cache *r = &ctxt->io_read;
4376 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4377
d2ddd1c4
GN		 4378 if (!string_insn_completed(ctxt)) {
4379 /*
4380 * Re-enter guest when pio read ahead buffer is empty
4381 * or, if it is not used, after each 1024 iteration.
4382 */
9dac77fa 4383 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4384 (r->end == 0 || r->end != r->pos)) {
4385 /*
4386 * Reset read cache. Usually happens before
4387 * decode, but since instruction is restarted
4388 * we have to do it here.
4389 */
9dac77fa 4390 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4391 return EMULATION_RESTART;
4392 }
4393 goto done; /* skip rip writeback */
0fa6ccbd 4394 }
5cd21917 4395 }
d2ddd1c4 4396
9dac77fa 4397 ctxt->eip = ctxt->_eip;
018a98db
AK		 4398
4399done:
da9cb575
AK		 4400 if (rc == X86EMUL_PROPAGATE_FAULT)
4401 ctxt->have_exception = true;
775fde86
JR		 4402 if (rc == X86EMUL_INTERCEPTED)
4403 return EMULATION_INTERCEPTED;
4404
d2ddd1c4 4405 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4406
4407twobyte_insn:
9dac77fa 4408 switch (ctxt->b) {
018a98db 4409 case 0x09: /* wbinvd */
cfb22375 4410 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4411 break;
4412 case 0x08: /* invd */
018a98db
AK		 4413 case 0x0d: /* GrpP (prefetch) */
4414 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4415 break;
4416 case 0x20: /* mov cr, reg */
9dac77fa 4417 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4418 break;
6aa8b732 4419 case 0x21: /* mov from dr to reg */
9dac77fa 4420 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4421 break;
6aa8b732 4422 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4423 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4424 if (!test_cc(ctxt->b, ctxt->eflags))
4425 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4426 break;
b2833e3c 4427 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4428 if (test_cc(ctxt->b, ctxt->eflags))
4429 jmp_rel(ctxt, ctxt->src.val);
018a98db 4430 break;
ee45b58e 4431 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4432 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4433 break;
9bf8ea42
GT		 4434 case 0xa4: /* shld imm8, r, r/m */
4435 case 0xa5: /* shld cl, r, r/m */
761441b9 4436 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4437 break;
9bf8ea42
GT		 4438 case 0xac: /* shrd imm8, r, r/m */
4439 case 0xad: /* shrd cl, r, r/m */
761441b9 4440 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4441 break;
2a7c5b8b
GC		 4442 case 0xae: /* clflush */
4443 break;
6aa8b732 4444 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4445 ctxt->dst.bytes = ctxt->op_bytes;
4446 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4447 : (u16) ctxt->src.val;
6aa8b732 4448 break;
6aa8b732 4449 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4450 ctxt->dst.bytes = ctxt->op_bytes;
4451 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4452 (s16) ctxt->src.val;
6aa8b732 4453 break;
92f738a5 4454 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4455 emulate_2op_SrcV(ctxt, "add");
92f738a5 4456 /* Write back the register source. */
9dac77fa
AK		 4457 ctxt->src.val = ctxt->dst.orig_val;
4458 write_register_operand(&ctxt->src);
92f738a5 4459 break;
a012e65a 4460 case 0xc3: /* movnti */
9dac77fa
AK		 4461 ctxt->dst.bytes = ctxt->op_bytes;
4462 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4463 (u64) ctxt->src.val;
a012e65a 4464 break;
91269b8f
AK		 4465 default:
4466 goto cannot_emulate;
6aa8b732 4467 }
7d9ddaed
AK		 4468
4469 if (rc != X86EMUL_CONTINUE)
4470 goto done;
4471
6aa8b732
AK		 4472 goto writeback;
4473
4474cannot_emulate:
a0c0ab2f 4475 return EMULATION_FAILED;
6aa8b732 4476}
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