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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
f47cfa31
AK		 436static void assign_masked(ulong *dest, ulong src, ulong mask)
437{
438 *dest = (*dest & ~mask) | (src & mask);
439}
440
9dac77fa 441static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 442{
9dac77fa 443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 444}
445
f47cfa31
AK		 446static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447{
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455}
456
6aa8b732 457/* Access/update address held in a register, based on addressing mode. */
e4706772 458static inline unsigned long
9dac77fa 459address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 460{
9dac77fa 461 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 462 return reg;
463 else
9dac77fa 464 return reg & ad_mask(ctxt);
e4706772
HH		 465}
466
467static inline unsigned long
9dac77fa 468register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 469{
9dac77fa 470 return address_mask(ctxt, reg);
e4706772
HH		 471}
472
7a957275 473static inline void
9dac77fa 474register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 475{
9dac77fa 476 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 477 *reg += inc;
478 else
9dac77fa 479 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 480}
6aa8b732 481
9dac77fa 482static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 483{
9dac77fa 484 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 485}
098c937b 486
56697687
AK		 487static u32 desc_limit_scaled(struct desc_struct *desc)
488{
489 u32 limit = get_desc_limit(desc);
490
491 return desc->g ? (limit << 12) | 0xfff : limit;
492}
493
9dac77fa 494static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 495{
9dac77fa
AK		 496 ctxt->has_seg_override = true;
497 ctxt->seg_override = seg;
7a5b56df
AK		 498}
499
7b105ca2 500static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 501{
502 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
503 return 0;
504
7b105ca2 505 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 506}
507
9dac77fa 508static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 509{
9dac77fa 510 if (!ctxt->has_seg_override)
7a5b56df
AK		 511 return 0;
512
9dac77fa 513 return ctxt->seg_override;
7a5b56df
AK		 514}
515
35d3d4a1
AK		 516static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
517 u32 error, bool valid)
54b8486f 518{
da9cb575
AK		 519 ctxt->exception.vector = vec;
520 ctxt->exception.error_code = error;
521 ctxt->exception.error_code_valid = valid;
35d3d4a1 522 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 523}
524
3b88e41a
JR		 525static int emulate_db(struct x86_emulate_ctxt *ctxt)
526{
527 return emulate_exception(ctxt, DB_VECTOR, 0, false);
528}
529
35d3d4a1 530static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 531{
35d3d4a1 532 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 533}
534
618ff15d
AK		 535static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
536{
537 return emulate_exception(ctxt, SS_VECTOR, err, true);
538}
539
35d3d4a1 540static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 543}
544
35d3d4a1 545static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 546{
35d3d4a1 547 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 548}
549
34d1f490
AK		 550static int emulate_de(struct x86_emulate_ctxt *ctxt)
551{
35d3d4a1 552 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 553}
554
1253791d
AK		 555static int emulate_nm(struct x86_emulate_ctxt *ctxt)
556{
557 return emulate_exception(ctxt, NM_VECTOR, 0, false);
558}
559
1aa36616
AK		 560static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
561{
562 u16 selector;
563 struct desc_struct desc;
564
565 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
566 return selector;
567}
568
569static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
570 unsigned seg)
571{
572 u16 dummy;
573 u32 base3;
574 struct desc_struct desc;
575
576 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
577 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
578}
579
1c11b376
AK		 580/*
581 * x86 defines three classes of vector instructions: explicitly
582 * aligned, explicitly unaligned, and the rest, which change behaviour
583 * depending on whether they're AVX encoded or not.
584 *
585 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
586 * subject to the same check.
587 */
588static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
589{
590 if (likely(size < 16))
591 return false;
592
593 if (ctxt->d & Aligned)
594 return true;
595 else if (ctxt->d & Unaligned)
596 return false;
597 else if (ctxt->d & Avx)
598 return false;
599 else
600 return true;
601}
602
3d9b938e 603static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 604 struct segmented_address addr,
3d9b938e 605 unsigned size, bool write, bool fetch,
52fd8b44
AK		 606 ulong *linear)
607{
618ff15d
AK		 608 struct desc_struct desc;
609 bool usable;
52fd8b44 610 ulong la;
618ff15d 611 u32 lim;
1aa36616 612 u16 sel;
618ff15d 613 unsigned cpl, rpl;
52fd8b44 614
7b105ca2 615 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 616 switch (ctxt->mode) {
617 case X86EMUL_MODE_REAL:
618 break;
619 case X86EMUL_MODE_PROT64:
620 if (((signed long)la << 16) >> 16 != la)
621 return emulate_gp(ctxt, 0);
622 break;
623 default:
1aa36616
AK		 624 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
625 addr.seg);
618ff15d
AK		 626 if (!usable)
627 goto bad;
628 /* code segment or read-only data segment */
629 if (((desc.type & 8) || !(desc.type & 2)) && write)
630 goto bad;
631 /* unreadable code segment */
3d9b938e 632 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 633 goto bad;
634 lim = desc_limit_scaled(&desc);
635 if ((desc.type & 8) || !(desc.type & 4)) {
636 /* expand-up segment */
637 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
638 goto bad;
639 } else {
640 /* exapand-down segment */
641 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
642 goto bad;
643 lim = desc.d ? 0xffffffff : 0xffff;
644 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
645 goto bad;
646 }
717746e3 647 cpl = ctxt->ops->cpl(ctxt);
1aa36616 648 rpl = sel & 3;
618ff15d
AK		 649 cpl = max(cpl, rpl);
650 if (!(desc.type & 8)) {
651 /* data segment */
652 if (cpl > desc.dpl)
653 goto bad;
654 } else if ((desc.type & 8) && !(desc.type & 4)) {
655 /* nonconforming code segment */
656 if (cpl != desc.dpl)
657 goto bad;
658 } else if ((desc.type & 8) && (desc.type & 4)) {
659 /* conforming code segment */
660 if (cpl < desc.dpl)
661 goto bad;
662 }
663 break;
664 }
9dac77fa 665 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 666 la &= (u32)-1;
1c11b376
AK		 667 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
668 return emulate_gp(ctxt, 0);
52fd8b44
AK		 669 *linear = la;
670 return X86EMUL_CONTINUE;
618ff15d
AK		 671bad:
672 if (addr.seg == VCPU_SREG_SS)
673 return emulate_ss(ctxt, addr.seg);
674 else
675 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 676}
677
3d9b938e
NE		 678static int linearize(struct x86_emulate_ctxt *ctxt,
679 struct segmented_address addr,
680 unsigned size, bool write,
681 ulong *linear)
682{
683 return __linearize(ctxt, addr, size, write, false, linear);
684}
685
686
3ca3ac4d
AK		 687static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
688 struct segmented_address addr,
689 void *data,
690 unsigned size)
691{
9fa088f4
AK		 692 int rc;
693 ulong linear;
694
83b8795a 695 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 696 if (rc != X86EMUL_CONTINUE)
697 return rc;
0f65dd70 698 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 699}
700
807941b1
TY		 701/*
702 * Fetch the next byte of the instruction being emulated which is pointed to
703 * by ctxt->_eip, then increment ctxt->_eip.
704 *
705 * Also prefetch the remaining bytes of the instruction without crossing page
706 * boundary if they are not in fetch_cache yet.
707 */
708static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 709{
9dac77fa 710 struct fetch_cache *fc = &ctxt->fetch;
62266869 711 int rc;
2fb53ad8 712 int size, cur_size;
62266869 713
807941b1 714 if (ctxt->_eip == fc->end) {
3d9b938e 715 unsigned long linear;
807941b1
TY		 716 struct segmented_address addr = { .seg = VCPU_SREG_CS,
717 .ea = ctxt->_eip };
2fb53ad8 718 cur_size = fc->end - fc->start;
807941b1
TY		 719 size = min(15UL - cur_size,
720 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 721 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 722 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 723 return rc;
ef5d75cc
TY		 724 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
725 size, &ctxt->exception);
7d88bb48 726 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 727 return rc;
2fb53ad8 728 fc->end += size;
62266869 729 }
807941b1
TY		 730 *dest = fc->data[ctxt->_eip - fc->start];
731 ctxt->_eip++;
3e2815e9 732 return X86EMUL_CONTINUE;
62266869
AK		 733}
734
735static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 736 void *dest, unsigned size)
62266869 737{
3e2815e9 738 int rc;
62266869 739
eb3c79e6 740 /* x86 instructions are limited to 15 bytes. */
7d88bb48 741 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 742 return X86EMUL_UNHANDLEABLE;
62266869 743 while (size--) {
807941b1 744 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 745 if (rc != X86EMUL_CONTINUE)
62266869
AK		 746 return rc;
747 }
3e2815e9 748 return X86EMUL_CONTINUE;
62266869
AK		 749}
750
67cbc90d 751/* Fetch next part of the instruction being emulated. */
e85a1085 752#define insn_fetch(_type, _ctxt) \
67cbc90d 753({ unsigned long _x; \
e85a1085 754 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 755 if (rc != X86EMUL_CONTINUE) \
756 goto done; \
67cbc90d
TY		 757 (_type)_x; \
758})
759
807941b1
TY		 760#define insn_fetch_arr(_arr, _size, _ctxt) \
761({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 762 if (rc != X86EMUL_CONTINUE) \
763 goto done; \
67cbc90d
TY		 764})
765
1e3c5cb0
RR		 766/*
767 * Given the 'reg' portion of a ModRM byte, and a register block, return a
768 * pointer into the block that addresses the relevant register.
769 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
770 */
771static void *decode_register(u8 modrm_reg, unsigned long *regs,
772 int highbyte_regs)
6aa8b732
AK		 773{
774 void *p;
775
776 p = &regs[modrm_reg];
777 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
778 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
779 return p;
780}
781
782static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 783 struct segmented_address addr,
6aa8b732
AK		 784 u16 *size, unsigned long *address, int op_bytes)
785{
786 int rc;
787
788 if (op_bytes == 2)
789 op_bytes = 3;
790 *address = 0;
3ca3ac4d 791 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 792 if (rc != X86EMUL_CONTINUE)
6aa8b732 793 return rc;
30b31ab6 794 addr.ea += 2;
3ca3ac4d 795 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 796 return rc;
797}
798
bbe9abbd
NK		 799static int test_cc(unsigned int condition, unsigned int flags)
800{
801 int rc = 0;
802
803 switch ((condition & 15) >> 1) {
804 case 0: /* o */
805 rc |= (flags & EFLG_OF);
806 break;
807 case 1: /* b/c/nae */
808 rc |= (flags & EFLG_CF);
809 break;
810 case 2: /* z/e */
811 rc |= (flags & EFLG_ZF);
812 break;
813 case 3: /* be/na */
814 rc |= (flags & (EFLG_CF|EFLG_ZF));
815 break;
816 case 4: /* s */
817 rc |= (flags & EFLG_SF);
818 break;
819 case 5: /* p/pe */
820 rc |= (flags & EFLG_PF);
821 break;
822 case 7: /* le/ng */
823 rc |= (flags & EFLG_ZF);
824 /* fall through */
825 case 6: /* l/nge */
826 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
827 break;
828 }
829
830 /* Odd condition identifiers (lsb == 1) have inverted sense. */
831 return (!!rc ^ (condition & 1));
832}
833
91ff3cb4
AK		 834static void fetch_register_operand(struct operand *op)
835{
836 switch (op->bytes) {
837 case 1:
838 op->val = *(u8 *)op->addr.reg;
839 break;
840 case 2:
841 op->val = *(u16 *)op->addr.reg;
842 break;
843 case 4:
844 op->val = *(u32 *)op->addr.reg;
845 break;
846 case 8:
847 op->val = *(u64 *)op->addr.reg;
848 break;
849 }
850}
851
1253791d
AK		 852static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
853{
854 ctxt->ops->get_fpu(ctxt);
855 switch (reg) {
856 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
857 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
858 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
859 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
860 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
861 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
862 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
863 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
864#ifdef CONFIG_X86_64
865 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
866 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
867 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
868 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
869 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
870 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
871 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
872 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
873#endif
874 default: BUG();
875 }
876 ctxt->ops->put_fpu(ctxt);
877}
878
879static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
880 int reg)
881{
882 ctxt->ops->get_fpu(ctxt);
883 switch (reg) {
884 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
885 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
886 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
887 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
888 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
889 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
890 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
891 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
892#ifdef CONFIG_X86_64
893 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
894 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
895 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
896 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
897 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
898 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
899 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
900 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
901#endif
902 default: BUG();
903 }
904 ctxt->ops->put_fpu(ctxt);
905}
906
cbe2c9d3
AK		 907static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
908{
909 ctxt->ops->get_fpu(ctxt);
910 switch (reg) {
911 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
912 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
913 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
914 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
915 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
916 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
917 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
918 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
919 default: BUG();
920 }
921 ctxt->ops->put_fpu(ctxt);
922}
923
924static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
925{
926 ctxt->ops->get_fpu(ctxt);
927 switch (reg) {
928 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
929 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
930 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
931 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
932 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
933 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
934 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
935 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
936 default: BUG();
937 }
938 ctxt->ops->put_fpu(ctxt);
939}
940
1253791d 941static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 942 struct operand *op)
3c118e24 943{
9dac77fa
AK		 944 unsigned reg = ctxt->modrm_reg;
945 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 946
9dac77fa
AK		 947 if (!(ctxt->d & ModRM))
948 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 949
9dac77fa 950 if (ctxt->d & Sse) {
1253791d
AK		 951 op->type = OP_XMM;
952 op->bytes = 16;
953 op->addr.xmm = reg;
954 read_sse_reg(ctxt, &op->vec_val, reg);
955 return;
956 }
cbe2c9d3
AK		 957 if (ctxt->d & Mmx) {
958 reg &= 7;
959 op->type = OP_MM;
960 op->bytes = 8;
961 op->addr.mm = reg;
962 return;
963 }
1253791d 964
3c118e24 965 op->type = OP_REG;
2adb5ad9 966 if (ctxt->d & ByteOp) {
9dac77fa 967 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 968 op->bytes = 1;
969 } else {
9dac77fa
AK		 970 op->addr.reg = decode_register(reg, ctxt->regs, 0);
971 op->bytes = ctxt->op_bytes;
3c118e24 972 }
91ff3cb4 973 fetch_register_operand(op);
3c118e24
AK		 974 op->orig_val = op->val;
975}
976
a6e3407b
AK		 977static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
978{
979 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
980 ctxt->modrm_seg = VCPU_SREG_SS;
981}
982
1c73ef66 983static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 984 struct operand *op)
1c73ef66 985{
1c73ef66 986 u8 sib;
f5b4edcd 987 int index_reg = 0, base_reg = 0, scale;
3e2815e9 988 int rc = X86EMUL_CONTINUE;
2dbd0dd7 989 ulong modrm_ea = 0;
1c73ef66 990
9dac77fa
AK		 991 if (ctxt->rex_prefix) {
992 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
993 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
994 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 995 }
996
9dac77fa
AK		 997 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
998 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
999 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1000 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1001
9dac77fa 1002 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1003 op->type = OP_REG;
9dac77fa
AK		 1004 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1005 op->addr.reg = decode_register(ctxt->modrm_rm,
1006 ctxt->regs, ctxt->d & ByteOp);
1007 if (ctxt->d & Sse) {
1253791d
AK		 1008 op->type = OP_XMM;
1009 op->bytes = 16;
9dac77fa
AK		 1010 op->addr.xmm = ctxt->modrm_rm;
1011 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1012 return rc;
1013 }
cbe2c9d3
AK		 1014 if (ctxt->d & Mmx) {
1015 op->type = OP_MM;
1016 op->bytes = 8;
1017 op->addr.xmm = ctxt->modrm_rm & 7;
1018 return rc;
1019 }
2dbd0dd7 1020 fetch_register_operand(op);
1c73ef66
AK		 1021 return rc;
1022 }
1023
2dbd0dd7
AK		 1024 op->type = OP_MEM;
1025
9dac77fa
AK		 1026 if (ctxt->ad_bytes == 2) {
1027 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1028 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1029 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1030 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1031
1032 /* 16-bit ModR/M decode. */
9dac77fa 1033 switch (ctxt->modrm_mod) {
1c73ef66 1034 case 0:
9dac77fa 1035 if (ctxt->modrm_rm == 6)
e85a1085 1036 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1037 break;
1038 case 1:
e85a1085 1039 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1040 break;
1041 case 2:
e85a1085 1042 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1043 break;
1044 }
9dac77fa 1045 switch (ctxt->modrm_rm) {
1c73ef66 1046 case 0:
2dbd0dd7 1047 modrm_ea += bx + si;
1c73ef66
AK		 1048 break;
1049 case 1:
2dbd0dd7 1050 modrm_ea += bx + di;
1c73ef66
AK		 1051 break;
1052 case 2:
2dbd0dd7 1053 modrm_ea += bp + si;
1c73ef66
AK		 1054 break;
1055 case 3:
2dbd0dd7 1056 modrm_ea += bp + di;
1c73ef66
AK		 1057 break;
1058 case 4:
2dbd0dd7 1059 modrm_ea += si;
1c73ef66
AK		 1060 break;
1061 case 5:
2dbd0dd7 1062 modrm_ea += di;
1c73ef66
AK		 1063 break;
1064 case 6:
9dac77fa 1065 if (ctxt->modrm_mod != 0)
2dbd0dd7 1066 modrm_ea += bp;
1c73ef66
AK		 1067 break;
1068 case 7:
2dbd0dd7 1069 modrm_ea += bx;
1c73ef66
AK		 1070 break;
1071 }
9dac77fa
AK		 1072 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1073 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1074 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1075 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1076 } else {
1077 /* 32/64-bit ModR/M decode. */
9dac77fa 1078 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1079 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1080 index_reg |= (sib >> 3) & 7;
1081 base_reg |= sib & 7;
1082 scale = sib >> 6;
1083
9dac77fa 1084 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1085 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1086 else {
9dac77fa 1087 modrm_ea += ctxt->regs[base_reg];
a6e3407b
AK		 1088 adjust_modrm_seg(ctxt, base_reg);
1089 }
dc71d0f1 1090 if (index_reg != 4)
9dac77fa
AK		 1091 modrm_ea += ctxt->regs[index_reg] << scale;
1092 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1093 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1094 ctxt->rip_relative = 1;
a6e3407b
AK		 1095 } else {
1096 base_reg = ctxt->modrm_rm;
1097 modrm_ea += ctxt->regs[base_reg];
1098 adjust_modrm_seg(ctxt, base_reg);
1099 }
9dac77fa 1100 switch (ctxt->modrm_mod) {
1c73ef66 1101 case 0:
9dac77fa 1102 if (ctxt->modrm_rm == 5)
e85a1085 1103 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1104 break;
1105 case 1:
e85a1085 1106 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1107 break;
1108 case 2:
e85a1085 1109 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1110 break;
1111 }
1112 }
90de84f5 1113 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1114done:
1115 return rc;
1116}
1117
1118static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1119 struct operand *op)
1c73ef66 1120{
3e2815e9 1121 int rc = X86EMUL_CONTINUE;
1c73ef66 1122
2dbd0dd7 1123 op->type = OP_MEM;
9dac77fa 1124 switch (ctxt->ad_bytes) {
1c73ef66 1125 case 2:
e85a1085 1126 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1127 break;
1128 case 4:
e85a1085 1129 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1130 break;
1131 case 8:
e85a1085 1132 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1133 break;
1134 }
1135done:
1136 return rc;
1137}
1138
9dac77fa 1139static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1140{
7129eeca 1141 long sv = 0, mask;
35c843c4 1142
9dac77fa
AK		 1143 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1144 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1145
9dac77fa
AK		 1146 if (ctxt->src.bytes == 2)
1147 sv = (s16)ctxt->src.val & (s16)mask;
1148 else if (ctxt->src.bytes == 4)
1149 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1150
9dac77fa 1151 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1152 }
ba7ff2b7
WY		 1153
1154 /* only subword offset */
9dac77fa 1155 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1156}
1157
dde7e6d1 1158static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1159 unsigned long addr, void *dest, unsigned size)
6aa8b732 1160{
dde7e6d1 1161 int rc;
9dac77fa 1162 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1163
dde7e6d1
AK		 1164 while (size) {
1165 int n = min(size, 8u);
1166 size -= n;
1167 if (mc->pos < mc->end)
1168 goto read_cached;
5cd21917 1169
7b105ca2
TY		 1170 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1171 &ctxt->exception);
dde7e6d1
AK		 1172 if (rc != X86EMUL_CONTINUE)
1173 return rc;
1174 mc->end += n;
6aa8b732 1175
dde7e6d1
AK		 1176 read_cached:
1177 memcpy(dest, mc->data + mc->pos, n);
1178 mc->pos += n;
1179 dest += n;
1180 addr += n;
6aa8b732 1181 }
dde7e6d1
AK		 1182 return X86EMUL_CONTINUE;
1183}
6aa8b732 1184
3ca3ac4d
AK		 1185static int segmented_read(struct x86_emulate_ctxt *ctxt,
1186 struct segmented_address addr,
1187 void *data,
1188 unsigned size)
1189{
9fa088f4
AK		 1190 int rc;
1191 ulong linear;
1192
83b8795a 1193 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1194 if (rc != X86EMUL_CONTINUE)
1195 return rc;
7b105ca2 1196 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1197}
1198
1199static int segmented_write(struct x86_emulate_ctxt *ctxt,
1200 struct segmented_address addr,
1201 const void *data,
1202 unsigned size)
1203{
9fa088f4
AK		 1204 int rc;
1205 ulong linear;
1206
83b8795a 1207 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1208 if (rc != X86EMUL_CONTINUE)
1209 return rc;
0f65dd70
AK		 1210 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1211 &ctxt->exception);
3ca3ac4d
AK		 1212}
1213
1214static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1215 struct segmented_address addr,
1216 const void *orig_data, const void *data,
1217 unsigned size)
1218{
9fa088f4
AK		 1219 int rc;
1220 ulong linear;
1221
83b8795a 1222 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1223 if (rc != X86EMUL_CONTINUE)
1224 return rc;
0f65dd70
AK		 1225 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1226 size, &ctxt->exception);
3ca3ac4d
AK		 1227}
1228
dde7e6d1 1229static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1230 unsigned int size, unsigned short port,
1231 void *dest)
1232{
9dac77fa 1233 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1234
dde7e6d1 1235 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1236 unsigned int in_page, n;
9dac77fa
AK		 1237 unsigned int count = ctxt->rep_prefix ?
1238 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1239 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1240 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1241 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1242 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1243 count);
1244 if (n == 0)
1245 n = 1;
1246 rc->pos = rc->end = 0;
7b105ca2 1247 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1248 return 0;
1249 rc->end = n * size;
6aa8b732
AK		 1250 }
1251
dde7e6d1
AK		 1252 memcpy(dest, rc->data + rc->pos, size);
1253 rc->pos += size;
1254 return 1;
1255}
6aa8b732 1256
7f3d35fd
KW		 1257static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1258 u16 index, struct desc_struct *desc)
1259{
1260 struct desc_ptr dt;
1261 ulong addr;
1262
1263 ctxt->ops->get_idt(ctxt, &dt);
1264
1265 if (dt.size < index * 8 + 7)
1266 return emulate_gp(ctxt, index << 3 | 0x2);
1267
1268 addr = dt.address + index * 8;
1269 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1270 &ctxt->exception);
1271}
1272
dde7e6d1 1273static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1274 u16 selector, struct desc_ptr *dt)
1275{
7b105ca2
TY		 1276 struct x86_emulate_ops *ops = ctxt->ops;
1277
dde7e6d1
AK		 1278 if (selector & 1 << 2) {
1279 struct desc_struct desc;
1aa36616
AK		 1280 u16 sel;
1281
dde7e6d1 1282 memset (dt, 0, sizeof *dt);
1aa36616 1283 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1284 return;
e09d082c 1285
dde7e6d1
AK		 1286 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1287 dt->address = get_desc_base(&desc);
1288 } else
4bff1e86 1289 ops->get_gdt(ctxt, dt);
dde7e6d1 1290}
120df890 1291
dde7e6d1
AK		 1292/* allowed just for 8 bytes segments */
1293static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1294 u16 selector, struct desc_struct *desc)
1295{
1296 struct desc_ptr dt;
1297 u16 index = selector >> 3;
dde7e6d1 1298 ulong addr;
120df890 1299
7b105ca2 1300 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1301
35d3d4a1
AK		 1302 if (dt.size < index * 8 + 7)
1303 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1304
7b105ca2
TY		 1305 addr = dt.address + index * 8;
1306 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1307 &ctxt->exception);
dde7e6d1 1308}
ef65c889 1309
dde7e6d1
AK		 1310/* allowed just for 8 bytes segments */
1311static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1312 u16 selector, struct desc_struct *desc)
1313{
1314 struct desc_ptr dt;
1315 u16 index = selector >> 3;
dde7e6d1 1316 ulong addr;
6aa8b732 1317
7b105ca2 1318 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1319
35d3d4a1
AK		 1320 if (dt.size < index * 8 + 7)
1321 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1322
dde7e6d1 1323 addr = dt.address + index * 8;
7b105ca2
TY		 1324 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1325 &ctxt->exception);
dde7e6d1 1326}
c7e75a3d 1327
5601d05b 1328/* Does not support long mode */
dde7e6d1 1329static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1330 u16 selector, int seg)
1331{
1332 struct desc_struct seg_desc;
1333 u8 dpl, rpl, cpl;
1334 unsigned err_vec = GP_VECTOR;
1335 u32 err_code = 0;
1336 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1337 int ret;
69f55cb1 1338
dde7e6d1 1339 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1340
dde7e6d1
AK		 1341 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1342 || ctxt->mode == X86EMUL_MODE_REAL) {
1343 /* set real mode segment descriptor */
1344 set_desc_base(&seg_desc, selector << 4);
1345 set_desc_limit(&seg_desc, 0xffff);
1346 seg_desc.type = 3;
1347 seg_desc.p = 1;
1348 seg_desc.s = 1;
66b0ab8f
KW		 1349 if (ctxt->mode == X86EMUL_MODE_VM86)
1350 seg_desc.dpl = 3;
dde7e6d1
AK		 1351 goto load;
1352 }
1353
79d5b4c3
AK		 1354 rpl = selector & 3;
1355 cpl = ctxt->ops->cpl(ctxt);
1356
1357 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1358 if ((seg == VCPU_SREG_CS
1359 || (seg == VCPU_SREG_SS
1360 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1361 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1362 && null_selector)
1363 goto exception;
1364
1365 /* TR should be in GDT only */
1366 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1367 goto exception;
1368
1369 if (null_selector) /* for NULL selector skip all following checks */
1370 goto load;
1371
7b105ca2 1372 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1373 if (ret != X86EMUL_CONTINUE)
1374 return ret;
1375
1376 err_code = selector & 0xfffc;
1377 err_vec = GP_VECTOR;
1378
1379 /* can't load system descriptor into segment selecor */
1380 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1381 goto exception;
1382
1383 if (!seg_desc.p) {
1384 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1385 goto exception;
1386 }
1387
dde7e6d1 1388 dpl = seg_desc.dpl;
dde7e6d1
AK		 1389
1390 switch (seg) {
1391 case VCPU_SREG_SS:
1392 /*
1393 * segment is not a writable data segment or segment
1394 * selector's RPL != CPL or segment selector's RPL != CPL
1395 */
1396 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1397 goto exception;
6aa8b732 1398 break;
dde7e6d1
AK		 1399 case VCPU_SREG_CS:
1400 if (!(seg_desc.type & 8))
1401 goto exception;
1402
1403 if (seg_desc.type & 4) {
1404 /* conforming */
1405 if (dpl > cpl)
1406 goto exception;
1407 } else {
1408 /* nonconforming */
1409 if (rpl > cpl || dpl != cpl)
1410 goto exception;
1411 }
1412 /* CS(RPL) <- CPL */
1413 selector = (selector & 0xfffc) | cpl;
6aa8b732 1414 break;
dde7e6d1
AK		 1415 case VCPU_SREG_TR:
1416 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1417 goto exception;
1418 break;
1419 case VCPU_SREG_LDTR:
1420 if (seg_desc.s || seg_desc.type != 2)
1421 goto exception;
1422 break;
1423 default: /* DS, ES, FS, or GS */
4e62417b 1424 /*
dde7e6d1
AK		 1425 * segment is not a data or readable code segment or
1426 * ((segment is a data or nonconforming code segment)
1427 * and (both RPL and CPL > DPL))
4e62417b 1428 */
dde7e6d1
AK		 1429 if ((seg_desc.type & 0xa) == 0x8 ||
1430 (((seg_desc.type & 0xc) != 0xc) &&
1431 (rpl > dpl && cpl > dpl)))
1432 goto exception;
6aa8b732 1433 break;
dde7e6d1
AK		 1434 }
1435
1436 if (seg_desc.s) {
1437 /* mark segment as accessed */
1438 seg_desc.type |= 1;
7b105ca2 1439 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1440 if (ret != X86EMUL_CONTINUE)
1441 return ret;
1442 }
1443load:
7b105ca2 1444 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1445 return X86EMUL_CONTINUE;
1446exception:
1447 emulate_exception(ctxt, err_vec, err_code, true);
1448 return X86EMUL_PROPAGATE_FAULT;
1449}
1450
31be40b3
WY		 1451static void write_register_operand(struct operand *op)
1452{
1453 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1454 switch (op->bytes) {
1455 case 1:
1456 *(u8 *)op->addr.reg = (u8)op->val;
1457 break;
1458 case 2:
1459 *(u16 *)op->addr.reg = (u16)op->val;
1460 break;
1461 case 4:
1462 *op->addr.reg = (u32)op->val;
1463 break; /* 64b: zero-extend */
1464 case 8:
1465 *op->addr.reg = op->val;
1466 break;
1467 }
1468}
1469
adddcecf 1470static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1471{
1472 int rc;
dde7e6d1 1473
9dac77fa 1474 switch (ctxt->dst.type) {
dde7e6d1 1475 case OP_REG:
9dac77fa 1476 write_register_operand(&ctxt->dst);
6aa8b732 1477 break;
dde7e6d1 1478 case OP_MEM:
9dac77fa 1479 if (ctxt->lock_prefix)
3ca3ac4d 1480 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1481 ctxt->dst.addr.mem,
1482 &ctxt->dst.orig_val,
1483 &ctxt->dst.val,
1484 ctxt->dst.bytes);
341de7e3 1485 else
3ca3ac4d 1486 rc = segmented_write(ctxt,
9dac77fa
AK		 1487 ctxt->dst.addr.mem,
1488 &ctxt->dst.val,
1489 ctxt->dst.bytes);
dde7e6d1
AK		 1490 if (rc != X86EMUL_CONTINUE)
1491 return rc;
a682e354 1492 break;
1253791d 1493 case OP_XMM:
9dac77fa 1494 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1495 break;
cbe2c9d3
AK		 1496 case OP_MM:
1497 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1498 break;
dde7e6d1
AK		 1499 case OP_NONE:
1500 /* no writeback */
414e6277 1501 break;
dde7e6d1 1502 default:
414e6277 1503 break;
6aa8b732 1504 }
dde7e6d1
AK		 1505 return X86EMUL_CONTINUE;
1506}
6aa8b732 1507
4487b3b4 1508static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1509{
4179bb02 1510 struct segmented_address addr;
0dc8d10f 1511
9dac77fa
AK		 1512 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1513 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1514 addr.seg = VCPU_SREG_SS;
1515
1516 /* Disable writeback. */
9dac77fa
AK		 1517 ctxt->dst.type = OP_NONE;
1518 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1519}
69f55cb1 1520
dde7e6d1 1521static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1522 void *dest, int len)
1523{
dde7e6d1 1524 int rc;
90de84f5 1525 struct segmented_address addr;
8b4caf66 1526
9dac77fa 1527 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1528 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1529 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1530 if (rc != X86EMUL_CONTINUE)
1531 return rc;
1532
9dac77fa 1533 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1534 return rc;
8b4caf66
LV		 1535}
1536
c54fe504
TY		 1537static int em_pop(struct x86_emulate_ctxt *ctxt)
1538{
9dac77fa 1539 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1540}
1541
dde7e6d1 1542static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1543 void *dest, int len)
9de41573
GN		 1544{
1545 int rc;
dde7e6d1
AK		 1546 unsigned long val, change_mask;
1547 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1548 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1549
3b9be3bf 1550 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1551 if (rc != X86EMUL_CONTINUE)
1552 return rc;
9de41573 1553
dde7e6d1
AK		 1554 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1555 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1556
dde7e6d1
AK		 1557 switch(ctxt->mode) {
1558 case X86EMUL_MODE_PROT64:
1559 case X86EMUL_MODE_PROT32:
1560 case X86EMUL_MODE_PROT16:
1561 if (cpl == 0)
1562 change_mask |= EFLG_IOPL;
1563 if (cpl <= iopl)
1564 change_mask |= EFLG_IF;
1565 break;
1566 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1567 if (iopl < 3)
1568 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1569 change_mask |= EFLG_IF;
1570 break;
1571 default: /* real mode */
1572 change_mask |= (EFLG_IOPL | EFLG_IF);
1573 break;
9de41573 1574 }
dde7e6d1
AK		 1575
1576 *(unsigned long *)dest =
1577 (ctxt->eflags & ~change_mask) | (val & change_mask);
1578
1579 return rc;
9de41573
GN		 1580}
1581
62aaa2f0
TY		 1582static int em_popf(struct x86_emulate_ctxt *ctxt)
1583{
9dac77fa
AK		 1584 ctxt->dst.type = OP_REG;
1585 ctxt->dst.addr.reg = &ctxt->eflags;
1586 ctxt->dst.bytes = ctxt->op_bytes;
1587 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1588}
1589
f47cfa31
AK		 1590static int em_leave(struct x86_emulate_ctxt *ctxt)
1591{
1592 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1593 stack_mask(ctxt));
1594 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1595}
1596
1cd196ea 1597static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1598{
1cd196ea
AK		 1599 int seg = ctxt->src2.val;
1600
9dac77fa 1601 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1602
4487b3b4 1603 return em_push(ctxt);
7b262e90
GN		 1604}
1605
1cd196ea 1606static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1607{
1cd196ea 1608 int seg = ctxt->src2.val;
dde7e6d1
AK		 1609 unsigned long selector;
1610 int rc;
38ba30ba 1611
9dac77fa 1612 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1613 if (rc != X86EMUL_CONTINUE)
1614 return rc;
1615
7b105ca2 1616 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1617 return rc;
38ba30ba
GN		 1618}
1619
b96a7fad 1620static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1621{
9dac77fa 1622 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1623 int rc = X86EMUL_CONTINUE;
1624 int reg = VCPU_REGS_RAX;
38ba30ba 1625
dde7e6d1
AK		 1626 while (reg <= VCPU_REGS_RDI) {
1627 (reg == VCPU_REGS_RSP) ?
9dac77fa 1628 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1629
4487b3b4 1630 rc = em_push(ctxt);
dde7e6d1
AK		 1631 if (rc != X86EMUL_CONTINUE)
1632 return rc;
38ba30ba 1633
dde7e6d1 1634 ++reg;
38ba30ba 1635 }
38ba30ba 1636
dde7e6d1 1637 return rc;
38ba30ba
GN		 1638}
1639
62aaa2f0
TY		 1640static int em_pushf(struct x86_emulate_ctxt *ctxt)
1641{
9dac77fa 1642 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1643 return em_push(ctxt);
1644}
1645
b96a7fad 1646static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1647{
dde7e6d1
AK		 1648 int rc = X86EMUL_CONTINUE;
1649 int reg = VCPU_REGS_RDI;
38ba30ba 1650
dde7e6d1
AK		 1651 while (reg >= VCPU_REGS_RAX) {
1652 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1653 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1654 ctxt->op_bytes);
dde7e6d1
AK		 1655 --reg;
1656 }
38ba30ba 1657
9dac77fa 1658 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1659 if (rc != X86EMUL_CONTINUE)
1660 break;
1661 --reg;
38ba30ba 1662 }
dde7e6d1 1663 return rc;
38ba30ba
GN		 1664}
1665
7b105ca2 1666int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1667{
7b105ca2 1668 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1669 int rc;
6e154e56
MG		 1670 struct desc_ptr dt;
1671 gva_t cs_addr;
1672 gva_t eip_addr;
1673 u16 cs, eip;
6e154e56
MG		 1674
1675 /* TODO: Add limit checks */
9dac77fa 1676 ctxt->src.val = ctxt->eflags;
4487b3b4 1677 rc = em_push(ctxt);
5c56e1cf
AK		 1678 if (rc != X86EMUL_CONTINUE)
1679 return rc;
6e154e56
MG		 1680
1681 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1682
9dac77fa 1683 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1684 rc = em_push(ctxt);
5c56e1cf
AK		 1685 if (rc != X86EMUL_CONTINUE)
1686 return rc;
6e154e56 1687
9dac77fa 1688 ctxt->src.val = ctxt->_eip;
4487b3b4 1689 rc = em_push(ctxt);
5c56e1cf
AK		 1690 if (rc != X86EMUL_CONTINUE)
1691 return rc;
1692
4bff1e86 1693 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1694
1695 eip_addr = dt.address + (irq << 2);
1696 cs_addr = dt.address + (irq << 2) + 2;
1697
0f65dd70 1698 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1699 if (rc != X86EMUL_CONTINUE)
1700 return rc;
1701
0f65dd70 1702 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1703 if (rc != X86EMUL_CONTINUE)
1704 return rc;
1705
7b105ca2 1706 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1707 if (rc != X86EMUL_CONTINUE)
1708 return rc;
1709
9dac77fa 1710 ctxt->_eip = eip;
6e154e56
MG		 1711
1712 return rc;
1713}
1714
7b105ca2 1715static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1716{
1717 switch(ctxt->mode) {
1718 case X86EMUL_MODE_REAL:
7b105ca2 1719 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1720 case X86EMUL_MODE_VM86:
1721 case X86EMUL_MODE_PROT16:
1722 case X86EMUL_MODE_PROT32:
1723 case X86EMUL_MODE_PROT64:
1724 default:
1725 /* Protected mode interrupts unimplemented yet */
1726 return X86EMUL_UNHANDLEABLE;
1727 }
1728}
1729
7b105ca2 1730static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1731{
dde7e6d1
AK		 1732 int rc = X86EMUL_CONTINUE;
1733 unsigned long temp_eip = 0;
1734 unsigned long temp_eflags = 0;
1735 unsigned long cs = 0;
1736 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1737 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1738 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1739 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1740
dde7e6d1 1741 /* TODO: Add stack limit check */
38ba30ba 1742
9dac77fa 1743 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1744
dde7e6d1
AK		 1745 if (rc != X86EMUL_CONTINUE)
1746 return rc;
38ba30ba 1747
35d3d4a1
AK		 1748 if (temp_eip & ~0xffff)
1749 return emulate_gp(ctxt, 0);
38ba30ba 1750
9dac77fa 1751 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1752
dde7e6d1
AK		 1753 if (rc != X86EMUL_CONTINUE)
1754 return rc;
38ba30ba 1755
9dac77fa 1756 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1757
dde7e6d1
AK		 1758 if (rc != X86EMUL_CONTINUE)
1759 return rc;
38ba30ba 1760
7b105ca2 1761 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1762
dde7e6d1
AK		 1763 if (rc != X86EMUL_CONTINUE)
1764 return rc;
38ba30ba 1765
9dac77fa 1766 ctxt->_eip = temp_eip;
38ba30ba 1767
38ba30ba 1768
9dac77fa 1769 if (ctxt->op_bytes == 4)
dde7e6d1 1770 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1771 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1772 ctxt->eflags &= ~0xffff;
1773 ctxt->eflags |= temp_eflags;
38ba30ba 1774 }
dde7e6d1
AK		 1775
1776 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1777 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1778
1779 return rc;
38ba30ba
GN		 1780}
1781
e01991e7 1782static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1783{
dde7e6d1
AK		 1784 switch(ctxt->mode) {
1785 case X86EMUL_MODE_REAL:
7b105ca2 1786 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1787 case X86EMUL_MODE_VM86:
1788 case X86EMUL_MODE_PROT16:
1789 case X86EMUL_MODE_PROT32:
1790 case X86EMUL_MODE_PROT64:
c37eda13 1791 default:
dde7e6d1
AK		 1792 /* iret from protected mode unimplemented yet */
1793 return X86EMUL_UNHANDLEABLE;
c37eda13 1794 }
c37eda13
WY		 1795}
1796
d2f62766
TY		 1797static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1798{
d2f62766
TY		 1799 int rc;
1800 unsigned short sel;
1801
9dac77fa 1802 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1803
7b105ca2 1804 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1805 if (rc != X86EMUL_CONTINUE)
1806 return rc;
1807
9dac77fa
AK		 1808 ctxt->_eip = 0;
1809 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1810 return X86EMUL_CONTINUE;
1811}
1812
51187683 1813static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1814{
9dac77fa 1815 switch (ctxt->modrm_reg) {
8cdbd2c9 1816 case 0: /* rol */
a31b9cea 1817 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1818 break;
1819 case 1: /* ror */
a31b9cea 1820 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1821 break;
1822 case 2: /* rcl */
a31b9cea 1823 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1824 break;
1825 case 3: /* rcr */
a31b9cea 1826 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1827 break;
1828 case 4: /* sal/shl */
1829 case 6: /* sal/shl */
a31b9cea 1830 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1831 break;
1832 case 5: /* shr */
a31b9cea 1833 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1834 break;
1835 case 7: /* sar */
a31b9cea 1836 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1837 break;
1838 }
51187683 1839 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1840}
1841
3329ece1
AK		 1842static int em_not(struct x86_emulate_ctxt *ctxt)
1843{
1844 ctxt->dst.val = ~ctxt->dst.val;
1845 return X86EMUL_CONTINUE;
1846}
1847
1848static int em_neg(struct x86_emulate_ctxt *ctxt)
1849{
1850 emulate_1op(ctxt, "neg");
1851 return X86EMUL_CONTINUE;
1852}
1853
1854static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1855{
1856 u8 ex = 0;
1857
1858 emulate_1op_rax_rdx(ctxt, "mul", ex);
1859 return X86EMUL_CONTINUE;
1860}
1861
1862static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1863{
1864 u8 ex = 0;
1865
1866 emulate_1op_rax_rdx(ctxt, "imul", ex);
1867 return X86EMUL_CONTINUE;
1868}
1869
1870static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1871{
34d1f490 1872 u8 de = 0;
8cdbd2c9 1873
3329ece1
AK		 1874 emulate_1op_rax_rdx(ctxt, "div", de);
1875 if (de)
1876 return emulate_de(ctxt);
1877 return X86EMUL_CONTINUE;
1878}
1879
1880static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1881{
1882 u8 de = 0;
1883
1884 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1885 if (de)
1886 return emulate_de(ctxt);
8c5eee30 1887 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1888}
1889
51187683 1890static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1891{
4179bb02 1892 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1893
9dac77fa 1894 switch (ctxt->modrm_reg) {
8cdbd2c9 1895 case 0: /* inc */
d1eef45d 1896 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1897 break;
1898 case 1: /* dec */
d1eef45d 1899 emulate_1op(ctxt, "dec");
8cdbd2c9 1900 break;
d19292e4
MG		 1901 case 2: /* call near abs */ {
1902 long int old_eip;
9dac77fa
AK		 1903 old_eip = ctxt->_eip;
1904 ctxt->_eip = ctxt->src.val;
1905 ctxt->src.val = old_eip;
4487b3b4 1906 rc = em_push(ctxt);
d19292e4
MG		 1907 break;
1908 }
8cdbd2c9 1909 case 4: /* jmp abs */
9dac77fa 1910 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1911 break;
d2f62766
TY		 1912 case 5: /* jmp far */
1913 rc = em_jmp_far(ctxt);
1914 break;
8cdbd2c9 1915 case 6: /* push */
4487b3b4 1916 rc = em_push(ctxt);
8cdbd2c9 1917 break;
8cdbd2c9 1918 }
4179bb02 1919 return rc;
8cdbd2c9
LV		 1920}
1921
e0dac408 1922static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1923{
9dac77fa 1924 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1925
9dac77fa
AK		 1926 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1927 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1928 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1929 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1930 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1931 } else {
9dac77fa
AK		 1932 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1933 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1934
05f086f8 1935 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1936 }
1b30eaa8 1937 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1938}
1939
ebda02c2
TY		 1940static int em_ret(struct x86_emulate_ctxt *ctxt)
1941{
9dac77fa
AK		 1942 ctxt->dst.type = OP_REG;
1943 ctxt->dst.addr.reg = &ctxt->_eip;
1944 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1945 return em_pop(ctxt);
1946}
1947
e01991e7 1948static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1949{
a77ab5ea
AK		 1950 int rc;
1951 unsigned long cs;
1952
9dac77fa 1953 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1954 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1955 return rc;
9dac77fa
AK		 1956 if (ctxt->op_bytes == 4)
1957 ctxt->_eip = (u32)ctxt->_eip;
1958 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1959 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1960 return rc;
7b105ca2 1961 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1962 return rc;
1963}
1964
e940b5c2
TY		 1965static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1966{
1967 /* Save real source value, then compare EAX against destination. */
1968 ctxt->src.orig_val = ctxt->src.val;
1969 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1970 emulate_2op_SrcV(ctxt, "cmp");
1971
1972 if (ctxt->eflags & EFLG_ZF) {
1973 /* Success: write back to memory. */
1974 ctxt->dst.val = ctxt->src.orig_val;
1975 } else {
1976 /* Failure: write the value we saw to EAX. */
1977 ctxt->dst.type = OP_REG;
1978 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1979 }
1980 return X86EMUL_CONTINUE;
1981}
1982
d4b4325f 1983static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1984{
d4b4325f 1985 int seg = ctxt->src2.val;
09b5f4d3
WY		 1986 unsigned short sel;
1987 int rc;
1988
9dac77fa 1989 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1990
7b105ca2 1991 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
1994
9dac77fa 1995 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1996 return rc;
1997}
1998
7b105ca2 1999static void
e66bb2cc 2000setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2001 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2002{
1aa36616
AK		 2003 u16 selector;
2004
79168fd1 2005 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 2006 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 2007 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 2008
2009 cs->l = 0; /* will be adjusted later */
79168fd1 2010 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2011 cs->g = 1; /* 4kb granularity */
79168fd1 2012 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2013 cs->type = 0x0b; /* Read, Execute, Accessed */
2014 cs->s = 1;
2015 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2016 cs->p = 1;
2017 cs->d = 1;
e66bb2cc 2018
79168fd1
GN		 2019 set_desc_base(ss, 0); /* flat segment */
2020 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2021 ss->g = 1; /* 4kb granularity */
2022 ss->s = 1;
2023 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2024 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2025 ss->dpl = 0;
79168fd1 2026 ss->p = 1;
e66bb2cc
AP		 2027}
2028
1a18a69b
AK		 2029static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2030{
2031 u32 eax, ebx, ecx, edx;
2032
2033 eax = ecx = 0;
0017f93a
AK		 2034 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2035 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2036 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2037 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2038}
2039
c2226fc9
SB		 2040static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2041{
2042 struct x86_emulate_ops *ops = ctxt->ops;
2043 u32 eax, ebx, ecx, edx;
2044
2045 /*
2046 * syscall should always be enabled in longmode - so only become
2047 * vendor specific (cpuid) if other modes are active...
2048 */
2049 if (ctxt->mode == X86EMUL_MODE_PROT64)
2050 return true;
2051
2052 eax = 0x00000000;
2053 ecx = 0x00000000;
0017f93a
AK		 2054 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2055 /*
2056 * Intel ("GenuineIntel")
2057 * remark: Intel CPUs only support "syscall" in 64bit
2058 * longmode. Also an 64bit guest with a
2059 * 32bit compat-app running will #UD !! While this
2060 * behaviour can be fixed (by emulating) into AMD
2061 * response - CPUs of AMD can't behave like Intel.
2062 */
2063 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2064 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2065 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2066 return false;
2067
2068 /* AMD ("AuthenticAMD") */
2069 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2070 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2071 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2072 return true;
2073
2074 /* AMD ("AMDisbetter!") */
2075 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2076 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2077 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2078 return true;
c2226fc9
SB		 2079
2080 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2081 return false;
2082}
2083
e01991e7 2084static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2085{
7b105ca2 2086 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2087 struct desc_struct cs, ss;
e66bb2cc 2088 u64 msr_data;
79168fd1 2089 u16 cs_sel, ss_sel;
c2ad2bb3 2090 u64 efer = 0;
e66bb2cc
AP		 2091
2092 /* syscall is not available in real mode */
2e901c4c 2093 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2094 ctxt->mode == X86EMUL_MODE_VM86)
2095 return emulate_ud(ctxt);
e66bb2cc 2096
c2226fc9
SB		 2097 if (!(em_syscall_is_enabled(ctxt)))
2098 return emulate_ud(ctxt);
2099
c2ad2bb3 2100 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2101 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2102
c2226fc9
SB		 2103 if (!(efer & EFER_SCE))
2104 return emulate_ud(ctxt);
2105
717746e3 2106 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2107 msr_data >>= 32;
79168fd1
GN		 2108 cs_sel = (u16)(msr_data & 0xfffc);
2109 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2110
c2ad2bb3 2111 if (efer & EFER_LMA) {
79168fd1 2112 cs.d = 0;
e66bb2cc
AP		 2113 cs.l = 1;
2114 }
1aa36616
AK		 2115 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2116 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2117
9dac77fa 2118 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2119 if (efer & EFER_LMA) {
e66bb2cc 2120#ifdef CONFIG_X86_64
9dac77fa 2121 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2122
717746e3 2123 ops->get_msr(ctxt,
3fb1b5db
GN		 2124 ctxt->mode == X86EMUL_MODE_PROT64 ?
2125 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2126 ctxt->_eip = msr_data;
e66bb2cc 2127
717746e3 2128 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2129 ctxt->eflags &= ~(msr_data | EFLG_RF);
2130#endif
2131 } else {
2132 /* legacy mode */
717746e3 2133 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2134 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2135
2136 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2137 }
2138
e54cfa97 2139 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2140}
2141
e01991e7 2142static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2143{
7b105ca2 2144 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2145 struct desc_struct cs, ss;
8c604352 2146 u64 msr_data;
79168fd1 2147 u16 cs_sel, ss_sel;
c2ad2bb3 2148 u64 efer = 0;
8c604352 2149
7b105ca2 2150 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2151 /* inject #GP if in real mode */
35d3d4a1
AK		 2152 if (ctxt->mode == X86EMUL_MODE_REAL)
2153 return emulate_gp(ctxt, 0);
8c604352 2154
1a18a69b
AK		 2155 /*
2156 * Not recognized on AMD in compat mode (but is recognized in legacy
2157 * mode).
2158 */
2159 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2160 && !vendor_intel(ctxt))
2161 return emulate_ud(ctxt);
2162
8c604352
AP		 2163 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2164 * Therefore, we inject an #UD.
2165 */
35d3d4a1
AK		 2166 if (ctxt->mode == X86EMUL_MODE_PROT64)
2167 return emulate_ud(ctxt);
8c604352 2168
7b105ca2 2169 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2170
717746e3 2171 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2172 switch (ctxt->mode) {
2173 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2174 if ((msr_data & 0xfffc) == 0x0)
2175 return emulate_gp(ctxt, 0);
8c604352
AP		 2176 break;
2177 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2178 if (msr_data == 0x0)
2179 return emulate_gp(ctxt, 0);
8c604352
AP		 2180 break;
2181 }
2182
2183 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2184 cs_sel = (u16)msr_data;
2185 cs_sel &= ~SELECTOR_RPL_MASK;
2186 ss_sel = cs_sel + 8;
2187 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2188 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2189 cs.d = 0;
8c604352
AP		 2190 cs.l = 1;
2191 }
2192
1aa36616
AK		 2193 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2194 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2195
717746e3 2196 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2197 ctxt->_eip = msr_data;
8c604352 2198
717746e3 2199 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2200 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2201
e54cfa97 2202 return X86EMUL_CONTINUE;
8c604352
AP		 2203}
2204
e01991e7 2205static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2206{
7b105ca2 2207 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2208 struct desc_struct cs, ss;
4668f050
AP		 2209 u64 msr_data;
2210 int usermode;
1249b96e 2211 u16 cs_sel = 0, ss_sel = 0;
4668f050 2212
a0044755
GN		 2213 /* inject #GP if in real mode or Virtual 8086 mode */
2214 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2215 ctxt->mode == X86EMUL_MODE_VM86)
2216 return emulate_gp(ctxt, 0);
4668f050 2217
7b105ca2 2218 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2219
9dac77fa 2220 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2221 usermode = X86EMUL_MODE_PROT64;
2222 else
2223 usermode = X86EMUL_MODE_PROT32;
2224
2225 cs.dpl = 3;
2226 ss.dpl = 3;
717746e3 2227 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2228 switch (usermode) {
2229 case X86EMUL_MODE_PROT32:
79168fd1 2230 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2231 if ((msr_data & 0xfffc) == 0x0)
2232 return emulate_gp(ctxt, 0);
79168fd1 2233 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2234 break;
2235 case X86EMUL_MODE_PROT64:
79168fd1 2236 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2237 if (msr_data == 0x0)
2238 return emulate_gp(ctxt, 0);
79168fd1
GN		 2239 ss_sel = cs_sel + 8;
2240 cs.d = 0;
4668f050
AP		 2241 cs.l = 1;
2242 break;
2243 }
79168fd1
GN		 2244 cs_sel |= SELECTOR_RPL_MASK;
2245 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2246
1aa36616
AK		 2247 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2248 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2249
9dac77fa
AK		 2250 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2251 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2252
e54cfa97 2253 return X86EMUL_CONTINUE;
4668f050
AP		 2254}
2255
7b105ca2 2256static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2257{
2258 int iopl;
2259 if (ctxt->mode == X86EMUL_MODE_REAL)
2260 return false;
2261 if (ctxt->mode == X86EMUL_MODE_VM86)
2262 return true;
2263 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2264 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2265}
2266
2267static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2268 u16 port, u16 len)
2269{
7b105ca2 2270 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2271 struct desc_struct tr_seg;
5601d05b 2272 u32 base3;
f850e2e6 2273 int r;
1aa36616 2274 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2275 unsigned mask = (1 << len) - 1;
5601d05b 2276 unsigned long base;
f850e2e6 2277
1aa36616 2278 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2279 if (!tr_seg.p)
f850e2e6 2280 return false;
79168fd1 2281 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2282 return false;
5601d05b
GN		 2283 base = get_desc_base(&tr_seg);
2284#ifdef CONFIG_X86_64
2285 base |= ((u64)base3) << 32;
2286#endif
0f65dd70 2287 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2288 if (r != X86EMUL_CONTINUE)
2289 return false;
79168fd1 2290 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2291 return false;
0f65dd70 2292 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2293 if (r != X86EMUL_CONTINUE)
2294 return false;
2295 if ((perm >> bit_idx) & mask)
2296 return false;
2297 return true;
2298}
2299
2300static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2301 u16 port, u16 len)
2302{
4fc40f07
GN		 2303 if (ctxt->perm_ok)
2304 return true;
2305
7b105ca2
TY		 2306 if (emulator_bad_iopl(ctxt))
2307 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2308 return false;
4fc40f07
GN		 2309
2310 ctxt->perm_ok = true;
2311
f850e2e6
GN		 2312 return true;
2313}
2314
38ba30ba 2315static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2316 struct tss_segment_16 *tss)
2317{
9dac77fa 2318 tss->ip = ctxt->_eip;
38ba30ba 2319 tss->flag = ctxt->eflags;
9dac77fa
AK		 2320 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2321 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2322 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2323 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2324 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2325 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2326 tss->si = ctxt->regs[VCPU_REGS_RSI];
2327 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2328
1aa36616
AK		 2329 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2330 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2331 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2332 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2333 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2334}
2335
2336static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2337 struct tss_segment_16 *tss)
2338{
38ba30ba
GN		 2339 int ret;
2340
9dac77fa 2341 ctxt->_eip = tss->ip;
38ba30ba 2342 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2343 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2344 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2345 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2346 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2347 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2348 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2349 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2350 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2351
2352 /*
2353 * SDM says that segment selectors are loaded before segment
2354 * descriptors
2355 */
1aa36616
AK		 2356 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2357 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2358 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2359 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2360 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2361
2362 /*
2363 * Now load segment descriptors. If fault happenes at this stage
2364 * it is handled in a context of new task
2365 */
7b105ca2 2366 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2367 if (ret != X86EMUL_CONTINUE)
2368 return ret;
7b105ca2 2369 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2370 if (ret != X86EMUL_CONTINUE)
2371 return ret;
7b105ca2 2372 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2373 if (ret != X86EMUL_CONTINUE)
2374 return ret;
7b105ca2 2375 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2376 if (ret != X86EMUL_CONTINUE)
2377 return ret;
7b105ca2 2378 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2379 if (ret != X86EMUL_CONTINUE)
2380 return ret;
2381
2382 return X86EMUL_CONTINUE;
2383}
2384
2385static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2386 u16 tss_selector, u16 old_tss_sel,
2387 ulong old_tss_base, struct desc_struct *new_desc)
2388{
7b105ca2 2389 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2390 struct tss_segment_16 tss_seg;
2391 int ret;
bcc55cba 2392 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2393
0f65dd70 2394 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2395 &ctxt->exception);
db297e3d 2396 if (ret != X86EMUL_CONTINUE)
38ba30ba 2397 /* FIXME: need to provide precise fault address */
38ba30ba 2398 return ret;
38ba30ba 2399
7b105ca2 2400 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2401
0f65dd70 2402 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2403 &ctxt->exception);
db297e3d 2404 if (ret != X86EMUL_CONTINUE)
38ba30ba 2405 /* FIXME: need to provide precise fault address */
38ba30ba 2406 return ret;
38ba30ba 2407
0f65dd70 2408 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2409 &ctxt->exception);
db297e3d 2410 if (ret != X86EMUL_CONTINUE)
38ba30ba 2411 /* FIXME: need to provide precise fault address */
38ba30ba 2412 return ret;
38ba30ba
GN		 2413
2414 if (old_tss_sel != 0xffff) {
2415 tss_seg.prev_task_link = old_tss_sel;
2416
0f65dd70 2417 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2418 &tss_seg.prev_task_link,
2419 sizeof tss_seg.prev_task_link,
0f65dd70 2420 &ctxt->exception);
db297e3d 2421 if (ret != X86EMUL_CONTINUE)
38ba30ba 2422 /* FIXME: need to provide precise fault address */
38ba30ba 2423 return ret;
38ba30ba
GN		 2424 }
2425
7b105ca2 2426 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2427}
2428
2429static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2430 struct tss_segment_32 *tss)
2431{
7b105ca2 2432 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2433 tss->eip = ctxt->_eip;
38ba30ba 2434 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2435 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2436 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2437 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2438 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2439 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2440 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2441 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2442 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2443
1aa36616
AK		 2444 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2445 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2446 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2447 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2448 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2449 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2450 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2451}
2452
2453static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2454 struct tss_segment_32 *tss)
2455{
38ba30ba
GN		 2456 int ret;
2457
7b105ca2 2458 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2459 return emulate_gp(ctxt, 0);
9dac77fa 2460 ctxt->_eip = tss->eip;
38ba30ba 2461 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2462
2463 /* General purpose registers */
9dac77fa
AK		 2464 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2465 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2466 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2467 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2468 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2469 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2470 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2471 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2472
2473 /*
2474 * SDM says that segment selectors are loaded before segment
2475 * descriptors
2476 */
1aa36616
AK		 2477 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2478 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2479 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2480 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2481 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2482 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2483 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2484
4cee4798
KW		 2485 /*
2486 * If we're switching between Protected Mode and VM86, we need to make
2487 * sure to update the mode before loading the segment descriptors so
2488 * that the selectors are interpreted correctly.
2489 *
2490 * Need to get rflags to the vcpu struct immediately because it
2491 * influences the CPL which is checked at least when loading the segment
2492 * descriptors and when pushing an error code to the new kernel stack.
2493 *
2494 * TODO Introduce a separate ctxt->ops->set_cpl callback
2495 */
2496 if (ctxt->eflags & X86_EFLAGS_VM)
2497 ctxt->mode = X86EMUL_MODE_VM86;
2498 else
2499 ctxt->mode = X86EMUL_MODE_PROT32;
2500
2501 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2502
38ba30ba
GN		 2503 /*
2504 * Now load segment descriptors. If fault happenes at this stage
2505 * it is handled in a context of new task
2506 */
7b105ca2 2507 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2508 if (ret != X86EMUL_CONTINUE)
2509 return ret;
7b105ca2 2510 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2511 if (ret != X86EMUL_CONTINUE)
2512 return ret;
7b105ca2 2513 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2514 if (ret != X86EMUL_CONTINUE)
2515 return ret;
7b105ca2 2516 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2517 if (ret != X86EMUL_CONTINUE)
2518 return ret;
7b105ca2 2519 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2520 if (ret != X86EMUL_CONTINUE)
2521 return ret;
7b105ca2 2522 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2523 if (ret != X86EMUL_CONTINUE)
2524 return ret;
7b105ca2 2525 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2526 if (ret != X86EMUL_CONTINUE)
2527 return ret;
2528
2529 return X86EMUL_CONTINUE;
2530}
2531
2532static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2533 u16 tss_selector, u16 old_tss_sel,
2534 ulong old_tss_base, struct desc_struct *new_desc)
2535{
7b105ca2 2536 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2537 struct tss_segment_32 tss_seg;
2538 int ret;
bcc55cba 2539 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2540
0f65dd70 2541 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2542 &ctxt->exception);
db297e3d 2543 if (ret != X86EMUL_CONTINUE)
38ba30ba 2544 /* FIXME: need to provide precise fault address */
38ba30ba 2545 return ret;
38ba30ba 2546
7b105ca2 2547 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2548
0f65dd70 2549 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2550 &ctxt->exception);
db297e3d 2551 if (ret != X86EMUL_CONTINUE)
38ba30ba 2552 /* FIXME: need to provide precise fault address */
38ba30ba 2553 return ret;
38ba30ba 2554
0f65dd70 2555 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2556 &ctxt->exception);
db297e3d 2557 if (ret != X86EMUL_CONTINUE)
38ba30ba 2558 /* FIXME: need to provide precise fault address */
38ba30ba 2559 return ret;
38ba30ba
GN		 2560
2561 if (old_tss_sel != 0xffff) {
2562 tss_seg.prev_task_link = old_tss_sel;
2563
0f65dd70 2564 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2565 &tss_seg.prev_task_link,
2566 sizeof tss_seg.prev_task_link,
0f65dd70 2567 &ctxt->exception);
db297e3d 2568 if (ret != X86EMUL_CONTINUE)
38ba30ba 2569 /* FIXME: need to provide precise fault address */
38ba30ba 2570 return ret;
38ba30ba
GN		 2571 }
2572
7b105ca2 2573 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2574}
2575
2576static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2577 u16 tss_selector, int idt_index, int reason,
e269fb21 2578 bool has_error_code, u32 error_code)
38ba30ba 2579{
7b105ca2 2580 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2581 struct desc_struct curr_tss_desc, next_tss_desc;
2582 int ret;
1aa36616 2583 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2584 ulong old_tss_base =
4bff1e86 2585 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2586 u32 desc_limit;
38ba30ba
GN		 2587
2588 /* FIXME: old_tss_base == ~0 ? */
2589
7b105ca2 2590 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
7b105ca2 2593 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2594 if (ret != X86EMUL_CONTINUE)
2595 return ret;
2596
2597 /* FIXME: check that next_tss_desc is tss */
2598
7f3d35fd
KW		 2599 /*
2600 * Check privileges. The three cases are task switch caused by...
2601 *
2602 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2603 * 2. Exception/IRQ/iret: No check is performed
2604 * 3. jmp/call to TSS: Check agains DPL of the TSS
2605 */
2606 if (reason == TASK_SWITCH_GATE) {
2607 if (idt_index != -1) {
2608 /* Software interrupts */
2609 struct desc_struct task_gate_desc;
2610 int dpl;
2611
2612 ret = read_interrupt_descriptor(ctxt, idt_index,
2613 &task_gate_desc);
2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
2616
2617 dpl = task_gate_desc.dpl;
2618 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2619 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2620 }
2621 } else if (reason != TASK_SWITCH_IRET) {
2622 int dpl = next_tss_desc.dpl;
2623 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2624 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2625 }
2626
7f3d35fd 2627
ceffb459
GN		 2628 desc_limit = desc_limit_scaled(&next_tss_desc);
2629 if (!next_tss_desc.p ||
2630 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2631 desc_limit < 0x2b)) {
54b8486f 2632 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2633 return X86EMUL_PROPAGATE_FAULT;
2634 }
2635
2636 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2637 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2638 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2639 }
2640
2641 if (reason == TASK_SWITCH_IRET)
2642 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2643
2644 /* set back link to prev task only if NT bit is set in eflags
2645 note that old_tss_sel is not used afetr this point */
2646 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2647 old_tss_sel = 0xffff;
2648
2649 if (next_tss_desc.type & 8)
7b105ca2 2650 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2651 old_tss_base, &next_tss_desc);
2652 else
7b105ca2 2653 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2654 old_tss_base, &next_tss_desc);
0760d448
JK		 2655 if (ret != X86EMUL_CONTINUE)
2656 return ret;
38ba30ba
GN		 2657
2658 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2659 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2660
2661 if (reason != TASK_SWITCH_IRET) {
2662 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2663 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2664 }
2665
717746e3 2666 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2667 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2668
e269fb21 2669 if (has_error_code) {
9dac77fa
AK		 2670 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2671 ctxt->lock_prefix = 0;
2672 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2673 ret = em_push(ctxt);
e269fb21
JK		 2674 }
2675
38ba30ba
GN		 2676 return ret;
2677}
2678
2679int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2680 u16 tss_selector, int idt_index, int reason,
e269fb21 2681 bool has_error_code, u32 error_code)
38ba30ba 2682{
38ba30ba
GN		 2683 int rc;
2684
9dac77fa
AK		 2685 ctxt->_eip = ctxt->eip;
2686 ctxt->dst.type = OP_NONE;
38ba30ba 2687
7f3d35fd 2688 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2689 has_error_code, error_code);
38ba30ba 2690
4179bb02 2691 if (rc == X86EMUL_CONTINUE)
9dac77fa 2692 ctxt->eip = ctxt->_eip;
38ba30ba 2693
a0c0ab2f 2694 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2695}
2696
90de84f5 2697static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2698 int reg, struct operand *op)
a682e354 2699{
a682e354
GN		 2700 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2701
9dac77fa
AK		 2702 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2703 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2704 op->addr.mem.seg = seg;
a682e354
GN		 2705}
2706
7af04fc0
AK		 2707static int em_das(struct x86_emulate_ctxt *ctxt)
2708{
7af04fc0
AK		 2709 u8 al, old_al;
2710 bool af, cf, old_cf;
2711
2712 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2713 al = ctxt->dst.val;
7af04fc0
AK		 2714
2715 old_al = al;
2716 old_cf = cf;
2717 cf = false;
2718 af = ctxt->eflags & X86_EFLAGS_AF;
2719 if ((al & 0x0f) > 9 || af) {
2720 al -= 6;
2721 cf = old_cf | (al >= 250);
2722 af = true;
2723 } else {
2724 af = false;
2725 }
2726 if (old_al > 0x99 || old_cf) {
2727 al -= 0x60;
2728 cf = true;
2729 }
2730
9dac77fa 2731 ctxt->dst.val = al;
7af04fc0 2732 /* Set PF, ZF, SF */
9dac77fa
AK		 2733 ctxt->src.type = OP_IMM;
2734 ctxt->src.val = 0;
2735 ctxt->src.bytes = 1;
a31b9cea 2736 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2737 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2738 if (cf)
2739 ctxt->eflags |= X86_EFLAGS_CF;
2740 if (af)
2741 ctxt->eflags |= X86_EFLAGS_AF;
2742 return X86EMUL_CONTINUE;
2743}
2744
d4ddafcd
TY		 2745static int em_call(struct x86_emulate_ctxt *ctxt)
2746{
2747 long rel = ctxt->src.val;
2748
2749 ctxt->src.val = (unsigned long)ctxt->_eip;
2750 jmp_rel(ctxt, rel);
2751 return em_push(ctxt);
2752}
2753
0ef753b8
AK		 2754static int em_call_far(struct x86_emulate_ctxt *ctxt)
2755{
0ef753b8
AK		 2756 u16 sel, old_cs;
2757 ulong old_eip;
2758 int rc;
2759
1aa36616 2760 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2761 old_eip = ctxt->_eip;
0ef753b8 2762
9dac77fa 2763 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2764 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2765 return X86EMUL_CONTINUE;
2766
9dac77fa
AK		 2767 ctxt->_eip = 0;
2768 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2769
9dac77fa 2770 ctxt->src.val = old_cs;
4487b3b4 2771 rc = em_push(ctxt);
0ef753b8
AK		 2772 if (rc != X86EMUL_CONTINUE)
2773 return rc;
2774
9dac77fa 2775 ctxt->src.val = old_eip;
4487b3b4 2776 return em_push(ctxt);
0ef753b8
AK		 2777}
2778
40ece7c7
AK		 2779static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2780{
40ece7c7
AK		 2781 int rc;
2782
9dac77fa
AK		 2783 ctxt->dst.type = OP_REG;
2784 ctxt->dst.addr.reg = &ctxt->_eip;
2785 ctxt->dst.bytes = ctxt->op_bytes;
2786 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2787 if (rc != X86EMUL_CONTINUE)
2788 return rc;
9dac77fa 2789 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2790 return X86EMUL_CONTINUE;
2791}
2792
d67fc27a
TY		 2793static int em_add(struct x86_emulate_ctxt *ctxt)
2794{
a31b9cea 2795 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2796 return X86EMUL_CONTINUE;
2797}
2798
2799static int em_or(struct x86_emulate_ctxt *ctxt)
2800{
a31b9cea 2801 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2802 return X86EMUL_CONTINUE;
2803}
2804
2805static int em_adc(struct x86_emulate_ctxt *ctxt)
2806{
a31b9cea 2807 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2808 return X86EMUL_CONTINUE;
2809}
2810
2811static int em_sbb(struct x86_emulate_ctxt *ctxt)
2812{
a31b9cea 2813 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2814 return X86EMUL_CONTINUE;
2815}
2816
2817static int em_and(struct x86_emulate_ctxt *ctxt)
2818{
a31b9cea 2819 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2820 return X86EMUL_CONTINUE;
2821}
2822
2823static int em_sub(struct x86_emulate_ctxt *ctxt)
2824{
a31b9cea 2825 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2826 return X86EMUL_CONTINUE;
2827}
2828
2829static int em_xor(struct x86_emulate_ctxt *ctxt)
2830{
a31b9cea 2831 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2832 return X86EMUL_CONTINUE;
2833}
2834
2835static int em_cmp(struct x86_emulate_ctxt *ctxt)
2836{
a31b9cea 2837 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2838 /* Disable writeback. */
9dac77fa 2839 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2840 return X86EMUL_CONTINUE;
2841}
2842
9f21ca59
TY		 2843static int em_test(struct x86_emulate_ctxt *ctxt)
2844{
a31b9cea 2845 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2846 /* Disable writeback. */
2847 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2848 return X86EMUL_CONTINUE;
2849}
2850
e4f973ae
TY		 2851static int em_xchg(struct x86_emulate_ctxt *ctxt)
2852{
e4f973ae 2853 /* Write back the register source. */
9dac77fa
AK		 2854 ctxt->src.val = ctxt->dst.val;
2855 write_register_operand(&ctxt->src);
e4f973ae
TY		 2856
2857 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2858 ctxt->dst.val = ctxt->src.orig_val;
2859 ctxt->lock_prefix = 1;
e4f973ae
TY		 2860 return X86EMUL_CONTINUE;
2861}
2862
5c82aa29 2863static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2864{
a31b9cea 2865 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2866 return X86EMUL_CONTINUE;
2867}
2868
5c82aa29
AK		 2869static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2870{
9dac77fa 2871 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2872 return em_imul(ctxt);
2873}
2874
61429142
AK		 2875static int em_cwd(struct x86_emulate_ctxt *ctxt)
2876{
9dac77fa
AK		 2877 ctxt->dst.type = OP_REG;
2878 ctxt->dst.bytes = ctxt->src.bytes;
2879 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2880 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2881
2882 return X86EMUL_CONTINUE;
2883}
2884
48bb5d3c
AK		 2885static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2886{
48bb5d3c
AK		 2887 u64 tsc = 0;
2888
717746e3 2889 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2890 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2891 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2892 return X86EMUL_CONTINUE;
2893}
2894
222d21aa
AK		 2895static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2896{
2897 u64 pmc;
2898
2899 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2900 return emulate_gp(ctxt, 0);
2901 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2902 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2903 return X86EMUL_CONTINUE;
2904}
2905
b9eac5f4
AK		 2906static int em_mov(struct x86_emulate_ctxt *ctxt)
2907{
49597d81 2908 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2909 return X86EMUL_CONTINUE;
2910}
2911
bc00f8d2
TY		 2912static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2913{
2914 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2915 return emulate_gp(ctxt, 0);
2916
2917 /* Disable writeback. */
2918 ctxt->dst.type = OP_NONE;
2919 return X86EMUL_CONTINUE;
2920}
2921
2922static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2923{
2924 unsigned long val;
2925
2926 if (ctxt->mode == X86EMUL_MODE_PROT64)
2927 val = ctxt->src.val & ~0ULL;
2928 else
2929 val = ctxt->src.val & ~0U;
2930
2931 /* #UD condition is already handled. */
2932 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2933 return emulate_gp(ctxt, 0);
2934
2935 /* Disable writeback. */
2936 ctxt->dst.type = OP_NONE;
2937 return X86EMUL_CONTINUE;
2938}
2939
e1e210b0
TY		 2940static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2941{
2942 u64 msr_data;
2943
2944 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2945 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2946 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2947 return emulate_gp(ctxt, 0);
2948
2949 return X86EMUL_CONTINUE;
2950}
2951
2952static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2953{
2954 u64 msr_data;
2955
2956 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2957 return emulate_gp(ctxt, 0);
2958
2959 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2960 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2961 return X86EMUL_CONTINUE;
2962}
2963
1bd5f469
TY		 2964static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2965{
9dac77fa 2966 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2967 return emulate_ud(ctxt);
2968
9dac77fa 2969 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2970 return X86EMUL_CONTINUE;
2971}
2972
2973static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2974{
9dac77fa 2975 u16 sel = ctxt->src.val;
1bd5f469 2976
9dac77fa 2977 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2978 return emulate_ud(ctxt);
2979
9dac77fa 2980 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2981 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2982
2983 /* Disable writeback. */
9dac77fa
AK		 2984 ctxt->dst.type = OP_NONE;
2985 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2986}
2987
38503911
AK		 2988static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2989{
9fa088f4
AK		 2990 int rc;
2991 ulong linear;
2992
9dac77fa 2993 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2994 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2995 ctxt->ops->invlpg(ctxt, linear);
38503911 2996 /* Disable writeback. */
9dac77fa 2997 ctxt->dst.type = OP_NONE;
38503911
AK		 2998 return X86EMUL_CONTINUE;
2999}
3000
2d04a05b
AK		 3001static int em_clts(struct x86_emulate_ctxt *ctxt)
3002{
3003 ulong cr0;
3004
3005 cr0 = ctxt->ops->get_cr(ctxt, 0);
3006 cr0 &= ~X86_CR0_TS;
3007 ctxt->ops->set_cr(ctxt, 0, cr0);
3008 return X86EMUL_CONTINUE;
3009}
3010
26d05cc7
AK		 3011static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3012{
26d05cc7
AK		 3013 int rc;
3014
9dac77fa 3015 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3016 return X86EMUL_UNHANDLEABLE;
3017
3018 rc = ctxt->ops->fix_hypercall(ctxt);
3019 if (rc != X86EMUL_CONTINUE)
3020 return rc;
3021
3022 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3023 ctxt->_eip = ctxt->eip;
26d05cc7 3024 /* Disable writeback. */
9dac77fa 3025 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3026 return X86EMUL_CONTINUE;
3027}
3028
96051572
AK		 3029static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3030 void (*get)(struct x86_emulate_ctxt *ctxt,
3031 struct desc_ptr *ptr))
3032{
3033 struct desc_ptr desc_ptr;
3034
3035 if (ctxt->mode == X86EMUL_MODE_PROT64)
3036 ctxt->op_bytes = 8;
3037 get(ctxt, &desc_ptr);
3038 if (ctxt->op_bytes == 2) {
3039 ctxt->op_bytes = 4;
3040 desc_ptr.address &= 0x00ffffff;
3041 }
3042 /* Disable writeback. */
3043 ctxt->dst.type = OP_NONE;
3044 return segmented_write(ctxt, ctxt->dst.addr.mem,
3045 &desc_ptr, 2 + ctxt->op_bytes);
3046}
3047
3048static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3049{
3050 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3051}
3052
3053static int em_sidt(struct x86_emulate_ctxt *ctxt)
3054{
3055 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3056}
3057
26d05cc7
AK		 3058static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3059{
26d05cc7
AK		 3060 struct desc_ptr desc_ptr;
3061 int rc;
3062
510425ff
AK		 3063 if (ctxt->mode == X86EMUL_MODE_PROT64)
3064 ctxt->op_bytes = 8;
9dac77fa 3065 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3066 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3067 ctxt->op_bytes);
26d05cc7
AK		 3068 if (rc != X86EMUL_CONTINUE)
3069 return rc;
3070 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3071 /* Disable writeback. */
9dac77fa 3072 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3073 return X86EMUL_CONTINUE;
3074}
3075
5ef39c71 3076static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3077{
26d05cc7
AK		 3078 int rc;
3079
5ef39c71
AK		 3080 rc = ctxt->ops->fix_hypercall(ctxt);
3081
26d05cc7 3082 /* Disable writeback. */
9dac77fa 3083 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3084 return rc;
3085}
3086
3087static int em_lidt(struct x86_emulate_ctxt *ctxt)
3088{
26d05cc7
AK		 3089 struct desc_ptr desc_ptr;
3090 int rc;
3091
510425ff
AK		 3092 if (ctxt->mode == X86EMUL_MODE_PROT64)
3093 ctxt->op_bytes = 8;
9dac77fa 3094 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3095 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3096 ctxt->op_bytes);
26d05cc7
AK		 3097 if (rc != X86EMUL_CONTINUE)
3098 return rc;
3099 ctxt->ops->set_idt(ctxt, &desc_ptr);
3100 /* Disable writeback. */
9dac77fa 3101 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3102 return X86EMUL_CONTINUE;
3103}
3104
3105static int em_smsw(struct x86_emulate_ctxt *ctxt)
3106{
9dac77fa
AK		 3107 ctxt->dst.bytes = 2;
3108 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3109 return X86EMUL_CONTINUE;
3110}
3111
3112static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3113{
26d05cc7 3114 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3115 | (ctxt->src.val & 0x0f));
3116 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3117 return X86EMUL_CONTINUE;
3118}
3119
d06e03ad
TY		 3120static int em_loop(struct x86_emulate_ctxt *ctxt)
3121{
9dac77fa
AK		 3122 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3123 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3124 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3125 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3126
3127 return X86EMUL_CONTINUE;
3128}
3129
3130static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3131{
9dac77fa
AK		 3132 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3133 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3134
3135 return X86EMUL_CONTINUE;
3136}
3137
d7841a4b
TY		 3138static int em_in(struct x86_emulate_ctxt *ctxt)
3139{
3140 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3141 &ctxt->dst.val))
3142 return X86EMUL_IO_NEEDED;
3143
3144 return X86EMUL_CONTINUE;
3145}
3146
3147static int em_out(struct x86_emulate_ctxt *ctxt)
3148{
3149 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3150 &ctxt->src.val, 1);
3151 /* Disable writeback. */
3152 ctxt->dst.type = OP_NONE;
3153 return X86EMUL_CONTINUE;
3154}
3155
f411e6cd
TY		 3156static int em_cli(struct x86_emulate_ctxt *ctxt)
3157{
3158 if (emulator_bad_iopl(ctxt))
3159 return emulate_gp(ctxt, 0);
3160
3161 ctxt->eflags &= ~X86_EFLAGS_IF;
3162 return X86EMUL_CONTINUE;
3163}
3164
3165static int em_sti(struct x86_emulate_ctxt *ctxt)
3166{
3167 if (emulator_bad_iopl(ctxt))
3168 return emulate_gp(ctxt, 0);
3169
3170 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3171 ctxt->eflags |= X86_EFLAGS_IF;
3172 return X86EMUL_CONTINUE;
3173}
3174
ce7faab2
TY		 3175static int em_bt(struct x86_emulate_ctxt *ctxt)
3176{
3177 /* Disable writeback. */
3178 ctxt->dst.type = OP_NONE;
3179 /* only subword offset */
3180 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3181
3182 emulate_2op_SrcV_nobyte(ctxt, "bt");
3183 return X86EMUL_CONTINUE;
3184}
3185
3186static int em_bts(struct x86_emulate_ctxt *ctxt)
3187{
3188 emulate_2op_SrcV_nobyte(ctxt, "bts");
3189 return X86EMUL_CONTINUE;
3190}
3191
3192static int em_btr(struct x86_emulate_ctxt *ctxt)
3193{
3194 emulate_2op_SrcV_nobyte(ctxt, "btr");
3195 return X86EMUL_CONTINUE;
3196}
3197
3198static int em_btc(struct x86_emulate_ctxt *ctxt)
3199{
3200 emulate_2op_SrcV_nobyte(ctxt, "btc");
3201 return X86EMUL_CONTINUE;
3202}
3203
ff227392
TY		 3204static int em_bsf(struct x86_emulate_ctxt *ctxt)
3205{
d54e4237 3206 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3207 return X86EMUL_CONTINUE;
3208}
3209
3210static int em_bsr(struct x86_emulate_ctxt *ctxt)
3211{
d54e4237 3212 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3213 return X86EMUL_CONTINUE;
3214}
3215
6d6eede4
AK		 3216static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3217{
3218 u32 eax, ebx, ecx, edx;
3219
3220 eax = ctxt->regs[VCPU_REGS_RAX];
3221 ecx = ctxt->regs[VCPU_REGS_RCX];
3222 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3223 ctxt->regs[VCPU_REGS_RAX] = eax;
3224 ctxt->regs[VCPU_REGS_RBX] = ebx;
3225 ctxt->regs[VCPU_REGS_RCX] = ecx;
3226 ctxt->regs[VCPU_REGS_RDX] = edx;
3227 return X86EMUL_CONTINUE;
3228}
3229
cfec82cb
JR		 3230static bool valid_cr(int nr)
3231{
3232 switch (nr) {
3233 case 0:
3234 case 2 ... 4:
3235 case 8:
3236 return true;
3237 default:
3238 return false;
3239 }
3240}
3241
3242static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3243{
9dac77fa 3244 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3245 return emulate_ud(ctxt);
3246
3247 return X86EMUL_CONTINUE;
3248}
3249
3250static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3251{
9dac77fa
AK		 3252 u64 new_val = ctxt->src.val64;
3253 int cr = ctxt->modrm_reg;
c2ad2bb3 3254 u64 efer = 0;
cfec82cb
JR		 3255
3256 static u64 cr_reserved_bits[] = {
3257 0xffffffff00000000ULL,
3258 0, 0, 0, /* CR3 checked later */
3259 CR4_RESERVED_BITS,
3260 0, 0, 0,
3261 CR8_RESERVED_BITS,
3262 };
3263
3264 if (!valid_cr(cr))
3265 return emulate_ud(ctxt);
3266
3267 if (new_val & cr_reserved_bits[cr])
3268 return emulate_gp(ctxt, 0);
3269
3270 switch (cr) {
3271 case 0: {
c2ad2bb3 3272 u64 cr4;
cfec82cb
JR		 3273 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3274 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3275 return emulate_gp(ctxt, 0);
3276
717746e3
AK		 3277 cr4 = ctxt->ops->get_cr(ctxt, 4);
3278 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3279
3280 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3281 !(cr4 & X86_CR4_PAE))
3282 return emulate_gp(ctxt, 0);
3283
3284 break;
3285 }
3286 case 3: {
3287 u64 rsvd = 0;
3288
c2ad2bb3
AK		 3289 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3290 if (efer & EFER_LMA)
cfec82cb 3291 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3292 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3293 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3294 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3295 rsvd = CR3_NONPAE_RESERVED_BITS;
3296
3297 if (new_val & rsvd)
3298 return emulate_gp(ctxt, 0);
3299
3300 break;
3301 }
3302 case 4: {
717746e3 3303 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3304
3305 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3306 return emulate_gp(ctxt, 0);
3307
3308 break;
3309 }
3310 }
3311
3312 return X86EMUL_CONTINUE;
3313}
3314
3b88e41a
JR		 3315static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3316{
3317 unsigned long dr7;
3318
717746e3 3319 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3320
3321 /* Check if DR7.Global_Enable is set */
3322 return dr7 & (1 << 13);
3323}
3324
3325static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3326{
9dac77fa 3327 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3328 u64 cr4;
3329
3330 if (dr > 7)
3331 return emulate_ud(ctxt);
3332
717746e3 3333 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3334 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3335 return emulate_ud(ctxt);
3336
3337 if (check_dr7_gd(ctxt))
3338 return emulate_db(ctxt);
3339
3340 return X86EMUL_CONTINUE;
3341}
3342
3343static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3344{
9dac77fa
AK		 3345 u64 new_val = ctxt->src.val64;
3346 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3347
3348 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3349 return emulate_gp(ctxt, 0);
3350
3351 return check_dr_read(ctxt);
3352}
3353
01de8b09
JR		 3354static int check_svme(struct x86_emulate_ctxt *ctxt)
3355{
3356 u64 efer;
3357
717746e3 3358 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3359
3360 if (!(efer & EFER_SVME))
3361 return emulate_ud(ctxt);
3362
3363 return X86EMUL_CONTINUE;
3364}
3365
3366static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3367{
9dac77fa 3368 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3369
3370 /* Valid physical address? */
d4224449 3371 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3372 return emulate_gp(ctxt, 0);
3373
3374 return check_svme(ctxt);
3375}
3376
d7eb8203
JR		 3377static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3378{
717746e3 3379 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3380
717746e3 3381 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3382 return emulate_ud(ctxt);
3383
3384 return X86EMUL_CONTINUE;
3385}
3386
8061252e
JR		 3387static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3388{
717746e3 3389 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3390 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3391
717746e3 3392 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3393 (rcx > 3))
3394 return emulate_gp(ctxt, 0);
3395
3396 return X86EMUL_CONTINUE;
3397}
3398
f6511935
JR		 3399static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3400{
9dac77fa
AK		 3401 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3402 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3403 return emulate_gp(ctxt, 0);
3404
3405 return X86EMUL_CONTINUE;
3406}
3407
3408static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3409{
9dac77fa
AK		 3410 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3411 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3412 return emulate_gp(ctxt, 0);
3413
3414 return X86EMUL_CONTINUE;
3415}
3416
73fba5f4 3417#define D(_y) { .flags = (_y) }
c4f035c6 3418#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3419#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3420 .check_perm = (_p) }
73fba5f4 3421#define N D(0)
01de8b09 3422#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3423#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3424#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3425#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3426#define II(_f, _e, _i) \
3427 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3428#define IIP(_f, _e, _i, _p) \
3429 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3430 .check_perm = (_p) }
aa97bb48 3431#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3432
8d8f4e9f 3433#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3434#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3435#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3436#define I2bvIP(_f, _e, _i, _p) \
3437 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3438
d67fc27a
TY		 3439#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3440 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3441 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3442
d7eb8203 3443static struct opcode group7_rm1[] = {
1c2545be
TY		 3444 DI(SrcNone | Priv, monitor),
3445 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3446 N, N, N, N, N, N,
3447};
3448
01de8b09 3449static struct opcode group7_rm3[] = {
1c2545be
TY		 3450 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3451 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3452 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3453 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3454 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3455 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3456 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3457 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3458};
6230f7fc 3459
d7eb8203
JR		 3460static struct opcode group7_rm7[] = {
3461 N,
1c2545be 3462 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3463 N, N, N, N, N, N,
3464};
d67fc27a 3465
73fba5f4 3466static struct opcode group1[] = {
d67fc27a 3467 I(Lock, em_add),
d5ae7ce8 3468 I(Lock | PageTable, em_or),
d67fc27a
TY		 3469 I(Lock, em_adc),
3470 I(Lock, em_sbb),
d5ae7ce8 3471 I(Lock | PageTable, em_and),
d67fc27a
TY		 3472 I(Lock, em_sub),
3473 I(Lock, em_xor),
3474 I(0, em_cmp),
73fba5f4
AK		 3475};
3476
3477static struct opcode group1A[] = {
1c2545be 3478 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3479};
3480
3481static struct opcode group3[] = {
1c2545be
TY		 3482 I(DstMem | SrcImm, em_test),
3483 I(DstMem | SrcImm, em_test),
3484 I(DstMem | SrcNone | Lock, em_not),
3485 I(DstMem | SrcNone | Lock, em_neg),
3486 I(SrcMem, em_mul_ex),
3487 I(SrcMem, em_imul_ex),
3488 I(SrcMem, em_div_ex),
3489 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3490};
3491
3492static struct opcode group4[] = {
1c2545be
TY		 3493 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3494 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3495 N, N, N, N, N, N,
3496};
3497
3498static struct opcode group5[] = {
1c2545be
TY		 3499 I(DstMem | SrcNone | Lock, em_grp45),
3500 I(DstMem | SrcNone | Lock, em_grp45),
3501 I(SrcMem | Stack, em_grp45),
3502 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3503 I(SrcMem | Stack, em_grp45),
3504 I(SrcMemFAddr | ImplicitOps, em_grp45),
3505 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3506};
3507
dee6bb70 3508static struct opcode group6[] = {
1c2545be
TY		 3509 DI(Prot, sldt),
3510 DI(Prot, str),
3511 DI(Prot | Priv, lldt),
3512 DI(Prot | Priv, ltr),
dee6bb70
JR		 3513 N, N, N, N,
3514};
3515
73fba5f4 3516static struct group_dual group7 = { {
96051572
AK		 3517 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3518 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3519 II(SrcMem | Priv, em_lgdt, lgdt),
3520 II(SrcMem | Priv, em_lidt, lidt),
3521 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3522 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3523 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3524}, {
1c2545be 3525 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3526 EXT(0, group7_rm1),
01de8b09 3527 N, EXT(0, group7_rm3),
1c2545be
TY		 3528 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3529 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3530 EXT(0, group7_rm7),
73fba5f4
AK		 3531} };
3532
3533static struct opcode group8[] = {
3534 N, N, N, N,
1c2545be
TY		 3535 I(DstMem | SrcImmByte, em_bt),
3536 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3537 I(DstMem | SrcImmByte | Lock, em_btr),
3538 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3539};
3540
3541static struct group_dual group9 = { {
1c2545be 3542 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3543}, {
3544 N, N, N, N, N, N, N, N,
3545} };
3546
a4d4a7c1 3547static struct opcode group11[] = {
1c2545be 3548 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3549 X7(D(Undefined)),
a4d4a7c1
AK		 3550};
3551
aa97bb48 3552static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3553 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3554};
3555
3e114eb4
AK		 3556static struct gprefix pfx_vmovntpx = {
3557 I(0, em_mov), N, N, N,
3558};
3559
73fba5f4
AK		 3560static struct opcode opcode_table[256] = {
3561 /* 0x00 - 0x07 */
d67fc27a 3562 I6ALU(Lock, em_add),
1cd196ea
AK		 3563 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3564 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3565 /* 0x08 - 0x0F */
d5ae7ce8 3566 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3567 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3568 N,
73fba5f4 3569 /* 0x10 - 0x17 */
d67fc27a 3570 I6ALU(Lock, em_adc),
1cd196ea
AK		 3571 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3572 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3573 /* 0x18 - 0x1F */
d67fc27a 3574 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3575 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3576 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3577 /* 0x20 - 0x27 */
d5ae7ce8 3578 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3579 /* 0x28 - 0x2F */
d67fc27a 3580 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3581 /* 0x30 - 0x37 */
d67fc27a 3582 I6ALU(Lock, em_xor), N, N,
73fba5f4 3583 /* 0x38 - 0x3F */
d67fc27a 3584 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3585 /* 0x40 - 0x4F */
3586 X16(D(DstReg)),
3587 /* 0x50 - 0x57 */
63540382 3588 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3589 /* 0x58 - 0x5F */
c54fe504 3590 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3591 /* 0x60 - 0x67 */
b96a7fad
TY		 3592 I(ImplicitOps | Stack | No64, em_pusha),
3593 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3594 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3595 N, N, N, N,
3596 /* 0x68 - 0x6F */
d46164db
AK		 3597 I(SrcImm | Mov | Stack, em_push),
3598 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3599 I(SrcImmByte | Mov | Stack, em_push),
3600 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3601 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3602 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3603 /* 0x70 - 0x7F */
3604 X16(D(SrcImmByte)),
3605 /* 0x80 - 0x87 */
1c2545be
TY		 3606 G(ByteOp | DstMem | SrcImm, group1),
3607 G(DstMem | SrcImm, group1),
3608 G(ByteOp | DstMem | SrcImm | No64, group1),
3609 G(DstMem | SrcImmByte, group1),
9f21ca59 3610 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3611 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3612 /* 0x88 - 0x8F */
d5ae7ce8 3613 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3614 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3615 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3616 D(ModRM | SrcMem | NoAccess | DstReg),
3617 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3618 G(0, group1A),
73fba5f4 3619 /* 0x90 - 0x97 */
bf608f88 3620 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3621 /* 0x98 - 0x9F */
61429142 3622 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3623 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3624 II(ImplicitOps | Stack, em_pushf, pushf),
3625 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3626 /* 0xA0 - 0xA7 */
b9eac5f4 3627 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3628 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3629 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3630 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3631 /* 0xA8 - 0xAF */
9f21ca59 3632 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3633 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3634 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3635 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3636 /* 0xB0 - 0xB7 */
b9eac5f4 3637 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3638 /* 0xB8 - 0xBF */
b9eac5f4 3639 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3640 /* 0xC0 - 0xC7 */
d2c6c7ad 3641 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3642 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3643 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3644 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3645 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3646 G(ByteOp, group11), G(0, group11),
73fba5f4 3647 /* 0xC8 - 0xCF */
f47cfa31 3648 N, I(Stack, em_leave), N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3649 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3650 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3651 /* 0xD0 - 0xD7 */
d2c6c7ad 3652 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3653 N, N, N, N,
3654 /* 0xD8 - 0xDF */
3655 N, N, N, N, N, N, N, N,
3656 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3657 X3(I(SrcImmByte, em_loop)),
3658 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3659 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3660 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3661 /* 0xE8 - 0xEF */
d4ddafcd 3662 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3663 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3664 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3665 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3666 /* 0xF0 - 0xF7 */
bf608f88 3667 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3668 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3669 G(ByteOp, group3), G(0, group3),
73fba5f4 3670 /* 0xF8 - 0xFF */
f411e6cd
TY		 3671 D(ImplicitOps), D(ImplicitOps),
3672 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3673 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3674};
3675
3676static struct opcode twobyte_table[256] = {
3677 /* 0x00 - 0x0F */
dee6bb70 3678 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3679 N, I(ImplicitOps | VendorSpecific, em_syscall),
3680 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3681 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3682 N, D(ImplicitOps | ModRM), N, N,
3683 /* 0x10 - 0x1F */
3684 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3685 /* 0x20 - 0x2F */
cfec82cb 3686 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3687 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3688 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3689 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3690 N, N, N, N,
3e114eb4
AK		 3691 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3692 N, N, N, N,
73fba5f4 3693 /* 0x30 - 0x3F */
e1e210b0 3694 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3695 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3696 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3697 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3698 I(ImplicitOps | VendorSpecific, em_sysenter),
3699 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3700 N, N,
73fba5f4
AK		 3701 N, N, N, N, N, N, N, N,
3702 /* 0x40 - 0x4F */
3703 X16(D(DstReg | SrcMem | ModRM | Mov)),
3704 /* 0x50 - 0x5F */
3705 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3706 /* 0x60 - 0x6F */
aa97bb48
AK		 3707 N, N, N, N,
3708 N, N, N, N,
3709 N, N, N, N,
3710 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3711 /* 0x70 - 0x7F */
aa97bb48
AK		 3712 N, N, N, N,
3713 N, N, N, N,
3714 N, N, N, N,
3715 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3716 /* 0x80 - 0x8F */
3717 X16(D(SrcImm)),
3718 /* 0x90 - 0x9F */
ee45b58e 3719 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3720 /* 0xA0 - 0xA7 */
1cd196ea 3721 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3722 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3723 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3724 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3725 /* 0xA8 - 0xAF */
1cd196ea 3726 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3727 DI(ImplicitOps, rsm),
ce7faab2 3728 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3729 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3730 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3731 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3732 /* 0xB0 - 0xB7 */
e940b5c2 3733 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3734 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3735 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3736 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3737 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3738 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3739 /* 0xB8 - 0xBF */
3740 N, N,
ce7faab2
TY		 3741 G(BitOp, group8),
3742 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3743 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3744 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3745 /* 0xC0 - 0xCF */
739ae406 3746 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3747 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3748 N, N, N, GD(0, &group9),
3749 N, N, N, N, N, N, N, N,
3750 /* 0xD0 - 0xDF */
3751 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3752 /* 0xE0 - 0xEF */
3753 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3754 /* 0xF0 - 0xFF */
3755 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3756};
3757
3758#undef D
3759#undef N
3760#undef G
3761#undef GD
3762#undef I
aa97bb48 3763#undef GP
01de8b09 3764#undef EXT
73fba5f4 3765
8d8f4e9f 3766#undef D2bv
f6511935 3767#undef D2bvIP
8d8f4e9f 3768#undef I2bv
d7841a4b 3769#undef I2bvIP
d67fc27a 3770#undef I6ALU
8d8f4e9f 3771
9dac77fa 3772static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3773{
3774 unsigned size;
3775
9dac77fa 3776 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3777 if (size == 8)
3778 size = 4;
3779 return size;
3780}
3781
3782static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3783 unsigned size, bool sign_extension)
3784{
39f21ee5
AK		 3785 int rc = X86EMUL_CONTINUE;
3786
3787 op->type = OP_IMM;
3788 op->bytes = size;
9dac77fa 3789 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3790 /* NB. Immediates are sign-extended as necessary. */
3791 switch (op->bytes) {
3792 case 1:
e85a1085 3793 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3794 break;
3795 case 2:
e85a1085 3796 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3797 break;
3798 case 4:
e85a1085 3799 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3800 break;
3801 }
3802 if (!sign_extension) {
3803 switch (op->bytes) {
3804 case 1:
3805 op->val &= 0xff;
3806 break;
3807 case 2:
3808 op->val &= 0xffff;
3809 break;
3810 case 4:
3811 op->val &= 0xffffffff;
3812 break;
3813 }
3814 }
3815done:
3816 return rc;
3817}
3818
a9945549
AK		 3819static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3820 unsigned d)
3821{
3822 int rc = X86EMUL_CONTINUE;
3823
3824 switch (d) {
3825 case OpReg:
2adb5ad9 3826 decode_register_operand(ctxt, op);
a9945549
AK		 3827 break;
3828 case OpImmUByte:
608aabe3 3829 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3830 break;
3831 case OpMem:
41ddf978 3832 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3833 mem_common:
3834 *op = ctxt->memop;
3835 ctxt->memopp = op;
3836 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3837 fetch_bit_operand(ctxt);
3838 op->orig_val = op->val;
3839 break;
41ddf978
AK		 3840 case OpMem64:
3841 ctxt->memop.bytes = 8;
3842 goto mem_common;
a9945549
AK		 3843 case OpAcc:
3844 op->type = OP_REG;
3845 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3846 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3847 fetch_register_operand(op);
3848 op->orig_val = op->val;
3849 break;
3850 case OpDI:
3851 op->type = OP_MEM;
3852 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3853 op->addr.mem.ea =
3854 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3855 op->addr.mem.seg = VCPU_SREG_ES;
3856 op->val = 0;
3857 break;
3858 case OpDX:
3859 op->type = OP_REG;
3860 op->bytes = 2;
3861 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3862 fetch_register_operand(op);
3863 break;
4dd6a57d
AK		 3864 case OpCL:
3865 op->bytes = 1;
3866 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3867 break;
3868 case OpImmByte:
3869 rc = decode_imm(ctxt, op, 1, true);
3870 break;
3871 case OpOne:
3872 op->bytes = 1;
3873 op->val = 1;
3874 break;
3875 case OpImm:
3876 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3877 break;
28867cee
AK		 3878 case OpMem8:
3879 ctxt->memop.bytes = 1;
3880 goto mem_common;
0fe59128
AK		 3881 case OpMem16:
3882 ctxt->memop.bytes = 2;
3883 goto mem_common;
3884 case OpMem32:
3885 ctxt->memop.bytes = 4;
3886 goto mem_common;
3887 case OpImmU16:
3888 rc = decode_imm(ctxt, op, 2, false);
3889 break;
3890 case OpImmU:
3891 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3892 break;
3893 case OpSI:
3894 op->type = OP_MEM;
3895 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3896 op->addr.mem.ea =
3897 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3898 op->addr.mem.seg = seg_override(ctxt);
3899 op->val = 0;
3900 break;
3901 case OpImmFAddr:
3902 op->type = OP_IMM;
3903 op->addr.mem.ea = ctxt->_eip;
3904 op->bytes = ctxt->op_bytes + 2;
3905 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3906 break;
3907 case OpMemFAddr:
3908 ctxt->memop.bytes = ctxt->op_bytes + 2;
3909 goto mem_common;
c191a7a0
AK		 3910 case OpES:
3911 op->val = VCPU_SREG_ES;
3912 break;
3913 case OpCS:
3914 op->val = VCPU_SREG_CS;
3915 break;
3916 case OpSS:
3917 op->val = VCPU_SREG_SS;
3918 break;
3919 case OpDS:
3920 op->val = VCPU_SREG_DS;
3921 break;
3922 case OpFS:
3923 op->val = VCPU_SREG_FS;
3924 break;
3925 case OpGS:
3926 op->val = VCPU_SREG_GS;
3927 break;
a9945549
AK		 3928 case OpImplicit:
3929 /* Special instructions do their own operand decoding. */
3930 default:
3931 op->type = OP_NONE; /* Disable writeback. */
3932 break;
3933 }
3934
3935done:
3936 return rc;
3937}
3938
ef5d75cc 3939int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3940{
dde7e6d1
AK		 3941 int rc = X86EMUL_CONTINUE;
3942 int mode = ctxt->mode;
46561646 3943 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3944 bool op_prefix = false;
46561646 3945 struct opcode opcode;
dde7e6d1 3946
f09ed83e
AK		 3947 ctxt->memop.type = OP_NONE;
3948 ctxt->memopp = NULL;
9dac77fa
AK		 3949 ctxt->_eip = ctxt->eip;
3950 ctxt->fetch.start = ctxt->_eip;
3951 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3952 if (insn_len > 0)
9dac77fa 3953 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3954
3955 switch (mode) {
3956 case X86EMUL_MODE_REAL:
3957 case X86EMUL_MODE_VM86:
3958 case X86EMUL_MODE_PROT16:
3959 def_op_bytes = def_ad_bytes = 2;
3960 break;
3961 case X86EMUL_MODE_PROT32:
3962 def_op_bytes = def_ad_bytes = 4;
3963 break;
3964#ifdef CONFIG_X86_64
3965 case X86EMUL_MODE_PROT64:
3966 def_op_bytes = 4;
3967 def_ad_bytes = 8;
3968 break;
3969#endif
3970 default:
1d2887e2 3971 return EMULATION_FAILED;
dde7e6d1
AK		 3972 }
3973
9dac77fa
AK		 3974 ctxt->op_bytes = def_op_bytes;
3975 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3976
3977 /* Legacy prefixes. */
3978 for (;;) {
e85a1085 3979 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3980 case 0x66: /* operand-size override */
0d7cdee8 3981 op_prefix = true;
dde7e6d1 3982 /* switch between 2/4 bytes */
9dac77fa 3983 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3984 break;
3985 case 0x67: /* address-size override */
3986 if (mode == X86EMUL_MODE_PROT64)
3987 /* switch between 4/8 bytes */
9dac77fa 3988 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3989 else
3990 /* switch between 2/4 bytes */
9dac77fa 3991 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3992 break;
3993 case 0x26: /* ES override */
3994 case 0x2e: /* CS override */
3995 case 0x36: /* SS override */
3996 case 0x3e: /* DS override */
9dac77fa 3997 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3998 break;
3999 case 0x64: /* FS override */
4000 case 0x65: /* GS override */
9dac77fa 4001 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4002 break;
4003 case 0x40 ... 0x4f: /* REX */
4004 if (mode != X86EMUL_MODE_PROT64)
4005 goto done_prefixes;
9dac77fa 4006 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4007 continue;
4008 case 0xf0: /* LOCK */
9dac77fa 4009 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4010 break;
4011 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4012 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4013 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4014 break;
4015 default:
4016 goto done_prefixes;
4017 }
4018
4019 /* Any legacy prefix after a REX prefix nullifies its effect. */
4020
9dac77fa 4021 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4022 }
4023
4024done_prefixes:
4025
4026 /* REX prefix. */
9dac77fa
AK		 4027 if (ctxt->rex_prefix & 8)
4028 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4029
4030 /* Opcode byte(s). */
9dac77fa 4031 opcode = opcode_table[ctxt->b];
d3ad6243 4032 /* Two-byte opcode? */
9dac77fa
AK		 4033 if (ctxt->b == 0x0f) {
4034 ctxt->twobyte = 1;
e85a1085 4035 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4036 opcode = twobyte_table[ctxt->b];
dde7e6d1 4037 }
9dac77fa 4038 ctxt->d = opcode.flags;
dde7e6d1 4039
9f4260e7
TY		 4040 if (ctxt->d & ModRM)
4041 ctxt->modrm = insn_fetch(u8, ctxt);
4042
9dac77fa
AK		 4043 while (ctxt->d & GroupMask) {
4044 switch (ctxt->d & GroupMask) {
46561646 4045 case Group:
9dac77fa 4046 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4047 opcode = opcode.u.group[goffset];
4048 break;
4049 case GroupDual:
9dac77fa
AK		 4050 goffset = (ctxt->modrm >> 3) & 7;
4051 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4052 opcode = opcode.u.gdual->mod3[goffset];
4053 else
4054 opcode = opcode.u.gdual->mod012[goffset];
4055 break;
4056 case RMExt:
9dac77fa 4057 goffset = ctxt->modrm & 7;
01de8b09 4058 opcode = opcode.u.group[goffset];
46561646
AK		 4059 break;
4060 case Prefix:
9dac77fa 4061 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4062 return EMULATION_FAILED;
9dac77fa 4063 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4064 switch (simd_prefix) {
4065 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4066 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4067 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4068 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4069 }
4070 break;
4071 default:
1d2887e2 4072 return EMULATION_FAILED;
0d7cdee8 4073 }
46561646 4074
b1ea50b2 4075 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4076 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4077 }
4078
9dac77fa
AK		 4079 ctxt->execute = opcode.u.execute;
4080 ctxt->check_perm = opcode.check_perm;
4081 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4082
4083 /* Unrecognised? */
9dac77fa 4084 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4085 return EMULATION_FAILED;
dde7e6d1 4086
9dac77fa 4087 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4088 return EMULATION_FAILED;
d867162c 4089
9dac77fa
AK		 4090 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4091 ctxt->op_bytes = 8;
dde7e6d1 4092
9dac77fa 4093 if (ctxt->d & Op3264) {
7f9b4b75 4094 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4095 ctxt->op_bytes = 8;
7f9b4b75 4096 else
9dac77fa 4097 ctxt->op_bytes = 4;
7f9b4b75
AK		 4098 }
4099
9dac77fa
AK		 4100 if (ctxt->d & Sse)
4101 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4102 else if (ctxt->d & Mmx)
4103 ctxt->op_bytes = 8;
1253791d 4104
dde7e6d1 4105 /* ModRM and SIB bytes. */
9dac77fa 4106 if (ctxt->d & ModRM) {
f09ed83e 4107 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4108 if (!ctxt->has_seg_override)
4109 set_seg_override(ctxt, ctxt->modrm_seg);
4110 } else if (ctxt->d & MemAbs)
f09ed83e 4111 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4112 if (rc != X86EMUL_CONTINUE)
4113 goto done;
4114
9dac77fa
AK		 4115 if (!ctxt->has_seg_override)
4116 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4117
f09ed83e 4118 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4119
f09ed83e
AK		 4120 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4121 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4122
dde7e6d1
AK		 4123 /*
4124 * Decode and fetch the source operand: register, memory
4125 * or immediate.
4126 */
0fe59128 4127 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4128 if (rc != X86EMUL_CONTINUE)
4129 goto done;
4130
dde7e6d1
AK		 4131 /*
4132 * Decode and fetch the second source operand: register, memory
4133 * or immediate.
4134 */
4dd6a57d 4135 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4136 if (rc != X86EMUL_CONTINUE)
4137 goto done;
4138
dde7e6d1 4139 /* Decode and fetch the destination operand: register or memory. */
a9945549 4140 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4141
4142done:
f09ed83e
AK		 4143 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4144 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4145
1d2887e2 4146 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4147}
4148
1cb3f3ae
XG		 4149bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4150{
4151 return ctxt->d & PageTable;
4152}
4153
3e2f65d5
GN		 4154static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4155{
3e2f65d5
GN		 4156 /* The second termination condition only applies for REPE
4157 * and REPNE. Test if the repeat string operation prefix is
4158 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4159 * corresponding termination condition according to:
4160 * - if REPE/REPZ and ZF = 0 then done
4161 * - if REPNE/REPNZ and ZF = 1 then done
4162 */
9dac77fa
AK		 4163 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4164 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4165 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4166 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4167 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4168 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4169 return true;
4170
4171 return false;
4172}
4173
cbe2c9d3
AK		 4174static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4175{
4176 bool fault = false;
4177
4178 ctxt->ops->get_fpu(ctxt);
4179 asm volatile("1: fwait \n\t"
4180 "2: \n\t"
4181 ".pushsection .fixup,\"ax\" \n\t"
4182 "3: \n\t"
4183 "movb $1, %[fault] \n\t"
4184 "jmp 2b \n\t"
4185 ".popsection \n\t"
4186 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4187 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4188 ctxt->ops->put_fpu(ctxt);
4189
4190 if (unlikely(fault))
4191 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4192
4193 return X86EMUL_CONTINUE;
4194}
4195
4196static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4197 struct operand *op)
4198{
4199 if (op->type == OP_MM)
4200 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4201}
4202
7b105ca2 4203int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4204{
9aabc88f 4205 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4206 int rc = X86EMUL_CONTINUE;
9dac77fa 4207 int saved_dst_type = ctxt->dst.type;
8b4caf66 4208
9dac77fa 4209 ctxt->mem_read.pos = 0;
310b5d30 4210
9dac77fa 4211 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4212 rc = emulate_ud(ctxt);
1161624f
GN		 4213 goto done;
4214 }
4215
d380a5e4 4216 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4217 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4218 rc = emulate_ud(ctxt);
d380a5e4
GN		 4219 goto done;
4220 }
4221
9dac77fa 4222 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4223 rc = emulate_ud(ctxt);
081bca0e
AK		 4224 goto done;
4225 }
4226
cbe2c9d3
AK		 4227 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4228 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4229 rc = emulate_ud(ctxt);
4230 goto done;
4231 }
4232
cbe2c9d3 4233 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4234 rc = emulate_nm(ctxt);
4235 goto done;
4236 }
4237
cbe2c9d3
AK		 4238 if (ctxt->d & Mmx) {
4239 rc = flush_pending_x87_faults(ctxt);
4240 if (rc != X86EMUL_CONTINUE)
4241 goto done;
4242 /*
4243 * Now that we know the fpu is exception safe, we can fetch
4244 * operands from it.
4245 */
4246 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4247 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4248 if (!(ctxt->d & Mov))
4249 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4250 }
4251
9dac77fa
AK		 4252 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4253 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4254 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4255 if (rc != X86EMUL_CONTINUE)
4256 goto done;
4257 }
4258
e92805ac 4259 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4260 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4261 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4262 goto done;
4263 }
4264
8ea7d6ae 4265 /* Instruction can only be executed in protected mode */
9dac77fa 4266 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4267 rc = emulate_ud(ctxt);
4268 goto done;
4269 }
4270
d09beabd 4271 /* Do instruction specific permission checks */
9dac77fa
AK		 4272 if (ctxt->check_perm) {
4273 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4274 if (rc != X86EMUL_CONTINUE)
4275 goto done;
4276 }
4277
9dac77fa
AK		 4278 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4279 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4280 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4281 if (rc != X86EMUL_CONTINUE)
4282 goto done;
4283 }
4284
9dac77fa 4285 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4286 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4287 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4288 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4289 goto done;
4290 }
b9fa9d6b
AK		 4291 }
4292
9dac77fa
AK		 4293 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4294 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4295 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4296 if (rc != X86EMUL_CONTINUE)
8b4caf66 4297 goto done;
9dac77fa 4298 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4299 }
4300
9dac77fa
AK		 4301 if (ctxt->src2.type == OP_MEM) {
4302 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4303 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4304 if (rc != X86EMUL_CONTINUE)
4305 goto done;
4306 }
4307
9dac77fa 4308 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4309 goto special_insn;
4310
4311
9dac77fa 4312 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4313 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4314 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4315 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4316 if (rc != X86EMUL_CONTINUE)
4317 goto done;
038e51de 4318 }
9dac77fa 4319 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4320
018a98db
AK		 4321special_insn:
4322
9dac77fa
AK		 4323 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4324 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4325 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4326 if (rc != X86EMUL_CONTINUE)
4327 goto done;
4328 }
4329
9dac77fa
AK		 4330 if (ctxt->execute) {
4331 rc = ctxt->execute(ctxt);
ef65c889
AK		 4332 if (rc != X86EMUL_CONTINUE)
4333 goto done;
4334 goto writeback;
4335 }
4336
9dac77fa 4337 if (ctxt->twobyte)
6aa8b732
AK		 4338 goto twobyte_insn;
4339
9dac77fa 4340 switch (ctxt->b) {
33615aa9 4341 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4342 emulate_1op(ctxt, "inc");
33615aa9
AK		 4343 break;
4344 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4345 emulate_1op(ctxt, "dec");
33615aa9 4346 break;
6aa8b732 4347 case 0x63: /* movsxd */
8b4caf66 4348 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4349 goto cannot_emulate;
9dac77fa 4350 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4351 break;
b2833e3c 4352 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4353 if (test_cc(ctxt->b, ctxt->eflags))
4354 jmp_rel(ctxt, ctxt->src.val);
018a98db 4355 break;
7e0b54b1 4356 case 0x8d: /* lea r16/r32, m */
9dac77fa 4357 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4358 break;
3d9e77df 4359 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4360 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4361 break;
e4f973ae
TY		 4362 rc = em_xchg(ctxt);
4363 break;
e8b6fa70 4364 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4365 switch (ctxt->op_bytes) {
4366 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4367 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4368 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4369 }
4370 break;
018a98db 4371 case 0xc0 ... 0xc1:
51187683 4372 rc = em_grp2(ctxt);
018a98db 4373 break;
6e154e56 4374 case 0xcc: /* int3 */
5c5df76b
TY		 4375 rc = emulate_int(ctxt, 3);
4376 break;
6e154e56 4377 case 0xcd: /* int n */
9dac77fa 4378 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4379 break;
4380 case 0xce: /* into */
5c5df76b
TY		 4381 if (ctxt->eflags & EFLG_OF)
4382 rc = emulate_int(ctxt, 4);
6e154e56 4383 break;
018a98db 4384 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4385 rc = em_grp2(ctxt);
018a98db
AK		 4386 break;
4387 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4388 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4389 rc = em_grp2(ctxt);
018a98db 4390 break;
1a52e051 4391 case 0xe9: /* jmp rel */
db5b0762 4392 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4393 jmp_rel(ctxt, ctxt->src.val);
4394 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4395 break;
111de5d6 4396 case 0xf4: /* hlt */
6c3287f7 4397 ctxt->ops->halt(ctxt);
19fdfa0d 4398 break;
111de5d6
AK		 4399 case 0xf5: /* cmc */
4400 /* complement carry flag from eflags reg */
4401 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4402 break;
4403 case 0xf8: /* clc */
4404 ctxt->eflags &= ~EFLG_CF;
111de5d6 4405 break;
8744aa9a
MG		 4406 case 0xf9: /* stc */
4407 ctxt->eflags |= EFLG_CF;
4408 break;
fb4616f4
MG		 4409 case 0xfc: /* cld */
4410 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4411 break;
4412 case 0xfd: /* std */
4413 ctxt->eflags |= EFLG_DF;
fb4616f4 4414 break;
91269b8f
AK		 4415 default:
4416 goto cannot_emulate;
6aa8b732 4417 }
018a98db 4418
7d9ddaed
AK		 4419 if (rc != X86EMUL_CONTINUE)
4420 goto done;
4421
018a98db 4422writeback:
adddcecf 4423 rc = writeback(ctxt);
1b30eaa8 4424 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4425 goto done;
4426
5cd21917
GN		 4427 /*
4428 * restore dst type in case the decoding will be reused
4429 * (happens for string instruction )
4430 */
9dac77fa 4431 ctxt->dst.type = saved_dst_type;
5cd21917 4432
9dac77fa
AK		 4433 if ((ctxt->d & SrcMask) == SrcSI)
4434 string_addr_inc(ctxt, seg_override(ctxt),
4435 VCPU_REGS_RSI, &ctxt->src);
a682e354 4436
9dac77fa 4437 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4438 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4439 &ctxt->dst);
d9271123 4440
9dac77fa
AK		 4441 if (ctxt->rep_prefix && (ctxt->d & String)) {
4442 struct read_cache *r = &ctxt->io_read;
4443 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4444
d2ddd1c4
GN		 4445 if (!string_insn_completed(ctxt)) {
4446 /*
4447 * Re-enter guest when pio read ahead buffer is empty
4448 * or, if it is not used, after each 1024 iteration.
4449 */
9dac77fa 4450 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4451 (r->end == 0 || r->end != r->pos)) {
4452 /*
4453 * Reset read cache. Usually happens before
4454 * decode, but since instruction is restarted
4455 * we have to do it here.
4456 */
9dac77fa 4457 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4458 return EMULATION_RESTART;
4459 }
4460 goto done; /* skip rip writeback */
0fa6ccbd 4461 }
5cd21917 4462 }
d2ddd1c4 4463
9dac77fa 4464 ctxt->eip = ctxt->_eip;
018a98db
AK		 4465
4466done:
da9cb575
AK		 4467 if (rc == X86EMUL_PROPAGATE_FAULT)
4468 ctxt->have_exception = true;
775fde86
JR		 4469 if (rc == X86EMUL_INTERCEPTED)
4470 return EMULATION_INTERCEPTED;
4471
d2ddd1c4 4472 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4473
4474twobyte_insn:
9dac77fa 4475 switch (ctxt->b) {
018a98db 4476 case 0x09: /* wbinvd */
cfb22375 4477 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4478 break;
4479 case 0x08: /* invd */
018a98db
AK		 4480 case 0x0d: /* GrpP (prefetch) */
4481 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4482 break;
4483 case 0x20: /* mov cr, reg */
9dac77fa 4484 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4485 break;
6aa8b732 4486 case 0x21: /* mov from dr to reg */
9dac77fa 4487 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4488 break;
6aa8b732 4489 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4490 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4491 if (!test_cc(ctxt->b, ctxt->eflags))
4492 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4493 break;
b2833e3c 4494 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4495 if (test_cc(ctxt->b, ctxt->eflags))
4496 jmp_rel(ctxt, ctxt->src.val);
018a98db 4497 break;
ee45b58e 4498 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4499 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4500 break;
9bf8ea42
GT		 4501 case 0xa4: /* shld imm8, r, r/m */
4502 case 0xa5: /* shld cl, r, r/m */
761441b9 4503 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4504 break;
9bf8ea42
GT		 4505 case 0xac: /* shrd imm8, r, r/m */
4506 case 0xad: /* shrd cl, r, r/m */
761441b9 4507 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4508 break;
2a7c5b8b
GC		 4509 case 0xae: /* clflush */
4510 break;
6aa8b732 4511 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4512 ctxt->dst.bytes = ctxt->op_bytes;
4513 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4514 : (u16) ctxt->src.val;
6aa8b732 4515 break;
6aa8b732 4516 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4517 ctxt->dst.bytes = ctxt->op_bytes;
4518 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4519 (s16) ctxt->src.val;
6aa8b732 4520 break;
92f738a5 4521 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4522 emulate_2op_SrcV(ctxt, "add");
92f738a5 4523 /* Write back the register source. */
9dac77fa
AK		 4524 ctxt->src.val = ctxt->dst.orig_val;
4525 write_register_operand(&ctxt->src);
92f738a5 4526 break;
a012e65a 4527 case 0xc3: /* movnti */
9dac77fa
AK		 4528 ctxt->dst.bytes = ctxt->op_bytes;
4529 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4530 (u64) ctxt->src.val;
a012e65a 4531 break;
91269b8f
AK		 4532 default:
4533 goto cannot_emulate;
6aa8b732 4534 }
7d9ddaed
AK		 4535
4536 if (rc != X86EMUL_CONTINUE)
4537 goto done;
4538
6aa8b732
AK		 4539 goto writeback;
4540
4541cannot_emulate:
a0c0ab2f 4542 return EMULATION_FAILED;
6aa8b732 4543}
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