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KVM: x86: Revert NoBigReal patch in the emulator
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 169#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 170#define No16 ((u64)1 << 53) /* No 16 bit operand */
6aa8b732 171
820207c8 172#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 173
d0e53325
AK		 174#define X2(x...) x, x
175#define X3(x...) X2(x), x
176#define X4(x...) X2(x), X2(x)
177#define X5(x...) X4(x), x
178#define X6(x...) X4(x), X2(x)
179#define X7(x...) X4(x), X3(x)
180#define X8(x...) X4(x), X4(x)
181#define X16(x...) X8(x), X8(x)
83babbca 182
e28bbd44
AK		 183#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
184#define FASTOP_SIZE 8
185
186/*
187 * fastop functions have a special calling convention:
188 *
017da7b6
AK		 189 * dst: rax (in/out)
190 * src: rdx (in/out)
e28bbd44
AK		 191 * src2: rcx (in)
192 * flags: rflags (in/out)
b8c0b6ae 193 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 194 *
195 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
196 * different operand sizes can be reached by calculation, rather than a jump
197 * table (which would be bigger than the code).
198 *
199 * fastop functions are declared as taking a never-defined fastop parameter,
200 * so they can't be called from C directly.
201 */
202
203struct fastop;
204
d65b1dee 205struct opcode {
b1ea50b2
AK		 206 u64 flags : 56;
207 u64 intercept : 8;
120df890 208 union {
ef65c889 209 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 210 const struct opcode *group;
211 const struct group_dual *gdual;
212 const struct gprefix *gprefix;
045a282c 213 const struct escape *esc;
e28bbd44 214 void (*fastop)(struct fastop *fake);
120df890 215 } u;
d09beabd 216 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 217};
218
219struct group_dual {
220 struct opcode mod012[8];
221 struct opcode mod3[8];
d65b1dee
AK		 222};
223
0d7cdee8
AK		 224struct gprefix {
225 struct opcode pfx_no;
226 struct opcode pfx_66;
227 struct opcode pfx_f2;
228 struct opcode pfx_f3;
229};
230
045a282c
GN		 231struct escape {
232 struct opcode op[8];
233 struct opcode high[64];
234};
235
6aa8b732 236/* EFLAGS bit definitions. */
d4c6a154
GN		 237#define EFLG_ID (1<<21)
238#define EFLG_VIP (1<<20)
239#define EFLG_VIF (1<<19)
240#define EFLG_AC (1<<18)
b1d86143
AP		 241#define EFLG_VM (1<<17)
242#define EFLG_RF (1<<16)
d4c6a154
GN		 243#define EFLG_IOPL (3<<12)
244#define EFLG_NT (1<<14)
6aa8b732
AK		 245#define EFLG_OF (1<<11)
246#define EFLG_DF (1<<10)
b1d86143 247#define EFLG_IF (1<<9)
d4c6a154 248#define EFLG_TF (1<<8)
6aa8b732
AK		 249#define EFLG_SF (1<<7)
250#define EFLG_ZF (1<<6)
251#define EFLG_AF (1<<4)
252#define EFLG_PF (1<<2)
253#define EFLG_CF (1<<0)
254
62bd430e
MG		 255#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
256#define EFLG_RESERVED_ONE_MASK 2
257
dd856efa
AK		 258static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
259{
260 if (!(ctxt->regs_valid & (1 << nr))) {
261 ctxt->regs_valid |= 1 << nr;
262 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
263 }
264 return ctxt->_regs[nr];
265}
266
267static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
268{
269 ctxt->regs_valid |= 1 << nr;
270 ctxt->regs_dirty |= 1 << nr;
271 return &ctxt->_regs[nr];
272}
273
274static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 reg_read(ctxt, nr);
277 return reg_write(ctxt, nr);
278}
279
280static void writeback_registers(struct x86_emulate_ctxt *ctxt)
281{
282 unsigned reg;
283
284 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
285 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
286}
287
288static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
289{
290 ctxt->regs_dirty = 0;
291 ctxt->regs_valid = 0;
292}
293
6aa8b732
AK		 294/*
295 * These EFLAGS bits are restored from saved value during emulation, and
296 * any changes are written back to the saved value after emulation.
297 */
298#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
299
dda96d8f
AK		 300#ifdef CONFIG_X86_64
301#define ON64(x) x
302#else
303#define ON64(x)
304#endif
305
4d758349
AK		 306static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
307
b7d491e7
AK		 308#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
309#define FOP_RET "ret \n\t"
310
311#define FOP_START(op) \
312 extern void em_##op(struct fastop *fake); \
313 asm(".pushsection .text, \"ax\" \n\t" \
314 ".global em_" #op " \n\t" \
315 FOP_ALIGN \
316 "em_" #op ": \n\t"
317
318#define FOP_END \
319 ".popsection")
320
0bdea068
AK		 321#define FOPNOP() FOP_ALIGN FOP_RET
322
b7d491e7 323#define FOP1E(op, dst) \
b8c0b6ae
AK		 324 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
325
326#define FOP1EEX(op, dst) \
327 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 328
329#define FASTOP1(op) \
330 FOP_START(op) \
331 FOP1E(op##b, al) \
332 FOP1E(op##w, ax) \
333 FOP1E(op##l, eax) \
334 ON64(FOP1E(op##q, rax)) \
335 FOP_END
336
b9fa409b
AK		 337/* 1-operand, using src2 (for MUL/DIV r/m) */
338#define FASTOP1SRC2(op, name) \
339 FOP_START(name) \
340 FOP1E(op, cl) \
341 FOP1E(op, cx) \
342 FOP1E(op, ecx) \
343 ON64(FOP1E(op, rcx)) \
344 FOP_END
345
b8c0b6ae
AK		 346/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
347#define FASTOP1SRC2EX(op, name) \
348 FOP_START(name) \
349 FOP1EEX(op, cl) \
350 FOP1EEX(op, cx) \
351 FOP1EEX(op, ecx) \
352 ON64(FOP1EEX(op, rcx)) \
353 FOP_END
354
f7857f35
AK		 355#define FOP2E(op, dst, src) \
356 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
357
358#define FASTOP2(op) \
359 FOP_START(op) \
017da7b6
AK		 360 FOP2E(op##b, al, dl) \
361 FOP2E(op##w, ax, dx) \
362 FOP2E(op##l, eax, edx) \
363 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 364 FOP_END
365
11c363ba
AK		 366/* 2 operand, word only */
367#define FASTOP2W(op) \
368 FOP_START(op) \
369 FOPNOP() \
017da7b6
AK		 370 FOP2E(op##w, ax, dx) \
371 FOP2E(op##l, eax, edx) \
372 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 373 FOP_END
374
007a3b54
AK		 375/* 2 operand, src is CL */
376#define FASTOP2CL(op) \
377 FOP_START(op) \
378 FOP2E(op##b, al, cl) \
379 FOP2E(op##w, ax, cl) \
380 FOP2E(op##l, eax, cl) \
381 ON64(FOP2E(op##q, rax, cl)) \
382 FOP_END
383
5aca3722
NA		 384/* 2 operand, src and dest are reversed */
385#define FASTOP2R(op, name) \
386 FOP_START(name) \
387 FOP2E(op##b, dl, al) \
388 FOP2E(op##w, dx, ax) \
389 FOP2E(op##l, edx, eax) \
390 ON64(FOP2E(op##q, rdx, rax)) \
391 FOP_END
392
0bdea068
AK		 393#define FOP3E(op, dst, src, src2) \
394 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
395
396/* 3-operand, word-only, src2=cl */
397#define FASTOP3WCL(op) \
398 FOP_START(op) \
399 FOPNOP() \
017da7b6
AK		 400 FOP3E(op##w, ax, dx, cl) \
401 FOP3E(op##l, eax, edx, cl) \
402 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 403 FOP_END
404
9ae9feba
AK		 405/* Special case for SETcc - 1 instruction per cc */
406#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
407
b8c0b6ae
AK		 408asm(".global kvm_fastop_exception \n"
409 "kvm_fastop_exception: xor %esi, %esi; ret");
410
9ae9feba
AK		 411FOP_START(setcc)
412FOP_SETCC(seto)
413FOP_SETCC(setno)
414FOP_SETCC(setc)
415FOP_SETCC(setnc)
416FOP_SETCC(setz)
417FOP_SETCC(setnz)
418FOP_SETCC(setbe)
419FOP_SETCC(setnbe)
420FOP_SETCC(sets)
421FOP_SETCC(setns)
422FOP_SETCC(setp)
423FOP_SETCC(setnp)
424FOP_SETCC(setl)
425FOP_SETCC(setnl)
426FOP_SETCC(setle)
427FOP_SETCC(setnle)
428FOP_END;
429
326f578f
PB		 430FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
431FOP_END;
432
8a76d7f2
JR		 433static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
434 enum x86_intercept intercept,
435 enum x86_intercept_stage stage)
436{
437 struct x86_instruction_info info = {
438 .intercept = intercept,
9dac77fa
AK		 439 .rep_prefix = ctxt->rep_prefix,
440 .modrm_mod = ctxt->modrm_mod,
441 .modrm_reg = ctxt->modrm_reg,
442 .modrm_rm = ctxt->modrm_rm,
443 .src_val = ctxt->src.val64,
6cbc5f5a 444 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 445 .src_bytes = ctxt->src.bytes,
446 .dst_bytes = ctxt->dst.bytes,
447 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 448 .next_rip = ctxt->eip,
449 };
450
2953538e 451 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 452}
453
f47cfa31
AK		 454static void assign_masked(ulong *dest, ulong src, ulong mask)
455{
456 *dest = (*dest & ~mask) | (src & mask);
457}
458
9dac77fa 459static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 460{
9dac77fa 461 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 462}
463
f47cfa31
AK		 464static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
465{
466 u16 sel;
467 struct desc_struct ss;
468
469 if (ctxt->mode == X86EMUL_MODE_PROT64)
470 return ~0UL;
471 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
472 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
473}
474
612e89f0
AK		 475static int stack_size(struct x86_emulate_ctxt *ctxt)
476{
477 return (__fls(stack_mask(ctxt)) + 1) >> 3;
478}
479
6aa8b732 480/* Access/update address held in a register, based on addressing mode. */
e4706772 481static inline unsigned long
9dac77fa 482address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 483{
9dac77fa 484 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 485 return reg;
486 else
9dac77fa 487 return reg & ad_mask(ctxt);
e4706772
HH		 488}
489
490static inline unsigned long
9dac77fa 491register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 492{
9dac77fa 493 return address_mask(ctxt, reg);
e4706772
HH		 494}
495
5ad105e5
AK		 496static void masked_increment(ulong *reg, ulong mask, int inc)
497{
498 assign_masked(reg, *reg + inc, mask);
499}
500
7a957275 501static inline void
9dac77fa 502register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 503{
5ad105e5
AK		 504 ulong mask;
505
9dac77fa 506 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 507 mask = ~0UL;
7a957275 508 else
5ad105e5
AK		 509 mask = ad_mask(ctxt);
510 masked_increment(reg, mask, inc);
511}
512
513static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
514{
dd856efa 515 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 516}
6aa8b732 517
56697687
AK		 518static u32 desc_limit_scaled(struct desc_struct *desc)
519{
520 u32 limit = get_desc_limit(desc);
521
522 return desc->g ? (limit << 12) | 0xfff : limit;
523}
524
7b105ca2 525static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 526{
527 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
528 return 0;
529
7b105ca2 530 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 531}
532
35d3d4a1
AK		 533static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
534 u32 error, bool valid)
54b8486f 535{
e0ad0b47 536 WARN_ON(vec > 0x1f);
da9cb575
AK		 537 ctxt->exception.vector = vec;
538 ctxt->exception.error_code = error;
539 ctxt->exception.error_code_valid = valid;
35d3d4a1 540 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 541}
542
3b88e41a
JR		 543static int emulate_db(struct x86_emulate_ctxt *ctxt)
544{
545 return emulate_exception(ctxt, DB_VECTOR, 0, false);
546}
547
35d3d4a1 548static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 549{
35d3d4a1 550 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 551}
552
618ff15d
AK		 553static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
554{
555 return emulate_exception(ctxt, SS_VECTOR, err, true);
556}
557
35d3d4a1 558static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 559{
35d3d4a1 560 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 561}
562
35d3d4a1 563static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 564{
35d3d4a1 565 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 566}
567
34d1f490
AK		 568static int emulate_de(struct x86_emulate_ctxt *ctxt)
569{
35d3d4a1 570 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 571}
572
1253791d
AK		 573static int emulate_nm(struct x86_emulate_ctxt *ctxt)
574{
575 return emulate_exception(ctxt, NM_VECTOR, 0, false);
576}
577
234f3ce4
NA		 578static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
579 int cs_l)
05c83ec9
NA		 580{
581 switch (ctxt->op_bytes) {
582 case 2:
583 ctxt->_eip = (u16)dst;
584 break;
585 case 4:
586 ctxt->_eip = (u32)dst;
587 break;
cd9b8e2c 588#ifdef CONFIG_X86_64
05c83ec9 589 case 8:
234f3ce4 590 if ((cs_l && is_noncanonical_address(dst)) ||
cd9b8e2c 591 (!cs_l && (dst >> 32) != 0))
234f3ce4 592 return emulate_gp(ctxt, 0);
05c83ec9
NA		 593 ctxt->_eip = dst;
594 break;
cd9b8e2c 595#endif
05c83ec9
NA		 596 default:
597 WARN(1, "unsupported eip assignment size\n");
598 }
234f3ce4
NA		 599 return X86EMUL_CONTINUE;
600}
601
602static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
603{
604 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
05c83ec9
NA		 605}
606
234f3ce4 607static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
05c83ec9 608{
234f3ce4 609 return assign_eip_near(ctxt, ctxt->_eip + rel);
05c83ec9
NA		 610}
611
1aa36616
AK		 612static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
613{
614 u16 selector;
615 struct desc_struct desc;
616
617 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
618 return selector;
619}
620
621static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
622 unsigned seg)
623{
624 u16 dummy;
625 u32 base3;
626 struct desc_struct desc;
627
628 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
629 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
630}
631
1c11b376
AK		 632/*
633 * x86 defines three classes of vector instructions: explicitly
634 * aligned, explicitly unaligned, and the rest, which change behaviour
635 * depending on whether they're AVX encoded or not.
636 *
637 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
638 * subject to the same check.
639 */
640static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
641{
642 if (likely(size < 16))
643 return false;
644
645 if (ctxt->d & Aligned)
646 return true;
647 else if (ctxt->d & Unaligned)
648 return false;
649 else if (ctxt->d & Avx)
650 return false;
651 else
652 return true;
653}
654
d09155d2
PB		 655static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
656 struct segmented_address addr,
657 unsigned *max_size, unsigned size,
658 bool write, bool fetch,
659 ulong *linear)
52fd8b44 660{
618ff15d
AK		 661 struct desc_struct desc;
662 bool usable;
52fd8b44 663 ulong la;
618ff15d 664 u32 lim;
1aa36616 665 u16 sel;
3a78a4f4 666 unsigned cpl;
52fd8b44 667
518547b3
NA		 668 la = seg_base(ctxt, addr.seg) +
669 (fetch || ctxt->ad_bytes == 8 ? addr.ea : (u32)addr.ea);
fd56e154 670 *max_size = 0;
618ff15d 671 switch (ctxt->mode) {
618ff15d 672 case X86EMUL_MODE_PROT64:
4be4de7e 673 if (is_noncanonical_address(la))
618ff15d 674 return emulate_gp(ctxt, 0);
fd56e154
PB		 675
676 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
677 if (size > *max_size)
678 goto bad;
618ff15d
AK		 679 break;
680 default:
1aa36616
AK		 681 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
682 addr.seg);
618ff15d
AK		 683 if (!usable)
684 goto bad;
58b7825b
GN		 685 /* code segment in protected mode or read-only data segment */
686 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
687 || !(desc.type & 2)) && write)
618ff15d
AK		 688 goto bad;
689 /* unreadable code segment */
3d9b938e 690 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 691 goto bad;
692 lim = desc_limit_scaled(&desc);
7d882ffa 693 if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d 694 /* expand-up segment */
fd56e154 695 if (addr.ea > lim)
618ff15d 696 goto bad;
fd56e154 697 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 698 } else {
fc058680 699 /* expand-down segment */
fd56e154 700 if (addr.ea <= lim)
618ff15d
AK		 701 goto bad;
702 lim = desc.d ? 0xffffffff : 0xffff;
fd56e154 703 if (addr.ea > lim)
618ff15d 704 goto bad;
fd56e154 705 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 706 }
fd56e154
PB		 707 if (size > *max_size)
708 goto bad;
717746e3 709 cpl = ctxt->ops->cpl(ctxt);
c49c759f
NA		 710 if (!fetch) {
711 /* data segment or readable code segment */
618ff15d
AK		 712 if (cpl > desc.dpl)
713 goto bad;
714 } else if ((desc.type & 8) && !(desc.type & 4)) {
715 /* nonconforming code segment */
716 if (cpl != desc.dpl)
717 goto bad;
718 } else if ((desc.type & 8) && (desc.type & 4)) {
719 /* conforming code segment */
720 if (cpl < desc.dpl)
721 goto bad;
722 }
723 break;
724 }
518547b3 725 if (ctxt->mode != X86EMUL_MODE_PROT64)
52fd8b44 726 la &= (u32)-1;
1c11b376
AK		 727 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
728 return emulate_gp(ctxt, 0);
52fd8b44
AK		 729 *linear = la;
730 return X86EMUL_CONTINUE;
618ff15d
AK		 731bad:
732 if (addr.seg == VCPU_SREG_SS)
3606189f 733 return emulate_ss(ctxt, 0);
618ff15d 734 else
3606189f 735 return emulate_gp(ctxt, 0);
52fd8b44
AK		 736}
737
3d9b938e
NE		 738static int linearize(struct x86_emulate_ctxt *ctxt,
739 struct segmented_address addr,
740 unsigned size, bool write,
741 ulong *linear)
742{
fd56e154
PB		 743 unsigned max_size;
744 return __linearize(ctxt, addr, &max_size, size, write, false, linear);
3d9b938e
NE		 745}
746
747
3ca3ac4d
AK		 748static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
749 struct segmented_address addr,
750 void *data,
751 unsigned size)
752{
9fa088f4
AK		 753 int rc;
754 ulong linear;
755
83b8795a 756 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 757 if (rc != X86EMUL_CONTINUE)
758 return rc;
0f65dd70 759 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 760}
761
807941b1 762/*
285ca9e9 763 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 764 * boundary if they are not in fetch_cache yet.
765 */
9506d57d 766static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 767{
62266869 768 int rc;
fd56e154 769 unsigned size, max_size;
285ca9e9 770 unsigned long linear;
17052f16 771 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 772 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 773 .ea = ctxt->eip + cur_size };
774
fd56e154
PB		 775 /*
776 * We do not know exactly how many bytes will be needed, and
777 * __linearize is expensive, so fetch as much as possible. We
778 * just have to avoid going beyond the 15 byte limit, the end
779 * of the segment, or the end of the page.
780 *
781 * __linearize is called with size 0 so that it does not do any
782 * boundary check itself. Instead, we use max_size to check
783 * against op_size.
784 */
785 rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
719d5a9b
PB		 786 if (unlikely(rc != X86EMUL_CONTINUE))
787 return rc;
788
fd56e154 789 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 790 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 791
792 /*
793 * One instruction can only straddle two pages,
794 * and one has been loaded at the beginning of
795 * x86_decode_insn. So, if not enough bytes
796 * still, we must have hit the 15-byte boundary.
797 */
798 if (unlikely(size < op_size))
fd56e154
PB		 799 return emulate_gp(ctxt, 0);
800
17052f16 801 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 802 size, &ctxt->exception);
803 if (unlikely(rc != X86EMUL_CONTINUE))
804 return rc;
17052f16 805 ctxt->fetch.end += size;
3e2815e9 806 return X86EMUL_CONTINUE;
62266869
AK		 807}
808
9506d57d
PB		 809static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
810 unsigned size)
62266869 811{
08da44ae
NA		 812 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
813
814 if (unlikely(done_size < size))
815 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 816 else
817 return X86EMUL_CONTINUE;
62266869
AK		 818}
819
67cbc90d 820/* Fetch next part of the instruction being emulated. */
e85a1085 821#define insn_fetch(_type, _ctxt) \
9506d57d 822({ _type _x; \
9506d57d
PB		 823 \
824 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 825 if (rc != X86EMUL_CONTINUE) \
826 goto done; \
9506d57d 827 ctxt->_eip += sizeof(_type); \
17052f16
PB		 828 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
829 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 830 _x; \
67cbc90d
TY		 831})
832
807941b1 833#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 834({ \
9506d57d 835 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 836 if (rc != X86EMUL_CONTINUE) \
837 goto done; \
9506d57d 838 ctxt->_eip += (_size); \
17052f16
PB		 839 memcpy(_arr, ctxt->fetch.ptr, _size); \
840 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 841})
842
1e3c5cb0
RR		 843/*
844 * Given the 'reg' portion of a ModRM byte, and a register block, return a
845 * pointer into the block that addresses the relevant register.
846 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
847 */
dd856efa 848static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 849 int byteop)
6aa8b732
AK		 850{
851 void *p;
aa9ac1a6 852 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 853
6aa8b732 854 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 855 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
856 else
857 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 858 return p;
859}
860
861static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 862 struct segmented_address addr,
6aa8b732
AK		 863 u16 *size, unsigned long *address, int op_bytes)
864{
865 int rc;
866
867 if (op_bytes == 2)
868 op_bytes = 3;
869 *address = 0;
3ca3ac4d 870 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 871 if (rc != X86EMUL_CONTINUE)
6aa8b732 872 return rc;
30b31ab6 873 addr.ea += 2;
3ca3ac4d 874 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 875 return rc;
876}
877
34b77652
AK		 878FASTOP2(add);
879FASTOP2(or);
880FASTOP2(adc);
881FASTOP2(sbb);
882FASTOP2(and);
883FASTOP2(sub);
884FASTOP2(xor);
885FASTOP2(cmp);
886FASTOP2(test);
887
b9fa409b
AK		 888FASTOP1SRC2(mul, mul_ex);
889FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 890FASTOP1SRC2EX(div, div_ex);
891FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 892
34b77652
AK		 893FASTOP3WCL(shld);
894FASTOP3WCL(shrd);
895
896FASTOP2W(imul);
897
898FASTOP1(not);
899FASTOP1(neg);
900FASTOP1(inc);
901FASTOP1(dec);
902
903FASTOP2CL(rol);
904FASTOP2CL(ror);
905FASTOP2CL(rcl);
906FASTOP2CL(rcr);
907FASTOP2CL(shl);
908FASTOP2CL(shr);
909FASTOP2CL(sar);
910
911FASTOP2W(bsf);
912FASTOP2W(bsr);
913FASTOP2W(bt);
914FASTOP2W(bts);
915FASTOP2W(btr);
916FASTOP2W(btc);
917
e47a5f5f
AK		 918FASTOP2(xadd);
919
5aca3722
NA		 920FASTOP2R(cmp, cmp_r);
921
9ae9feba 922static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 923{
9ae9feba
AK		 924 u8 rc;
925 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 926
9ae9feba 927 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 928 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 929 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
930 return rc;
bbe9abbd
NK		 931}
932
91ff3cb4
AK		 933static void fetch_register_operand(struct operand *op)
934{
935 switch (op->bytes) {
936 case 1:
937 op->val = *(u8 *)op->addr.reg;
938 break;
939 case 2:
940 op->val = *(u16 *)op->addr.reg;
941 break;
942 case 4:
943 op->val = *(u32 *)op->addr.reg;
944 break;
945 case 8:
946 op->val = *(u64 *)op->addr.reg;
947 break;
948 }
949}
950
1253791d
AK		 951static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
952{
953 ctxt->ops->get_fpu(ctxt);
954 switch (reg) {
89a87c67
MK		 955 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
956 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
957 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
958 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
959 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
960 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
961 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
962 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 963#ifdef CONFIG_X86_64
89a87c67
MK		 964 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
965 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
966 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
967 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
968 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
969 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
970 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
971 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 972#endif
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
978static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
979 int reg)
980{
981 ctxt->ops->get_fpu(ctxt);
982 switch (reg) {
89a87c67
MK		 983 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
984 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
985 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
986 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
987 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
988 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
989 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
990 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 991#ifdef CONFIG_X86_64
89a87c67
MK		 992 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
993 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
994 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
995 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
996 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
997 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
998 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
999 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1000#endif
1001 default: BUG();
1002 }
1003 ctxt->ops->put_fpu(ctxt);
1004}
1005
cbe2c9d3
AK		 1006static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1007{
1008 ctxt->ops->get_fpu(ctxt);
1009 switch (reg) {
1010 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1011 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1012 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1013 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1014 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1015 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1016 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1017 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1018 default: BUG();
1019 }
1020 ctxt->ops->put_fpu(ctxt);
1021}
1022
1023static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1024{
1025 ctxt->ops->get_fpu(ctxt);
1026 switch (reg) {
1027 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1028 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1029 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1030 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1031 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1032 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1033 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1034 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1035 default: BUG();
1036 }
1037 ctxt->ops->put_fpu(ctxt);
1038}
1039
045a282c
GN		 1040static int em_fninit(struct x86_emulate_ctxt *ctxt)
1041{
1042 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1043 return emulate_nm(ctxt);
1044
1045 ctxt->ops->get_fpu(ctxt);
1046 asm volatile("fninit");
1047 ctxt->ops->put_fpu(ctxt);
1048 return X86EMUL_CONTINUE;
1049}
1050
1051static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1052{
1053 u16 fcw;
1054
1055 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1056 return emulate_nm(ctxt);
1057
1058 ctxt->ops->get_fpu(ctxt);
1059 asm volatile("fnstcw %0": "+m"(fcw));
1060 ctxt->ops->put_fpu(ctxt);
1061
1062 /* force 2 byte destination */
1063 ctxt->dst.bytes = 2;
1064 ctxt->dst.val = fcw;
1065
1066 return X86EMUL_CONTINUE;
1067}
1068
1069static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1070{
1071 u16 fsw;
1072
1073 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1074 return emulate_nm(ctxt);
1075
1076 ctxt->ops->get_fpu(ctxt);
1077 asm volatile("fnstsw %0": "+m"(fsw));
1078 ctxt->ops->put_fpu(ctxt);
1079
1080 /* force 2 byte destination */
1081 ctxt->dst.bytes = 2;
1082 ctxt->dst.val = fsw;
1083
1084 return X86EMUL_CONTINUE;
1085}
1086
1253791d 1087static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1088 struct operand *op)
3c118e24 1089{
9dac77fa 1090 unsigned reg = ctxt->modrm_reg;
33615aa9 1091
9dac77fa
AK		 1092 if (!(ctxt->d & ModRM))
1093 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1094
9dac77fa 1095 if (ctxt->d & Sse) {
1253791d
AK		 1096 op->type = OP_XMM;
1097 op->bytes = 16;
1098 op->addr.xmm = reg;
1099 read_sse_reg(ctxt, &op->vec_val, reg);
1100 return;
1101 }
cbe2c9d3
AK		 1102 if (ctxt->d & Mmx) {
1103 reg &= 7;
1104 op->type = OP_MM;
1105 op->bytes = 8;
1106 op->addr.mm = reg;
1107 return;
1108 }
1253791d 1109
3c118e24 1110 op->type = OP_REG;
6d4d85ec
GN		 1111 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1112 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1113
91ff3cb4 1114 fetch_register_operand(op);
3c118e24
AK		 1115 op->orig_val = op->val;
1116}
1117
a6e3407b
AK		 1118static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1119{
1120 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1121 ctxt->modrm_seg = VCPU_SREG_SS;
1122}
1123
1c73ef66 1124static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1125 struct operand *op)
1c73ef66 1126{
1c73ef66 1127 u8 sib;
02357bdc 1128 int index_reg, base_reg, scale;
3e2815e9 1129 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1130 ulong modrm_ea = 0;
1c73ef66 1131
02357bdc
BD		 1132 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1133 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1134 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1135
02357bdc 1136 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1137 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1138 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1139 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1140
9b88ae99 1141 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1142 op->type = OP_REG;
9dac77fa 1143 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1144 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1145 ctxt->d & ByteOp);
9dac77fa 1146 if (ctxt->d & Sse) {
1253791d
AK		 1147 op->type = OP_XMM;
1148 op->bytes = 16;
9dac77fa
AK		 1149 op->addr.xmm = ctxt->modrm_rm;
1150 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1151 return rc;
1152 }
cbe2c9d3
AK		 1153 if (ctxt->d & Mmx) {
1154 op->type = OP_MM;
1155 op->bytes = 8;
bdc90722 1156 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1157 return rc;
1158 }
2dbd0dd7 1159 fetch_register_operand(op);
1c73ef66
AK		 1160 return rc;
1161 }
1162
2dbd0dd7
AK		 1163 op->type = OP_MEM;
1164
9dac77fa 1165 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1166 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1167 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1168 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1169 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1170
1171 /* 16-bit ModR/M decode. */
9dac77fa 1172 switch (ctxt->modrm_mod) {
1c73ef66 1173 case 0:
9dac77fa 1174 if (ctxt->modrm_rm == 6)
e85a1085 1175 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1176 break;
1177 case 1:
e85a1085 1178 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1179 break;
1180 case 2:
e85a1085 1181 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1182 break;
1183 }
9dac77fa 1184 switch (ctxt->modrm_rm) {
1c73ef66 1185 case 0:
2dbd0dd7 1186 modrm_ea += bx + si;
1c73ef66
AK		 1187 break;
1188 case 1:
2dbd0dd7 1189 modrm_ea += bx + di;
1c73ef66
AK		 1190 break;
1191 case 2:
2dbd0dd7 1192 modrm_ea += bp + si;
1c73ef66
AK		 1193 break;
1194 case 3:
2dbd0dd7 1195 modrm_ea += bp + di;
1c73ef66
AK		 1196 break;
1197 case 4:
2dbd0dd7 1198 modrm_ea += si;
1c73ef66
AK		 1199 break;
1200 case 5:
2dbd0dd7 1201 modrm_ea += di;
1c73ef66
AK		 1202 break;
1203 case 6:
9dac77fa 1204 if (ctxt->modrm_mod != 0)
2dbd0dd7 1205 modrm_ea += bp;
1c73ef66
AK		 1206 break;
1207 case 7:
2dbd0dd7 1208 modrm_ea += bx;
1c73ef66
AK		 1209 break;
1210 }
9dac77fa
AK		 1211 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1212 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1213 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1214 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1215 } else {
1216 /* 32/64-bit ModR/M decode. */
9dac77fa 1217 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1218 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1219 index_reg |= (sib >> 3) & 7;
1220 base_reg |= sib & 7;
1221 scale = sib >> 6;
1222
9dac77fa 1223 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1224 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1225 else {
dd856efa 1226 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1227 adjust_modrm_seg(ctxt, base_reg);
1228 }
dc71d0f1 1229 if (index_reg != 4)
dd856efa 1230 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1231 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1232 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1233 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1234 ctxt->rip_relative = 1;
a6e3407b
AK		 1235 } else {
1236 base_reg = ctxt->modrm_rm;
dd856efa 1237 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1238 adjust_modrm_seg(ctxt, base_reg);
1239 }
9dac77fa 1240 switch (ctxt->modrm_mod) {
1c73ef66 1241 case 1:
e85a1085 1242 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1243 break;
1244 case 2:
e85a1085 1245 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1246 break;
1247 }
1248 }
90de84f5 1249 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1250 if (ctxt->ad_bytes != 8)
1251 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1252
1c73ef66
AK		 1253done:
1254 return rc;
1255}
1256
1257static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1258 struct operand *op)
1c73ef66 1259{
3e2815e9 1260 int rc = X86EMUL_CONTINUE;
1c73ef66 1261
2dbd0dd7 1262 op->type = OP_MEM;
9dac77fa 1263 switch (ctxt->ad_bytes) {
1c73ef66 1264 case 2:
e85a1085 1265 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1266 break;
1267 case 4:
e85a1085 1268 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1269 break;
1270 case 8:
e85a1085 1271 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1272 break;
1273 }
1274done:
1275 return rc;
1276}
1277
9dac77fa 1278static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1279{
7129eeca 1280 long sv = 0, mask;
35c843c4 1281
9dac77fa 1282 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1283 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1284
9dac77fa
AK		 1285 if (ctxt->src.bytes == 2)
1286 sv = (s16)ctxt->src.val & (s16)mask;
1287 else if (ctxt->src.bytes == 4)
1288 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1289 else
1290 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1291
9dac77fa 1292 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1293 }
ba7ff2b7
WY		 1294
1295 /* only subword offset */
9dac77fa 1296 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1297}
1298
dde7e6d1 1299static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1300 unsigned long addr, void *dest, unsigned size)
6aa8b732 1301{
dde7e6d1 1302 int rc;
9dac77fa 1303 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1304
f23b070e
XG		 1305 if (mc->pos < mc->end)
1306 goto read_cached;
6aa8b732 1307
f23b070e
XG		 1308 WARN_ON((mc->end + size) >= sizeof(mc->data));
1309
1310 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1311 &ctxt->exception);
1312 if (rc != X86EMUL_CONTINUE)
1313 return rc;
1314
1315 mc->end += size;
1316
1317read_cached:
1318 memcpy(dest, mc->data + mc->pos, size);
1319 mc->pos += size;
dde7e6d1
AK		 1320 return X86EMUL_CONTINUE;
1321}
6aa8b732 1322
3ca3ac4d
AK		 1323static int segmented_read(struct x86_emulate_ctxt *ctxt,
1324 struct segmented_address addr,
1325 void *data,
1326 unsigned size)
1327{
9fa088f4
AK		 1328 int rc;
1329 ulong linear;
1330
83b8795a 1331 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1332 if (rc != X86EMUL_CONTINUE)
1333 return rc;
7b105ca2 1334 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1335}
1336
1337static int segmented_write(struct x86_emulate_ctxt *ctxt,
1338 struct segmented_address addr,
1339 const void *data,
1340 unsigned size)
1341{
9fa088f4
AK		 1342 int rc;
1343 ulong linear;
1344
83b8795a 1345 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1346 if (rc != X86EMUL_CONTINUE)
1347 return rc;
0f65dd70
AK		 1348 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1349 &ctxt->exception);
3ca3ac4d
AK		 1350}
1351
1352static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1353 struct segmented_address addr,
1354 const void *orig_data, const void *data,
1355 unsigned size)
1356{
9fa088f4
AK		 1357 int rc;
1358 ulong linear;
1359
83b8795a 1360 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1361 if (rc != X86EMUL_CONTINUE)
1362 return rc;
0f65dd70
AK		 1363 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1364 size, &ctxt->exception);
3ca3ac4d
AK		 1365}
1366
dde7e6d1 1367static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1368 unsigned int size, unsigned short port,
1369 void *dest)
1370{
9dac77fa 1371 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1372
dde7e6d1 1373 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1374 unsigned int in_page, n;
9dac77fa 1375 unsigned int count = ctxt->rep_prefix ?
dd856efa 1376 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1377 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1378 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1379 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1380 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1381 if (n == 0)
1382 n = 1;
1383 rc->pos = rc->end = 0;
7b105ca2 1384 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1385 return 0;
1386 rc->end = n * size;
6aa8b732
AK		 1387 }
1388
e6e39f04
NA		 1389 if (ctxt->rep_prefix && (ctxt->d & String) &&
1390 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1391 ctxt->dst.data = rc->data + rc->pos;
1392 ctxt->dst.type = OP_MEM_STR;
1393 ctxt->dst.count = (rc->end - rc->pos) / size;
1394 rc->pos = rc->end;
1395 } else {
1396 memcpy(dest, rc->data + rc->pos, size);
1397 rc->pos += size;
1398 }
dde7e6d1
AK		 1399 return 1;
1400}
6aa8b732 1401
7f3d35fd
KW		 1402static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1403 u16 index, struct desc_struct *desc)
1404{
1405 struct desc_ptr dt;
1406 ulong addr;
1407
1408 ctxt->ops->get_idt(ctxt, &dt);
1409
1410 if (dt.size < index * 8 + 7)
1411 return emulate_gp(ctxt, index << 3 | 0x2);
1412
1413 addr = dt.address + index * 8;
1414 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1415 &ctxt->exception);
1416}
1417
dde7e6d1 1418static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1419 u16 selector, struct desc_ptr *dt)
1420{
0225fb50 1421 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1422 u32 base3 = 0;
7b105ca2 1423
dde7e6d1
AK		 1424 if (selector & 1 << 2) {
1425 struct desc_struct desc;
1aa36616
AK		 1426 u16 sel;
1427
dde7e6d1 1428 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1429 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1430 VCPU_SREG_LDTR))
dde7e6d1 1431 return;
e09d082c 1432
dde7e6d1 1433 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1434 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1435 } else
4bff1e86 1436 ops->get_gdt(ctxt, dt);
dde7e6d1 1437}
120df890 1438
dde7e6d1
AK		 1439/* allowed just for 8 bytes segments */
1440static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1441 u16 selector, struct desc_struct *desc,
1442 ulong *desc_addr_p)
dde7e6d1
AK		 1443{
1444 struct desc_ptr dt;
1445 u16 index = selector >> 3;
dde7e6d1 1446 ulong addr;
120df890 1447
7b105ca2 1448 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1449
35d3d4a1
AK		 1450 if (dt.size < index * 8 + 7)
1451 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1452
e919464b 1453 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1454 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1455 &ctxt->exception);
dde7e6d1 1456}
ef65c889 1457
dde7e6d1
AK		 1458/* allowed just for 8 bytes segments */
1459static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1460 u16 selector, struct desc_struct *desc)
1461{
1462 struct desc_ptr dt;
1463 u16 index = selector >> 3;
dde7e6d1 1464 ulong addr;
6aa8b732 1465
7b105ca2 1466 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1467
35d3d4a1
AK		 1468 if (dt.size < index * 8 + 7)
1469 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1470
dde7e6d1 1471 addr = dt.address + index * 8;
7b105ca2
TY		 1472 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1473 &ctxt->exception);
dde7e6d1 1474}
c7e75a3d 1475
5601d05b 1476/* Does not support long mode */
2356aaeb 1477static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1478 u16 selector, int seg, u8 cpl,
1479 bool in_task_switch,
1480 struct desc_struct *desc)
dde7e6d1 1481{
869be99c 1482 struct desc_struct seg_desc, old_desc;
2356aaeb 1483 u8 dpl, rpl;
dde7e6d1
AK		 1484 unsigned err_vec = GP_VECTOR;
1485 u32 err_code = 0;
1486 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1487 ulong desc_addr;
dde7e6d1 1488 int ret;
03ebebeb 1489 u16 dummy;
e37a75a1 1490 u32 base3 = 0;
69f55cb1 1491
dde7e6d1 1492 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1493
f8da94e9
KW		 1494 if (ctxt->mode == X86EMUL_MODE_REAL) {
1495 /* set real mode segment descriptor (keep limit etc. for
1496 * unreal mode) */
03ebebeb 1497 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1498 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1499 goto load;
f8da94e9
KW		 1500 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1501 /* VM86 needs a clean new segment descriptor */
1502 set_desc_base(&seg_desc, selector << 4);
1503 set_desc_limit(&seg_desc, 0xffff);
1504 seg_desc.type = 3;
1505 seg_desc.p = 1;
1506 seg_desc.s = 1;
1507 seg_desc.dpl = 3;
1508 goto load;
dde7e6d1
AK		 1509 }
1510
79d5b4c3 1511 rpl = selector & 3;
79d5b4c3
AK		 1512
1513 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1514 if ((seg == VCPU_SREG_CS
1515 || (seg == VCPU_SREG_SS
1516 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1517 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1518 && null_selector)
1519 goto exception;
1520
1521 /* TR should be in GDT only */
1522 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1523 goto exception;
1524
1525 if (null_selector) /* for NULL selector skip all following checks */
1526 goto load;
1527
e919464b 1528 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1529 if (ret != X86EMUL_CONTINUE)
1530 return ret;
1531
1532 err_code = selector & 0xfffc;
15fc0752 1533 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1534
fc058680 1535 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1536 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1537 goto exception;
1538
1539 if (!seg_desc.p) {
1540 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1541 goto exception;
1542 }
1543
dde7e6d1 1544 dpl = seg_desc.dpl;
dde7e6d1
AK		 1545
1546 switch (seg) {
1547 case VCPU_SREG_SS:
1548 /*
1549 * segment is not a writable data segment or segment
1550 * selector's RPL != CPL or segment selector's RPL != CPL
1551 */
1552 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1553 goto exception;
6aa8b732 1554 break;
dde7e6d1
AK		 1555 case VCPU_SREG_CS:
1556 if (!(seg_desc.type & 8))
1557 goto exception;
1558
1559 if (seg_desc.type & 4) {
1560 /* conforming */
1561 if (dpl > cpl)
1562 goto exception;
1563 } else {
1564 /* nonconforming */
1565 if (rpl > cpl || dpl != cpl)
1566 goto exception;
1567 }
040c8dc8
NA		 1568 /* in long-mode d/b must be clear if l is set */
1569 if (seg_desc.d && seg_desc.l) {
1570 u64 efer = 0;
1571
1572 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1573 if (efer & EFER_LMA)
1574 goto exception;
1575 }
1576
dde7e6d1
AK		 1577 /* CS(RPL) <- CPL */
1578 selector = (selector & 0xfffc) | cpl;
6aa8b732 1579 break;
dde7e6d1
AK		 1580 case VCPU_SREG_TR:
1581 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1582 goto exception;
869be99c
AK		 1583 old_desc = seg_desc;
1584 seg_desc.type |= 2; /* busy */
1585 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1586 sizeof(seg_desc), &ctxt->exception);
1587 if (ret != X86EMUL_CONTINUE)
1588 return ret;
dde7e6d1
AK		 1589 break;
1590 case VCPU_SREG_LDTR:
1591 if (seg_desc.s || seg_desc.type != 2)
1592 goto exception;
1593 break;
1594 default: /* DS, ES, FS, or GS */
4e62417b 1595 /*
dde7e6d1
AK		 1596 * segment is not a data or readable code segment or
1597 * ((segment is a data or nonconforming code segment)
1598 * and (both RPL and CPL > DPL))
4e62417b 1599 */
dde7e6d1
AK		 1600 if ((seg_desc.type & 0xa) == 0x8 ||
1601 (((seg_desc.type & 0xc) != 0xc) &&
1602 (rpl > dpl && cpl > dpl)))
1603 goto exception;
6aa8b732 1604 break;
dde7e6d1
AK		 1605 }
1606
1607 if (seg_desc.s) {
1608 /* mark segment as accessed */
1609 seg_desc.type |= 1;
7b105ca2 1610 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1611 if (ret != X86EMUL_CONTINUE)
1612 return ret;
e37a75a1
NA		 1613 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1614 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1615 sizeof(base3), &ctxt->exception);
1616 if (ret != X86EMUL_CONTINUE)
1617 return ret;
9a9abf6b
NA		 1618 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1619 ((u64)base3 << 32)))
1620 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1621 }
1622load:
e37a75a1 1623 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1624 if (desc)
1625 *desc = seg_desc;
dde7e6d1
AK		 1626 return X86EMUL_CONTINUE;
1627exception:
592f0858 1628 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1629}
1630
2356aaeb
PB		 1631static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1632 u16 selector, int seg)
1633{
1634 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1635 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1636}
1637
31be40b3
WY		 1638static void write_register_operand(struct operand *op)
1639{
1640 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1641 switch (op->bytes) {
1642 case 1:
1643 *(u8 *)op->addr.reg = (u8)op->val;
1644 break;
1645 case 2:
1646 *(u16 *)op->addr.reg = (u16)op->val;
1647 break;
1648 case 4:
1649 *op->addr.reg = (u32)op->val;
1650 break; /* 64b: zero-extend */
1651 case 8:
1652 *op->addr.reg = op->val;
1653 break;
1654 }
1655}
1656
fb32b1ed 1657static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1658{
fb32b1ed 1659 switch (op->type) {
dde7e6d1 1660 case OP_REG:
fb32b1ed 1661 write_register_operand(op);
6aa8b732 1662 break;
dde7e6d1 1663 case OP_MEM:
9dac77fa 1664 if (ctxt->lock_prefix)
f5f87dfb
PB		 1665 return segmented_cmpxchg(ctxt,
1666 op->addr.mem,
1667 &op->orig_val,
1668 &op->val,
1669 op->bytes);
1670 else
1671 return segmented_write(ctxt,
fb32b1ed 1672 op->addr.mem,
fb32b1ed
AK		 1673 &op->val,
1674 op->bytes);
a682e354 1675 break;
b3356bf0 1676 case OP_MEM_STR:
f5f87dfb
PB		 1677 return segmented_write(ctxt,
1678 op->addr.mem,
1679 op->data,
1680 op->bytes * op->count);
b3356bf0 1681 break;
1253791d 1682 case OP_XMM:
fb32b1ed 1683 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1684 break;
cbe2c9d3 1685 case OP_MM:
fb32b1ed 1686 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1687 break;
dde7e6d1
AK		 1688 case OP_NONE:
1689 /* no writeback */
414e6277 1690 break;
dde7e6d1 1691 default:
414e6277 1692 break;
6aa8b732 1693 }
dde7e6d1
AK		 1694 return X86EMUL_CONTINUE;
1695}
6aa8b732 1696
51ddff50 1697static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1698{
4179bb02 1699 struct segmented_address addr;
0dc8d10f 1700
5ad105e5 1701 rsp_increment(ctxt, -bytes);
dd856efa 1702 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1703 addr.seg = VCPU_SREG_SS;
1704
51ddff50
AK		 1705 return segmented_write(ctxt, addr, data, bytes);
1706}
1707
1708static int em_push(struct x86_emulate_ctxt *ctxt)
1709{
4179bb02 1710 /* Disable writeback. */
9dac77fa 1711 ctxt->dst.type = OP_NONE;
51ddff50 1712 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1713}
69f55cb1 1714
dde7e6d1 1715static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1716 void *dest, int len)
1717{
dde7e6d1 1718 int rc;
90de84f5 1719 struct segmented_address addr;
8b4caf66 1720
dd856efa 1721 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1722 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1723 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1724 if (rc != X86EMUL_CONTINUE)
1725 return rc;
1726
5ad105e5 1727 rsp_increment(ctxt, len);
dde7e6d1 1728 return rc;
8b4caf66
LV		 1729}
1730
c54fe504
TY		 1731static int em_pop(struct x86_emulate_ctxt *ctxt)
1732{
9dac77fa 1733 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1734}
1735
dde7e6d1 1736static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1737 void *dest, int len)
9de41573
GN		 1738{
1739 int rc;
dde7e6d1
AK		 1740 unsigned long val, change_mask;
1741 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1742 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1743
3b9be3bf 1744 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1745 if (rc != X86EMUL_CONTINUE)
1746 return rc;
9de41573 1747
dde7e6d1 1748 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1749 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1750
dde7e6d1
AK		 1751 switch(ctxt->mode) {
1752 case X86EMUL_MODE_PROT64:
1753 case X86EMUL_MODE_PROT32:
1754 case X86EMUL_MODE_PROT16:
1755 if (cpl == 0)
1756 change_mask |= EFLG_IOPL;
1757 if (cpl <= iopl)
1758 change_mask |= EFLG_IF;
1759 break;
1760 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1761 if (iopl < 3)
1762 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1763 change_mask |= EFLG_IF;
1764 break;
1765 default: /* real mode */
1766 change_mask |= (EFLG_IOPL | EFLG_IF);
1767 break;
9de41573 1768 }
dde7e6d1
AK		 1769
1770 *(unsigned long *)dest =
1771 (ctxt->eflags & ~change_mask) | (val & change_mask);
1772
1773 return rc;
9de41573
GN		 1774}
1775
62aaa2f0
TY		 1776static int em_popf(struct x86_emulate_ctxt *ctxt)
1777{
9dac77fa
AK		 1778 ctxt->dst.type = OP_REG;
1779 ctxt->dst.addr.reg = &ctxt->eflags;
1780 ctxt->dst.bytes = ctxt->op_bytes;
1781 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1782}
1783
612e89f0
AK		 1784static int em_enter(struct x86_emulate_ctxt *ctxt)
1785{
1786 int rc;
1787 unsigned frame_size = ctxt->src.val;
1788 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1789 ulong rbp;
612e89f0
AK		 1790
1791 if (nesting_level)
1792 return X86EMUL_UNHANDLEABLE;
1793
dd856efa
AK		 1794 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1795 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1796 if (rc != X86EMUL_CONTINUE)
1797 return rc;
dd856efa 1798 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1799 stack_mask(ctxt));
dd856efa
AK		 1800 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1801 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1802 stack_mask(ctxt));
1803 return X86EMUL_CONTINUE;
1804}
1805
f47cfa31
AK		 1806static int em_leave(struct x86_emulate_ctxt *ctxt)
1807{
dd856efa 1808 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1809 stack_mask(ctxt));
dd856efa 1810 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1811}
1812
1cd196ea 1813static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1814{
1cd196ea
AK		 1815 int seg = ctxt->src2.val;
1816
9dac77fa 1817 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1818 if (ctxt->op_bytes == 4) {
1819 rsp_increment(ctxt, -2);
1820 ctxt->op_bytes = 2;
1821 }
7b262e90 1822
4487b3b4 1823 return em_push(ctxt);
7b262e90
GN		 1824}
1825
1cd196ea 1826static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1827{
1cd196ea 1828 int seg = ctxt->src2.val;
dde7e6d1
AK		 1829 unsigned long selector;
1830 int rc;
38ba30ba 1831
9dac77fa 1832 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
1835
a5457e7b
PB		 1836 if (ctxt->modrm_reg == VCPU_SREG_SS)
1837 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1838
7b105ca2 1839 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1840 return rc;
38ba30ba
GN		 1841}
1842
b96a7fad 1843static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1844{
dd856efa 1845 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1846 int rc = X86EMUL_CONTINUE;
1847 int reg = VCPU_REGS_RAX;
38ba30ba 1848
dde7e6d1
AK		 1849 while (reg <= VCPU_REGS_RDI) {
1850 (reg == VCPU_REGS_RSP) ?
dd856efa 1851 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1852
4487b3b4 1853 rc = em_push(ctxt);
dde7e6d1
AK		 1854 if (rc != X86EMUL_CONTINUE)
1855 return rc;
38ba30ba 1856
dde7e6d1 1857 ++reg;
38ba30ba 1858 }
38ba30ba 1859
dde7e6d1 1860 return rc;
38ba30ba
GN		 1861}
1862
62aaa2f0
TY		 1863static int em_pushf(struct x86_emulate_ctxt *ctxt)
1864{
9dac77fa 1865 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1866 return em_push(ctxt);
1867}
1868
b96a7fad 1869static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1870{
dde7e6d1
AK		 1871 int rc = X86EMUL_CONTINUE;
1872 int reg = VCPU_REGS_RDI;
38ba30ba 1873
dde7e6d1
AK		 1874 while (reg >= VCPU_REGS_RAX) {
1875 if (reg == VCPU_REGS_RSP) {
5ad105e5 1876 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1877 --reg;
1878 }
38ba30ba 1879
dd856efa 1880 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1881 if (rc != X86EMUL_CONTINUE)
1882 break;
1883 --reg;
38ba30ba 1884 }
dde7e6d1 1885 return rc;
38ba30ba
GN		 1886}
1887
dd856efa 1888static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1889{
0225fb50 1890 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1891 int rc;
6e154e56
MG		 1892 struct desc_ptr dt;
1893 gva_t cs_addr;
1894 gva_t eip_addr;
1895 u16 cs, eip;
6e154e56
MG		 1896
1897 /* TODO: Add limit checks */
9dac77fa 1898 ctxt->src.val = ctxt->eflags;
4487b3b4 1899 rc = em_push(ctxt);
5c56e1cf
AK		 1900 if (rc != X86EMUL_CONTINUE)
1901 return rc;
6e154e56
MG		 1902
1903 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1904
9dac77fa 1905 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1906 rc = em_push(ctxt);
5c56e1cf
AK		 1907 if (rc != X86EMUL_CONTINUE)
1908 return rc;
6e154e56 1909
9dac77fa 1910 ctxt->src.val = ctxt->_eip;
4487b3b4 1911 rc = em_push(ctxt);
5c56e1cf
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
1914
4bff1e86 1915 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1916
1917 eip_addr = dt.address + (irq << 2);
1918 cs_addr = dt.address + (irq << 2) + 2;
1919
0f65dd70 1920 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1921 if (rc != X86EMUL_CONTINUE)
1922 return rc;
1923
0f65dd70 1924 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1925 if (rc != X86EMUL_CONTINUE)
1926 return rc;
1927
7b105ca2 1928 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1929 if (rc != X86EMUL_CONTINUE)
1930 return rc;
1931
9dac77fa 1932 ctxt->_eip = eip;
6e154e56
MG		 1933
1934 return rc;
1935}
1936
dd856efa
AK		 1937int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1938{
1939 int rc;
1940
1941 invalidate_registers(ctxt);
1942 rc = __emulate_int_real(ctxt, irq);
1943 if (rc == X86EMUL_CONTINUE)
1944 writeback_registers(ctxt);
1945 return rc;
1946}
1947
7b105ca2 1948static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1949{
1950 switch(ctxt->mode) {
1951 case X86EMUL_MODE_REAL:
dd856efa 1952 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1953 case X86EMUL_MODE_VM86:
1954 case X86EMUL_MODE_PROT16:
1955 case X86EMUL_MODE_PROT32:
1956 case X86EMUL_MODE_PROT64:
1957 default:
1958 /* Protected mode interrupts unimplemented yet */
1959 return X86EMUL_UNHANDLEABLE;
1960 }
1961}
1962
7b105ca2 1963static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1964{
dde7e6d1
AK		 1965 int rc = X86EMUL_CONTINUE;
1966 unsigned long temp_eip = 0;
1967 unsigned long temp_eflags = 0;
1968 unsigned long cs = 0;
1969 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1970 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1971 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1972 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1973
dde7e6d1 1974 /* TODO: Add stack limit check */
38ba30ba 1975
9dac77fa 1976 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1977
dde7e6d1
AK		 1978 if (rc != X86EMUL_CONTINUE)
1979 return rc;
38ba30ba 1980
35d3d4a1
AK		 1981 if (temp_eip & ~0xffff)
1982 return emulate_gp(ctxt, 0);
38ba30ba 1983
9dac77fa 1984 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1985
dde7e6d1
AK		 1986 if (rc != X86EMUL_CONTINUE)
1987 return rc;
38ba30ba 1988
9dac77fa 1989 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1990
dde7e6d1
AK		 1991 if (rc != X86EMUL_CONTINUE)
1992 return rc;
38ba30ba 1993
7b105ca2 1994 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1995
dde7e6d1
AK		 1996 if (rc != X86EMUL_CONTINUE)
1997 return rc;
38ba30ba 1998
9dac77fa 1999 ctxt->_eip = temp_eip;
38ba30ba 2000
38ba30ba 2001
9dac77fa 2002 if (ctxt->op_bytes == 4)
dde7e6d1 2003 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2004 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2005 ctxt->eflags &= ~0xffff;
2006 ctxt->eflags |= temp_eflags;
38ba30ba 2007 }
dde7e6d1
AK		 2008
2009 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2010 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2011
2012 return rc;
38ba30ba
GN		 2013}
2014
e01991e7 2015static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2016{
dde7e6d1
AK		 2017 switch(ctxt->mode) {
2018 case X86EMUL_MODE_REAL:
7b105ca2 2019 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2020 case X86EMUL_MODE_VM86:
2021 case X86EMUL_MODE_PROT16:
2022 case X86EMUL_MODE_PROT32:
2023 case X86EMUL_MODE_PROT64:
c37eda13 2024 default:
dde7e6d1
AK		 2025 /* iret from protected mode unimplemented yet */
2026 return X86EMUL_UNHANDLEABLE;
c37eda13 2027 }
c37eda13
WY		 2028}
2029
d2f62766
TY		 2030static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2031{
d2f62766 2032 int rc;
d1442d85
NA		 2033 unsigned short sel, old_sel;
2034 struct desc_struct old_desc, new_desc;
2035 const struct x86_emulate_ops *ops = ctxt->ops;
2036 u8 cpl = ctxt->ops->cpl(ctxt);
2037
2038 /* Assignment of RIP may only fail in 64-bit mode */
2039 if (ctxt->mode == X86EMUL_MODE_PROT64)
2040 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2041 VCPU_SREG_CS);
d2f62766 2042
9dac77fa 2043 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2044
d1442d85
NA		 2045 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2046 &new_desc);
d2f62766
TY		 2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
2049
d1442d85
NA		 2050 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2051 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2052 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2053 /* assigning eip failed; restore the old cs */
2054 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2055 return rc;
2056 }
2057 return rc;
d2f62766
TY		 2058}
2059
f7784046 2060static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2061{
f7784046
NA		 2062 return assign_eip_near(ctxt, ctxt->src.val);
2063}
8cdbd2c9 2064
f7784046
NA		 2065static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2066{
2067 int rc;
2068 long int old_eip;
2069
2070 old_eip = ctxt->_eip;
2071 rc = assign_eip_near(ctxt, ctxt->src.val);
2072 if (rc != X86EMUL_CONTINUE)
2073 return rc;
2074 ctxt->src.val = old_eip;
2075 rc = em_push(ctxt);
4179bb02 2076 return rc;
8cdbd2c9
LV		 2077}
2078
e0dac408 2079static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2080{
9dac77fa 2081 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2082
aaa05f24
NA		 2083 if (ctxt->dst.bytes == 16)
2084 return X86EMUL_UNHANDLEABLE;
2085
dd856efa
AK		 2086 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2087 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2088 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2089 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2090 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2091 } else {
dd856efa
AK		 2092 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2093 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2094
05f086f8 2095 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2096 }
1b30eaa8 2097 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2098}
2099
ebda02c2
TY		 2100static int em_ret(struct x86_emulate_ctxt *ctxt)
2101{
234f3ce4
NA		 2102 int rc;
2103 unsigned long eip;
2104
2105 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2106 if (rc != X86EMUL_CONTINUE)
2107 return rc;
2108
2109 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2110}
2111
e01991e7 2112static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2113{
a77ab5ea 2114 int rc;
d1442d85
NA		 2115 unsigned long eip, cs;
2116 u16 old_cs;
9e8919ae 2117 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2118 struct desc_struct old_desc, new_desc;
2119 const struct x86_emulate_ops *ops = ctxt->ops;
2120
2121 if (ctxt->mode == X86EMUL_MODE_PROT64)
2122 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2123 VCPU_SREG_CS);
a77ab5ea 2124
d1442d85 2125 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2126 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2127 return rc;
9dac77fa 2128 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2129 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2130 return rc;
9e8919ae
NA		 2131 /* Outer-privilege level return is not implemented */
2132 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2133 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2134 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2135 &new_desc);
2136 if (rc != X86EMUL_CONTINUE)
2137 return rc;
2138 rc = assign_eip_far(ctxt, eip, new_desc.l);
2139 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2140 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2141 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2142 }
a77ab5ea
AK		 2143 return rc;
2144}
2145
3261107e
BR		 2146static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2147{
2148 int rc;
2149
2150 rc = em_ret_far(ctxt);
2151 if (rc != X86EMUL_CONTINUE)
2152 return rc;
2153 rsp_increment(ctxt, ctxt->src.val);
2154 return X86EMUL_CONTINUE;
2155}
2156
e940b5c2
TY		 2157static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2158{
2159 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2160 ctxt->dst.orig_val = ctxt->dst.val;
2161 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2162 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2163 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2164 fastop(ctxt, em_cmp);
e940b5c2
TY		 2165
2166 if (ctxt->eflags & EFLG_ZF) {
2167 /* Success: write back to memory. */
2168 ctxt->dst.val = ctxt->src.orig_val;
2169 } else {
2170 /* Failure: write the value we saw to EAX. */
2171 ctxt->dst.type = OP_REG;
dd856efa 2172 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2173 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2174 }
2175 return X86EMUL_CONTINUE;
2176}
2177
d4b4325f 2178static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2179{
d4b4325f 2180 int seg = ctxt->src2.val;
09b5f4d3
WY		 2181 unsigned short sel;
2182 int rc;
2183
9dac77fa 2184 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2185
7b105ca2 2186 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2187 if (rc != X86EMUL_CONTINUE)
2188 return rc;
2189
9dac77fa 2190 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2191 return rc;
2192}
2193
7b105ca2 2194static void
e66bb2cc 2195setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2196 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2197{
e66bb2cc 2198 cs->l = 0; /* will be adjusted later */
79168fd1 2199 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2200 cs->g = 1; /* 4kb granularity */
79168fd1 2201 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2202 cs->type = 0x0b; /* Read, Execute, Accessed */
2203 cs->s = 1;
2204 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2205 cs->p = 1;
2206 cs->d = 1;
99245b50 2207 cs->avl = 0;
e66bb2cc 2208
79168fd1
GN		 2209 set_desc_base(ss, 0); /* flat segment */
2210 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2211 ss->g = 1; /* 4kb granularity */
2212 ss->s = 1;
2213 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2214 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2215 ss->dpl = 0;
79168fd1 2216 ss->p = 1;
99245b50
GN		 2217 ss->l = 0;
2218 ss->avl = 0;
e66bb2cc
AP		 2219}
2220
1a18a69b
AK		 2221static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2222{
2223 u32 eax, ebx, ecx, edx;
2224
2225 eax = ecx = 0;
0017f93a
AK		 2226 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2227 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2228 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2229 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2230}
2231
c2226fc9
SB		 2232static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2233{
0225fb50 2234 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2235 u32 eax, ebx, ecx, edx;
2236
2237 /*
2238 * syscall should always be enabled in longmode - so only become
2239 * vendor specific (cpuid) if other modes are active...
2240 */
2241 if (ctxt->mode == X86EMUL_MODE_PROT64)
2242 return true;
2243
2244 eax = 0x00000000;
2245 ecx = 0x00000000;
0017f93a
AK		 2246 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2247 /*
2248 * Intel ("GenuineIntel")
2249 * remark: Intel CPUs only support "syscall" in 64bit
2250 * longmode. Also an 64bit guest with a
2251 * 32bit compat-app running will #UD !! While this
2252 * behaviour can be fixed (by emulating) into AMD
2253 * response - CPUs of AMD can't behave like Intel.
2254 */
2255 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2256 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2257 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2258 return false;
2259
2260 /* AMD ("AuthenticAMD") */
2261 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2262 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2263 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2264 return true;
2265
2266 /* AMD ("AMDisbetter!") */
2267 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2268 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2269 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2270 return true;
c2226fc9
SB		 2271
2272 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2273 return false;
2274}
2275
e01991e7 2276static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2277{
0225fb50 2278 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2279 struct desc_struct cs, ss;
e66bb2cc 2280 u64 msr_data;
79168fd1 2281 u16 cs_sel, ss_sel;
c2ad2bb3 2282 u64 efer = 0;
e66bb2cc
AP		 2283
2284 /* syscall is not available in real mode */
2e901c4c 2285 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2286 ctxt->mode == X86EMUL_MODE_VM86)
2287 return emulate_ud(ctxt);
e66bb2cc 2288
c2226fc9
SB		 2289 if (!(em_syscall_is_enabled(ctxt)))
2290 return emulate_ud(ctxt);
2291
c2ad2bb3 2292 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2293 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2294
c2226fc9
SB		 2295 if (!(efer & EFER_SCE))
2296 return emulate_ud(ctxt);
2297
717746e3 2298 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2299 msr_data >>= 32;
79168fd1
GN		 2300 cs_sel = (u16)(msr_data & 0xfffc);
2301 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2302
c2ad2bb3 2303 if (efer & EFER_LMA) {
79168fd1 2304 cs.d = 0;
e66bb2cc
AP		 2305 cs.l = 1;
2306 }
1aa36616
AK		 2307 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2308 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2309
dd856efa 2310 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2311 if (efer & EFER_LMA) {
e66bb2cc 2312#ifdef CONFIG_X86_64
6c6cb69b 2313 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2314
717746e3 2315 ops->get_msr(ctxt,
3fb1b5db
GN		 2316 ctxt->mode == X86EMUL_MODE_PROT64 ?
2317 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2318 ctxt->_eip = msr_data;
e66bb2cc 2319
717746e3 2320 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2321 ctxt->eflags &= ~msr_data;
807c1425 2322 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2323#endif
2324 } else {
2325 /* legacy mode */
717746e3 2326 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2327 ctxt->_eip = (u32)msr_data;
e66bb2cc 2328
6c6cb69b 2329 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2330 }
2331
e54cfa97 2332 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2333}
2334
e01991e7 2335static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2336{
0225fb50 2337 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2338 struct desc_struct cs, ss;
8c604352 2339 u64 msr_data;
79168fd1 2340 u16 cs_sel, ss_sel;
c2ad2bb3 2341 u64 efer = 0;
8c604352 2342
7b105ca2 2343 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2344 /* inject #GP if in real mode */
35d3d4a1
AK		 2345 if (ctxt->mode == X86EMUL_MODE_REAL)
2346 return emulate_gp(ctxt, 0);
8c604352 2347
1a18a69b
AK		 2348 /*
2349 * Not recognized on AMD in compat mode (but is recognized in legacy
2350 * mode).
2351 */
2352 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2353 && !vendor_intel(ctxt))
2354 return emulate_ud(ctxt);
2355
b2c9d43e 2356 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2357 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2358 return X86EMUL_UNHANDLEABLE;
8c604352 2359
7b105ca2 2360 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2361
717746e3 2362 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2363 switch (ctxt->mode) {
2364 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2365 if ((msr_data & 0xfffc) == 0x0)
2366 return emulate_gp(ctxt, 0);
8c604352
AP		 2367 break;
2368 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2369 if (msr_data == 0x0)
2370 return emulate_gp(ctxt, 0);
8c604352 2371 break;
9d1b39a9
GN		 2372 default:
2373 break;
8c604352
AP		 2374 }
2375
6c6cb69b 2376 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2377 cs_sel = (u16)msr_data;
2378 cs_sel &= ~SELECTOR_RPL_MASK;
2379 ss_sel = cs_sel + 8;
2380 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2381 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2382 cs.d = 0;
8c604352
AP		 2383 cs.l = 1;
2384 }
2385
1aa36616
AK		 2386 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2387 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2388
717746e3 2389 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2390 ctxt->_eip = msr_data;
8c604352 2391
717746e3 2392 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2393 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2394
e54cfa97 2395 return X86EMUL_CONTINUE;
8c604352
AP		 2396}
2397
e01991e7 2398static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2399{
0225fb50 2400 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2401 struct desc_struct cs, ss;
234f3ce4 2402 u64 msr_data, rcx, rdx;
4668f050 2403 int usermode;
1249b96e 2404 u16 cs_sel = 0, ss_sel = 0;
4668f050 2405
a0044755
GN		 2406 /* inject #GP if in real mode or Virtual 8086 mode */
2407 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2408 ctxt->mode == X86EMUL_MODE_VM86)
2409 return emulate_gp(ctxt, 0);
4668f050 2410
7b105ca2 2411 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2412
9dac77fa 2413 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2414 usermode = X86EMUL_MODE_PROT64;
2415 else
2416 usermode = X86EMUL_MODE_PROT32;
2417
234f3ce4
NA		 2418 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2419 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2420
4668f050
AP		 2421 cs.dpl = 3;
2422 ss.dpl = 3;
717746e3 2423 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2424 switch (usermode) {
2425 case X86EMUL_MODE_PROT32:
79168fd1 2426 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2427 if ((msr_data & 0xfffc) == 0x0)
2428 return emulate_gp(ctxt, 0);
79168fd1 2429 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2430 rcx = (u32)rcx;
2431 rdx = (u32)rdx;
4668f050
AP		 2432 break;
2433 case X86EMUL_MODE_PROT64:
79168fd1 2434 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2435 if (msr_data == 0x0)
2436 return emulate_gp(ctxt, 0);
79168fd1
GN		 2437 ss_sel = cs_sel + 8;
2438 cs.d = 0;
4668f050 2439 cs.l = 1;
234f3ce4
NA		 2440 if (is_noncanonical_address(rcx) ||
2441 is_noncanonical_address(rdx))
2442 return emulate_gp(ctxt, 0);
4668f050
AP		 2443 break;
2444 }
79168fd1
GN		 2445 cs_sel |= SELECTOR_RPL_MASK;
2446 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2447
1aa36616
AK		 2448 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2449 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2450
234f3ce4
NA		 2451 ctxt->_eip = rdx;
2452 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2453
e54cfa97 2454 return X86EMUL_CONTINUE;
4668f050
AP		 2455}
2456
7b105ca2 2457static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2458{
2459 int iopl;
2460 if (ctxt->mode == X86EMUL_MODE_REAL)
2461 return false;
2462 if (ctxt->mode == X86EMUL_MODE_VM86)
2463 return true;
2464 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2465 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2466}
2467
2468static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2469 u16 port, u16 len)
2470{
0225fb50 2471 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2472 struct desc_struct tr_seg;
5601d05b 2473 u32 base3;
f850e2e6 2474 int r;
1aa36616 2475 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2476 unsigned mask = (1 << len) - 1;
5601d05b 2477 unsigned long base;
f850e2e6 2478
1aa36616 2479 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2480 if (!tr_seg.p)
f850e2e6 2481 return false;
79168fd1 2482 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2483 return false;
5601d05b
GN		 2484 base = get_desc_base(&tr_seg);
2485#ifdef CONFIG_X86_64
2486 base |= ((u64)base3) << 32;
2487#endif
0f65dd70 2488 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2489 if (r != X86EMUL_CONTINUE)
2490 return false;
79168fd1 2491 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2492 return false;
0f65dd70 2493 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2494 if (r != X86EMUL_CONTINUE)
2495 return false;
2496 if ((perm >> bit_idx) & mask)
2497 return false;
2498 return true;
2499}
2500
2501static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2502 u16 port, u16 len)
2503{
4fc40f07
GN		 2504 if (ctxt->perm_ok)
2505 return true;
2506
7b105ca2
TY		 2507 if (emulator_bad_iopl(ctxt))
2508 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2509 return false;
4fc40f07
GN		 2510
2511 ctxt->perm_ok = true;
2512
f850e2e6
GN		 2513 return true;
2514}
2515
38ba30ba 2516static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2517 struct tss_segment_16 *tss)
2518{
9dac77fa 2519 tss->ip = ctxt->_eip;
38ba30ba 2520 tss->flag = ctxt->eflags;
dd856efa
AK		 2521 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2522 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2523 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2524 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2525 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2526 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2527 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2528 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2529
1aa36616
AK		 2530 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2531 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2532 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2533 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2534 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2535}
2536
2537static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2538 struct tss_segment_16 *tss)
2539{
38ba30ba 2540 int ret;
2356aaeb 2541 u8 cpl;
38ba30ba 2542
9dac77fa 2543 ctxt->_eip = tss->ip;
38ba30ba 2544 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2545 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2546 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2547 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2548 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2549 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2550 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2551 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2552 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2553
2554 /*
2555 * SDM says that segment selectors are loaded before segment
2556 * descriptors
2557 */
1aa36616
AK		 2558 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2559 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2560 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2561 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2562 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2563
2356aaeb
PB		 2564 cpl = tss->cs & 3;
2565
38ba30ba 2566 /*
fc058680 2567 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2568 * it is handled in a context of new task
2569 */
d1442d85
NA		 2570 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2571 true, NULL);
38ba30ba
GN		 2572 if (ret != X86EMUL_CONTINUE)
2573 return ret;
d1442d85
NA		 2574 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2575 true, NULL);
38ba30ba
GN		 2576 if (ret != X86EMUL_CONTINUE)
2577 return ret;
d1442d85
NA		 2578 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2579 true, NULL);
38ba30ba
GN		 2580 if (ret != X86EMUL_CONTINUE)
2581 return ret;
d1442d85
NA		 2582 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2583 true, NULL);
38ba30ba
GN		 2584 if (ret != X86EMUL_CONTINUE)
2585 return ret;
d1442d85
NA		 2586 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2587 true, NULL);
38ba30ba
GN		 2588 if (ret != X86EMUL_CONTINUE)
2589 return ret;
2590
2591 return X86EMUL_CONTINUE;
2592}
2593
2594static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2595 u16 tss_selector, u16 old_tss_sel,
2596 ulong old_tss_base, struct desc_struct *new_desc)
2597{
0225fb50 2598 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2599 struct tss_segment_16 tss_seg;
2600 int ret;
bcc55cba 2601 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2602
0f65dd70 2603 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2604 &ctxt->exception);
db297e3d 2605 if (ret != X86EMUL_CONTINUE)
38ba30ba 2606 /* FIXME: need to provide precise fault address */
38ba30ba 2607 return ret;
38ba30ba 2608
7b105ca2 2609 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2610
0f65dd70 2611 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2612 &ctxt->exception);
db297e3d 2613 if (ret != X86EMUL_CONTINUE)
38ba30ba 2614 /* FIXME: need to provide precise fault address */
38ba30ba 2615 return ret;
38ba30ba 2616
0f65dd70 2617 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2618 &ctxt->exception);
db297e3d 2619 if (ret != X86EMUL_CONTINUE)
38ba30ba 2620 /* FIXME: need to provide precise fault address */
38ba30ba 2621 return ret;
38ba30ba
GN		 2622
2623 if (old_tss_sel != 0xffff) {
2624 tss_seg.prev_task_link = old_tss_sel;
2625
0f65dd70 2626 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2627 &tss_seg.prev_task_link,
2628 sizeof tss_seg.prev_task_link,
0f65dd70 2629 &ctxt->exception);
db297e3d 2630 if (ret != X86EMUL_CONTINUE)
38ba30ba 2631 /* FIXME: need to provide precise fault address */
38ba30ba 2632 return ret;
38ba30ba
GN		 2633 }
2634
7b105ca2 2635 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2636}
2637
2638static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2639 struct tss_segment_32 *tss)
2640{
5c7411e2 2641 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2642 tss->eip = ctxt->_eip;
38ba30ba 2643 tss->eflags = ctxt->eflags;
dd856efa
AK		 2644 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2645 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2646 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2647 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2648 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2649 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2650 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2651 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2652
1aa36616
AK		 2653 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2654 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2655 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2656 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2657 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2658 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2659}
2660
2661static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2662 struct tss_segment_32 *tss)
2663{
38ba30ba 2664 int ret;
2356aaeb 2665 u8 cpl;
38ba30ba 2666
7b105ca2 2667 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2668 return emulate_gp(ctxt, 0);
9dac77fa 2669 ctxt->_eip = tss->eip;
38ba30ba 2670 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2671
2672 /* General purpose registers */
dd856efa
AK		 2673 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2674 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2675 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2676 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2677 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2678 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2679 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2680 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2681
2682 /*
2683 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2684 * descriptors. This is important because CPL checks will
2685 * use CS.RPL.
38ba30ba 2686 */
1aa36616
AK		 2687 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2688 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2689 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2690 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2691 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2692 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2693 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2694
4cee4798
KW		 2695 /*
2696 * If we're switching between Protected Mode and VM86, we need to make
2697 * sure to update the mode before loading the segment descriptors so
2698 * that the selectors are interpreted correctly.
4cee4798 2699 */
2356aaeb 2700 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2701 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2702 cpl = 3;
2703 } else {
4cee4798 2704 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2705 cpl = tss->cs & 3;
2706 }
4cee4798 2707
38ba30ba
GN		 2708 /*
2709 * Now load segment descriptors. If fault happenes at this stage
2710 * it is handled in a context of new task
2711 */
d1442d85
NA		 2712 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2713 cpl, true, NULL);
38ba30ba
GN		 2714 if (ret != X86EMUL_CONTINUE)
2715 return ret;
d1442d85
NA		 2716 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2717 true, NULL);
38ba30ba
GN		 2718 if (ret != X86EMUL_CONTINUE)
2719 return ret;
d1442d85
NA		 2720 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2721 true, NULL);
38ba30ba
GN		 2722 if (ret != X86EMUL_CONTINUE)
2723 return ret;
d1442d85
NA		 2724 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2725 true, NULL);
38ba30ba
GN		 2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
d1442d85
NA		 2728 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2729 true, NULL);
38ba30ba
GN		 2730 if (ret != X86EMUL_CONTINUE)
2731 return ret;
d1442d85
NA		 2732 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2733 true, NULL);
38ba30ba
GN		 2734 if (ret != X86EMUL_CONTINUE)
2735 return ret;
d1442d85
NA		 2736 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2737 true, NULL);
38ba30ba
GN		 2738 if (ret != X86EMUL_CONTINUE)
2739 return ret;
2740
2741 return X86EMUL_CONTINUE;
2742}
2743
2744static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2745 u16 tss_selector, u16 old_tss_sel,
2746 ulong old_tss_base, struct desc_struct *new_desc)
2747{
0225fb50 2748 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2749 struct tss_segment_32 tss_seg;
2750 int ret;
bcc55cba 2751 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2752 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2753 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2754
0f65dd70 2755 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2756 &ctxt->exception);
db297e3d 2757 if (ret != X86EMUL_CONTINUE)
38ba30ba 2758 /* FIXME: need to provide precise fault address */
38ba30ba 2759 return ret;
38ba30ba 2760
7b105ca2 2761 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2762
5c7411e2
NA		 2763 /* Only GP registers and segment selectors are saved */
2764 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2765 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2766 if (ret != X86EMUL_CONTINUE)
38ba30ba 2767 /* FIXME: need to provide precise fault address */
38ba30ba 2768 return ret;
38ba30ba 2769
0f65dd70 2770 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2771 &ctxt->exception);
db297e3d 2772 if (ret != X86EMUL_CONTINUE)
38ba30ba 2773 /* FIXME: need to provide precise fault address */
38ba30ba 2774 return ret;
38ba30ba
GN		 2775
2776 if (old_tss_sel != 0xffff) {
2777 tss_seg.prev_task_link = old_tss_sel;
2778
0f65dd70 2779 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2780 &tss_seg.prev_task_link,
2781 sizeof tss_seg.prev_task_link,
0f65dd70 2782 &ctxt->exception);
db297e3d 2783 if (ret != X86EMUL_CONTINUE)
38ba30ba 2784 /* FIXME: need to provide precise fault address */
38ba30ba 2785 return ret;
38ba30ba
GN		 2786 }
2787
7b105ca2 2788 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2789}
2790
2791static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2792 u16 tss_selector, int idt_index, int reason,
e269fb21 2793 bool has_error_code, u32 error_code)
38ba30ba 2794{
0225fb50 2795 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2796 struct desc_struct curr_tss_desc, next_tss_desc;
2797 int ret;
1aa36616 2798 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2799 ulong old_tss_base =
4bff1e86 2800 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2801 u32 desc_limit;
e919464b 2802 ulong desc_addr;
38ba30ba
GN		 2803
2804 /* FIXME: old_tss_base == ~0 ? */
2805
e919464b 2806 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2807 if (ret != X86EMUL_CONTINUE)
2808 return ret;
e919464b 2809 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2810 if (ret != X86EMUL_CONTINUE)
2811 return ret;
2812
2813 /* FIXME: check that next_tss_desc is tss */
2814
7f3d35fd
KW		 2815 /*
2816 * Check privileges. The three cases are task switch caused by...
2817 *
2818 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2819 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2820 * 3. jmp/call to TSS/task-gate: No check is performed since the
2821 * hardware checks it before exiting.
7f3d35fd
KW		 2822 */
2823 if (reason == TASK_SWITCH_GATE) {
2824 if (idt_index != -1) {
2825 /* Software interrupts */
2826 struct desc_struct task_gate_desc;
2827 int dpl;
2828
2829 ret = read_interrupt_descriptor(ctxt, idt_index,
2830 &task_gate_desc);
2831 if (ret != X86EMUL_CONTINUE)
2832 return ret;
2833
2834 dpl = task_gate_desc.dpl;
2835 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2836 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2837 }
38ba30ba
GN		 2838 }
2839
ceffb459
GN		 2840 desc_limit = desc_limit_scaled(&next_tss_desc);
2841 if (!next_tss_desc.p ||
2842 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2843 desc_limit < 0x2b)) {
592f0858 2844 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2845 }
2846
2847 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2848 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2849 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2850 }
2851
2852 if (reason == TASK_SWITCH_IRET)
2853 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2854
2855 /* set back link to prev task only if NT bit is set in eflags
fc058680 2856 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2857 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2858 old_tss_sel = 0xffff;
2859
2860 if (next_tss_desc.type & 8)
7b105ca2 2861 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2862 old_tss_base, &next_tss_desc);
2863 else
7b105ca2 2864 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2865 old_tss_base, &next_tss_desc);
0760d448
JK		 2866 if (ret != X86EMUL_CONTINUE)
2867 return ret;
38ba30ba
GN		 2868
2869 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2870 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2871
2872 if (reason != TASK_SWITCH_IRET) {
2873 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2874 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2875 }
2876
717746e3 2877 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2878 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2879
e269fb21 2880 if (has_error_code) {
9dac77fa
AK		 2881 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2882 ctxt->lock_prefix = 0;
2883 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2884 ret = em_push(ctxt);
e269fb21
JK		 2885 }
2886
38ba30ba
GN		 2887 return ret;
2888}
2889
2890int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2891 u16 tss_selector, int idt_index, int reason,
e269fb21 2892 bool has_error_code, u32 error_code)
38ba30ba 2893{
38ba30ba
GN		 2894 int rc;
2895
dd856efa 2896 invalidate_registers(ctxt);
9dac77fa
AK		 2897 ctxt->_eip = ctxt->eip;
2898 ctxt->dst.type = OP_NONE;
38ba30ba 2899
7f3d35fd 2900 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2901 has_error_code, error_code);
38ba30ba 2902
dd856efa 2903 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2904 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2905 writeback_registers(ctxt);
2906 }
38ba30ba 2907
a0c0ab2f 2908 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2909}
2910
f3bd64c6
GN		 2911static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2912 struct operand *op)
a682e354 2913{
b3356bf0 2914 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2915
dd856efa
AK		 2916 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2917 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2918}
2919
7af04fc0
AK		 2920static int em_das(struct x86_emulate_ctxt *ctxt)
2921{
7af04fc0
AK		 2922 u8 al, old_al;
2923 bool af, cf, old_cf;
2924
2925 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2926 al = ctxt->dst.val;
7af04fc0
AK		 2927
2928 old_al = al;
2929 old_cf = cf;
2930 cf = false;
2931 af = ctxt->eflags & X86_EFLAGS_AF;
2932 if ((al & 0x0f) > 9 || af) {
2933 al -= 6;
2934 cf = old_cf | (al >= 250);
2935 af = true;
2936 } else {
2937 af = false;
2938 }
2939 if (old_al > 0x99 || old_cf) {
2940 al -= 0x60;
2941 cf = true;
2942 }
2943
9dac77fa 2944 ctxt->dst.val = al;
7af04fc0 2945 /* Set PF, ZF, SF */
9dac77fa
AK		 2946 ctxt->src.type = OP_IMM;
2947 ctxt->src.val = 0;
2948 ctxt->src.bytes = 1;
158de57f 2949 fastop(ctxt, em_or);
7af04fc0
AK		 2950 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2951 if (cf)
2952 ctxt->eflags |= X86_EFLAGS_CF;
2953 if (af)
2954 ctxt->eflags |= X86_EFLAGS_AF;
2955 return X86EMUL_CONTINUE;
2956}
2957
a035d5c6
PB		 2958static int em_aam(struct x86_emulate_ctxt *ctxt)
2959{
2960 u8 al, ah;
2961
2962 if (ctxt->src.val == 0)
2963 return emulate_de(ctxt);
2964
2965 al = ctxt->dst.val & 0xff;
2966 ah = al / ctxt->src.val;
2967 al %= ctxt->src.val;
2968
2969 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2970
2971 /* Set PF, ZF, SF */
2972 ctxt->src.type = OP_IMM;
2973 ctxt->src.val = 0;
2974 ctxt->src.bytes = 1;
2975 fastop(ctxt, em_or);
2976
2977 return X86EMUL_CONTINUE;
2978}
2979
7f662273
GN		 2980static int em_aad(struct x86_emulate_ctxt *ctxt)
2981{
2982 u8 al = ctxt->dst.val & 0xff;
2983 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2984
2985 al = (al + (ah * ctxt->src.val)) & 0xff;
2986
2987 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2988
f583c29b
GN		 2989 /* Set PF, ZF, SF */
2990 ctxt->src.type = OP_IMM;
2991 ctxt->src.val = 0;
2992 ctxt->src.bytes = 1;
2993 fastop(ctxt, em_or);
7f662273
GN		 2994
2995 return X86EMUL_CONTINUE;
2996}
2997
d4ddafcd
TY		 2998static int em_call(struct x86_emulate_ctxt *ctxt)
2999{
234f3ce4 3000 int rc;
d4ddafcd
TY		 3001 long rel = ctxt->src.val;
3002
3003 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3004 rc = jmp_rel(ctxt, rel);
3005 if (rc != X86EMUL_CONTINUE)
3006 return rc;
d4ddafcd
TY		 3007 return em_push(ctxt);
3008}
3009
0ef753b8
AK		 3010static int em_call_far(struct x86_emulate_ctxt *ctxt)
3011{
0ef753b8
AK		 3012 u16 sel, old_cs;
3013 ulong old_eip;
3014 int rc;
d1442d85
NA		 3015 struct desc_struct old_desc, new_desc;
3016 const struct x86_emulate_ops *ops = ctxt->ops;
3017 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3018
9dac77fa 3019 old_eip = ctxt->_eip;
d1442d85 3020 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3021
9dac77fa 3022 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3023 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3024 &new_desc);
3025 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3026 return X86EMUL_CONTINUE;
3027
d1442d85
NA		 3028 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
3029 if (rc != X86EMUL_CONTINUE)
3030 goto fail;
0ef753b8 3031
9dac77fa 3032 ctxt->src.val = old_cs;
4487b3b4 3033 rc = em_push(ctxt);
0ef753b8 3034 if (rc != X86EMUL_CONTINUE)
d1442d85 3035 goto fail;
0ef753b8 3036
9dac77fa 3037 ctxt->src.val = old_eip;
d1442d85
NA		 3038 rc = em_push(ctxt);
3039 /* If we failed, we tainted the memory, but the very least we should
3040 restore cs */
3041 if (rc != X86EMUL_CONTINUE)
3042 goto fail;
3043 return rc;
3044fail:
3045 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3046 return rc;
3047
0ef753b8
AK		 3048}
3049
40ece7c7
AK		 3050static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3051{
40ece7c7 3052 int rc;
234f3ce4 3053 unsigned long eip;
40ece7c7 3054
234f3ce4
NA		 3055 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3056 if (rc != X86EMUL_CONTINUE)
3057 return rc;
3058 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3059 if (rc != X86EMUL_CONTINUE)
3060 return rc;
5ad105e5 3061 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3062 return X86EMUL_CONTINUE;
3063}
3064
e4f973ae
TY		 3065static int em_xchg(struct x86_emulate_ctxt *ctxt)
3066{
e4f973ae 3067 /* Write back the register source. */
9dac77fa
AK		 3068 ctxt->src.val = ctxt->dst.val;
3069 write_register_operand(&ctxt->src);
e4f973ae
TY		 3070
3071 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3072 ctxt->dst.val = ctxt->src.orig_val;
3073 ctxt->lock_prefix = 1;
e4f973ae
TY		 3074 return X86EMUL_CONTINUE;
3075}
3076
5c82aa29
AK		 3077static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3078{
9dac77fa 3079 ctxt->dst.val = ctxt->src2.val;
4d758349 3080 return fastop(ctxt, em_imul);
5c82aa29
AK		 3081}
3082
61429142
AK		 3083static int em_cwd(struct x86_emulate_ctxt *ctxt)
3084{
9dac77fa
AK		 3085 ctxt->dst.type = OP_REG;
3086 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3087 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3088 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3089
3090 return X86EMUL_CONTINUE;
3091}
3092
48bb5d3c
AK		 3093static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3094{
48bb5d3c
AK		 3095 u64 tsc = 0;
3096
717746e3 3097 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3098 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3099 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3100 return X86EMUL_CONTINUE;
3101}
3102
222d21aa
AK		 3103static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3104{
3105 u64 pmc;
3106
dd856efa 3107 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3108 return emulate_gp(ctxt, 0);
dd856efa
AK		 3109 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3110 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3111 return X86EMUL_CONTINUE;
3112}
3113
b9eac5f4
AK		 3114static int em_mov(struct x86_emulate_ctxt *ctxt)
3115{
54cfdb3e 3116 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3117 return X86EMUL_CONTINUE;
3118}
3119
84cffe49
BP		 3120#define FFL(x) bit(X86_FEATURE_##x)
3121
3122static int em_movbe(struct x86_emulate_ctxt *ctxt)
3123{
3124 u32 ebx, ecx, edx, eax = 1;
3125 u16 tmp;
3126
3127 /*
3128 * Check MOVBE is set in the guest-visible CPUID leaf.
3129 */
3130 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3131 if (!(ecx & FFL(MOVBE)))
3132 return emulate_ud(ctxt);
3133
3134 switch (ctxt->op_bytes) {
3135 case 2:
3136 /*
3137 * From MOVBE definition: "...When the operand size is 16 bits,
3138 * the upper word of the destination register remains unchanged
3139 * ..."
3140 *
3141 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3142 * rules so we have to do the operation almost per hand.
3143 */
3144 tmp = (u16)ctxt->src.val;
3145 ctxt->dst.val &= ~0xffffUL;
3146 ctxt->dst.val |= (unsigned long)swab16(tmp);
3147 break;
3148 case 4:
3149 ctxt->dst.val = swab32((u32)ctxt->src.val);
3150 break;
3151 case 8:
3152 ctxt->dst.val = swab64(ctxt->src.val);
3153 break;
3154 default:
592f0858 3155 BUG();
84cffe49
BP		 3156 }
3157 return X86EMUL_CONTINUE;
3158}
3159
bc00f8d2
TY		 3160static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3161{
3162 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3163 return emulate_gp(ctxt, 0);
3164
3165 /* Disable writeback. */
3166 ctxt->dst.type = OP_NONE;
3167 return X86EMUL_CONTINUE;
3168}
3169
3170static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3171{
3172 unsigned long val;
3173
3174 if (ctxt->mode == X86EMUL_MODE_PROT64)
3175 val = ctxt->src.val & ~0ULL;
3176 else
3177 val = ctxt->src.val & ~0U;
3178
3179 /* #UD condition is already handled. */
3180 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3181 return emulate_gp(ctxt, 0);
3182
3183 /* Disable writeback. */
3184 ctxt->dst.type = OP_NONE;
3185 return X86EMUL_CONTINUE;
3186}
3187
e1e210b0
TY		 3188static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3189{
3190 u64 msr_data;
3191
dd856efa
AK		 3192 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3193 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3194 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3195 return emulate_gp(ctxt, 0);
3196
3197 return X86EMUL_CONTINUE;
3198}
3199
3200static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3201{
3202 u64 msr_data;
3203
dd856efa 3204 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3205 return emulate_gp(ctxt, 0);
3206
dd856efa
AK		 3207 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3208 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3209 return X86EMUL_CONTINUE;
3210}
3211
1bd5f469
TY		 3212static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3213{
9dac77fa 3214 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3215 return emulate_ud(ctxt);
3216
9dac77fa 3217 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3218 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3219 ctxt->dst.bytes = 2;
1bd5f469
TY		 3220 return X86EMUL_CONTINUE;
3221}
3222
3223static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3224{
9dac77fa 3225 u16 sel = ctxt->src.val;
1bd5f469 3226
9dac77fa 3227 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3228 return emulate_ud(ctxt);
3229
9dac77fa 3230 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3231 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3232
3233 /* Disable writeback. */
9dac77fa
AK		 3234 ctxt->dst.type = OP_NONE;
3235 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3236}
3237
a14e579f
AK		 3238static int em_lldt(struct x86_emulate_ctxt *ctxt)
3239{
3240 u16 sel = ctxt->src.val;
3241
3242 /* Disable writeback. */
3243 ctxt->dst.type = OP_NONE;
3244 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3245}
3246
80890006
AK		 3247static int em_ltr(struct x86_emulate_ctxt *ctxt)
3248{
3249 u16 sel = ctxt->src.val;
3250
3251 /* Disable writeback. */
3252 ctxt->dst.type = OP_NONE;
3253 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3254}
3255
38503911
AK		 3256static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3257{
9fa088f4
AK		 3258 int rc;
3259 ulong linear;
3260
9dac77fa 3261 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3262 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3263 ctxt->ops->invlpg(ctxt, linear);
38503911 3264 /* Disable writeback. */
9dac77fa 3265 ctxt->dst.type = OP_NONE;
38503911
AK		 3266 return X86EMUL_CONTINUE;
3267}
3268
2d04a05b
AK		 3269static int em_clts(struct x86_emulate_ctxt *ctxt)
3270{
3271 ulong cr0;
3272
3273 cr0 = ctxt->ops->get_cr(ctxt, 0);
3274 cr0 &= ~X86_CR0_TS;
3275 ctxt->ops->set_cr(ctxt, 0, cr0);
3276 return X86EMUL_CONTINUE;
3277}
3278
26d05cc7
AK		 3279static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3280{
0f54a321 3281 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3282
26d05cc7
AK		 3283 if (rc != X86EMUL_CONTINUE)
3284 return rc;
3285
3286 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3287 ctxt->_eip = ctxt->eip;
26d05cc7 3288 /* Disable writeback. */
9dac77fa 3289 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3290 return X86EMUL_CONTINUE;
3291}
3292
96051572
AK		 3293static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3294 void (*get)(struct x86_emulate_ctxt *ctxt,
3295 struct desc_ptr *ptr))
3296{
3297 struct desc_ptr desc_ptr;
3298
3299 if (ctxt->mode == X86EMUL_MODE_PROT64)
3300 ctxt->op_bytes = 8;
3301 get(ctxt, &desc_ptr);
3302 if (ctxt->op_bytes == 2) {
3303 ctxt->op_bytes = 4;
3304 desc_ptr.address &= 0x00ffffff;
3305 }
3306 /* Disable writeback. */
3307 ctxt->dst.type = OP_NONE;
3308 return segmented_write(ctxt, ctxt->dst.addr.mem,
3309 &desc_ptr, 2 + ctxt->op_bytes);
3310}
3311
3312static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3313{
3314 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3315}
3316
3317static int em_sidt(struct x86_emulate_ctxt *ctxt)
3318{
3319 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3320}
3321
5b7f6a1e 3322static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3323{
26d05cc7
AK		 3324 struct desc_ptr desc_ptr;
3325 int rc;
3326
510425ff
AK		 3327 if (ctxt->mode == X86EMUL_MODE_PROT64)
3328 ctxt->op_bytes = 8;
9dac77fa 3329 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3330 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3331 ctxt->op_bytes);
26d05cc7
AK		 3332 if (rc != X86EMUL_CONTINUE)
3333 return rc;
9a9abf6b
NA		 3334 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3335 is_noncanonical_address(desc_ptr.address))
3336 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3337 if (lgdt)
3338 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3339 else
3340 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3341 /* Disable writeback. */
9dac77fa 3342 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3343 return X86EMUL_CONTINUE;
3344}
3345
5b7f6a1e
NA		 3346static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3347{
3348 return em_lgdt_lidt(ctxt, true);
3349}
3350
5ef39c71 3351static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3352{
26d05cc7
AK		 3353 int rc;
3354
5ef39c71
AK		 3355 rc = ctxt->ops->fix_hypercall(ctxt);
3356
26d05cc7 3357 /* Disable writeback. */
9dac77fa 3358 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3359 return rc;
3360}
3361
3362static int em_lidt(struct x86_emulate_ctxt *ctxt)
3363{
5b7f6a1e 3364 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3365}
3366
3367static int em_smsw(struct x86_emulate_ctxt *ctxt)
3368{
32e94d06
NA		 3369 if (ctxt->dst.type == OP_MEM)
3370 ctxt->dst.bytes = 2;
9dac77fa 3371 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3372 return X86EMUL_CONTINUE;
3373}
3374
3375static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3376{
26d05cc7 3377 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3378 | (ctxt->src.val & 0x0f));
3379 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3380 return X86EMUL_CONTINUE;
3381}
3382
d06e03ad
TY		 3383static int em_loop(struct x86_emulate_ctxt *ctxt)
3384{
234f3ce4
NA		 3385 int rc = X86EMUL_CONTINUE;
3386
dd856efa
AK		 3387 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3388 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3389 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3390 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3391
234f3ce4 3392 return rc;
d06e03ad
TY		 3393}
3394
3395static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3396{
234f3ce4
NA		 3397 int rc = X86EMUL_CONTINUE;
3398
dd856efa 3399 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3400 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3401
234f3ce4 3402 return rc;
d06e03ad
TY		 3403}
3404
d7841a4b
TY		 3405static int em_in(struct x86_emulate_ctxt *ctxt)
3406{
3407 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3408 &ctxt->dst.val))
3409 return X86EMUL_IO_NEEDED;
3410
3411 return X86EMUL_CONTINUE;
3412}
3413
3414static int em_out(struct x86_emulate_ctxt *ctxt)
3415{
3416 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3417 &ctxt->src.val, 1);
3418 /* Disable writeback. */
3419 ctxt->dst.type = OP_NONE;
3420 return X86EMUL_CONTINUE;
3421}
3422
f411e6cd
TY		 3423static int em_cli(struct x86_emulate_ctxt *ctxt)
3424{
3425 if (emulator_bad_iopl(ctxt))
3426 return emulate_gp(ctxt, 0);
3427
3428 ctxt->eflags &= ~X86_EFLAGS_IF;
3429 return X86EMUL_CONTINUE;
3430}
3431
3432static int em_sti(struct x86_emulate_ctxt *ctxt)
3433{
3434 if (emulator_bad_iopl(ctxt))
3435 return emulate_gp(ctxt, 0);
3436
3437 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3438 ctxt->eflags |= X86_EFLAGS_IF;
3439 return X86EMUL_CONTINUE;
3440}
3441
6d6eede4
AK		 3442static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3443{
3444 u32 eax, ebx, ecx, edx;
3445
dd856efa
AK		 3446 eax = reg_read(ctxt, VCPU_REGS_RAX);
3447 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3448 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3449 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3450 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3451 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3452 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3453 return X86EMUL_CONTINUE;
3454}
3455
98f73630
PB		 3456static int em_sahf(struct x86_emulate_ctxt *ctxt)
3457{
3458 u32 flags;
3459
3460 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3461 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3462
3463 ctxt->eflags &= ~0xffUL;
3464 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3465 return X86EMUL_CONTINUE;
3466}
3467
2dd7caa0
AK		 3468static int em_lahf(struct x86_emulate_ctxt *ctxt)
3469{
dd856efa
AK		 3470 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3471 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3472 return X86EMUL_CONTINUE;
3473}
3474
9299836e
AK		 3475static int em_bswap(struct x86_emulate_ctxt *ctxt)
3476{
3477 switch (ctxt->op_bytes) {
3478#ifdef CONFIG_X86_64
3479 case 8:
3480 asm("bswap %0" : "+r"(ctxt->dst.val));
3481 break;
3482#endif
3483 default:
3484 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3485 break;
3486 }
3487 return X86EMUL_CONTINUE;
3488}
3489
13e457e0
NA		 3490static int em_clflush(struct x86_emulate_ctxt *ctxt)
3491{
3492 /* emulating clflush regardless of cpuid */
3493 return X86EMUL_CONTINUE;
3494}
3495
cfec82cb
JR		 3496static bool valid_cr(int nr)
3497{
3498 switch (nr) {
3499 case 0:
3500 case 2 ... 4:
3501 case 8:
3502 return true;
3503 default:
3504 return false;
3505 }
3506}
3507
3508static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3509{
9dac77fa 3510 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3511 return emulate_ud(ctxt);
3512
3513 return X86EMUL_CONTINUE;
3514}
3515
3516static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3517{
9dac77fa
AK		 3518 u64 new_val = ctxt->src.val64;
3519 int cr = ctxt->modrm_reg;
c2ad2bb3 3520 u64 efer = 0;
cfec82cb
JR		 3521
3522 static u64 cr_reserved_bits[] = {
3523 0xffffffff00000000ULL,
3524 0, 0, 0, /* CR3 checked later */
3525 CR4_RESERVED_BITS,
3526 0, 0, 0,
3527 CR8_RESERVED_BITS,
3528 };
3529
3530 if (!valid_cr(cr))
3531 return emulate_ud(ctxt);
3532
3533 if (new_val & cr_reserved_bits[cr])
3534 return emulate_gp(ctxt, 0);
3535
3536 switch (cr) {
3537 case 0: {
c2ad2bb3 3538 u64 cr4;
cfec82cb
JR		 3539 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3540 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3541 return emulate_gp(ctxt, 0);
3542
717746e3
AK		 3543 cr4 = ctxt->ops->get_cr(ctxt, 4);
3544 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3545
3546 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3547 !(cr4 & X86_CR4_PAE))
3548 return emulate_gp(ctxt, 0);
3549
3550 break;
3551 }
3552 case 3: {
3553 u64 rsvd = 0;
3554
c2ad2bb3
AK		 3555 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3556 if (efer & EFER_LMA)
9d88fca7 3557 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3558
3559 if (new_val & rsvd)
3560 return emulate_gp(ctxt, 0);
3561
3562 break;
3563 }
3564 case 4: {
717746e3 3565 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3566
3567 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3568 return emulate_gp(ctxt, 0);
3569
3570 break;
3571 }
3572 }
3573
3574 return X86EMUL_CONTINUE;
3575}
3576
3b88e41a
JR		 3577static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3578{
3579 unsigned long dr7;
3580
717746e3 3581 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3582
3583 /* Check if DR7.Global_Enable is set */
3584 return dr7 & (1 << 13);
3585}
3586
3587static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3588{
9dac77fa 3589 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3590 u64 cr4;
3591
3592 if (dr > 7)
3593 return emulate_ud(ctxt);
3594
717746e3 3595 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3596 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3597 return emulate_ud(ctxt);
3598
6d2a0526
NA		 3599 if (check_dr7_gd(ctxt)) {
3600 ulong dr6;
3601
3602 ctxt->ops->get_dr(ctxt, 6, &dr6);
3603 dr6 &= ~15;
3604 dr6 |= DR6_BD | DR6_RTM;
3605 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3606 return emulate_db(ctxt);
6d2a0526 3607 }
3b88e41a
JR		 3608
3609 return X86EMUL_CONTINUE;
3610}
3611
3612static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3613{
9dac77fa
AK		 3614 u64 new_val = ctxt->src.val64;
3615 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3616
3617 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3618 return emulate_gp(ctxt, 0);
3619
3620 return check_dr_read(ctxt);
3621}
3622
01de8b09
JR		 3623static int check_svme(struct x86_emulate_ctxt *ctxt)
3624{
3625 u64 efer;
3626
717746e3 3627 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3628
3629 if (!(efer & EFER_SVME))
3630 return emulate_ud(ctxt);
3631
3632 return X86EMUL_CONTINUE;
3633}
3634
3635static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3636{
dd856efa 3637 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3638
3639 /* Valid physical address? */
d4224449 3640 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3641 return emulate_gp(ctxt, 0);
3642
3643 return check_svme(ctxt);
3644}
3645
d7eb8203
JR		 3646static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3647{
717746e3 3648 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3649
717746e3 3650 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3651 return emulate_ud(ctxt);
3652
3653 return X86EMUL_CONTINUE;
3654}
3655
8061252e
JR		 3656static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3657{
717746e3 3658 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3659 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3660
717746e3 3661 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3662 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3663 return emulate_gp(ctxt, 0);
3664
3665 return X86EMUL_CONTINUE;
3666}
3667
f6511935
JR		 3668static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3669{
9dac77fa
AK		 3670 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3671 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3672 return emulate_gp(ctxt, 0);
3673
3674 return X86EMUL_CONTINUE;
3675}
3676
3677static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3678{
9dac77fa
AK		 3679 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3680 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3681 return emulate_gp(ctxt, 0);
3682
3683 return X86EMUL_CONTINUE;
3684}
3685
73fba5f4 3686#define D(_y) { .flags = (_y) }
d40a6898
PB		 3687#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3688#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3689 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3690#define N D(NotImpl)
01de8b09 3691#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3692#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3693#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3694#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3695#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3696#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3697#define II(_f, _e, _i) \
d40a6898 3698 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3699#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3700 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3701 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3702#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3703
8d8f4e9f 3704#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3705#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3706#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3707#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3708#define I2bvIP(_f, _e, _i, _p) \
3709 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3710
fb864fbc
AK		 3711#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3712 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3713 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3714
0f54a321
NA		 3715static const struct opcode group7_rm0[] = {
3716 N,
3717 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3718 N, N, N, N, N, N,
3719};
3720
fd0a0d82 3721static const struct opcode group7_rm1[] = {
1c2545be
TY		 3722 DI(SrcNone | Priv, monitor),
3723 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3724 N, N, N, N, N, N,
3725};
3726
fd0a0d82 3727static const struct opcode group7_rm3[] = {
1c2545be 3728 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3729 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3730 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3731 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3732 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3733 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3734 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3735 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3736};
6230f7fc 3737
fd0a0d82 3738static const struct opcode group7_rm7[] = {
d7eb8203 3739 N,
1c2545be 3740 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3741 N, N, N, N, N, N,
3742};
d67fc27a 3743
fd0a0d82 3744static const struct opcode group1[] = {
fb864fbc
AK		 3745 F(Lock, em_add),
3746 F(Lock | PageTable, em_or),
3747 F(Lock, em_adc),
3748 F(Lock, em_sbb),
3749 F(Lock | PageTable, em_and),
3750 F(Lock, em_sub),
3751 F(Lock, em_xor),
3752 F(NoWrite, em_cmp),
73fba5f4
AK		 3753};
3754
fd0a0d82 3755static const struct opcode group1A[] = {
1c2545be 3756 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3757};
3758
007a3b54
AK		 3759static const struct opcode group2[] = {
3760 F(DstMem | ModRM, em_rol),
3761 F(DstMem | ModRM, em_ror),
3762 F(DstMem | ModRM, em_rcl),
3763 F(DstMem | ModRM, em_rcr),
3764 F(DstMem | ModRM, em_shl),
3765 F(DstMem | ModRM, em_shr),
3766 F(DstMem | ModRM, em_shl),
3767 F(DstMem | ModRM, em_sar),
3768};
3769
fd0a0d82 3770static const struct opcode group3[] = {
fb864fbc
AK		 3771 F(DstMem | SrcImm | NoWrite, em_test),
3772 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3773 F(DstMem | SrcNone | Lock, em_not),
3774 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3775 F(DstXacc | Src2Mem, em_mul_ex),
3776 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3777 F(DstXacc | Src2Mem, em_div_ex),
3778 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3779};
3780
fd0a0d82 3781static const struct opcode group4[] = {
95413dc4
AK		 3782 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3783 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3784 N, N, N, N, N, N,
3785};
3786
fd0a0d82 3787static const struct opcode group5[] = {
95413dc4
AK		 3788 F(DstMem | SrcNone | Lock, em_inc),
3789 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3790 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3791 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3792 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3793 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3794 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3795};
3796
fd0a0d82 3797static const struct opcode group6[] = {
1c2545be
TY		 3798 DI(Prot, sldt),
3799 DI(Prot, str),
a14e579f 3800 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3801 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3802 N, N, N, N,
3803};
3804
fd0a0d82 3805static const struct group_dual group7 = { {
606b1c3e
NA		 3806 II(Mov | DstMem, em_sgdt, sgdt),
3807 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3808 II(SrcMem | Priv, em_lgdt, lgdt),
3809 II(SrcMem | Priv, em_lidt, lidt),
3810 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3811 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3812 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3813}, {
0f54a321 3814 EXT(0, group7_rm0),
5ef39c71 3815 EXT(0, group7_rm1),
01de8b09 3816 N, EXT(0, group7_rm3),
1c2545be
TY		 3817 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3818 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3819 EXT(0, group7_rm7),
73fba5f4
AK		 3820} };
3821
fd0a0d82 3822static const struct opcode group8[] = {
73fba5f4 3823 N, N, N, N,
11c363ba
AK		 3824 F(DstMem | SrcImmByte | NoWrite, em_bt),
3825 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3826 F(DstMem | SrcImmByte | Lock, em_btr),
3827 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3828};
3829
fd0a0d82 3830static const struct group_dual group9 = { {
1c2545be 3831 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3832}, {
3833 N, N, N, N, N, N, N, N,
3834} };
3835
fd0a0d82 3836static const struct opcode group11[] = {
1c2545be 3837 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3838 X7(D(Undefined)),
a4d4a7c1
AK		 3839};
3840
13e457e0 3841static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3842 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3843};
3844
3845static const struct group_dual group15 = { {
3846 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3847}, {
3848 N, N, N, N, N, N, N, N,
3849} };
3850
fd0a0d82 3851static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3852 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3853};
3854
d5b77069
PB		 3855static const struct gprefix pfx_0f_2b = {
3856 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3857};
3858
27ce8258 3859static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3860 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3861};
3862
0a37027e
AW		 3863static const struct gprefix pfx_0f_e7 = {
3864 N, I(Sse, em_mov), N, N,
3865};
3866
045a282c
GN		 3867static const struct escape escape_d9 = { {
3868 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3869}, {
3870 /* 0xC0 - 0xC7 */
3871 N, N, N, N, N, N, N, N,
3872 /* 0xC8 - 0xCF */
3873 N, N, N, N, N, N, N, N,
3874 /* 0xD0 - 0xC7 */
3875 N, N, N, N, N, N, N, N,
3876 /* 0xD8 - 0xDF */
3877 N, N, N, N, N, N, N, N,
3878 /* 0xE0 - 0xE7 */
3879 N, N, N, N, N, N, N, N,
3880 /* 0xE8 - 0xEF */
3881 N, N, N, N, N, N, N, N,
3882 /* 0xF0 - 0xF7 */
3883 N, N, N, N, N, N, N, N,
3884 /* 0xF8 - 0xFF */
3885 N, N, N, N, N, N, N, N,
3886} };
3887
3888static const struct escape escape_db = { {
3889 N, N, N, N, N, N, N, N,
3890}, {
3891 /* 0xC0 - 0xC7 */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xC8 - 0xCF */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xD0 - 0xC7 */
3896 N, N, N, N, N, N, N, N,
3897 /* 0xD8 - 0xDF */
3898 N, N, N, N, N, N, N, N,
3899 /* 0xE0 - 0xE7 */
3900 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3901 /* 0xE8 - 0xEF */
3902 N, N, N, N, N, N, N, N,
3903 /* 0xF0 - 0xF7 */
3904 N, N, N, N, N, N, N, N,
3905 /* 0xF8 - 0xFF */
3906 N, N, N, N, N, N, N, N,
3907} };
3908
3909static const struct escape escape_dd = { {
3910 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3911}, {
3912 /* 0xC0 - 0xC7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xC8 - 0xCF */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xD0 - 0xC7 */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xD8 - 0xDF */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xE0 - 0xE7 */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xE8 - 0xEF */
3923 N, N, N, N, N, N, N, N,
3924 /* 0xF0 - 0xF7 */
3925 N, N, N, N, N, N, N, N,
3926 /* 0xF8 - 0xFF */
3927 N, N, N, N, N, N, N, N,
3928} };
3929
fd0a0d82 3930static const struct opcode opcode_table[256] = {
73fba5f4 3931 /* 0x00 - 0x07 */
fb864fbc 3932 F6ALU(Lock, em_add),
1cd196ea
AK		 3933 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3934 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3935 /* 0x08 - 0x0F */
fb864fbc 3936 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3937 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3938 N,
73fba5f4 3939 /* 0x10 - 0x17 */
fb864fbc 3940 F6ALU(Lock, em_adc),
1cd196ea
AK		 3941 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3942 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3943 /* 0x18 - 0x1F */
fb864fbc 3944 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3945 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3946 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3947 /* 0x20 - 0x27 */
fb864fbc 3948 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3949 /* 0x28 - 0x2F */
fb864fbc 3950 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3951 /* 0x30 - 0x37 */
fb864fbc 3952 F6ALU(Lock, em_xor), N, N,
73fba5f4 3953 /* 0x38 - 0x3F */
fb864fbc 3954 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3955 /* 0x40 - 0x4F */
95413dc4 3956 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3957 /* 0x50 - 0x57 */
63540382 3958 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3959 /* 0x58 - 0x5F */
c54fe504 3960 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3961 /* 0x60 - 0x67 */
b96a7fad
TY		 3962 I(ImplicitOps | Stack | No64, em_pusha),
3963 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3964 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3965 N, N, N, N,
3966 /* 0x68 - 0x6F */
d46164db
AK		 3967 I(SrcImm | Mov | Stack, em_push),
3968 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3969 I(SrcImmByte | Mov | Stack, em_push),
3970 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3971 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3972 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3973 /* 0x70 - 0x7F */
58b7075d 3974 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3975 /* 0x80 - 0x87 */
1c2545be
TY		 3976 G(ByteOp | DstMem | SrcImm, group1),
3977 G(DstMem | SrcImm, group1),
3978 G(ByteOp | DstMem | SrcImm | No64, group1),
3979 G(DstMem | SrcImmByte, group1),
fb864fbc 3980 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3981 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3982 /* 0x88 - 0x8F */
d5ae7ce8 3983 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3984 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3985 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3986 D(ModRM | SrcMem | NoAccess | DstReg),
3987 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3988 G(0, group1A),
73fba5f4 3989 /* 0x90 - 0x97 */
bf608f88 3990 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3991 /* 0x98 - 0x9F */
61429142 3992 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3993 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3994 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3995 II(ImplicitOps | Stack, em_popf, popf),
3996 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3997 /* 0xA0 - 0xA7 */
b9eac5f4 3998 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3999 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4000 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4001 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4002 /* 0xA8 - 0xAF */
fb864fbc 4003 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4004 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4005 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4006 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4007 /* 0xB0 - 0xB7 */
b9eac5f4 4008 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4009 /* 0xB8 - 0xBF */
5e2c6883 4010 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4011 /* 0xC0 - 0xC7 */
007a3b54 4012 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4013 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4014 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4015 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4016 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4017 G(ByteOp, group11), G(0, group11),
73fba5f4 4018 /* 0xC8 - 0xCF */
612e89f0 4019 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4020 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4021 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4022 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4023 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4024 /* 0xD0 - 0xD7 */
007a3b54
AK		 4025 G(Src2One | ByteOp, group2), G(Src2One, group2),
4026 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4027 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4028 I(DstAcc | SrcImmUByte | No64, em_aad),
4029 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4030 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4031 /* 0xD8 - 0xDF */
045a282c 4032 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4033 /* 0xE0 - 0xE7 */
58b7075d
NA		 4034 X3(I(SrcImmByte | NearBranch, em_loop)),
4035 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4036 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4037 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4038 /* 0xE8 - 0xEF */
58b7075d
NA		 4039 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4040 I(SrcImmFAddr | No64, em_jmp_far),
4041 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4042 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4043 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4044 /* 0xF0 - 0xF7 */
bf608f88 4045 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4046 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4047 G(ByteOp, group3), G(0, group3),
73fba5f4 4048 /* 0xF8 - 0xFF */
f411e6cd
TY		 4049 D(ImplicitOps), D(ImplicitOps),
4050 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4051 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4052};
4053
fd0a0d82 4054static const struct opcode twobyte_table[256] = {
73fba5f4 4055 /* 0x00 - 0x0F */
dee6bb70 4056 G(0, group6), GD(0, &group7), N, N,
b51e974f 4057 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4058 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4059 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4060 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4061 /* 0x10 - 0x1F */
103f98ea 4062 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4063 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4064 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4065 /* 0x20 - 0x2F */
9b88ae99
NA		 4066 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4067 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4068 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4069 check_cr_write),
4070 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4071 check_dr_write),
73fba5f4 4072 N, N, N, N,
27ce8258
IM		 4073 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4074 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4075 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4076 N, N, N, N,
73fba5f4 4077 /* 0x30 - 0x3F */
e1e210b0 4078 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4079 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4080 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4081 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4082 I(ImplicitOps | EmulateOnUD, em_sysenter),
4083 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4084 N, N,
73fba5f4
AK		 4085 N, N, N, N, N, N, N, N,
4086 /* 0x40 - 0x4F */
140bad89 4087 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4088 /* 0x50 - 0x5F */
4089 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4090 /* 0x60 - 0x6F */
aa97bb48
AK		 4091 N, N, N, N,
4092 N, N, N, N,
4093 N, N, N, N,
4094 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4095 /* 0x70 - 0x7F */
aa97bb48
AK		 4096 N, N, N, N,
4097 N, N, N, N,
4098 N, N, N, N,
4099 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4100 /* 0x80 - 0x8F */
58b7075d 4101 X16(D(SrcImm | NearBranch)),
73fba5f4 4102 /* 0x90 - 0x9F */
ee45b58e 4103 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4104 /* 0xA0 - 0xA7 */
1cd196ea 4105 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4106 II(ImplicitOps, em_cpuid, cpuid),
4107 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4108 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4109 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4110 /* 0xA8 - 0xAF */
1cd196ea 4111 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4112 DI(ImplicitOps, rsm),
11c363ba 4113 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4114 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4115 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4116 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4117 /* 0xB0 - 0xB7 */
e940b5c2 4118 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4119 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4120 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4121 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4122 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4123 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4124 /* 0xB8 - 0xBF */
4125 N, N,
ce7faab2 4126 G(BitOp, group8),
11c363ba
AK		 4127 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4128 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4129 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4130 /* 0xC0 - 0xC7 */
e47a5f5f 4131 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
ed9aad21 4132 N, I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov),
73fba5f4 4133 N, N, N, GD(0, &group9),
9299836e
AK		 4134 /* 0xC8 - 0xCF */
4135 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4136 /* 0xD0 - 0xDF */
4137 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4138 /* 0xE0 - 0xEF */
0a37027e
AW		 4139 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4140 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4141 /* 0xF0 - 0xFF */
4142 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4143};
4144
0bc5eedb 4145static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4146 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4147};
4148
4149static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4150 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4151};
4152
4153/*
4154 * Insns below are selected by the prefix which indexed by the third opcode
4155 * byte.
4156 */
4157static const struct opcode opcode_map_0f_38[256] = {
4158 /* 0x00 - 0x7f */
4159 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4160 /* 0x80 - 0xef */
4161 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4162 /* 0xf0 - 0xf1 */
4163 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4164 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4165 /* 0xf2 - 0xff */
4166 N, N, X4(N), X8(N)
0bc5eedb
BP		 4167};
4168
73fba5f4
AK		 4169#undef D
4170#undef N
4171#undef G
4172#undef GD
4173#undef I
aa97bb48 4174#undef GP
01de8b09 4175#undef EXT
73fba5f4 4176
8d8f4e9f 4177#undef D2bv
f6511935 4178#undef D2bvIP
8d8f4e9f 4179#undef I2bv
d7841a4b 4180#undef I2bvIP
d67fc27a 4181#undef I6ALU
8d8f4e9f 4182
9dac77fa 4183static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4184{
4185 unsigned size;
4186
9dac77fa 4187 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4188 if (size == 8)
4189 size = 4;
4190 return size;
4191}
4192
4193static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4194 unsigned size, bool sign_extension)
4195{
39f21ee5
AK		 4196 int rc = X86EMUL_CONTINUE;
4197
4198 op->type = OP_IMM;
4199 op->bytes = size;
9dac77fa 4200 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4201 /* NB. Immediates are sign-extended as necessary. */
4202 switch (op->bytes) {
4203 case 1:
e85a1085 4204 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4205 break;
4206 case 2:
e85a1085 4207 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4208 break;
4209 case 4:
e85a1085 4210 op->val = insn_fetch(s32, ctxt);
39f21ee5 4211 break;
5e2c6883
NA		 4212 case 8:
4213 op->val = insn_fetch(s64, ctxt);
4214 break;
39f21ee5
AK		 4215 }
4216 if (!sign_extension) {
4217 switch (op->bytes) {
4218 case 1:
4219 op->val &= 0xff;
4220 break;
4221 case 2:
4222 op->val &= 0xffff;
4223 break;
4224 case 4:
4225 op->val &= 0xffffffff;
4226 break;
4227 }
4228 }
4229done:
4230 return rc;
4231}
4232
a9945549
AK		 4233static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4234 unsigned d)
4235{
4236 int rc = X86EMUL_CONTINUE;
4237
4238 switch (d) {
4239 case OpReg:
2adb5ad9 4240 decode_register_operand(ctxt, op);
a9945549
AK		 4241 break;
4242 case OpImmUByte:
608aabe3 4243 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4244 break;
4245 case OpMem:
41ddf978 4246 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4247 mem_common:
4248 *op = ctxt->memop;
4249 ctxt->memopp = op;
96888977 4250 if (ctxt->d & BitOp)
a9945549
AK		 4251 fetch_bit_operand(ctxt);
4252 op->orig_val = op->val;
4253 break;
41ddf978 4254 case OpMem64:
aaa05f24 4255 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4256 goto mem_common;
a9945549
AK		 4257 case OpAcc:
4258 op->type = OP_REG;
4259 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4260 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4261 fetch_register_operand(op);
4262 op->orig_val = op->val;
4263 break;
820207c8
AK		 4264 case OpAccLo:
4265 op->type = OP_REG;
4266 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4267 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4268 fetch_register_operand(op);
4269 op->orig_val = op->val;
4270 break;
4271 case OpAccHi:
4272 if (ctxt->d & ByteOp) {
4273 op->type = OP_NONE;
4274 break;
4275 }
4276 op->type = OP_REG;
4277 op->bytes = ctxt->op_bytes;
4278 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4279 fetch_register_operand(op);
4280 op->orig_val = op->val;
4281 break;
a9945549
AK		 4282 case OpDI:
4283 op->type = OP_MEM;
4284 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4285 op->addr.mem.ea =
dd856efa 4286 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4287 op->addr.mem.seg = VCPU_SREG_ES;
4288 op->val = 0;
b3356bf0 4289 op->count = 1;
a9945549
AK		 4290 break;
4291 case OpDX:
4292 op->type = OP_REG;
4293 op->bytes = 2;
dd856efa 4294 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4295 fetch_register_operand(op);
4296 break;
4dd6a57d
AK		 4297 case OpCL:
4298 op->bytes = 1;
dd856efa 4299 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4300 break;
4301 case OpImmByte:
4302 rc = decode_imm(ctxt, op, 1, true);
4303 break;
4304 case OpOne:
4305 op->bytes = 1;
4306 op->val = 1;
4307 break;
4308 case OpImm:
4309 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4310 break;
5e2c6883
NA		 4311 case OpImm64:
4312 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4313 break;
28867cee
AK		 4314 case OpMem8:
4315 ctxt->memop.bytes = 1;
660696d1 4316 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4317 ctxt->memop.addr.reg = decode_register(ctxt,
4318 ctxt->modrm_rm, true);
660696d1
GN		 4319 fetch_register_operand(&ctxt->memop);
4320 }
28867cee 4321 goto mem_common;
0fe59128
AK		 4322 case OpMem16:
4323 ctxt->memop.bytes = 2;
4324 goto mem_common;
4325 case OpMem32:
4326 ctxt->memop.bytes = 4;
4327 goto mem_common;
4328 case OpImmU16:
4329 rc = decode_imm(ctxt, op, 2, false);
4330 break;
4331 case OpImmU:
4332 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4333 break;
4334 case OpSI:
4335 op->type = OP_MEM;
4336 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4337 op->addr.mem.ea =
dd856efa 4338 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4339 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4340 op->val = 0;
b3356bf0 4341 op->count = 1;
0fe59128 4342 break;
7fa57952
PB		 4343 case OpXLat:
4344 op->type = OP_MEM;
4345 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4346 op->addr.mem.ea =
4347 register_address(ctxt,
4348 reg_read(ctxt, VCPU_REGS_RBX) +
4349 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4350 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4351 op->val = 0;
4352 break;
0fe59128
AK		 4353 case OpImmFAddr:
4354 op->type = OP_IMM;
4355 op->addr.mem.ea = ctxt->_eip;
4356 op->bytes = ctxt->op_bytes + 2;
4357 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4358 break;
4359 case OpMemFAddr:
4360 ctxt->memop.bytes = ctxt->op_bytes + 2;
4361 goto mem_common;
c191a7a0
AK		 4362 case OpES:
4363 op->val = VCPU_SREG_ES;
4364 break;
4365 case OpCS:
4366 op->val = VCPU_SREG_CS;
4367 break;
4368 case OpSS:
4369 op->val = VCPU_SREG_SS;
4370 break;
4371 case OpDS:
4372 op->val = VCPU_SREG_DS;
4373 break;
4374 case OpFS:
4375 op->val = VCPU_SREG_FS;
4376 break;
4377 case OpGS:
4378 op->val = VCPU_SREG_GS;
4379 break;
a9945549
AK		 4380 case OpImplicit:
4381 /* Special instructions do their own operand decoding. */
4382 default:
4383 op->type = OP_NONE; /* Disable writeback. */
4384 break;
4385 }
4386
4387done:
4388 return rc;
4389}
4390
ef5d75cc 4391int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4392{
dde7e6d1
AK		 4393 int rc = X86EMUL_CONTINUE;
4394 int mode = ctxt->mode;
46561646 4395 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4396 bool op_prefix = false;
573e80fe 4397 bool has_seg_override = false;
46561646 4398 struct opcode opcode;
dde7e6d1 4399
f09ed83e
AK		 4400 ctxt->memop.type = OP_NONE;
4401 ctxt->memopp = NULL;
9dac77fa 4402 ctxt->_eip = ctxt->eip;
17052f16
PB		 4403 ctxt->fetch.ptr = ctxt->fetch.data;
4404 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4405 ctxt->opcode_len = 1;
dc25e89e 4406 if (insn_len > 0)
9dac77fa 4407 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4408 else {
9506d57d 4409 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4410 if (rc != X86EMUL_CONTINUE)
4411 return rc;
4412 }
dde7e6d1
AK		 4413
4414 switch (mode) {
4415 case X86EMUL_MODE_REAL:
4416 case X86EMUL_MODE_VM86:
4417 case X86EMUL_MODE_PROT16:
4418 def_op_bytes = def_ad_bytes = 2;
4419 break;
4420 case X86EMUL_MODE_PROT32:
4421 def_op_bytes = def_ad_bytes = 4;
4422 break;
4423#ifdef CONFIG_X86_64
4424 case X86EMUL_MODE_PROT64:
4425 def_op_bytes = 4;
4426 def_ad_bytes = 8;
4427 break;
4428#endif
4429 default:
1d2887e2 4430 return EMULATION_FAILED;
dde7e6d1
AK		 4431 }
4432
9dac77fa
AK		 4433 ctxt->op_bytes = def_op_bytes;
4434 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4435
4436 /* Legacy prefixes. */
4437 for (;;) {
e85a1085 4438 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4439 case 0x66: /* operand-size override */
0d7cdee8 4440 op_prefix = true;
dde7e6d1 4441 /* switch between 2/4 bytes */
9dac77fa 4442 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4443 break;
4444 case 0x67: /* address-size override */
4445 if (mode == X86EMUL_MODE_PROT64)
4446 /* switch between 4/8 bytes */
9dac77fa 4447 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4448 else
4449 /* switch between 2/4 bytes */
9dac77fa 4450 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4451 break;
4452 case 0x26: /* ES override */
4453 case 0x2e: /* CS override */
4454 case 0x36: /* SS override */
4455 case 0x3e: /* DS override */
573e80fe
BD		 4456 has_seg_override = true;
4457 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4458 break;
4459 case 0x64: /* FS override */
4460 case 0x65: /* GS override */
573e80fe
BD		 4461 has_seg_override = true;
4462 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4463 break;
4464 case 0x40 ... 0x4f: /* REX */
4465 if (mode != X86EMUL_MODE_PROT64)
4466 goto done_prefixes;
9dac77fa 4467 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4468 continue;
4469 case 0xf0: /* LOCK */
9dac77fa 4470 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4471 break;
4472 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4473 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4474 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4475 break;
4476 default:
4477 goto done_prefixes;
4478 }
4479
4480 /* Any legacy prefix after a REX prefix nullifies its effect. */
4481
9dac77fa 4482 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4483 }
4484
4485done_prefixes:
4486
4487 /* REX prefix. */
9dac77fa
AK		 4488 if (ctxt->rex_prefix & 8)
4489 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4490
4491 /* Opcode byte(s). */
9dac77fa 4492 opcode = opcode_table[ctxt->b];
d3ad6243 4493 /* Two-byte opcode? */
9dac77fa 4494 if (ctxt->b == 0x0f) {
1ce19dc1 4495 ctxt->opcode_len = 2;
e85a1085 4496 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4497 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4498
4499 /* 0F_38 opcode map */
4500 if (ctxt->b == 0x38) {
4501 ctxt->opcode_len = 3;
4502 ctxt->b = insn_fetch(u8, ctxt);
4503 opcode = opcode_map_0f_38[ctxt->b];
4504 }
dde7e6d1 4505 }
9dac77fa 4506 ctxt->d = opcode.flags;
dde7e6d1 4507
9f4260e7
TY		 4508 if (ctxt->d & ModRM)
4509 ctxt->modrm = insn_fetch(u8, ctxt);
4510
7fe864dc
NA		 4511 /* vex-prefix instructions are not implemented */
4512 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4513 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4514 ctxt->d = NotImpl;
4515 }
4516
9dac77fa
AK		 4517 while (ctxt->d & GroupMask) {
4518 switch (ctxt->d & GroupMask) {
46561646 4519 case Group:
9dac77fa 4520 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4521 opcode = opcode.u.group[goffset];
4522 break;
4523 case GroupDual:
9dac77fa
AK		 4524 goffset = (ctxt->modrm >> 3) & 7;
4525 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4526 opcode = opcode.u.gdual->mod3[goffset];
4527 else
4528 opcode = opcode.u.gdual->mod012[goffset];
4529 break;
4530 case RMExt:
9dac77fa 4531 goffset = ctxt->modrm & 7;
01de8b09 4532 opcode = opcode.u.group[goffset];
46561646
AK		 4533 break;
4534 case Prefix:
9dac77fa 4535 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4536 return EMULATION_FAILED;
9dac77fa 4537 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4538 switch (simd_prefix) {
4539 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4540 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4541 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4542 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4543 }
4544 break;
045a282c
GN		 4545 case Escape:
4546 if (ctxt->modrm > 0xbf)
4547 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4548 else
4549 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4550 break;
46561646 4551 default:
1d2887e2 4552 return EMULATION_FAILED;
0d7cdee8 4553 }
46561646 4554
b1ea50b2 4555 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4556 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4557 }
4558
e24186e0
PB		 4559 /* Unrecognised? */
4560 if (ctxt->d == 0)
4561 return EMULATION_FAILED;
4562
9dac77fa 4563 ctxt->execute = opcode.u.execute;
dde7e6d1 4564
3a6095a0
NA		 4565 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4566 return EMULATION_FAILED;
4567
d40a6898 4568 if (unlikely(ctxt->d &
ed9aad21
NA		 4569 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4570 No16))) {
d40a6898
PB		 4571 /*
4572 * These are copied unconditionally here, and checked unconditionally
4573 * in x86_emulate_insn.
4574 */
4575 ctxt->check_perm = opcode.check_perm;
4576 ctxt->intercept = opcode.intercept;
dde7e6d1 4577
d40a6898
PB		 4578 if (ctxt->d & NotImpl)
4579 return EMULATION_FAILED;
d867162c 4580
58b7075d
NA		 4581 if (mode == X86EMUL_MODE_PROT64) {
4582 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4583 ctxt->op_bytes = 8;
4584 else if (ctxt->d & NearBranch)
4585 ctxt->op_bytes = 8;
4586 }
7f9b4b75 4587
d40a6898
PB		 4588 if (ctxt->d & Op3264) {
4589 if (mode == X86EMUL_MODE_PROT64)
4590 ctxt->op_bytes = 8;
4591 else
4592 ctxt->op_bytes = 4;
4593 }
4594
ed9aad21
NA		 4595 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4596 ctxt->op_bytes = 4;
4597
d40a6898
PB		 4598 if (ctxt->d & Sse)
4599 ctxt->op_bytes = 16;
4600 else if (ctxt->d & Mmx)
4601 ctxt->op_bytes = 8;
4602 }
1253791d 4603
dde7e6d1 4604 /* ModRM and SIB bytes. */
9dac77fa 4605 if (ctxt->d & ModRM) {
f09ed83e 4606 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4607 if (!has_seg_override) {
4608 has_seg_override = true;
4609 ctxt->seg_override = ctxt->modrm_seg;
4610 }
9dac77fa 4611 } else if (ctxt->d & MemAbs)
f09ed83e 4612 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4613 if (rc != X86EMUL_CONTINUE)
4614 goto done;
4615
573e80fe
BD		 4616 if (!has_seg_override)
4617 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4618
573e80fe 4619 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4620
dde7e6d1
AK		 4621 /*
4622 * Decode and fetch the source operand: register, memory
4623 * or immediate.
4624 */
0fe59128 4625 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4626 if (rc != X86EMUL_CONTINUE)
4627 goto done;
4628
dde7e6d1
AK		 4629 /*
4630 * Decode and fetch the second source operand: register, memory
4631 * or immediate.
4632 */
4dd6a57d 4633 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4634 if (rc != X86EMUL_CONTINUE)
4635 goto done;
4636
dde7e6d1 4637 /* Decode and fetch the destination operand: register or memory. */
a9945549 4638 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4639
41061cdb 4640 if (ctxt->rip_relative)
f09ed83e 4641 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4642
a430c916 4643done:
1d2887e2 4644 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4645}
4646
1cb3f3ae
XG		 4647bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4648{
4649 return ctxt->d & PageTable;
4650}
4651
3e2f65d5
GN		 4652static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4653{
3e2f65d5
GN		 4654 /* The second termination condition only applies for REPE
4655 * and REPNE. Test if the repeat string operation prefix is
4656 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4657 * corresponding termination condition according to:
4658 * - if REPE/REPZ and ZF = 0 then done
4659 * - if REPNE/REPNZ and ZF = 1 then done
4660 */
9dac77fa
AK		 4661 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4662 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4663 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4664 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4665 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4666 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4667 return true;
4668
4669 return false;
4670}
4671
cbe2c9d3
AK		 4672static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4673{
4674 bool fault = false;
4675
4676 ctxt->ops->get_fpu(ctxt);
4677 asm volatile("1: fwait \n\t"
4678 "2: \n\t"
4679 ".pushsection .fixup,\"ax\" \n\t"
4680 "3: \n\t"
4681 "movb $1, %[fault] \n\t"
4682 "jmp 2b \n\t"
4683 ".popsection \n\t"
4684 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4685 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4686 ctxt->ops->put_fpu(ctxt);
4687
4688 if (unlikely(fault))
4689 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4690
4691 return X86EMUL_CONTINUE;
4692}
4693
4694static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4695 struct operand *op)
4696{
4697 if (op->type == OP_MM)
4698 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4699}
4700
e28bbd44
AK		 4701static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4702{
4703 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4704 if (!(ctxt->d & ByteOp))
4705 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4706 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4707 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4708 [fastop]"+S"(fop)
4709 : "c"(ctxt->src2.val));
e28bbd44 4710 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4711 if (!fop) /* exception is returned in fop variable */
4712 return emulate_de(ctxt);
e28bbd44
AK		 4713 return X86EMUL_CONTINUE;
4714}
dd856efa 4715
1498507a
BD		 4716void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4717{
573e80fe
BD		 4718 memset(&ctxt->rip_relative, 0,
4719 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4720
1498507a
BD		 4721 ctxt->io_read.pos = 0;
4722 ctxt->io_read.end = 0;
1498507a
BD		 4723 ctxt->mem_read.end = 0;
4724}
4725
7b105ca2 4726int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4727{
0225fb50 4728 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4729 int rc = X86EMUL_CONTINUE;
9dac77fa 4730 int saved_dst_type = ctxt->dst.type;
8b4caf66 4731
9dac77fa 4732 ctxt->mem_read.pos = 0;
310b5d30 4733
e24186e0
PB		 4734 /* LOCK prefix is allowed only with some instructions */
4735 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4736 rc = emulate_ud(ctxt);
1161624f
GN		 4737 goto done;
4738 }
4739
e24186e0 4740 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4741 rc = emulate_ud(ctxt);
d380a5e4
GN		 4742 goto done;
4743 }
4744
d40a6898
PB		 4745 if (unlikely(ctxt->d &
4746 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4747 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4748 (ctxt->d & Undefined)) {
4749 rc = emulate_ud(ctxt);
4750 goto done;
4751 }
1253791d 4752
d40a6898
PB		 4753 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4754 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4755 rc = emulate_ud(ctxt);
cbe2c9d3 4756 goto done;
d40a6898 4757 }
cbe2c9d3 4758
d40a6898
PB		 4759 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4760 rc = emulate_nm(ctxt);
c4f035c6 4761 goto done;
d40a6898 4762 }
c4f035c6 4763
d40a6898
PB		 4764 if (ctxt->d & Mmx) {
4765 rc = flush_pending_x87_faults(ctxt);
4766 if (rc != X86EMUL_CONTINUE)
4767 goto done;
4768 /*
4769 * Now that we know the fpu is exception safe, we can fetch
4770 * operands from it.
4771 */
4772 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4773 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4774 if (!(ctxt->d & Mov))
4775 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4776 }
e92805ac 4777
685bbf4a 4778 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4779 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4780 X86_ICPT_PRE_EXCEPT);
4781 if (rc != X86EMUL_CONTINUE)
4782 goto done;
4783 }
8ea7d6ae 4784
d40a6898
PB		 4785 /* Privileged instruction can be executed only in CPL=0 */
4786 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4787 if (ctxt->d & PrivUD)
4788 rc = emulate_ud(ctxt);
4789 else
4790 rc = emulate_gp(ctxt, 0);
d09beabd 4791 goto done;
d40a6898 4792 }
d09beabd 4793
d40a6898
PB		 4794 /* Instruction can only be executed in protected mode */
4795 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4796 rc = emulate_ud(ctxt);
c4f035c6 4797 goto done;
d40a6898 4798 }
c4f035c6 4799
d40a6898 4800 /* Do instruction specific permission checks */
685bbf4a 4801 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4802 rc = ctxt->check_perm(ctxt);
4803 if (rc != X86EMUL_CONTINUE)
4804 goto done;
4805 }
4806
685bbf4a 4807 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4808 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4809 X86_ICPT_POST_EXCEPT);
4810 if (rc != X86EMUL_CONTINUE)
4811 goto done;
4812 }
4813
4814 if (ctxt->rep_prefix && (ctxt->d & String)) {
4815 /* All REP prefixes have the same first termination condition */
4816 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4817 ctxt->eip = ctxt->_eip;
4467c3f1 4818 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4819 goto done;
4820 }
b9fa9d6b 4821 }
b9fa9d6b
AK		 4822 }
4823
9dac77fa
AK		 4824 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4825 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4826 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4827 if (rc != X86EMUL_CONTINUE)
8b4caf66 4828 goto done;
9dac77fa 4829 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4830 }
4831
9dac77fa
AK		 4832 if (ctxt->src2.type == OP_MEM) {
4833 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4834 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4835 if (rc != X86EMUL_CONTINUE)
4836 goto done;
4837 }
4838
9dac77fa 4839 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4840 goto special_insn;
4841
4842
9dac77fa 4843 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4844 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4845 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4846 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4847 if (rc != X86EMUL_CONTINUE)
4848 goto done;
038e51de 4849 }
9dac77fa 4850 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4851
018a98db
AK		 4852special_insn:
4853
685bbf4a 4854 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4855 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4856 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4857 if (rc != X86EMUL_CONTINUE)
4858 goto done;
4859 }
4860
b9a1ecb9
NA		 4861 if (ctxt->rep_prefix && (ctxt->d & String))
4862 ctxt->eflags |= EFLG_RF;
4863 else
4864 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4865
9dac77fa 4866 if (ctxt->execute) {
e28bbd44
AK		 4867 if (ctxt->d & Fastop) {
4868 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4869 rc = fastop(ctxt, fop);
4870 if (rc != X86EMUL_CONTINUE)
4871 goto done;
4872 goto writeback;
4873 }
9dac77fa 4874 rc = ctxt->execute(ctxt);
ef65c889
AK		 4875 if (rc != X86EMUL_CONTINUE)
4876 goto done;
4877 goto writeback;
4878 }
4879
1ce19dc1 4880 if (ctxt->opcode_len == 2)
6aa8b732 4881 goto twobyte_insn;
0bc5eedb
BP		 4882 else if (ctxt->opcode_len == 3)
4883 goto threebyte_insn;
6aa8b732 4884
9dac77fa 4885 switch (ctxt->b) {
6aa8b732 4886 case 0x63: /* movsxd */
8b4caf66 4887 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4888 goto cannot_emulate;
9dac77fa 4889 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4890 break;
b2833e3c 4891 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4892 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4893 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4894 break;
7e0b54b1 4895 case 0x8d: /* lea r16/r32, m */
9dac77fa 4896 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4897 break;
3d9e77df 4898 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4899 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4900 ctxt->dst.type = OP_NONE;
4901 else
4902 rc = em_xchg(ctxt);
e4f973ae 4903 break;
e8b6fa70 4904 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4905 switch (ctxt->op_bytes) {
4906 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4907 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4908 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4909 }
4910 break;
6e154e56 4911 case 0xcc: /* int3 */
5c5df76b
TY		 4912 rc = emulate_int(ctxt, 3);
4913 break;
6e154e56 4914 case 0xcd: /* int n */
9dac77fa 4915 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4916 break;
4917 case 0xce: /* into */
5c5df76b
TY		 4918 if (ctxt->eflags & EFLG_OF)
4919 rc = emulate_int(ctxt, 4);
6e154e56 4920 break;
1a52e051 4921 case 0xe9: /* jmp rel */
db5b0762 4922 case 0xeb: /* jmp rel short */
234f3ce4 4923 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4924 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4925 break;
111de5d6 4926 case 0xf4: /* hlt */
6c3287f7 4927 ctxt->ops->halt(ctxt);
19fdfa0d 4928 break;
111de5d6
AK		 4929 case 0xf5: /* cmc */
4930 /* complement carry flag from eflags reg */
4931 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4932 break;
4933 case 0xf8: /* clc */
4934 ctxt->eflags &= ~EFLG_CF;
111de5d6 4935 break;
8744aa9a
MG		 4936 case 0xf9: /* stc */
4937 ctxt->eflags |= EFLG_CF;
4938 break;
fb4616f4
MG		 4939 case 0xfc: /* cld */
4940 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4941 break;
4942 case 0xfd: /* std */
4943 ctxt->eflags |= EFLG_DF;
fb4616f4 4944 break;
91269b8f
AK		 4945 default:
4946 goto cannot_emulate;
6aa8b732 4947 }
018a98db 4948
7d9ddaed
AK		 4949 if (rc != X86EMUL_CONTINUE)
4950 goto done;
4951
018a98db 4952writeback:
fb32b1ed
AK		 4953 if (ctxt->d & SrcWrite) {
4954 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4955 rc = writeback(ctxt, &ctxt->src);
4956 if (rc != X86EMUL_CONTINUE)
4957 goto done;
4958 }
ee212297
NA		 4959 if (!(ctxt->d & NoWrite)) {
4960 rc = writeback(ctxt, &ctxt->dst);
4961 if (rc != X86EMUL_CONTINUE)
4962 goto done;
4963 }
018a98db 4964
5cd21917
GN		 4965 /*
4966 * restore dst type in case the decoding will be reused
4967 * (happens for string instruction )
4968 */
9dac77fa 4969 ctxt->dst.type = saved_dst_type;
5cd21917 4970
9dac77fa 4971 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4972 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4973
9dac77fa 4974 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4975 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4976
9dac77fa 4977 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4978 unsigned int count;
9dac77fa 4979 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4980 if ((ctxt->d & SrcMask) == SrcSI)
4981 count = ctxt->src.count;
4982 else
4983 count = ctxt->dst.count;
4984 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4985 -count);
3e2f65d5 4986
d2ddd1c4
GN		 4987 if (!string_insn_completed(ctxt)) {
4988 /*
4989 * Re-enter guest when pio read ahead buffer is empty
4990 * or, if it is not used, after each 1024 iteration.
4991 */
dd856efa 4992 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4993 (r->end == 0 || r->end != r->pos)) {
4994 /*
4995 * Reset read cache. Usually happens before
4996 * decode, but since instruction is restarted
4997 * we have to do it here.
4998 */
9dac77fa 4999 ctxt->mem_read.end = 0;
dd856efa 5000 writeback_registers(ctxt);
d2ddd1c4
GN		 5001 return EMULATION_RESTART;
5002 }
5003 goto done; /* skip rip writeback */
0fa6ccbd 5004 }
b9a1ecb9 5005 ctxt->eflags &= ~EFLG_RF;
5cd21917 5006 }
d2ddd1c4 5007
9dac77fa 5008 ctxt->eip = ctxt->_eip;
018a98db
AK		 5009
5010done:
e0ad0b47
PB		 5011 if (rc == X86EMUL_PROPAGATE_FAULT) {
5012 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5013 ctxt->have_exception = true;
e0ad0b47 5014 }
775fde86
JR		 5015 if (rc == X86EMUL_INTERCEPTED)
5016 return EMULATION_INTERCEPTED;
5017
dd856efa
AK		 5018 if (rc == X86EMUL_CONTINUE)
5019 writeback_registers(ctxt);
5020
d2ddd1c4 5021 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5022
5023twobyte_insn:
9dac77fa 5024 switch (ctxt->b) {
018a98db 5025 case 0x09: /* wbinvd */
cfb22375 5026 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5027 break;
5028 case 0x08: /* invd */
018a98db
AK		 5029 case 0x0d: /* GrpP (prefetch) */
5030 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5031 case 0x1f: /* nop */
018a98db
AK		 5032 break;
5033 case 0x20: /* mov cr, reg */
9dac77fa 5034 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5035 break;
6aa8b732 5036 case 0x21: /* mov from dr to reg */
9dac77fa 5037 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5038 break;
6aa8b732 5039 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5040 if (test_cc(ctxt->b, ctxt->eflags))
5041 ctxt->dst.val = ctxt->src.val;
5042 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5043 ctxt->op_bytes != 4)
9dac77fa 5044 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5045 break;
b2833e3c 5046 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5047 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5048 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5049 break;
ee45b58e 5050 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5051 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5052 break;
6aa8b732 5053 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5054 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5055 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5056 : (u16) ctxt->src.val;
6aa8b732 5057 break;
6aa8b732 5058 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5059 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5060 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5061 (s16) ctxt->src.val;
6aa8b732 5062 break;
91269b8f
AK		 5063 default:
5064 goto cannot_emulate;
6aa8b732 5065 }
7d9ddaed 5066
0bc5eedb
BP		 5067threebyte_insn:
5068
7d9ddaed
AK		 5069 if (rc != X86EMUL_CONTINUE)
5070 goto done;
5071
6aa8b732
AK		 5072 goto writeback;
5073
5074cannot_emulate:
a0c0ab2f 5075 return EMULATION_FAILED;
6aa8b732 5076}
dd856efa
AK		 5077
5078void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5079{
5080 invalidate_registers(ctxt);
5081}
5082
5083void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5084{
5085 writeback_registers(ctxt);
5086}
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