]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/emulate.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: update masterclock values on TSC writes
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 165#define Intercept ((u64)1 << 48) /* Has valid intercept field */
166#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 167#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 168#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 169#define NearBranch ((u64)1 << 52) /* Near branches */
6aa8b732 170
820207c8 171#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 172
d0e53325
AK		 173#define X2(x...) x, x
174#define X3(x...) X2(x), x
175#define X4(x...) X2(x), X2(x)
176#define X5(x...) X4(x), x
177#define X6(x...) X4(x), X2(x)
178#define X7(x...) X4(x), X3(x)
179#define X8(x...) X4(x), X4(x)
180#define X16(x...) X8(x), X8(x)
83babbca 181
e28bbd44
AK		 182#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
183#define FASTOP_SIZE 8
184
185/*
186 * fastop functions have a special calling convention:
187 *
017da7b6
AK		 188 * dst: rax (in/out)
189 * src: rdx (in/out)
e28bbd44
AK		 190 * src2: rcx (in)
191 * flags: rflags (in/out)
b8c0b6ae 192 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 193 *
194 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
195 * different operand sizes can be reached by calculation, rather than a jump
196 * table (which would be bigger than the code).
197 *
198 * fastop functions are declared as taking a never-defined fastop parameter,
199 * so they can't be called from C directly.
200 */
201
202struct fastop;
203
d65b1dee 204struct opcode {
b1ea50b2
AK		 205 u64 flags : 56;
206 u64 intercept : 8;
120df890 207 union {
ef65c889 208 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 209 const struct opcode *group;
210 const struct group_dual *gdual;
211 const struct gprefix *gprefix;
045a282c 212 const struct escape *esc;
e28bbd44 213 void (*fastop)(struct fastop *fake);
120df890 214 } u;
d09beabd 215 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 216};
217
218struct group_dual {
219 struct opcode mod012[8];
220 struct opcode mod3[8];
d65b1dee
AK		 221};
222
0d7cdee8
AK		 223struct gprefix {
224 struct opcode pfx_no;
225 struct opcode pfx_66;
226 struct opcode pfx_f2;
227 struct opcode pfx_f3;
228};
229
045a282c
GN		 230struct escape {
231 struct opcode op[8];
232 struct opcode high[64];
233};
234
6aa8b732 235/* EFLAGS bit definitions. */
d4c6a154
GN		 236#define EFLG_ID (1<<21)
237#define EFLG_VIP (1<<20)
238#define EFLG_VIF (1<<19)
239#define EFLG_AC (1<<18)
b1d86143
AP		 240#define EFLG_VM (1<<17)
241#define EFLG_RF (1<<16)
d4c6a154
GN		 242#define EFLG_IOPL (3<<12)
243#define EFLG_NT (1<<14)
6aa8b732
AK		 244#define EFLG_OF (1<<11)
245#define EFLG_DF (1<<10)
b1d86143 246#define EFLG_IF (1<<9)
d4c6a154 247#define EFLG_TF (1<<8)
6aa8b732
AK		 248#define EFLG_SF (1<<7)
249#define EFLG_ZF (1<<6)
250#define EFLG_AF (1<<4)
251#define EFLG_PF (1<<2)
252#define EFLG_CF (1<<0)
253
62bd430e
MG		 254#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
255#define EFLG_RESERVED_ONE_MASK 2
256
dd856efa
AK		 257static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
258{
259 if (!(ctxt->regs_valid & (1 << nr))) {
260 ctxt->regs_valid |= 1 << nr;
261 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
262 }
263 return ctxt->_regs[nr];
264}
265
266static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
267{
268 ctxt->regs_valid |= 1 << nr;
269 ctxt->regs_dirty |= 1 << nr;
270 return &ctxt->_regs[nr];
271}
272
273static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
274{
275 reg_read(ctxt, nr);
276 return reg_write(ctxt, nr);
277}
278
279static void writeback_registers(struct x86_emulate_ctxt *ctxt)
280{
281 unsigned reg;
282
283 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
284 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
285}
286
287static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
288{
289 ctxt->regs_dirty = 0;
290 ctxt->regs_valid = 0;
291}
292
6aa8b732
AK		 293/*
294 * These EFLAGS bits are restored from saved value during emulation, and
295 * any changes are written back to the saved value after emulation.
296 */
297#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
298
dda96d8f
AK		 299#ifdef CONFIG_X86_64
300#define ON64(x) x
301#else
302#define ON64(x)
303#endif
304
4d758349
AK		 305static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
306
b7d491e7
AK		 307#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
308#define FOP_RET "ret \n\t"
309
310#define FOP_START(op) \
311 extern void em_##op(struct fastop *fake); \
312 asm(".pushsection .text, \"ax\" \n\t" \
313 ".global em_" #op " \n\t" \
314 FOP_ALIGN \
315 "em_" #op ": \n\t"
316
317#define FOP_END \
318 ".popsection")
319
0bdea068
AK		 320#define FOPNOP() FOP_ALIGN FOP_RET
321
b7d491e7 322#define FOP1E(op, dst) \
b8c0b6ae
AK		 323 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
324
325#define FOP1EEX(op, dst) \
326 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 327
328#define FASTOP1(op) \
329 FOP_START(op) \
330 FOP1E(op##b, al) \
331 FOP1E(op##w, ax) \
332 FOP1E(op##l, eax) \
333 ON64(FOP1E(op##q, rax)) \
334 FOP_END
335
b9fa409b
AK		 336/* 1-operand, using src2 (for MUL/DIV r/m) */
337#define FASTOP1SRC2(op, name) \
338 FOP_START(name) \
339 FOP1E(op, cl) \
340 FOP1E(op, cx) \
341 FOP1E(op, ecx) \
342 ON64(FOP1E(op, rcx)) \
343 FOP_END
344
b8c0b6ae
AK		 345/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
346#define FASTOP1SRC2EX(op, name) \
347 FOP_START(name) \
348 FOP1EEX(op, cl) \
349 FOP1EEX(op, cx) \
350 FOP1EEX(op, ecx) \
351 ON64(FOP1EEX(op, rcx)) \
352 FOP_END
353
f7857f35
AK		 354#define FOP2E(op, dst, src) \
355 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
356
357#define FASTOP2(op) \
358 FOP_START(op) \
017da7b6
AK		 359 FOP2E(op##b, al, dl) \
360 FOP2E(op##w, ax, dx) \
361 FOP2E(op##l, eax, edx) \
362 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 363 FOP_END
364
11c363ba
AK		 365/* 2 operand, word only */
366#define FASTOP2W(op) \
367 FOP_START(op) \
368 FOPNOP() \
017da7b6
AK		 369 FOP2E(op##w, ax, dx) \
370 FOP2E(op##l, eax, edx) \
371 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 372 FOP_END
373
007a3b54
AK		 374/* 2 operand, src is CL */
375#define FASTOP2CL(op) \
376 FOP_START(op) \
377 FOP2E(op##b, al, cl) \
378 FOP2E(op##w, ax, cl) \
379 FOP2E(op##l, eax, cl) \
380 ON64(FOP2E(op##q, rax, cl)) \
381 FOP_END
382
5aca3722
NA		 383/* 2 operand, src and dest are reversed */
384#define FASTOP2R(op, name) \
385 FOP_START(name) \
386 FOP2E(op##b, dl, al) \
387 FOP2E(op##w, dx, ax) \
388 FOP2E(op##l, edx, eax) \
389 ON64(FOP2E(op##q, rdx, rax)) \
390 FOP_END
391
0bdea068
AK		 392#define FOP3E(op, dst, src, src2) \
393 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
394
395/* 3-operand, word-only, src2=cl */
396#define FASTOP3WCL(op) \
397 FOP_START(op) \
398 FOPNOP() \
017da7b6
AK		 399 FOP3E(op##w, ax, dx, cl) \
400 FOP3E(op##l, eax, edx, cl) \
401 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 402 FOP_END
403
9ae9feba
AK		 404/* Special case for SETcc - 1 instruction per cc */
405#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
406
b8c0b6ae
AK		 407asm(".global kvm_fastop_exception \n"
408 "kvm_fastop_exception: xor %esi, %esi; ret");
409
9ae9feba
AK		 410FOP_START(setcc)
411FOP_SETCC(seto)
412FOP_SETCC(setno)
413FOP_SETCC(setc)
414FOP_SETCC(setnc)
415FOP_SETCC(setz)
416FOP_SETCC(setnz)
417FOP_SETCC(setbe)
418FOP_SETCC(setnbe)
419FOP_SETCC(sets)
420FOP_SETCC(setns)
421FOP_SETCC(setp)
422FOP_SETCC(setnp)
423FOP_SETCC(setl)
424FOP_SETCC(setnl)
425FOP_SETCC(setle)
426FOP_SETCC(setnle)
427FOP_END;
428
326f578f
PB		 429FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
430FOP_END;
431
8a76d7f2
JR		 432static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
433 enum x86_intercept intercept,
434 enum x86_intercept_stage stage)
435{
436 struct x86_instruction_info info = {
437 .intercept = intercept,
9dac77fa
AK		 438 .rep_prefix = ctxt->rep_prefix,
439 .modrm_mod = ctxt->modrm_mod,
440 .modrm_reg = ctxt->modrm_reg,
441 .modrm_rm = ctxt->modrm_rm,
442 .src_val = ctxt->src.val64,
6cbc5f5a 443 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 444 .src_bytes = ctxt->src.bytes,
445 .dst_bytes = ctxt->dst.bytes,
446 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 447 .next_rip = ctxt->eip,
448 };
449
2953538e 450 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 451}
452
f47cfa31
AK		 453static void assign_masked(ulong *dest, ulong src, ulong mask)
454{
455 *dest = (*dest & ~mask) | (src & mask);
456}
457
9dac77fa 458static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 459{
9dac77fa 460 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 461}
462
f47cfa31
AK		 463static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
464{
465 u16 sel;
466 struct desc_struct ss;
467
468 if (ctxt->mode == X86EMUL_MODE_PROT64)
469 return ~0UL;
470 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
471 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
472}
473
612e89f0
AK		 474static int stack_size(struct x86_emulate_ctxt *ctxt)
475{
476 return (__fls(stack_mask(ctxt)) + 1) >> 3;
477}
478
6aa8b732 479/* Access/update address held in a register, based on addressing mode. */
e4706772 480static inline unsigned long
9dac77fa 481address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 482{
9dac77fa 483 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 484 return reg;
485 else
9dac77fa 486 return reg & ad_mask(ctxt);
e4706772
HH		 487}
488
489static inline unsigned long
9dac77fa 490register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 491{
9dac77fa 492 return address_mask(ctxt, reg);
e4706772
HH		 493}
494
5ad105e5
AK		 495static void masked_increment(ulong *reg, ulong mask, int inc)
496{
497 assign_masked(reg, *reg + inc, mask);
498}
499
7a957275 500static inline void
9dac77fa 501register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 502{
5ad105e5
AK		 503 ulong mask;
504
9dac77fa 505 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 506 mask = ~0UL;
7a957275 507 else
5ad105e5
AK		 508 mask = ad_mask(ctxt);
509 masked_increment(reg, mask, inc);
510}
511
512static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
513{
dd856efa 514 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 515}
6aa8b732 516
56697687
AK		 517static u32 desc_limit_scaled(struct desc_struct *desc)
518{
519 u32 limit = get_desc_limit(desc);
520
521 return desc->g ? (limit << 12) | 0xfff : limit;
522}
523
7b105ca2 524static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 525{
526 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
527 return 0;
528
7b105ca2 529 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 530}
531
35d3d4a1
AK		 532static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
533 u32 error, bool valid)
54b8486f 534{
e0ad0b47 535 WARN_ON(vec > 0x1f);
da9cb575
AK		 536 ctxt->exception.vector = vec;
537 ctxt->exception.error_code = error;
538 ctxt->exception.error_code_valid = valid;
35d3d4a1 539 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 540}
541
3b88e41a
JR		 542static int emulate_db(struct x86_emulate_ctxt *ctxt)
543{
544 return emulate_exception(ctxt, DB_VECTOR, 0, false);
545}
546
35d3d4a1 547static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 548{
35d3d4a1 549 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 550}
551
618ff15d
AK		 552static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
553{
554 return emulate_exception(ctxt, SS_VECTOR, err, true);
555}
556
35d3d4a1 557static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 558{
35d3d4a1 559 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 560}
561
35d3d4a1 562static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 563{
35d3d4a1 564 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 565}
566
34d1f490
AK		 567static int emulate_de(struct x86_emulate_ctxt *ctxt)
568{
35d3d4a1 569 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 570}
571
1253791d
AK		 572static int emulate_nm(struct x86_emulate_ctxt *ctxt)
573{
574 return emulate_exception(ctxt, NM_VECTOR, 0, false);
575}
576
234f3ce4
NA		 577static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
578 int cs_l)
05c83ec9
NA		 579{
580 switch (ctxt->op_bytes) {
581 case 2:
582 ctxt->_eip = (u16)dst;
583 break;
584 case 4:
585 ctxt->_eip = (u32)dst;
586 break;
cd9b8e2c 587#ifdef CONFIG_X86_64
05c83ec9 588 case 8:
234f3ce4 589 if ((cs_l && is_noncanonical_address(dst)) ||
cd9b8e2c 590 (!cs_l && (dst >> 32) != 0))
234f3ce4 591 return emulate_gp(ctxt, 0);
05c83ec9
NA		 592 ctxt->_eip = dst;
593 break;
cd9b8e2c 594#endif
05c83ec9
NA		 595 default:
596 WARN(1, "unsupported eip assignment size\n");
597 }
234f3ce4
NA		 598 return X86EMUL_CONTINUE;
599}
600
601static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
602{
603 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
05c83ec9
NA		 604}
605
234f3ce4 606static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
05c83ec9 607{
234f3ce4 608 return assign_eip_near(ctxt, ctxt->_eip + rel);
05c83ec9
NA		 609}
610
1aa36616
AK		 611static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
612{
613 u16 selector;
614 struct desc_struct desc;
615
616 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
617 return selector;
618}
619
620static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
621 unsigned seg)
622{
623 u16 dummy;
624 u32 base3;
625 struct desc_struct desc;
626
627 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
628 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
629}
630
1c11b376
AK		 631/*
632 * x86 defines three classes of vector instructions: explicitly
633 * aligned, explicitly unaligned, and the rest, which change behaviour
634 * depending on whether they're AVX encoded or not.
635 *
636 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
637 * subject to the same check.
638 */
639static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
640{
641 if (likely(size < 16))
642 return false;
643
644 if (ctxt->d & Aligned)
645 return true;
646 else if (ctxt->d & Unaligned)
647 return false;
648 else if (ctxt->d & Avx)
649 return false;
650 else
651 return true;
652}
653
d09155d2
PB		 654static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
655 struct segmented_address addr,
656 unsigned *max_size, unsigned size,
657 bool write, bool fetch,
658 ulong *linear)
52fd8b44 659{
618ff15d
AK		 660 struct desc_struct desc;
661 bool usable;
52fd8b44 662 ulong la;
618ff15d 663 u32 lim;
1aa36616 664 u16 sel;
3a78a4f4 665 unsigned cpl;
52fd8b44 666
518547b3
NA		 667 la = seg_base(ctxt, addr.seg) +
668 (fetch || ctxt->ad_bytes == 8 ? addr.ea : (u32)addr.ea);
fd56e154 669 *max_size = 0;
618ff15d 670 switch (ctxt->mode) {
618ff15d 671 case X86EMUL_MODE_PROT64:
4be4de7e 672 if (is_noncanonical_address(la))
618ff15d 673 return emulate_gp(ctxt, 0);
fd56e154
PB		 674
675 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
676 if (size > *max_size)
677 goto bad;
618ff15d
AK		 678 break;
679 default:
1aa36616
AK		 680 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
681 addr.seg);
618ff15d
AK		 682 if (!usable)
683 goto bad;
58b7825b
GN		 684 /* code segment in protected mode or read-only data segment */
685 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
686 || !(desc.type & 2)) && write)
618ff15d
AK		 687 goto bad;
688 /* unreadable code segment */
3d9b938e 689 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 690 goto bad;
691 lim = desc_limit_scaled(&desc);
10e38fc7
NA		 692 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
693 (ctxt->d & NoBigReal)) {
694 /* la is between zero and 0xffff */
fd56e154 695 if (la > 0xffff)
10e38fc7 696 goto bad;
fd56e154 697 *max_size = 0x10000 - la;
10e38fc7 698 } else if ((desc.type & 8) || !(desc.type & 4)) {
618ff15d 699 /* expand-up segment */
fd56e154 700 if (addr.ea > lim)
618ff15d 701 goto bad;
fd56e154 702 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 703 } else {
fc058680 704 /* expand-down segment */
fd56e154 705 if (addr.ea <= lim)
618ff15d
AK		 706 goto bad;
707 lim = desc.d ? 0xffffffff : 0xffff;
fd56e154 708 if (addr.ea > lim)
618ff15d 709 goto bad;
fd56e154 710 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
618ff15d 711 }
fd56e154
PB		 712 if (size > *max_size)
713 goto bad;
717746e3 714 cpl = ctxt->ops->cpl(ctxt);
c49c759f
NA		 715 if (!fetch) {
716 /* data segment or readable code segment */
618ff15d
AK		 717 if (cpl > desc.dpl)
718 goto bad;
719 } else if ((desc.type & 8) && !(desc.type & 4)) {
720 /* nonconforming code segment */
721 if (cpl != desc.dpl)
722 goto bad;
723 } else if ((desc.type & 8) && (desc.type & 4)) {
724 /* conforming code segment */
725 if (cpl < desc.dpl)
726 goto bad;
727 }
728 break;
729 }
518547b3 730 if (ctxt->mode != X86EMUL_MODE_PROT64)
52fd8b44 731 la &= (u32)-1;
1c11b376
AK		 732 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
733 return emulate_gp(ctxt, 0);
52fd8b44
AK		 734 *linear = la;
735 return X86EMUL_CONTINUE;
618ff15d
AK		 736bad:
737 if (addr.seg == VCPU_SREG_SS)
3606189f 738 return emulate_ss(ctxt, 0);
618ff15d 739 else
3606189f 740 return emulate_gp(ctxt, 0);
52fd8b44
AK		 741}
742
3d9b938e
NE		 743static int linearize(struct x86_emulate_ctxt *ctxt,
744 struct segmented_address addr,
745 unsigned size, bool write,
746 ulong *linear)
747{
fd56e154
PB		 748 unsigned max_size;
749 return __linearize(ctxt, addr, &max_size, size, write, false, linear);
3d9b938e
NE		 750}
751
752
3ca3ac4d
AK		 753static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
754 struct segmented_address addr,
755 void *data,
756 unsigned size)
757{
9fa088f4
AK		 758 int rc;
759 ulong linear;
760
83b8795a 761 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 762 if (rc != X86EMUL_CONTINUE)
763 return rc;
0f65dd70 764 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 765}
766
807941b1 767/*
285ca9e9 768 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 769 * boundary if they are not in fetch_cache yet.
770 */
9506d57d 771static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 772{
62266869 773 int rc;
fd56e154 774 unsigned size, max_size;
285ca9e9 775 unsigned long linear;
17052f16 776 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 777 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 778 .ea = ctxt->eip + cur_size };
779
fd56e154
PB		 780 /*
781 * We do not know exactly how many bytes will be needed, and
782 * __linearize is expensive, so fetch as much as possible. We
783 * just have to avoid going beyond the 15 byte limit, the end
784 * of the segment, or the end of the page.
785 *
786 * __linearize is called with size 0 so that it does not do any
787 * boundary check itself. Instead, we use max_size to check
788 * against op_size.
789 */
790 rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
719d5a9b
PB		 791 if (unlikely(rc != X86EMUL_CONTINUE))
792 return rc;
793
fd56e154 794 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 795 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 796
797 /*
798 * One instruction can only straddle two pages,
799 * and one has been loaded at the beginning of
800 * x86_decode_insn. So, if not enough bytes
801 * still, we must have hit the 15-byte boundary.
802 */
803 if (unlikely(size < op_size))
fd56e154
PB		 804 return emulate_gp(ctxt, 0);
805
17052f16 806 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 807 size, &ctxt->exception);
808 if (unlikely(rc != X86EMUL_CONTINUE))
809 return rc;
17052f16 810 ctxt->fetch.end += size;
3e2815e9 811 return X86EMUL_CONTINUE;
62266869
AK		 812}
813
9506d57d
PB		 814static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
815 unsigned size)
62266869 816{
08da44ae
NA		 817 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
818
819 if (unlikely(done_size < size))
820 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 821 else
822 return X86EMUL_CONTINUE;
62266869
AK		 823}
824
67cbc90d 825/* Fetch next part of the instruction being emulated. */
e85a1085 826#define insn_fetch(_type, _ctxt) \
9506d57d 827({ _type _x; \
9506d57d
PB		 828 \
829 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 830 if (rc != X86EMUL_CONTINUE) \
831 goto done; \
9506d57d 832 ctxt->_eip += sizeof(_type); \
17052f16
PB		 833 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
834 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 835 _x; \
67cbc90d
TY		 836})
837
807941b1 838#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 839({ \
9506d57d 840 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 841 if (rc != X86EMUL_CONTINUE) \
842 goto done; \
9506d57d 843 ctxt->_eip += (_size); \
17052f16
PB		 844 memcpy(_arr, ctxt->fetch.ptr, _size); \
845 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 846})
847
1e3c5cb0
RR		 848/*
849 * Given the 'reg' portion of a ModRM byte, and a register block, return a
850 * pointer into the block that addresses the relevant register.
851 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
852 */
dd856efa 853static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 854 int byteop)
6aa8b732
AK		 855{
856 void *p;
aa9ac1a6 857 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 858
6aa8b732 859 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 860 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
861 else
862 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 863 return p;
864}
865
866static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 867 struct segmented_address addr,
6aa8b732
AK		 868 u16 *size, unsigned long *address, int op_bytes)
869{
870 int rc;
871
872 if (op_bytes == 2)
873 op_bytes = 3;
874 *address = 0;
3ca3ac4d 875 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 876 if (rc != X86EMUL_CONTINUE)
6aa8b732 877 return rc;
30b31ab6 878 addr.ea += 2;
3ca3ac4d 879 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 880 return rc;
881}
882
34b77652
AK		 883FASTOP2(add);
884FASTOP2(or);
885FASTOP2(adc);
886FASTOP2(sbb);
887FASTOP2(and);
888FASTOP2(sub);
889FASTOP2(xor);
890FASTOP2(cmp);
891FASTOP2(test);
892
b9fa409b
AK		 893FASTOP1SRC2(mul, mul_ex);
894FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 895FASTOP1SRC2EX(div, div_ex);
896FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 897
34b77652
AK		 898FASTOP3WCL(shld);
899FASTOP3WCL(shrd);
900
901FASTOP2W(imul);
902
903FASTOP1(not);
904FASTOP1(neg);
905FASTOP1(inc);
906FASTOP1(dec);
907
908FASTOP2CL(rol);
909FASTOP2CL(ror);
910FASTOP2CL(rcl);
911FASTOP2CL(rcr);
912FASTOP2CL(shl);
913FASTOP2CL(shr);
914FASTOP2CL(sar);
915
916FASTOP2W(bsf);
917FASTOP2W(bsr);
918FASTOP2W(bt);
919FASTOP2W(bts);
920FASTOP2W(btr);
921FASTOP2W(btc);
922
e47a5f5f
AK		 923FASTOP2(xadd);
924
5aca3722
NA		 925FASTOP2R(cmp, cmp_r);
926
9ae9feba 927static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 928{
9ae9feba
AK		 929 u8 rc;
930 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 931
9ae9feba 932 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 933 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 934 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
935 return rc;
bbe9abbd
NK		 936}
937
91ff3cb4
AK		 938static void fetch_register_operand(struct operand *op)
939{
940 switch (op->bytes) {
941 case 1:
942 op->val = *(u8 *)op->addr.reg;
943 break;
944 case 2:
945 op->val = *(u16 *)op->addr.reg;
946 break;
947 case 4:
948 op->val = *(u32 *)op->addr.reg;
949 break;
950 case 8:
951 op->val = *(u64 *)op->addr.reg;
952 break;
953 }
954}
955
1253791d
AK		 956static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
957{
958 ctxt->ops->get_fpu(ctxt);
959 switch (reg) {
89a87c67
MK		 960 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
961 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
962 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
963 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
964 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
965 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
966 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
967 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 968#ifdef CONFIG_X86_64
89a87c67
MK		 969 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
970 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
971 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
972 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
973 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
974 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
975 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
976 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 977#endif
978 default: BUG();
979 }
980 ctxt->ops->put_fpu(ctxt);
981}
982
983static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
984 int reg)
985{
986 ctxt->ops->get_fpu(ctxt);
987 switch (reg) {
89a87c67
MK		 988 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
989 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
990 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
991 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
992 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
993 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
994 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
995 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 996#ifdef CONFIG_X86_64
89a87c67
MK		 997 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
998 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
999 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1000 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1001 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1002 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1003 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1004 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1005#endif
1006 default: BUG();
1007 }
1008 ctxt->ops->put_fpu(ctxt);
1009}
1010
cbe2c9d3
AK		 1011static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1012{
1013 ctxt->ops->get_fpu(ctxt);
1014 switch (reg) {
1015 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1016 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1017 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1018 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1019 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1020 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1021 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1022 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1023 default: BUG();
1024 }
1025 ctxt->ops->put_fpu(ctxt);
1026}
1027
1028static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1029{
1030 ctxt->ops->get_fpu(ctxt);
1031 switch (reg) {
1032 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1033 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1034 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1035 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1036 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1037 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1038 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1039 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1040 default: BUG();
1041 }
1042 ctxt->ops->put_fpu(ctxt);
1043}
1044
045a282c
GN		 1045static int em_fninit(struct x86_emulate_ctxt *ctxt)
1046{
1047 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1048 return emulate_nm(ctxt);
1049
1050 ctxt->ops->get_fpu(ctxt);
1051 asm volatile("fninit");
1052 ctxt->ops->put_fpu(ctxt);
1053 return X86EMUL_CONTINUE;
1054}
1055
1056static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1057{
1058 u16 fcw;
1059
1060 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1061 return emulate_nm(ctxt);
1062
1063 ctxt->ops->get_fpu(ctxt);
1064 asm volatile("fnstcw %0": "+m"(fcw));
1065 ctxt->ops->put_fpu(ctxt);
1066
1067 /* force 2 byte destination */
1068 ctxt->dst.bytes = 2;
1069 ctxt->dst.val = fcw;
1070
1071 return X86EMUL_CONTINUE;
1072}
1073
1074static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1075{
1076 u16 fsw;
1077
1078 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1079 return emulate_nm(ctxt);
1080
1081 ctxt->ops->get_fpu(ctxt);
1082 asm volatile("fnstsw %0": "+m"(fsw));
1083 ctxt->ops->put_fpu(ctxt);
1084
1085 /* force 2 byte destination */
1086 ctxt->dst.bytes = 2;
1087 ctxt->dst.val = fsw;
1088
1089 return X86EMUL_CONTINUE;
1090}
1091
1253791d 1092static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1093 struct operand *op)
3c118e24 1094{
9dac77fa 1095 unsigned reg = ctxt->modrm_reg;
33615aa9 1096
9dac77fa
AK		 1097 if (!(ctxt->d & ModRM))
1098 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1099
9dac77fa 1100 if (ctxt->d & Sse) {
1253791d
AK		 1101 op->type = OP_XMM;
1102 op->bytes = 16;
1103 op->addr.xmm = reg;
1104 read_sse_reg(ctxt, &op->vec_val, reg);
1105 return;
1106 }
cbe2c9d3
AK		 1107 if (ctxt->d & Mmx) {
1108 reg &= 7;
1109 op->type = OP_MM;
1110 op->bytes = 8;
1111 op->addr.mm = reg;
1112 return;
1113 }
1253791d 1114
3c118e24 1115 op->type = OP_REG;
6d4d85ec
GN		 1116 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1117 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1118
91ff3cb4 1119 fetch_register_operand(op);
3c118e24
AK		 1120 op->orig_val = op->val;
1121}
1122
a6e3407b
AK		 1123static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1124{
1125 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1126 ctxt->modrm_seg = VCPU_SREG_SS;
1127}
1128
1c73ef66 1129static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1130 struct operand *op)
1c73ef66 1131{
1c73ef66 1132 u8 sib;
02357bdc 1133 int index_reg, base_reg, scale;
3e2815e9 1134 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1135 ulong modrm_ea = 0;
1c73ef66 1136
02357bdc
BD		 1137 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1138 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1139 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1140
02357bdc 1141 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1142 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1143 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1144 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1145
9b88ae99 1146 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1147 op->type = OP_REG;
9dac77fa 1148 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1149 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1150 ctxt->d & ByteOp);
9dac77fa 1151 if (ctxt->d & Sse) {
1253791d
AK		 1152 op->type = OP_XMM;
1153 op->bytes = 16;
9dac77fa
AK		 1154 op->addr.xmm = ctxt->modrm_rm;
1155 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1156 return rc;
1157 }
cbe2c9d3
AK		 1158 if (ctxt->d & Mmx) {
1159 op->type = OP_MM;
1160 op->bytes = 8;
bdc90722 1161 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1162 return rc;
1163 }
2dbd0dd7 1164 fetch_register_operand(op);
1c73ef66
AK		 1165 return rc;
1166 }
1167
2dbd0dd7
AK		 1168 op->type = OP_MEM;
1169
9dac77fa 1170 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1171 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1172 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1173 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1174 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1175
1176 /* 16-bit ModR/M decode. */
9dac77fa 1177 switch (ctxt->modrm_mod) {
1c73ef66 1178 case 0:
9dac77fa 1179 if (ctxt->modrm_rm == 6)
e85a1085 1180 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1181 break;
1182 case 1:
e85a1085 1183 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1184 break;
1185 case 2:
e85a1085 1186 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1187 break;
1188 }
9dac77fa 1189 switch (ctxt->modrm_rm) {
1c73ef66 1190 case 0:
2dbd0dd7 1191 modrm_ea += bx + si;
1c73ef66
AK		 1192 break;
1193 case 1:
2dbd0dd7 1194 modrm_ea += bx + di;
1c73ef66
AK		 1195 break;
1196 case 2:
2dbd0dd7 1197 modrm_ea += bp + si;
1c73ef66
AK		 1198 break;
1199 case 3:
2dbd0dd7 1200 modrm_ea += bp + di;
1c73ef66
AK		 1201 break;
1202 case 4:
2dbd0dd7 1203 modrm_ea += si;
1c73ef66
AK		 1204 break;
1205 case 5:
2dbd0dd7 1206 modrm_ea += di;
1c73ef66
AK		 1207 break;
1208 case 6:
9dac77fa 1209 if (ctxt->modrm_mod != 0)
2dbd0dd7 1210 modrm_ea += bp;
1c73ef66
AK		 1211 break;
1212 case 7:
2dbd0dd7 1213 modrm_ea += bx;
1c73ef66
AK		 1214 break;
1215 }
9dac77fa
AK		 1216 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1217 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1218 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1219 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1220 } else {
1221 /* 32/64-bit ModR/M decode. */
9dac77fa 1222 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1223 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1224 index_reg |= (sib >> 3) & 7;
1225 base_reg |= sib & 7;
1226 scale = sib >> 6;
1227
9dac77fa 1228 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1229 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1230 else {
dd856efa 1231 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1232 adjust_modrm_seg(ctxt, base_reg);
1233 }
dc71d0f1 1234 if (index_reg != 4)
dd856efa 1235 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1236 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1237 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1238 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1239 ctxt->rip_relative = 1;
a6e3407b
AK		 1240 } else {
1241 base_reg = ctxt->modrm_rm;
dd856efa 1242 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1243 adjust_modrm_seg(ctxt, base_reg);
1244 }
9dac77fa 1245 switch (ctxt->modrm_mod) {
1c73ef66 1246 case 1:
e85a1085 1247 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1248 break;
1249 case 2:
e85a1085 1250 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1251 break;
1252 }
1253 }
90de84f5 1254 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1255 if (ctxt->ad_bytes != 8)
1256 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1257
1c73ef66
AK		 1258done:
1259 return rc;
1260}
1261
1262static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1263 struct operand *op)
1c73ef66 1264{
3e2815e9 1265 int rc = X86EMUL_CONTINUE;
1c73ef66 1266
2dbd0dd7 1267 op->type = OP_MEM;
9dac77fa 1268 switch (ctxt->ad_bytes) {
1c73ef66 1269 case 2:
e85a1085 1270 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1271 break;
1272 case 4:
e85a1085 1273 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1274 break;
1275 case 8:
e85a1085 1276 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1277 break;
1278 }
1279done:
1280 return rc;
1281}
1282
9dac77fa 1283static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1284{
7129eeca 1285 long sv = 0, mask;
35c843c4 1286
9dac77fa 1287 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1288 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1289
9dac77fa
AK		 1290 if (ctxt->src.bytes == 2)
1291 sv = (s16)ctxt->src.val & (s16)mask;
1292 else if (ctxt->src.bytes == 4)
1293 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1294 else
1295 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1296
9dac77fa 1297 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1298 }
ba7ff2b7
WY		 1299
1300 /* only subword offset */
9dac77fa 1301 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1302}
1303
dde7e6d1 1304static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1305 unsigned long addr, void *dest, unsigned size)
6aa8b732 1306{
dde7e6d1 1307 int rc;
9dac77fa 1308 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1309
f23b070e
XG		 1310 if (mc->pos < mc->end)
1311 goto read_cached;
6aa8b732 1312
f23b070e
XG		 1313 WARN_ON((mc->end + size) >= sizeof(mc->data));
1314
1315 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1316 &ctxt->exception);
1317 if (rc != X86EMUL_CONTINUE)
1318 return rc;
1319
1320 mc->end += size;
1321
1322read_cached:
1323 memcpy(dest, mc->data + mc->pos, size);
1324 mc->pos += size;
dde7e6d1
AK		 1325 return X86EMUL_CONTINUE;
1326}
6aa8b732 1327
3ca3ac4d
AK		 1328static int segmented_read(struct x86_emulate_ctxt *ctxt,
1329 struct segmented_address addr,
1330 void *data,
1331 unsigned size)
1332{
9fa088f4
AK		 1333 int rc;
1334 ulong linear;
1335
83b8795a 1336 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1337 if (rc != X86EMUL_CONTINUE)
1338 return rc;
7b105ca2 1339 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1340}
1341
1342static int segmented_write(struct x86_emulate_ctxt *ctxt,
1343 struct segmented_address addr,
1344 const void *data,
1345 unsigned size)
1346{
9fa088f4
AK		 1347 int rc;
1348 ulong linear;
1349
83b8795a 1350 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1351 if (rc != X86EMUL_CONTINUE)
1352 return rc;
0f65dd70
AK		 1353 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1354 &ctxt->exception);
3ca3ac4d
AK		 1355}
1356
1357static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1358 struct segmented_address addr,
1359 const void *orig_data, const void *data,
1360 unsigned size)
1361{
9fa088f4
AK		 1362 int rc;
1363 ulong linear;
1364
83b8795a 1365 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1366 if (rc != X86EMUL_CONTINUE)
1367 return rc;
0f65dd70
AK		 1368 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1369 size, &ctxt->exception);
3ca3ac4d
AK		 1370}
1371
dde7e6d1 1372static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1373 unsigned int size, unsigned short port,
1374 void *dest)
1375{
9dac77fa 1376 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1377
dde7e6d1 1378 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1379 unsigned int in_page, n;
9dac77fa 1380 unsigned int count = ctxt->rep_prefix ?
dd856efa 1381 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1382 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1383 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1384 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1385 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1386 if (n == 0)
1387 n = 1;
1388 rc->pos = rc->end = 0;
7b105ca2 1389 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1390 return 0;
1391 rc->end = n * size;
6aa8b732
AK		 1392 }
1393
e6e39f04
NA		 1394 if (ctxt->rep_prefix && (ctxt->d & String) &&
1395 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1396 ctxt->dst.data = rc->data + rc->pos;
1397 ctxt->dst.type = OP_MEM_STR;
1398 ctxt->dst.count = (rc->end - rc->pos) / size;
1399 rc->pos = rc->end;
1400 } else {
1401 memcpy(dest, rc->data + rc->pos, size);
1402 rc->pos += size;
1403 }
dde7e6d1
AK		 1404 return 1;
1405}
6aa8b732 1406
7f3d35fd
KW		 1407static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1408 u16 index, struct desc_struct *desc)
1409{
1410 struct desc_ptr dt;
1411 ulong addr;
1412
1413 ctxt->ops->get_idt(ctxt, &dt);
1414
1415 if (dt.size < index * 8 + 7)
1416 return emulate_gp(ctxt, index << 3 | 0x2);
1417
1418 addr = dt.address + index * 8;
1419 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1420 &ctxt->exception);
1421}
1422
dde7e6d1 1423static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1424 u16 selector, struct desc_ptr *dt)
1425{
0225fb50 1426 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1427 u32 base3 = 0;
7b105ca2 1428
dde7e6d1
AK		 1429 if (selector & 1 << 2) {
1430 struct desc_struct desc;
1aa36616
AK		 1431 u16 sel;
1432
dde7e6d1 1433 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1434 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1435 VCPU_SREG_LDTR))
dde7e6d1 1436 return;
e09d082c 1437
dde7e6d1 1438 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1439 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1440 } else
4bff1e86 1441 ops->get_gdt(ctxt, dt);
dde7e6d1 1442}
120df890 1443
dde7e6d1
AK		 1444/* allowed just for 8 bytes segments */
1445static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1446 u16 selector, struct desc_struct *desc,
1447 ulong *desc_addr_p)
dde7e6d1
AK		 1448{
1449 struct desc_ptr dt;
1450 u16 index = selector >> 3;
dde7e6d1 1451 ulong addr;
120df890 1452
7b105ca2 1453 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1454
35d3d4a1
AK		 1455 if (dt.size < index * 8 + 7)
1456 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1457
e919464b 1458 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1459 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1460 &ctxt->exception);
dde7e6d1 1461}
ef65c889 1462
dde7e6d1
AK		 1463/* allowed just for 8 bytes segments */
1464static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1465 u16 selector, struct desc_struct *desc)
1466{
1467 struct desc_ptr dt;
1468 u16 index = selector >> 3;
dde7e6d1 1469 ulong addr;
6aa8b732 1470
7b105ca2 1471 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1472
35d3d4a1
AK		 1473 if (dt.size < index * 8 + 7)
1474 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1475
dde7e6d1 1476 addr = dt.address + index * 8;
7b105ca2
TY		 1477 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1478 &ctxt->exception);
dde7e6d1 1479}
c7e75a3d 1480
5601d05b 1481/* Does not support long mode */
2356aaeb 1482static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85
NA		 1483 u16 selector, int seg, u8 cpl,
1484 bool in_task_switch,
1485 struct desc_struct *desc)
dde7e6d1 1486{
869be99c 1487 struct desc_struct seg_desc, old_desc;
2356aaeb 1488 u8 dpl, rpl;
dde7e6d1
AK		 1489 unsigned err_vec = GP_VECTOR;
1490 u32 err_code = 0;
1491 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1492 ulong desc_addr;
dde7e6d1 1493 int ret;
03ebebeb 1494 u16 dummy;
e37a75a1 1495 u32 base3 = 0;
69f55cb1 1496
dde7e6d1 1497 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1498
f8da94e9
KW		 1499 if (ctxt->mode == X86EMUL_MODE_REAL) {
1500 /* set real mode segment descriptor (keep limit etc. for
1501 * unreal mode) */
03ebebeb 1502 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1503 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1504 goto load;
f8da94e9
KW		 1505 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1506 /* VM86 needs a clean new segment descriptor */
1507 set_desc_base(&seg_desc, selector << 4);
1508 set_desc_limit(&seg_desc, 0xffff);
1509 seg_desc.type = 3;
1510 seg_desc.p = 1;
1511 seg_desc.s = 1;
1512 seg_desc.dpl = 3;
1513 goto load;
dde7e6d1
AK		 1514 }
1515
79d5b4c3 1516 rpl = selector & 3;
79d5b4c3
AK		 1517
1518 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1519 if ((seg == VCPU_SREG_CS
1520 || (seg == VCPU_SREG_SS
1521 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1522 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1523 && null_selector)
1524 goto exception;
1525
1526 /* TR should be in GDT only */
1527 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1528 goto exception;
1529
1530 if (null_selector) /* for NULL selector skip all following checks */
1531 goto load;
1532
e919464b 1533 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1534 if (ret != X86EMUL_CONTINUE)
1535 return ret;
1536
1537 err_code = selector & 0xfffc;
15fc0752 1538 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
dde7e6d1 1539
fc058680 1540 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1541 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1542 goto exception;
1543
1544 if (!seg_desc.p) {
1545 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1546 goto exception;
1547 }
1548
dde7e6d1 1549 dpl = seg_desc.dpl;
dde7e6d1
AK		 1550
1551 switch (seg) {
1552 case VCPU_SREG_SS:
1553 /*
1554 * segment is not a writable data segment or segment
1555 * selector's RPL != CPL or segment selector's RPL != CPL
1556 */
1557 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1558 goto exception;
6aa8b732 1559 break;
dde7e6d1
AK		 1560 case VCPU_SREG_CS:
1561 if (!(seg_desc.type & 8))
1562 goto exception;
1563
1564 if (seg_desc.type & 4) {
1565 /* conforming */
1566 if (dpl > cpl)
1567 goto exception;
1568 } else {
1569 /* nonconforming */
1570 if (rpl > cpl || dpl != cpl)
1571 goto exception;
1572 }
040c8dc8
NA		 1573 /* in long-mode d/b must be clear if l is set */
1574 if (seg_desc.d && seg_desc.l) {
1575 u64 efer = 0;
1576
1577 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1578 if (efer & EFER_LMA)
1579 goto exception;
1580 }
1581
dde7e6d1
AK		 1582 /* CS(RPL) <- CPL */
1583 selector = (selector & 0xfffc) | cpl;
6aa8b732 1584 break;
dde7e6d1
AK		 1585 case VCPU_SREG_TR:
1586 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1587 goto exception;
869be99c
AK		 1588 old_desc = seg_desc;
1589 seg_desc.type |= 2; /* busy */
1590 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1591 sizeof(seg_desc), &ctxt->exception);
1592 if (ret != X86EMUL_CONTINUE)
1593 return ret;
dde7e6d1
AK		 1594 break;
1595 case VCPU_SREG_LDTR:
1596 if (seg_desc.s || seg_desc.type != 2)
1597 goto exception;
1598 break;
1599 default: /* DS, ES, FS, or GS */
4e62417b 1600 /*
dde7e6d1
AK		 1601 * segment is not a data or readable code segment or
1602 * ((segment is a data or nonconforming code segment)
1603 * and (both RPL and CPL > DPL))
4e62417b 1604 */
dde7e6d1
AK		 1605 if ((seg_desc.type & 0xa) == 0x8 ||
1606 (((seg_desc.type & 0xc) != 0xc) &&
1607 (rpl > dpl && cpl > dpl)))
1608 goto exception;
6aa8b732 1609 break;
dde7e6d1
AK		 1610 }
1611
1612 if (seg_desc.s) {
1613 /* mark segment as accessed */
1614 seg_desc.type |= 1;
7b105ca2 1615 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1616 if (ret != X86EMUL_CONTINUE)
1617 return ret;
e37a75a1
NA		 1618 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1619 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1620 sizeof(base3), &ctxt->exception);
1621 if (ret != X86EMUL_CONTINUE)
1622 return ret;
9a9abf6b
NA		 1623 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1624 ((u64)base3 << 32)))
1625 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1626 }
1627load:
e37a75a1 1628 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1629 if (desc)
1630 *desc = seg_desc;
dde7e6d1
AK		 1631 return X86EMUL_CONTINUE;
1632exception:
592f0858 1633 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1634}
1635
2356aaeb
PB		 1636static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1637 u16 selector, int seg)
1638{
1639 u8 cpl = ctxt->ops->cpl(ctxt);
d1442d85 1640 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
2356aaeb
PB		 1641}
1642
31be40b3
WY		 1643static void write_register_operand(struct operand *op)
1644{
1645 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1646 switch (op->bytes) {
1647 case 1:
1648 *(u8 *)op->addr.reg = (u8)op->val;
1649 break;
1650 case 2:
1651 *(u16 *)op->addr.reg = (u16)op->val;
1652 break;
1653 case 4:
1654 *op->addr.reg = (u32)op->val;
1655 break; /* 64b: zero-extend */
1656 case 8:
1657 *op->addr.reg = op->val;
1658 break;
1659 }
1660}
1661
fb32b1ed 1662static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1663{
fb32b1ed 1664 switch (op->type) {
dde7e6d1 1665 case OP_REG:
fb32b1ed 1666 write_register_operand(op);
6aa8b732 1667 break;
dde7e6d1 1668 case OP_MEM:
9dac77fa 1669 if (ctxt->lock_prefix)
f5f87dfb
PB		 1670 return segmented_cmpxchg(ctxt,
1671 op->addr.mem,
1672 &op->orig_val,
1673 &op->val,
1674 op->bytes);
1675 else
1676 return segmented_write(ctxt,
fb32b1ed 1677 op->addr.mem,
fb32b1ed
AK		 1678 &op->val,
1679 op->bytes);
a682e354 1680 break;
b3356bf0 1681 case OP_MEM_STR:
f5f87dfb
PB		 1682 return segmented_write(ctxt,
1683 op->addr.mem,
1684 op->data,
1685 op->bytes * op->count);
b3356bf0 1686 break;
1253791d 1687 case OP_XMM:
fb32b1ed 1688 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1689 break;
cbe2c9d3 1690 case OP_MM:
fb32b1ed 1691 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1692 break;
dde7e6d1
AK		 1693 case OP_NONE:
1694 /* no writeback */
414e6277 1695 break;
dde7e6d1 1696 default:
414e6277 1697 break;
6aa8b732 1698 }
dde7e6d1
AK		 1699 return X86EMUL_CONTINUE;
1700}
6aa8b732 1701
51ddff50 1702static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1703{
4179bb02 1704 struct segmented_address addr;
0dc8d10f 1705
5ad105e5 1706 rsp_increment(ctxt, -bytes);
dd856efa 1707 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1708 addr.seg = VCPU_SREG_SS;
1709
51ddff50
AK		 1710 return segmented_write(ctxt, addr, data, bytes);
1711}
1712
1713static int em_push(struct x86_emulate_ctxt *ctxt)
1714{
4179bb02 1715 /* Disable writeback. */
9dac77fa 1716 ctxt->dst.type = OP_NONE;
51ddff50 1717 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1718}
69f55cb1 1719
dde7e6d1 1720static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1721 void *dest, int len)
1722{
dde7e6d1 1723 int rc;
90de84f5 1724 struct segmented_address addr;
8b4caf66 1725
dd856efa 1726 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1727 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1728 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
1731
5ad105e5 1732 rsp_increment(ctxt, len);
dde7e6d1 1733 return rc;
8b4caf66
LV		 1734}
1735
c54fe504
TY		 1736static int em_pop(struct x86_emulate_ctxt *ctxt)
1737{
9dac77fa 1738 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1739}
1740
dde7e6d1 1741static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1742 void *dest, int len)
9de41573
GN		 1743{
1744 int rc;
dde7e6d1
AK		 1745 unsigned long val, change_mask;
1746 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1747 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1748
3b9be3bf 1749 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1750 if (rc != X86EMUL_CONTINUE)
1751 return rc;
9de41573 1752
dde7e6d1 1753 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1754 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1755
dde7e6d1
AK		 1756 switch(ctxt->mode) {
1757 case X86EMUL_MODE_PROT64:
1758 case X86EMUL_MODE_PROT32:
1759 case X86EMUL_MODE_PROT16:
1760 if (cpl == 0)
1761 change_mask |= EFLG_IOPL;
1762 if (cpl <= iopl)
1763 change_mask |= EFLG_IF;
1764 break;
1765 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1766 if (iopl < 3)
1767 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1768 change_mask |= EFLG_IF;
1769 break;
1770 default: /* real mode */
1771 change_mask |= (EFLG_IOPL | EFLG_IF);
1772 break;
9de41573 1773 }
dde7e6d1
AK		 1774
1775 *(unsigned long *)dest =
1776 (ctxt->eflags & ~change_mask) | (val & change_mask);
1777
1778 return rc;
9de41573
GN		 1779}
1780
62aaa2f0
TY		 1781static int em_popf(struct x86_emulate_ctxt *ctxt)
1782{
9dac77fa
AK		 1783 ctxt->dst.type = OP_REG;
1784 ctxt->dst.addr.reg = &ctxt->eflags;
1785 ctxt->dst.bytes = ctxt->op_bytes;
1786 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1787}
1788
612e89f0
AK		 1789static int em_enter(struct x86_emulate_ctxt *ctxt)
1790{
1791 int rc;
1792 unsigned frame_size = ctxt->src.val;
1793 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1794 ulong rbp;
612e89f0
AK		 1795
1796 if (nesting_level)
1797 return X86EMUL_UNHANDLEABLE;
1798
dd856efa
AK		 1799 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1800 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1801 if (rc != X86EMUL_CONTINUE)
1802 return rc;
dd856efa 1803 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1804 stack_mask(ctxt));
dd856efa
AK		 1805 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1806 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1807 stack_mask(ctxt));
1808 return X86EMUL_CONTINUE;
1809}
1810
f47cfa31
AK		 1811static int em_leave(struct x86_emulate_ctxt *ctxt)
1812{
dd856efa 1813 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1814 stack_mask(ctxt));
dd856efa 1815 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1816}
1817
1cd196ea 1818static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1819{
1cd196ea
AK		 1820 int seg = ctxt->src2.val;
1821
9dac77fa 1822 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1823 if (ctxt->op_bytes == 4) {
1824 rsp_increment(ctxt, -2);
1825 ctxt->op_bytes = 2;
1826 }
7b262e90 1827
4487b3b4 1828 return em_push(ctxt);
7b262e90
GN		 1829}
1830
1cd196ea 1831static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1832{
1cd196ea 1833 int seg = ctxt->src2.val;
dde7e6d1
AK		 1834 unsigned long selector;
1835 int rc;
38ba30ba 1836
9dac77fa 1837 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
1840
a5457e7b
PB		 1841 if (ctxt->modrm_reg == VCPU_SREG_SS)
1842 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1843
7b105ca2 1844 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1845 return rc;
38ba30ba
GN		 1846}
1847
b96a7fad 1848static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1849{
dd856efa 1850 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1851 int rc = X86EMUL_CONTINUE;
1852 int reg = VCPU_REGS_RAX;
38ba30ba 1853
dde7e6d1
AK		 1854 while (reg <= VCPU_REGS_RDI) {
1855 (reg == VCPU_REGS_RSP) ?
dd856efa 1856 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1857
4487b3b4 1858 rc = em_push(ctxt);
dde7e6d1
AK		 1859 if (rc != X86EMUL_CONTINUE)
1860 return rc;
38ba30ba 1861
dde7e6d1 1862 ++reg;
38ba30ba 1863 }
38ba30ba 1864
dde7e6d1 1865 return rc;
38ba30ba
GN		 1866}
1867
62aaa2f0
TY		 1868static int em_pushf(struct x86_emulate_ctxt *ctxt)
1869{
9dac77fa 1870 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1871 return em_push(ctxt);
1872}
1873
b96a7fad 1874static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1875{
dde7e6d1
AK		 1876 int rc = X86EMUL_CONTINUE;
1877 int reg = VCPU_REGS_RDI;
38ba30ba 1878
dde7e6d1
AK		 1879 while (reg >= VCPU_REGS_RAX) {
1880 if (reg == VCPU_REGS_RSP) {
5ad105e5 1881 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1882 --reg;
1883 }
38ba30ba 1884
dd856efa 1885 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1886 if (rc != X86EMUL_CONTINUE)
1887 break;
1888 --reg;
38ba30ba 1889 }
dde7e6d1 1890 return rc;
38ba30ba
GN		 1891}
1892
dd856efa 1893static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1894{
0225fb50 1895 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1896 int rc;
6e154e56
MG		 1897 struct desc_ptr dt;
1898 gva_t cs_addr;
1899 gva_t eip_addr;
1900 u16 cs, eip;
6e154e56
MG		 1901
1902 /* TODO: Add limit checks */
9dac77fa 1903 ctxt->src.val = ctxt->eflags;
4487b3b4 1904 rc = em_push(ctxt);
5c56e1cf
AK		 1905 if (rc != X86EMUL_CONTINUE)
1906 return rc;
6e154e56
MG		 1907
1908 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1909
9dac77fa 1910 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1911 rc = em_push(ctxt);
5c56e1cf
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
6e154e56 1914
9dac77fa 1915 ctxt->src.val = ctxt->_eip;
4487b3b4 1916 rc = em_push(ctxt);
5c56e1cf
AK		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
1919
4bff1e86 1920 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1921
1922 eip_addr = dt.address + (irq << 2);
1923 cs_addr = dt.address + (irq << 2) + 2;
1924
0f65dd70 1925 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1926 if (rc != X86EMUL_CONTINUE)
1927 return rc;
1928
0f65dd70 1929 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
1932
7b105ca2 1933 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1934 if (rc != X86EMUL_CONTINUE)
1935 return rc;
1936
9dac77fa 1937 ctxt->_eip = eip;
6e154e56
MG		 1938
1939 return rc;
1940}
1941
dd856efa
AK		 1942int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1943{
1944 int rc;
1945
1946 invalidate_registers(ctxt);
1947 rc = __emulate_int_real(ctxt, irq);
1948 if (rc == X86EMUL_CONTINUE)
1949 writeback_registers(ctxt);
1950 return rc;
1951}
1952
7b105ca2 1953static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1954{
1955 switch(ctxt->mode) {
1956 case X86EMUL_MODE_REAL:
dd856efa 1957 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1958 case X86EMUL_MODE_VM86:
1959 case X86EMUL_MODE_PROT16:
1960 case X86EMUL_MODE_PROT32:
1961 case X86EMUL_MODE_PROT64:
1962 default:
1963 /* Protected mode interrupts unimplemented yet */
1964 return X86EMUL_UNHANDLEABLE;
1965 }
1966}
1967
7b105ca2 1968static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1969{
dde7e6d1
AK		 1970 int rc = X86EMUL_CONTINUE;
1971 unsigned long temp_eip = 0;
1972 unsigned long temp_eflags = 0;
1973 unsigned long cs = 0;
1974 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1975 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1976 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1977 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1978
dde7e6d1 1979 /* TODO: Add stack limit check */
38ba30ba 1980
9dac77fa 1981 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1982
dde7e6d1
AK		 1983 if (rc != X86EMUL_CONTINUE)
1984 return rc;
38ba30ba 1985
35d3d4a1
AK		 1986 if (temp_eip & ~0xffff)
1987 return emulate_gp(ctxt, 0);
38ba30ba 1988
9dac77fa 1989 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1990
dde7e6d1
AK		 1991 if (rc != X86EMUL_CONTINUE)
1992 return rc;
38ba30ba 1993
9dac77fa 1994 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1995
dde7e6d1
AK		 1996 if (rc != X86EMUL_CONTINUE)
1997 return rc;
38ba30ba 1998
7b105ca2 1999 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2000
dde7e6d1
AK		 2001 if (rc != X86EMUL_CONTINUE)
2002 return rc;
38ba30ba 2003
9dac77fa 2004 ctxt->_eip = temp_eip;
38ba30ba 2005
38ba30ba 2006
9dac77fa 2007 if (ctxt->op_bytes == 4)
dde7e6d1 2008 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2009 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2010 ctxt->eflags &= ~0xffff;
2011 ctxt->eflags |= temp_eflags;
38ba30ba 2012 }
dde7e6d1
AK		 2013
2014 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2015 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2016
2017 return rc;
38ba30ba
GN		 2018}
2019
e01991e7 2020static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2021{
dde7e6d1
AK		 2022 switch(ctxt->mode) {
2023 case X86EMUL_MODE_REAL:
7b105ca2 2024 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2025 case X86EMUL_MODE_VM86:
2026 case X86EMUL_MODE_PROT16:
2027 case X86EMUL_MODE_PROT32:
2028 case X86EMUL_MODE_PROT64:
c37eda13 2029 default:
dde7e6d1
AK		 2030 /* iret from protected mode unimplemented yet */
2031 return X86EMUL_UNHANDLEABLE;
c37eda13 2032 }
c37eda13
WY		 2033}
2034
d2f62766
TY		 2035static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2036{
d2f62766 2037 int rc;
d1442d85
NA		 2038 unsigned short sel, old_sel;
2039 struct desc_struct old_desc, new_desc;
2040 const struct x86_emulate_ops *ops = ctxt->ops;
2041 u8 cpl = ctxt->ops->cpl(ctxt);
2042
2043 /* Assignment of RIP may only fail in 64-bit mode */
2044 if (ctxt->mode == X86EMUL_MODE_PROT64)
2045 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2046 VCPU_SREG_CS);
d2f62766 2047
9dac77fa 2048 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2049
d1442d85
NA		 2050 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2051 &new_desc);
d2f62766
TY		 2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
2054
d1442d85
NA		 2055 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2056 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2057 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2058 /* assigning eip failed; restore the old cs */
2059 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2060 return rc;
2061 }
2062 return rc;
d2f62766
TY		 2063}
2064
f7784046 2065static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2066{
f7784046
NA		 2067 return assign_eip_near(ctxt, ctxt->src.val);
2068}
8cdbd2c9 2069
f7784046
NA		 2070static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2071{
2072 int rc;
2073 long int old_eip;
2074
2075 old_eip = ctxt->_eip;
2076 rc = assign_eip_near(ctxt, ctxt->src.val);
2077 if (rc != X86EMUL_CONTINUE)
2078 return rc;
2079 ctxt->src.val = old_eip;
2080 rc = em_push(ctxt);
4179bb02 2081 return rc;
8cdbd2c9
LV		 2082}
2083
e0dac408 2084static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2085{
9dac77fa 2086 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2087
aaa05f24
NA		 2088 if (ctxt->dst.bytes == 16)
2089 return X86EMUL_UNHANDLEABLE;
2090
dd856efa
AK		 2091 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2092 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2093 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2094 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2095 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2096 } else {
dd856efa
AK		 2097 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2098 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2099
05f086f8 2100 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2101 }
1b30eaa8 2102 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2103}
2104
ebda02c2
TY		 2105static int em_ret(struct x86_emulate_ctxt *ctxt)
2106{
234f3ce4
NA		 2107 int rc;
2108 unsigned long eip;
2109
2110 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2111 if (rc != X86EMUL_CONTINUE)
2112 return rc;
2113
2114 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2115}
2116
e01991e7 2117static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2118{
a77ab5ea 2119 int rc;
d1442d85
NA		 2120 unsigned long eip, cs;
2121 u16 old_cs;
9e8919ae 2122 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2123 struct desc_struct old_desc, new_desc;
2124 const struct x86_emulate_ops *ops = ctxt->ops;
2125
2126 if (ctxt->mode == X86EMUL_MODE_PROT64)
2127 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2128 VCPU_SREG_CS);
a77ab5ea 2129
d1442d85 2130 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2131 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2132 return rc;
9dac77fa 2133 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2134 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2135 return rc;
9e8919ae
NA		 2136 /* Outer-privilege level return is not implemented */
2137 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2138 return X86EMUL_UNHANDLEABLE;
d1442d85
NA		 2139 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2140 &new_desc);
2141 if (rc != X86EMUL_CONTINUE)
2142 return rc;
2143 rc = assign_eip_far(ctxt, eip, new_desc.l);
2144 if (rc != X86EMUL_CONTINUE) {
cd9b8e2c 2145 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2146 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2147 }
a77ab5ea
AK		 2148 return rc;
2149}
2150
3261107e
BR		 2151static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2152{
2153 int rc;
2154
2155 rc = em_ret_far(ctxt);
2156 if (rc != X86EMUL_CONTINUE)
2157 return rc;
2158 rsp_increment(ctxt, ctxt->src.val);
2159 return X86EMUL_CONTINUE;
2160}
2161
e940b5c2
TY		 2162static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2163{
2164 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2165 ctxt->dst.orig_val = ctxt->dst.val;
2166 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2167 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2168 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2169 fastop(ctxt, em_cmp);
e940b5c2
TY		 2170
2171 if (ctxt->eflags & EFLG_ZF) {
2172 /* Success: write back to memory. */
2173 ctxt->dst.val = ctxt->src.orig_val;
2174 } else {
2175 /* Failure: write the value we saw to EAX. */
2176 ctxt->dst.type = OP_REG;
dd856efa 2177 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2178 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2179 }
2180 return X86EMUL_CONTINUE;
2181}
2182
d4b4325f 2183static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2184{
d4b4325f 2185 int seg = ctxt->src2.val;
09b5f4d3
WY		 2186 unsigned short sel;
2187 int rc;
2188
9dac77fa 2189 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2190
7b105ca2 2191 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2192 if (rc != X86EMUL_CONTINUE)
2193 return rc;
2194
9dac77fa 2195 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2196 return rc;
2197}
2198
7b105ca2 2199static void
e66bb2cc 2200setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2201 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2202{
e66bb2cc 2203 cs->l = 0; /* will be adjusted later */
79168fd1 2204 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2205 cs->g = 1; /* 4kb granularity */
79168fd1 2206 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2207 cs->type = 0x0b; /* Read, Execute, Accessed */
2208 cs->s = 1;
2209 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2210 cs->p = 1;
2211 cs->d = 1;
99245b50 2212 cs->avl = 0;
e66bb2cc 2213
79168fd1
GN		 2214 set_desc_base(ss, 0); /* flat segment */
2215 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2216 ss->g = 1; /* 4kb granularity */
2217 ss->s = 1;
2218 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2219 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2220 ss->dpl = 0;
79168fd1 2221 ss->p = 1;
99245b50
GN		 2222 ss->l = 0;
2223 ss->avl = 0;
e66bb2cc
AP		 2224}
2225
1a18a69b
AK		 2226static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2227{
2228 u32 eax, ebx, ecx, edx;
2229
2230 eax = ecx = 0;
0017f93a
AK		 2231 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2232 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2233 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2234 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2235}
2236
c2226fc9
SB		 2237static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2238{
0225fb50 2239 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2240 u32 eax, ebx, ecx, edx;
2241
2242 /*
2243 * syscall should always be enabled in longmode - so only become
2244 * vendor specific (cpuid) if other modes are active...
2245 */
2246 if (ctxt->mode == X86EMUL_MODE_PROT64)
2247 return true;
2248
2249 eax = 0x00000000;
2250 ecx = 0x00000000;
0017f93a
AK		 2251 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2252 /*
2253 * Intel ("GenuineIntel")
2254 * remark: Intel CPUs only support "syscall" in 64bit
2255 * longmode. Also an 64bit guest with a
2256 * 32bit compat-app running will #UD !! While this
2257 * behaviour can be fixed (by emulating) into AMD
2258 * response - CPUs of AMD can't behave like Intel.
2259 */
2260 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2261 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2262 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2263 return false;
2264
2265 /* AMD ("AuthenticAMD") */
2266 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2267 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2268 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2269 return true;
2270
2271 /* AMD ("AMDisbetter!") */
2272 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2273 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2274 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2275 return true;
c2226fc9
SB		 2276
2277 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2278 return false;
2279}
2280
e01991e7 2281static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2282{
0225fb50 2283 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2284 struct desc_struct cs, ss;
e66bb2cc 2285 u64 msr_data;
79168fd1 2286 u16 cs_sel, ss_sel;
c2ad2bb3 2287 u64 efer = 0;
e66bb2cc
AP		 2288
2289 /* syscall is not available in real mode */
2e901c4c 2290 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2291 ctxt->mode == X86EMUL_MODE_VM86)
2292 return emulate_ud(ctxt);
e66bb2cc 2293
c2226fc9
SB		 2294 if (!(em_syscall_is_enabled(ctxt)))
2295 return emulate_ud(ctxt);
2296
c2ad2bb3 2297 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2298 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2299
c2226fc9
SB		 2300 if (!(efer & EFER_SCE))
2301 return emulate_ud(ctxt);
2302
717746e3 2303 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2304 msr_data >>= 32;
79168fd1
GN		 2305 cs_sel = (u16)(msr_data & 0xfffc);
2306 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2307
c2ad2bb3 2308 if (efer & EFER_LMA) {
79168fd1 2309 cs.d = 0;
e66bb2cc
AP		 2310 cs.l = 1;
2311 }
1aa36616
AK		 2312 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2313 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2314
dd856efa 2315 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2316 if (efer & EFER_LMA) {
e66bb2cc 2317#ifdef CONFIG_X86_64
6c6cb69b 2318 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2319
717746e3 2320 ops->get_msr(ctxt,
3fb1b5db
GN		 2321 ctxt->mode == X86EMUL_MODE_PROT64 ?
2322 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2323 ctxt->_eip = msr_data;
e66bb2cc 2324
717746e3 2325 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2326 ctxt->eflags &= ~msr_data;
807c1425 2327 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2328#endif
2329 } else {
2330 /* legacy mode */
717746e3 2331 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2332 ctxt->_eip = (u32)msr_data;
e66bb2cc 2333
6c6cb69b 2334 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2335 }
2336
e54cfa97 2337 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2338}
2339
e01991e7 2340static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2341{
0225fb50 2342 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2343 struct desc_struct cs, ss;
8c604352 2344 u64 msr_data;
79168fd1 2345 u16 cs_sel, ss_sel;
c2ad2bb3 2346 u64 efer = 0;
8c604352 2347
7b105ca2 2348 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2349 /* inject #GP if in real mode */
35d3d4a1
AK		 2350 if (ctxt->mode == X86EMUL_MODE_REAL)
2351 return emulate_gp(ctxt, 0);
8c604352 2352
1a18a69b
AK		 2353 /*
2354 * Not recognized on AMD in compat mode (but is recognized in legacy
2355 * mode).
2356 */
2357 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2358 && !vendor_intel(ctxt))
2359 return emulate_ud(ctxt);
2360
b2c9d43e 2361 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2362 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2363 return X86EMUL_UNHANDLEABLE;
8c604352 2364
7b105ca2 2365 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2366
717746e3 2367 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2368 switch (ctxt->mode) {
2369 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2370 if ((msr_data & 0xfffc) == 0x0)
2371 return emulate_gp(ctxt, 0);
8c604352
AP		 2372 break;
2373 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2374 if (msr_data == 0x0)
2375 return emulate_gp(ctxt, 0);
8c604352 2376 break;
9d1b39a9
GN		 2377 default:
2378 break;
8c604352
AP		 2379 }
2380
6c6cb69b 2381 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2382 cs_sel = (u16)msr_data;
2383 cs_sel &= ~SELECTOR_RPL_MASK;
2384 ss_sel = cs_sel + 8;
2385 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2386 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2387 cs.d = 0;
8c604352
AP		 2388 cs.l = 1;
2389 }
2390
1aa36616
AK		 2391 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2392 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2393
717746e3 2394 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2395 ctxt->_eip = msr_data;
8c604352 2396
717746e3 2397 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2398 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2399
e54cfa97 2400 return X86EMUL_CONTINUE;
8c604352
AP		 2401}
2402
e01991e7 2403static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2404{
0225fb50 2405 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2406 struct desc_struct cs, ss;
234f3ce4 2407 u64 msr_data, rcx, rdx;
4668f050 2408 int usermode;
1249b96e 2409 u16 cs_sel = 0, ss_sel = 0;
4668f050 2410
a0044755
GN		 2411 /* inject #GP if in real mode or Virtual 8086 mode */
2412 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2413 ctxt->mode == X86EMUL_MODE_VM86)
2414 return emulate_gp(ctxt, 0);
4668f050 2415
7b105ca2 2416 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2417
9dac77fa 2418 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2419 usermode = X86EMUL_MODE_PROT64;
2420 else
2421 usermode = X86EMUL_MODE_PROT32;
2422
234f3ce4
NA		 2423 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2424 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2425
4668f050
AP		 2426 cs.dpl = 3;
2427 ss.dpl = 3;
717746e3 2428 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2429 switch (usermode) {
2430 case X86EMUL_MODE_PROT32:
79168fd1 2431 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2432 if ((msr_data & 0xfffc) == 0x0)
2433 return emulate_gp(ctxt, 0);
79168fd1 2434 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2435 rcx = (u32)rcx;
2436 rdx = (u32)rdx;
4668f050
AP		 2437 break;
2438 case X86EMUL_MODE_PROT64:
79168fd1 2439 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2440 if (msr_data == 0x0)
2441 return emulate_gp(ctxt, 0);
79168fd1
GN		 2442 ss_sel = cs_sel + 8;
2443 cs.d = 0;
4668f050 2444 cs.l = 1;
234f3ce4
NA		 2445 if (is_noncanonical_address(rcx) ||
2446 is_noncanonical_address(rdx))
2447 return emulate_gp(ctxt, 0);
4668f050
AP		 2448 break;
2449 }
79168fd1
GN		 2450 cs_sel |= SELECTOR_RPL_MASK;
2451 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2452
1aa36616
AK		 2453 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2454 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2455
234f3ce4
NA		 2456 ctxt->_eip = rdx;
2457 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2458
e54cfa97 2459 return X86EMUL_CONTINUE;
4668f050
AP		 2460}
2461
7b105ca2 2462static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2463{
2464 int iopl;
2465 if (ctxt->mode == X86EMUL_MODE_REAL)
2466 return false;
2467 if (ctxt->mode == X86EMUL_MODE_VM86)
2468 return true;
2469 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2470 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2471}
2472
2473static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2474 u16 port, u16 len)
2475{
0225fb50 2476 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2477 struct desc_struct tr_seg;
5601d05b 2478 u32 base3;
f850e2e6 2479 int r;
1aa36616 2480 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2481 unsigned mask = (1 << len) - 1;
5601d05b 2482 unsigned long base;
f850e2e6 2483
1aa36616 2484 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2485 if (!tr_seg.p)
f850e2e6 2486 return false;
79168fd1 2487 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2488 return false;
5601d05b
GN		 2489 base = get_desc_base(&tr_seg);
2490#ifdef CONFIG_X86_64
2491 base |= ((u64)base3) << 32;
2492#endif
0f65dd70 2493 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2494 if (r != X86EMUL_CONTINUE)
2495 return false;
79168fd1 2496 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2497 return false;
0f65dd70 2498 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2499 if (r != X86EMUL_CONTINUE)
2500 return false;
2501 if ((perm >> bit_idx) & mask)
2502 return false;
2503 return true;
2504}
2505
2506static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2507 u16 port, u16 len)
2508{
4fc40f07
GN		 2509 if (ctxt->perm_ok)
2510 return true;
2511
7b105ca2
TY		 2512 if (emulator_bad_iopl(ctxt))
2513 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2514 return false;
4fc40f07
GN		 2515
2516 ctxt->perm_ok = true;
2517
f850e2e6
GN		 2518 return true;
2519}
2520
38ba30ba 2521static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2522 struct tss_segment_16 *tss)
2523{
9dac77fa 2524 tss->ip = ctxt->_eip;
38ba30ba 2525 tss->flag = ctxt->eflags;
dd856efa
AK		 2526 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2527 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2528 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2529 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2530 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2531 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2532 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2533 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2534
1aa36616
AK		 2535 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2536 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2537 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2538 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2539 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2540}
2541
2542static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2543 struct tss_segment_16 *tss)
2544{
38ba30ba 2545 int ret;
2356aaeb 2546 u8 cpl;
38ba30ba 2547
9dac77fa 2548 ctxt->_eip = tss->ip;
38ba30ba 2549 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2550 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2551 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2552 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2553 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2554 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2555 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2556 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2557 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2558
2559 /*
2560 * SDM says that segment selectors are loaded before segment
2561 * descriptors
2562 */
1aa36616
AK		 2563 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2564 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2565 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2566 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2567 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2568
2356aaeb
PB		 2569 cpl = tss->cs & 3;
2570
38ba30ba 2571 /*
fc058680 2572 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2573 * it is handled in a context of new task
2574 */
d1442d85
NA		 2575 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2576 true, NULL);
38ba30ba
GN		 2577 if (ret != X86EMUL_CONTINUE)
2578 return ret;
d1442d85
NA		 2579 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2580 true, NULL);
38ba30ba
GN		 2581 if (ret != X86EMUL_CONTINUE)
2582 return ret;
d1442d85
NA		 2583 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2584 true, NULL);
38ba30ba
GN		 2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
d1442d85
NA		 2587 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2588 true, NULL);
38ba30ba
GN		 2589 if (ret != X86EMUL_CONTINUE)
2590 return ret;
d1442d85
NA		 2591 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2592 true, NULL);
38ba30ba
GN		 2593 if (ret != X86EMUL_CONTINUE)
2594 return ret;
2595
2596 return X86EMUL_CONTINUE;
2597}
2598
2599static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2600 u16 tss_selector, u16 old_tss_sel,
2601 ulong old_tss_base, struct desc_struct *new_desc)
2602{
0225fb50 2603 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2604 struct tss_segment_16 tss_seg;
2605 int ret;
bcc55cba 2606 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2607
0f65dd70 2608 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2609 &ctxt->exception);
db297e3d 2610 if (ret != X86EMUL_CONTINUE)
38ba30ba 2611 /* FIXME: need to provide precise fault address */
38ba30ba 2612 return ret;
38ba30ba 2613
7b105ca2 2614 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2615
0f65dd70 2616 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2617 &ctxt->exception);
db297e3d 2618 if (ret != X86EMUL_CONTINUE)
38ba30ba 2619 /* FIXME: need to provide precise fault address */
38ba30ba 2620 return ret;
38ba30ba 2621
0f65dd70 2622 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2623 &ctxt->exception);
db297e3d 2624 if (ret != X86EMUL_CONTINUE)
38ba30ba 2625 /* FIXME: need to provide precise fault address */
38ba30ba 2626 return ret;
38ba30ba
GN		 2627
2628 if (old_tss_sel != 0xffff) {
2629 tss_seg.prev_task_link = old_tss_sel;
2630
0f65dd70 2631 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2632 &tss_seg.prev_task_link,
2633 sizeof tss_seg.prev_task_link,
0f65dd70 2634 &ctxt->exception);
db297e3d 2635 if (ret != X86EMUL_CONTINUE)
38ba30ba 2636 /* FIXME: need to provide precise fault address */
38ba30ba 2637 return ret;
38ba30ba
GN		 2638 }
2639
7b105ca2 2640 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2641}
2642
2643static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2644 struct tss_segment_32 *tss)
2645{
5c7411e2 2646 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2647 tss->eip = ctxt->_eip;
38ba30ba 2648 tss->eflags = ctxt->eflags;
dd856efa
AK		 2649 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2650 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2651 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2652 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2653 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2654 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2655 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2656 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2657
1aa36616
AK		 2658 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2659 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2660 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2661 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2662 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2663 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2664}
2665
2666static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2667 struct tss_segment_32 *tss)
2668{
38ba30ba 2669 int ret;
2356aaeb 2670 u8 cpl;
38ba30ba 2671
7b105ca2 2672 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2673 return emulate_gp(ctxt, 0);
9dac77fa 2674 ctxt->_eip = tss->eip;
38ba30ba 2675 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2676
2677 /* General purpose registers */
dd856efa
AK		 2678 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2679 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2680 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2681 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2682 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2683 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2684 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2685 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2686
2687 /*
2688 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2689 * descriptors. This is important because CPL checks will
2690 * use CS.RPL.
38ba30ba 2691 */
1aa36616
AK		 2692 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2693 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2694 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2695 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2696 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2697 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2698 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2699
4cee4798
KW		 2700 /*
2701 * If we're switching between Protected Mode and VM86, we need to make
2702 * sure to update the mode before loading the segment descriptors so
2703 * that the selectors are interpreted correctly.
4cee4798 2704 */
2356aaeb 2705 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2706 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2707 cpl = 3;
2708 } else {
4cee4798 2709 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2710 cpl = tss->cs & 3;
2711 }
4cee4798 2712
38ba30ba
GN		 2713 /*
2714 * Now load segment descriptors. If fault happenes at this stage
2715 * it is handled in a context of new task
2716 */
d1442d85
NA		 2717 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2718 cpl, true, NULL);
38ba30ba
GN		 2719 if (ret != X86EMUL_CONTINUE)
2720 return ret;
d1442d85
NA		 2721 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2722 true, NULL);
38ba30ba
GN		 2723 if (ret != X86EMUL_CONTINUE)
2724 return ret;
d1442d85
NA		 2725 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2726 true, NULL);
38ba30ba
GN		 2727 if (ret != X86EMUL_CONTINUE)
2728 return ret;
d1442d85
NA		 2729 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2730 true, NULL);
38ba30ba
GN		 2731 if (ret != X86EMUL_CONTINUE)
2732 return ret;
d1442d85
NA		 2733 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2734 true, NULL);
38ba30ba
GN		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
d1442d85
NA		 2737 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2738 true, NULL);
38ba30ba
GN		 2739 if (ret != X86EMUL_CONTINUE)
2740 return ret;
d1442d85
NA		 2741 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2742 true, NULL);
38ba30ba
GN		 2743 if (ret != X86EMUL_CONTINUE)
2744 return ret;
2745
2746 return X86EMUL_CONTINUE;
2747}
2748
2749static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2750 u16 tss_selector, u16 old_tss_sel,
2751 ulong old_tss_base, struct desc_struct *new_desc)
2752{
0225fb50 2753 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2754 struct tss_segment_32 tss_seg;
2755 int ret;
bcc55cba 2756 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2757 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2758 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2759
0f65dd70 2760 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2761 &ctxt->exception);
db297e3d 2762 if (ret != X86EMUL_CONTINUE)
38ba30ba 2763 /* FIXME: need to provide precise fault address */
38ba30ba 2764 return ret;
38ba30ba 2765
7b105ca2 2766 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2767
5c7411e2
NA		 2768 /* Only GP registers and segment selectors are saved */
2769 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2770 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2771 if (ret != X86EMUL_CONTINUE)
38ba30ba 2772 /* FIXME: need to provide precise fault address */
38ba30ba 2773 return ret;
38ba30ba 2774
0f65dd70 2775 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2776 &ctxt->exception);
db297e3d 2777 if (ret != X86EMUL_CONTINUE)
38ba30ba 2778 /* FIXME: need to provide precise fault address */
38ba30ba 2779 return ret;
38ba30ba
GN		 2780
2781 if (old_tss_sel != 0xffff) {
2782 tss_seg.prev_task_link = old_tss_sel;
2783
0f65dd70 2784 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2785 &tss_seg.prev_task_link,
2786 sizeof tss_seg.prev_task_link,
0f65dd70 2787 &ctxt->exception);
db297e3d 2788 if (ret != X86EMUL_CONTINUE)
38ba30ba 2789 /* FIXME: need to provide precise fault address */
38ba30ba 2790 return ret;
38ba30ba
GN		 2791 }
2792
7b105ca2 2793 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2794}
2795
2796static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2797 u16 tss_selector, int idt_index, int reason,
e269fb21 2798 bool has_error_code, u32 error_code)
38ba30ba 2799{
0225fb50 2800 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2801 struct desc_struct curr_tss_desc, next_tss_desc;
2802 int ret;
1aa36616 2803 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2804 ulong old_tss_base =
4bff1e86 2805 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2806 u32 desc_limit;
e919464b 2807 ulong desc_addr;
38ba30ba
GN		 2808
2809 /* FIXME: old_tss_base == ~0 ? */
2810
e919464b 2811 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2812 if (ret != X86EMUL_CONTINUE)
2813 return ret;
e919464b 2814 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2815 if (ret != X86EMUL_CONTINUE)
2816 return ret;
2817
2818 /* FIXME: check that next_tss_desc is tss */
2819
7f3d35fd
KW		 2820 /*
2821 * Check privileges. The three cases are task switch caused by...
2822 *
2823 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2824 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2825 * 3. jmp/call to TSS/task-gate: No check is performed since the
2826 * hardware checks it before exiting.
7f3d35fd
KW		 2827 */
2828 if (reason == TASK_SWITCH_GATE) {
2829 if (idt_index != -1) {
2830 /* Software interrupts */
2831 struct desc_struct task_gate_desc;
2832 int dpl;
2833
2834 ret = read_interrupt_descriptor(ctxt, idt_index,
2835 &task_gate_desc);
2836 if (ret != X86EMUL_CONTINUE)
2837 return ret;
2838
2839 dpl = task_gate_desc.dpl;
2840 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2841 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2842 }
38ba30ba
GN		 2843 }
2844
ceffb459
GN		 2845 desc_limit = desc_limit_scaled(&next_tss_desc);
2846 if (!next_tss_desc.p ||
2847 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2848 desc_limit < 0x2b)) {
592f0858 2849 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2850 }
2851
2852 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2853 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2854 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2855 }
2856
2857 if (reason == TASK_SWITCH_IRET)
2858 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2859
2860 /* set back link to prev task only if NT bit is set in eflags
fc058680 2861 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2862 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2863 old_tss_sel = 0xffff;
2864
2865 if (next_tss_desc.type & 8)
7b105ca2 2866 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2867 old_tss_base, &next_tss_desc);
2868 else
7b105ca2 2869 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2870 old_tss_base, &next_tss_desc);
0760d448
JK		 2871 if (ret != X86EMUL_CONTINUE)
2872 return ret;
38ba30ba
GN		 2873
2874 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2875 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2876
2877 if (reason != TASK_SWITCH_IRET) {
2878 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2879 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2880 }
2881
717746e3 2882 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2883 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2884
e269fb21 2885 if (has_error_code) {
9dac77fa
AK		 2886 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2887 ctxt->lock_prefix = 0;
2888 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2889 ret = em_push(ctxt);
e269fb21
JK		 2890 }
2891
38ba30ba
GN		 2892 return ret;
2893}
2894
2895int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2896 u16 tss_selector, int idt_index, int reason,
e269fb21 2897 bool has_error_code, u32 error_code)
38ba30ba 2898{
38ba30ba
GN		 2899 int rc;
2900
dd856efa 2901 invalidate_registers(ctxt);
9dac77fa
AK		 2902 ctxt->_eip = ctxt->eip;
2903 ctxt->dst.type = OP_NONE;
38ba30ba 2904
7f3d35fd 2905 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2906 has_error_code, error_code);
38ba30ba 2907
dd856efa 2908 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2909 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2910 writeback_registers(ctxt);
2911 }
38ba30ba 2912
a0c0ab2f 2913 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2914}
2915
f3bd64c6
GN		 2916static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2917 struct operand *op)
a682e354 2918{
b3356bf0 2919 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2920
dd856efa
AK		 2921 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2922 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2923}
2924
7af04fc0
AK		 2925static int em_das(struct x86_emulate_ctxt *ctxt)
2926{
7af04fc0
AK		 2927 u8 al, old_al;
2928 bool af, cf, old_cf;
2929
2930 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2931 al = ctxt->dst.val;
7af04fc0
AK		 2932
2933 old_al = al;
2934 old_cf = cf;
2935 cf = false;
2936 af = ctxt->eflags & X86_EFLAGS_AF;
2937 if ((al & 0x0f) > 9 || af) {
2938 al -= 6;
2939 cf = old_cf | (al >= 250);
2940 af = true;
2941 } else {
2942 af = false;
2943 }
2944 if (old_al > 0x99 || old_cf) {
2945 al -= 0x60;
2946 cf = true;
2947 }
2948
9dac77fa 2949 ctxt->dst.val = al;
7af04fc0 2950 /* Set PF, ZF, SF */
9dac77fa
AK		 2951 ctxt->src.type = OP_IMM;
2952 ctxt->src.val = 0;
2953 ctxt->src.bytes = 1;
158de57f 2954 fastop(ctxt, em_or);
7af04fc0
AK		 2955 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2956 if (cf)
2957 ctxt->eflags |= X86_EFLAGS_CF;
2958 if (af)
2959 ctxt->eflags |= X86_EFLAGS_AF;
2960 return X86EMUL_CONTINUE;
2961}
2962
a035d5c6
PB		 2963static int em_aam(struct x86_emulate_ctxt *ctxt)
2964{
2965 u8 al, ah;
2966
2967 if (ctxt->src.val == 0)
2968 return emulate_de(ctxt);
2969
2970 al = ctxt->dst.val & 0xff;
2971 ah = al / ctxt->src.val;
2972 al %= ctxt->src.val;
2973
2974 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2975
2976 /* Set PF, ZF, SF */
2977 ctxt->src.type = OP_IMM;
2978 ctxt->src.val = 0;
2979 ctxt->src.bytes = 1;
2980 fastop(ctxt, em_or);
2981
2982 return X86EMUL_CONTINUE;
2983}
2984
7f662273
GN		 2985static int em_aad(struct x86_emulate_ctxt *ctxt)
2986{
2987 u8 al = ctxt->dst.val & 0xff;
2988 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2989
2990 al = (al + (ah * ctxt->src.val)) & 0xff;
2991
2992 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2993
f583c29b
GN		 2994 /* Set PF, ZF, SF */
2995 ctxt->src.type = OP_IMM;
2996 ctxt->src.val = 0;
2997 ctxt->src.bytes = 1;
2998 fastop(ctxt, em_or);
7f662273
GN		 2999
3000 return X86EMUL_CONTINUE;
3001}
3002
d4ddafcd
TY		 3003static int em_call(struct x86_emulate_ctxt *ctxt)
3004{
234f3ce4 3005 int rc;
d4ddafcd
TY		 3006 long rel = ctxt->src.val;
3007
3008 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3009 rc = jmp_rel(ctxt, rel);
3010 if (rc != X86EMUL_CONTINUE)
3011 return rc;
d4ddafcd
TY		 3012 return em_push(ctxt);
3013}
3014
0ef753b8
AK		 3015static int em_call_far(struct x86_emulate_ctxt *ctxt)
3016{
0ef753b8
AK		 3017 u16 sel, old_cs;
3018 ulong old_eip;
3019 int rc;
d1442d85
NA		 3020 struct desc_struct old_desc, new_desc;
3021 const struct x86_emulate_ops *ops = ctxt->ops;
3022 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3023
9dac77fa 3024 old_eip = ctxt->_eip;
d1442d85 3025 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3026
9dac77fa 3027 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d1442d85
NA		 3028 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3029 &new_desc);
3030 if (rc != X86EMUL_CONTINUE)
0ef753b8
AK		 3031 return X86EMUL_CONTINUE;
3032
d1442d85
NA		 3033 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
3034 if (rc != X86EMUL_CONTINUE)
3035 goto fail;
0ef753b8 3036
9dac77fa 3037 ctxt->src.val = old_cs;
4487b3b4 3038 rc = em_push(ctxt);
0ef753b8 3039 if (rc != X86EMUL_CONTINUE)
d1442d85 3040 goto fail;
0ef753b8 3041
9dac77fa 3042 ctxt->src.val = old_eip;
d1442d85
NA		 3043 rc = em_push(ctxt);
3044 /* If we failed, we tainted the memory, but the very least we should
3045 restore cs */
3046 if (rc != X86EMUL_CONTINUE)
3047 goto fail;
3048 return rc;
3049fail:
3050 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3051 return rc;
3052
0ef753b8
AK		 3053}
3054
40ece7c7
AK		 3055static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3056{
40ece7c7 3057 int rc;
234f3ce4 3058 unsigned long eip;
40ece7c7 3059
234f3ce4
NA		 3060 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3061 if (rc != X86EMUL_CONTINUE)
3062 return rc;
3063 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3064 if (rc != X86EMUL_CONTINUE)
3065 return rc;
5ad105e5 3066 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3067 return X86EMUL_CONTINUE;
3068}
3069
e4f973ae
TY		 3070static int em_xchg(struct x86_emulate_ctxt *ctxt)
3071{
e4f973ae 3072 /* Write back the register source. */
9dac77fa
AK		 3073 ctxt->src.val = ctxt->dst.val;
3074 write_register_operand(&ctxt->src);
e4f973ae
TY		 3075
3076 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3077 ctxt->dst.val = ctxt->src.orig_val;
3078 ctxt->lock_prefix = 1;
e4f973ae
TY		 3079 return X86EMUL_CONTINUE;
3080}
3081
5c82aa29
AK		 3082static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3083{
9dac77fa 3084 ctxt->dst.val = ctxt->src2.val;
4d758349 3085 return fastop(ctxt, em_imul);
5c82aa29
AK		 3086}
3087
61429142
AK		 3088static int em_cwd(struct x86_emulate_ctxt *ctxt)
3089{
9dac77fa
AK		 3090 ctxt->dst.type = OP_REG;
3091 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3092 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3093 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3094
3095 return X86EMUL_CONTINUE;
3096}
3097
48bb5d3c
AK		 3098static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3099{
48bb5d3c
AK		 3100 u64 tsc = 0;
3101
717746e3 3102 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3103 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3104 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3105 return X86EMUL_CONTINUE;
3106}
3107
222d21aa
AK		 3108static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3109{
3110 u64 pmc;
3111
dd856efa 3112 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3113 return emulate_gp(ctxt, 0);
dd856efa
AK		 3114 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3115 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3116 return X86EMUL_CONTINUE;
3117}
3118
b9eac5f4
AK		 3119static int em_mov(struct x86_emulate_ctxt *ctxt)
3120{
54cfdb3e 3121 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3122 return X86EMUL_CONTINUE;
3123}
3124
84cffe49
BP		 3125#define FFL(x) bit(X86_FEATURE_##x)
3126
3127static int em_movbe(struct x86_emulate_ctxt *ctxt)
3128{
3129 u32 ebx, ecx, edx, eax = 1;
3130 u16 tmp;
3131
3132 /*
3133 * Check MOVBE is set in the guest-visible CPUID leaf.
3134 */
3135 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3136 if (!(ecx & FFL(MOVBE)))
3137 return emulate_ud(ctxt);
3138
3139 switch (ctxt->op_bytes) {
3140 case 2:
3141 /*
3142 * From MOVBE definition: "...When the operand size is 16 bits,
3143 * the upper word of the destination register remains unchanged
3144 * ..."
3145 *
3146 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3147 * rules so we have to do the operation almost per hand.
3148 */
3149 tmp = (u16)ctxt->src.val;
3150 ctxt->dst.val &= ~0xffffUL;
3151 ctxt->dst.val |= (unsigned long)swab16(tmp);
3152 break;
3153 case 4:
3154 ctxt->dst.val = swab32((u32)ctxt->src.val);
3155 break;
3156 case 8:
3157 ctxt->dst.val = swab64(ctxt->src.val);
3158 break;
3159 default:
592f0858 3160 BUG();
84cffe49
BP		 3161 }
3162 return X86EMUL_CONTINUE;
3163}
3164
bc00f8d2
TY		 3165static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3166{
3167 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3168 return emulate_gp(ctxt, 0);
3169
3170 /* Disable writeback. */
3171 ctxt->dst.type = OP_NONE;
3172 return X86EMUL_CONTINUE;
3173}
3174
3175static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3176{
3177 unsigned long val;
3178
3179 if (ctxt->mode == X86EMUL_MODE_PROT64)
3180 val = ctxt->src.val & ~0ULL;
3181 else
3182 val = ctxt->src.val & ~0U;
3183
3184 /* #UD condition is already handled. */
3185 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3186 return emulate_gp(ctxt, 0);
3187
3188 /* Disable writeback. */
3189 ctxt->dst.type = OP_NONE;
3190 return X86EMUL_CONTINUE;
3191}
3192
e1e210b0
TY		 3193static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3194{
3195 u64 msr_data;
3196
dd856efa
AK		 3197 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3198 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3199 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3200 return emulate_gp(ctxt, 0);
3201
3202 return X86EMUL_CONTINUE;
3203}
3204
3205static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3206{
3207 u64 msr_data;
3208
dd856efa 3209 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3210 return emulate_gp(ctxt, 0);
3211
dd856efa
AK		 3212 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3213 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3214 return X86EMUL_CONTINUE;
3215}
3216
1bd5f469
TY		 3217static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3218{
9dac77fa 3219 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3220 return emulate_ud(ctxt);
3221
9dac77fa 3222 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3223 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3224 ctxt->dst.bytes = 2;
1bd5f469
TY		 3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3229{
9dac77fa 3230 u16 sel = ctxt->src.val;
1bd5f469 3231
9dac77fa 3232 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3233 return emulate_ud(ctxt);
3234
9dac77fa 3235 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3236 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3237
3238 /* Disable writeback. */
9dac77fa
AK		 3239 ctxt->dst.type = OP_NONE;
3240 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3241}
3242
a14e579f
AK		 3243static int em_lldt(struct x86_emulate_ctxt *ctxt)
3244{
3245 u16 sel = ctxt->src.val;
3246
3247 /* Disable writeback. */
3248 ctxt->dst.type = OP_NONE;
3249 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3250}
3251
80890006
AK		 3252static int em_ltr(struct x86_emulate_ctxt *ctxt)
3253{
3254 u16 sel = ctxt->src.val;
3255
3256 /* Disable writeback. */
3257 ctxt->dst.type = OP_NONE;
3258 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3259}
3260
38503911
AK		 3261static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3262{
9fa088f4
AK		 3263 int rc;
3264 ulong linear;
3265
9dac77fa 3266 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3267 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3268 ctxt->ops->invlpg(ctxt, linear);
38503911 3269 /* Disable writeback. */
9dac77fa 3270 ctxt->dst.type = OP_NONE;
38503911
AK		 3271 return X86EMUL_CONTINUE;
3272}
3273
2d04a05b
AK		 3274static int em_clts(struct x86_emulate_ctxt *ctxt)
3275{
3276 ulong cr0;
3277
3278 cr0 = ctxt->ops->get_cr(ctxt, 0);
3279 cr0 &= ~X86_CR0_TS;
3280 ctxt->ops->set_cr(ctxt, 0, cr0);
3281 return X86EMUL_CONTINUE;
3282}
3283
26d05cc7
AK		 3284static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3285{
0f54a321 3286 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3287
26d05cc7
AK		 3288 if (rc != X86EMUL_CONTINUE)
3289 return rc;
3290
3291 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3292 ctxt->_eip = ctxt->eip;
26d05cc7 3293 /* Disable writeback. */
9dac77fa 3294 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3295 return X86EMUL_CONTINUE;
3296}
3297
96051572
AK		 3298static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3299 void (*get)(struct x86_emulate_ctxt *ctxt,
3300 struct desc_ptr *ptr))
3301{
3302 struct desc_ptr desc_ptr;
3303
3304 if (ctxt->mode == X86EMUL_MODE_PROT64)
3305 ctxt->op_bytes = 8;
3306 get(ctxt, &desc_ptr);
3307 if (ctxt->op_bytes == 2) {
3308 ctxt->op_bytes = 4;
3309 desc_ptr.address &= 0x00ffffff;
3310 }
3311 /* Disable writeback. */
3312 ctxt->dst.type = OP_NONE;
3313 return segmented_write(ctxt, ctxt->dst.addr.mem,
3314 &desc_ptr, 2 + ctxt->op_bytes);
3315}
3316
3317static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3318{
3319 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3320}
3321
3322static int em_sidt(struct x86_emulate_ctxt *ctxt)
3323{
3324 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3325}
3326
5b7f6a1e 3327static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3328{
26d05cc7
AK		 3329 struct desc_ptr desc_ptr;
3330 int rc;
3331
510425ff
AK		 3332 if (ctxt->mode == X86EMUL_MODE_PROT64)
3333 ctxt->op_bytes = 8;
9dac77fa 3334 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3335 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3336 ctxt->op_bytes);
26d05cc7
AK		 3337 if (rc != X86EMUL_CONTINUE)
3338 return rc;
9a9abf6b
NA		 3339 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3340 is_noncanonical_address(desc_ptr.address))
3341 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3342 if (lgdt)
3343 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3344 else
3345 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3346 /* Disable writeback. */
9dac77fa 3347 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3348 return X86EMUL_CONTINUE;
3349}
3350
5b7f6a1e
NA		 3351static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3352{
3353 return em_lgdt_lidt(ctxt, true);
3354}
3355
5ef39c71 3356static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3357{
26d05cc7
AK		 3358 int rc;
3359
5ef39c71
AK		 3360 rc = ctxt->ops->fix_hypercall(ctxt);
3361
26d05cc7 3362 /* Disable writeback. */
9dac77fa 3363 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3364 return rc;
3365}
3366
3367static int em_lidt(struct x86_emulate_ctxt *ctxt)
3368{
5b7f6a1e 3369 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3370}
3371
3372static int em_smsw(struct x86_emulate_ctxt *ctxt)
3373{
32e94d06
NA		 3374 if (ctxt->dst.type == OP_MEM)
3375 ctxt->dst.bytes = 2;
9dac77fa 3376 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3377 return X86EMUL_CONTINUE;
3378}
3379
3380static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3381{
26d05cc7 3382 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3383 | (ctxt->src.val & 0x0f));
3384 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3385 return X86EMUL_CONTINUE;
3386}
3387
d06e03ad
TY		 3388static int em_loop(struct x86_emulate_ctxt *ctxt)
3389{
234f3ce4
NA		 3390 int rc = X86EMUL_CONTINUE;
3391
dd856efa
AK		 3392 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3393 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3394 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3395 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3396
234f3ce4 3397 return rc;
d06e03ad
TY		 3398}
3399
3400static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3401{
234f3ce4
NA		 3402 int rc = X86EMUL_CONTINUE;
3403
dd856efa 3404 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3405 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3406
234f3ce4 3407 return rc;
d06e03ad
TY		 3408}
3409
d7841a4b
TY		 3410static int em_in(struct x86_emulate_ctxt *ctxt)
3411{
3412 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3413 &ctxt->dst.val))
3414 return X86EMUL_IO_NEEDED;
3415
3416 return X86EMUL_CONTINUE;
3417}
3418
3419static int em_out(struct x86_emulate_ctxt *ctxt)
3420{
3421 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3422 &ctxt->src.val, 1);
3423 /* Disable writeback. */
3424 ctxt->dst.type = OP_NONE;
3425 return X86EMUL_CONTINUE;
3426}
3427
f411e6cd
TY		 3428static int em_cli(struct x86_emulate_ctxt *ctxt)
3429{
3430 if (emulator_bad_iopl(ctxt))
3431 return emulate_gp(ctxt, 0);
3432
3433 ctxt->eflags &= ~X86_EFLAGS_IF;
3434 return X86EMUL_CONTINUE;
3435}
3436
3437static int em_sti(struct x86_emulate_ctxt *ctxt)
3438{
3439 if (emulator_bad_iopl(ctxt))
3440 return emulate_gp(ctxt, 0);
3441
3442 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3443 ctxt->eflags |= X86_EFLAGS_IF;
3444 return X86EMUL_CONTINUE;
3445}
3446
6d6eede4
AK		 3447static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3448{
3449 u32 eax, ebx, ecx, edx;
3450
dd856efa
AK		 3451 eax = reg_read(ctxt, VCPU_REGS_RAX);
3452 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3453 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3454 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3455 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3456 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3457 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3458 return X86EMUL_CONTINUE;
3459}
3460
98f73630
PB		 3461static int em_sahf(struct x86_emulate_ctxt *ctxt)
3462{
3463 u32 flags;
3464
3465 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3466 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3467
3468 ctxt->eflags &= ~0xffUL;
3469 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3470 return X86EMUL_CONTINUE;
3471}
3472
2dd7caa0
AK		 3473static int em_lahf(struct x86_emulate_ctxt *ctxt)
3474{
dd856efa
AK		 3475 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3476 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3477 return X86EMUL_CONTINUE;
3478}
3479
9299836e
AK		 3480static int em_bswap(struct x86_emulate_ctxt *ctxt)
3481{
3482 switch (ctxt->op_bytes) {
3483#ifdef CONFIG_X86_64
3484 case 8:
3485 asm("bswap %0" : "+r"(ctxt->dst.val));
3486 break;
3487#endif
3488 default:
3489 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3490 break;
3491 }
3492 return X86EMUL_CONTINUE;
3493}
3494
13e457e0
NA		 3495static int em_clflush(struct x86_emulate_ctxt *ctxt)
3496{
3497 /* emulating clflush regardless of cpuid */
3498 return X86EMUL_CONTINUE;
3499}
3500
cfec82cb
JR		 3501static bool valid_cr(int nr)
3502{
3503 switch (nr) {
3504 case 0:
3505 case 2 ... 4:
3506 case 8:
3507 return true;
3508 default:
3509 return false;
3510 }
3511}
3512
3513static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3514{
9dac77fa 3515 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3516 return emulate_ud(ctxt);
3517
3518 return X86EMUL_CONTINUE;
3519}
3520
3521static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3522{
9dac77fa
AK		 3523 u64 new_val = ctxt->src.val64;
3524 int cr = ctxt->modrm_reg;
c2ad2bb3 3525 u64 efer = 0;
cfec82cb
JR		 3526
3527 static u64 cr_reserved_bits[] = {
3528 0xffffffff00000000ULL,
3529 0, 0, 0, /* CR3 checked later */
3530 CR4_RESERVED_BITS,
3531 0, 0, 0,
3532 CR8_RESERVED_BITS,
3533 };
3534
3535 if (!valid_cr(cr))
3536 return emulate_ud(ctxt);
3537
3538 if (new_val & cr_reserved_bits[cr])
3539 return emulate_gp(ctxt, 0);
3540
3541 switch (cr) {
3542 case 0: {
c2ad2bb3 3543 u64 cr4;
cfec82cb
JR		 3544 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3545 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3546 return emulate_gp(ctxt, 0);
3547
717746e3
AK		 3548 cr4 = ctxt->ops->get_cr(ctxt, 4);
3549 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3550
3551 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3552 !(cr4 & X86_CR4_PAE))
3553 return emulate_gp(ctxt, 0);
3554
3555 break;
3556 }
3557 case 3: {
3558 u64 rsvd = 0;
3559
c2ad2bb3
AK		 3560 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3561 if (efer & EFER_LMA)
9d88fca7 3562 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3563
3564 if (new_val & rsvd)
3565 return emulate_gp(ctxt, 0);
3566
3567 break;
3568 }
3569 case 4: {
717746e3 3570 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3571
3572 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3573 return emulate_gp(ctxt, 0);
3574
3575 break;
3576 }
3577 }
3578
3579 return X86EMUL_CONTINUE;
3580}
3581
3b88e41a
JR		 3582static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3583{
3584 unsigned long dr7;
3585
717746e3 3586 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3587
3588 /* Check if DR7.Global_Enable is set */
3589 return dr7 & (1 << 13);
3590}
3591
3592static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3593{
9dac77fa 3594 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3595 u64 cr4;
3596
3597 if (dr > 7)
3598 return emulate_ud(ctxt);
3599
717746e3 3600 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3601 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3602 return emulate_ud(ctxt);
3603
6d2a0526
NA		 3604 if (check_dr7_gd(ctxt)) {
3605 ulong dr6;
3606
3607 ctxt->ops->get_dr(ctxt, 6, &dr6);
3608 dr6 &= ~15;
3609 dr6 |= DR6_BD | DR6_RTM;
3610 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3611 return emulate_db(ctxt);
6d2a0526 3612 }
3b88e41a
JR		 3613
3614 return X86EMUL_CONTINUE;
3615}
3616
3617static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3618{
9dac77fa
AK		 3619 u64 new_val = ctxt->src.val64;
3620 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3621
3622 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3623 return emulate_gp(ctxt, 0);
3624
3625 return check_dr_read(ctxt);
3626}
3627
01de8b09
JR		 3628static int check_svme(struct x86_emulate_ctxt *ctxt)
3629{
3630 u64 efer;
3631
717746e3 3632 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3633
3634 if (!(efer & EFER_SVME))
3635 return emulate_ud(ctxt);
3636
3637 return X86EMUL_CONTINUE;
3638}
3639
3640static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3641{
dd856efa 3642 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3643
3644 /* Valid physical address? */
d4224449 3645 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3646 return emulate_gp(ctxt, 0);
3647
3648 return check_svme(ctxt);
3649}
3650
d7eb8203
JR		 3651static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3652{
717746e3 3653 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3654
717746e3 3655 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3656 return emulate_ud(ctxt);
3657
3658 return X86EMUL_CONTINUE;
3659}
3660
8061252e
JR		 3661static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3662{
717746e3 3663 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3664 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3665
717746e3 3666 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3667 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3668 return emulate_gp(ctxt, 0);
3669
3670 return X86EMUL_CONTINUE;
3671}
3672
f6511935
JR		 3673static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3674{
9dac77fa
AK		 3675 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3676 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3677 return emulate_gp(ctxt, 0);
3678
3679 return X86EMUL_CONTINUE;
3680}
3681
3682static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3683{
9dac77fa
AK		 3684 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3685 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3686 return emulate_gp(ctxt, 0);
3687
3688 return X86EMUL_CONTINUE;
3689}
3690
73fba5f4 3691#define D(_y) { .flags = (_y) }
d40a6898
PB		 3692#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3693#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3694 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3695#define N D(NotImpl)
01de8b09 3696#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3697#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3698#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3699#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3700#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3701#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3702#define II(_f, _e, _i) \
d40a6898 3703 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3704#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3705 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3706 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3707#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3708
8d8f4e9f 3709#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3710#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3711#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3712#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3713#define I2bvIP(_f, _e, _i, _p) \
3714 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3715
fb864fbc
AK		 3716#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3717 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3718 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3719
0f54a321
NA		 3720static const struct opcode group7_rm0[] = {
3721 N,
3722 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3723 N, N, N, N, N, N,
3724};
3725
fd0a0d82 3726static const struct opcode group7_rm1[] = {
1c2545be
TY		 3727 DI(SrcNone | Priv, monitor),
3728 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3729 N, N, N, N, N, N,
3730};
3731
fd0a0d82 3732static const struct opcode group7_rm3[] = {
1c2545be 3733 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3734 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3735 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3736 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3737 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3738 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3739 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3740 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3741};
6230f7fc 3742
fd0a0d82 3743static const struct opcode group7_rm7[] = {
d7eb8203 3744 N,
1c2545be 3745 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3746 N, N, N, N, N, N,
3747};
d67fc27a 3748
fd0a0d82 3749static const struct opcode group1[] = {
fb864fbc
AK		 3750 F(Lock, em_add),
3751 F(Lock | PageTable, em_or),
3752 F(Lock, em_adc),
3753 F(Lock, em_sbb),
3754 F(Lock | PageTable, em_and),
3755 F(Lock, em_sub),
3756 F(Lock, em_xor),
3757 F(NoWrite, em_cmp),
73fba5f4
AK		 3758};
3759
fd0a0d82 3760static const struct opcode group1A[] = {
1c2545be 3761 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3762};
3763
007a3b54
AK		 3764static const struct opcode group2[] = {
3765 F(DstMem | ModRM, em_rol),
3766 F(DstMem | ModRM, em_ror),
3767 F(DstMem | ModRM, em_rcl),
3768 F(DstMem | ModRM, em_rcr),
3769 F(DstMem | ModRM, em_shl),
3770 F(DstMem | ModRM, em_shr),
3771 F(DstMem | ModRM, em_shl),
3772 F(DstMem | ModRM, em_sar),
3773};
3774
fd0a0d82 3775static const struct opcode group3[] = {
fb864fbc
AK		 3776 F(DstMem | SrcImm | NoWrite, em_test),
3777 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3778 F(DstMem | SrcNone | Lock, em_not),
3779 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3780 F(DstXacc | Src2Mem, em_mul_ex),
3781 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3782 F(DstXacc | Src2Mem, em_div_ex),
3783 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3784};
3785
fd0a0d82 3786static const struct opcode group4[] = {
95413dc4
AK		 3787 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3788 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3789 N, N, N, N, N, N,
3790};
3791
fd0a0d82 3792static const struct opcode group5[] = {
95413dc4
AK		 3793 F(DstMem | SrcNone | Lock, em_inc),
3794 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3795 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3796 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3797 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3798 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3799 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3800};
3801
fd0a0d82 3802static const struct opcode group6[] = {
1c2545be
TY		 3803 DI(Prot, sldt),
3804 DI(Prot, str),
a14e579f 3805 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3806 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3807 N, N, N, N,
3808};
3809
fd0a0d82 3810static const struct group_dual group7 = { {
606b1c3e
NA		 3811 II(Mov | DstMem, em_sgdt, sgdt),
3812 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3813 II(SrcMem | Priv, em_lgdt, lgdt),
3814 II(SrcMem | Priv, em_lidt, lidt),
3815 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3816 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3817 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3818}, {
0f54a321 3819 EXT(0, group7_rm0),
5ef39c71 3820 EXT(0, group7_rm1),
01de8b09 3821 N, EXT(0, group7_rm3),
1c2545be
TY		 3822 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3823 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3824 EXT(0, group7_rm7),
73fba5f4
AK		 3825} };
3826
fd0a0d82 3827static const struct opcode group8[] = {
73fba5f4 3828 N, N, N, N,
11c363ba
AK		 3829 F(DstMem | SrcImmByte | NoWrite, em_bt),
3830 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3831 F(DstMem | SrcImmByte | Lock, em_btr),
3832 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3833};
3834
fd0a0d82 3835static const struct group_dual group9 = { {
1c2545be 3836 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3837}, {
3838 N, N, N, N, N, N, N, N,
3839} };
3840
fd0a0d82 3841static const struct opcode group11[] = {
1c2545be 3842 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3843 X7(D(Undefined)),
a4d4a7c1
AK		 3844};
3845
13e457e0 3846static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3847 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3848};
3849
3850static const struct group_dual group15 = { {
3851 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3852}, {
3853 N, N, N, N, N, N, N, N,
3854} };
3855
fd0a0d82 3856static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3857 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3858};
3859
d5b77069
PB		 3860static const struct gprefix pfx_0f_2b = {
3861 I(0, em_mov), I(0, em_mov), N, N,
3e114eb4
AK		 3862};
3863
27ce8258 3864static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3865 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3866};
3867
0a37027e
AW		 3868static const struct gprefix pfx_0f_e7 = {
3869 N, I(Sse, em_mov), N, N,
3870};
3871
045a282c
GN		 3872static const struct escape escape_d9 = { {
3873 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3874}, {
3875 /* 0xC0 - 0xC7 */
3876 N, N, N, N, N, N, N, N,
3877 /* 0xC8 - 0xCF */
3878 N, N, N, N, N, N, N, N,
3879 /* 0xD0 - 0xC7 */
3880 N, N, N, N, N, N, N, N,
3881 /* 0xD8 - 0xDF */
3882 N, N, N, N, N, N, N, N,
3883 /* 0xE0 - 0xE7 */
3884 N, N, N, N, N, N, N, N,
3885 /* 0xE8 - 0xEF */
3886 N, N, N, N, N, N, N, N,
3887 /* 0xF0 - 0xF7 */
3888 N, N, N, N, N, N, N, N,
3889 /* 0xF8 - 0xFF */
3890 N, N, N, N, N, N, N, N,
3891} };
3892
3893static const struct escape escape_db = { {
3894 N, N, N, N, N, N, N, N,
3895}, {
3896 /* 0xC0 - 0xC7 */
3897 N, N, N, N, N, N, N, N,
3898 /* 0xC8 - 0xCF */
3899 N, N, N, N, N, N, N, N,
3900 /* 0xD0 - 0xC7 */
3901 N, N, N, N, N, N, N, N,
3902 /* 0xD8 - 0xDF */
3903 N, N, N, N, N, N, N, N,
3904 /* 0xE0 - 0xE7 */
3905 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3906 /* 0xE8 - 0xEF */
3907 N, N, N, N, N, N, N, N,
3908 /* 0xF0 - 0xF7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xF8 - 0xFF */
3911 N, N, N, N, N, N, N, N,
3912} };
3913
3914static const struct escape escape_dd = { {
3915 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3916}, {
3917 /* 0xC0 - 0xC7 */
3918 N, N, N, N, N, N, N, N,
3919 /* 0xC8 - 0xCF */
3920 N, N, N, N, N, N, N, N,
3921 /* 0xD0 - 0xC7 */
3922 N, N, N, N, N, N, N, N,
3923 /* 0xD8 - 0xDF */
3924 N, N, N, N, N, N, N, N,
3925 /* 0xE0 - 0xE7 */
3926 N, N, N, N, N, N, N, N,
3927 /* 0xE8 - 0xEF */
3928 N, N, N, N, N, N, N, N,
3929 /* 0xF0 - 0xF7 */
3930 N, N, N, N, N, N, N, N,
3931 /* 0xF8 - 0xFF */
3932 N, N, N, N, N, N, N, N,
3933} };
3934
fd0a0d82 3935static const struct opcode opcode_table[256] = {
73fba5f4 3936 /* 0x00 - 0x07 */
fb864fbc 3937 F6ALU(Lock, em_add),
1cd196ea
AK		 3938 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3939 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3940 /* 0x08 - 0x0F */
fb864fbc 3941 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3942 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3943 N,
73fba5f4 3944 /* 0x10 - 0x17 */
fb864fbc 3945 F6ALU(Lock, em_adc),
1cd196ea
AK		 3946 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3947 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3948 /* 0x18 - 0x1F */
fb864fbc 3949 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3950 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3951 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3952 /* 0x20 - 0x27 */
fb864fbc 3953 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3954 /* 0x28 - 0x2F */
fb864fbc 3955 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3956 /* 0x30 - 0x37 */
fb864fbc 3957 F6ALU(Lock, em_xor), N, N,
73fba5f4 3958 /* 0x38 - 0x3F */
fb864fbc 3959 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3960 /* 0x40 - 0x4F */
95413dc4 3961 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3962 /* 0x50 - 0x57 */
63540382 3963 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3964 /* 0x58 - 0x5F */
c54fe504 3965 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3966 /* 0x60 - 0x67 */
b96a7fad
TY		 3967 I(ImplicitOps | Stack | No64, em_pusha),
3968 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3969 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3970 N, N, N, N,
3971 /* 0x68 - 0x6F */
d46164db
AK		 3972 I(SrcImm | Mov | Stack, em_push),
3973 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3974 I(SrcImmByte | Mov | Stack, em_push),
3975 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3976 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3977 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3978 /* 0x70 - 0x7F */
58b7075d 3979 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3980 /* 0x80 - 0x87 */
1c2545be
TY		 3981 G(ByteOp | DstMem | SrcImm, group1),
3982 G(DstMem | SrcImm, group1),
3983 G(ByteOp | DstMem | SrcImm | No64, group1),
3984 G(DstMem | SrcImmByte, group1),
fb864fbc 3985 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3986 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3987 /* 0x88 - 0x8F */
d5ae7ce8 3988 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3989 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3990 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3991 D(ModRM | SrcMem | NoAccess | DstReg),
3992 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3993 G(0, group1A),
73fba5f4 3994 /* 0x90 - 0x97 */
bf608f88 3995 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3996 /* 0x98 - 0x9F */
61429142 3997 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3998 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3999 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4000 II(ImplicitOps | Stack, em_popf, popf),
4001 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4002 /* 0xA0 - 0xA7 */
b9eac5f4 4003 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4004 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4005 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4006 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4007 /* 0xA8 - 0xAF */
fb864fbc 4008 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4009 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4010 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4011 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4012 /* 0xB0 - 0xB7 */
b9eac5f4 4013 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4014 /* 0xB8 - 0xBF */
5e2c6883 4015 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4016 /* 0xC0 - 0xC7 */
007a3b54 4017 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4018 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4019 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4020 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4021 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4022 G(ByteOp, group11), G(0, group11),
73fba5f4 4023 /* 0xC8 - 0xCF */
612e89f0 4024 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4025 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4026 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4027 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4028 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4029 /* 0xD0 - 0xD7 */
007a3b54
AK		 4030 G(Src2One | ByteOp, group2), G(Src2One, group2),
4031 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4032 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4033 I(DstAcc | SrcImmUByte | No64, em_aad),
4034 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4035 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4036 /* 0xD8 - 0xDF */
045a282c 4037 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4038 /* 0xE0 - 0xE7 */
58b7075d
NA		 4039 X3(I(SrcImmByte | NearBranch, em_loop)),
4040 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4041 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4042 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4043 /* 0xE8 - 0xEF */
58b7075d
NA		 4044 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4045 I(SrcImmFAddr | No64, em_jmp_far),
4046 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4047 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4048 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4049 /* 0xF0 - 0xF7 */
bf608f88 4050 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4051 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4052 G(ByteOp, group3), G(0, group3),
73fba5f4 4053 /* 0xF8 - 0xFF */
f411e6cd
TY		 4054 D(ImplicitOps), D(ImplicitOps),
4055 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4056 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4057};
4058
fd0a0d82 4059static const struct opcode twobyte_table[256] = {
73fba5f4 4060 /* 0x00 - 0x0F */
dee6bb70 4061 G(0, group6), GD(0, &group7), N, N,
b51e974f 4062 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4063 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4064 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4065 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4066 /* 0x10 - 0x1F */
103f98ea 4067 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4068 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4069 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4070 /* 0x20 - 0x2F */
9b88ae99
NA		 4071 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4072 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4073 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4074 check_cr_write),
4075 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4076 check_dr_write),
73fba5f4 4077 N, N, N, N,
27ce8258
IM		 4078 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4079 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4080 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4081 N, N, N, N,
73fba5f4 4082 /* 0x30 - 0x3F */
e1e210b0 4083 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4084 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4085 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4086 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4087 I(ImplicitOps | EmulateOnUD, em_sysenter),
4088 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4089 N, N,
73fba5f4
AK		 4090 N, N, N, N, N, N, N, N,
4091 /* 0x40 - 0x4F */
140bad89 4092 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4093 /* 0x50 - 0x5F */
4094 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4095 /* 0x60 - 0x6F */
aa97bb48
AK		 4096 N, N, N, N,
4097 N, N, N, N,
4098 N, N, N, N,
4099 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4100 /* 0x70 - 0x7F */
aa97bb48
AK		 4101 N, N, N, N,
4102 N, N, N, N,
4103 N, N, N, N,
4104 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4105 /* 0x80 - 0x8F */
58b7075d 4106 X16(D(SrcImm | NearBranch)),
73fba5f4 4107 /* 0x90 - 0x9F */
ee45b58e 4108 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4109 /* 0xA0 - 0xA7 */
1cd196ea 4110 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4111 II(ImplicitOps, em_cpuid, cpuid),
4112 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4113 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4114 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4115 /* 0xA8 - 0xAF */
1cd196ea 4116 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4117 DI(ImplicitOps, rsm),
11c363ba 4118 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4119 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4120 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4121 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4122 /* 0xB0 - 0xB7 */
e940b5c2 4123 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4124 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4125 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4126 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4127 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4128 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4129 /* 0xB8 - 0xBF */
4130 N, N,
ce7faab2 4131 G(BitOp, group8),
11c363ba
AK		 4132 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4133 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4134 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4135 /* 0xC0 - 0xC7 */
e47a5f5f 4136 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 4137 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4138 N, N, N, GD(0, &group9),
9299836e
AK		 4139 /* 0xC8 - 0xCF */
4140 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4141 /* 0xD0 - 0xDF */
4142 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4143 /* 0xE0 - 0xEF */
0a37027e
AW		 4144 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4145 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4146 /* 0xF0 - 0xFF */
4147 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4148};
4149
0bc5eedb 4150static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 4151 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4152};
4153
4154static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 4155 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 4156};
4157
4158/*
4159 * Insns below are selected by the prefix which indexed by the third opcode
4160 * byte.
4161 */
4162static const struct opcode opcode_map_0f_38[256] = {
4163 /* 0x00 - 0x7f */
4164 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4165 /* 0x80 - 0xef */
4166 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4167 /* 0xf0 - 0xf1 */
4168 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
4169 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
4170 /* 0xf2 - 0xff */
4171 N, N, X4(N), X8(N)
0bc5eedb
BP		 4172};
4173
73fba5f4
AK		 4174#undef D
4175#undef N
4176#undef G
4177#undef GD
4178#undef I
aa97bb48 4179#undef GP
01de8b09 4180#undef EXT
73fba5f4 4181
8d8f4e9f 4182#undef D2bv
f6511935 4183#undef D2bvIP
8d8f4e9f 4184#undef I2bv
d7841a4b 4185#undef I2bvIP
d67fc27a 4186#undef I6ALU
8d8f4e9f 4187
9dac77fa 4188static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4189{
4190 unsigned size;
4191
9dac77fa 4192 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4193 if (size == 8)
4194 size = 4;
4195 return size;
4196}
4197
4198static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4199 unsigned size, bool sign_extension)
4200{
39f21ee5
AK		 4201 int rc = X86EMUL_CONTINUE;
4202
4203 op->type = OP_IMM;
4204 op->bytes = size;
9dac77fa 4205 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4206 /* NB. Immediates are sign-extended as necessary. */
4207 switch (op->bytes) {
4208 case 1:
e85a1085 4209 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4210 break;
4211 case 2:
e85a1085 4212 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4213 break;
4214 case 4:
e85a1085 4215 op->val = insn_fetch(s32, ctxt);
39f21ee5 4216 break;
5e2c6883
NA		 4217 case 8:
4218 op->val = insn_fetch(s64, ctxt);
4219 break;
39f21ee5
AK		 4220 }
4221 if (!sign_extension) {
4222 switch (op->bytes) {
4223 case 1:
4224 op->val &= 0xff;
4225 break;
4226 case 2:
4227 op->val &= 0xffff;
4228 break;
4229 case 4:
4230 op->val &= 0xffffffff;
4231 break;
4232 }
4233 }
4234done:
4235 return rc;
4236}
4237
a9945549
AK		 4238static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4239 unsigned d)
4240{
4241 int rc = X86EMUL_CONTINUE;
4242
4243 switch (d) {
4244 case OpReg:
2adb5ad9 4245 decode_register_operand(ctxt, op);
a9945549
AK		 4246 break;
4247 case OpImmUByte:
608aabe3 4248 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4249 break;
4250 case OpMem:
41ddf978 4251 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4252 mem_common:
4253 *op = ctxt->memop;
4254 ctxt->memopp = op;
96888977 4255 if (ctxt->d & BitOp)
a9945549
AK		 4256 fetch_bit_operand(ctxt);
4257 op->orig_val = op->val;
4258 break;
41ddf978 4259 case OpMem64:
aaa05f24 4260 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4261 goto mem_common;
a9945549
AK		 4262 case OpAcc:
4263 op->type = OP_REG;
4264 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4265 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4266 fetch_register_operand(op);
4267 op->orig_val = op->val;
4268 break;
820207c8
AK		 4269 case OpAccLo:
4270 op->type = OP_REG;
4271 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4272 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4273 fetch_register_operand(op);
4274 op->orig_val = op->val;
4275 break;
4276 case OpAccHi:
4277 if (ctxt->d & ByteOp) {
4278 op->type = OP_NONE;
4279 break;
4280 }
4281 op->type = OP_REG;
4282 op->bytes = ctxt->op_bytes;
4283 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4284 fetch_register_operand(op);
4285 op->orig_val = op->val;
4286 break;
a9945549
AK		 4287 case OpDI:
4288 op->type = OP_MEM;
4289 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4290 op->addr.mem.ea =
dd856efa 4291 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4292 op->addr.mem.seg = VCPU_SREG_ES;
4293 op->val = 0;
b3356bf0 4294 op->count = 1;
a9945549
AK		 4295 break;
4296 case OpDX:
4297 op->type = OP_REG;
4298 op->bytes = 2;
dd856efa 4299 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4300 fetch_register_operand(op);
4301 break;
4dd6a57d
AK		 4302 case OpCL:
4303 op->bytes = 1;
dd856efa 4304 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4305 break;
4306 case OpImmByte:
4307 rc = decode_imm(ctxt, op, 1, true);
4308 break;
4309 case OpOne:
4310 op->bytes = 1;
4311 op->val = 1;
4312 break;
4313 case OpImm:
4314 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4315 break;
5e2c6883
NA		 4316 case OpImm64:
4317 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4318 break;
28867cee
AK		 4319 case OpMem8:
4320 ctxt->memop.bytes = 1;
660696d1 4321 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4322 ctxt->memop.addr.reg = decode_register(ctxt,
4323 ctxt->modrm_rm, true);
660696d1
GN		 4324 fetch_register_operand(&ctxt->memop);
4325 }
28867cee 4326 goto mem_common;
0fe59128
AK		 4327 case OpMem16:
4328 ctxt->memop.bytes = 2;
4329 goto mem_common;
4330 case OpMem32:
4331 ctxt->memop.bytes = 4;
4332 goto mem_common;
4333 case OpImmU16:
4334 rc = decode_imm(ctxt, op, 2, false);
4335 break;
4336 case OpImmU:
4337 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4338 break;
4339 case OpSI:
4340 op->type = OP_MEM;
4341 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4342 op->addr.mem.ea =
dd856efa 4343 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
573e80fe 4344 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4345 op->val = 0;
b3356bf0 4346 op->count = 1;
0fe59128 4347 break;
7fa57952
PB		 4348 case OpXLat:
4349 op->type = OP_MEM;
4350 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4351 op->addr.mem.ea =
4352 register_address(ctxt,
4353 reg_read(ctxt, VCPU_REGS_RBX) +
4354 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4355 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4356 op->val = 0;
4357 break;
0fe59128
AK		 4358 case OpImmFAddr:
4359 op->type = OP_IMM;
4360 op->addr.mem.ea = ctxt->_eip;
4361 op->bytes = ctxt->op_bytes + 2;
4362 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4363 break;
4364 case OpMemFAddr:
4365 ctxt->memop.bytes = ctxt->op_bytes + 2;
4366 goto mem_common;
c191a7a0
AK		 4367 case OpES:
4368 op->val = VCPU_SREG_ES;
4369 break;
4370 case OpCS:
4371 op->val = VCPU_SREG_CS;
4372 break;
4373 case OpSS:
4374 op->val = VCPU_SREG_SS;
4375 break;
4376 case OpDS:
4377 op->val = VCPU_SREG_DS;
4378 break;
4379 case OpFS:
4380 op->val = VCPU_SREG_FS;
4381 break;
4382 case OpGS:
4383 op->val = VCPU_SREG_GS;
4384 break;
a9945549
AK		 4385 case OpImplicit:
4386 /* Special instructions do their own operand decoding. */
4387 default:
4388 op->type = OP_NONE; /* Disable writeback. */
4389 break;
4390 }
4391
4392done:
4393 return rc;
4394}
4395
ef5d75cc 4396int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4397{
dde7e6d1
AK		 4398 int rc = X86EMUL_CONTINUE;
4399 int mode = ctxt->mode;
46561646 4400 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4401 bool op_prefix = false;
573e80fe 4402 bool has_seg_override = false;
46561646 4403 struct opcode opcode;
dde7e6d1 4404
f09ed83e
AK		 4405 ctxt->memop.type = OP_NONE;
4406 ctxt->memopp = NULL;
9dac77fa 4407 ctxt->_eip = ctxt->eip;
17052f16
PB		 4408 ctxt->fetch.ptr = ctxt->fetch.data;
4409 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4410 ctxt->opcode_len = 1;
dc25e89e 4411 if (insn_len > 0)
9dac77fa 4412 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4413 else {
9506d57d 4414 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4415 if (rc != X86EMUL_CONTINUE)
4416 return rc;
4417 }
dde7e6d1
AK		 4418
4419 switch (mode) {
4420 case X86EMUL_MODE_REAL:
4421 case X86EMUL_MODE_VM86:
4422 case X86EMUL_MODE_PROT16:
4423 def_op_bytes = def_ad_bytes = 2;
4424 break;
4425 case X86EMUL_MODE_PROT32:
4426 def_op_bytes = def_ad_bytes = 4;
4427 break;
4428#ifdef CONFIG_X86_64
4429 case X86EMUL_MODE_PROT64:
4430 def_op_bytes = 4;
4431 def_ad_bytes = 8;
4432 break;
4433#endif
4434 default:
1d2887e2 4435 return EMULATION_FAILED;
dde7e6d1
AK		 4436 }
4437
9dac77fa
AK		 4438 ctxt->op_bytes = def_op_bytes;
4439 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4440
4441 /* Legacy prefixes. */
4442 for (;;) {
e85a1085 4443 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4444 case 0x66: /* operand-size override */
0d7cdee8 4445 op_prefix = true;
dde7e6d1 4446 /* switch between 2/4 bytes */
9dac77fa 4447 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4448 break;
4449 case 0x67: /* address-size override */
4450 if (mode == X86EMUL_MODE_PROT64)
4451 /* switch between 4/8 bytes */
9dac77fa 4452 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4453 else
4454 /* switch between 2/4 bytes */
9dac77fa 4455 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4456 break;
4457 case 0x26: /* ES override */
4458 case 0x2e: /* CS override */
4459 case 0x36: /* SS override */
4460 case 0x3e: /* DS override */
573e80fe
BD		 4461 has_seg_override = true;
4462 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4463 break;
4464 case 0x64: /* FS override */
4465 case 0x65: /* GS override */
573e80fe
BD		 4466 has_seg_override = true;
4467 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4468 break;
4469 case 0x40 ... 0x4f: /* REX */
4470 if (mode != X86EMUL_MODE_PROT64)
4471 goto done_prefixes;
9dac77fa 4472 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4473 continue;
4474 case 0xf0: /* LOCK */
9dac77fa 4475 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4476 break;
4477 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4478 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4479 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4480 break;
4481 default:
4482 goto done_prefixes;
4483 }
4484
4485 /* Any legacy prefix after a REX prefix nullifies its effect. */
4486
9dac77fa 4487 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4488 }
4489
4490done_prefixes:
4491
4492 /* REX prefix. */
9dac77fa
AK		 4493 if (ctxt->rex_prefix & 8)
4494 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4495
4496 /* Opcode byte(s). */
9dac77fa 4497 opcode = opcode_table[ctxt->b];
d3ad6243 4498 /* Two-byte opcode? */
9dac77fa 4499 if (ctxt->b == 0x0f) {
1ce19dc1 4500 ctxt->opcode_len = 2;
e85a1085 4501 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4502 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4503
4504 /* 0F_38 opcode map */
4505 if (ctxt->b == 0x38) {
4506 ctxt->opcode_len = 3;
4507 ctxt->b = insn_fetch(u8, ctxt);
4508 opcode = opcode_map_0f_38[ctxt->b];
4509 }
dde7e6d1 4510 }
9dac77fa 4511 ctxt->d = opcode.flags;
dde7e6d1 4512
9f4260e7
TY		 4513 if (ctxt->d & ModRM)
4514 ctxt->modrm = insn_fetch(u8, ctxt);
4515
7fe864dc
NA		 4516 /* vex-prefix instructions are not implemented */
4517 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4518 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4519 ctxt->d = NotImpl;
4520 }
4521
9dac77fa
AK		 4522 while (ctxt->d & GroupMask) {
4523 switch (ctxt->d & GroupMask) {
46561646 4524 case Group:
9dac77fa 4525 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4526 opcode = opcode.u.group[goffset];
4527 break;
4528 case GroupDual:
9dac77fa
AK		 4529 goffset = (ctxt->modrm >> 3) & 7;
4530 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4531 opcode = opcode.u.gdual->mod3[goffset];
4532 else
4533 opcode = opcode.u.gdual->mod012[goffset];
4534 break;
4535 case RMExt:
9dac77fa 4536 goffset = ctxt->modrm & 7;
01de8b09 4537 opcode = opcode.u.group[goffset];
46561646
AK		 4538 break;
4539 case Prefix:
9dac77fa 4540 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4541 return EMULATION_FAILED;
9dac77fa 4542 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4543 switch (simd_prefix) {
4544 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4545 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4546 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4547 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4548 }
4549 break;
045a282c
GN		 4550 case Escape:
4551 if (ctxt->modrm > 0xbf)
4552 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4553 else
4554 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4555 break;
46561646 4556 default:
1d2887e2 4557 return EMULATION_FAILED;
0d7cdee8 4558 }
46561646 4559
b1ea50b2 4560 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4561 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4562 }
4563
e24186e0
PB		 4564 /* Unrecognised? */
4565 if (ctxt->d == 0)
4566 return EMULATION_FAILED;
4567
9dac77fa 4568 ctxt->execute = opcode.u.execute;
dde7e6d1 4569
3a6095a0
NA		 4570 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4571 return EMULATION_FAILED;
4572
d40a6898 4573 if (unlikely(ctxt->d &
58b7075d 4574 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch))) {
d40a6898
PB		 4575 /*
4576 * These are copied unconditionally here, and checked unconditionally
4577 * in x86_emulate_insn.
4578 */
4579 ctxt->check_perm = opcode.check_perm;
4580 ctxt->intercept = opcode.intercept;
dde7e6d1 4581
d40a6898
PB		 4582 if (ctxt->d & NotImpl)
4583 return EMULATION_FAILED;
d867162c 4584
58b7075d
NA		 4585 if (mode == X86EMUL_MODE_PROT64) {
4586 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4587 ctxt->op_bytes = 8;
4588 else if (ctxt->d & NearBranch)
4589 ctxt->op_bytes = 8;
4590 }
7f9b4b75 4591
d40a6898
PB		 4592 if (ctxt->d & Op3264) {
4593 if (mode == X86EMUL_MODE_PROT64)
4594 ctxt->op_bytes = 8;
4595 else
4596 ctxt->op_bytes = 4;
4597 }
4598
4599 if (ctxt->d & Sse)
4600 ctxt->op_bytes = 16;
4601 else if (ctxt->d & Mmx)
4602 ctxt->op_bytes = 8;
4603 }
1253791d 4604
dde7e6d1 4605 /* ModRM and SIB bytes. */
9dac77fa 4606 if (ctxt->d & ModRM) {
f09ed83e 4607 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4608 if (!has_seg_override) {
4609 has_seg_override = true;
4610 ctxt->seg_override = ctxt->modrm_seg;
4611 }
9dac77fa 4612 } else if (ctxt->d & MemAbs)
f09ed83e 4613 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4614 if (rc != X86EMUL_CONTINUE)
4615 goto done;
4616
573e80fe
BD		 4617 if (!has_seg_override)
4618 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4619
573e80fe 4620 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4621
dde7e6d1
AK		 4622 /*
4623 * Decode and fetch the source operand: register, memory
4624 * or immediate.
4625 */
0fe59128 4626 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4627 if (rc != X86EMUL_CONTINUE)
4628 goto done;
4629
dde7e6d1
AK		 4630 /*
4631 * Decode and fetch the second source operand: register, memory
4632 * or immediate.
4633 */
4dd6a57d 4634 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4635 if (rc != X86EMUL_CONTINUE)
4636 goto done;
4637
dde7e6d1 4638 /* Decode and fetch the destination operand: register or memory. */
a9945549 4639 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4640
41061cdb 4641 if (ctxt->rip_relative)
f09ed83e 4642 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4643
a430c916 4644done:
1d2887e2 4645 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4646}
4647
1cb3f3ae
XG		 4648bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4649{
4650 return ctxt->d & PageTable;
4651}
4652
3e2f65d5
GN		 4653static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4654{
3e2f65d5
GN		 4655 /* The second termination condition only applies for REPE
4656 * and REPNE. Test if the repeat string operation prefix is
4657 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4658 * corresponding termination condition according to:
4659 * - if REPE/REPZ and ZF = 0 then done
4660 * - if REPNE/REPNZ and ZF = 1 then done
4661 */
9dac77fa
AK		 4662 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4663 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4664 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4665 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4666 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4667 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4668 return true;
4669
4670 return false;
4671}
4672
cbe2c9d3
AK		 4673static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4674{
4675 bool fault = false;
4676
4677 ctxt->ops->get_fpu(ctxt);
4678 asm volatile("1: fwait \n\t"
4679 "2: \n\t"
4680 ".pushsection .fixup,\"ax\" \n\t"
4681 "3: \n\t"
4682 "movb $1, %[fault] \n\t"
4683 "jmp 2b \n\t"
4684 ".popsection \n\t"
4685 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4686 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4687 ctxt->ops->put_fpu(ctxt);
4688
4689 if (unlikely(fault))
4690 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4691
4692 return X86EMUL_CONTINUE;
4693}
4694
4695static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4696 struct operand *op)
4697{
4698 if (op->type == OP_MM)
4699 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4700}
4701
e28bbd44
AK		 4702static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4703{
4704 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4705 if (!(ctxt->d & ByteOp))
4706 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4707 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4708 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4709 [fastop]"+S"(fop)
4710 : "c"(ctxt->src2.val));
e28bbd44 4711 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4712 if (!fop) /* exception is returned in fop variable */
4713 return emulate_de(ctxt);
e28bbd44
AK		 4714 return X86EMUL_CONTINUE;
4715}
dd856efa 4716
1498507a
BD		 4717void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4718{
573e80fe
BD		 4719 memset(&ctxt->rip_relative, 0,
4720 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4721
1498507a
BD		 4722 ctxt->io_read.pos = 0;
4723 ctxt->io_read.end = 0;
1498507a
BD		 4724 ctxt->mem_read.end = 0;
4725}
4726
7b105ca2 4727int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4728{
0225fb50 4729 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4730 int rc = X86EMUL_CONTINUE;
9dac77fa 4731 int saved_dst_type = ctxt->dst.type;
8b4caf66 4732
9dac77fa 4733 ctxt->mem_read.pos = 0;
310b5d30 4734
e24186e0
PB		 4735 /* LOCK prefix is allowed only with some instructions */
4736 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4737 rc = emulate_ud(ctxt);
1161624f
GN		 4738 goto done;
4739 }
4740
e24186e0 4741 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4742 rc = emulate_ud(ctxt);
d380a5e4
GN		 4743 goto done;
4744 }
4745
d40a6898
PB		 4746 if (unlikely(ctxt->d &
4747 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4748 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4749 (ctxt->d & Undefined)) {
4750 rc = emulate_ud(ctxt);
4751 goto done;
4752 }
1253791d 4753
d40a6898
PB		 4754 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4755 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4756 rc = emulate_ud(ctxt);
cbe2c9d3 4757 goto done;
d40a6898 4758 }
cbe2c9d3 4759
d40a6898
PB		 4760 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4761 rc = emulate_nm(ctxt);
c4f035c6 4762 goto done;
d40a6898 4763 }
c4f035c6 4764
d40a6898
PB		 4765 if (ctxt->d & Mmx) {
4766 rc = flush_pending_x87_faults(ctxt);
4767 if (rc != X86EMUL_CONTINUE)
4768 goto done;
4769 /*
4770 * Now that we know the fpu is exception safe, we can fetch
4771 * operands from it.
4772 */
4773 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4774 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4775 if (!(ctxt->d & Mov))
4776 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4777 }
e92805ac 4778
685bbf4a 4779 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4780 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4781 X86_ICPT_PRE_EXCEPT);
4782 if (rc != X86EMUL_CONTINUE)
4783 goto done;
4784 }
8ea7d6ae 4785
d40a6898
PB		 4786 /* Privileged instruction can be executed only in CPL=0 */
4787 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4788 if (ctxt->d & PrivUD)
4789 rc = emulate_ud(ctxt);
4790 else
4791 rc = emulate_gp(ctxt, 0);
d09beabd 4792 goto done;
d40a6898 4793 }
d09beabd 4794
d40a6898
PB		 4795 /* Instruction can only be executed in protected mode */
4796 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4797 rc = emulate_ud(ctxt);
c4f035c6 4798 goto done;
d40a6898 4799 }
c4f035c6 4800
d40a6898 4801 /* Do instruction specific permission checks */
685bbf4a 4802 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4803 rc = ctxt->check_perm(ctxt);
4804 if (rc != X86EMUL_CONTINUE)
4805 goto done;
4806 }
4807
685bbf4a 4808 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4809 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4810 X86_ICPT_POST_EXCEPT);
4811 if (rc != X86EMUL_CONTINUE)
4812 goto done;
4813 }
4814
4815 if (ctxt->rep_prefix && (ctxt->d & String)) {
4816 /* All REP prefixes have the same first termination condition */
4817 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4818 ctxt->eip = ctxt->_eip;
4467c3f1 4819 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4820 goto done;
4821 }
b9fa9d6b 4822 }
b9fa9d6b
AK		 4823 }
4824
9dac77fa
AK		 4825 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4826 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4827 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4828 if (rc != X86EMUL_CONTINUE)
8b4caf66 4829 goto done;
9dac77fa 4830 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4831 }
4832
9dac77fa
AK		 4833 if (ctxt->src2.type == OP_MEM) {
4834 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4835 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4836 if (rc != X86EMUL_CONTINUE)
4837 goto done;
4838 }
4839
9dac77fa 4840 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4841 goto special_insn;
4842
4843
9dac77fa 4844 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4845 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4846 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4847 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4848 if (rc != X86EMUL_CONTINUE)
4849 goto done;
038e51de 4850 }
9dac77fa 4851 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4852
018a98db
AK		 4853special_insn:
4854
685bbf4a 4855 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4856 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4857 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4858 if (rc != X86EMUL_CONTINUE)
4859 goto done;
4860 }
4861
b9a1ecb9
NA		 4862 if (ctxt->rep_prefix && (ctxt->d & String))
4863 ctxt->eflags |= EFLG_RF;
4864 else
4865 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4866
9dac77fa 4867 if (ctxt->execute) {
e28bbd44
AK		 4868 if (ctxt->d & Fastop) {
4869 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4870 rc = fastop(ctxt, fop);
4871 if (rc != X86EMUL_CONTINUE)
4872 goto done;
4873 goto writeback;
4874 }
9dac77fa 4875 rc = ctxt->execute(ctxt);
ef65c889
AK		 4876 if (rc != X86EMUL_CONTINUE)
4877 goto done;
4878 goto writeback;
4879 }
4880
1ce19dc1 4881 if (ctxt->opcode_len == 2)
6aa8b732 4882 goto twobyte_insn;
0bc5eedb
BP		 4883 else if (ctxt->opcode_len == 3)
4884 goto threebyte_insn;
6aa8b732 4885
9dac77fa 4886 switch (ctxt->b) {
6aa8b732 4887 case 0x63: /* movsxd */
8b4caf66 4888 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4889 goto cannot_emulate;
9dac77fa 4890 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4891 break;
b2833e3c 4892 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4893 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4894 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4895 break;
7e0b54b1 4896 case 0x8d: /* lea r16/r32, m */
9dac77fa 4897 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4898 break;
3d9e77df 4899 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4900 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4901 ctxt->dst.type = OP_NONE;
4902 else
4903 rc = em_xchg(ctxt);
e4f973ae 4904 break;
e8b6fa70 4905 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4906 switch (ctxt->op_bytes) {
4907 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4908 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4909 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4910 }
4911 break;
6e154e56 4912 case 0xcc: /* int3 */
5c5df76b
TY		 4913 rc = emulate_int(ctxt, 3);
4914 break;
6e154e56 4915 case 0xcd: /* int n */
9dac77fa 4916 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4917 break;
4918 case 0xce: /* into */
5c5df76b
TY		 4919 if (ctxt->eflags & EFLG_OF)
4920 rc = emulate_int(ctxt, 4);
6e154e56 4921 break;
1a52e051 4922 case 0xe9: /* jmp rel */
db5b0762 4923 case 0xeb: /* jmp rel short */
234f3ce4 4924 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4925 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4926 break;
111de5d6 4927 case 0xf4: /* hlt */
6c3287f7 4928 ctxt->ops->halt(ctxt);
19fdfa0d 4929 break;
111de5d6
AK		 4930 case 0xf5: /* cmc */
4931 /* complement carry flag from eflags reg */
4932 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4933 break;
4934 case 0xf8: /* clc */
4935 ctxt->eflags &= ~EFLG_CF;
111de5d6 4936 break;
8744aa9a
MG		 4937 case 0xf9: /* stc */
4938 ctxt->eflags |= EFLG_CF;
4939 break;
fb4616f4
MG		 4940 case 0xfc: /* cld */
4941 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4942 break;
4943 case 0xfd: /* std */
4944 ctxt->eflags |= EFLG_DF;
fb4616f4 4945 break;
91269b8f
AK		 4946 default:
4947 goto cannot_emulate;
6aa8b732 4948 }
018a98db 4949
7d9ddaed
AK		 4950 if (rc != X86EMUL_CONTINUE)
4951 goto done;
4952
018a98db 4953writeback:
fb32b1ed
AK		 4954 if (ctxt->d & SrcWrite) {
4955 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4956 rc = writeback(ctxt, &ctxt->src);
4957 if (rc != X86EMUL_CONTINUE)
4958 goto done;
4959 }
ee212297
NA		 4960 if (!(ctxt->d & NoWrite)) {
4961 rc = writeback(ctxt, &ctxt->dst);
4962 if (rc != X86EMUL_CONTINUE)
4963 goto done;
4964 }
018a98db 4965
5cd21917
GN		 4966 /*
4967 * restore dst type in case the decoding will be reused
4968 * (happens for string instruction )
4969 */
9dac77fa 4970 ctxt->dst.type = saved_dst_type;
5cd21917 4971
9dac77fa 4972 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4973 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4974
9dac77fa 4975 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4976 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4977
9dac77fa 4978 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4979 unsigned int count;
9dac77fa 4980 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4981 if ((ctxt->d & SrcMask) == SrcSI)
4982 count = ctxt->src.count;
4983 else
4984 count = ctxt->dst.count;
4985 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4986 -count);
3e2f65d5 4987
d2ddd1c4
GN		 4988 if (!string_insn_completed(ctxt)) {
4989 /*
4990 * Re-enter guest when pio read ahead buffer is empty
4991 * or, if it is not used, after each 1024 iteration.
4992 */
dd856efa 4993 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4994 (r->end == 0 || r->end != r->pos)) {
4995 /*
4996 * Reset read cache. Usually happens before
4997 * decode, but since instruction is restarted
4998 * we have to do it here.
4999 */
9dac77fa 5000 ctxt->mem_read.end = 0;
dd856efa 5001 writeback_registers(ctxt);
d2ddd1c4
GN		 5002 return EMULATION_RESTART;
5003 }
5004 goto done; /* skip rip writeback */
0fa6ccbd 5005 }
b9a1ecb9 5006 ctxt->eflags &= ~EFLG_RF;
5cd21917 5007 }
d2ddd1c4 5008
9dac77fa 5009 ctxt->eip = ctxt->_eip;
018a98db
AK		 5010
5011done:
e0ad0b47
PB		 5012 if (rc == X86EMUL_PROPAGATE_FAULT) {
5013 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5014 ctxt->have_exception = true;
e0ad0b47 5015 }
775fde86
JR		 5016 if (rc == X86EMUL_INTERCEPTED)
5017 return EMULATION_INTERCEPTED;
5018
dd856efa
AK		 5019 if (rc == X86EMUL_CONTINUE)
5020 writeback_registers(ctxt);
5021
d2ddd1c4 5022 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5023
5024twobyte_insn:
9dac77fa 5025 switch (ctxt->b) {
018a98db 5026 case 0x09: /* wbinvd */
cfb22375 5027 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5028 break;
5029 case 0x08: /* invd */
018a98db
AK		 5030 case 0x0d: /* GrpP (prefetch) */
5031 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5032 case 0x1f: /* nop */
018a98db
AK		 5033 break;
5034 case 0x20: /* mov cr, reg */
9dac77fa 5035 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5036 break;
6aa8b732 5037 case 0x21: /* mov from dr to reg */
9dac77fa 5038 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5039 break;
6aa8b732 5040 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5041 if (test_cc(ctxt->b, ctxt->eflags))
5042 ctxt->dst.val = ctxt->src.val;
5043 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5044 ctxt->op_bytes != 4)
9dac77fa 5045 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5046 break;
b2833e3c 5047 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5048 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5049 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5050 break;
ee45b58e 5051 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5052 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5053 break;
6aa8b732 5054 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5055 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5056 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5057 : (u16) ctxt->src.val;
6aa8b732 5058 break;
6aa8b732 5059 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5060 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5061 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5062 (s16) ctxt->src.val;
6aa8b732 5063 break;
a012e65a 5064 case 0xc3: /* movnti */
9dac77fa 5065 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 5066 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
5067 (u32) ctxt->src.val;
a012e65a 5068 break;
91269b8f
AK		 5069 default:
5070 goto cannot_emulate;
6aa8b732 5071 }
7d9ddaed 5072
0bc5eedb
BP		 5073threebyte_insn:
5074
7d9ddaed
AK		 5075 if (rc != X86EMUL_CONTINUE)
5076 goto done;
5077
6aa8b732
AK		 5078 goto writeback;
5079
5080cannot_emulate:
a0c0ab2f 5081 return EMULATION_FAILED;
6aa8b732 5082}
dd856efa
AK		 5083
5084void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5085{
5086 invalidate_registers(ctxt);
5087}
5088
5089void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5090{
5091 writeback_registers(ctxt);
5092}
ubuntu-bionic-kernel mirror