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KVM: x86 emulator: fix RDPMC privilege check
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
0fe59128
AK		 60
61#define OpBits 5 /* Width of operand field */
b1ea50b2 62#define OpMask ((1ull << OpBits) - 1)
a9945549 63
6aa8b732
AK		 64/*
65 * Opcode effective-address decode tables.
66 * Note that we only emulate instructions that have at least one memory
67 * operand (excluding implicit stack references). We assume that stack
68 * references and instruction fetches will never occur in special memory
69 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
70 * not be handled.
71 */
72
73/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 74#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 75/* Destination operand type. */
a9945549
AK		 76#define DstShift 1
77#define ImplicitOps (OpImplicit << DstShift)
78#define DstReg (OpReg << DstShift)
79#define DstMem (OpMem << DstShift)
80#define DstAcc (OpAcc << DstShift)
81#define DstDI (OpDI << DstShift)
82#define DstMem64 (OpMem64 << DstShift)
83#define DstImmUByte (OpImmUByte << DstShift)
84#define DstDX (OpDX << DstShift)
85#define DstMask (OpMask << DstShift)
6aa8b732 86/* Source operand type. */
0fe59128
AK		 87#define SrcShift 6
88#define SrcNone (OpNone << SrcShift)
89#define SrcReg (OpReg << SrcShift)
90#define SrcMem (OpMem << SrcShift)
91#define SrcMem16 (OpMem16 << SrcShift)
92#define SrcMem32 (OpMem32 << SrcShift)
93#define SrcImm (OpImm << SrcShift)
94#define SrcImmByte (OpImmByte << SrcShift)
95#define SrcOne (OpOne << SrcShift)
96#define SrcImmUByte (OpImmUByte << SrcShift)
97#define SrcImmU (OpImmU << SrcShift)
98#define SrcSI (OpSI << SrcShift)
99#define SrcImmFAddr (OpImmFAddr << SrcShift)
100#define SrcMemFAddr (OpMemFAddr << SrcShift)
101#define SrcAcc (OpAcc << SrcShift)
102#define SrcImmU16 (OpImmU16 << SrcShift)
103#define SrcDX (OpDX << SrcShift)
104#define SrcMask (OpMask << SrcShift)
221192bd
MT		 105#define BitOp (1<<11)
106#define MemAbs (1<<12) /* Memory operand is absolute displacement */
107#define String (1<<13) /* String instruction (rep capable) */
108#define Stack (1<<14) /* Stack instruction (push/pop) */
109#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
110#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
111#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
112#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
113#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
114#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 115/* Generic ModRM decode. */
116#define ModRM (1<<19)
117/* Destination is only written; never read. */
118#define Mov (1<<20)
d8769fed 119/* Misc flags */
8ea7d6ae 120#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 121#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 122#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 123#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 124#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 125#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 126#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 127#define No64 (1<<28)
d5ae7ce8 128#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 129/* Source 2 operand type */
d5ae7ce8 130#define Src2Shift (30)
4dd6a57d
AK		 131#define Src2None (OpNone << Src2Shift)
132#define Src2CL (OpCL << Src2Shift)
133#define Src2ImmByte (OpImmByte << Src2Shift)
134#define Src2One (OpOne << Src2Shift)
135#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 136#define Src2ES (OpES << Src2Shift)
137#define Src2CS (OpCS << Src2Shift)
138#define Src2SS (OpSS << Src2Shift)
139#define Src2DS (OpDS << Src2Shift)
140#define Src2FS (OpFS << Src2Shift)
141#define Src2GS (OpGS << Src2Shift)
4dd6a57d 142#define Src2Mask (OpMask << Src2Shift)
6aa8b732 143
d0e53325
AK		 144#define X2(x...) x, x
145#define X3(x...) X2(x), x
146#define X4(x...) X2(x), X2(x)
147#define X5(x...) X4(x), x
148#define X6(x...) X4(x), X2(x)
149#define X7(x...) X4(x), X3(x)
150#define X8(x...) X4(x), X4(x)
151#define X16(x...) X8(x), X8(x)
83babbca 152
d65b1dee 153struct opcode {
b1ea50b2
AK		 154 u64 flags : 56;
155 u64 intercept : 8;
120df890 156 union {
ef65c889 157 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 158 struct opcode *group;
159 struct group_dual *gdual;
0d7cdee8 160 struct gprefix *gprefix;
120df890 161 } u;
d09beabd 162 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 163};
164
165struct group_dual {
166 struct opcode mod012[8];
167 struct opcode mod3[8];
d65b1dee
AK		 168};
169
0d7cdee8
AK		 170struct gprefix {
171 struct opcode pfx_no;
172 struct opcode pfx_66;
173 struct opcode pfx_f2;
174 struct opcode pfx_f3;
175};
176
6aa8b732 177/* EFLAGS bit definitions. */
d4c6a154
GN		 178#define EFLG_ID (1<<21)
179#define EFLG_VIP (1<<20)
180#define EFLG_VIF (1<<19)
181#define EFLG_AC (1<<18)
b1d86143
AP		 182#define EFLG_VM (1<<17)
183#define EFLG_RF (1<<16)
d4c6a154
GN		 184#define EFLG_IOPL (3<<12)
185#define EFLG_NT (1<<14)
6aa8b732
AK		 186#define EFLG_OF (1<<11)
187#define EFLG_DF (1<<10)
b1d86143 188#define EFLG_IF (1<<9)
d4c6a154 189#define EFLG_TF (1<<8)
6aa8b732
AK		 190#define EFLG_SF (1<<7)
191#define EFLG_ZF (1<<6)
192#define EFLG_AF (1<<4)
193#define EFLG_PF (1<<2)
194#define EFLG_CF (1<<0)
195
62bd430e
MG		 196#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
197#define EFLG_RESERVED_ONE_MASK 2
198
6aa8b732
AK		 199/*
200 * Instruction emulation:
201 * Most instructions are emulated directly via a fragment of inline assembly
202 * code. This allows us to save/restore EFLAGS and thus very easily pick up
203 * any modified flags.
204 */
205
05b3e0c2 206#if defined(CONFIG_X86_64)
6aa8b732
AK		 207#define _LO32 "k" /* force 32-bit operand */
208#define _STK "%%rsp" /* stack pointer */
209#elif defined(__i386__)
210#define _LO32 "" /* force 32-bit operand */
211#define _STK "%%esp" /* stack pointer */
212#endif
213
214/*
215 * These EFLAGS bits are restored from saved value during emulation, and
216 * any changes are written back to the saved value after emulation.
217 */
218#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
219
220/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 221#define _PRE_EFLAGS(_sav, _msk, _tmp) \
222 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
223 "movl %"_sav",%"_LO32 _tmp"; " \
224 "push %"_tmp"; " \
225 "push %"_tmp"; " \
226 "movl %"_msk",%"_LO32 _tmp"; " \
227 "andl %"_LO32 _tmp",("_STK"); " \
228 "pushf; " \
229 "notl %"_LO32 _tmp"; " \
230 "andl %"_LO32 _tmp",("_STK"); " \
231 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
232 "pop %"_tmp"; " \
233 "orl %"_LO32 _tmp",("_STK"); " \
234 "popf; " \
235 "pop %"_sav"; "
6aa8b732
AK		 236
237/* After executing instruction: write-back necessary bits in EFLAGS. */
238#define _POST_EFLAGS(_sav, _msk, _tmp) \
239 /* _sav |= EFLAGS & _msk; */ \
240 "pushf; " \
241 "pop %"_tmp"; " \
242 "andl %"_msk",%"_LO32 _tmp"; " \
243 "orl %"_LO32 _tmp",%"_sav"; "
244
dda96d8f
AK		 245#ifdef CONFIG_X86_64
246#define ON64(x) x
247#else
248#define ON64(x)
249#endif
250
a31b9cea 251#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 252 do { \
253 __asm__ __volatile__ ( \
254 _PRE_EFLAGS("0", "4", "2") \
255 _op _suffix " %"_x"3,%1; " \
256 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 257 : "=m" ((ctxt)->eflags), \
258 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 259 "=&r" (_tmp) \
a31b9cea 260 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 261 } while (0)
6b7ad61f
AK		 262
263
6aa8b732 264/* Raw emulation: instruction has two explicit operands. */
a31b9cea 265#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 266 do { \
267 unsigned long _tmp; \
268 \
a31b9cea 269 switch ((ctxt)->dst.bytes) { \
6b7ad61f 270 case 2: \
a31b9cea 271 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 272 break; \
273 case 4: \
a31b9cea 274 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 275 break; \
276 case 8: \
a31b9cea 277 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 278 break; \
279 } \
6aa8b732
AK		 280 } while (0)
281
a31b9cea 282#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 283 do { \
6b7ad61f 284 unsigned long _tmp; \
a31b9cea 285 switch ((ctxt)->dst.bytes) { \
6aa8b732 286 case 1: \
a31b9cea 287 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 288 break; \
289 default: \
a31b9cea 290 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 291 _wx, _wy, _lx, _ly, _qx, _qy); \
292 break; \
293 } \
294 } while (0)
295
296/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 297#define emulate_2op_SrcB(ctxt, _op) \
298 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 299
300/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 301#define emulate_2op_SrcV(ctxt, _op) \
302 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 303
304/* Source operand is word, long or quad sized. */
a31b9cea
AK		 305#define emulate_2op_SrcV_nobyte(ctxt, _op) \
306 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 307
d175226a 308/* Instruction has three operands and one operand is stored in ECX register */
29053a60 309#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 310 do { \
311 unsigned long _tmp; \
761441b9
AK		 312 _type _clv = (ctxt)->src2.val; \
313 _type _srcv = (ctxt)->src.val; \
314 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 315 \
316 __asm__ __volatile__ ( \
317 _PRE_EFLAGS("0", "5", "2") \
318 _op _suffix " %4,%1 \n" \
319 _POST_EFLAGS("0", "5", "2") \
761441b9 320 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 321 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
322 ); \
323 \
761441b9
AK		 324 (ctxt)->src2.val = (unsigned long) _clv; \
325 (ctxt)->src2.val = (unsigned long) _srcv; \
326 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 327 } while (0)
328
761441b9 329#define emulate_2op_cl(ctxt, _op) \
7295261c 330 do { \
761441b9 331 switch ((ctxt)->dst.bytes) { \
7295261c 332 case 2: \
29053a60 333 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 334 break; \
335 case 4: \
29053a60 336 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 337 break; \
338 case 8: \
29053a60 339 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 340 break; \
341 } \
d175226a
GT		 342 } while (0)
343
d1eef45d 344#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 345 do { \
346 unsigned long _tmp; \
347 \
dda96d8f
AK		 348 __asm__ __volatile__ ( \
349 _PRE_EFLAGS("0", "3", "2") \
350 _op _suffix " %1; " \
351 _POST_EFLAGS("0", "3", "2") \
d1eef45d 352 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 353 "=&r" (_tmp) \
354 : "i" (EFLAGS_MASK)); \
355 } while (0)
356
357/* Instruction has only one explicit operand (no source operand). */
d1eef45d 358#define emulate_1op(ctxt, _op) \
dda96d8f 359 do { \
d1eef45d
AK		 360 switch ((ctxt)->dst.bytes) { \
361 case 1: __emulate_1op(ctxt, _op, "b"); break; \
362 case 2: __emulate_1op(ctxt, _op, "w"); break; \
363 case 4: __emulate_1op(ctxt, _op, "l"); break; \
364 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 365 } \
366 } while (0)
367
e8f2b1d6 368#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 369 do { \
370 unsigned long _tmp; \
e8f2b1d6
AK		 371 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
372 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 373 \
374 __asm__ __volatile__ ( \
375 _PRE_EFLAGS("0", "5", "1") \
376 "1: \n\t" \
377 _op _suffix " %6; " \
378 "2: \n\t" \
379 _POST_EFLAGS("0", "5", "1") \
380 ".pushsection .fixup,\"ax\" \n\t" \
381 "3: movb $1, %4 \n\t" \
382 "jmp 2b \n\t" \
383 ".popsection \n\t" \
384 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 385 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
386 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
387 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
388 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 389 } while (0)
390
3f9f53b0 391/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 392#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 393 do { \
e8f2b1d6 394 switch((ctxt)->src.bytes) { \
7295261c 395 case 1: \
e8f2b1d6 396 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 397 break; \
398 case 2: \
e8f2b1d6 399 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 400 break; \
401 case 4: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 403 break; \
404 case 8: ON64( \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 406 break; \
407 } \
408 } while (0)
409
8a76d7f2
JR		 410static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
411 enum x86_intercept intercept,
412 enum x86_intercept_stage stage)
413{
414 struct x86_instruction_info info = {
415 .intercept = intercept,
9dac77fa
AK		 416 .rep_prefix = ctxt->rep_prefix,
417 .modrm_mod = ctxt->modrm_mod,
418 .modrm_reg = ctxt->modrm_reg,
419 .modrm_rm = ctxt->modrm_rm,
420 .src_val = ctxt->src.val64,
421 .src_bytes = ctxt->src.bytes,
422 .dst_bytes = ctxt->dst.bytes,
423 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 424 .next_rip = ctxt->eip,
425 };
426
2953538e 427 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 428}
429
9dac77fa 430static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 431{
9dac77fa 432 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 433}
434
6aa8b732 435/* Access/update address held in a register, based on addressing mode. */
e4706772 436static inline unsigned long
9dac77fa 437address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 438{
9dac77fa 439 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 440 return reg;
441 else
9dac77fa 442 return reg & ad_mask(ctxt);
e4706772
HH		 443}
444
445static inline unsigned long
9dac77fa 446register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 447{
9dac77fa 448 return address_mask(ctxt, reg);
e4706772
HH		 449}
450
7a957275 451static inline void
9dac77fa 452register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 453{
9dac77fa 454 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 455 *reg += inc;
456 else
9dac77fa 457 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 458}
6aa8b732 459
9dac77fa 460static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 461{
9dac77fa 462 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 463}
098c937b 464
56697687
AK		 465static u32 desc_limit_scaled(struct desc_struct *desc)
466{
467 u32 limit = get_desc_limit(desc);
468
469 return desc->g ? (limit << 12) | 0xfff : limit;
470}
471
9dac77fa 472static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 473{
9dac77fa
AK		 474 ctxt->has_seg_override = true;
475 ctxt->seg_override = seg;
7a5b56df
AK		 476}
477
7b105ca2 478static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 479{
480 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
481 return 0;
482
7b105ca2 483 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 484}
485
9dac77fa 486static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 487{
9dac77fa 488 if (!ctxt->has_seg_override)
7a5b56df
AK		 489 return 0;
490
9dac77fa 491 return ctxt->seg_override;
7a5b56df
AK		 492}
493
35d3d4a1
AK		 494static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
495 u32 error, bool valid)
54b8486f 496{
da9cb575
AK		 497 ctxt->exception.vector = vec;
498 ctxt->exception.error_code = error;
499 ctxt->exception.error_code_valid = valid;
35d3d4a1 500 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 501}
502
3b88e41a
JR		 503static int emulate_db(struct x86_emulate_ctxt *ctxt)
504{
505 return emulate_exception(ctxt, DB_VECTOR, 0, false);
506}
507
35d3d4a1 508static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 509{
35d3d4a1 510 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 511}
512
618ff15d
AK		 513static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
514{
515 return emulate_exception(ctxt, SS_VECTOR, err, true);
516}
517
35d3d4a1 518static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 519{
35d3d4a1 520 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 521}
522
35d3d4a1 523static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 524{
35d3d4a1 525 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 526}
527
34d1f490
AK		 528static int emulate_de(struct x86_emulate_ctxt *ctxt)
529{
35d3d4a1 530 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 531}
532
1253791d
AK		 533static int emulate_nm(struct x86_emulate_ctxt *ctxt)
534{
535 return emulate_exception(ctxt, NM_VECTOR, 0, false);
536}
537
1aa36616
AK		 538static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
539{
540 u16 selector;
541 struct desc_struct desc;
542
543 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
544 return selector;
545}
546
547static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
548 unsigned seg)
549{
550 u16 dummy;
551 u32 base3;
552 struct desc_struct desc;
553
554 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
555 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
556}
557
3d9b938e 558static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 559 struct segmented_address addr,
3d9b938e 560 unsigned size, bool write, bool fetch,
52fd8b44
AK		 561 ulong *linear)
562{
618ff15d
AK		 563 struct desc_struct desc;
564 bool usable;
52fd8b44 565 ulong la;
618ff15d 566 u32 lim;
1aa36616 567 u16 sel;
618ff15d 568 unsigned cpl, rpl;
52fd8b44 569
7b105ca2 570 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 571 switch (ctxt->mode) {
572 case X86EMUL_MODE_REAL:
573 break;
574 case X86EMUL_MODE_PROT64:
575 if (((signed long)la << 16) >> 16 != la)
576 return emulate_gp(ctxt, 0);
577 break;
578 default:
1aa36616
AK		 579 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
580 addr.seg);
618ff15d
AK		 581 if (!usable)
582 goto bad;
583 /* code segment or read-only data segment */
584 if (((desc.type & 8) || !(desc.type & 2)) && write)
585 goto bad;
586 /* unreadable code segment */
3d9b938e 587 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 588 goto bad;
589 lim = desc_limit_scaled(&desc);
590 if ((desc.type & 8) || !(desc.type & 4)) {
591 /* expand-up segment */
592 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
593 goto bad;
594 } else {
595 /* exapand-down segment */
596 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
597 goto bad;
598 lim = desc.d ? 0xffffffff : 0xffff;
599 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
600 goto bad;
601 }
717746e3 602 cpl = ctxt->ops->cpl(ctxt);
1aa36616 603 rpl = sel & 3;
618ff15d
AK		 604 cpl = max(cpl, rpl);
605 if (!(desc.type & 8)) {
606 /* data segment */
607 if (cpl > desc.dpl)
608 goto bad;
609 } else if ((desc.type & 8) && !(desc.type & 4)) {
610 /* nonconforming code segment */
611 if (cpl != desc.dpl)
612 goto bad;
613 } else if ((desc.type & 8) && (desc.type & 4)) {
614 /* conforming code segment */
615 if (cpl < desc.dpl)
616 goto bad;
617 }
618 break;
619 }
9dac77fa 620 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 621 la &= (u32)-1;
622 *linear = la;
623 return X86EMUL_CONTINUE;
618ff15d
AK		 624bad:
625 if (addr.seg == VCPU_SREG_SS)
626 return emulate_ss(ctxt, addr.seg);
627 else
628 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 629}
630
3d9b938e
NE		 631static int linearize(struct x86_emulate_ctxt *ctxt,
632 struct segmented_address addr,
633 unsigned size, bool write,
634 ulong *linear)
635{
636 return __linearize(ctxt, addr, size, write, false, linear);
637}
638
639
3ca3ac4d
AK		 640static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
641 struct segmented_address addr,
642 void *data,
643 unsigned size)
644{
9fa088f4
AK		 645 int rc;
646 ulong linear;
647
83b8795a 648 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 649 if (rc != X86EMUL_CONTINUE)
650 return rc;
0f65dd70 651 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 652}
653
807941b1
TY		 654/*
655 * Fetch the next byte of the instruction being emulated which is pointed to
656 * by ctxt->_eip, then increment ctxt->_eip.
657 *
658 * Also prefetch the remaining bytes of the instruction without crossing page
659 * boundary if they are not in fetch_cache yet.
660 */
661static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 662{
9dac77fa 663 struct fetch_cache *fc = &ctxt->fetch;
62266869 664 int rc;
2fb53ad8 665 int size, cur_size;
62266869 666
807941b1 667 if (ctxt->_eip == fc->end) {
3d9b938e 668 unsigned long linear;
807941b1
TY		 669 struct segmented_address addr = { .seg = VCPU_SREG_CS,
670 .ea = ctxt->_eip };
2fb53ad8 671 cur_size = fc->end - fc->start;
807941b1
TY		 672 size = min(15UL - cur_size,
673 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 674 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 675 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 676 return rc;
ef5d75cc
TY		 677 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
678 size, &ctxt->exception);
7d88bb48 679 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 680 return rc;
2fb53ad8 681 fc->end += size;
62266869 682 }
807941b1
TY		 683 *dest = fc->data[ctxt->_eip - fc->start];
684 ctxt->_eip++;
3e2815e9 685 return X86EMUL_CONTINUE;
62266869
AK		 686}
687
688static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 689 void *dest, unsigned size)
62266869 690{
3e2815e9 691 int rc;
62266869 692
eb3c79e6 693 /* x86 instructions are limited to 15 bytes. */
7d88bb48 694 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 695 return X86EMUL_UNHANDLEABLE;
62266869 696 while (size--) {
807941b1 697 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 698 if (rc != X86EMUL_CONTINUE)
62266869
AK		 699 return rc;
700 }
3e2815e9 701 return X86EMUL_CONTINUE;
62266869
AK		 702}
703
67cbc90d 704/* Fetch next part of the instruction being emulated. */
e85a1085 705#define insn_fetch(_type, _ctxt) \
67cbc90d 706({ unsigned long _x; \
e85a1085 707 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 708 if (rc != X86EMUL_CONTINUE) \
709 goto done; \
67cbc90d
TY		 710 (_type)_x; \
711})
712
807941b1
TY		 713#define insn_fetch_arr(_arr, _size, _ctxt) \
714({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 715 if (rc != X86EMUL_CONTINUE) \
716 goto done; \
67cbc90d
TY		 717})
718
1e3c5cb0
RR		 719/*
720 * Given the 'reg' portion of a ModRM byte, and a register block, return a
721 * pointer into the block that addresses the relevant register.
722 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
723 */
724static void *decode_register(u8 modrm_reg, unsigned long *regs,
725 int highbyte_regs)
6aa8b732
AK		 726{
727 void *p;
728
729 p = &regs[modrm_reg];
730 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
731 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
732 return p;
733}
734
735static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 736 struct segmented_address addr,
6aa8b732
AK		 737 u16 *size, unsigned long *address, int op_bytes)
738{
739 int rc;
740
741 if (op_bytes == 2)
742 op_bytes = 3;
743 *address = 0;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 745 if (rc != X86EMUL_CONTINUE)
6aa8b732 746 return rc;
30b31ab6 747 addr.ea += 2;
3ca3ac4d 748 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 749 return rc;
750}
751
bbe9abbd
NK		 752static int test_cc(unsigned int condition, unsigned int flags)
753{
754 int rc = 0;
755
756 switch ((condition & 15) >> 1) {
757 case 0: /* o */
758 rc |= (flags & EFLG_OF);
759 break;
760 case 1: /* b/c/nae */
761 rc |= (flags & EFLG_CF);
762 break;
763 case 2: /* z/e */
764 rc |= (flags & EFLG_ZF);
765 break;
766 case 3: /* be/na */
767 rc |= (flags & (EFLG_CF|EFLG_ZF));
768 break;
769 case 4: /* s */
770 rc |= (flags & EFLG_SF);
771 break;
772 case 5: /* p/pe */
773 rc |= (flags & EFLG_PF);
774 break;
775 case 7: /* le/ng */
776 rc |= (flags & EFLG_ZF);
777 /* fall through */
778 case 6: /* l/nge */
779 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
780 break;
781 }
782
783 /* Odd condition identifiers (lsb == 1) have inverted sense. */
784 return (!!rc ^ (condition & 1));
785}
786
91ff3cb4
AK		 787static void fetch_register_operand(struct operand *op)
788{
789 switch (op->bytes) {
790 case 1:
791 op->val = *(u8 *)op->addr.reg;
792 break;
793 case 2:
794 op->val = *(u16 *)op->addr.reg;
795 break;
796 case 4:
797 op->val = *(u32 *)op->addr.reg;
798 break;
799 case 8:
800 op->val = *(u64 *)op->addr.reg;
801 break;
802 }
803}
804
1253791d
AK		 805static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
806{
807 ctxt->ops->get_fpu(ctxt);
808 switch (reg) {
809 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
810 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
811 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
812 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
813 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
814 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
815 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
816 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
817#ifdef CONFIG_X86_64
818 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
819 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
820 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
821 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
822 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
823 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
824 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
825 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
826#endif
827 default: BUG();
828 }
829 ctxt->ops->put_fpu(ctxt);
830}
831
832static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
833 int reg)
834{
835 ctxt->ops->get_fpu(ctxt);
836 switch (reg) {
837 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
838 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
839 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
840 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
841 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
842 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
843 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
844 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
845#ifdef CONFIG_X86_64
846 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
847 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
848 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
849 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
850 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
851 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
852 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
853 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
854#endif
855 default: BUG();
856 }
857 ctxt->ops->put_fpu(ctxt);
858}
859
860static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
861 struct operand *op,
3c118e24
AK		 862 int inhibit_bytereg)
863{
9dac77fa
AK		 864 unsigned reg = ctxt->modrm_reg;
865 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 866
9dac77fa
AK		 867 if (!(ctxt->d & ModRM))
868 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 869
9dac77fa 870 if (ctxt->d & Sse) {
1253791d
AK		 871 op->type = OP_XMM;
872 op->bytes = 16;
873 op->addr.xmm = reg;
874 read_sse_reg(ctxt, &op->vec_val, reg);
875 return;
876 }
877
3c118e24 878 op->type = OP_REG;
9dac77fa
AK		 879 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
880 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 881 op->bytes = 1;
882 } else {
9dac77fa
AK		 883 op->addr.reg = decode_register(reg, ctxt->regs, 0);
884 op->bytes = ctxt->op_bytes;
3c118e24 885 }
91ff3cb4 886 fetch_register_operand(op);
3c118e24
AK		 887 op->orig_val = op->val;
888}
889
1c73ef66 890static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 891 struct operand *op)
1c73ef66 892{
1c73ef66 893 u8 sib;
f5b4edcd 894 int index_reg = 0, base_reg = 0, scale;
3e2815e9 895 int rc = X86EMUL_CONTINUE;
2dbd0dd7 896 ulong modrm_ea = 0;
1c73ef66 897
9dac77fa
AK		 898 if (ctxt->rex_prefix) {
899 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
900 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
901 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 902 }
903
e85a1085 904 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 905 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
906 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
907 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
908 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 909
9dac77fa 910 if (ctxt->modrm_mod == 3) {
2dbd0dd7 911 op->type = OP_REG;
9dac77fa
AK		 912 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
913 op->addr.reg = decode_register(ctxt->modrm_rm,
914 ctxt->regs, ctxt->d & ByteOp);
915 if (ctxt->d & Sse) {
1253791d
AK		 916 op->type = OP_XMM;
917 op->bytes = 16;
9dac77fa
AK		 918 op->addr.xmm = ctxt->modrm_rm;
919 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 920 return rc;
921 }
2dbd0dd7 922 fetch_register_operand(op);
1c73ef66
AK		 923 return rc;
924 }
925
2dbd0dd7
AK		 926 op->type = OP_MEM;
927
9dac77fa
AK		 928 if (ctxt->ad_bytes == 2) {
929 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
930 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
931 unsigned si = ctxt->regs[VCPU_REGS_RSI];
932 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 933
934 /* 16-bit ModR/M decode. */
9dac77fa 935 switch (ctxt->modrm_mod) {
1c73ef66 936 case 0:
9dac77fa 937 if (ctxt->modrm_rm == 6)
e85a1085 938 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 939 break;
940 case 1:
e85a1085 941 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 942 break;
943 case 2:
e85a1085 944 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 945 break;
946 }
9dac77fa 947 switch (ctxt->modrm_rm) {
1c73ef66 948 case 0:
2dbd0dd7 949 modrm_ea += bx + si;
1c73ef66
AK		 950 break;
951 case 1:
2dbd0dd7 952 modrm_ea += bx + di;
1c73ef66
AK		 953 break;
954 case 2:
2dbd0dd7 955 modrm_ea += bp + si;
1c73ef66
AK		 956 break;
957 case 3:
2dbd0dd7 958 modrm_ea += bp + di;
1c73ef66
AK		 959 break;
960 case 4:
2dbd0dd7 961 modrm_ea += si;
1c73ef66
AK		 962 break;
963 case 5:
2dbd0dd7 964 modrm_ea += di;
1c73ef66
AK		 965 break;
966 case 6:
9dac77fa 967 if (ctxt->modrm_mod != 0)
2dbd0dd7 968 modrm_ea += bp;
1c73ef66
AK		 969 break;
970 case 7:
2dbd0dd7 971 modrm_ea += bx;
1c73ef66
AK		 972 break;
973 }
9dac77fa
AK		 974 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
975 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
976 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 977 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 978 } else {
979 /* 32/64-bit ModR/M decode. */
9dac77fa 980 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 981 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 982 index_reg |= (sib >> 3) & 7;
983 base_reg |= sib & 7;
984 scale = sib >> 6;
985
9dac77fa 986 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 987 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 988 else
9dac77fa 989 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 990 if (index_reg != 4)
9dac77fa
AK		 991 modrm_ea += ctxt->regs[index_reg] << scale;
992 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 993 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 994 ctxt->rip_relative = 1;
84411d85 995 } else
9dac77fa
AK		 996 modrm_ea += ctxt->regs[ctxt->modrm_rm];
997 switch (ctxt->modrm_mod) {
1c73ef66 998 case 0:
9dac77fa 999 if (ctxt->modrm_rm == 5)
e85a1085 1000 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1001 break;
1002 case 1:
e85a1085 1003 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1004 break;
1005 case 2:
e85a1085 1006 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1007 break;
1008 }
1009 }
90de84f5 1010 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1011done:
1012 return rc;
1013}
1014
1015static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1016 struct operand *op)
1c73ef66 1017{
3e2815e9 1018 int rc = X86EMUL_CONTINUE;
1c73ef66 1019
2dbd0dd7 1020 op->type = OP_MEM;
9dac77fa 1021 switch (ctxt->ad_bytes) {
1c73ef66 1022 case 2:
e85a1085 1023 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1024 break;
1025 case 4:
e85a1085 1026 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1027 break;
1028 case 8:
e85a1085 1029 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1030 break;
1031 }
1032done:
1033 return rc;
1034}
1035
9dac77fa 1036static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1037{
7129eeca 1038 long sv = 0, mask;
35c843c4 1039
9dac77fa
AK		 1040 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1041 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1042
9dac77fa
AK		 1043 if (ctxt->src.bytes == 2)
1044 sv = (s16)ctxt->src.val & (s16)mask;
1045 else if (ctxt->src.bytes == 4)
1046 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1047
9dac77fa 1048 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1049 }
ba7ff2b7
WY		 1050
1051 /* only subword offset */
9dac77fa 1052 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1053}
1054
dde7e6d1 1055static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1056 unsigned long addr, void *dest, unsigned size)
6aa8b732 1057{
dde7e6d1 1058 int rc;
9dac77fa 1059 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1060
dde7e6d1
AK		 1061 while (size) {
1062 int n = min(size, 8u);
1063 size -= n;
1064 if (mc->pos < mc->end)
1065 goto read_cached;
5cd21917 1066
7b105ca2
TY		 1067 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1068 &ctxt->exception);
dde7e6d1
AK		 1069 if (rc != X86EMUL_CONTINUE)
1070 return rc;
1071 mc->end += n;
6aa8b732 1072
dde7e6d1
AK		 1073 read_cached:
1074 memcpy(dest, mc->data + mc->pos, n);
1075 mc->pos += n;
1076 dest += n;
1077 addr += n;
6aa8b732 1078 }
dde7e6d1
AK		 1079 return X86EMUL_CONTINUE;
1080}
6aa8b732 1081
3ca3ac4d
AK		 1082static int segmented_read(struct x86_emulate_ctxt *ctxt,
1083 struct segmented_address addr,
1084 void *data,
1085 unsigned size)
1086{
9fa088f4
AK		 1087 int rc;
1088 ulong linear;
1089
83b8795a 1090 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1091 if (rc != X86EMUL_CONTINUE)
1092 return rc;
7b105ca2 1093 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1094}
1095
1096static int segmented_write(struct x86_emulate_ctxt *ctxt,
1097 struct segmented_address addr,
1098 const void *data,
1099 unsigned size)
1100{
9fa088f4
AK		 1101 int rc;
1102 ulong linear;
1103
83b8795a 1104 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1105 if (rc != X86EMUL_CONTINUE)
1106 return rc;
0f65dd70
AK		 1107 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1108 &ctxt->exception);
3ca3ac4d
AK		 1109}
1110
1111static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1112 struct segmented_address addr,
1113 const void *orig_data, const void *data,
1114 unsigned size)
1115{
9fa088f4
AK		 1116 int rc;
1117 ulong linear;
1118
83b8795a 1119 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1120 if (rc != X86EMUL_CONTINUE)
1121 return rc;
0f65dd70
AK		 1122 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1123 size, &ctxt->exception);
3ca3ac4d
AK		 1124}
1125
dde7e6d1 1126static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1127 unsigned int size, unsigned short port,
1128 void *dest)
1129{
9dac77fa 1130 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1131
dde7e6d1 1132 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1133 unsigned int in_page, n;
9dac77fa
AK		 1134 unsigned int count = ctxt->rep_prefix ?
1135 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1136 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1137 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1138 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1139 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1140 count);
1141 if (n == 0)
1142 n = 1;
1143 rc->pos = rc->end = 0;
7b105ca2 1144 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1145 return 0;
1146 rc->end = n * size;
6aa8b732
AK		 1147 }
1148
dde7e6d1
AK		 1149 memcpy(dest, rc->data + rc->pos, size);
1150 rc->pos += size;
1151 return 1;
1152}
6aa8b732 1153
dde7e6d1 1154static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1155 u16 selector, struct desc_ptr *dt)
1156{
7b105ca2
TY		 1157 struct x86_emulate_ops *ops = ctxt->ops;
1158
dde7e6d1
AK		 1159 if (selector & 1 << 2) {
1160 struct desc_struct desc;
1aa36616
AK		 1161 u16 sel;
1162
dde7e6d1 1163 memset (dt, 0, sizeof *dt);
1aa36616 1164 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1165 return;
e09d082c 1166
dde7e6d1
AK		 1167 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1168 dt->address = get_desc_base(&desc);
1169 } else
4bff1e86 1170 ops->get_gdt(ctxt, dt);
dde7e6d1 1171}
120df890 1172
dde7e6d1
AK		 1173/* allowed just for 8 bytes segments */
1174static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1175 u16 selector, struct desc_struct *desc)
1176{
1177 struct desc_ptr dt;
1178 u16 index = selector >> 3;
dde7e6d1 1179 ulong addr;
120df890 1180
7b105ca2 1181 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1182
35d3d4a1
AK		 1183 if (dt.size < index * 8 + 7)
1184 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1185
7b105ca2
TY		 1186 addr = dt.address + index * 8;
1187 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1188 &ctxt->exception);
dde7e6d1 1189}
ef65c889 1190
dde7e6d1
AK		 1191/* allowed just for 8 bytes segments */
1192static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1193 u16 selector, struct desc_struct *desc)
1194{
1195 struct desc_ptr dt;
1196 u16 index = selector >> 3;
dde7e6d1 1197 ulong addr;
6aa8b732 1198
7b105ca2 1199 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1200
35d3d4a1
AK		 1201 if (dt.size < index * 8 + 7)
1202 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1203
dde7e6d1 1204 addr = dt.address + index * 8;
7b105ca2
TY		 1205 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1206 &ctxt->exception);
dde7e6d1 1207}
c7e75a3d 1208
5601d05b 1209/* Does not support long mode */
dde7e6d1 1210static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1211 u16 selector, int seg)
1212{
1213 struct desc_struct seg_desc;
1214 u8 dpl, rpl, cpl;
1215 unsigned err_vec = GP_VECTOR;
1216 u32 err_code = 0;
1217 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1218 int ret;
69f55cb1 1219
dde7e6d1 1220 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1221
dde7e6d1
AK		 1222 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1223 || ctxt->mode == X86EMUL_MODE_REAL) {
1224 /* set real mode segment descriptor */
1225 set_desc_base(&seg_desc, selector << 4);
1226 set_desc_limit(&seg_desc, 0xffff);
1227 seg_desc.type = 3;
1228 seg_desc.p = 1;
1229 seg_desc.s = 1;
1230 goto load;
1231 }
1232
1233 /* NULL selector is not valid for TR, CS and SS */
1234 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1235 && null_selector)
1236 goto exception;
1237
1238 /* TR should be in GDT only */
1239 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1240 goto exception;
1241
1242 if (null_selector) /* for NULL selector skip all following checks */
1243 goto load;
1244
7b105ca2 1245 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1246 if (ret != X86EMUL_CONTINUE)
1247 return ret;
1248
1249 err_code = selector & 0xfffc;
1250 err_vec = GP_VECTOR;
1251
1252 /* can't load system descriptor into segment selecor */
1253 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1254 goto exception;
1255
1256 if (!seg_desc.p) {
1257 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1258 goto exception;
1259 }
1260
1261 rpl = selector & 3;
1262 dpl = seg_desc.dpl;
7b105ca2 1263 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1264
1265 switch (seg) {
1266 case VCPU_SREG_SS:
1267 /*
1268 * segment is not a writable data segment or segment
1269 * selector's RPL != CPL or segment selector's RPL != CPL
1270 */
1271 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1272 goto exception;
6aa8b732 1273 break;
dde7e6d1
AK		 1274 case VCPU_SREG_CS:
1275 if (!(seg_desc.type & 8))
1276 goto exception;
1277
1278 if (seg_desc.type & 4) {
1279 /* conforming */
1280 if (dpl > cpl)
1281 goto exception;
1282 } else {
1283 /* nonconforming */
1284 if (rpl > cpl || dpl != cpl)
1285 goto exception;
1286 }
1287 /* CS(RPL) <- CPL */
1288 selector = (selector & 0xfffc) | cpl;
6aa8b732 1289 break;
dde7e6d1
AK		 1290 case VCPU_SREG_TR:
1291 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1292 goto exception;
1293 break;
1294 case VCPU_SREG_LDTR:
1295 if (seg_desc.s || seg_desc.type != 2)
1296 goto exception;
1297 break;
1298 default: /* DS, ES, FS, or GS */
4e62417b 1299 /*
dde7e6d1
AK		 1300 * segment is not a data or readable code segment or
1301 * ((segment is a data or nonconforming code segment)
1302 * and (both RPL and CPL > DPL))
4e62417b 1303 */
dde7e6d1
AK		 1304 if ((seg_desc.type & 0xa) == 0x8 ||
1305 (((seg_desc.type & 0xc) != 0xc) &&
1306 (rpl > dpl && cpl > dpl)))
1307 goto exception;
6aa8b732 1308 break;
dde7e6d1
AK		 1309 }
1310
1311 if (seg_desc.s) {
1312 /* mark segment as accessed */
1313 seg_desc.type |= 1;
7b105ca2 1314 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1315 if (ret != X86EMUL_CONTINUE)
1316 return ret;
1317 }
1318load:
7b105ca2 1319 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1320 return X86EMUL_CONTINUE;
1321exception:
1322 emulate_exception(ctxt, err_vec, err_code, true);
1323 return X86EMUL_PROPAGATE_FAULT;
1324}
1325
31be40b3
WY		 1326static void write_register_operand(struct operand *op)
1327{
1328 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1329 switch (op->bytes) {
1330 case 1:
1331 *(u8 *)op->addr.reg = (u8)op->val;
1332 break;
1333 case 2:
1334 *(u16 *)op->addr.reg = (u16)op->val;
1335 break;
1336 case 4:
1337 *op->addr.reg = (u32)op->val;
1338 break; /* 64b: zero-extend */
1339 case 8:
1340 *op->addr.reg = op->val;
1341 break;
1342 }
1343}
1344
adddcecf 1345static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1346{
1347 int rc;
dde7e6d1 1348
9dac77fa 1349 switch (ctxt->dst.type) {
dde7e6d1 1350 case OP_REG:
9dac77fa 1351 write_register_operand(&ctxt->dst);
6aa8b732 1352 break;
dde7e6d1 1353 case OP_MEM:
9dac77fa 1354 if (ctxt->lock_prefix)
3ca3ac4d 1355 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1356 ctxt->dst.addr.mem,
1357 &ctxt->dst.orig_val,
1358 &ctxt->dst.val,
1359 ctxt->dst.bytes);
341de7e3 1360 else
3ca3ac4d 1361 rc = segmented_write(ctxt,
9dac77fa
AK		 1362 ctxt->dst.addr.mem,
1363 &ctxt->dst.val,
1364 ctxt->dst.bytes);
dde7e6d1
AK		 1365 if (rc != X86EMUL_CONTINUE)
1366 return rc;
a682e354 1367 break;
1253791d 1368 case OP_XMM:
9dac77fa 1369 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1370 break;
dde7e6d1
AK		 1371 case OP_NONE:
1372 /* no writeback */
414e6277 1373 break;
dde7e6d1 1374 default:
414e6277 1375 break;
6aa8b732 1376 }
dde7e6d1
AK		 1377 return X86EMUL_CONTINUE;
1378}
6aa8b732 1379
4487b3b4 1380static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1381{
4179bb02 1382 struct segmented_address addr;
0dc8d10f 1383
9dac77fa
AK		 1384 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1385 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1386 addr.seg = VCPU_SREG_SS;
1387
1388 /* Disable writeback. */
9dac77fa
AK		 1389 ctxt->dst.type = OP_NONE;
1390 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1391}
69f55cb1 1392
dde7e6d1 1393static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1394 void *dest, int len)
1395{
dde7e6d1 1396 int rc;
90de84f5 1397 struct segmented_address addr;
8b4caf66 1398
9dac77fa 1399 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1400 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1401 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1402 if (rc != X86EMUL_CONTINUE)
1403 return rc;
1404
9dac77fa 1405 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1406 return rc;
8b4caf66
LV		 1407}
1408
c54fe504
TY		 1409static int em_pop(struct x86_emulate_ctxt *ctxt)
1410{
9dac77fa 1411 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1412}
1413
dde7e6d1 1414static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1415 void *dest, int len)
9de41573
GN		 1416{
1417 int rc;
dde7e6d1
AK		 1418 unsigned long val, change_mask;
1419 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1420 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1421
3b9be3bf 1422 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1423 if (rc != X86EMUL_CONTINUE)
1424 return rc;
9de41573 1425
dde7e6d1
AK		 1426 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1427 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1428
dde7e6d1
AK		 1429 switch(ctxt->mode) {
1430 case X86EMUL_MODE_PROT64:
1431 case X86EMUL_MODE_PROT32:
1432 case X86EMUL_MODE_PROT16:
1433 if (cpl == 0)
1434 change_mask |= EFLG_IOPL;
1435 if (cpl <= iopl)
1436 change_mask |= EFLG_IF;
1437 break;
1438 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1439 if (iopl < 3)
1440 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1441 change_mask |= EFLG_IF;
1442 break;
1443 default: /* real mode */
1444 change_mask |= (EFLG_IOPL | EFLG_IF);
1445 break;
9de41573 1446 }
dde7e6d1
AK		 1447
1448 *(unsigned long *)dest =
1449 (ctxt->eflags & ~change_mask) | (val & change_mask);
1450
1451 return rc;
9de41573
GN		 1452}
1453
62aaa2f0
TY		 1454static int em_popf(struct x86_emulate_ctxt *ctxt)
1455{
9dac77fa
AK		 1456 ctxt->dst.type = OP_REG;
1457 ctxt->dst.addr.reg = &ctxt->eflags;
1458 ctxt->dst.bytes = ctxt->op_bytes;
1459 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1460}
1461
1cd196ea 1462static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1463{
1cd196ea
AK		 1464 int seg = ctxt->src2.val;
1465
9dac77fa 1466 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1467
4487b3b4 1468 return em_push(ctxt);
7b262e90
GN		 1469}
1470
1cd196ea 1471static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1472{
1cd196ea 1473 int seg = ctxt->src2.val;
dde7e6d1
AK		 1474 unsigned long selector;
1475 int rc;
38ba30ba 1476
9dac77fa 1477 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1478 if (rc != X86EMUL_CONTINUE)
1479 return rc;
1480
7b105ca2 1481 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1482 return rc;
38ba30ba
GN		 1483}
1484
b96a7fad 1485static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1486{
9dac77fa 1487 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1488 int rc = X86EMUL_CONTINUE;
1489 int reg = VCPU_REGS_RAX;
38ba30ba 1490
dde7e6d1
AK		 1491 while (reg <= VCPU_REGS_RDI) {
1492 (reg == VCPU_REGS_RSP) ?
9dac77fa 1493 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1494
4487b3b4 1495 rc = em_push(ctxt);
dde7e6d1
AK		 1496 if (rc != X86EMUL_CONTINUE)
1497 return rc;
38ba30ba 1498
dde7e6d1 1499 ++reg;
38ba30ba 1500 }
38ba30ba 1501
dde7e6d1 1502 return rc;
38ba30ba
GN		 1503}
1504
62aaa2f0
TY		 1505static int em_pushf(struct x86_emulate_ctxt *ctxt)
1506{
9dac77fa 1507 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1508 return em_push(ctxt);
1509}
1510
b96a7fad 1511static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1512{
dde7e6d1
AK		 1513 int rc = X86EMUL_CONTINUE;
1514 int reg = VCPU_REGS_RDI;
38ba30ba 1515
dde7e6d1
AK		 1516 while (reg >= VCPU_REGS_RAX) {
1517 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1518 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1519 ctxt->op_bytes);
dde7e6d1
AK		 1520 --reg;
1521 }
38ba30ba 1522
9dac77fa 1523 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1524 if (rc != X86EMUL_CONTINUE)
1525 break;
1526 --reg;
38ba30ba 1527 }
dde7e6d1 1528 return rc;
38ba30ba
GN		 1529}
1530
7b105ca2 1531int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1532{
7b105ca2 1533 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1534 int rc;
6e154e56
MG		 1535 struct desc_ptr dt;
1536 gva_t cs_addr;
1537 gva_t eip_addr;
1538 u16 cs, eip;
6e154e56
MG		 1539
1540 /* TODO: Add limit checks */
9dac77fa 1541 ctxt->src.val = ctxt->eflags;
4487b3b4 1542 rc = em_push(ctxt);
5c56e1cf
AK		 1543 if (rc != X86EMUL_CONTINUE)
1544 return rc;
6e154e56
MG		 1545
1546 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1547
9dac77fa 1548 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1549 rc = em_push(ctxt);
5c56e1cf
AK		 1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
6e154e56 1552
9dac77fa 1553 ctxt->src.val = ctxt->_eip;
4487b3b4 1554 rc = em_push(ctxt);
5c56e1cf
AK		 1555 if (rc != X86EMUL_CONTINUE)
1556 return rc;
1557
4bff1e86 1558 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1559
1560 eip_addr = dt.address + (irq << 2);
1561 cs_addr = dt.address + (irq << 2) + 2;
1562
0f65dd70 1563 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
0f65dd70 1567 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1568 if (rc != X86EMUL_CONTINUE)
1569 return rc;
1570
7b105ca2 1571 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1572 if (rc != X86EMUL_CONTINUE)
1573 return rc;
1574
9dac77fa 1575 ctxt->_eip = eip;
6e154e56
MG		 1576
1577 return rc;
1578}
1579
7b105ca2 1580static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1581{
1582 switch(ctxt->mode) {
1583 case X86EMUL_MODE_REAL:
7b105ca2 1584 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1585 case X86EMUL_MODE_VM86:
1586 case X86EMUL_MODE_PROT16:
1587 case X86EMUL_MODE_PROT32:
1588 case X86EMUL_MODE_PROT64:
1589 default:
1590 /* Protected mode interrupts unimplemented yet */
1591 return X86EMUL_UNHANDLEABLE;
1592 }
1593}
1594
7b105ca2 1595static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1596{
dde7e6d1
AK		 1597 int rc = X86EMUL_CONTINUE;
1598 unsigned long temp_eip = 0;
1599 unsigned long temp_eflags = 0;
1600 unsigned long cs = 0;
1601 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1602 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1603 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1604 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1605
dde7e6d1 1606 /* TODO: Add stack limit check */
38ba30ba 1607
9dac77fa 1608 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1609
dde7e6d1
AK		 1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
38ba30ba 1612
35d3d4a1
AK		 1613 if (temp_eip & ~0xffff)
1614 return emulate_gp(ctxt, 0);
38ba30ba 1615
9dac77fa 1616 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1617
dde7e6d1
AK		 1618 if (rc != X86EMUL_CONTINUE)
1619 return rc;
38ba30ba 1620
9dac77fa 1621 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1622
dde7e6d1
AK		 1623 if (rc != X86EMUL_CONTINUE)
1624 return rc;
38ba30ba 1625
7b105ca2 1626 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1627
dde7e6d1
AK		 1628 if (rc != X86EMUL_CONTINUE)
1629 return rc;
38ba30ba 1630
9dac77fa 1631 ctxt->_eip = temp_eip;
38ba30ba 1632
38ba30ba 1633
9dac77fa 1634 if (ctxt->op_bytes == 4)
dde7e6d1 1635 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1636 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1637 ctxt->eflags &= ~0xffff;
1638 ctxt->eflags |= temp_eflags;
38ba30ba 1639 }
dde7e6d1
AK		 1640
1641 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1642 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1643
1644 return rc;
38ba30ba
GN		 1645}
1646
e01991e7 1647static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1648{
dde7e6d1
AK		 1649 switch(ctxt->mode) {
1650 case X86EMUL_MODE_REAL:
7b105ca2 1651 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1652 case X86EMUL_MODE_VM86:
1653 case X86EMUL_MODE_PROT16:
1654 case X86EMUL_MODE_PROT32:
1655 case X86EMUL_MODE_PROT64:
c37eda13 1656 default:
dde7e6d1
AK		 1657 /* iret from protected mode unimplemented yet */
1658 return X86EMUL_UNHANDLEABLE;
c37eda13 1659 }
c37eda13
WY		 1660}
1661
d2f62766
TY		 1662static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1663{
d2f62766
TY		 1664 int rc;
1665 unsigned short sel;
1666
9dac77fa 1667 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1668
7b105ca2 1669 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1670 if (rc != X86EMUL_CONTINUE)
1671 return rc;
1672
9dac77fa
AK		 1673 ctxt->_eip = 0;
1674 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1675 return X86EMUL_CONTINUE;
1676}
1677
51187683 1678static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1679{
9dac77fa 1680 switch (ctxt->modrm_reg) {
8cdbd2c9 1681 case 0: /* rol */
a31b9cea 1682 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1683 break;
1684 case 1: /* ror */
a31b9cea 1685 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1686 break;
1687 case 2: /* rcl */
a31b9cea 1688 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1689 break;
1690 case 3: /* rcr */
a31b9cea 1691 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1692 break;
1693 case 4: /* sal/shl */
1694 case 6: /* sal/shl */
a31b9cea 1695 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1696 break;
1697 case 5: /* shr */
a31b9cea 1698 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1699 break;
1700 case 7: /* sar */
a31b9cea 1701 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1702 break;
1703 }
51187683 1704 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1705}
1706
3329ece1
AK		 1707static int em_not(struct x86_emulate_ctxt *ctxt)
1708{
1709 ctxt->dst.val = ~ctxt->dst.val;
1710 return X86EMUL_CONTINUE;
1711}
1712
1713static int em_neg(struct x86_emulate_ctxt *ctxt)
1714{
1715 emulate_1op(ctxt, "neg");
1716 return X86EMUL_CONTINUE;
1717}
1718
1719static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1720{
1721 u8 ex = 0;
1722
1723 emulate_1op_rax_rdx(ctxt, "mul", ex);
1724 return X86EMUL_CONTINUE;
1725}
1726
1727static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1728{
1729 u8 ex = 0;
1730
1731 emulate_1op_rax_rdx(ctxt, "imul", ex);
1732 return X86EMUL_CONTINUE;
1733}
1734
1735static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1736{
34d1f490 1737 u8 de = 0;
8cdbd2c9 1738
3329ece1
AK		 1739 emulate_1op_rax_rdx(ctxt, "div", de);
1740 if (de)
1741 return emulate_de(ctxt);
1742 return X86EMUL_CONTINUE;
1743}
1744
1745static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1746{
1747 u8 de = 0;
1748
1749 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1750 if (de)
1751 return emulate_de(ctxt);
8c5eee30 1752 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1753}
1754
51187683 1755static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1756{
4179bb02 1757 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1758
9dac77fa 1759 switch (ctxt->modrm_reg) {
8cdbd2c9 1760 case 0: /* inc */
d1eef45d 1761 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1762 break;
1763 case 1: /* dec */
d1eef45d 1764 emulate_1op(ctxt, "dec");
8cdbd2c9 1765 break;
d19292e4
MG		 1766 case 2: /* call near abs */ {
1767 long int old_eip;
9dac77fa
AK		 1768 old_eip = ctxt->_eip;
1769 ctxt->_eip = ctxt->src.val;
1770 ctxt->src.val = old_eip;
4487b3b4 1771 rc = em_push(ctxt);
d19292e4
MG		 1772 break;
1773 }
8cdbd2c9 1774 case 4: /* jmp abs */
9dac77fa 1775 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1776 break;
d2f62766
TY		 1777 case 5: /* jmp far */
1778 rc = em_jmp_far(ctxt);
1779 break;
8cdbd2c9 1780 case 6: /* push */
4487b3b4 1781 rc = em_push(ctxt);
8cdbd2c9 1782 break;
8cdbd2c9 1783 }
4179bb02 1784 return rc;
8cdbd2c9
LV		 1785}
1786
e0dac408 1787static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1788{
9dac77fa 1789 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1790
9dac77fa
AK		 1791 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1792 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1793 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1794 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1795 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1796 } else {
9dac77fa
AK		 1797 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1798 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1799
05f086f8 1800 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1801 }
1b30eaa8 1802 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1803}
1804
ebda02c2
TY		 1805static int em_ret(struct x86_emulate_ctxt *ctxt)
1806{
9dac77fa
AK		 1807 ctxt->dst.type = OP_REG;
1808 ctxt->dst.addr.reg = &ctxt->_eip;
1809 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1810 return em_pop(ctxt);
1811}
1812
e01991e7 1813static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1814{
a77ab5ea
AK		 1815 int rc;
1816 unsigned long cs;
1817
9dac77fa 1818 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1819 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1820 return rc;
9dac77fa
AK		 1821 if (ctxt->op_bytes == 4)
1822 ctxt->_eip = (u32)ctxt->_eip;
1823 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1824 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1825 return rc;
7b105ca2 1826 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1827 return rc;
1828}
1829
e940b5c2
TY		 1830static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1831{
1832 /* Save real source value, then compare EAX against destination. */
1833 ctxt->src.orig_val = ctxt->src.val;
1834 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1835 emulate_2op_SrcV(ctxt, "cmp");
1836
1837 if (ctxt->eflags & EFLG_ZF) {
1838 /* Success: write back to memory. */
1839 ctxt->dst.val = ctxt->src.orig_val;
1840 } else {
1841 /* Failure: write the value we saw to EAX. */
1842 ctxt->dst.type = OP_REG;
1843 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1844 }
1845 return X86EMUL_CONTINUE;
1846}
1847
d4b4325f 1848static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1849{
d4b4325f 1850 int seg = ctxt->src2.val;
09b5f4d3
WY		 1851 unsigned short sel;
1852 int rc;
1853
9dac77fa 1854 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1855
7b105ca2 1856 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1857 if (rc != X86EMUL_CONTINUE)
1858 return rc;
1859
9dac77fa 1860 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1861 return rc;
1862}
1863
7b105ca2 1864static void
e66bb2cc 1865setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1866 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1867{
1aa36616
AK		 1868 u16 selector;
1869
79168fd1 1870 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1871 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1872 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1873
1874 cs->l = 0; /* will be adjusted later */
79168fd1 1875 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1876 cs->g = 1; /* 4kb granularity */
79168fd1 1877 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1878 cs->type = 0x0b; /* Read, Execute, Accessed */
1879 cs->s = 1;
1880 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1881 cs->p = 1;
1882 cs->d = 1;
e66bb2cc 1883
79168fd1
GN		 1884 set_desc_base(ss, 0); /* flat segment */
1885 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1886 ss->g = 1; /* 4kb granularity */
1887 ss->s = 1;
1888 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1889 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1890 ss->dpl = 0;
79168fd1 1891 ss->p = 1;
e66bb2cc
AP		 1892}
1893
e01991e7 1894static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1895{
7b105ca2 1896 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1897 struct desc_struct cs, ss;
e66bb2cc 1898 u64 msr_data;
79168fd1 1899 u16 cs_sel, ss_sel;
c2ad2bb3 1900 u64 efer = 0;
e66bb2cc
AP		 1901
1902 /* syscall is not available in real mode */
2e901c4c 1903 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1904 ctxt->mode == X86EMUL_MODE_VM86)
1905 return emulate_ud(ctxt);
e66bb2cc 1906
c2ad2bb3 1907 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1908 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1909
717746e3 1910 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1911 msr_data >>= 32;
79168fd1
GN		 1912 cs_sel = (u16)(msr_data & 0xfffc);
1913 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1914
c2ad2bb3 1915 if (efer & EFER_LMA) {
79168fd1 1916 cs.d = 0;
e66bb2cc
AP		 1917 cs.l = 1;
1918 }
1aa36616
AK		 1919 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1920 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1921
9dac77fa 1922 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1923 if (efer & EFER_LMA) {
e66bb2cc 1924#ifdef CONFIG_X86_64
9dac77fa 1925 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1926
717746e3 1927 ops->get_msr(ctxt,
3fb1b5db
GN		 1928 ctxt->mode == X86EMUL_MODE_PROT64 ?
1929 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1930 ctxt->_eip = msr_data;
e66bb2cc 1931
717746e3 1932 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1933 ctxt->eflags &= ~(msr_data | EFLG_RF);
1934#endif
1935 } else {
1936 /* legacy mode */
717746e3 1937 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1938 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1939
1940 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1941 }
1942
e54cfa97 1943 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1944}
1945
e01991e7 1946static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1947{
7b105ca2 1948 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1949 struct desc_struct cs, ss;
8c604352 1950 u64 msr_data;
79168fd1 1951 u16 cs_sel, ss_sel;
c2ad2bb3 1952 u64 efer = 0;
8c604352 1953
7b105ca2 1954 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1955 /* inject #GP if in real mode */
35d3d4a1
AK		 1956 if (ctxt->mode == X86EMUL_MODE_REAL)
1957 return emulate_gp(ctxt, 0);
8c604352
AP		 1958
1959 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1960 * Therefore, we inject an #UD.
1961 */
35d3d4a1
AK		 1962 if (ctxt->mode == X86EMUL_MODE_PROT64)
1963 return emulate_ud(ctxt);
8c604352 1964
7b105ca2 1965 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1966
717746e3 1967 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1968 switch (ctxt->mode) {
1969 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1970 if ((msr_data & 0xfffc) == 0x0)
1971 return emulate_gp(ctxt, 0);
8c604352
AP		 1972 break;
1973 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1974 if (msr_data == 0x0)
1975 return emulate_gp(ctxt, 0);
8c604352
AP		 1976 break;
1977 }
1978
1979 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1980 cs_sel = (u16)msr_data;
1981 cs_sel &= ~SELECTOR_RPL_MASK;
1982 ss_sel = cs_sel + 8;
1983 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1984 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1985 cs.d = 0;
8c604352
AP		 1986 cs.l = 1;
1987 }
1988
1aa36616
AK		 1989 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1990 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1991
717746e3 1992 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1993 ctxt->_eip = msr_data;
8c604352 1994
717746e3 1995 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1996 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1997
e54cfa97 1998 return X86EMUL_CONTINUE;
8c604352
AP		 1999}
2000
e01991e7 2001static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2002{
7b105ca2 2003 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2004 struct desc_struct cs, ss;
4668f050
AP		 2005 u64 msr_data;
2006 int usermode;
1249b96e 2007 u16 cs_sel = 0, ss_sel = 0;
4668f050 2008
a0044755
GN		 2009 /* inject #GP if in real mode or Virtual 8086 mode */
2010 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2011 ctxt->mode == X86EMUL_MODE_VM86)
2012 return emulate_gp(ctxt, 0);
4668f050 2013
7b105ca2 2014 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2015
9dac77fa 2016 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2017 usermode = X86EMUL_MODE_PROT64;
2018 else
2019 usermode = X86EMUL_MODE_PROT32;
2020
2021 cs.dpl = 3;
2022 ss.dpl = 3;
717746e3 2023 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2024 switch (usermode) {
2025 case X86EMUL_MODE_PROT32:
79168fd1 2026 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2027 if ((msr_data & 0xfffc) == 0x0)
2028 return emulate_gp(ctxt, 0);
79168fd1 2029 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2030 break;
2031 case X86EMUL_MODE_PROT64:
79168fd1 2032 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2033 if (msr_data == 0x0)
2034 return emulate_gp(ctxt, 0);
79168fd1
GN		 2035 ss_sel = cs_sel + 8;
2036 cs.d = 0;
4668f050
AP		 2037 cs.l = 1;
2038 break;
2039 }
79168fd1
GN		 2040 cs_sel |= SELECTOR_RPL_MASK;
2041 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2042
1aa36616
AK		 2043 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2044 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2045
9dac77fa
AK		 2046 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2047 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2048
e54cfa97 2049 return X86EMUL_CONTINUE;
4668f050
AP		 2050}
2051
7b105ca2 2052static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2053{
2054 int iopl;
2055 if (ctxt->mode == X86EMUL_MODE_REAL)
2056 return false;
2057 if (ctxt->mode == X86EMUL_MODE_VM86)
2058 return true;
2059 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2060 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2061}
2062
2063static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2064 u16 port, u16 len)
2065{
7b105ca2 2066 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2067 struct desc_struct tr_seg;
5601d05b 2068 u32 base3;
f850e2e6 2069 int r;
1aa36616 2070 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2071 unsigned mask = (1 << len) - 1;
5601d05b 2072 unsigned long base;
f850e2e6 2073
1aa36616 2074 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2075 if (!tr_seg.p)
f850e2e6 2076 return false;
79168fd1 2077 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2078 return false;
5601d05b
GN		 2079 base = get_desc_base(&tr_seg);
2080#ifdef CONFIG_X86_64
2081 base |= ((u64)base3) << 32;
2082#endif
0f65dd70 2083 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2084 if (r != X86EMUL_CONTINUE)
2085 return false;
79168fd1 2086 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2087 return false;
0f65dd70 2088 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2089 if (r != X86EMUL_CONTINUE)
2090 return false;
2091 if ((perm >> bit_idx) & mask)
2092 return false;
2093 return true;
2094}
2095
2096static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2097 u16 port, u16 len)
2098{
4fc40f07
GN		 2099 if (ctxt->perm_ok)
2100 return true;
2101
7b105ca2
TY		 2102 if (emulator_bad_iopl(ctxt))
2103 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2104 return false;
4fc40f07
GN		 2105
2106 ctxt->perm_ok = true;
2107
f850e2e6
GN		 2108 return true;
2109}
2110
38ba30ba 2111static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2112 struct tss_segment_16 *tss)
2113{
9dac77fa 2114 tss->ip = ctxt->_eip;
38ba30ba 2115 tss->flag = ctxt->eflags;
9dac77fa
AK		 2116 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2117 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2118 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2119 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2120 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2121 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2122 tss->si = ctxt->regs[VCPU_REGS_RSI];
2123 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2124
1aa36616
AK		 2125 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2126 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2127 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2128 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2129 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2130}
2131
2132static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2133 struct tss_segment_16 *tss)
2134{
38ba30ba
GN		 2135 int ret;
2136
9dac77fa 2137 ctxt->_eip = tss->ip;
38ba30ba 2138 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2139 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2140 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2141 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2142 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2143 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2144 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2145 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2146 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2147
2148 /*
2149 * SDM says that segment selectors are loaded before segment
2150 * descriptors
2151 */
1aa36616
AK		 2152 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2153 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2154 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2155 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2156 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2157
2158 /*
2159 * Now load segment descriptors. If fault happenes at this stage
2160 * it is handled in a context of new task
2161 */
7b105ca2 2162 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2163 if (ret != X86EMUL_CONTINUE)
2164 return ret;
7b105ca2 2165 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2166 if (ret != X86EMUL_CONTINUE)
2167 return ret;
7b105ca2 2168 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2169 if (ret != X86EMUL_CONTINUE)
2170 return ret;
7b105ca2 2171 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2172 if (ret != X86EMUL_CONTINUE)
2173 return ret;
7b105ca2 2174 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2175 if (ret != X86EMUL_CONTINUE)
2176 return ret;
2177
2178 return X86EMUL_CONTINUE;
2179}
2180
2181static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2182 u16 tss_selector, u16 old_tss_sel,
2183 ulong old_tss_base, struct desc_struct *new_desc)
2184{
7b105ca2 2185 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2186 struct tss_segment_16 tss_seg;
2187 int ret;
bcc55cba 2188 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2189
0f65dd70 2190 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2191 &ctxt->exception);
db297e3d 2192 if (ret != X86EMUL_CONTINUE)
38ba30ba 2193 /* FIXME: need to provide precise fault address */
38ba30ba 2194 return ret;
38ba30ba 2195
7b105ca2 2196 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2197
0f65dd70 2198 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2199 &ctxt->exception);
db297e3d 2200 if (ret != X86EMUL_CONTINUE)
38ba30ba 2201 /* FIXME: need to provide precise fault address */
38ba30ba 2202 return ret;
38ba30ba 2203
0f65dd70 2204 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2205 &ctxt->exception);
db297e3d 2206 if (ret != X86EMUL_CONTINUE)
38ba30ba 2207 /* FIXME: need to provide precise fault address */
38ba30ba 2208 return ret;
38ba30ba
GN		 2209
2210 if (old_tss_sel != 0xffff) {
2211 tss_seg.prev_task_link = old_tss_sel;
2212
0f65dd70 2213 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2214 &tss_seg.prev_task_link,
2215 sizeof tss_seg.prev_task_link,
0f65dd70 2216 &ctxt->exception);
db297e3d 2217 if (ret != X86EMUL_CONTINUE)
38ba30ba 2218 /* FIXME: need to provide precise fault address */
38ba30ba 2219 return ret;
38ba30ba
GN		 2220 }
2221
7b105ca2 2222 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2223}
2224
2225static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2226 struct tss_segment_32 *tss)
2227{
7b105ca2 2228 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2229 tss->eip = ctxt->_eip;
38ba30ba 2230 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2231 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2232 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2233 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2234 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2235 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2236 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2237 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2238 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2239
1aa36616
AK		 2240 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2241 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2242 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2243 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2244 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2245 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2246 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2247}
2248
2249static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2250 struct tss_segment_32 *tss)
2251{
38ba30ba
GN		 2252 int ret;
2253
7b105ca2 2254 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2255 return emulate_gp(ctxt, 0);
9dac77fa 2256 ctxt->_eip = tss->eip;
38ba30ba 2257 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2258 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2259 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2260 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2261 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2262 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2263 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2264 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2265 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2266
2267 /*
2268 * SDM says that segment selectors are loaded before segment
2269 * descriptors
2270 */
1aa36616
AK		 2271 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2272 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2273 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2274 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2275 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2276 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2277 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2278
2279 /*
2280 * Now load segment descriptors. If fault happenes at this stage
2281 * it is handled in a context of new task
2282 */
7b105ca2 2283 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2284 if (ret != X86EMUL_CONTINUE)
2285 return ret;
7b105ca2 2286 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2287 if (ret != X86EMUL_CONTINUE)
2288 return ret;
7b105ca2 2289 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2290 if (ret != X86EMUL_CONTINUE)
2291 return ret;
7b105ca2 2292 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2293 if (ret != X86EMUL_CONTINUE)
2294 return ret;
7b105ca2 2295 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2296 if (ret != X86EMUL_CONTINUE)
2297 return ret;
7b105ca2 2298 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2299 if (ret != X86EMUL_CONTINUE)
2300 return ret;
7b105ca2 2301 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2302 if (ret != X86EMUL_CONTINUE)
2303 return ret;
2304
2305 return X86EMUL_CONTINUE;
2306}
2307
2308static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2309 u16 tss_selector, u16 old_tss_sel,
2310 ulong old_tss_base, struct desc_struct *new_desc)
2311{
7b105ca2 2312 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2313 struct tss_segment_32 tss_seg;
2314 int ret;
bcc55cba 2315 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2316
0f65dd70 2317 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2318 &ctxt->exception);
db297e3d 2319 if (ret != X86EMUL_CONTINUE)
38ba30ba 2320 /* FIXME: need to provide precise fault address */
38ba30ba 2321 return ret;
38ba30ba 2322
7b105ca2 2323 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2324
0f65dd70 2325 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2326 &ctxt->exception);
db297e3d 2327 if (ret != X86EMUL_CONTINUE)
38ba30ba 2328 /* FIXME: need to provide precise fault address */
38ba30ba 2329 return ret;
38ba30ba 2330
0f65dd70 2331 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2332 &ctxt->exception);
db297e3d 2333 if (ret != X86EMUL_CONTINUE)
38ba30ba 2334 /* FIXME: need to provide precise fault address */
38ba30ba 2335 return ret;
38ba30ba
GN		 2336
2337 if (old_tss_sel != 0xffff) {
2338 tss_seg.prev_task_link = old_tss_sel;
2339
0f65dd70 2340 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2341 &tss_seg.prev_task_link,
2342 sizeof tss_seg.prev_task_link,
0f65dd70 2343 &ctxt->exception);
db297e3d 2344 if (ret != X86EMUL_CONTINUE)
38ba30ba 2345 /* FIXME: need to provide precise fault address */
38ba30ba 2346 return ret;
38ba30ba
GN		 2347 }
2348
7b105ca2 2349 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2350}
2351
2352static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2353 u16 tss_selector, int reason,
2354 bool has_error_code, u32 error_code)
38ba30ba 2355{
7b105ca2 2356 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2357 struct desc_struct curr_tss_desc, next_tss_desc;
2358 int ret;
1aa36616 2359 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2360 ulong old_tss_base =
4bff1e86 2361 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2362 u32 desc_limit;
38ba30ba
GN		 2363
2364 /* FIXME: old_tss_base == ~0 ? */
2365
7b105ca2 2366 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2367 if (ret != X86EMUL_CONTINUE)
2368 return ret;
7b105ca2 2369 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2370 if (ret != X86EMUL_CONTINUE)
2371 return ret;
2372
2373 /* FIXME: check that next_tss_desc is tss */
2374
2375 if (reason != TASK_SWITCH_IRET) {
2376 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2377 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2378 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2379 }
2380
ceffb459
GN		 2381 desc_limit = desc_limit_scaled(&next_tss_desc);
2382 if (!next_tss_desc.p ||
2383 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2384 desc_limit < 0x2b)) {
54b8486f 2385 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2386 return X86EMUL_PROPAGATE_FAULT;
2387 }
2388
2389 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2390 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2391 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2392 }
2393
2394 if (reason == TASK_SWITCH_IRET)
2395 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2396
2397 /* set back link to prev task only if NT bit is set in eflags
2398 note that old_tss_sel is not used afetr this point */
2399 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2400 old_tss_sel = 0xffff;
2401
2402 if (next_tss_desc.type & 8)
7b105ca2 2403 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2404 old_tss_base, &next_tss_desc);
2405 else
7b105ca2 2406 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2407 old_tss_base, &next_tss_desc);
0760d448
JK		 2408 if (ret != X86EMUL_CONTINUE)
2409 return ret;
38ba30ba
GN		 2410
2411 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2412 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2413
2414 if (reason != TASK_SWITCH_IRET) {
2415 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2416 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2417 }
2418
717746e3 2419 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2420 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2421
e269fb21 2422 if (has_error_code) {
9dac77fa
AK		 2423 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2424 ctxt->lock_prefix = 0;
2425 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2426 ret = em_push(ctxt);
e269fb21
JK		 2427 }
2428
38ba30ba
GN		 2429 return ret;
2430}
2431
2432int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2433 u16 tss_selector, int reason,
2434 bool has_error_code, u32 error_code)
38ba30ba 2435{
38ba30ba
GN		 2436 int rc;
2437
9dac77fa
AK		 2438 ctxt->_eip = ctxt->eip;
2439 ctxt->dst.type = OP_NONE;
38ba30ba 2440
7b105ca2 2441 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2442 has_error_code, error_code);
38ba30ba 2443
4179bb02 2444 if (rc == X86EMUL_CONTINUE)
9dac77fa 2445 ctxt->eip = ctxt->_eip;
38ba30ba 2446
a0c0ab2f 2447 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2448}
2449
90de84f5 2450static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2451 int reg, struct operand *op)
a682e354 2452{
a682e354
GN		 2453 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2454
9dac77fa
AK		 2455 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2456 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2457 op->addr.mem.seg = seg;
a682e354
GN		 2458}
2459
7af04fc0
AK		 2460static int em_das(struct x86_emulate_ctxt *ctxt)
2461{
7af04fc0
AK		 2462 u8 al, old_al;
2463 bool af, cf, old_cf;
2464
2465 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2466 al = ctxt->dst.val;
7af04fc0
AK		 2467
2468 old_al = al;
2469 old_cf = cf;
2470 cf = false;
2471 af = ctxt->eflags & X86_EFLAGS_AF;
2472 if ((al & 0x0f) > 9 || af) {
2473 al -= 6;
2474 cf = old_cf | (al >= 250);
2475 af = true;
2476 } else {
2477 af = false;
2478 }
2479 if (old_al > 0x99 || old_cf) {
2480 al -= 0x60;
2481 cf = true;
2482 }
2483
9dac77fa 2484 ctxt->dst.val = al;
7af04fc0 2485 /* Set PF, ZF, SF */
9dac77fa
AK		 2486 ctxt->src.type = OP_IMM;
2487 ctxt->src.val = 0;
2488 ctxt->src.bytes = 1;
a31b9cea 2489 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2490 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2491 if (cf)
2492 ctxt->eflags |= X86_EFLAGS_CF;
2493 if (af)
2494 ctxt->eflags |= X86_EFLAGS_AF;
2495 return X86EMUL_CONTINUE;
2496}
2497
d4ddafcd
TY		 2498static int em_call(struct x86_emulate_ctxt *ctxt)
2499{
2500 long rel = ctxt->src.val;
2501
2502 ctxt->src.val = (unsigned long)ctxt->_eip;
2503 jmp_rel(ctxt, rel);
2504 return em_push(ctxt);
2505}
2506
0ef753b8
AK		 2507static int em_call_far(struct x86_emulate_ctxt *ctxt)
2508{
0ef753b8
AK		 2509 u16 sel, old_cs;
2510 ulong old_eip;
2511 int rc;
2512
1aa36616 2513 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2514 old_eip = ctxt->_eip;
0ef753b8 2515
9dac77fa 2516 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2517 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2518 return X86EMUL_CONTINUE;
2519
9dac77fa
AK		 2520 ctxt->_eip = 0;
2521 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2522
9dac77fa 2523 ctxt->src.val = old_cs;
4487b3b4 2524 rc = em_push(ctxt);
0ef753b8
AK		 2525 if (rc != X86EMUL_CONTINUE)
2526 return rc;
2527
9dac77fa 2528 ctxt->src.val = old_eip;
4487b3b4 2529 return em_push(ctxt);
0ef753b8
AK		 2530}
2531
40ece7c7
AK		 2532static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2533{
40ece7c7
AK		 2534 int rc;
2535
9dac77fa
AK		 2536 ctxt->dst.type = OP_REG;
2537 ctxt->dst.addr.reg = &ctxt->_eip;
2538 ctxt->dst.bytes = ctxt->op_bytes;
2539 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2540 if (rc != X86EMUL_CONTINUE)
2541 return rc;
9dac77fa 2542 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2543 return X86EMUL_CONTINUE;
2544}
2545
d67fc27a
TY		 2546static int em_add(struct x86_emulate_ctxt *ctxt)
2547{
a31b9cea 2548 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2549 return X86EMUL_CONTINUE;
2550}
2551
2552static int em_or(struct x86_emulate_ctxt *ctxt)
2553{
a31b9cea 2554 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2555 return X86EMUL_CONTINUE;
2556}
2557
2558static int em_adc(struct x86_emulate_ctxt *ctxt)
2559{
a31b9cea 2560 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2561 return X86EMUL_CONTINUE;
2562}
2563
2564static int em_sbb(struct x86_emulate_ctxt *ctxt)
2565{
a31b9cea 2566 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2567 return X86EMUL_CONTINUE;
2568}
2569
2570static int em_and(struct x86_emulate_ctxt *ctxt)
2571{
a31b9cea 2572 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2573 return X86EMUL_CONTINUE;
2574}
2575
2576static int em_sub(struct x86_emulate_ctxt *ctxt)
2577{
a31b9cea 2578 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2579 return X86EMUL_CONTINUE;
2580}
2581
2582static int em_xor(struct x86_emulate_ctxt *ctxt)
2583{
a31b9cea 2584 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2585 return X86EMUL_CONTINUE;
2586}
2587
2588static int em_cmp(struct x86_emulate_ctxt *ctxt)
2589{
a31b9cea 2590 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2591 /* Disable writeback. */
9dac77fa 2592 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2593 return X86EMUL_CONTINUE;
2594}
2595
9f21ca59
TY		 2596static int em_test(struct x86_emulate_ctxt *ctxt)
2597{
a31b9cea 2598 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2599 /* Disable writeback. */
2600 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2601 return X86EMUL_CONTINUE;
2602}
2603
e4f973ae
TY		 2604static int em_xchg(struct x86_emulate_ctxt *ctxt)
2605{
e4f973ae 2606 /* Write back the register source. */
9dac77fa
AK		 2607 ctxt->src.val = ctxt->dst.val;
2608 write_register_operand(&ctxt->src);
e4f973ae
TY		 2609
2610 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2611 ctxt->dst.val = ctxt->src.orig_val;
2612 ctxt->lock_prefix = 1;
e4f973ae
TY		 2613 return X86EMUL_CONTINUE;
2614}
2615
5c82aa29 2616static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2617{
a31b9cea 2618 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2619 return X86EMUL_CONTINUE;
2620}
2621
5c82aa29
AK		 2622static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2623{
9dac77fa 2624 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2625 return em_imul(ctxt);
2626}
2627
61429142
AK		 2628static int em_cwd(struct x86_emulate_ctxt *ctxt)
2629{
9dac77fa
AK		 2630 ctxt->dst.type = OP_REG;
2631 ctxt->dst.bytes = ctxt->src.bytes;
2632 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2633 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2634
2635 return X86EMUL_CONTINUE;
2636}
2637
48bb5d3c
AK		 2638static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2639{
48bb5d3c
AK		 2640 u64 tsc = 0;
2641
717746e3 2642 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2643 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2644 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2645 return X86EMUL_CONTINUE;
2646}
2647
b9eac5f4
AK		 2648static int em_mov(struct x86_emulate_ctxt *ctxt)
2649{
9dac77fa 2650 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2651 return X86EMUL_CONTINUE;
2652}
2653
bc00f8d2
TY		 2654static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2655{
2656 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2657 return emulate_gp(ctxt, 0);
2658
2659 /* Disable writeback. */
2660 ctxt->dst.type = OP_NONE;
2661 return X86EMUL_CONTINUE;
2662}
2663
2664static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2665{
2666 unsigned long val;
2667
2668 if (ctxt->mode == X86EMUL_MODE_PROT64)
2669 val = ctxt->src.val & ~0ULL;
2670 else
2671 val = ctxt->src.val & ~0U;
2672
2673 /* #UD condition is already handled. */
2674 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2675 return emulate_gp(ctxt, 0);
2676
2677 /* Disable writeback. */
2678 ctxt->dst.type = OP_NONE;
2679 return X86EMUL_CONTINUE;
2680}
2681
e1e210b0
TY		 2682static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2683{
2684 u64 msr_data;
2685
2686 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2687 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2688 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2689 return emulate_gp(ctxt, 0);
2690
2691 return X86EMUL_CONTINUE;
2692}
2693
2694static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2695{
2696 u64 msr_data;
2697
2698 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2699 return emulate_gp(ctxt, 0);
2700
2701 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2702 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2703 return X86EMUL_CONTINUE;
2704}
2705
1bd5f469
TY		 2706static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2707{
9dac77fa 2708 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2709 return emulate_ud(ctxt);
2710
9dac77fa 2711 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2712 return X86EMUL_CONTINUE;
2713}
2714
2715static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2716{
9dac77fa 2717 u16 sel = ctxt->src.val;
1bd5f469 2718
9dac77fa 2719 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2720 return emulate_ud(ctxt);
2721
9dac77fa 2722 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2723 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2724
2725 /* Disable writeback. */
9dac77fa
AK		 2726 ctxt->dst.type = OP_NONE;
2727 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2728}
2729
aa97bb48
AK		 2730static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2731{
9dac77fa 2732 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2733 return X86EMUL_CONTINUE;
2734}
2735
38503911
AK		 2736static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2737{
9fa088f4
AK		 2738 int rc;
2739 ulong linear;
2740
9dac77fa 2741 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2742 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2743 ctxt->ops->invlpg(ctxt, linear);
38503911 2744 /* Disable writeback. */
9dac77fa 2745 ctxt->dst.type = OP_NONE;
38503911
AK		 2746 return X86EMUL_CONTINUE;
2747}
2748
2d04a05b
AK		 2749static int em_clts(struct x86_emulate_ctxt *ctxt)
2750{
2751 ulong cr0;
2752
2753 cr0 = ctxt->ops->get_cr(ctxt, 0);
2754 cr0 &= ~X86_CR0_TS;
2755 ctxt->ops->set_cr(ctxt, 0, cr0);
2756 return X86EMUL_CONTINUE;
2757}
2758
26d05cc7
AK		 2759static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2760{
26d05cc7
AK		 2761 int rc;
2762
9dac77fa 2763 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2764 return X86EMUL_UNHANDLEABLE;
2765
2766 rc = ctxt->ops->fix_hypercall(ctxt);
2767 if (rc != X86EMUL_CONTINUE)
2768 return rc;
2769
2770 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2771 ctxt->_eip = ctxt->eip;
26d05cc7 2772 /* Disable writeback. */
9dac77fa 2773 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2774 return X86EMUL_CONTINUE;
2775}
2776
2777static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2778{
26d05cc7
AK		 2779 struct desc_ptr desc_ptr;
2780 int rc;
2781
9dac77fa 2782 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2783 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2784 ctxt->op_bytes);
26d05cc7
AK		 2785 if (rc != X86EMUL_CONTINUE)
2786 return rc;
2787 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2788 /* Disable writeback. */
9dac77fa 2789 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2790 return X86EMUL_CONTINUE;
2791}
2792
5ef39c71 2793static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2794{
26d05cc7
AK		 2795 int rc;
2796
5ef39c71
AK		 2797 rc = ctxt->ops->fix_hypercall(ctxt);
2798
26d05cc7 2799 /* Disable writeback. */
9dac77fa 2800 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2801 return rc;
2802}
2803
2804static int em_lidt(struct x86_emulate_ctxt *ctxt)
2805{
26d05cc7
AK		 2806 struct desc_ptr desc_ptr;
2807 int rc;
2808
9dac77fa 2809 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2810 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2811 ctxt->op_bytes);
26d05cc7
AK		 2812 if (rc != X86EMUL_CONTINUE)
2813 return rc;
2814 ctxt->ops->set_idt(ctxt, &desc_ptr);
2815 /* Disable writeback. */
9dac77fa 2816 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2817 return X86EMUL_CONTINUE;
2818}
2819
2820static int em_smsw(struct x86_emulate_ctxt *ctxt)
2821{
9dac77fa
AK		 2822 ctxt->dst.bytes = 2;
2823 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2824 return X86EMUL_CONTINUE;
2825}
2826
2827static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2828{
26d05cc7 2829 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2830 | (ctxt->src.val & 0x0f));
2831 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2832 return X86EMUL_CONTINUE;
2833}
2834
d06e03ad
TY		 2835static int em_loop(struct x86_emulate_ctxt *ctxt)
2836{
9dac77fa
AK		 2837 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2838 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2839 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2840 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2841
2842 return X86EMUL_CONTINUE;
2843}
2844
2845static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2846{
9dac77fa
AK		 2847 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2848 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2849
2850 return X86EMUL_CONTINUE;
2851}
2852
d7841a4b
TY		 2853static int em_in(struct x86_emulate_ctxt *ctxt)
2854{
2855 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
2856 &ctxt->dst.val))
2857 return X86EMUL_IO_NEEDED;
2858
2859 return X86EMUL_CONTINUE;
2860}
2861
2862static int em_out(struct x86_emulate_ctxt *ctxt)
2863{
2864 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
2865 &ctxt->src.val, 1);
2866 /* Disable writeback. */
2867 ctxt->dst.type = OP_NONE;
2868 return X86EMUL_CONTINUE;
2869}
2870
f411e6cd
TY		 2871static int em_cli(struct x86_emulate_ctxt *ctxt)
2872{
2873 if (emulator_bad_iopl(ctxt))
2874 return emulate_gp(ctxt, 0);
2875
2876 ctxt->eflags &= ~X86_EFLAGS_IF;
2877 return X86EMUL_CONTINUE;
2878}
2879
2880static int em_sti(struct x86_emulate_ctxt *ctxt)
2881{
2882 if (emulator_bad_iopl(ctxt))
2883 return emulate_gp(ctxt, 0);
2884
2885 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2886 ctxt->eflags |= X86_EFLAGS_IF;
2887 return X86EMUL_CONTINUE;
2888}
2889
ce7faab2
TY		 2890static int em_bt(struct x86_emulate_ctxt *ctxt)
2891{
2892 /* Disable writeback. */
2893 ctxt->dst.type = OP_NONE;
2894 /* only subword offset */
2895 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
2896
2897 emulate_2op_SrcV_nobyte(ctxt, "bt");
2898 return X86EMUL_CONTINUE;
2899}
2900
2901static int em_bts(struct x86_emulate_ctxt *ctxt)
2902{
2903 emulate_2op_SrcV_nobyte(ctxt, "bts");
2904 return X86EMUL_CONTINUE;
2905}
2906
2907static int em_btr(struct x86_emulate_ctxt *ctxt)
2908{
2909 emulate_2op_SrcV_nobyte(ctxt, "btr");
2910 return X86EMUL_CONTINUE;
2911}
2912
2913static int em_btc(struct x86_emulate_ctxt *ctxt)
2914{
2915 emulate_2op_SrcV_nobyte(ctxt, "btc");
2916 return X86EMUL_CONTINUE;
2917}
2918
ff227392
TY		 2919static int em_bsf(struct x86_emulate_ctxt *ctxt)
2920{
2921 u8 zf;
2922
2923 __asm__ ("bsf %2, %0; setz %1"
2924 : "=r"(ctxt->dst.val), "=q"(zf)
2925 : "r"(ctxt->src.val));
2926
2927 ctxt->eflags &= ~X86_EFLAGS_ZF;
2928 if (zf) {
2929 ctxt->eflags |= X86_EFLAGS_ZF;
2930 /* Disable writeback. */
2931 ctxt->dst.type = OP_NONE;
2932 }
2933 return X86EMUL_CONTINUE;
2934}
2935
2936static int em_bsr(struct x86_emulate_ctxt *ctxt)
2937{
2938 u8 zf;
2939
2940 __asm__ ("bsr %2, %0; setz %1"
2941 : "=r"(ctxt->dst.val), "=q"(zf)
2942 : "r"(ctxt->src.val));
2943
2944 ctxt->eflags &= ~X86_EFLAGS_ZF;
2945 if (zf) {
2946 ctxt->eflags |= X86_EFLAGS_ZF;
2947 /* Disable writeback. */
2948 ctxt->dst.type = OP_NONE;
2949 }
2950 return X86EMUL_CONTINUE;
2951}
2952
cfec82cb
JR		 2953static bool valid_cr(int nr)
2954{
2955 switch (nr) {
2956 case 0:
2957 case 2 ... 4:
2958 case 8:
2959 return true;
2960 default:
2961 return false;
2962 }
2963}
2964
2965static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2966{
9dac77fa 2967 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2968 return emulate_ud(ctxt);
2969
2970 return X86EMUL_CONTINUE;
2971}
2972
2973static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2974{
9dac77fa
AK		 2975 u64 new_val = ctxt->src.val64;
2976 int cr = ctxt->modrm_reg;
c2ad2bb3 2977 u64 efer = 0;
cfec82cb
JR		 2978
2979 static u64 cr_reserved_bits[] = {
2980 0xffffffff00000000ULL,
2981 0, 0, 0, /* CR3 checked later */
2982 CR4_RESERVED_BITS,
2983 0, 0, 0,
2984 CR8_RESERVED_BITS,
2985 };
2986
2987 if (!valid_cr(cr))
2988 return emulate_ud(ctxt);
2989
2990 if (new_val & cr_reserved_bits[cr])
2991 return emulate_gp(ctxt, 0);
2992
2993 switch (cr) {
2994 case 0: {
c2ad2bb3 2995 u64 cr4;
cfec82cb
JR		 2996 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2997 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2998 return emulate_gp(ctxt, 0);
2999
717746e3
AK		 3000 cr4 = ctxt->ops->get_cr(ctxt, 4);
3001 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3002
3003 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3004 !(cr4 & X86_CR4_PAE))
3005 return emulate_gp(ctxt, 0);
3006
3007 break;
3008 }
3009 case 3: {
3010 u64 rsvd = 0;
3011
c2ad2bb3
AK		 3012 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3013 if (efer & EFER_LMA)
cfec82cb 3014 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3015 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3016 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3017 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3018 rsvd = CR3_NONPAE_RESERVED_BITS;
3019
3020 if (new_val & rsvd)
3021 return emulate_gp(ctxt, 0);
3022
3023 break;
3024 }
3025 case 4: {
717746e3 3026 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3027
3028 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3029 return emulate_gp(ctxt, 0);
3030
3031 break;
3032 }
3033 }
3034
3035 return X86EMUL_CONTINUE;
3036}
3037
3b88e41a
JR		 3038static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3039{
3040 unsigned long dr7;
3041
717746e3 3042 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3043
3044 /* Check if DR7.Global_Enable is set */
3045 return dr7 & (1 << 13);
3046}
3047
3048static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3049{
9dac77fa 3050 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3051 u64 cr4;
3052
3053 if (dr > 7)
3054 return emulate_ud(ctxt);
3055
717746e3 3056 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3057 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3058 return emulate_ud(ctxt);
3059
3060 if (check_dr7_gd(ctxt))
3061 return emulate_db(ctxt);
3062
3063 return X86EMUL_CONTINUE;
3064}
3065
3066static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3067{
9dac77fa
AK		 3068 u64 new_val = ctxt->src.val64;
3069 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3070
3071 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3072 return emulate_gp(ctxt, 0);
3073
3074 return check_dr_read(ctxt);
3075}
3076
01de8b09
JR		 3077static int check_svme(struct x86_emulate_ctxt *ctxt)
3078{
3079 u64 efer;
3080
717746e3 3081 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3082
3083 if (!(efer & EFER_SVME))
3084 return emulate_ud(ctxt);
3085
3086 return X86EMUL_CONTINUE;
3087}
3088
3089static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3090{
9dac77fa 3091 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3092
3093 /* Valid physical address? */
d4224449 3094 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3095 return emulate_gp(ctxt, 0);
3096
3097 return check_svme(ctxt);
3098}
3099
d7eb8203
JR		 3100static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3101{
717746e3 3102 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3103
717746e3 3104 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3105 return emulate_ud(ctxt);
3106
3107 return X86EMUL_CONTINUE;
3108}
3109
8061252e
JR		 3110static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3111{
717746e3 3112 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3113 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3114
717746e3 3115 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3116 (rcx > 3))
3117 return emulate_gp(ctxt, 0);
3118
3119 return X86EMUL_CONTINUE;
3120}
3121
f6511935
JR		 3122static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3123{
9dac77fa
AK		 3124 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3125 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3126 return emulate_gp(ctxt, 0);
3127
3128 return X86EMUL_CONTINUE;
3129}
3130
3131static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3132{
9dac77fa
AK		 3133 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3134 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3135 return emulate_gp(ctxt, 0);
3136
3137 return X86EMUL_CONTINUE;
3138}
3139
73fba5f4 3140#define D(_y) { .flags = (_y) }
c4f035c6 3141#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3142#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3143 .check_perm = (_p) }
73fba5f4 3144#define N D(0)
01de8b09 3145#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 3146#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3147#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3148#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3149#define II(_f, _e, _i) \
3150 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3151#define IIP(_f, _e, _i, _p) \
3152 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3153 .check_perm = (_p) }
aa97bb48 3154#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3155
8d8f4e9f 3156#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3157#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3158#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3159#define I2bvIP(_f, _e, _i, _p) \
3160 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3161
d67fc27a
TY		 3162#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3163 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3164 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3165
d7eb8203
JR		 3166static struct opcode group7_rm1[] = {
3167 DI(SrcNone | ModRM | Priv, monitor),
3168 DI(SrcNone | ModRM | Priv, mwait),
3169 N, N, N, N, N, N,
3170};
3171
01de8b09
JR		 3172static struct opcode group7_rm3[] = {
3173 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3174 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3175 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3176 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3177 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3178 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3179 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3180 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3181};
6230f7fc 3182
d7eb8203
JR		 3183static struct opcode group7_rm7[] = {
3184 N,
3185 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3186 N, N, N, N, N, N,
3187};
d67fc27a 3188
73fba5f4 3189static struct opcode group1[] = {
d67fc27a 3190 I(Lock, em_add),
d5ae7ce8 3191 I(Lock | PageTable, em_or),
d67fc27a
TY		 3192 I(Lock, em_adc),
3193 I(Lock, em_sbb),
d5ae7ce8 3194 I(Lock | PageTable, em_and),
d67fc27a
TY		 3195 I(Lock, em_sub),
3196 I(Lock, em_xor),
3197 I(0, em_cmp),
73fba5f4
AK		 3198};
3199
3200static struct opcode group1A[] = {
c15af35f 3201 I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3202};
3203
3204static struct opcode group3[] = {
3329ece1
AK		 3205 I(DstMem | SrcImm | ModRM, em_test),
3206 I(DstMem | SrcImm | ModRM, em_test),
3207 I(DstMem | SrcNone | ModRM | Lock, em_not),
3208 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3209 I(SrcMem | ModRM, em_mul_ex),
3210 I(SrcMem | ModRM, em_imul_ex),
3211 I(SrcMem | ModRM, em_div_ex),
3212 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3213};
3214
3215static struct opcode group4[] = {
c04ec839
TY		 3216 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
3217 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
73fba5f4
AK		 3218 N, N, N, N, N, N,
3219};
3220
3221static struct opcode group5[] = {
c04ec839
TY		 3222 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3223 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3224 I(SrcMem | ModRM | Stack, em_grp45),
0ef753b8 3225 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
c04ec839
TY		 3226 I(SrcMem | ModRM | Stack, em_grp45),
3227 I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45),
3228 I(SrcMem | ModRM | Stack, em_grp45), N,
73fba5f4
AK		 3229};
3230
dee6bb70
JR		 3231static struct opcode group6[] = {
3232 DI(ModRM | Prot, sldt),
3233 DI(ModRM | Prot, str),
3234 DI(ModRM | Prot | Priv, lldt),
3235 DI(ModRM | Prot | Priv, ltr),
3236 N, N, N, N,
3237};
3238
73fba5f4 3239static struct group_dual group7 = { {
dee6bb70
JR		 3240 DI(ModRM | Mov | DstMem | Priv, sgdt),
3241 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3242 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3243 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3244 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3245 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3246 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3247}, {
5ef39c71
AK		 3248 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3249 EXT(0, group7_rm1),
01de8b09 3250 N, EXT(0, group7_rm3),
5ef39c71
AK		 3251 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3252 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3253} };
3254
3255static struct opcode group8[] = {
3256 N, N, N, N,
ce7faab2
TY		 3257 I(DstMem | SrcImmByte | ModRM, em_bt),
3258 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts),
3259 I(DstMem | SrcImmByte | ModRM | Lock, em_btr),
3260 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc),
73fba5f4
AK		 3261};
3262
3263static struct group_dual group9 = { {
e0dac408 3264 N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3265}, {
3266 N, N, N, N, N, N, N, N,
3267} };
3268
a4d4a7c1 3269static struct opcode group11[] = {
d5ae7ce8
XG		 3270 I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov),
3271 X7(D(Undefined)),
a4d4a7c1
AK		 3272};
3273
aa97bb48
AK		 3274static struct gprefix pfx_0f_6f_0f_7f = {
3275 N, N, N, I(Sse, em_movdqu),
3276};
3277
73fba5f4
AK		 3278static struct opcode opcode_table[256] = {
3279 /* 0x00 - 0x07 */
d67fc27a 3280 I6ALU(Lock, em_add),
1cd196ea
AK		 3281 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3282 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3283 /* 0x08 - 0x0F */
d5ae7ce8 3284 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3285 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3286 N,
73fba5f4 3287 /* 0x10 - 0x17 */
d67fc27a 3288 I6ALU(Lock, em_adc),
1cd196ea
AK		 3289 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3290 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3291 /* 0x18 - 0x1F */
d67fc27a 3292 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3293 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3294 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3295 /* 0x20 - 0x27 */
d5ae7ce8 3296 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3297 /* 0x28 - 0x2F */
d67fc27a 3298 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3299 /* 0x30 - 0x37 */
d67fc27a 3300 I6ALU(Lock, em_xor), N, N,
73fba5f4 3301 /* 0x38 - 0x3F */
d67fc27a 3302 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3303 /* 0x40 - 0x4F */
3304 X16(D(DstReg)),
3305 /* 0x50 - 0x57 */
63540382 3306 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3307 /* 0x58 - 0x5F */
c54fe504 3308 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3309 /* 0x60 - 0x67 */
b96a7fad
TY		 3310 I(ImplicitOps | Stack | No64, em_pusha),
3311 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3312 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3313 N, N, N, N,
3314 /* 0x68 - 0x6F */
d46164db
AK		 3315 I(SrcImm | Mov | Stack, em_push),
3316 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3317 I(SrcImmByte | Mov | Stack, em_push),
3318 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3319 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3320 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3321 /* 0x70 - 0x7F */
3322 X16(D(SrcImmByte)),
3323 /* 0x80 - 0x87 */
3324 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3325 G(DstMem | SrcImm | ModRM | Group, group1),
3326 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3327 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3328 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3329 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3330 /* 0x88 - 0x8F */
d5ae7ce8 3331 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3332 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3333 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3334 D(ModRM | SrcMem | NoAccess | DstReg),
3335 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3336 G(0, group1A),
73fba5f4 3337 /* 0x90 - 0x97 */
bf608f88 3338 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3339 /* 0x98 - 0x9F */
61429142 3340 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3341 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3342 II(ImplicitOps | Stack, em_pushf, pushf),
3343 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3344 /* 0xA0 - 0xA7 */
b9eac5f4 3345 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3346 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3347 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3348 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3349 /* 0xA8 - 0xAF */
9f21ca59 3350 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3351 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3352 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3353 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3354 /* 0xB0 - 0xB7 */
b9eac5f4 3355 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3356 /* 0xB8 - 0xBF */
b9eac5f4 3357 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3358 /* 0xC0 - 0xC7 */
d2c6c7ad 3359 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3360 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3361 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3362 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3363 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3364 G(ByteOp, group11), G(0, group11),
73fba5f4 3365 /* 0xC8 - 0xCF */
db5b0762 3366 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3367 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3368 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3369 /* 0xD0 - 0xD7 */
d2c6c7ad 3370 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3371 N, N, N, N,
3372 /* 0xD8 - 0xDF */
3373 N, N, N, N, N, N, N, N,
3374 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3375 X3(I(SrcImmByte, em_loop)),
3376 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3377 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3378 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3379 /* 0xE8 - 0xEF */
d4ddafcd 3380 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3381 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3382 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3383 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3384 /* 0xF0 - 0xF7 */
bf608f88 3385 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3386 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3387 G(ByteOp, group3), G(0, group3),
73fba5f4 3388 /* 0xF8 - 0xFF */
f411e6cd
TY		 3389 D(ImplicitOps), D(ImplicitOps),
3390 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3391 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3392};
3393
3394static struct opcode twobyte_table[256] = {
3395 /* 0x00 - 0x0F */
dee6bb70 3396 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3397 N, I(ImplicitOps | VendorSpecific, em_syscall),
3398 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3399 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3400 N, D(ImplicitOps | ModRM), N, N,
3401 /* 0x10 - 0x1F */
3402 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3403 /* 0x20 - 0x2F */
cfec82cb 3404 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3405 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3406 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3407 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4
AK		 3408 N, N, N, N,
3409 N, N, N, N, N, N, N, N,
3410 /* 0x30 - 0x3F */
e1e210b0 3411 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3412 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3413 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
80bdec64 3414 DIP(ImplicitOps, rdpmc, check_rdpmc),
db5b0762
TY		 3415 I(ImplicitOps | VendorSpecific, em_sysenter),
3416 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3417 N, N,
73fba5f4
AK		 3418 N, N, N, N, N, N, N, N,
3419 /* 0x40 - 0x4F */
3420 X16(D(DstReg | SrcMem | ModRM | Mov)),
3421 /* 0x50 - 0x5F */
3422 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3423 /* 0x60 - 0x6F */
aa97bb48
AK		 3424 N, N, N, N,
3425 N, N, N, N,
3426 N, N, N, N,
3427 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3428 /* 0x70 - 0x7F */
aa97bb48
AK		 3429 N, N, N, N,
3430 N, N, N, N,
3431 N, N, N, N,
3432 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3433 /* 0x80 - 0x8F */
3434 X16(D(SrcImm)),
3435 /* 0x90 - 0x9F */
ee45b58e 3436 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3437 /* 0xA0 - 0xA7 */
1cd196ea 3438 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
ce7faab2 3439 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3440 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3441 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3442 /* 0xA8 - 0xAF */
1cd196ea 3443 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3444 DI(ImplicitOps, rsm),
ce7faab2 3445 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3446 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3447 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3448 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3449 /* 0xB0 - 0xB7 */
e940b5c2 3450 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3451 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3452 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3453 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3454 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
09b5f4d3 3455 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3456 /* 0xB8 - 0xBF */
3457 N, N,
ce7faab2
TY		 3458 G(BitOp, group8),
3459 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3460 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
d9574a25 3461 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3462 /* 0xC0 - 0xCF */
739ae406 3463 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3464 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3465 N, N, N, GD(0, &group9),
3466 N, N, N, N, N, N, N, N,
3467 /* 0xD0 - 0xDF */
3468 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3469 /* 0xE0 - 0xEF */
3470 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3471 /* 0xF0 - 0xFF */
3472 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3473};
3474
3475#undef D
3476#undef N
3477#undef G
3478#undef GD
3479#undef I
aa97bb48 3480#undef GP
01de8b09 3481#undef EXT
73fba5f4 3482
8d8f4e9f 3483#undef D2bv
f6511935 3484#undef D2bvIP
8d8f4e9f 3485#undef I2bv
d7841a4b 3486#undef I2bvIP
d67fc27a 3487#undef I6ALU
8d8f4e9f 3488
9dac77fa 3489static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3490{
3491 unsigned size;
3492
9dac77fa 3493 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3494 if (size == 8)
3495 size = 4;
3496 return size;
3497}
3498
3499static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3500 unsigned size, bool sign_extension)
3501{
39f21ee5
AK		 3502 int rc = X86EMUL_CONTINUE;
3503
3504 op->type = OP_IMM;
3505 op->bytes = size;
9dac77fa 3506 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3507 /* NB. Immediates are sign-extended as necessary. */
3508 switch (op->bytes) {
3509 case 1:
e85a1085 3510 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3511 break;
3512 case 2:
e85a1085 3513 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3514 break;
3515 case 4:
e85a1085 3516 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3517 break;
3518 }
3519 if (!sign_extension) {
3520 switch (op->bytes) {
3521 case 1:
3522 op->val &= 0xff;
3523 break;
3524 case 2:
3525 op->val &= 0xffff;
3526 break;
3527 case 4:
3528 op->val &= 0xffffffff;
3529 break;
3530 }
3531 }
3532done:
3533 return rc;
3534}
3535
a9945549
AK		 3536static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3537 unsigned d)
3538{
3539 int rc = X86EMUL_CONTINUE;
3540
3541 switch (d) {
3542 case OpReg:
3543 decode_register_operand(ctxt, op,
5217973e 3544 op == &ctxt->dst &&
a9945549
AK		 3545 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3546 break;
3547 case OpImmUByte:
608aabe3 3548 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3549 break;
3550 case OpMem:
41ddf978 3551 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3552 mem_common:
3553 *op = ctxt->memop;
3554 ctxt->memopp = op;
3555 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3556 fetch_bit_operand(ctxt);
3557 op->orig_val = op->val;
3558 break;
41ddf978
AK		 3559 case OpMem64:
3560 ctxt->memop.bytes = 8;
3561 goto mem_common;
a9945549
AK		 3562 case OpAcc:
3563 op->type = OP_REG;
3564 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3565 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3566 fetch_register_operand(op);
3567 op->orig_val = op->val;
3568 break;
3569 case OpDI:
3570 op->type = OP_MEM;
3571 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3572 op->addr.mem.ea =
3573 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3574 op->addr.mem.seg = VCPU_SREG_ES;
3575 op->val = 0;
3576 break;
3577 case OpDX:
3578 op->type = OP_REG;
3579 op->bytes = 2;
3580 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3581 fetch_register_operand(op);
3582 break;
4dd6a57d
AK		 3583 case OpCL:
3584 op->bytes = 1;
3585 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3586 break;
3587 case OpImmByte:
3588 rc = decode_imm(ctxt, op, 1, true);
3589 break;
3590 case OpOne:
3591 op->bytes = 1;
3592 op->val = 1;
3593 break;
3594 case OpImm:
3595 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3596 break;
0fe59128
AK		 3597 case OpMem16:
3598 ctxt->memop.bytes = 2;
3599 goto mem_common;
3600 case OpMem32:
3601 ctxt->memop.bytes = 4;
3602 goto mem_common;
3603 case OpImmU16:
3604 rc = decode_imm(ctxt, op, 2, false);
3605 break;
3606 case OpImmU:
3607 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3608 break;
3609 case OpSI:
3610 op->type = OP_MEM;
3611 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3612 op->addr.mem.ea =
3613 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3614 op->addr.mem.seg = seg_override(ctxt);
3615 op->val = 0;
3616 break;
3617 case OpImmFAddr:
3618 op->type = OP_IMM;
3619 op->addr.mem.ea = ctxt->_eip;
3620 op->bytes = ctxt->op_bytes + 2;
3621 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3622 break;
3623 case OpMemFAddr:
3624 ctxt->memop.bytes = ctxt->op_bytes + 2;
3625 goto mem_common;
c191a7a0
AK		 3626 case OpES:
3627 op->val = VCPU_SREG_ES;
3628 break;
3629 case OpCS:
3630 op->val = VCPU_SREG_CS;
3631 break;
3632 case OpSS:
3633 op->val = VCPU_SREG_SS;
3634 break;
3635 case OpDS:
3636 op->val = VCPU_SREG_DS;
3637 break;
3638 case OpFS:
3639 op->val = VCPU_SREG_FS;
3640 break;
3641 case OpGS:
3642 op->val = VCPU_SREG_GS;
3643 break;
a9945549
AK		 3644 case OpImplicit:
3645 /* Special instructions do their own operand decoding. */
3646 default:
3647 op->type = OP_NONE; /* Disable writeback. */
3648 break;
3649 }
3650
3651done:
3652 return rc;
3653}
3654
ef5d75cc 3655int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3656{
dde7e6d1
AK		 3657 int rc = X86EMUL_CONTINUE;
3658 int mode = ctxt->mode;
46561646 3659 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3660 bool op_prefix = false;
46561646 3661 struct opcode opcode;
dde7e6d1 3662
f09ed83e
AK		 3663 ctxt->memop.type = OP_NONE;
3664 ctxt->memopp = NULL;
9dac77fa
AK		 3665 ctxt->_eip = ctxt->eip;
3666 ctxt->fetch.start = ctxt->_eip;
3667 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3668 if (insn_len > 0)
9dac77fa 3669 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3670
3671 switch (mode) {
3672 case X86EMUL_MODE_REAL:
3673 case X86EMUL_MODE_VM86:
3674 case X86EMUL_MODE_PROT16:
3675 def_op_bytes = def_ad_bytes = 2;
3676 break;
3677 case X86EMUL_MODE_PROT32:
3678 def_op_bytes = def_ad_bytes = 4;
3679 break;
3680#ifdef CONFIG_X86_64
3681 case X86EMUL_MODE_PROT64:
3682 def_op_bytes = 4;
3683 def_ad_bytes = 8;
3684 break;
3685#endif
3686 default:
1d2887e2 3687 return EMULATION_FAILED;
dde7e6d1
AK		 3688 }
3689
9dac77fa
AK		 3690 ctxt->op_bytes = def_op_bytes;
3691 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3692
3693 /* Legacy prefixes. */
3694 for (;;) {
e85a1085 3695 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3696 case 0x66: /* operand-size override */
0d7cdee8 3697 op_prefix = true;
dde7e6d1 3698 /* switch between 2/4 bytes */
9dac77fa 3699 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3700 break;
3701 case 0x67: /* address-size override */
3702 if (mode == X86EMUL_MODE_PROT64)
3703 /* switch between 4/8 bytes */
9dac77fa 3704 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3705 else
3706 /* switch between 2/4 bytes */
9dac77fa 3707 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3708 break;
3709 case 0x26: /* ES override */
3710 case 0x2e: /* CS override */
3711 case 0x36: /* SS override */
3712 case 0x3e: /* DS override */
9dac77fa 3713 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3714 break;
3715 case 0x64: /* FS override */
3716 case 0x65: /* GS override */
9dac77fa 3717 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3718 break;
3719 case 0x40 ... 0x4f: /* REX */
3720 if (mode != X86EMUL_MODE_PROT64)
3721 goto done_prefixes;
9dac77fa 3722 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3723 continue;
3724 case 0xf0: /* LOCK */
9dac77fa 3725 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3726 break;
3727 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3728 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3729 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3730 break;
3731 default:
3732 goto done_prefixes;
3733 }
3734
3735 /* Any legacy prefix after a REX prefix nullifies its effect. */
3736
9dac77fa 3737 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3738 }
3739
3740done_prefixes:
3741
3742 /* REX prefix. */
9dac77fa
AK		 3743 if (ctxt->rex_prefix & 8)
3744 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3745
3746 /* Opcode byte(s). */
9dac77fa 3747 opcode = opcode_table[ctxt->b];
d3ad6243 3748 /* Two-byte opcode? */
9dac77fa
AK		 3749 if (ctxt->b == 0x0f) {
3750 ctxt->twobyte = 1;
e85a1085 3751 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3752 opcode = twobyte_table[ctxt->b];
dde7e6d1 3753 }
9dac77fa 3754 ctxt->d = opcode.flags;
dde7e6d1 3755
9dac77fa
AK		 3756 while (ctxt->d & GroupMask) {
3757 switch (ctxt->d & GroupMask) {
46561646 3758 case Group:
e85a1085 3759 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3760 --ctxt->_eip;
3761 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3762 opcode = opcode.u.group[goffset];
3763 break;
3764 case GroupDual:
e85a1085 3765 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3766 --ctxt->_eip;
3767 goffset = (ctxt->modrm >> 3) & 7;
3768 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3769 opcode = opcode.u.gdual->mod3[goffset];
3770 else
3771 opcode = opcode.u.gdual->mod012[goffset];
3772 break;
3773 case RMExt:
9dac77fa 3774 goffset = ctxt->modrm & 7;
01de8b09 3775 opcode = opcode.u.group[goffset];
46561646
AK		 3776 break;
3777 case Prefix:
9dac77fa 3778 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3779 return EMULATION_FAILED;
9dac77fa 3780 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3781 switch (simd_prefix) {
3782 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3783 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3784 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3785 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3786 }
3787 break;
3788 default:
1d2887e2 3789 return EMULATION_FAILED;
0d7cdee8 3790 }
46561646 3791
b1ea50b2 3792 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3793 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3794 }
3795
9dac77fa
AK		 3796 ctxt->execute = opcode.u.execute;
3797 ctxt->check_perm = opcode.check_perm;
3798 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3799
3800 /* Unrecognised? */
9dac77fa 3801 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3802 return EMULATION_FAILED;
dde7e6d1 3803
9dac77fa 3804 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3805 return EMULATION_FAILED;
d867162c 3806
9dac77fa
AK		 3807 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3808 ctxt->op_bytes = 8;
dde7e6d1 3809
9dac77fa 3810 if (ctxt->d & Op3264) {
7f9b4b75 3811 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3812 ctxt->op_bytes = 8;
7f9b4b75 3813 else
9dac77fa 3814 ctxt->op_bytes = 4;
7f9b4b75
AK		 3815 }
3816
9dac77fa
AK		 3817 if (ctxt->d & Sse)
3818 ctxt->op_bytes = 16;
1253791d 3819
dde7e6d1 3820 /* ModRM and SIB bytes. */
9dac77fa 3821 if (ctxt->d & ModRM) {
f09ed83e 3822 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3823 if (!ctxt->has_seg_override)
3824 set_seg_override(ctxt, ctxt->modrm_seg);
3825 } else if (ctxt->d & MemAbs)
f09ed83e 3826 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3827 if (rc != X86EMUL_CONTINUE)
3828 goto done;
3829
9dac77fa
AK		 3830 if (!ctxt->has_seg_override)
3831 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3832
f09ed83e 3833 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3834
f09ed83e
AK		 3835 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3836 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3837
dde7e6d1
AK		 3838 /*
3839 * Decode and fetch the source operand: register, memory
3840 * or immediate.
3841 */
0fe59128 3842 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 3843 if (rc != X86EMUL_CONTINUE)
3844 goto done;
3845
dde7e6d1
AK		 3846 /*
3847 * Decode and fetch the second source operand: register, memory
3848 * or immediate.
3849 */
4dd6a57d 3850 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3851 if (rc != X86EMUL_CONTINUE)
3852 goto done;
3853
dde7e6d1 3854 /* Decode and fetch the destination operand: register or memory. */
a9945549 3855 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3856
3857done:
f09ed83e
AK		 3858 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3859 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3860
1d2887e2 3861 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3862}
3863
1cb3f3ae
XG		 3864bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
3865{
3866 return ctxt->d & PageTable;
3867}
3868
3e2f65d5
GN		 3869static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3870{
3e2f65d5
GN		 3871 /* The second termination condition only applies for REPE
3872 * and REPNE. Test if the repeat string operation prefix is
3873 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3874 * corresponding termination condition according to:
3875 * - if REPE/REPZ and ZF = 0 then done
3876 * - if REPNE/REPNZ and ZF = 1 then done
3877 */
9dac77fa
AK		 3878 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3879 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3880 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3881 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3882 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3883 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3884 return true;
3885
3886 return false;
3887}
3888
7b105ca2 3889int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3890{
9aabc88f 3891 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 3892 int rc = X86EMUL_CONTINUE;
9dac77fa 3893 int saved_dst_type = ctxt->dst.type;
8b4caf66 3894
9dac77fa 3895 ctxt->mem_read.pos = 0;
310b5d30 3896
9dac77fa 3897 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3898 rc = emulate_ud(ctxt);
1161624f
GN		 3899 goto done;
3900 }
3901
d380a5e4 3902 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3903 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3904 rc = emulate_ud(ctxt);
d380a5e4
GN		 3905 goto done;
3906 }
3907
9dac77fa 3908 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3909 rc = emulate_ud(ctxt);
081bca0e
AK		 3910 goto done;
3911 }
3912
9dac77fa 3913 if ((ctxt->d & Sse)
717746e3
AK		 3914 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3915 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3916 rc = emulate_ud(ctxt);
3917 goto done;
3918 }
3919
9dac77fa 3920 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3921 rc = emulate_nm(ctxt);
3922 goto done;
3923 }
3924
9dac77fa
AK		 3925 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3926 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3927 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3928 if (rc != X86EMUL_CONTINUE)
3929 goto done;
3930 }
3931
e92805ac 3932 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3933 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3934 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3935 goto done;
3936 }
3937
8ea7d6ae 3938 /* Instruction can only be executed in protected mode */
9dac77fa 3939 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3940 rc = emulate_ud(ctxt);
3941 goto done;
3942 }
3943
d09beabd 3944 /* Do instruction specific permission checks */
9dac77fa
AK		 3945 if (ctxt->check_perm) {
3946 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3947 if (rc != X86EMUL_CONTINUE)
3948 goto done;
3949 }
3950
9dac77fa
AK		 3951 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3952 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3953 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3954 if (rc != X86EMUL_CONTINUE)
3955 goto done;
3956 }
3957
9dac77fa 3958 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3959 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3960 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3961 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3962 goto done;
3963 }
b9fa9d6b
AK		 3964 }
3965
9dac77fa
AK		 3966 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3967 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3968 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3969 if (rc != X86EMUL_CONTINUE)
8b4caf66 3970 goto done;
9dac77fa 3971 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3972 }
3973
9dac77fa
AK		 3974 if (ctxt->src2.type == OP_MEM) {
3975 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3976 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3977 if (rc != X86EMUL_CONTINUE)
3978 goto done;
3979 }
3980
9dac77fa 3981 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3982 goto special_insn;
3983
3984
9dac77fa 3985 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3986 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3987 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3988 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3989 if (rc != X86EMUL_CONTINUE)
3990 goto done;
038e51de 3991 }
9dac77fa 3992 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3993
018a98db
AK		 3994special_insn:
3995
9dac77fa
AK		 3996 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3997 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3998 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3999 if (rc != X86EMUL_CONTINUE)
4000 goto done;
4001 }
4002
9dac77fa
AK		 4003 if (ctxt->execute) {
4004 rc = ctxt->execute(ctxt);
ef65c889
AK		 4005 if (rc != X86EMUL_CONTINUE)
4006 goto done;
4007 goto writeback;
4008 }
4009
9dac77fa 4010 if (ctxt->twobyte)
6aa8b732
AK		 4011 goto twobyte_insn;
4012
9dac77fa 4013 switch (ctxt->b) {
33615aa9 4014 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4015 emulate_1op(ctxt, "inc");
33615aa9
AK		 4016 break;
4017 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4018 emulate_1op(ctxt, "dec");
33615aa9 4019 break;
6aa8b732 4020 case 0x63: /* movsxd */
8b4caf66 4021 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4022 goto cannot_emulate;
9dac77fa 4023 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4024 break;
b2833e3c 4025 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4026 if (test_cc(ctxt->b, ctxt->eflags))
4027 jmp_rel(ctxt, ctxt->src.val);
018a98db 4028 break;
7e0b54b1 4029 case 0x8d: /* lea r16/r32, m */
9dac77fa 4030 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4031 break;
3d9e77df 4032 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4033 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4034 break;
e4f973ae
TY		 4035 rc = em_xchg(ctxt);
4036 break;
e8b6fa70 4037 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4038 switch (ctxt->op_bytes) {
4039 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4040 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4041 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4042 }
4043 break;
018a98db 4044 case 0xc0 ... 0xc1:
51187683 4045 rc = em_grp2(ctxt);
018a98db 4046 break;
6e154e56 4047 case 0xcc: /* int3 */
5c5df76b
TY		 4048 rc = emulate_int(ctxt, 3);
4049 break;
6e154e56 4050 case 0xcd: /* int n */
9dac77fa 4051 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4052 break;
4053 case 0xce: /* into */
5c5df76b
TY		 4054 if (ctxt->eflags & EFLG_OF)
4055 rc = emulate_int(ctxt, 4);
6e154e56 4056 break;
018a98db 4057 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4058 rc = em_grp2(ctxt);
018a98db
AK		 4059 break;
4060 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4061 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4062 rc = em_grp2(ctxt);
018a98db 4063 break;
1a52e051 4064 case 0xe9: /* jmp rel */
db5b0762 4065 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4066 jmp_rel(ctxt, ctxt->src.val);
4067 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4068 break;
111de5d6 4069 case 0xf4: /* hlt */
6c3287f7 4070 ctxt->ops->halt(ctxt);
19fdfa0d 4071 break;
111de5d6
AK		 4072 case 0xf5: /* cmc */
4073 /* complement carry flag from eflags reg */
4074 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4075 break;
4076 case 0xf8: /* clc */
4077 ctxt->eflags &= ~EFLG_CF;
111de5d6 4078 break;
8744aa9a
MG		 4079 case 0xf9: /* stc */
4080 ctxt->eflags |= EFLG_CF;
4081 break;
fb4616f4
MG		 4082 case 0xfc: /* cld */
4083 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4084 break;
4085 case 0xfd: /* std */
4086 ctxt->eflags |= EFLG_DF;
fb4616f4 4087 break;
91269b8f
AK		 4088 default:
4089 goto cannot_emulate;
6aa8b732 4090 }
018a98db 4091
7d9ddaed
AK		 4092 if (rc != X86EMUL_CONTINUE)
4093 goto done;
4094
018a98db 4095writeback:
adddcecf 4096 rc = writeback(ctxt);
1b30eaa8 4097 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4098 goto done;
4099
5cd21917
GN		 4100 /*
4101 * restore dst type in case the decoding will be reused
4102 * (happens for string instruction )
4103 */
9dac77fa 4104 ctxt->dst.type = saved_dst_type;
5cd21917 4105
9dac77fa
AK		 4106 if ((ctxt->d & SrcMask) == SrcSI)
4107 string_addr_inc(ctxt, seg_override(ctxt),
4108 VCPU_REGS_RSI, &ctxt->src);
a682e354 4109
9dac77fa 4110 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4111 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4112 &ctxt->dst);
d9271123 4113
9dac77fa
AK		 4114 if (ctxt->rep_prefix && (ctxt->d & String)) {
4115 struct read_cache *r = &ctxt->io_read;
4116 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4117
d2ddd1c4
GN		 4118 if (!string_insn_completed(ctxt)) {
4119 /*
4120 * Re-enter guest when pio read ahead buffer is empty
4121 * or, if it is not used, after each 1024 iteration.
4122 */
9dac77fa 4123 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4124 (r->end == 0 || r->end != r->pos)) {
4125 /*
4126 * Reset read cache. Usually happens before
4127 * decode, but since instruction is restarted
4128 * we have to do it here.
4129 */
9dac77fa 4130 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4131 return EMULATION_RESTART;
4132 }
4133 goto done; /* skip rip writeback */
0fa6ccbd 4134 }
5cd21917 4135 }
d2ddd1c4 4136
9dac77fa 4137 ctxt->eip = ctxt->_eip;
018a98db
AK		 4138
4139done:
da9cb575
AK		 4140 if (rc == X86EMUL_PROPAGATE_FAULT)
4141 ctxt->have_exception = true;
775fde86
JR		 4142 if (rc == X86EMUL_INTERCEPTED)
4143 return EMULATION_INTERCEPTED;
4144
d2ddd1c4 4145 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4146
4147twobyte_insn:
9dac77fa 4148 switch (ctxt->b) {
018a98db 4149 case 0x09: /* wbinvd */
cfb22375 4150 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4151 break;
4152 case 0x08: /* invd */
018a98db
AK		 4153 case 0x0d: /* GrpP (prefetch) */
4154 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4155 break;
4156 case 0x20: /* mov cr, reg */
9dac77fa 4157 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4158 break;
6aa8b732 4159 case 0x21: /* mov from dr to reg */
9dac77fa 4160 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4161 break;
6aa8b732 4162 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4163 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4164 if (!test_cc(ctxt->b, ctxt->eflags))
4165 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4166 break;
b2833e3c 4167 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4168 if (test_cc(ctxt->b, ctxt->eflags))
4169 jmp_rel(ctxt, ctxt->src.val);
018a98db 4170 break;
ee45b58e 4171 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4172 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4173 break;
9bf8ea42
GT		 4174 case 0xa4: /* shld imm8, r, r/m */
4175 case 0xa5: /* shld cl, r, r/m */
761441b9 4176 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4177 break;
9bf8ea42
GT		 4178 case 0xac: /* shrd imm8, r, r/m */
4179 case 0xad: /* shrd cl, r, r/m */
761441b9 4180 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4181 break;
2a7c5b8b
GC		 4182 case 0xae: /* clflush */
4183 break;
6aa8b732 4184 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4185 ctxt->dst.bytes = ctxt->op_bytes;
4186 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4187 : (u16) ctxt->src.val;
6aa8b732 4188 break;
6aa8b732 4189 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4190 ctxt->dst.bytes = ctxt->op_bytes;
4191 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4192 (s16) ctxt->src.val;
6aa8b732 4193 break;
92f738a5 4194 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4195 emulate_2op_SrcV(ctxt, "add");
92f738a5 4196 /* Write back the register source. */
9dac77fa
AK		 4197 ctxt->src.val = ctxt->dst.orig_val;
4198 write_register_operand(&ctxt->src);
92f738a5 4199 break;
a012e65a 4200 case 0xc3: /* movnti */
9dac77fa
AK		 4201 ctxt->dst.bytes = ctxt->op_bytes;
4202 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4203 (u64) ctxt->src.val;
a012e65a 4204 break;
91269b8f
AK		 4205 default:
4206 goto cannot_emulate;
6aa8b732 4207 }
7d9ddaed
AK		 4208
4209 if (rc != X86EMUL_CONTINUE)
4210 goto done;
4211
6aa8b732
AK		 4212 goto writeback;
4213
4214cannot_emulate:
a0c0ab2f 4215 return EMULATION_FAILED;
6aa8b732 4216}
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