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Merge tag 'kvm-s390-next-20150122' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 128#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 129/* Generic ModRM decode. */
130#define ModRM (1<<19)
131/* Destination is only written; never read. */
132#define Mov (1<<20)
d8769fed 133/* Misc flags */
8ea7d6ae 134#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 135#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 136#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 137#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 138#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 139#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 140#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 141#define No64 (1<<28)
d5ae7ce8 142#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 143#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 144/* Source 2 operand type */
0b789eee 145#define Src2Shift (31)
4dd6a57d 146#define Src2None (OpNone << Src2Shift)
ab2c5ce6 147#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 148#define Src2CL (OpCL << Src2Shift)
149#define Src2ImmByte (OpImmByte << Src2Shift)
150#define Src2One (OpOne << Src2Shift)
151#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 152#define Src2ES (OpES << Src2Shift)
153#define Src2CS (OpCS << Src2Shift)
154#define Src2SS (OpSS << Src2Shift)
155#define Src2DS (OpDS << Src2Shift)
156#define Src2FS (OpFS << Src2Shift)
157#define Src2GS (OpGS << Src2Shift)
4dd6a57d 158#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 159#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 160#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
161#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
162#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 163#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 164#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 165#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 166#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 167#define Intercept ((u64)1 << 48) /* Has valid intercept field */
168#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 169#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 170#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 171#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 172#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 173#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 174
820207c8 175#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 176
d0e53325
AK		 177#define X2(x...) x, x
178#define X3(x...) X2(x), x
179#define X4(x...) X2(x), X2(x)
180#define X5(x...) X4(x), x
181#define X6(x...) X4(x), X2(x)
182#define X7(x...) X4(x), X3(x)
183#define X8(x...) X4(x), X4(x)
184#define X16(x...) X8(x), X8(x)
83babbca 185
e28bbd44
AK		 186#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
187#define FASTOP_SIZE 8
188
189/*
190 * fastop functions have a special calling convention:
191 *
017da7b6
AK		 192 * dst: rax (in/out)
193 * src: rdx (in/out)
e28bbd44
AK		 194 * src2: rcx (in)
195 * flags: rflags (in/out)
b8c0b6ae 196 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 197 *
198 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
199 * different operand sizes can be reached by calculation, rather than a jump
200 * table (which would be bigger than the code).
201 *
202 * fastop functions are declared as taking a never-defined fastop parameter,
203 * so they can't be called from C directly.
204 */
205
206struct fastop;
207
d65b1dee 208struct opcode {
b1ea50b2
AK		 209 u64 flags : 56;
210 u64 intercept : 8;
120df890 211 union {
ef65c889 212 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 213 const struct opcode *group;
214 const struct group_dual *gdual;
215 const struct gprefix *gprefix;
045a282c 216 const struct escape *esc;
39f062ff 217 const struct instr_dual *idual;
e28bbd44 218 void (*fastop)(struct fastop *fake);
120df890 219 } u;
d09beabd 220 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 221};
222
223struct group_dual {
224 struct opcode mod012[8];
225 struct opcode mod3[8];
d65b1dee
AK		 226};
227
0d7cdee8
AK		 228struct gprefix {
229 struct opcode pfx_no;
230 struct opcode pfx_66;
231 struct opcode pfx_f2;
232 struct opcode pfx_f3;
233};
234
045a282c
GN		 235struct escape {
236 struct opcode op[8];
237 struct opcode high[64];
238};
239
39f062ff
NA		 240struct instr_dual {
241 struct opcode mod012;
242 struct opcode mod3;
243};
244
6aa8b732 245/* EFLAGS bit definitions. */
d4c6a154
GN		 246#define EFLG_ID (1<<21)
247#define EFLG_VIP (1<<20)
248#define EFLG_VIF (1<<19)
249#define EFLG_AC (1<<18)
b1d86143
AP		 250#define EFLG_VM (1<<17)
251#define EFLG_RF (1<<16)
d4c6a154
GN		 252#define EFLG_IOPL (3<<12)
253#define EFLG_NT (1<<14)
6aa8b732
AK		 254#define EFLG_OF (1<<11)
255#define EFLG_DF (1<<10)
b1d86143 256#define EFLG_IF (1<<9)
d4c6a154 257#define EFLG_TF (1<<8)
6aa8b732
AK		 258#define EFLG_SF (1<<7)
259#define EFLG_ZF (1<<6)
260#define EFLG_AF (1<<4)
261#define EFLG_PF (1<<2)
262#define EFLG_CF (1<<0)
263
62bd430e
MG		 264#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
265#define EFLG_RESERVED_ONE_MASK 2
266
3dc4bc4f
NA		 267enum x86_transfer_type {
268 X86_TRANSFER_NONE,
269 X86_TRANSFER_CALL_JMP,
270 X86_TRANSFER_RET,
271 X86_TRANSFER_TASK_SWITCH,
272};
273
dd856efa
AK		 274static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 if (!(ctxt->regs_valid & (1 << nr))) {
277 ctxt->regs_valid |= 1 << nr;
278 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
279 }
280 return ctxt->_regs[nr];
281}
282
283static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
284{
285 ctxt->regs_valid |= 1 << nr;
286 ctxt->regs_dirty |= 1 << nr;
287 return &ctxt->_regs[nr];
288}
289
290static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
291{
292 reg_read(ctxt, nr);
293 return reg_write(ctxt, nr);
294}
295
296static void writeback_registers(struct x86_emulate_ctxt *ctxt)
297{
298 unsigned reg;
299
300 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
301 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
302}
303
304static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
305{
306 ctxt->regs_dirty = 0;
307 ctxt->regs_valid = 0;
308}
309
6aa8b732
AK		 310/*
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
313 */
314#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
315
dda96d8f
AK		 316#ifdef CONFIG_X86_64
317#define ON64(x) x
318#else
319#define ON64(x)
320#endif
321
4d758349
AK		 322static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
323
b7d491e7
AK		 324#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
325#define FOP_RET "ret \n\t"
326
327#define FOP_START(op) \
328 extern void em_##op(struct fastop *fake); \
329 asm(".pushsection .text, \"ax\" \n\t" \
330 ".global em_" #op " \n\t" \
331 FOP_ALIGN \
332 "em_" #op ": \n\t"
333
334#define FOP_END \
335 ".popsection")
336
0bdea068
AK		 337#define FOPNOP() FOP_ALIGN FOP_RET
338
b7d491e7 339#define FOP1E(op, dst) \
b8c0b6ae
AK		 340 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
341
342#define FOP1EEX(op, dst) \
343 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 344
345#define FASTOP1(op) \
346 FOP_START(op) \
347 FOP1E(op##b, al) \
348 FOP1E(op##w, ax) \
349 FOP1E(op##l, eax) \
350 ON64(FOP1E(op##q, rax)) \
351 FOP_END
352
b9fa409b
AK		 353/* 1-operand, using src2 (for MUL/DIV r/m) */
354#define FASTOP1SRC2(op, name) \
355 FOP_START(name) \
356 FOP1E(op, cl) \
357 FOP1E(op, cx) \
358 FOP1E(op, ecx) \
359 ON64(FOP1E(op, rcx)) \
360 FOP_END
361
b8c0b6ae
AK		 362/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
363#define FASTOP1SRC2EX(op, name) \
364 FOP_START(name) \
365 FOP1EEX(op, cl) \
366 FOP1EEX(op, cx) \
367 FOP1EEX(op, ecx) \
368 ON64(FOP1EEX(op, rcx)) \
369 FOP_END
370
f7857f35
AK		 371#define FOP2E(op, dst, src) \
372 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
373
374#define FASTOP2(op) \
375 FOP_START(op) \
017da7b6
AK		 376 FOP2E(op##b, al, dl) \
377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 380 FOP_END
381
11c363ba
AK		 382/* 2 operand, word only */
383#define FASTOP2W(op) \
384 FOP_START(op) \
385 FOPNOP() \
017da7b6
AK		 386 FOP2E(op##w, ax, dx) \
387 FOP2E(op##l, eax, edx) \
388 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 389 FOP_END
390
007a3b54
AK		 391/* 2 operand, src is CL */
392#define FASTOP2CL(op) \
393 FOP_START(op) \
394 FOP2E(op##b, al, cl) \
395 FOP2E(op##w, ax, cl) \
396 FOP2E(op##l, eax, cl) \
397 ON64(FOP2E(op##q, rax, cl)) \
398 FOP_END
399
5aca3722
NA		 400/* 2 operand, src and dest are reversed */
401#define FASTOP2R(op, name) \
402 FOP_START(name) \
403 FOP2E(op##b, dl, al) \
404 FOP2E(op##w, dx, ax) \
405 FOP2E(op##l, edx, eax) \
406 ON64(FOP2E(op##q, rdx, rax)) \
407 FOP_END
408
0bdea068
AK		 409#define FOP3E(op, dst, src, src2) \
410 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
411
412/* 3-operand, word-only, src2=cl */
413#define FASTOP3WCL(op) \
414 FOP_START(op) \
415 FOPNOP() \
017da7b6
AK		 416 FOP3E(op##w, ax, dx, cl) \
417 FOP3E(op##l, eax, edx, cl) \
418 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 419 FOP_END
420
9ae9feba
AK		 421/* Special case for SETcc - 1 instruction per cc */
422#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
423
b8c0b6ae
AK		 424asm(".global kvm_fastop_exception \n"
425 "kvm_fastop_exception: xor %esi, %esi; ret");
426
9ae9feba
AK		 427FOP_START(setcc)
428FOP_SETCC(seto)
429FOP_SETCC(setno)
430FOP_SETCC(setc)
431FOP_SETCC(setnc)
432FOP_SETCC(setz)
433FOP_SETCC(setnz)
434FOP_SETCC(setbe)
435FOP_SETCC(setnbe)
436FOP_SETCC(sets)
437FOP_SETCC(setns)
438FOP_SETCC(setp)
439FOP_SETCC(setnp)
440FOP_SETCC(setl)
441FOP_SETCC(setnl)
442FOP_SETCC(setle)
443FOP_SETCC(setnle)
444FOP_END;
445
326f578f
PB		 446FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
447FOP_END;
448
8a76d7f2
JR		 449static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
450 enum x86_intercept intercept,
451 enum x86_intercept_stage stage)
452{
453 struct x86_instruction_info info = {
454 .intercept = intercept,
9dac77fa
AK		 455 .rep_prefix = ctxt->rep_prefix,
456 .modrm_mod = ctxt->modrm_mod,
457 .modrm_reg = ctxt->modrm_reg,
458 .modrm_rm = ctxt->modrm_rm,
459 .src_val = ctxt->src.val64,
6cbc5f5a 460 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 461 .src_bytes = ctxt->src.bytes,
462 .dst_bytes = ctxt->dst.bytes,
463 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 464 .next_rip = ctxt->eip,
465 };
466
2953538e 467 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 468}
469
f47cfa31
AK		 470static void assign_masked(ulong *dest, ulong src, ulong mask)
471{
472 *dest = (*dest & ~mask) | (src & mask);
473}
474
9dac77fa 475static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 476{
9dac77fa 477 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 478}
479
f47cfa31
AK		 480static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
481{
482 u16 sel;
483 struct desc_struct ss;
484
485 if (ctxt->mode == X86EMUL_MODE_PROT64)
486 return ~0UL;
487 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
488 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
489}
490
612e89f0
AK		 491static int stack_size(struct x86_emulate_ctxt *ctxt)
492{
493 return (__fls(stack_mask(ctxt)) + 1) >> 3;
494}
495
6aa8b732 496/* Access/update address held in a register, based on addressing mode. */
e4706772 497static inline unsigned long
9dac77fa 498address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 499{
9dac77fa 500 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 501 return reg;
502 else
9dac77fa 503 return reg & ad_mask(ctxt);
e4706772
HH		 504}
505
506static inline unsigned long
01485a22 507register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 508{
01485a22 509 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 510}
511
5ad105e5
AK		 512static void masked_increment(ulong *reg, ulong mask, int inc)
513{
514 assign_masked(reg, *reg + inc, mask);
515}
516
7a957275 517static inline void
01485a22 518register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 519{
5ad105e5
AK		 520 ulong mask;
521
9dac77fa 522 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 523 mask = ~0UL;
7a957275 524 else
5ad105e5 525 mask = ad_mask(ctxt);
01485a22 526 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 527}
528
529static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
530{
dd856efa 531 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 532}
6aa8b732 533
56697687
AK		 534static u32 desc_limit_scaled(struct desc_struct *desc)
535{
536 u32 limit = get_desc_limit(desc);
537
538 return desc->g ? (limit << 12) | 0xfff : limit;
539}
540
7b105ca2 541static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 542{
543 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
544 return 0;
545
7b105ca2 546 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 547}
548
35d3d4a1
AK		 549static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
550 u32 error, bool valid)
54b8486f 551{
e0ad0b47 552 WARN_ON(vec > 0x1f);
da9cb575
AK		 553 ctxt->exception.vector = vec;
554 ctxt->exception.error_code = error;
555 ctxt->exception.error_code_valid = valid;
35d3d4a1 556 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 557}
558
3b88e41a
JR		 559static int emulate_db(struct x86_emulate_ctxt *ctxt)
560{
561 return emulate_exception(ctxt, DB_VECTOR, 0, false);
562}
563
35d3d4a1 564static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 565{
35d3d4a1 566 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 567}
568
618ff15d
AK		 569static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
570{
571 return emulate_exception(ctxt, SS_VECTOR, err, true);
572}
573
35d3d4a1 574static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 575{
35d3d4a1 576 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 577}
578
35d3d4a1 579static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 580{
35d3d4a1 581 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 582}
583
34d1f490
AK		 584static int emulate_de(struct x86_emulate_ctxt *ctxt)
585{
35d3d4a1 586 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 587}
588
1253791d
AK		 589static int emulate_nm(struct x86_emulate_ctxt *ctxt)
590{
591 return emulate_exception(ctxt, NM_VECTOR, 0, false);
592}
593
1aa36616
AK		 594static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
595{
596 u16 selector;
597 struct desc_struct desc;
598
599 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
600 return selector;
601}
602
603static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
604 unsigned seg)
605{
606 u16 dummy;
607 u32 base3;
608 struct desc_struct desc;
609
610 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
611 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
612}
613
1c11b376
AK		 614/*
615 * x86 defines three classes of vector instructions: explicitly
616 * aligned, explicitly unaligned, and the rest, which change behaviour
617 * depending on whether they're AVX encoded or not.
618 *
619 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
620 * subject to the same check.
621 */
622static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
623{
624 if (likely(size < 16))
625 return false;
626
627 if (ctxt->d & Aligned)
628 return true;
629 else if (ctxt->d & Unaligned)
630 return false;
631 else if (ctxt->d & Avx)
632 return false;
633 else
634 return true;
635}
636
d09155d2
PB		 637static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 unsigned *max_size, unsigned size,
640 bool write, bool fetch,
d50eaa18 641 enum x86emul_mode mode, ulong *linear)
52fd8b44 642{
618ff15d
AK		 643 struct desc_struct desc;
644 bool usable;
52fd8b44 645 ulong la;
618ff15d 646 u32 lim;
1aa36616 647 u16 sel;
52fd8b44 648
7b105ca2 649 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 650 *max_size = 0;
d50eaa18 651 switch (mode) {
618ff15d 652 case X86EMUL_MODE_PROT64:
4be4de7e 653 if (is_noncanonical_address(la))
abc7d8a4 654 goto bad;
fd56e154
PB		 655
656 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
657 if (size > *max_size)
658 goto bad;
618ff15d
AK		 659 break;
660 default:
1aa36616
AK		 661 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
662 addr.seg);
618ff15d
AK		 663 if (!usable)
664 goto bad;
58b7825b
GN		 665 /* code segment in protected mode or read-only data segment */
666 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
667 || !(desc.type & 2)) && write)
618ff15d
AK		 668 goto bad;
669 /* unreadable code segment */
3d9b938e 670 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 671 goto bad;
672 lim = desc_limit_scaled(&desc);
997b0412 673 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 674 /* expand-down segment */
fd56e154 675 if (addr.ea <= lim)
618ff15d
AK		 676 goto bad;
677 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 678 }
997b0412
PB		 679 if (addr.ea > lim)
680 goto bad;
681 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 682 if (size > *max_size)
683 goto bad;
31ff6488 684 la &= (u32)-1;
618ff15d
AK		 685 break;
686 }
1c11b376
AK		 687 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
688 return emulate_gp(ctxt, 0);
52fd8b44
AK		 689 *linear = la;
690 return X86EMUL_CONTINUE;
618ff15d
AK		 691bad:
692 if (addr.seg == VCPU_SREG_SS)
3606189f 693 return emulate_ss(ctxt, 0);
618ff15d 694 else
3606189f 695 return emulate_gp(ctxt, 0);
52fd8b44
AK		 696}
697
3d9b938e
NE		 698static int linearize(struct x86_emulate_ctxt *ctxt,
699 struct segmented_address addr,
700 unsigned size, bool write,
701 ulong *linear)
702{
fd56e154 703 unsigned max_size;
d50eaa18
NA		 704 return __linearize(ctxt, addr, &max_size, size, write, false,
705 ctxt->mode, linear);
3d9b938e
NE		 706}
707
d50eaa18
NA		 708static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
709 enum x86emul_mode mode)
710{
711 ulong linear;
712 int rc;
713 unsigned max_size;
714 struct segmented_address addr = { .seg = VCPU_SREG_CS,
715 .ea = dst };
716
717 if (ctxt->op_bytes != sizeof(unsigned long))
718 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
719 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
720 if (rc == X86EMUL_CONTINUE)
721 ctxt->_eip = addr.ea;
722 return rc;
723}
724
725static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
726{
727 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 728}
729
d50eaa18
NA		 730static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
731 const struct desc_struct *cs_desc)
732{
733 enum x86emul_mode mode = ctxt->mode;
734
735#ifdef CONFIG_X86_64
736 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
737 u64 efer = 0;
738
739 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
740 if (efer & EFER_LMA)
741 mode = X86EMUL_MODE_PROT64;
742 }
743#endif
744 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
745 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
746 return assign_eip(ctxt, dst, mode);
747}
748
749static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
750{
751 return assign_eip_near(ctxt, ctxt->_eip + rel);
752}
3d9b938e 753
3ca3ac4d
AK		 754static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
755 struct segmented_address addr,
756 void *data,
757 unsigned size)
758{
9fa088f4
AK		 759 int rc;
760 ulong linear;
761
83b8795a 762 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 763 if (rc != X86EMUL_CONTINUE)
764 return rc;
0f65dd70 765 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 766}
767
807941b1 768/*
285ca9e9 769 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 770 * boundary if they are not in fetch_cache yet.
771 */
9506d57d 772static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 773{
62266869 774 int rc;
fd56e154 775 unsigned size, max_size;
285ca9e9 776 unsigned long linear;
17052f16 777 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 778 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 779 .ea = ctxt->eip + cur_size };
780
fd56e154
PB		 781 /*
782 * We do not know exactly how many bytes will be needed, and
783 * __linearize is expensive, so fetch as much as possible. We
784 * just have to avoid going beyond the 15 byte limit, the end
785 * of the segment, or the end of the page.
786 *
787 * __linearize is called with size 0 so that it does not do any
788 * boundary check itself. Instead, we use max_size to check
789 * against op_size.
790 */
d50eaa18
NA		 791 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
792 &linear);
719d5a9b
PB		 793 if (unlikely(rc != X86EMUL_CONTINUE))
794 return rc;
795
fd56e154 796 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 797 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 798
799 /*
800 * One instruction can only straddle two pages,
801 * and one has been loaded at the beginning of
802 * x86_decode_insn. So, if not enough bytes
803 * still, we must have hit the 15-byte boundary.
804 */
805 if (unlikely(size < op_size))
fd56e154
PB		 806 return emulate_gp(ctxt, 0);
807
17052f16 808 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 809 size, &ctxt->exception);
810 if (unlikely(rc != X86EMUL_CONTINUE))
811 return rc;
17052f16 812 ctxt->fetch.end += size;
3e2815e9 813 return X86EMUL_CONTINUE;
62266869
AK		 814}
815
9506d57d
PB		 816static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
817 unsigned size)
62266869 818{
08da44ae
NA		 819 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
820
821 if (unlikely(done_size < size))
822 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 823 else
824 return X86EMUL_CONTINUE;
62266869
AK		 825}
826
67cbc90d 827/* Fetch next part of the instruction being emulated. */
e85a1085 828#define insn_fetch(_type, _ctxt) \
9506d57d 829({ _type _x; \
9506d57d
PB		 830 \
831 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 832 if (rc != X86EMUL_CONTINUE) \
833 goto done; \
9506d57d 834 ctxt->_eip += sizeof(_type); \
17052f16
PB		 835 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
836 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 837 _x; \
67cbc90d
TY		 838})
839
807941b1 840#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 841({ \
9506d57d 842 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 843 if (rc != X86EMUL_CONTINUE) \
844 goto done; \
9506d57d 845 ctxt->_eip += (_size); \
17052f16
PB		 846 memcpy(_arr, ctxt->fetch.ptr, _size); \
847 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 848})
849
1e3c5cb0
RR		 850/*
851 * Given the 'reg' portion of a ModRM byte, and a register block, return a
852 * pointer into the block that addresses the relevant register.
853 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
854 */
dd856efa 855static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 856 int byteop)
6aa8b732
AK		 857{
858 void *p;
aa9ac1a6 859 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 860
6aa8b732 861 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 862 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
863 else
864 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 865 return p;
866}
867
868static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 869 struct segmented_address addr,
6aa8b732
AK		 870 u16 *size, unsigned long *address, int op_bytes)
871{
872 int rc;
873
874 if (op_bytes == 2)
875 op_bytes = 3;
876 *address = 0;
3ca3ac4d 877 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 878 if (rc != X86EMUL_CONTINUE)
6aa8b732 879 return rc;
30b31ab6 880 addr.ea += 2;
3ca3ac4d 881 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 882 return rc;
883}
884
34b77652
AK		 885FASTOP2(add);
886FASTOP2(or);
887FASTOP2(adc);
888FASTOP2(sbb);
889FASTOP2(and);
890FASTOP2(sub);
891FASTOP2(xor);
892FASTOP2(cmp);
893FASTOP2(test);
894
b9fa409b
AK		 895FASTOP1SRC2(mul, mul_ex);
896FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 897FASTOP1SRC2EX(div, div_ex);
898FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 899
34b77652
AK		 900FASTOP3WCL(shld);
901FASTOP3WCL(shrd);
902
903FASTOP2W(imul);
904
905FASTOP1(not);
906FASTOP1(neg);
907FASTOP1(inc);
908FASTOP1(dec);
909
910FASTOP2CL(rol);
911FASTOP2CL(ror);
912FASTOP2CL(rcl);
913FASTOP2CL(rcr);
914FASTOP2CL(shl);
915FASTOP2CL(shr);
916FASTOP2CL(sar);
917
918FASTOP2W(bsf);
919FASTOP2W(bsr);
920FASTOP2W(bt);
921FASTOP2W(bts);
922FASTOP2W(btr);
923FASTOP2W(btc);
924
e47a5f5f
AK		 925FASTOP2(xadd);
926
5aca3722
NA		 927FASTOP2R(cmp, cmp_r);
928
9ae9feba 929static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 930{
9ae9feba
AK		 931 u8 rc;
932 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 933
9ae9feba 934 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 935 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 936 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
937 return rc;
bbe9abbd
NK		 938}
939
91ff3cb4
AK		 940static void fetch_register_operand(struct operand *op)
941{
942 switch (op->bytes) {
943 case 1:
944 op->val = *(u8 *)op->addr.reg;
945 break;
946 case 2:
947 op->val = *(u16 *)op->addr.reg;
948 break;
949 case 4:
950 op->val = *(u32 *)op->addr.reg;
951 break;
952 case 8:
953 op->val = *(u64 *)op->addr.reg;
954 break;
955 }
956}
957
1253791d
AK		 958static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
959{
960 ctxt->ops->get_fpu(ctxt);
961 switch (reg) {
89a87c67
MK		 962 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
963 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
964 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
965 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
966 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
967 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
968 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
969 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 970#ifdef CONFIG_X86_64
89a87c67
MK		 971 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
972 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
973 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
974 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
975 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
976 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
977 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
978 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 979#endif
980 default: BUG();
981 }
982 ctxt->ops->put_fpu(ctxt);
983}
984
985static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
986 int reg)
987{
988 ctxt->ops->get_fpu(ctxt);
989 switch (reg) {
89a87c67
MK		 990 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
991 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
992 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
993 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
994 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
995 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
996 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
997 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 998#ifdef CONFIG_X86_64
89a87c67
MK		 999 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1000 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1001 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1002 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1003 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1004 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1005 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1006 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1007#endif
1008 default: BUG();
1009 }
1010 ctxt->ops->put_fpu(ctxt);
1011}
1012
cbe2c9d3
AK		 1013static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1014{
1015 ctxt->ops->get_fpu(ctxt);
1016 switch (reg) {
1017 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1018 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1019 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1020 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1021 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1022 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1023 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1024 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1025 default: BUG();
1026 }
1027 ctxt->ops->put_fpu(ctxt);
1028}
1029
1030static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1031{
1032 ctxt->ops->get_fpu(ctxt);
1033 switch (reg) {
1034 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1035 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1036 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1037 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1038 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1039 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1040 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1041 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1042 default: BUG();
1043 }
1044 ctxt->ops->put_fpu(ctxt);
1045}
1046
045a282c
GN		 1047static int em_fninit(struct x86_emulate_ctxt *ctxt)
1048{
1049 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1050 return emulate_nm(ctxt);
1051
1052 ctxt->ops->get_fpu(ctxt);
1053 asm volatile("fninit");
1054 ctxt->ops->put_fpu(ctxt);
1055 return X86EMUL_CONTINUE;
1056}
1057
1058static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1059{
1060 u16 fcw;
1061
1062 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1063 return emulate_nm(ctxt);
1064
1065 ctxt->ops->get_fpu(ctxt);
1066 asm volatile("fnstcw %0": "+m"(fcw));
1067 ctxt->ops->put_fpu(ctxt);
1068
045a282c
GN		 1069 ctxt->dst.val = fcw;
1070
1071 return X86EMUL_CONTINUE;
1072}
1073
1074static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1075{
1076 u16 fsw;
1077
1078 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1079 return emulate_nm(ctxt);
1080
1081 ctxt->ops->get_fpu(ctxt);
1082 asm volatile("fnstsw %0": "+m"(fsw));
1083 ctxt->ops->put_fpu(ctxt);
1084
045a282c
GN		 1085 ctxt->dst.val = fsw;
1086
1087 return X86EMUL_CONTINUE;
1088}
1089
1253791d 1090static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1091 struct operand *op)
3c118e24 1092{
9dac77fa 1093 unsigned reg = ctxt->modrm_reg;
33615aa9 1094
9dac77fa
AK		 1095 if (!(ctxt->d & ModRM))
1096 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1097
9dac77fa 1098 if (ctxt->d & Sse) {
1253791d
AK		 1099 op->type = OP_XMM;
1100 op->bytes = 16;
1101 op->addr.xmm = reg;
1102 read_sse_reg(ctxt, &op->vec_val, reg);
1103 return;
1104 }
cbe2c9d3
AK		 1105 if (ctxt->d & Mmx) {
1106 reg &= 7;
1107 op->type = OP_MM;
1108 op->bytes = 8;
1109 op->addr.mm = reg;
1110 return;
1111 }
1253791d 1112
3c118e24 1113 op->type = OP_REG;
6d4d85ec
GN		 1114 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1115 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1116
91ff3cb4 1117 fetch_register_operand(op);
3c118e24
AK		 1118 op->orig_val = op->val;
1119}
1120
a6e3407b
AK		 1121static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1122{
1123 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1124 ctxt->modrm_seg = VCPU_SREG_SS;
1125}
1126
1c73ef66 1127static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1128 struct operand *op)
1c73ef66 1129{
1c73ef66 1130 u8 sib;
02357bdc 1131 int index_reg, base_reg, scale;
3e2815e9 1132 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1133 ulong modrm_ea = 0;
1c73ef66 1134
02357bdc
BD		 1135 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1136 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1137 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1138
02357bdc 1139 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1140 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1141 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1142 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1143
9b88ae99 1144 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1145 op->type = OP_REG;
9dac77fa 1146 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1147 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1148 ctxt->d & ByteOp);
9dac77fa 1149 if (ctxt->d & Sse) {
1253791d
AK		 1150 op->type = OP_XMM;
1151 op->bytes = 16;
9dac77fa
AK		 1152 op->addr.xmm = ctxt->modrm_rm;
1153 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1154 return rc;
1155 }
cbe2c9d3
AK		 1156 if (ctxt->d & Mmx) {
1157 op->type = OP_MM;
1158 op->bytes = 8;
bdc90722 1159 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1160 return rc;
1161 }
2dbd0dd7 1162 fetch_register_operand(op);
1c73ef66
AK		 1163 return rc;
1164 }
1165
2dbd0dd7
AK		 1166 op->type = OP_MEM;
1167
9dac77fa 1168 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1169 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1170 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1171 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1172 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1173
1174 /* 16-bit ModR/M decode. */
9dac77fa 1175 switch (ctxt->modrm_mod) {
1c73ef66 1176 case 0:
9dac77fa 1177 if (ctxt->modrm_rm == 6)
e85a1085 1178 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1179 break;
1180 case 1:
e85a1085 1181 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1182 break;
1183 case 2:
e85a1085 1184 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1185 break;
1186 }
9dac77fa 1187 switch (ctxt->modrm_rm) {
1c73ef66 1188 case 0:
2dbd0dd7 1189 modrm_ea += bx + si;
1c73ef66
AK		 1190 break;
1191 case 1:
2dbd0dd7 1192 modrm_ea += bx + di;
1c73ef66
AK		 1193 break;
1194 case 2:
2dbd0dd7 1195 modrm_ea += bp + si;
1c73ef66
AK		 1196 break;
1197 case 3:
2dbd0dd7 1198 modrm_ea += bp + di;
1c73ef66
AK		 1199 break;
1200 case 4:
2dbd0dd7 1201 modrm_ea += si;
1c73ef66
AK		 1202 break;
1203 case 5:
2dbd0dd7 1204 modrm_ea += di;
1c73ef66
AK		 1205 break;
1206 case 6:
9dac77fa 1207 if (ctxt->modrm_mod != 0)
2dbd0dd7 1208 modrm_ea += bp;
1c73ef66
AK		 1209 break;
1210 case 7:
2dbd0dd7 1211 modrm_ea += bx;
1c73ef66
AK		 1212 break;
1213 }
9dac77fa
AK		 1214 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1215 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1216 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1217 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1218 } else {
1219 /* 32/64-bit ModR/M decode. */
9dac77fa 1220 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1221 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1222 index_reg |= (sib >> 3) & 7;
1223 base_reg |= sib & 7;
1224 scale = sib >> 6;
1225
9dac77fa 1226 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1227 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1228 else {
dd856efa 1229 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1230 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1231 /* Increment ESP on POP [ESP] */
1232 if ((ctxt->d & IncSP) &&
1233 base_reg == VCPU_REGS_RSP)
1234 modrm_ea += ctxt->op_bytes;
a6e3407b 1235 }
dc71d0f1 1236 if (index_reg != 4)
dd856efa 1237 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1238 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1239 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1240 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1241 ctxt->rip_relative = 1;
a6e3407b
AK		 1242 } else {
1243 base_reg = ctxt->modrm_rm;
dd856efa 1244 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1245 adjust_modrm_seg(ctxt, base_reg);
1246 }
9dac77fa 1247 switch (ctxt->modrm_mod) {
1c73ef66 1248 case 1:
e85a1085 1249 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1250 break;
1251 case 2:
e85a1085 1252 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1253 break;
1254 }
1255 }
90de84f5 1256 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1257 if (ctxt->ad_bytes != 8)
1258 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1259
1c73ef66
AK		 1260done:
1261 return rc;
1262}
1263
1264static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1265 struct operand *op)
1c73ef66 1266{
3e2815e9 1267 int rc = X86EMUL_CONTINUE;
1c73ef66 1268
2dbd0dd7 1269 op->type = OP_MEM;
9dac77fa 1270 switch (ctxt->ad_bytes) {
1c73ef66 1271 case 2:
e85a1085 1272 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1273 break;
1274 case 4:
e85a1085 1275 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1276 break;
1277 case 8:
e85a1085 1278 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1279 break;
1280 }
1281done:
1282 return rc;
1283}
1284
9dac77fa 1285static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1286{
7129eeca 1287 long sv = 0, mask;
35c843c4 1288
9dac77fa 1289 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1290 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1291
9dac77fa
AK		 1292 if (ctxt->src.bytes == 2)
1293 sv = (s16)ctxt->src.val & (s16)mask;
1294 else if (ctxt->src.bytes == 4)
1295 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1296 else
1297 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1298
1c1c35ae
NA		 1299 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1300 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1301 }
ba7ff2b7
WY		 1302
1303 /* only subword offset */
9dac77fa 1304 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1305}
1306
dde7e6d1 1307static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1308 unsigned long addr, void *dest, unsigned size)
6aa8b732 1309{
dde7e6d1 1310 int rc;
9dac77fa 1311 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1312
f23b070e
XG		 1313 if (mc->pos < mc->end)
1314 goto read_cached;
6aa8b732 1315
f23b070e
XG		 1316 WARN_ON((mc->end + size) >= sizeof(mc->data));
1317
1318 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1319 &ctxt->exception);
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 mc->end += size;
1324
1325read_cached:
1326 memcpy(dest, mc->data + mc->pos, size);
1327 mc->pos += size;
dde7e6d1
AK		 1328 return X86EMUL_CONTINUE;
1329}
6aa8b732 1330
3ca3ac4d
AK		 1331static int segmented_read(struct x86_emulate_ctxt *ctxt,
1332 struct segmented_address addr,
1333 void *data,
1334 unsigned size)
1335{
9fa088f4
AK		 1336 int rc;
1337 ulong linear;
1338
83b8795a 1339 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
7b105ca2 1342 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1343}
1344
1345static int segmented_write(struct x86_emulate_ctxt *ctxt,
1346 struct segmented_address addr,
1347 const void *data,
1348 unsigned size)
1349{
9fa088f4
AK		 1350 int rc;
1351 ulong linear;
1352
83b8795a 1353 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1354 if (rc != X86EMUL_CONTINUE)
1355 return rc;
0f65dd70
AK		 1356 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1357 &ctxt->exception);
3ca3ac4d
AK		 1358}
1359
1360static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1361 struct segmented_address addr,
1362 const void *orig_data, const void *data,
1363 unsigned size)
1364{
9fa088f4
AK		 1365 int rc;
1366 ulong linear;
1367
83b8795a 1368 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1369 if (rc != X86EMUL_CONTINUE)
1370 return rc;
0f65dd70
AK		 1371 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1372 size, &ctxt->exception);
3ca3ac4d
AK		 1373}
1374
dde7e6d1 1375static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1376 unsigned int size, unsigned short port,
1377 void *dest)
1378{
9dac77fa 1379 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1380
dde7e6d1 1381 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1382 unsigned int in_page, n;
9dac77fa 1383 unsigned int count = ctxt->rep_prefix ?
dd856efa 1384 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1385 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1386 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1387 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1388 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1389 if (n == 0)
1390 n = 1;
1391 rc->pos = rc->end = 0;
7b105ca2 1392 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1393 return 0;
1394 rc->end = n * size;
6aa8b732
AK		 1395 }
1396
e6e39f04
NA		 1397 if (ctxt->rep_prefix && (ctxt->d & String) &&
1398 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1399 ctxt->dst.data = rc->data + rc->pos;
1400 ctxt->dst.type = OP_MEM_STR;
1401 ctxt->dst.count = (rc->end - rc->pos) / size;
1402 rc->pos = rc->end;
1403 } else {
1404 memcpy(dest, rc->data + rc->pos, size);
1405 rc->pos += size;
1406 }
dde7e6d1
AK		 1407 return 1;
1408}
6aa8b732 1409
7f3d35fd
KW		 1410static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1411 u16 index, struct desc_struct *desc)
1412{
1413 struct desc_ptr dt;
1414 ulong addr;
1415
1416 ctxt->ops->get_idt(ctxt, &dt);
1417
1418 if (dt.size < index * 8 + 7)
1419 return emulate_gp(ctxt, index << 3 | 0x2);
1420
1421 addr = dt.address + index * 8;
1422 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1423 &ctxt->exception);
1424}
1425
dde7e6d1 1426static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1427 u16 selector, struct desc_ptr *dt)
1428{
0225fb50 1429 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1430 u32 base3 = 0;
7b105ca2 1431
dde7e6d1
AK		 1432 if (selector & 1 << 2) {
1433 struct desc_struct desc;
1aa36616
AK		 1434 u16 sel;
1435
dde7e6d1 1436 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1437 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1438 VCPU_SREG_LDTR))
dde7e6d1 1439 return;
e09d082c 1440
dde7e6d1 1441 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1442 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1443 } else
4bff1e86 1444 ops->get_gdt(ctxt, dt);
dde7e6d1 1445}
120df890 1446
edccda7c
NA		 1447static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1448 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1449{
1450 struct desc_ptr dt;
1451 u16 index = selector >> 3;
dde7e6d1 1452 ulong addr;
120df890 1453
7b105ca2 1454 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1455
35d3d4a1
AK		 1456 if (dt.size < index * 8 + 7)
1457 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1458
edccda7c
NA		 1459 addr = dt.address + index * 8;
1460
1461#ifdef CONFIG_X86_64
1462 if (addr >> 32 != 0) {
1463 u64 efer = 0;
1464
1465 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1466 if (!(efer & EFER_LMA))
1467 addr &= (u32)-1;
1468 }
1469#endif
1470
1471 *desc_addr_p = addr;
1472 return X86EMUL_CONTINUE;
1473}
1474
1475/* allowed just for 8 bytes segments */
1476static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1477 u16 selector, struct desc_struct *desc,
1478 ulong *desc_addr_p)
1479{
1480 int rc;
1481
1482 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1483 if (rc != X86EMUL_CONTINUE)
1484 return rc;
1485
1486 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1487 &ctxt->exception);
dde7e6d1 1488}
ef65c889 1489
dde7e6d1
AK		 1490/* allowed just for 8 bytes segments */
1491static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1492 u16 selector, struct desc_struct *desc)
1493{
edccda7c 1494 int rc;
dde7e6d1 1495 ulong addr;
6aa8b732 1496
edccda7c
NA		 1497 rc = get_descriptor_ptr(ctxt, selector, &addr);
1498 if (rc != X86EMUL_CONTINUE)
1499 return rc;
6aa8b732 1500
7b105ca2
TY		 1501 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1502 &ctxt->exception);
dde7e6d1 1503}
c7e75a3d 1504
5601d05b 1505/* Does not support long mode */
2356aaeb 1506static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1507 u16 selector, int seg, u8 cpl,
3dc4bc4f 1508 enum x86_transfer_type transfer,
d1442d85 1509 struct desc_struct *desc)
dde7e6d1 1510{
869be99c 1511 struct desc_struct seg_desc, old_desc;
2356aaeb 1512 u8 dpl, rpl;
dde7e6d1
AK		 1513 unsigned err_vec = GP_VECTOR;
1514 u32 err_code = 0;
1515 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1516 ulong desc_addr;
dde7e6d1 1517 int ret;
03ebebeb 1518 u16 dummy;
e37a75a1 1519 u32 base3 = 0;
69f55cb1 1520
dde7e6d1 1521 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1522
f8da94e9
KW		 1523 if (ctxt->mode == X86EMUL_MODE_REAL) {
1524 /* set real mode segment descriptor (keep limit etc. for
1525 * unreal mode) */
03ebebeb 1526 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1527 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1528 goto load;
f8da94e9
KW		 1529 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1530 /* VM86 needs a clean new segment descriptor */
1531 set_desc_base(&seg_desc, selector << 4);
1532 set_desc_limit(&seg_desc, 0xffff);
1533 seg_desc.type = 3;
1534 seg_desc.p = 1;
1535 seg_desc.s = 1;
1536 seg_desc.dpl = 3;
1537 goto load;
dde7e6d1
AK		 1538 }
1539
79d5b4c3 1540 rpl = selector & 3;
79d5b4c3
AK		 1541
1542 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1543 if ((seg == VCPU_SREG_CS
1544 || (seg == VCPU_SREG_SS
1545 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1546 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1547 && null_selector)
1548 goto exception;
1549
1550 /* TR should be in GDT only */
1551 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1552 goto exception;
1553
1554 if (null_selector) /* for NULL selector skip all following checks */
1555 goto load;
1556
e919464b 1557 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1558 if (ret != X86EMUL_CONTINUE)
1559 return ret;
1560
1561 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1562 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1563 GP_VECTOR;
dde7e6d1 1564
fc058680 1565 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1566 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1567 if (transfer == X86_TRANSFER_CALL_JMP)
1568 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1569 goto exception;
3dc4bc4f 1570 }
dde7e6d1
AK		 1571
1572 if (!seg_desc.p) {
1573 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1574 goto exception;
1575 }
1576
dde7e6d1 1577 dpl = seg_desc.dpl;
dde7e6d1
AK		 1578
1579 switch (seg) {
1580 case VCPU_SREG_SS:
1581 /*
1582 * segment is not a writable data segment or segment
1583 * selector's RPL != CPL or segment selector's RPL != CPL
1584 */
1585 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1586 goto exception;
6aa8b732 1587 break;
dde7e6d1
AK		 1588 case VCPU_SREG_CS:
1589 if (!(seg_desc.type & 8))
1590 goto exception;
1591
1592 if (seg_desc.type & 4) {
1593 /* conforming */
1594 if (dpl > cpl)
1595 goto exception;
1596 } else {
1597 /* nonconforming */
1598 if (rpl > cpl || dpl != cpl)
1599 goto exception;
1600 }
040c8dc8
NA		 1601 /* in long-mode d/b must be clear if l is set */
1602 if (seg_desc.d && seg_desc.l) {
1603 u64 efer = 0;
1604
1605 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1606 if (efer & EFER_LMA)
1607 goto exception;
1608 }
1609
dde7e6d1
AK		 1610 /* CS(RPL) <- CPL */
1611 selector = (selector & 0xfffc) | cpl;
6aa8b732 1612 break;
dde7e6d1
AK		 1613 case VCPU_SREG_TR:
1614 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1615 goto exception;
869be99c
AK		 1616 old_desc = seg_desc;
1617 seg_desc.type |= 2; /* busy */
1618 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1619 sizeof(seg_desc), &ctxt->exception);
1620 if (ret != X86EMUL_CONTINUE)
1621 return ret;
dde7e6d1
AK		 1622 break;
1623 case VCPU_SREG_LDTR:
1624 if (seg_desc.s || seg_desc.type != 2)
1625 goto exception;
1626 break;
1627 default: /* DS, ES, FS, or GS */
4e62417b 1628 /*
dde7e6d1
AK		 1629 * segment is not a data or readable code segment or
1630 * ((segment is a data or nonconforming code segment)
1631 * and (both RPL and CPL > DPL))
4e62417b 1632 */
dde7e6d1
AK		 1633 if ((seg_desc.type & 0xa) == 0x8 ||
1634 (((seg_desc.type & 0xc) != 0xc) &&
1635 (rpl > dpl && cpl > dpl)))
1636 goto exception;
6aa8b732 1637 break;
dde7e6d1
AK		 1638 }
1639
1640 if (seg_desc.s) {
1641 /* mark segment as accessed */
e2cefa74
NA		 1642 if (!(seg_desc.type & 1)) {
1643 seg_desc.type |= 1;
1644 ret = write_segment_descriptor(ctxt, selector,
1645 &seg_desc);
1646 if (ret != X86EMUL_CONTINUE)
1647 return ret;
1648 }
e37a75a1
NA		 1649 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1650 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1651 sizeof(base3), &ctxt->exception);
1652 if (ret != X86EMUL_CONTINUE)
1653 return ret;
9a9abf6b
NA		 1654 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1655 ((u64)base3 << 32)))
1656 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1657 }
1658load:
e37a75a1 1659 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1660 if (desc)
1661 *desc = seg_desc;
dde7e6d1
AK		 1662 return X86EMUL_CONTINUE;
1663exception:
592f0858 1664 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1665}
1666
2356aaeb
PB		 1667static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1668 u16 selector, int seg)
1669{
1670 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1671 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1672 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1673}
1674
31be40b3
WY		 1675static void write_register_operand(struct operand *op)
1676{
1677 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1678 switch (op->bytes) {
1679 case 1:
1680 *(u8 *)op->addr.reg = (u8)op->val;
1681 break;
1682 case 2:
1683 *(u16 *)op->addr.reg = (u16)op->val;
1684 break;
1685 case 4:
1686 *op->addr.reg = (u32)op->val;
1687 break; /* 64b: zero-extend */
1688 case 8:
1689 *op->addr.reg = op->val;
1690 break;
1691 }
1692}
1693
fb32b1ed 1694static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1695{
fb32b1ed 1696 switch (op->type) {
dde7e6d1 1697 case OP_REG:
fb32b1ed 1698 write_register_operand(op);
6aa8b732 1699 break;
dde7e6d1 1700 case OP_MEM:
9dac77fa 1701 if (ctxt->lock_prefix)
f5f87dfb
PB		 1702 return segmented_cmpxchg(ctxt,
1703 op->addr.mem,
1704 &op->orig_val,
1705 &op->val,
1706 op->bytes);
1707 else
1708 return segmented_write(ctxt,
fb32b1ed 1709 op->addr.mem,
fb32b1ed
AK		 1710 &op->val,
1711 op->bytes);
a682e354 1712 break;
b3356bf0 1713 case OP_MEM_STR:
f5f87dfb
PB		 1714 return segmented_write(ctxt,
1715 op->addr.mem,
1716 op->data,
1717 op->bytes * op->count);
b3356bf0 1718 break;
1253791d 1719 case OP_XMM:
fb32b1ed 1720 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1721 break;
cbe2c9d3 1722 case OP_MM:
fb32b1ed 1723 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1724 break;
dde7e6d1
AK		 1725 case OP_NONE:
1726 /* no writeback */
414e6277 1727 break;
dde7e6d1 1728 default:
414e6277 1729 break;
6aa8b732 1730 }
dde7e6d1
AK		 1731 return X86EMUL_CONTINUE;
1732}
6aa8b732 1733
51ddff50 1734static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1735{
4179bb02 1736 struct segmented_address addr;
0dc8d10f 1737
5ad105e5 1738 rsp_increment(ctxt, -bytes);
dd856efa 1739 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1740 addr.seg = VCPU_SREG_SS;
1741
51ddff50
AK		 1742 return segmented_write(ctxt, addr, data, bytes);
1743}
1744
1745static int em_push(struct x86_emulate_ctxt *ctxt)
1746{
4179bb02 1747 /* Disable writeback. */
9dac77fa 1748 ctxt->dst.type = OP_NONE;
51ddff50 1749 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1750}
69f55cb1 1751
dde7e6d1 1752static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1753 void *dest, int len)
1754{
dde7e6d1 1755 int rc;
90de84f5 1756 struct segmented_address addr;
8b4caf66 1757
dd856efa 1758 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1759 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1760 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1761 if (rc != X86EMUL_CONTINUE)
1762 return rc;
1763
5ad105e5 1764 rsp_increment(ctxt, len);
dde7e6d1 1765 return rc;
8b4caf66
LV		 1766}
1767
c54fe504
TY		 1768static int em_pop(struct x86_emulate_ctxt *ctxt)
1769{
9dac77fa 1770 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1771}
1772
dde7e6d1 1773static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1774 void *dest, int len)
9de41573
GN		 1775{
1776 int rc;
dde7e6d1
AK		 1777 unsigned long val, change_mask;
1778 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1779 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1780
3b9be3bf 1781 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1782 if (rc != X86EMUL_CONTINUE)
1783 return rc;
9de41573 1784
dde7e6d1 1785 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1786 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1787
dde7e6d1
AK		 1788 switch(ctxt->mode) {
1789 case X86EMUL_MODE_PROT64:
1790 case X86EMUL_MODE_PROT32:
1791 case X86EMUL_MODE_PROT16:
1792 if (cpl == 0)
1793 change_mask |= EFLG_IOPL;
1794 if (cpl <= iopl)
1795 change_mask |= EFLG_IF;
1796 break;
1797 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1798 if (iopl < 3)
1799 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1800 change_mask |= EFLG_IF;
1801 break;
1802 default: /* real mode */
1803 change_mask |= (EFLG_IOPL | EFLG_IF);
1804 break;
9de41573 1805 }
dde7e6d1
AK		 1806
1807 *(unsigned long *)dest =
1808 (ctxt->eflags & ~change_mask) | (val & change_mask);
1809
1810 return rc;
9de41573
GN		 1811}
1812
62aaa2f0
TY		 1813static int em_popf(struct x86_emulate_ctxt *ctxt)
1814{
9dac77fa
AK		 1815 ctxt->dst.type = OP_REG;
1816 ctxt->dst.addr.reg = &ctxt->eflags;
1817 ctxt->dst.bytes = ctxt->op_bytes;
1818 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1819}
1820
612e89f0
AK		 1821static int em_enter(struct x86_emulate_ctxt *ctxt)
1822{
1823 int rc;
1824 unsigned frame_size = ctxt->src.val;
1825 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1826 ulong rbp;
612e89f0
AK		 1827
1828 if (nesting_level)
1829 return X86EMUL_UNHANDLEABLE;
1830
dd856efa
AK		 1831 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1832 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
dd856efa 1835 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1836 stack_mask(ctxt));
dd856efa
AK		 1837 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1838 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1839 stack_mask(ctxt));
1840 return X86EMUL_CONTINUE;
1841}
1842
f47cfa31
AK		 1843static int em_leave(struct x86_emulate_ctxt *ctxt)
1844{
dd856efa 1845 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1846 stack_mask(ctxt));
dd856efa 1847 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1848}
1849
1cd196ea 1850static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1851{
1cd196ea
AK		 1852 int seg = ctxt->src2.val;
1853
9dac77fa 1854 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1855 if (ctxt->op_bytes == 4) {
1856 rsp_increment(ctxt, -2);
1857 ctxt->op_bytes = 2;
1858 }
7b262e90 1859
4487b3b4 1860 return em_push(ctxt);
7b262e90
GN		 1861}
1862
1cd196ea 1863static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1864{
1cd196ea 1865 int seg = ctxt->src2.val;
dde7e6d1
AK		 1866 unsigned long selector;
1867 int rc;
38ba30ba 1868
3313bc4e 1869 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1870 if (rc != X86EMUL_CONTINUE)
1871 return rc;
1872
a5457e7b
PB		 1873 if (ctxt->modrm_reg == VCPU_SREG_SS)
1874 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1875 if (ctxt->op_bytes > 2)
1876 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1877
7b105ca2 1878 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1879 return rc;
38ba30ba
GN		 1880}
1881
b96a7fad 1882static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1883{
dd856efa 1884 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1885 int rc = X86EMUL_CONTINUE;
1886 int reg = VCPU_REGS_RAX;
38ba30ba 1887
dde7e6d1
AK		 1888 while (reg <= VCPU_REGS_RDI) {
1889 (reg == VCPU_REGS_RSP) ?
dd856efa 1890 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1891
4487b3b4 1892 rc = em_push(ctxt);
dde7e6d1
AK		 1893 if (rc != X86EMUL_CONTINUE)
1894 return rc;
38ba30ba 1895
dde7e6d1 1896 ++reg;
38ba30ba 1897 }
38ba30ba 1898
dde7e6d1 1899 return rc;
38ba30ba
GN		 1900}
1901
62aaa2f0
TY		 1902static int em_pushf(struct x86_emulate_ctxt *ctxt)
1903{
bc397a6c 1904 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1905 return em_push(ctxt);
1906}
1907
b96a7fad 1908static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1909{
dde7e6d1
AK		 1910 int rc = X86EMUL_CONTINUE;
1911 int reg = VCPU_REGS_RDI;
38ba30ba 1912
dde7e6d1
AK		 1913 while (reg >= VCPU_REGS_RAX) {
1914 if (reg == VCPU_REGS_RSP) {
5ad105e5 1915 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1916 --reg;
1917 }
38ba30ba 1918
dd856efa 1919 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1920 if (rc != X86EMUL_CONTINUE)
1921 break;
1922 --reg;
38ba30ba 1923 }
dde7e6d1 1924 return rc;
38ba30ba
GN		 1925}
1926
dd856efa 1927static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1928{
0225fb50 1929 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1930 int rc;
6e154e56
MG		 1931 struct desc_ptr dt;
1932 gva_t cs_addr;
1933 gva_t eip_addr;
1934 u16 cs, eip;
6e154e56
MG		 1935
1936 /* TODO: Add limit checks */
9dac77fa 1937 ctxt->src.val = ctxt->eflags;
4487b3b4 1938 rc = em_push(ctxt);
5c56e1cf
AK		 1939 if (rc != X86EMUL_CONTINUE)
1940 return rc;
6e154e56
MG		 1941
1942 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1943
9dac77fa 1944 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1945 rc = em_push(ctxt);
5c56e1cf
AK		 1946 if (rc != X86EMUL_CONTINUE)
1947 return rc;
6e154e56 1948
9dac77fa 1949 ctxt->src.val = ctxt->_eip;
4487b3b4 1950 rc = em_push(ctxt);
5c56e1cf
AK		 1951 if (rc != X86EMUL_CONTINUE)
1952 return rc;
1953
4bff1e86 1954 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1955
1956 eip_addr = dt.address + (irq << 2);
1957 cs_addr = dt.address + (irq << 2) + 2;
1958
0f65dd70 1959 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1960 if (rc != X86EMUL_CONTINUE)
1961 return rc;
1962
0f65dd70 1963 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1964 if (rc != X86EMUL_CONTINUE)
1965 return rc;
1966
7b105ca2 1967 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1968 if (rc != X86EMUL_CONTINUE)
1969 return rc;
1970
9dac77fa 1971 ctxt->_eip = eip;
6e154e56
MG		 1972
1973 return rc;
1974}
1975
dd856efa
AK		 1976int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1977{
1978 int rc;
1979
1980 invalidate_registers(ctxt);
1981 rc = __emulate_int_real(ctxt, irq);
1982 if (rc == X86EMUL_CONTINUE)
1983 writeback_registers(ctxt);
1984 return rc;
1985}
1986
7b105ca2 1987static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1988{
1989 switch(ctxt->mode) {
1990 case X86EMUL_MODE_REAL:
dd856efa 1991 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1992 case X86EMUL_MODE_VM86:
1993 case X86EMUL_MODE_PROT16:
1994 case X86EMUL_MODE_PROT32:
1995 case X86EMUL_MODE_PROT64:
1996 default:
1997 /* Protected mode interrupts unimplemented yet */
1998 return X86EMUL_UNHANDLEABLE;
1999 }
2000}
2001
7b105ca2 2002static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2003{
dde7e6d1
AK		 2004 int rc = X86EMUL_CONTINUE;
2005 unsigned long temp_eip = 0;
2006 unsigned long temp_eflags = 0;
2007 unsigned long cs = 0;
2008 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2009 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2010 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2011 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 2012
dde7e6d1 2013 /* TODO: Add stack limit check */
38ba30ba 2014
9dac77fa 2015 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2016
dde7e6d1
AK		 2017 if (rc != X86EMUL_CONTINUE)
2018 return rc;
38ba30ba 2019
35d3d4a1
AK		 2020 if (temp_eip & ~0xffff)
2021 return emulate_gp(ctxt, 0);
38ba30ba 2022
9dac77fa 2023 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2024
dde7e6d1
AK		 2025 if (rc != X86EMUL_CONTINUE)
2026 return rc;
38ba30ba 2027
9dac77fa 2028 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2029
dde7e6d1
AK		 2030 if (rc != X86EMUL_CONTINUE)
2031 return rc;
38ba30ba 2032
7b105ca2 2033 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2034
dde7e6d1
AK		 2035 if (rc != X86EMUL_CONTINUE)
2036 return rc;
38ba30ba 2037
9dac77fa 2038 ctxt->_eip = temp_eip;
38ba30ba 2039
38ba30ba 2040
9dac77fa 2041 if (ctxt->op_bytes == 4)
dde7e6d1 2042 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2043 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2044 ctxt->eflags &= ~0xffff;
2045 ctxt->eflags |= temp_eflags;
38ba30ba 2046 }
dde7e6d1
AK		 2047
2048 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2049 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2050
2051 return rc;
38ba30ba
GN		 2052}
2053
e01991e7 2054static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2055{
dde7e6d1
AK		 2056 switch(ctxt->mode) {
2057 case X86EMUL_MODE_REAL:
7b105ca2 2058 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2059 case X86EMUL_MODE_VM86:
2060 case X86EMUL_MODE_PROT16:
2061 case X86EMUL_MODE_PROT32:
2062 case X86EMUL_MODE_PROT64:
c37eda13 2063 default:
dde7e6d1
AK		 2064 /* iret from protected mode unimplemented yet */
2065 return X86EMUL_UNHANDLEABLE;
c37eda13 2066 }
c37eda13
WY		 2067}
2068
d2f62766
TY		 2069static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2070{
d2f62766 2071 int rc;
d1442d85
NA		 2072 unsigned short sel, old_sel;
2073 struct desc_struct old_desc, new_desc;
2074 const struct x86_emulate_ops *ops = ctxt->ops;
2075 u8 cpl = ctxt->ops->cpl(ctxt);
2076
2077 /* Assignment of RIP may only fail in 64-bit mode */
2078 if (ctxt->mode == X86EMUL_MODE_PROT64)
2079 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2080 VCPU_SREG_CS);
d2f62766 2081
9dac77fa 2082 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2083
3dc4bc4f
NA		 2084 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2085 X86_TRANSFER_CALL_JMP,
d1442d85 2086 &new_desc);
d2f62766
TY		 2087 if (rc != X86EMUL_CONTINUE)
2088 return rc;
2089
d50eaa18 2090 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2091 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2092 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2093 /* assigning eip failed; restore the old cs */
2094 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2095 return rc;
2096 }
2097 return rc;
d2f62766
TY		 2098}
2099
f7784046 2100static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2101{
f7784046
NA		 2102 return assign_eip_near(ctxt, ctxt->src.val);
2103}
8cdbd2c9 2104
f7784046
NA		 2105static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2106{
2107 int rc;
2108 long int old_eip;
2109
2110 old_eip = ctxt->_eip;
2111 rc = assign_eip_near(ctxt, ctxt->src.val);
2112 if (rc != X86EMUL_CONTINUE)
2113 return rc;
2114 ctxt->src.val = old_eip;
2115 rc = em_push(ctxt);
4179bb02 2116 return rc;
8cdbd2c9
LV		 2117}
2118
e0dac408 2119static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2120{
9dac77fa 2121 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2122
aaa05f24
NA		 2123 if (ctxt->dst.bytes == 16)
2124 return X86EMUL_UNHANDLEABLE;
2125
dd856efa
AK		 2126 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2127 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2128 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2129 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2130 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2131 } else {
dd856efa
AK		 2132 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2133 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2134
05f086f8 2135 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2136 }
1b30eaa8 2137 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2138}
2139
ebda02c2
TY		 2140static int em_ret(struct x86_emulate_ctxt *ctxt)
2141{
234f3ce4
NA		 2142 int rc;
2143 unsigned long eip;
2144
2145 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2146 if (rc != X86EMUL_CONTINUE)
2147 return rc;
2148
2149 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2150}
2151
e01991e7 2152static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2153{
a77ab5ea 2154 int rc;
d1442d85
NA		 2155 unsigned long eip, cs;
2156 u16 old_cs;
9e8919ae 2157 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2158 struct desc_struct old_desc, new_desc;
2159 const struct x86_emulate_ops *ops = ctxt->ops;
2160
2161 if (ctxt->mode == X86EMUL_MODE_PROT64)
2162 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2163 VCPU_SREG_CS);
a77ab5ea 2164
d1442d85 2165 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2166 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2167 return rc;
9dac77fa 2168 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2169 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2170 return rc;
9e8919ae
NA		 2171 /* Outer-privilege level return is not implemented */
2172 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2173 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2174 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2175 X86_TRANSFER_RET,
d1442d85
NA		 2176 &new_desc);
2177 if (rc != X86EMUL_CONTINUE)
2178 return rc;
d50eaa18 2179 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2180 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2181 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2182 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2183 }
a77ab5ea
AK		 2184 return rc;
2185}
2186
3261107e
BR		 2187static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2188{
2189 int rc;
2190
2191 rc = em_ret_far(ctxt);
2192 if (rc != X86EMUL_CONTINUE)
2193 return rc;
2194 rsp_increment(ctxt, ctxt->src.val);
2195 return X86EMUL_CONTINUE;
2196}
2197
e940b5c2
TY		 2198static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2199{
2200 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2201 ctxt->dst.orig_val = ctxt->dst.val;
2202 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2203 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2204 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2205 fastop(ctxt, em_cmp);
e940b5c2
TY		 2206
2207 if (ctxt->eflags & EFLG_ZF) {
2208 /* Success: write back to memory. */
2209 ctxt->dst.val = ctxt->src.orig_val;
2210 } else {
2211 /* Failure: write the value we saw to EAX. */
2212 ctxt->dst.type = OP_REG;
dd856efa 2213 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2214 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2215 }
2216 return X86EMUL_CONTINUE;
2217}
2218
d4b4325f 2219static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2220{
d4b4325f 2221 int seg = ctxt->src2.val;
09b5f4d3
WY		 2222 unsigned short sel;
2223 int rc;
2224
9dac77fa 2225 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2226
7b105ca2 2227 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2228 if (rc != X86EMUL_CONTINUE)
2229 return rc;
2230
9dac77fa 2231 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2232 return rc;
2233}
2234
7b105ca2 2235static void
e66bb2cc 2236setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2237 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2238{
e66bb2cc 2239 cs->l = 0; /* will be adjusted later */
79168fd1 2240 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2241 cs->g = 1; /* 4kb granularity */
79168fd1 2242 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2243 cs->type = 0x0b; /* Read, Execute, Accessed */
2244 cs->s = 1;
2245 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2246 cs->p = 1;
2247 cs->d = 1;
99245b50 2248 cs->avl = 0;
e66bb2cc 2249
79168fd1
GN		 2250 set_desc_base(ss, 0); /* flat segment */
2251 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2252 ss->g = 1; /* 4kb granularity */
2253 ss->s = 1;
2254 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2255 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2256 ss->dpl = 0;
79168fd1 2257 ss->p = 1;
99245b50
GN		 2258 ss->l = 0;
2259 ss->avl = 0;
e66bb2cc
AP		 2260}
2261
1a18a69b
AK		 2262static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2263{
2264 u32 eax, ebx, ecx, edx;
2265
2266 eax = ecx = 0;
0017f93a
AK		 2267 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2268 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2269 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2270 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2271}
2272
c2226fc9
SB		 2273static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2274{
0225fb50 2275 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2276 u32 eax, ebx, ecx, edx;
2277
2278 /*
2279 * syscall should always be enabled in longmode - so only become
2280 * vendor specific (cpuid) if other modes are active...
2281 */
2282 if (ctxt->mode == X86EMUL_MODE_PROT64)
2283 return true;
2284
2285 eax = 0x00000000;
2286 ecx = 0x00000000;
0017f93a
AK		 2287 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2288 /*
2289 * Intel ("GenuineIntel")
2290 * remark: Intel CPUs only support "syscall" in 64bit
2291 * longmode. Also an 64bit guest with a
2292 * 32bit compat-app running will #UD !! While this
2293 * behaviour can be fixed (by emulating) into AMD
2294 * response - CPUs of AMD can't behave like Intel.
2295 */
2296 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2297 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2298 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2299 return false;
2300
2301 /* AMD ("AuthenticAMD") */
2302 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2303 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2304 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2305 return true;
2306
2307 /* AMD ("AMDisbetter!") */
2308 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2309 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2310 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2311 return true;
c2226fc9
SB		 2312
2313 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2314 return false;
2315}
2316
e01991e7 2317static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2318{
0225fb50 2319 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2320 struct desc_struct cs, ss;
e66bb2cc 2321 u64 msr_data;
79168fd1 2322 u16 cs_sel, ss_sel;
c2ad2bb3 2323 u64 efer = 0;
e66bb2cc
AP		 2324
2325 /* syscall is not available in real mode */
2e901c4c 2326 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2327 ctxt->mode == X86EMUL_MODE_VM86)
2328 return emulate_ud(ctxt);
e66bb2cc 2329
c2226fc9
SB		 2330 if (!(em_syscall_is_enabled(ctxt)))
2331 return emulate_ud(ctxt);
2332
c2ad2bb3 2333 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2334 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2335
c2226fc9
SB		 2336 if (!(efer & EFER_SCE))
2337 return emulate_ud(ctxt);
2338
717746e3 2339 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2340 msr_data >>= 32;
79168fd1
GN		 2341 cs_sel = (u16)(msr_data & 0xfffc);
2342 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2343
c2ad2bb3 2344 if (efer & EFER_LMA) {
79168fd1 2345 cs.d = 0;
e66bb2cc
AP		 2346 cs.l = 1;
2347 }
1aa36616
AK		 2348 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2349 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2350
dd856efa 2351 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2352 if (efer & EFER_LMA) {
e66bb2cc 2353#ifdef CONFIG_X86_64
6c6cb69b 2354 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2355
717746e3 2356 ops->get_msr(ctxt,
3fb1b5db
GN		 2357 ctxt->mode == X86EMUL_MODE_PROT64 ?
2358 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2359 ctxt->_eip = msr_data;
e66bb2cc 2360
717746e3 2361 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2362 ctxt->eflags &= ~msr_data;
807c1425 2363 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2364#endif
2365 } else {
2366 /* legacy mode */
717746e3 2367 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2368 ctxt->_eip = (u32)msr_data;
e66bb2cc 2369
6c6cb69b 2370 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2371 }
2372
e54cfa97 2373 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2374}
2375
e01991e7 2376static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2377{
0225fb50 2378 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2379 struct desc_struct cs, ss;
8c604352 2380 u64 msr_data;
79168fd1 2381 u16 cs_sel, ss_sel;
c2ad2bb3 2382 u64 efer = 0;
8c604352 2383
7b105ca2 2384 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2385 /* inject #GP if in real mode */
35d3d4a1
AK		 2386 if (ctxt->mode == X86EMUL_MODE_REAL)
2387 return emulate_gp(ctxt, 0);
8c604352 2388
1a18a69b
AK		 2389 /*
2390 * Not recognized on AMD in compat mode (but is recognized in legacy
2391 * mode).
2392 */
2393 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2394 && !vendor_intel(ctxt))
2395 return emulate_ud(ctxt);
2396
b2c9d43e 2397 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2398 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2399 return X86EMUL_UNHANDLEABLE;
8c604352 2400
7b105ca2 2401 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2402
717746e3 2403 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2404 switch (ctxt->mode) {
2405 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2406 if ((msr_data & 0xfffc) == 0x0)
2407 return emulate_gp(ctxt, 0);
8c604352
AP		 2408 break;
2409 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2410 if (msr_data == 0x0)
2411 return emulate_gp(ctxt, 0);
8c604352 2412 break;
9d1b39a9
GN		 2413 default:
2414 break;
8c604352
AP		 2415 }
2416
6c6cb69b 2417 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2418 cs_sel = (u16)msr_data;
2419 cs_sel &= ~SELECTOR_RPL_MASK;
2420 ss_sel = cs_sel + 8;
2421 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2422 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2423 cs.d = 0;
8c604352
AP		 2424 cs.l = 1;
2425 }
2426
1aa36616
AK		 2427 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2428 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2429
717746e3 2430 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2431 ctxt->_eip = msr_data;
8c604352 2432
717746e3 2433 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2434 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2435
e54cfa97 2436 return X86EMUL_CONTINUE;
8c604352
AP		 2437}
2438
e01991e7 2439static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2440{
0225fb50 2441 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2442 struct desc_struct cs, ss;
234f3ce4 2443 u64 msr_data, rcx, rdx;
4668f050 2444 int usermode;
1249b96e 2445 u16 cs_sel = 0, ss_sel = 0;
4668f050 2446
a0044755
GN		 2447 /* inject #GP if in real mode or Virtual 8086 mode */
2448 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2449 ctxt->mode == X86EMUL_MODE_VM86)
2450 return emulate_gp(ctxt, 0);
4668f050 2451
7b105ca2 2452 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2453
9dac77fa 2454 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2455 usermode = X86EMUL_MODE_PROT64;
2456 else
2457 usermode = X86EMUL_MODE_PROT32;
2458
234f3ce4
NA		 2459 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2460 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2461
4668f050
AP		 2462 cs.dpl = 3;
2463 ss.dpl = 3;
717746e3 2464 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2465 switch (usermode) {
2466 case X86EMUL_MODE_PROT32:
79168fd1 2467 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2468 if ((msr_data & 0xfffc) == 0x0)
2469 return emulate_gp(ctxt, 0);
79168fd1 2470 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2471 rcx = (u32)rcx;
2472 rdx = (u32)rdx;
4668f050
AP		 2473 break;
2474 case X86EMUL_MODE_PROT64:
79168fd1 2475 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2476 if (msr_data == 0x0)
2477 return emulate_gp(ctxt, 0);
79168fd1
GN		 2478 ss_sel = cs_sel + 8;
2479 cs.d = 0;
4668f050 2480 cs.l = 1;
234f3ce4
NA		 2481 if (is_noncanonical_address(rcx) ||
2482 is_noncanonical_address(rdx))
2483 return emulate_gp(ctxt, 0);
4668f050
AP		 2484 break;
2485 }
79168fd1
GN		 2486 cs_sel |= SELECTOR_RPL_MASK;
2487 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2488
1aa36616
AK		 2489 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2490 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2491
234f3ce4
NA		 2492 ctxt->_eip = rdx;
2493 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2494
e54cfa97 2495 return X86EMUL_CONTINUE;
4668f050
AP		 2496}
2497
7b105ca2 2498static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2499{
2500 int iopl;
2501 if (ctxt->mode == X86EMUL_MODE_REAL)
2502 return false;
2503 if (ctxt->mode == X86EMUL_MODE_VM86)
2504 return true;
2505 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2506 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2507}
2508
2509static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2510 u16 port, u16 len)
2511{
0225fb50 2512 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2513 struct desc_struct tr_seg;
5601d05b 2514 u32 base3;
f850e2e6 2515 int r;
1aa36616 2516 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2517 unsigned mask = (1 << len) - 1;
5601d05b 2518 unsigned long base;
f850e2e6 2519
1aa36616 2520 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2521 if (!tr_seg.p)
f850e2e6 2522 return false;
79168fd1 2523 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2524 return false;
5601d05b
GN		 2525 base = get_desc_base(&tr_seg);
2526#ifdef CONFIG_X86_64
2527 base |= ((u64)base3) << 32;
2528#endif
0f65dd70 2529 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2530 if (r != X86EMUL_CONTINUE)
2531 return false;
79168fd1 2532 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2533 return false;
0f65dd70 2534 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2535 if (r != X86EMUL_CONTINUE)
2536 return false;
2537 if ((perm >> bit_idx) & mask)
2538 return false;
2539 return true;
2540}
2541
2542static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2543 u16 port, u16 len)
2544{
4fc40f07
GN		 2545 if (ctxt->perm_ok)
2546 return true;
2547
7b105ca2
TY		 2548 if (emulator_bad_iopl(ctxt))
2549 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2550 return false;
4fc40f07
GN		 2551
2552 ctxt->perm_ok = true;
2553
f850e2e6
GN		 2554 return true;
2555}
2556
38ba30ba 2557static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2558 struct tss_segment_16 *tss)
2559{
9dac77fa 2560 tss->ip = ctxt->_eip;
38ba30ba 2561 tss->flag = ctxt->eflags;
dd856efa
AK		 2562 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2563 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2564 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2565 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2566 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2567 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2568 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2569 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2570
1aa36616
AK		 2571 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2572 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2573 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2574 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2575 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2576}
2577
2578static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2579 struct tss_segment_16 *tss)
2580{
38ba30ba 2581 int ret;
2356aaeb 2582 u8 cpl;
38ba30ba 2583
9dac77fa 2584 ctxt->_eip = tss->ip;
38ba30ba 2585 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2586 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2587 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2588 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2589 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2590 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2591 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2592 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2593 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2594
2595 /*
2596 * SDM says that segment selectors are loaded before segment
2597 * descriptors
2598 */
1aa36616
AK		 2599 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2600 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2601 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2602 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2603 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2604
2356aaeb
PB		 2605 cpl = tss->cs & 3;
2606
38ba30ba 2607 /*
fc058680 2608 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2609 * it is handled in a context of new task
2610 */
d1442d85 2611 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2612 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2613 if (ret != X86EMUL_CONTINUE)
2614 return ret;
d1442d85 2615 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2616 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
d1442d85 2619 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2620 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
d1442d85 2623 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2624 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2625 if (ret != X86EMUL_CONTINUE)
2626 return ret;
d1442d85 2627 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2628 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2629 if (ret != X86EMUL_CONTINUE)
2630 return ret;
2631
2632 return X86EMUL_CONTINUE;
2633}
2634
2635static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2636 u16 tss_selector, u16 old_tss_sel,
2637 ulong old_tss_base, struct desc_struct *new_desc)
2638{
0225fb50 2639 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2640 struct tss_segment_16 tss_seg;
2641 int ret;
bcc55cba 2642 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2643
0f65dd70 2644 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2645 &ctxt->exception);
db297e3d 2646 if (ret != X86EMUL_CONTINUE)
38ba30ba 2647 return ret;
38ba30ba 2648
7b105ca2 2649 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2650
0f65dd70 2651 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2652 &ctxt->exception);
db297e3d 2653 if (ret != X86EMUL_CONTINUE)
38ba30ba 2654 return ret;
38ba30ba 2655
0f65dd70 2656 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2657 &ctxt->exception);
db297e3d 2658 if (ret != X86EMUL_CONTINUE)
38ba30ba 2659 return ret;
38ba30ba
GN		 2660
2661 if (old_tss_sel != 0xffff) {
2662 tss_seg.prev_task_link = old_tss_sel;
2663
0f65dd70 2664 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2665 &tss_seg.prev_task_link,
2666 sizeof tss_seg.prev_task_link,
0f65dd70 2667 &ctxt->exception);
db297e3d 2668 if (ret != X86EMUL_CONTINUE)
38ba30ba 2669 return ret;
38ba30ba
GN		 2670 }
2671
7b105ca2 2672 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2673}
2674
2675static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2676 struct tss_segment_32 *tss)
2677{
5c7411e2 2678 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2679 tss->eip = ctxt->_eip;
38ba30ba 2680 tss->eflags = ctxt->eflags;
dd856efa
AK		 2681 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2682 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2683 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2684 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2685 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2686 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2687 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2688 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2689
1aa36616
AK		 2690 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2691 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2692 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2693 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2694 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2695 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2696}
2697
2698static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2699 struct tss_segment_32 *tss)
2700{
38ba30ba 2701 int ret;
2356aaeb 2702 u8 cpl;
38ba30ba 2703
7b105ca2 2704 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2705 return emulate_gp(ctxt, 0);
9dac77fa 2706 ctxt->_eip = tss->eip;
38ba30ba 2707 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2708
2709 /* General purpose registers */
dd856efa
AK		 2710 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2711 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2712 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2713 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2714 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2715 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2716 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2717 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2718
2719 /*
2720 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2721 * descriptors. This is important because CPL checks will
2722 * use CS.RPL.
38ba30ba 2723 */
1aa36616
AK		 2724 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2725 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2726 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2727 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2728 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2729 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2730 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2731
4cee4798
KW		 2732 /*
2733 * If we're switching between Protected Mode and VM86, we need to make
2734 * sure to update the mode before loading the segment descriptors so
2735 * that the selectors are interpreted correctly.
4cee4798 2736 */
2356aaeb 2737 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2738 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2739 cpl = 3;
2740 } else {
4cee4798 2741 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2742 cpl = tss->cs & 3;
2743 }
4cee4798 2744
38ba30ba
GN		 2745 /*
2746 * Now load segment descriptors. If fault happenes at this stage
2747 * it is handled in a context of new task
2748 */
d1442d85 2749 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2750 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2751 if (ret != X86EMUL_CONTINUE)
2752 return ret;
d1442d85 2753 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2754 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2755 if (ret != X86EMUL_CONTINUE)
2756 return ret;
d1442d85 2757 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2758 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2759 if (ret != X86EMUL_CONTINUE)
2760 return ret;
d1442d85 2761 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2762 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2763 if (ret != X86EMUL_CONTINUE)
2764 return ret;
d1442d85 2765 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2766 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2767 if (ret != X86EMUL_CONTINUE)
2768 return ret;
d1442d85 2769 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2770 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2771 if (ret != X86EMUL_CONTINUE)
2772 return ret;
d1442d85 2773 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2774 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2775 if (ret != X86EMUL_CONTINUE)
2776 return ret;
2777
2778 return X86EMUL_CONTINUE;
2779}
2780
2781static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2782 u16 tss_selector, u16 old_tss_sel,
2783 ulong old_tss_base, struct desc_struct *new_desc)
2784{
0225fb50 2785 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2786 struct tss_segment_32 tss_seg;
2787 int ret;
bcc55cba 2788 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2789 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2790 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2791
0f65dd70 2792 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2793 &ctxt->exception);
db297e3d 2794 if (ret != X86EMUL_CONTINUE)
38ba30ba 2795 return ret;
38ba30ba 2796
7b105ca2 2797 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2798
5c7411e2
NA		 2799 /* Only GP registers and segment selectors are saved */
2800 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2801 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2802 if (ret != X86EMUL_CONTINUE)
38ba30ba 2803 return ret;
38ba30ba 2804
0f65dd70 2805 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2806 &ctxt->exception);
db297e3d 2807 if (ret != X86EMUL_CONTINUE)
38ba30ba 2808 return ret;
38ba30ba
GN		 2809
2810 if (old_tss_sel != 0xffff) {
2811 tss_seg.prev_task_link = old_tss_sel;
2812
0f65dd70 2813 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2814 &tss_seg.prev_task_link,
2815 sizeof tss_seg.prev_task_link,
0f65dd70 2816 &ctxt->exception);
db297e3d 2817 if (ret != X86EMUL_CONTINUE)
38ba30ba 2818 return ret;
38ba30ba
GN		 2819 }
2820
7b105ca2 2821 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2822}
2823
2824static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2825 u16 tss_selector, int idt_index, int reason,
e269fb21 2826 bool has_error_code, u32 error_code)
38ba30ba 2827{
0225fb50 2828 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2829 struct desc_struct curr_tss_desc, next_tss_desc;
2830 int ret;
1aa36616 2831 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2832 ulong old_tss_base =
4bff1e86 2833 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2834 u32 desc_limit;
e919464b 2835 ulong desc_addr;
38ba30ba
GN		 2836
2837 /* FIXME: old_tss_base == ~0 ? */
2838
e919464b 2839 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2840 if (ret != X86EMUL_CONTINUE)
2841 return ret;
e919464b 2842 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2843 if (ret != X86EMUL_CONTINUE)
2844 return ret;
2845
2846 /* FIXME: check that next_tss_desc is tss */
2847
7f3d35fd
KW		 2848 /*
2849 * Check privileges. The three cases are task switch caused by...
2850 *
2851 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2852 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2853 * 3. jmp/call to TSS/task-gate: No check is performed since the
2854 * hardware checks it before exiting.
7f3d35fd
KW		 2855 */
2856 if (reason == TASK_SWITCH_GATE) {
2857 if (idt_index != -1) {
2858 /* Software interrupts */
2859 struct desc_struct task_gate_desc;
2860 int dpl;
2861
2862 ret = read_interrupt_descriptor(ctxt, idt_index,
2863 &task_gate_desc);
2864 if (ret != X86EMUL_CONTINUE)
2865 return ret;
2866
2867 dpl = task_gate_desc.dpl;
2868 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2869 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2870 }
38ba30ba
GN		 2871 }
2872
ceffb459
GN		 2873 desc_limit = desc_limit_scaled(&next_tss_desc);
2874 if (!next_tss_desc.p ||
2875 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2876 desc_limit < 0x2b)) {
592f0858 2877 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2878 }
2879
2880 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2881 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2882 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2883 }
2884
2885 if (reason == TASK_SWITCH_IRET)
2886 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2887
2888 /* set back link to prev task only if NT bit is set in eflags
fc058680 2889 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2890 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2891 old_tss_sel = 0xffff;
2892
2893 if (next_tss_desc.type & 8)
7b105ca2 2894 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2895 old_tss_base, &next_tss_desc);
2896 else
7b105ca2 2897 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2898 old_tss_base, &next_tss_desc);
0760d448
JK		 2899 if (ret != X86EMUL_CONTINUE)
2900 return ret;
38ba30ba
GN		 2901
2902 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2903 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2904
2905 if (reason != TASK_SWITCH_IRET) {
2906 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2907 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2908 }
2909
717746e3 2910 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2911 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2912
e269fb21 2913 if (has_error_code) {
9dac77fa
AK		 2914 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2915 ctxt->lock_prefix = 0;
2916 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2917 ret = em_push(ctxt);
e269fb21
JK		 2918 }
2919
38ba30ba
GN		 2920 return ret;
2921}
2922
2923int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2924 u16 tss_selector, int idt_index, int reason,
e269fb21 2925 bool has_error_code, u32 error_code)
38ba30ba 2926{
38ba30ba
GN		 2927 int rc;
2928
dd856efa 2929 invalidate_registers(ctxt);
9dac77fa
AK		 2930 ctxt->_eip = ctxt->eip;
2931 ctxt->dst.type = OP_NONE;
38ba30ba 2932
7f3d35fd 2933 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2934 has_error_code, error_code);
38ba30ba 2935
dd856efa 2936 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2937 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2938 writeback_registers(ctxt);
2939 }
38ba30ba 2940
a0c0ab2f 2941 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2942}
2943
f3bd64c6
GN		 2944static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2945 struct operand *op)
a682e354 2946{
b3356bf0 2947 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2948
01485a22
PB		 2949 register_address_increment(ctxt, reg, df * op->bytes);
2950 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2951}
2952
7af04fc0
AK		 2953static int em_das(struct x86_emulate_ctxt *ctxt)
2954{
7af04fc0
AK		 2955 u8 al, old_al;
2956 bool af, cf, old_cf;
2957
2958 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2959 al = ctxt->dst.val;
7af04fc0
AK		 2960
2961 old_al = al;
2962 old_cf = cf;
2963 cf = false;
2964 af = ctxt->eflags & X86_EFLAGS_AF;
2965 if ((al & 0x0f) > 9 || af) {
2966 al -= 6;
2967 cf = old_cf | (al >= 250);
2968 af = true;
2969 } else {
2970 af = false;
2971 }
2972 if (old_al > 0x99 || old_cf) {
2973 al -= 0x60;
2974 cf = true;
2975 }
2976
9dac77fa 2977 ctxt->dst.val = al;
7af04fc0 2978 /* Set PF, ZF, SF */
9dac77fa
AK		 2979 ctxt->src.type = OP_IMM;
2980 ctxt->src.val = 0;
2981 ctxt->src.bytes = 1;
158de57f 2982 fastop(ctxt, em_or);
7af04fc0
AK		 2983 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2984 if (cf)
2985 ctxt->eflags |= X86_EFLAGS_CF;
2986 if (af)
2987 ctxt->eflags |= X86_EFLAGS_AF;
2988 return X86EMUL_CONTINUE;
2989}
2990
a035d5c6
PB		 2991static int em_aam(struct x86_emulate_ctxt *ctxt)
2992{
2993 u8 al, ah;
2994
2995 if (ctxt->src.val == 0)
2996 return emulate_de(ctxt);
2997
2998 al = ctxt->dst.val & 0xff;
2999 ah = al / ctxt->src.val;
3000 al %= ctxt->src.val;
3001
3002 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3003
3004 /* Set PF, ZF, SF */
3005 ctxt->src.type = OP_IMM;
3006 ctxt->src.val = 0;
3007 ctxt->src.bytes = 1;
3008 fastop(ctxt, em_or);
3009
3010 return X86EMUL_CONTINUE;
3011}
3012
7f662273
GN		 3013static int em_aad(struct x86_emulate_ctxt *ctxt)
3014{
3015 u8 al = ctxt->dst.val & 0xff;
3016 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3017
3018 al = (al + (ah * ctxt->src.val)) & 0xff;
3019
3020 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3021
f583c29b
GN		 3022 /* Set PF, ZF, SF */
3023 ctxt->src.type = OP_IMM;
3024 ctxt->src.val = 0;
3025 ctxt->src.bytes = 1;
3026 fastop(ctxt, em_or);
7f662273
GN		 3027
3028 return X86EMUL_CONTINUE;
3029}
3030
d4ddafcd
TY		 3031static int em_call(struct x86_emulate_ctxt *ctxt)
3032{
234f3ce4 3033 int rc;
d4ddafcd
TY		 3034 long rel = ctxt->src.val;
3035
3036 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3037 rc = jmp_rel(ctxt, rel);
3038 if (rc != X86EMUL_CONTINUE)
3039 return rc;
d4ddafcd
TY		 3040 return em_push(ctxt);
3041}
3042
0ef753b8
AK		 3043static int em_call_far(struct x86_emulate_ctxt *ctxt)
3044{
0ef753b8
AK		 3045 u16 sel, old_cs;
3046 ulong old_eip;
3047 int rc;
d1442d85
NA		 3048 struct desc_struct old_desc, new_desc;
3049 const struct x86_emulate_ops *ops = ctxt->ops;
3050 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3051
9dac77fa 3052 old_eip = ctxt->_eip;
d1442d85 3053 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3054
9dac77fa 3055 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3056 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3057 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3058 if (rc != X86EMUL_CONTINUE)
80976dbb 3059 return rc;
0ef753b8 3060
d50eaa18 3061 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3062 if (rc != X86EMUL_CONTINUE)
3063 goto fail;
0ef753b8 3064
9dac77fa 3065 ctxt->src.val = old_cs;
4487b3b4 3066 rc = em_push(ctxt);
0ef753b8 3067 if (rc != X86EMUL_CONTINUE)
d1442d85 3068 goto fail;
0ef753b8 3069
9dac77fa 3070 ctxt->src.val = old_eip;
d1442d85
NA		 3071 rc = em_push(ctxt);
3072 /* If we failed, we tainted the memory, but the very least we should
3073 restore cs */
3074 if (rc != X86EMUL_CONTINUE)
3075 goto fail;
3076 return rc;
3077fail:
3078 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3079 return rc;
3080
0ef753b8
AK		 3081}
3082
40ece7c7
AK		 3083static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3084{
40ece7c7 3085 int rc;
234f3ce4 3086 unsigned long eip;
40ece7c7 3087
234f3ce4
NA		 3088 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3089 if (rc != X86EMUL_CONTINUE)
3090 return rc;
3091 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3092 if (rc != X86EMUL_CONTINUE)
3093 return rc;
5ad105e5 3094 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3095 return X86EMUL_CONTINUE;
3096}
3097
e4f973ae
TY		 3098static int em_xchg(struct x86_emulate_ctxt *ctxt)
3099{
e4f973ae 3100 /* Write back the register source. */
9dac77fa
AK		 3101 ctxt->src.val = ctxt->dst.val;
3102 write_register_operand(&ctxt->src);
e4f973ae
TY		 3103
3104 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3105 ctxt->dst.val = ctxt->src.orig_val;
3106 ctxt->lock_prefix = 1;
e4f973ae
TY		 3107 return X86EMUL_CONTINUE;
3108}
3109
5c82aa29
AK		 3110static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3111{
9dac77fa 3112 ctxt->dst.val = ctxt->src2.val;
4d758349 3113 return fastop(ctxt, em_imul);
5c82aa29
AK		 3114}
3115
61429142
AK		 3116static int em_cwd(struct x86_emulate_ctxt *ctxt)
3117{
9dac77fa
AK		 3118 ctxt->dst.type = OP_REG;
3119 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3120 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3121 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3122
3123 return X86EMUL_CONTINUE;
3124}
3125
48bb5d3c
AK		 3126static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3127{
48bb5d3c
AK		 3128 u64 tsc = 0;
3129
717746e3 3130 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3131 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3132 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3133 return X86EMUL_CONTINUE;
3134}
3135
222d21aa
AK		 3136static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3137{
3138 u64 pmc;
3139
dd856efa 3140 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3141 return emulate_gp(ctxt, 0);
dd856efa
AK		 3142 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3143 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3144 return X86EMUL_CONTINUE;
3145}
3146
b9eac5f4
AK		 3147static int em_mov(struct x86_emulate_ctxt *ctxt)
3148{
54cfdb3e 3149 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3150 return X86EMUL_CONTINUE;
3151}
3152
84cffe49
BP		 3153#define FFL(x) bit(X86_FEATURE_##x)
3154
3155static int em_movbe(struct x86_emulate_ctxt *ctxt)
3156{
3157 u32 ebx, ecx, edx, eax = 1;
3158 u16 tmp;
3159
3160 /*
3161 * Check MOVBE is set in the guest-visible CPUID leaf.
3162 */
3163 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3164 if (!(ecx & FFL(MOVBE)))
3165 return emulate_ud(ctxt);
3166
3167 switch (ctxt->op_bytes) {
3168 case 2:
3169 /*
3170 * From MOVBE definition: "...When the operand size is 16 bits,
3171 * the upper word of the destination register remains unchanged
3172 * ..."
3173 *
3174 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3175 * rules so we have to do the operation almost per hand.
3176 */
3177 tmp = (u16)ctxt->src.val;
3178 ctxt->dst.val &= ~0xffffUL;
3179 ctxt->dst.val |= (unsigned long)swab16(tmp);
3180 break;
3181 case 4:
3182 ctxt->dst.val = swab32((u32)ctxt->src.val);
3183 break;
3184 case 8:
3185 ctxt->dst.val = swab64(ctxt->src.val);
3186 break;
3187 default:
592f0858 3188 BUG();
84cffe49
BP		 3189 }
3190 return X86EMUL_CONTINUE;
3191}
3192
bc00f8d2
TY		 3193static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3194{
3195 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3196 return emulate_gp(ctxt, 0);
3197
3198 /* Disable writeback. */
3199 ctxt->dst.type = OP_NONE;
3200 return X86EMUL_CONTINUE;
3201}
3202
3203static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3204{
3205 unsigned long val;
3206
3207 if (ctxt->mode == X86EMUL_MODE_PROT64)
3208 val = ctxt->src.val & ~0ULL;
3209 else
3210 val = ctxt->src.val & ~0U;
3211
3212 /* #UD condition is already handled. */
3213 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3214 return emulate_gp(ctxt, 0);
3215
3216 /* Disable writeback. */
3217 ctxt->dst.type = OP_NONE;
3218 return X86EMUL_CONTINUE;
3219}
3220
e1e210b0
TY		 3221static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3222{
3223 u64 msr_data;
3224
dd856efa
AK		 3225 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3226 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3227 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3228 return emulate_gp(ctxt, 0);
3229
3230 return X86EMUL_CONTINUE;
3231}
3232
3233static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3234{
3235 u64 msr_data;
3236
dd856efa 3237 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3238 return emulate_gp(ctxt, 0);
3239
dd856efa
AK		 3240 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3241 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3242 return X86EMUL_CONTINUE;
3243}
3244
1bd5f469
TY		 3245static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3246{
9dac77fa 3247 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3248 return emulate_ud(ctxt);
3249
9dac77fa 3250 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3251 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3252 ctxt->dst.bytes = 2;
1bd5f469
TY		 3253 return X86EMUL_CONTINUE;
3254}
3255
3256static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3257{
9dac77fa 3258 u16 sel = ctxt->src.val;
1bd5f469 3259
9dac77fa 3260 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3261 return emulate_ud(ctxt);
3262
9dac77fa 3263 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3264 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3265
3266 /* Disable writeback. */
9dac77fa
AK		 3267 ctxt->dst.type = OP_NONE;
3268 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3269}
3270
a14e579f
AK		 3271static int em_lldt(struct x86_emulate_ctxt *ctxt)
3272{
3273 u16 sel = ctxt->src.val;
3274
3275 /* Disable writeback. */
3276 ctxt->dst.type = OP_NONE;
3277 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3278}
3279
80890006
AK		 3280static int em_ltr(struct x86_emulate_ctxt *ctxt)
3281{
3282 u16 sel = ctxt->src.val;
3283
3284 /* Disable writeback. */
3285 ctxt->dst.type = OP_NONE;
3286 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3287}
3288
38503911
AK		 3289static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3290{
9fa088f4
AK		 3291 int rc;
3292 ulong linear;
3293
9dac77fa 3294 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3295 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3296 ctxt->ops->invlpg(ctxt, linear);
38503911 3297 /* Disable writeback. */
9dac77fa 3298 ctxt->dst.type = OP_NONE;
38503911
AK		 3299 return X86EMUL_CONTINUE;
3300}
3301
2d04a05b
AK		 3302static int em_clts(struct x86_emulate_ctxt *ctxt)
3303{
3304 ulong cr0;
3305
3306 cr0 = ctxt->ops->get_cr(ctxt, 0);
3307 cr0 &= ~X86_CR0_TS;
3308 ctxt->ops->set_cr(ctxt, 0, cr0);
3309 return X86EMUL_CONTINUE;
3310}
3311
26d05cc7
AK		 3312static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3313{
0f54a321 3314 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3315
26d05cc7
AK		 3316 if (rc != X86EMUL_CONTINUE)
3317 return rc;
3318
3319 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3320 ctxt->_eip = ctxt->eip;
26d05cc7 3321 /* Disable writeback. */
9dac77fa 3322 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3323 return X86EMUL_CONTINUE;
3324}
3325
96051572
AK		 3326static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3327 void (*get)(struct x86_emulate_ctxt *ctxt,
3328 struct desc_ptr *ptr))
3329{
3330 struct desc_ptr desc_ptr;
3331
3332 if (ctxt->mode == X86EMUL_MODE_PROT64)
3333 ctxt->op_bytes = 8;
3334 get(ctxt, &desc_ptr);
3335 if (ctxt->op_bytes == 2) {
3336 ctxt->op_bytes = 4;
3337 desc_ptr.address &= 0x00ffffff;
3338 }
3339 /* Disable writeback. */
3340 ctxt->dst.type = OP_NONE;
3341 return segmented_write(ctxt, ctxt->dst.addr.mem,
3342 &desc_ptr, 2 + ctxt->op_bytes);
3343}
3344
3345static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3346{
3347 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3348}
3349
3350static int em_sidt(struct x86_emulate_ctxt *ctxt)
3351{
3352 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3353}
3354
5b7f6a1e 3355static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3356{
26d05cc7
AK		 3357 struct desc_ptr desc_ptr;
3358 int rc;
3359
510425ff
AK		 3360 if (ctxt->mode == X86EMUL_MODE_PROT64)
3361 ctxt->op_bytes = 8;
9dac77fa 3362 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3363 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3364 ctxt->op_bytes);
26d05cc7
AK		 3365 if (rc != X86EMUL_CONTINUE)
3366 return rc;
9a9abf6b
NA		 3367 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3368 is_noncanonical_address(desc_ptr.address))
3369 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3370 if (lgdt)
3371 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3372 else
3373 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3374 /* Disable writeback. */
9dac77fa 3375 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3376 return X86EMUL_CONTINUE;
3377}
3378
5b7f6a1e
NA		 3379static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3380{
3381 return em_lgdt_lidt(ctxt, true);
3382}
3383
5ef39c71 3384static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3385{
26d05cc7
AK		 3386 int rc;
3387
5ef39c71
AK		 3388 rc = ctxt->ops->fix_hypercall(ctxt);
3389
26d05cc7 3390 /* Disable writeback. */
9dac77fa 3391 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3392 return rc;
3393}
3394
3395static int em_lidt(struct x86_emulate_ctxt *ctxt)
3396{
5b7f6a1e 3397 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3398}
3399
3400static int em_smsw(struct x86_emulate_ctxt *ctxt)
3401{
32e94d06
NA		 3402 if (ctxt->dst.type == OP_MEM)
3403 ctxt->dst.bytes = 2;
9dac77fa 3404 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3405 return X86EMUL_CONTINUE;
3406}
3407
3408static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3409{
26d05cc7 3410 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3411 | (ctxt->src.val & 0x0f));
3412 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3413 return X86EMUL_CONTINUE;
3414}
3415
d06e03ad
TY		 3416static int em_loop(struct x86_emulate_ctxt *ctxt)
3417{
234f3ce4
NA		 3418 int rc = X86EMUL_CONTINUE;
3419
01485a22 3420 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3421 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3422 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3423 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3424
234f3ce4 3425 return rc;
d06e03ad
TY		 3426}
3427
3428static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3429{
234f3ce4
NA		 3430 int rc = X86EMUL_CONTINUE;
3431
dd856efa 3432 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3433 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3434
234f3ce4 3435 return rc;
d06e03ad
TY		 3436}
3437
d7841a4b
TY		 3438static int em_in(struct x86_emulate_ctxt *ctxt)
3439{
3440 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3441 &ctxt->dst.val))
3442 return X86EMUL_IO_NEEDED;
3443
3444 return X86EMUL_CONTINUE;
3445}
3446
3447static int em_out(struct x86_emulate_ctxt *ctxt)
3448{
3449 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3450 &ctxt->src.val, 1);
3451 /* Disable writeback. */
3452 ctxt->dst.type = OP_NONE;
3453 return X86EMUL_CONTINUE;
3454}
3455
f411e6cd
TY		 3456static int em_cli(struct x86_emulate_ctxt *ctxt)
3457{
3458 if (emulator_bad_iopl(ctxt))
3459 return emulate_gp(ctxt, 0);
3460
3461 ctxt->eflags &= ~X86_EFLAGS_IF;
3462 return X86EMUL_CONTINUE;
3463}
3464
3465static int em_sti(struct x86_emulate_ctxt *ctxt)
3466{
3467 if (emulator_bad_iopl(ctxt))
3468 return emulate_gp(ctxt, 0);
3469
3470 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3471 ctxt->eflags |= X86_EFLAGS_IF;
3472 return X86EMUL_CONTINUE;
3473}
3474
6d6eede4
AK		 3475static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3476{
3477 u32 eax, ebx, ecx, edx;
3478
dd856efa
AK		 3479 eax = reg_read(ctxt, VCPU_REGS_RAX);
3480 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3481 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3482 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3483 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3484 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3485 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3486 return X86EMUL_CONTINUE;
3487}
3488
98f73630
PB		 3489static int em_sahf(struct x86_emulate_ctxt *ctxt)
3490{
3491 u32 flags;
3492
3493 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3494 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3495
3496 ctxt->eflags &= ~0xffUL;
3497 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3498 return X86EMUL_CONTINUE;
3499}
3500
2dd7caa0
AK		 3501static int em_lahf(struct x86_emulate_ctxt *ctxt)
3502{
dd856efa
AK		 3503 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3504 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3505 return X86EMUL_CONTINUE;
3506}
3507
9299836e
AK		 3508static int em_bswap(struct x86_emulate_ctxt *ctxt)
3509{
3510 switch (ctxt->op_bytes) {
3511#ifdef CONFIG_X86_64
3512 case 8:
3513 asm("bswap %0" : "+r"(ctxt->dst.val));
3514 break;
3515#endif
3516 default:
3517 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3518 break;
3519 }
3520 return X86EMUL_CONTINUE;
3521}
3522
13e457e0
NA		 3523static int em_clflush(struct x86_emulate_ctxt *ctxt)
3524{
3525 /* emulating clflush regardless of cpuid */
3526 return X86EMUL_CONTINUE;
3527}
3528
cfec82cb
JR		 3529static bool valid_cr(int nr)
3530{
3531 switch (nr) {
3532 case 0:
3533 case 2 ... 4:
3534 case 8:
3535 return true;
3536 default:
3537 return false;
3538 }
3539}
3540
3541static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3542{
9dac77fa 3543 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3544 return emulate_ud(ctxt);
3545
3546 return X86EMUL_CONTINUE;
3547}
3548
3549static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3550{
9dac77fa
AK		 3551 u64 new_val = ctxt->src.val64;
3552 int cr = ctxt->modrm_reg;
c2ad2bb3 3553 u64 efer = 0;
cfec82cb
JR		 3554
3555 static u64 cr_reserved_bits[] = {
3556 0xffffffff00000000ULL,
3557 0, 0, 0, /* CR3 checked later */
3558 CR4_RESERVED_BITS,
3559 0, 0, 0,
3560 CR8_RESERVED_BITS,
3561 };
3562
3563 if (!valid_cr(cr))
3564 return emulate_ud(ctxt);
3565
3566 if (new_val & cr_reserved_bits[cr])
3567 return emulate_gp(ctxt, 0);
3568
3569 switch (cr) {
3570 case 0: {
c2ad2bb3 3571 u64 cr4;
cfec82cb
JR		 3572 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3573 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3574 return emulate_gp(ctxt, 0);
3575
717746e3
AK		 3576 cr4 = ctxt->ops->get_cr(ctxt, 4);
3577 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3578
3579 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3580 !(cr4 & X86_CR4_PAE))
3581 return emulate_gp(ctxt, 0);
3582
3583 break;
3584 }
3585 case 3: {
3586 u64 rsvd = 0;
3587
c2ad2bb3
AK		 3588 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3589 if (efer & EFER_LMA)
9d88fca7 3590 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3591
3592 if (new_val & rsvd)
3593 return emulate_gp(ctxt, 0);
3594
3595 break;
3596 }
3597 case 4: {
717746e3 3598 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3599
3600 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3601 return emulate_gp(ctxt, 0);
3602
3603 break;
3604 }
3605 }
3606
3607 return X86EMUL_CONTINUE;
3608}
3609
3b88e41a
JR		 3610static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3611{
3612 unsigned long dr7;
3613
717746e3 3614 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3615
3616 /* Check if DR7.Global_Enable is set */
3617 return dr7 & (1 << 13);
3618}
3619
3620static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3621{
9dac77fa 3622 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3623 u64 cr4;
3624
3625 if (dr > 7)
3626 return emulate_ud(ctxt);
3627
717746e3 3628 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3629 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3630 return emulate_ud(ctxt);
3631
6d2a0526
NA		 3632 if (check_dr7_gd(ctxt)) {
3633 ulong dr6;
3634
3635 ctxt->ops->get_dr(ctxt, 6, &dr6);
3636 dr6 &= ~15;
3637 dr6 |= DR6_BD | DR6_RTM;
3638 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3639 return emulate_db(ctxt);
6d2a0526 3640 }
3b88e41a
JR		 3641
3642 return X86EMUL_CONTINUE;
3643}
3644
3645static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3646{
9dac77fa
AK		 3647 u64 new_val = ctxt->src.val64;
3648 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3649
3650 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3651 return emulate_gp(ctxt, 0);
3652
3653 return check_dr_read(ctxt);
3654}
3655
01de8b09
JR		 3656static int check_svme(struct x86_emulate_ctxt *ctxt)
3657{
3658 u64 efer;
3659
717746e3 3660 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3661
3662 if (!(efer & EFER_SVME))
3663 return emulate_ud(ctxt);
3664
3665 return X86EMUL_CONTINUE;
3666}
3667
3668static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3669{
dd856efa 3670 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3671
3672 /* Valid physical address? */
d4224449 3673 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3674 return emulate_gp(ctxt, 0);
3675
3676 return check_svme(ctxt);
3677}
3678
d7eb8203
JR		 3679static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3680{
717746e3 3681 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3682
717746e3 3683 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3684 return emulate_ud(ctxt);
3685
3686 return X86EMUL_CONTINUE;
3687}
3688
8061252e
JR		 3689static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3690{
717746e3 3691 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3692 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3693
717746e3 3694 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3695 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3696 return emulate_gp(ctxt, 0);
3697
3698 return X86EMUL_CONTINUE;
3699}
3700
f6511935
JR		 3701static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3702{
9dac77fa
AK		 3703 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3704 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3705 return emulate_gp(ctxt, 0);
3706
3707 return X86EMUL_CONTINUE;
3708}
3709
3710static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3711{
9dac77fa
AK		 3712 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3713 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3714 return emulate_gp(ctxt, 0);
3715
3716 return X86EMUL_CONTINUE;
3717}
3718
73fba5f4 3719#define D(_y) { .flags = (_y) }
d40a6898
PB		 3720#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3721#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3722 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3723#define N D(NotImpl)
01de8b09 3724#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3725#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3726#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3727#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3728#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3729#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3730#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3731#define II(_f, _e, _i) \
d40a6898 3732 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3733#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3734 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3735 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3736#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3737
8d8f4e9f 3738#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3739#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3740#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3741#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3742#define I2bvIP(_f, _e, _i, _p) \
3743 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3744
fb864fbc
AK		 3745#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3746 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3747 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3748
0f54a321
NA		 3749static const struct opcode group7_rm0[] = {
3750 N,
3751 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3752 N, N, N, N, N, N,
3753};
3754
fd0a0d82 3755static const struct opcode group7_rm1[] = {
1c2545be
TY		 3756 DI(SrcNone | Priv, monitor),
3757 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3758 N, N, N, N, N, N,
3759};
3760
fd0a0d82 3761static const struct opcode group7_rm3[] = {
1c2545be 3762 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3763 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3764 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3765 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3766 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3767 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3768 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3769 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3770};
6230f7fc 3771
fd0a0d82 3772static const struct opcode group7_rm7[] = {
d7eb8203 3773 N,
1c2545be 3774 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3775 N, N, N, N, N, N,
3776};
d67fc27a 3777
fd0a0d82 3778static const struct opcode group1[] = {
fb864fbc
AK		 3779 F(Lock, em_add),
3780 F(Lock | PageTable, em_or),
3781 F(Lock, em_adc),
3782 F(Lock, em_sbb),
3783 F(Lock | PageTable, em_and),
3784 F(Lock, em_sub),
3785 F(Lock, em_xor),
3786 F(NoWrite, em_cmp),
73fba5f4
AK		 3787};
3788
fd0a0d82 3789static const struct opcode group1A[] = {
ab708099 3790 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3791};
3792
007a3b54
AK		 3793static const struct opcode group2[] = {
3794 F(DstMem | ModRM, em_rol),
3795 F(DstMem | ModRM, em_ror),
3796 F(DstMem | ModRM, em_rcl),
3797 F(DstMem | ModRM, em_rcr),
3798 F(DstMem | ModRM, em_shl),
3799 F(DstMem | ModRM, em_shr),
3800 F(DstMem | ModRM, em_shl),
3801 F(DstMem | ModRM, em_sar),
3802};
3803
fd0a0d82 3804static const struct opcode group3[] = {
fb864fbc
AK		 3805 F(DstMem | SrcImm | NoWrite, em_test),
3806 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3807 F(DstMem | SrcNone | Lock, em_not),
3808 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3809 F(DstXacc | Src2Mem, em_mul_ex),
3810 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3811 F(DstXacc | Src2Mem, em_div_ex),
3812 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3813};
3814
fd0a0d82 3815static const struct opcode group4[] = {
95413dc4
AK		 3816 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3817 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3818 N, N, N, N, N, N,
3819};
3820
fd0a0d82 3821static const struct opcode group5[] = {
95413dc4
AK		 3822 F(DstMem | SrcNone | Lock, em_inc),
3823 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3824 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3825 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3826 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3827 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3828 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3829};
3830
fd0a0d82 3831static const struct opcode group6[] = {
1c2545be
TY		 3832 DI(Prot, sldt),
3833 DI(Prot, str),
a14e579f 3834 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3835 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3836 N, N, N, N,
3837};
3838
fd0a0d82 3839static const struct group_dual group7 = { {
606b1c3e
NA		 3840 II(Mov | DstMem, em_sgdt, sgdt),
3841 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3842 II(SrcMem | Priv, em_lgdt, lgdt),
3843 II(SrcMem | Priv, em_lidt, lidt),
3844 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3845 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3846 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3847}, {
0f54a321 3848 EXT(0, group7_rm0),
5ef39c71 3849 EXT(0, group7_rm1),
01de8b09 3850 N, EXT(0, group7_rm3),
1c2545be
TY		 3851 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3852 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3853 EXT(0, group7_rm7),
73fba5f4
AK		 3854} };
3855
fd0a0d82 3856static const struct opcode group8[] = {
73fba5f4 3857 N, N, N, N,
11c363ba
AK		 3858 F(DstMem | SrcImmByte | NoWrite, em_bt),
3859 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3860 F(DstMem | SrcImmByte | Lock, em_btr),
3861 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3862};
3863
fd0a0d82 3864static const struct group_dual group9 = { {
1c2545be 3865 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3866}, {
3867 N, N, N, N, N, N, N, N,
3868} };
3869
fd0a0d82 3870static const struct opcode group11[] = {
1c2545be 3871 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3872 X7(D(Undefined)),
a4d4a7c1
AK		 3873};
3874
13e457e0 3875static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3876 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3877};
3878
3879static const struct group_dual group15 = { {
3880 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3881}, {
3882 N, N, N, N, N, N, N, N,
3883} };
3884
fd0a0d82 3885static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3886 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3887};
3888
39f062ff
NA		 3889static const struct instr_dual instr_dual_0f_2b = {
3890 I(0, em_mov), N
3891};
3892
d5b77069 3893static const struct gprefix pfx_0f_2b = {
39f062ff 3894 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3895};
3896
27ce8258 3897static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3898 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3899};
3900
0a37027e
AW		 3901static const struct gprefix pfx_0f_e7 = {
3902 N, I(Sse, em_mov), N, N,
3903};
3904
045a282c 3905static const struct escape escape_d9 = { {
16bebefe 3906 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3907}, {
3908 /* 0xC0 - 0xC7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xC8 - 0xCF */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xD0 - 0xC7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xD8 - 0xDF */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xE0 - 0xE7 */
3917 N, N, N, N, N, N, N, N,
3918 /* 0xE8 - 0xEF */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xF0 - 0xF7 */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xF8 - 0xFF */
3923 N, N, N, N, N, N, N, N,
3924} };
3925
3926static const struct escape escape_db = { {
3927 N, N, N, N, N, N, N, N,
3928}, {
3929 /* 0xC0 - 0xC7 */
3930 N, N, N, N, N, N, N, N,
3931 /* 0xC8 - 0xCF */
3932 N, N, N, N, N, N, N, N,
3933 /* 0xD0 - 0xC7 */
3934 N, N, N, N, N, N, N, N,
3935 /* 0xD8 - 0xDF */
3936 N, N, N, N, N, N, N, N,
3937 /* 0xE0 - 0xE7 */
3938 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3939 /* 0xE8 - 0xEF */
3940 N, N, N, N, N, N, N, N,
3941 /* 0xF0 - 0xF7 */
3942 N, N, N, N, N, N, N, N,
3943 /* 0xF8 - 0xFF */
3944 N, N, N, N, N, N, N, N,
3945} };
3946
3947static const struct escape escape_dd = { {
16bebefe 3948 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3949}, {
3950 /* 0xC0 - 0xC7 */
3951 N, N, N, N, N, N, N, N,
3952 /* 0xC8 - 0xCF */
3953 N, N, N, N, N, N, N, N,
3954 /* 0xD0 - 0xC7 */
3955 N, N, N, N, N, N, N, N,
3956 /* 0xD8 - 0xDF */
3957 N, N, N, N, N, N, N, N,
3958 /* 0xE0 - 0xE7 */
3959 N, N, N, N, N, N, N, N,
3960 /* 0xE8 - 0xEF */
3961 N, N, N, N, N, N, N, N,
3962 /* 0xF0 - 0xF7 */
3963 N, N, N, N, N, N, N, N,
3964 /* 0xF8 - 0xFF */
3965 N, N, N, N, N, N, N, N,
3966} };
3967
39f062ff
NA		 3968static const struct instr_dual instr_dual_0f_c3 = {
3969 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3970};
3971
fd0a0d82 3972static const struct opcode opcode_table[256] = {
73fba5f4 3973 /* 0x00 - 0x07 */
fb864fbc 3974 F6ALU(Lock, em_add),
1cd196ea
AK		 3975 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3976 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3977 /* 0x08 - 0x0F */
fb864fbc 3978 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3979 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3980 N,
73fba5f4 3981 /* 0x10 - 0x17 */
fb864fbc 3982 F6ALU(Lock, em_adc),
1cd196ea
AK		 3983 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3984 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3985 /* 0x18 - 0x1F */
fb864fbc 3986 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3987 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3988 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3989 /* 0x20 - 0x27 */
fb864fbc 3990 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3991 /* 0x28 - 0x2F */
fb864fbc 3992 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3993 /* 0x30 - 0x37 */
fb864fbc 3994 F6ALU(Lock, em_xor), N, N,
73fba5f4 3995 /* 0x38 - 0x3F */
fb864fbc 3996 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3997 /* 0x40 - 0x4F */
95413dc4 3998 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3999 /* 0x50 - 0x57 */
63540382 4000 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4001 /* 0x58 - 0x5F */
c54fe504 4002 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4003 /* 0x60 - 0x67 */
b96a7fad
TY		 4004 I(ImplicitOps | Stack | No64, em_pusha),
4005 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 4006 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
4007 N, N, N, N,
4008 /* 0x68 - 0x6F */
d46164db
AK		 4009 I(SrcImm | Mov | Stack, em_push),
4010 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4011 I(SrcImmByte | Mov | Stack, em_push),
4012 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4013 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4014 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4015 /* 0x70 - 0x7F */
58b7075d 4016 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4017 /* 0x80 - 0x87 */
1c2545be
TY		 4018 G(ByteOp | DstMem | SrcImm, group1),
4019 G(DstMem | SrcImm, group1),
4020 G(ByteOp | DstMem | SrcImm | No64, group1),
4021 G(DstMem | SrcImmByte, group1),
fb864fbc 4022 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4023 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4024 /* 0x88 - 0x8F */
d5ae7ce8 4025 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4026 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4027 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4028 D(ModRM | SrcMem | NoAccess | DstReg),
4029 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4030 G(0, group1A),
73fba5f4 4031 /* 0x90 - 0x97 */
bf608f88 4032 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4033 /* 0x98 - 0x9F */
61429142 4034 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4035 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4036 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4037 II(ImplicitOps | Stack, em_popf, popf),
4038 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4039 /* 0xA0 - 0xA7 */
b9eac5f4 4040 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4041 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4042 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4043 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4044 /* 0xA8 - 0xAF */
fb864fbc 4045 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4046 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4047 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4048 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4049 /* 0xB0 - 0xB7 */
b9eac5f4 4050 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4051 /* 0xB8 - 0xBF */
5e2c6883 4052 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4053 /* 0xC0 - 0xC7 */
007a3b54 4054 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4055 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4056 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4057 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4058 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4059 G(ByteOp, group11), G(0, group11),
73fba5f4 4060 /* 0xC8 - 0xCF */
612e89f0 4061 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4062 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4063 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4064 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4065 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4066 /* 0xD0 - 0xD7 */
007a3b54
AK		 4067 G(Src2One | ByteOp, group2), G(Src2One, group2),
4068 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4069 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4070 I(DstAcc | SrcImmUByte | No64, em_aad),
4071 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4072 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4073 /* 0xD8 - 0xDF */
045a282c 4074 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4075 /* 0xE0 - 0xE7 */
58b7075d
NA		 4076 X3(I(SrcImmByte | NearBranch, em_loop)),
4077 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4078 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4079 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4080 /* 0xE8 - 0xEF */
58b7075d
NA		 4081 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4082 I(SrcImmFAddr | No64, em_jmp_far),
4083 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4084 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4085 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4086 /* 0xF0 - 0xF7 */
bf608f88 4087 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4088 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4089 G(ByteOp, group3), G(0, group3),
73fba5f4 4090 /* 0xF8 - 0xFF */
f411e6cd
TY		 4091 D(ImplicitOps), D(ImplicitOps),
4092 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4093 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4094};
4095
fd0a0d82 4096static const struct opcode twobyte_table[256] = {
73fba5f4 4097 /* 0x00 - 0x0F */
dee6bb70 4098 G(0, group6), GD(0, &group7), N, N,
b51e974f 4099 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4100 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4101 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4102 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4103 /* 0x10 - 0x1F */
103f98ea 4104 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4105 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4106 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4107 /* 0x20 - 0x2F */
9b88ae99
NA		 4108 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4109 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4110 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4111 check_cr_write),
4112 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4113 check_dr_write),
73fba5f4 4114 N, N, N, N,
27ce8258
IM		 4115 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4116 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4117 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4118 N, N, N, N,
73fba5f4 4119 /* 0x30 - 0x3F */
e1e210b0 4120 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4121 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4122 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4123 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4124 I(ImplicitOps | EmulateOnUD, em_sysenter),
4125 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4126 N, N,
73fba5f4
AK		 4127 N, N, N, N, N, N, N, N,
4128 /* 0x40 - 0x4F */
140bad89 4129 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4130 /* 0x50 - 0x5F */
4131 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4132 /* 0x60 - 0x6F */
aa97bb48
AK		 4133 N, N, N, N,
4134 N, N, N, N,
4135 N, N, N, N,
4136 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4137 /* 0x70 - 0x7F */
aa97bb48
AK		 4138 N, N, N, N,
4139 N, N, N, N,
4140 N, N, N, N,
4141 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4142 /* 0x80 - 0x8F */
58b7075d 4143 X16(D(SrcImm | NearBranch)),
73fba5f4 4144 /* 0x90 - 0x9F */
ee45b58e 4145 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4146 /* 0xA0 - 0xA7 */
1cd196ea 4147 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4148 II(ImplicitOps, em_cpuid, cpuid),
4149 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4150 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4151 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4152 /* 0xA8 - 0xAF */
1cd196ea 4153 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4154 DI(ImplicitOps, rsm),
11c363ba 4155 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4156 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4157 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4158 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4159 /* 0xB0 - 0xB7 */
e940b5c2 4160 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4161 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4162 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4163 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4164 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4165 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4166 /* 0xB8 - 0xBF */
4167 N, N,
ce7faab2 4168 G(BitOp, group8),
11c363ba
AK		 4169 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4170 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4171 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4172 /* 0xC0 - 0xC7 */
e47a5f5f 4173 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4174 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4175 N, N, N, GD(0, &group9),
9299836e
AK		 4176 /* 0xC8 - 0xCF */
4177 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4178 /* 0xD0 - 0xDF */
4179 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4180 /* 0xE0 - 0xEF */
0a37027e
AW		 4181 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4182 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4183 /* 0xF0 - 0xFF */
4184 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4185};
4186
39f062ff
NA		 4187static const struct instr_dual instr_dual_0f_38_f0 = {
4188 I(DstReg | SrcMem | Mov, em_movbe), N
4189};
4190
4191static const struct instr_dual instr_dual_0f_38_f1 = {
4192 I(DstMem | SrcReg | Mov, em_movbe), N
4193};
4194
0bc5eedb 4195static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4196 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4197};
4198
4199static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4200 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4201};
4202
4203/*
4204 * Insns below are selected by the prefix which indexed by the third opcode
4205 * byte.
4206 */
4207static const struct opcode opcode_map_0f_38[256] = {
4208 /* 0x00 - 0x7f */
4209 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4210 /* 0x80 - 0xef */
4211 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4212 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4213 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4214 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4215 /* 0xf2 - 0xff */
4216 N, N, X4(N), X8(N)
0bc5eedb
BP		 4217};
4218
73fba5f4
AK		 4219#undef D
4220#undef N
4221#undef G
4222#undef GD
4223#undef I
aa97bb48 4224#undef GP
01de8b09 4225#undef EXT
73fba5f4 4226
8d8f4e9f 4227#undef D2bv
f6511935 4228#undef D2bvIP
8d8f4e9f 4229#undef I2bv
d7841a4b 4230#undef I2bvIP
d67fc27a 4231#undef I6ALU
8d8f4e9f 4232
9dac77fa 4233static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4234{
4235 unsigned size;
4236
9dac77fa 4237 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4238 if (size == 8)
4239 size = 4;
4240 return size;
4241}
4242
4243static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4244 unsigned size, bool sign_extension)
4245{
39f21ee5
AK		 4246 int rc = X86EMUL_CONTINUE;
4247
4248 op->type = OP_IMM;
4249 op->bytes = size;
9dac77fa 4250 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4251 /* NB. Immediates are sign-extended as necessary. */
4252 switch (op->bytes) {
4253 case 1:
e85a1085 4254 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4255 break;
4256 case 2:
e85a1085 4257 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4258 break;
4259 case 4:
e85a1085 4260 op->val = insn_fetch(s32, ctxt);
39f21ee5 4261 break;
5e2c6883
NA		 4262 case 8:
4263 op->val = insn_fetch(s64, ctxt);
4264 break;
39f21ee5
AK		 4265 }
4266 if (!sign_extension) {
4267 switch (op->bytes) {
4268 case 1:
4269 op->val &= 0xff;
4270 break;
4271 case 2:
4272 op->val &= 0xffff;
4273 break;
4274 case 4:
4275 op->val &= 0xffffffff;
4276 break;
4277 }
4278 }
4279done:
4280 return rc;
4281}
4282
a9945549
AK		 4283static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4284 unsigned d)
4285{
4286 int rc = X86EMUL_CONTINUE;
4287
4288 switch (d) {
4289 case OpReg:
2adb5ad9 4290 decode_register_operand(ctxt, op);
a9945549
AK		 4291 break;
4292 case OpImmUByte:
608aabe3 4293 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4294 break;
4295 case OpMem:
41ddf978 4296 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4297 mem_common:
4298 *op = ctxt->memop;
4299 ctxt->memopp = op;
96888977 4300 if (ctxt->d & BitOp)
a9945549
AK		 4301 fetch_bit_operand(ctxt);
4302 op->orig_val = op->val;
4303 break;
41ddf978 4304 case OpMem64:
aaa05f24 4305 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4306 goto mem_common;
a9945549
AK		 4307 case OpAcc:
4308 op->type = OP_REG;
4309 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4310 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4311 fetch_register_operand(op);
4312 op->orig_val = op->val;
4313 break;
820207c8
AK		 4314 case OpAccLo:
4315 op->type = OP_REG;
4316 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4317 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4318 fetch_register_operand(op);
4319 op->orig_val = op->val;
4320 break;
4321 case OpAccHi:
4322 if (ctxt->d & ByteOp) {
4323 op->type = OP_NONE;
4324 break;
4325 }
4326 op->type = OP_REG;
4327 op->bytes = ctxt->op_bytes;
4328 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4329 fetch_register_operand(op);
4330 op->orig_val = op->val;
4331 break;
a9945549
AK		 4332 case OpDI:
4333 op->type = OP_MEM;
4334 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4335 op->addr.mem.ea =
01485a22 4336 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4337 op->addr.mem.seg = VCPU_SREG_ES;
4338 op->val = 0;
b3356bf0 4339 op->count = 1;
a9945549
AK		 4340 break;
4341 case OpDX:
4342 op->type = OP_REG;
4343 op->bytes = 2;
dd856efa 4344 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4345 fetch_register_operand(op);
4346 break;
4dd6a57d 4347 case OpCL:
d29b9d7e 4348 op->type = OP_IMM;
4dd6a57d 4349 op->bytes = 1;
dd856efa 4350 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4351 break;
4352 case OpImmByte:
4353 rc = decode_imm(ctxt, op, 1, true);
4354 break;
4355 case OpOne:
d29b9d7e 4356 op->type = OP_IMM;
4dd6a57d
AK		 4357 op->bytes = 1;
4358 op->val = 1;
4359 break;
4360 case OpImm:
4361 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4362 break;
5e2c6883
NA		 4363 case OpImm64:
4364 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4365 break;
28867cee
AK		 4366 case OpMem8:
4367 ctxt->memop.bytes = 1;
660696d1 4368 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4369 ctxt->memop.addr.reg = decode_register(ctxt,
4370 ctxt->modrm_rm, true);
660696d1
GN		 4371 fetch_register_operand(&ctxt->memop);
4372 }
28867cee 4373 goto mem_common;
0fe59128
AK		 4374 case OpMem16:
4375 ctxt->memop.bytes = 2;
4376 goto mem_common;
4377 case OpMem32:
4378 ctxt->memop.bytes = 4;
4379 goto mem_common;
4380 case OpImmU16:
4381 rc = decode_imm(ctxt, op, 2, false);
4382 break;
4383 case OpImmU:
4384 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4385 break;
4386 case OpSI:
4387 op->type = OP_MEM;
4388 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4389 op->addr.mem.ea =
01485a22 4390 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4391 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4392 op->val = 0;
b3356bf0 4393 op->count = 1;
0fe59128 4394 break;
7fa57952
PB		 4395 case OpXLat:
4396 op->type = OP_MEM;
4397 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4398 op->addr.mem.ea =
01485a22 4399 address_mask(ctxt,
7fa57952
PB		 4400 reg_read(ctxt, VCPU_REGS_RBX) +
4401 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4402 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4403 op->val = 0;
4404 break;
0fe59128
AK		 4405 case OpImmFAddr:
4406 op->type = OP_IMM;
4407 op->addr.mem.ea = ctxt->_eip;
4408 op->bytes = ctxt->op_bytes + 2;
4409 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4410 break;
4411 case OpMemFAddr:
4412 ctxt->memop.bytes = ctxt->op_bytes + 2;
4413 goto mem_common;
c191a7a0 4414 case OpES:
d29b9d7e 4415 op->type = OP_IMM;
c191a7a0
AK		 4416 op->val = VCPU_SREG_ES;
4417 break;
4418 case OpCS:
d29b9d7e 4419 op->type = OP_IMM;
c191a7a0
AK		 4420 op->val = VCPU_SREG_CS;
4421 break;
4422 case OpSS:
d29b9d7e 4423 op->type = OP_IMM;
c191a7a0
AK		 4424 op->val = VCPU_SREG_SS;
4425 break;
4426 case OpDS:
d29b9d7e 4427 op->type = OP_IMM;
c191a7a0
AK		 4428 op->val = VCPU_SREG_DS;
4429 break;
4430 case OpFS:
d29b9d7e 4431 op->type = OP_IMM;
c191a7a0
AK		 4432 op->val = VCPU_SREG_FS;
4433 break;
4434 case OpGS:
d29b9d7e 4435 op->type = OP_IMM;
c191a7a0
AK		 4436 op->val = VCPU_SREG_GS;
4437 break;
a9945549
AK		 4438 case OpImplicit:
4439 /* Special instructions do their own operand decoding. */
4440 default:
4441 op->type = OP_NONE; /* Disable writeback. */
4442 break;
4443 }
4444
4445done:
4446 return rc;
4447}
4448
ef5d75cc 4449int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4450{
dde7e6d1
AK		 4451 int rc = X86EMUL_CONTINUE;
4452 int mode = ctxt->mode;
46561646 4453 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4454 bool op_prefix = false;
573e80fe 4455 bool has_seg_override = false;
46561646 4456 struct opcode opcode;
dde7e6d1 4457
f09ed83e
AK		 4458 ctxt->memop.type = OP_NONE;
4459 ctxt->memopp = NULL;
9dac77fa 4460 ctxt->_eip = ctxt->eip;
17052f16
PB		 4461 ctxt->fetch.ptr = ctxt->fetch.data;
4462 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4463 ctxt->opcode_len = 1;
dc25e89e 4464 if (insn_len > 0)
9dac77fa 4465 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4466 else {
9506d57d 4467 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4468 if (rc != X86EMUL_CONTINUE)
4469 return rc;
4470 }
dde7e6d1
AK		 4471
4472 switch (mode) {
4473 case X86EMUL_MODE_REAL:
4474 case X86EMUL_MODE_VM86:
4475 case X86EMUL_MODE_PROT16:
4476 def_op_bytes = def_ad_bytes = 2;
4477 break;
4478 case X86EMUL_MODE_PROT32:
4479 def_op_bytes = def_ad_bytes = 4;
4480 break;
4481#ifdef CONFIG_X86_64
4482 case X86EMUL_MODE_PROT64:
4483 def_op_bytes = 4;
4484 def_ad_bytes = 8;
4485 break;
4486#endif
4487 default:
1d2887e2 4488 return EMULATION_FAILED;
dde7e6d1
AK		 4489 }
4490
9dac77fa
AK		 4491 ctxt->op_bytes = def_op_bytes;
4492 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4493
4494 /* Legacy prefixes. */
4495 for (;;) {
e85a1085 4496 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4497 case 0x66: /* operand-size override */
0d7cdee8 4498 op_prefix = true;
dde7e6d1 4499 /* switch between 2/4 bytes */
9dac77fa 4500 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4501 break;
4502 case 0x67: /* address-size override */
4503 if (mode == X86EMUL_MODE_PROT64)
4504 /* switch between 4/8 bytes */
9dac77fa 4505 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4506 else
4507 /* switch between 2/4 bytes */
9dac77fa 4508 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4509 break;
4510 case 0x26: /* ES override */
4511 case 0x2e: /* CS override */
4512 case 0x36: /* SS override */
4513 case 0x3e: /* DS override */
573e80fe
BD		 4514 has_seg_override = true;
4515 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4516 break;
4517 case 0x64: /* FS override */
4518 case 0x65: /* GS override */
573e80fe
BD		 4519 has_seg_override = true;
4520 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4521 break;
4522 case 0x40 ... 0x4f: /* REX */
4523 if (mode != X86EMUL_MODE_PROT64)
4524 goto done_prefixes;
9dac77fa 4525 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4526 continue;
4527 case 0xf0: /* LOCK */
9dac77fa 4528 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4529 break;
4530 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4531 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4532 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4533 break;
4534 default:
4535 goto done_prefixes;
4536 }
4537
4538 /* Any legacy prefix after a REX prefix nullifies its effect. */
4539
9dac77fa 4540 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4541 }
4542
4543done_prefixes:
4544
4545 /* REX prefix. */
9dac77fa
AK		 4546 if (ctxt->rex_prefix & 8)
4547 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4548
4549 /* Opcode byte(s). */
9dac77fa 4550 opcode = opcode_table[ctxt->b];
d3ad6243 4551 /* Two-byte opcode? */
9dac77fa 4552 if (ctxt->b == 0x0f) {
1ce19dc1 4553 ctxt->opcode_len = 2;
e85a1085 4554 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4555 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4556
4557 /* 0F_38 opcode map */
4558 if (ctxt->b == 0x38) {
4559 ctxt->opcode_len = 3;
4560 ctxt->b = insn_fetch(u8, ctxt);
4561 opcode = opcode_map_0f_38[ctxt->b];
4562 }
dde7e6d1 4563 }
9dac77fa 4564 ctxt->d = opcode.flags;
dde7e6d1 4565
9f4260e7
TY		 4566 if (ctxt->d & ModRM)
4567 ctxt->modrm = insn_fetch(u8, ctxt);
4568
7fe864dc
NA		 4569 /* vex-prefix instructions are not implemented */
4570 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4571 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4572 ctxt->d = NotImpl;
4573 }
4574
9dac77fa
AK		 4575 while (ctxt->d & GroupMask) {
4576 switch (ctxt->d & GroupMask) {
46561646 4577 case Group:
9dac77fa 4578 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4579 opcode = opcode.u.group[goffset];
4580 break;
4581 case GroupDual:
9dac77fa
AK		 4582 goffset = (ctxt->modrm >> 3) & 7;
4583 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4584 opcode = opcode.u.gdual->mod3[goffset];
4585 else
4586 opcode = opcode.u.gdual->mod012[goffset];
4587 break;
4588 case RMExt:
9dac77fa 4589 goffset = ctxt->modrm & 7;
01de8b09 4590 opcode = opcode.u.group[goffset];
46561646
AK		 4591 break;
4592 case Prefix:
9dac77fa 4593 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4594 return EMULATION_FAILED;
9dac77fa 4595 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4596 switch (simd_prefix) {
4597 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4598 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4599 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4600 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4601 }
4602 break;
045a282c
GN		 4603 case Escape:
4604 if (ctxt->modrm > 0xbf)
4605 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4606 else
4607 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4608 break;
39f062ff
NA		 4609 case InstrDual:
4610 if ((ctxt->modrm >> 6) == 3)
4611 opcode = opcode.u.idual->mod3;
4612 else
4613 opcode = opcode.u.idual->mod012;
4614 break;
46561646 4615 default:
1d2887e2 4616 return EMULATION_FAILED;
0d7cdee8 4617 }
46561646 4618
b1ea50b2 4619 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4620 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4621 }
4622
e24186e0
PB		 4623 /* Unrecognised? */
4624 if (ctxt->d == 0)
4625 return EMULATION_FAILED;
4626
9dac77fa 4627 ctxt->execute = opcode.u.execute;
dde7e6d1 4628
3a6095a0
NA		 4629 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4630 return EMULATION_FAILED;
4631
d40a6898 4632 if (unlikely(ctxt->d &
ed9aad21
NA		 4633 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4634 No16))) {
d40a6898
PB		 4635 /*
4636 * These are copied unconditionally here, and checked unconditionally
4637 * in x86_emulate_insn.
4638 */
4639 ctxt->check_perm = opcode.check_perm;
4640 ctxt->intercept = opcode.intercept;
dde7e6d1 4641
d40a6898
PB		 4642 if (ctxt->d & NotImpl)
4643 return EMULATION_FAILED;
d867162c 4644
58b7075d
NA		 4645 if (mode == X86EMUL_MODE_PROT64) {
4646 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4647 ctxt->op_bytes = 8;
4648 else if (ctxt->d & NearBranch)
4649 ctxt->op_bytes = 8;
4650 }
7f9b4b75 4651
d40a6898
PB		 4652 if (ctxt->d & Op3264) {
4653 if (mode == X86EMUL_MODE_PROT64)
4654 ctxt->op_bytes = 8;
4655 else
4656 ctxt->op_bytes = 4;
4657 }
4658
ed9aad21
NA		 4659 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4660 ctxt->op_bytes = 4;
4661
d40a6898
PB		 4662 if (ctxt->d & Sse)
4663 ctxt->op_bytes = 16;
4664 else if (ctxt->d & Mmx)
4665 ctxt->op_bytes = 8;
4666 }
1253791d 4667
dde7e6d1 4668 /* ModRM and SIB bytes. */
9dac77fa 4669 if (ctxt->d & ModRM) {
f09ed83e 4670 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4671 if (!has_seg_override) {
4672 has_seg_override = true;
4673 ctxt->seg_override = ctxt->modrm_seg;
4674 }
9dac77fa 4675 } else if (ctxt->d & MemAbs)
f09ed83e 4676 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4677 if (rc != X86EMUL_CONTINUE)
4678 goto done;
4679
573e80fe
BD		 4680 if (!has_seg_override)
4681 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4682
573e80fe 4683 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4684
dde7e6d1
AK		 4685 /*
4686 * Decode and fetch the source operand: register, memory
4687 * or immediate.
4688 */
0fe59128 4689 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4690 if (rc != X86EMUL_CONTINUE)
4691 goto done;
4692
dde7e6d1
AK		 4693 /*
4694 * Decode and fetch the second source operand: register, memory
4695 * or immediate.
4696 */
4dd6a57d 4697 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4698 if (rc != X86EMUL_CONTINUE)
4699 goto done;
4700
dde7e6d1 4701 /* Decode and fetch the destination operand: register or memory. */
a9945549 4702 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4703
41061cdb 4704 if (ctxt->rip_relative)
1c1c35ae
NA		 4705 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4706 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4707
a430c916 4708done:
1d2887e2 4709 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4710}
4711
1cb3f3ae
XG		 4712bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4713{
4714 return ctxt->d & PageTable;
4715}
4716
3e2f65d5
GN		 4717static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4718{
3e2f65d5
GN		 4719 /* The second termination condition only applies for REPE
4720 * and REPNE. Test if the repeat string operation prefix is
4721 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4722 * corresponding termination condition according to:
4723 * - if REPE/REPZ and ZF = 0 then done
4724 * - if REPNE/REPNZ and ZF = 1 then done
4725 */
9dac77fa
AK		 4726 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4727 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4728 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4729 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4730 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4731 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4732 return true;
4733
4734 return false;
4735}
4736
cbe2c9d3
AK		 4737static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4738{
4739 bool fault = false;
4740
4741 ctxt->ops->get_fpu(ctxt);
4742 asm volatile("1: fwait \n\t"
4743 "2: \n\t"
4744 ".pushsection .fixup,\"ax\" \n\t"
4745 "3: \n\t"
4746 "movb $1, %[fault] \n\t"
4747 "jmp 2b \n\t"
4748 ".popsection \n\t"
4749 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4750 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4751 ctxt->ops->put_fpu(ctxt);
4752
4753 if (unlikely(fault))
4754 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4755
4756 return X86EMUL_CONTINUE;
4757}
4758
4759static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4760 struct operand *op)
4761{
4762 if (op->type == OP_MM)
4763 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4764}
4765
e28bbd44
AK		 4766static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4767{
4768 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4769 if (!(ctxt->d & ByteOp))
4770 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4771 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4772 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4773 [fastop]"+S"(fop)
4774 : "c"(ctxt->src2.val));
e28bbd44 4775 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4776 if (!fop) /* exception is returned in fop variable */
4777 return emulate_de(ctxt);
e28bbd44
AK		 4778 return X86EMUL_CONTINUE;
4779}
dd856efa 4780
1498507a
BD		 4781void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4782{
573e80fe
BD		 4783 memset(&ctxt->rip_relative, 0,
4784 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4785
1498507a
BD		 4786 ctxt->io_read.pos = 0;
4787 ctxt->io_read.end = 0;
1498507a
BD		 4788 ctxt->mem_read.end = 0;
4789}
4790
7b105ca2 4791int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4792{
0225fb50 4793 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4794 int rc = X86EMUL_CONTINUE;
9dac77fa 4795 int saved_dst_type = ctxt->dst.type;
8b4caf66 4796
9dac77fa 4797 ctxt->mem_read.pos = 0;
310b5d30 4798
e24186e0
PB		 4799 /* LOCK prefix is allowed only with some instructions */
4800 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4801 rc = emulate_ud(ctxt);
1161624f
GN		 4802 goto done;
4803 }
4804
e24186e0 4805 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4806 rc = emulate_ud(ctxt);
d380a5e4
GN		 4807 goto done;
4808 }
4809
d40a6898
PB		 4810 if (unlikely(ctxt->d &
4811 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4812 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4813 (ctxt->d & Undefined)) {
4814 rc = emulate_ud(ctxt);
4815 goto done;
4816 }
1253791d 4817
d40a6898
PB		 4818 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4819 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4820 rc = emulate_ud(ctxt);
cbe2c9d3 4821 goto done;
d40a6898 4822 }
cbe2c9d3 4823
d40a6898
PB		 4824 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4825 rc = emulate_nm(ctxt);
c4f035c6 4826 goto done;
d40a6898 4827 }
c4f035c6 4828
d40a6898
PB		 4829 if (ctxt->d & Mmx) {
4830 rc = flush_pending_x87_faults(ctxt);
4831 if (rc != X86EMUL_CONTINUE)
4832 goto done;
4833 /*
4834 * Now that we know the fpu is exception safe, we can fetch
4835 * operands from it.
4836 */
4837 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4838 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4839 if (!(ctxt->d & Mov))
4840 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4841 }
e92805ac 4842
685bbf4a 4843 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4844 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4845 X86_ICPT_PRE_EXCEPT);
4846 if (rc != X86EMUL_CONTINUE)
4847 goto done;
4848 }
8ea7d6ae 4849
64a38292
NA		 4850 /* Instruction can only be executed in protected mode */
4851 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4852 rc = emulate_ud(ctxt);
4853 goto done;
4854 }
4855
d40a6898
PB		 4856 /* Privileged instruction can be executed only in CPL=0 */
4857 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4858 if (ctxt->d & PrivUD)
4859 rc = emulate_ud(ctxt);
4860 else
4861 rc = emulate_gp(ctxt, 0);
d09beabd 4862 goto done;
d40a6898 4863 }
d09beabd 4864
d40a6898 4865 /* Do instruction specific permission checks */
685bbf4a 4866 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4867 rc = ctxt->check_perm(ctxt);
4868 if (rc != X86EMUL_CONTINUE)
4869 goto done;
4870 }
4871
685bbf4a 4872 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4873 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4874 X86_ICPT_POST_EXCEPT);
4875 if (rc != X86EMUL_CONTINUE)
4876 goto done;
4877 }
4878
4879 if (ctxt->rep_prefix && (ctxt->d & String)) {
4880 /* All REP prefixes have the same first termination condition */
4881 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4882 ctxt->eip = ctxt->_eip;
4467c3f1 4883 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4884 goto done;
4885 }
b9fa9d6b 4886 }
b9fa9d6b
AK		 4887 }
4888
9dac77fa
AK		 4889 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4890 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4891 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4892 if (rc != X86EMUL_CONTINUE)
8b4caf66 4893 goto done;
9dac77fa 4894 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4895 }
4896
9dac77fa
AK		 4897 if (ctxt->src2.type == OP_MEM) {
4898 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4899 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4900 if (rc != X86EMUL_CONTINUE)
4901 goto done;
4902 }
4903
9dac77fa 4904 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4905 goto special_insn;
4906
4907
9dac77fa 4908 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4909 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4910 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4911 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d
NA		 4912 if (rc != X86EMUL_CONTINUE) {
4913 if (rc == X86EMUL_PROPAGATE_FAULT &&
4914 ctxt->exception.vector == PF_VECTOR)
4915 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 4916 goto done;
c205fb7d 4917 }
038e51de 4918 }
9dac77fa 4919 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4920
018a98db
AK		 4921special_insn:
4922
685bbf4a 4923 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4924 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4925 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4926 if (rc != X86EMUL_CONTINUE)
4927 goto done;
4928 }
4929
b9a1ecb9
NA		 4930 if (ctxt->rep_prefix && (ctxt->d & String))
4931 ctxt->eflags |= EFLG_RF;
4932 else
4933 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4934
9dac77fa 4935 if (ctxt->execute) {
e28bbd44
AK		 4936 if (ctxt->d & Fastop) {
4937 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4938 rc = fastop(ctxt, fop);
4939 if (rc != X86EMUL_CONTINUE)
4940 goto done;
4941 goto writeback;
4942 }
9dac77fa 4943 rc = ctxt->execute(ctxt);
ef65c889
AK		 4944 if (rc != X86EMUL_CONTINUE)
4945 goto done;
4946 goto writeback;
4947 }
4948
1ce19dc1 4949 if (ctxt->opcode_len == 2)
6aa8b732 4950 goto twobyte_insn;
0bc5eedb
BP		 4951 else if (ctxt->opcode_len == 3)
4952 goto threebyte_insn;
6aa8b732 4953
9dac77fa 4954 switch (ctxt->b) {
6aa8b732 4955 case 0x63: /* movsxd */
8b4caf66 4956 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4957 goto cannot_emulate;
9dac77fa 4958 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4959 break;
b2833e3c 4960 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4961 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4962 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4963 break;
7e0b54b1 4964 case 0x8d: /* lea r16/r32, m */
9dac77fa 4965 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4966 break;
3d9e77df 4967 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4968 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4969 ctxt->dst.type = OP_NONE;
4970 else
4971 rc = em_xchg(ctxt);
e4f973ae 4972 break;
e8b6fa70 4973 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4974 switch (ctxt->op_bytes) {
4975 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4976 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4977 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4978 }
4979 break;
6e154e56 4980 case 0xcc: /* int3 */
5c5df76b
TY		 4981 rc = emulate_int(ctxt, 3);
4982 break;
6e154e56 4983 case 0xcd: /* int n */
9dac77fa 4984 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4985 break;
4986 case 0xce: /* into */
5c5df76b
TY		 4987 if (ctxt->eflags & EFLG_OF)
4988 rc = emulate_int(ctxt, 4);
6e154e56 4989 break;
1a52e051 4990 case 0xe9: /* jmp rel */
db5b0762 4991 case 0xeb: /* jmp rel short */
234f3ce4 4992 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4993 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4994 break;
111de5d6 4995 case 0xf4: /* hlt */
6c3287f7 4996 ctxt->ops->halt(ctxt);
19fdfa0d 4997 break;
111de5d6
AK		 4998 case 0xf5: /* cmc */
4999 /* complement carry flag from eflags reg */
5000 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 5001 break;
5002 case 0xf8: /* clc */
5003 ctxt->eflags &= ~EFLG_CF;
111de5d6 5004 break;
8744aa9a
MG		 5005 case 0xf9: /* stc */
5006 ctxt->eflags |= EFLG_CF;
5007 break;
fb4616f4
MG		 5008 case 0xfc: /* cld */
5009 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 5010 break;
5011 case 0xfd: /* std */
5012 ctxt->eflags |= EFLG_DF;
fb4616f4 5013 break;
91269b8f
AK		 5014 default:
5015 goto cannot_emulate;
6aa8b732 5016 }
018a98db 5017
7d9ddaed
AK		 5018 if (rc != X86EMUL_CONTINUE)
5019 goto done;
5020
018a98db 5021writeback:
fb32b1ed
AK		 5022 if (ctxt->d & SrcWrite) {
5023 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5024 rc = writeback(ctxt, &ctxt->src);
5025 if (rc != X86EMUL_CONTINUE)
5026 goto done;
5027 }
ee212297
NA		 5028 if (!(ctxt->d & NoWrite)) {
5029 rc = writeback(ctxt, &ctxt->dst);
5030 if (rc != X86EMUL_CONTINUE)
5031 goto done;
5032 }
018a98db 5033
5cd21917
GN		 5034 /*
5035 * restore dst type in case the decoding will be reused
5036 * (happens for string instruction )
5037 */
9dac77fa 5038 ctxt->dst.type = saved_dst_type;
5cd21917 5039
9dac77fa 5040 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5041 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5042
9dac77fa 5043 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5044 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5045
9dac77fa 5046 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5047 unsigned int count;
9dac77fa 5048 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5049 if ((ctxt->d & SrcMask) == SrcSI)
5050 count = ctxt->src.count;
5051 else
5052 count = ctxt->dst.count;
01485a22 5053 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5054
d2ddd1c4
GN		 5055 if (!string_insn_completed(ctxt)) {
5056 /*
5057 * Re-enter guest when pio read ahead buffer is empty
5058 * or, if it is not used, after each 1024 iteration.
5059 */
dd856efa 5060 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5061 (r->end == 0 || r->end != r->pos)) {
5062 /*
5063 * Reset read cache. Usually happens before
5064 * decode, but since instruction is restarted
5065 * we have to do it here.
5066 */
9dac77fa 5067 ctxt->mem_read.end = 0;
dd856efa 5068 writeback_registers(ctxt);
d2ddd1c4
GN		 5069 return EMULATION_RESTART;
5070 }
5071 goto done; /* skip rip writeback */
0fa6ccbd 5072 }
b9a1ecb9 5073 ctxt->eflags &= ~EFLG_RF;
5cd21917 5074 }
d2ddd1c4 5075
9dac77fa 5076 ctxt->eip = ctxt->_eip;
018a98db
AK		 5077
5078done:
e0ad0b47
PB		 5079 if (rc == X86EMUL_PROPAGATE_FAULT) {
5080 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5081 ctxt->have_exception = true;
e0ad0b47 5082 }
775fde86
JR		 5083 if (rc == X86EMUL_INTERCEPTED)
5084 return EMULATION_INTERCEPTED;
5085
dd856efa
AK		 5086 if (rc == X86EMUL_CONTINUE)
5087 writeback_registers(ctxt);
5088
d2ddd1c4 5089 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5090
5091twobyte_insn:
9dac77fa 5092 switch (ctxt->b) {
018a98db 5093 case 0x09: /* wbinvd */
cfb22375 5094 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5095 break;
5096 case 0x08: /* invd */
018a98db
AK		 5097 case 0x0d: /* GrpP (prefetch) */
5098 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5099 case 0x1f: /* nop */
018a98db
AK		 5100 break;
5101 case 0x20: /* mov cr, reg */
9dac77fa 5102 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5103 break;
6aa8b732 5104 case 0x21: /* mov from dr to reg */
9dac77fa 5105 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5106 break;
6aa8b732 5107 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5108 if (test_cc(ctxt->b, ctxt->eflags))
5109 ctxt->dst.val = ctxt->src.val;
5110 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5111 ctxt->op_bytes != 4)
9dac77fa 5112 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5113 break;
b2833e3c 5114 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5115 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5116 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5117 break;
ee45b58e 5118 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5119 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5120 break;
6aa8b732 5121 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5122 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5123 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5124 : (u16) ctxt->src.val;
6aa8b732 5125 break;
6aa8b732 5126 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5127 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5128 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5129 (s16) ctxt->src.val;
6aa8b732 5130 break;
91269b8f
AK		 5131 default:
5132 goto cannot_emulate;
6aa8b732 5133 }
7d9ddaed 5134
0bc5eedb
BP		 5135threebyte_insn:
5136
7d9ddaed
AK		 5137 if (rc != X86EMUL_CONTINUE)
5138 goto done;
5139
6aa8b732
AK		 5140 goto writeback;
5141
5142cannot_emulate:
a0c0ab2f 5143 return EMULATION_FAILED;
6aa8b732 5144}
dd856efa
AK		 5145
5146void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5147{
5148 invalidate_registers(ctxt);
5149}
5150
5151void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5152{
5153 writeback_registers(ctxt);
5154}
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