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KVM: x86: improve reexecute_instruction
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
0fe59128
AK		 63
64#define OpBits 5 /* Width of operand field */
b1ea50b2 65#define OpMask ((1ull << OpBits) - 1)
a9945549 66
6aa8b732
AK		 67/*
68 * Opcode effective-address decode tables.
69 * Note that we only emulate instructions that have at least one memory
70 * operand (excluding implicit stack references). We assume that stack
71 * references and instruction fetches will never occur in special memory
72 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
73 * not be handled.
74 */
75
76/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 77#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 78/* Destination operand type. */
a9945549
AK		 79#define DstShift 1
80#define ImplicitOps (OpImplicit << DstShift)
81#define DstReg (OpReg << DstShift)
82#define DstMem (OpMem << DstShift)
83#define DstAcc (OpAcc << DstShift)
84#define DstDI (OpDI << DstShift)
85#define DstMem64 (OpMem64 << DstShift)
86#define DstImmUByte (OpImmUByte << DstShift)
87#define DstDX (OpDX << DstShift)
88#define DstMask (OpMask << DstShift)
6aa8b732 89/* Source operand type. */
0fe59128
AK		 90#define SrcShift 6
91#define SrcNone (OpNone << SrcShift)
92#define SrcReg (OpReg << SrcShift)
93#define SrcMem (OpMem << SrcShift)
94#define SrcMem16 (OpMem16 << SrcShift)
95#define SrcMem32 (OpMem32 << SrcShift)
96#define SrcImm (OpImm << SrcShift)
97#define SrcImmByte (OpImmByte << SrcShift)
98#define SrcOne (OpOne << SrcShift)
99#define SrcImmUByte (OpImmUByte << SrcShift)
100#define SrcImmU (OpImmU << SrcShift)
101#define SrcSI (OpSI << SrcShift)
102#define SrcImmFAddr (OpImmFAddr << SrcShift)
103#define SrcMemFAddr (OpMemFAddr << SrcShift)
104#define SrcAcc (OpAcc << SrcShift)
105#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 106#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 107#define SrcDX (OpDX << SrcShift)
28867cee 108#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 109#define SrcMask (OpMask << SrcShift)
221192bd
MT		 110#define BitOp (1<<11)
111#define MemAbs (1<<12) /* Memory operand is absolute displacement */
112#define String (1<<13) /* String instruction (rep capable) */
113#define Stack (1<<14) /* Stack instruction (push/pop) */
114#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
115#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
116#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
117#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
118#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 119#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 120#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 121/* Generic ModRM decode. */
122#define ModRM (1<<19)
123/* Destination is only written; never read. */
124#define Mov (1<<20)
d8769fed 125/* Misc flags */
8ea7d6ae 126#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 127#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 128#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 129#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 130#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 131#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 132#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 133#define No64 (1<<28)
d5ae7ce8 134#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 135/* Source 2 operand type */
d5ae7ce8 136#define Src2Shift (30)
4dd6a57d
AK		 137#define Src2None (OpNone << Src2Shift)
138#define Src2CL (OpCL << Src2Shift)
139#define Src2ImmByte (OpImmByte << Src2Shift)
140#define Src2One (OpOne << Src2Shift)
141#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 142#define Src2ES (OpES << Src2Shift)
143#define Src2CS (OpCS << Src2Shift)
144#define Src2SS (OpSS << Src2Shift)
145#define Src2DS (OpDS << Src2Shift)
146#define Src2FS (OpFS << Src2Shift)
147#define Src2GS (OpGS << Src2Shift)
4dd6a57d 148#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 149#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 150#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
151#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
152#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 153#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 154#define NoWrite ((u64)1 << 45) /* No writeback */
6aa8b732 155
d0e53325
AK		 156#define X2(x...) x, x
157#define X3(x...) X2(x), x
158#define X4(x...) X2(x), X2(x)
159#define X5(x...) X4(x), x
160#define X6(x...) X4(x), X2(x)
161#define X7(x...) X4(x), X3(x)
162#define X8(x...) X4(x), X4(x)
163#define X16(x...) X8(x), X8(x)
83babbca 164
e28bbd44
AK		 165#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
166#define FASTOP_SIZE 8
167
168/*
169 * fastop functions have a special calling convention:
170 *
171 * dst: [rdx]:rax (in/out)
172 * src: rbx (in/out)
173 * src2: rcx (in)
174 * flags: rflags (in/out)
175 *
176 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
177 * different operand sizes can be reached by calculation, rather than a jump
178 * table (which would be bigger than the code).
179 *
180 * fastop functions are declared as taking a never-defined fastop parameter,
181 * so they can't be called from C directly.
182 */
183
184struct fastop;
185
d65b1dee 186struct opcode {
b1ea50b2
AK		 187 u64 flags : 56;
188 u64 intercept : 8;
120df890 189 union {
ef65c889 190 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 191 const struct opcode *group;
192 const struct group_dual *gdual;
193 const struct gprefix *gprefix;
045a282c 194 const struct escape *esc;
e28bbd44 195 void (*fastop)(struct fastop *fake);
120df890 196 } u;
d09beabd 197 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 198};
199
200struct group_dual {
201 struct opcode mod012[8];
202 struct opcode mod3[8];
d65b1dee
AK		 203};
204
0d7cdee8
AK		 205struct gprefix {
206 struct opcode pfx_no;
207 struct opcode pfx_66;
208 struct opcode pfx_f2;
209 struct opcode pfx_f3;
210};
211
045a282c
GN		 212struct escape {
213 struct opcode op[8];
214 struct opcode high[64];
215};
216
6aa8b732 217/* EFLAGS bit definitions. */
d4c6a154
GN		 218#define EFLG_ID (1<<21)
219#define EFLG_VIP (1<<20)
220#define EFLG_VIF (1<<19)
221#define EFLG_AC (1<<18)
b1d86143
AP		 222#define EFLG_VM (1<<17)
223#define EFLG_RF (1<<16)
d4c6a154
GN		 224#define EFLG_IOPL (3<<12)
225#define EFLG_NT (1<<14)
6aa8b732
AK		 226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
b1d86143 228#define EFLG_IF (1<<9)
d4c6a154 229#define EFLG_TF (1<<8)
6aa8b732
AK		 230#define EFLG_SF (1<<7)
231#define EFLG_ZF (1<<6)
232#define EFLG_AF (1<<4)
233#define EFLG_PF (1<<2)
234#define EFLG_CF (1<<0)
235
62bd430e
MG		 236#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
237#define EFLG_RESERVED_ONE_MASK 2
238
dd856efa
AK		 239static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
240{
241 if (!(ctxt->regs_valid & (1 << nr))) {
242 ctxt->regs_valid |= 1 << nr;
243 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
244 }
245 return ctxt->_regs[nr];
246}
247
248static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
249{
250 ctxt->regs_valid |= 1 << nr;
251 ctxt->regs_dirty |= 1 << nr;
252 return &ctxt->_regs[nr];
253}
254
255static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 reg_read(ctxt, nr);
258 return reg_write(ctxt, nr);
259}
260
261static void writeback_registers(struct x86_emulate_ctxt *ctxt)
262{
263 unsigned reg;
264
265 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
266 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
267}
268
269static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
270{
271 ctxt->regs_dirty = 0;
272 ctxt->regs_valid = 0;
273}
274
6aa8b732
AK		 275/*
276 * Instruction emulation:
277 * Most instructions are emulated directly via a fragment of inline assembly
278 * code. This allows us to save/restore EFLAGS and thus very easily pick up
279 * any modified flags.
280 */
281
05b3e0c2 282#if defined(CONFIG_X86_64)
6aa8b732
AK		 283#define _LO32 "k" /* force 32-bit operand */
284#define _STK "%%rsp" /* stack pointer */
285#elif defined(__i386__)
286#define _LO32 "" /* force 32-bit operand */
287#define _STK "%%esp" /* stack pointer */
288#endif
289
290/*
291 * These EFLAGS bits are restored from saved value during emulation, and
292 * any changes are written back to the saved value after emulation.
293 */
294#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
295
296/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 297#define _PRE_EFLAGS(_sav, _msk, _tmp) \
298 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
299 "movl %"_sav",%"_LO32 _tmp"; " \
300 "push %"_tmp"; " \
301 "push %"_tmp"; " \
302 "movl %"_msk",%"_LO32 _tmp"; " \
303 "andl %"_LO32 _tmp",("_STK"); " \
304 "pushf; " \
305 "notl %"_LO32 _tmp"; " \
306 "andl %"_LO32 _tmp",("_STK"); " \
307 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
308 "pop %"_tmp"; " \
309 "orl %"_LO32 _tmp",("_STK"); " \
310 "popf; " \
311 "pop %"_sav"; "
6aa8b732
AK		 312
313/* After executing instruction: write-back necessary bits in EFLAGS. */
314#define _POST_EFLAGS(_sav, _msk, _tmp) \
315 /* _sav |= EFLAGS & _msk; */ \
316 "pushf; " \
317 "pop %"_tmp"; " \
318 "andl %"_msk",%"_LO32 _tmp"; " \
319 "orl %"_LO32 _tmp",%"_sav"; "
320
dda96d8f
AK		 321#ifdef CONFIG_X86_64
322#define ON64(x) x
323#else
324#define ON64(x)
325#endif
326
a31b9cea 327#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 328 do { \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "2") \
331 _op _suffix " %"_x"3,%1; " \
332 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 333 : "=m" ((ctxt)->eflags), \
334 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 335 "=&r" (_tmp) \
a31b9cea 336 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 337 } while (0)
6b7ad61f
AK		 338
339
6aa8b732 340/* Raw emulation: instruction has two explicit operands. */
a31b9cea 341#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 342 do { \
343 unsigned long _tmp; \
344 \
a31b9cea 345 switch ((ctxt)->dst.bytes) { \
6b7ad61f 346 case 2: \
a31b9cea 347 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 348 break; \
349 case 4: \
a31b9cea 350 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 351 break; \
352 case 8: \
a31b9cea 353 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 354 break; \
355 } \
6aa8b732
AK		 356 } while (0)
357
a31b9cea 358#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 359 do { \
6b7ad61f 360 unsigned long _tmp; \
a31b9cea 361 switch ((ctxt)->dst.bytes) { \
6aa8b732 362 case 1: \
a31b9cea 363 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 364 break; \
365 default: \
a31b9cea 366 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 367 _wx, _wy, _lx, _ly, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 373#define emulate_2op_SrcB(ctxt, _op) \
374 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 375
376/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 377#define emulate_2op_SrcV(ctxt, _op) \
378 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 379
380/* Source operand is word, long or quad sized. */
a31b9cea
AK		 381#define emulate_2op_SrcV_nobyte(ctxt, _op) \
382 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 383
d175226a 384/* Instruction has three operands and one operand is stored in ECX register */
29053a60 385#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 386 do { \
387 unsigned long _tmp; \
761441b9
AK		 388 _type _clv = (ctxt)->src2.val; \
389 _type _srcv = (ctxt)->src.val; \
390 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 391 \
392 __asm__ __volatile__ ( \
393 _PRE_EFLAGS("0", "5", "2") \
394 _op _suffix " %4,%1 \n" \
395 _POST_EFLAGS("0", "5", "2") \
761441b9 396 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 397 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
398 ); \
399 \
761441b9
AK		 400 (ctxt)->src2.val = (unsigned long) _clv; \
401 (ctxt)->src2.val = (unsigned long) _srcv; \
402 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 403 } while (0)
404
761441b9 405#define emulate_2op_cl(ctxt, _op) \
7295261c 406 do { \
761441b9 407 switch ((ctxt)->dst.bytes) { \
7295261c 408 case 2: \
29053a60 409 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 410 break; \
411 case 4: \
29053a60 412 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 413 break; \
414 case 8: \
29053a60 415 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 416 break; \
417 } \
d175226a
GT		 418 } while (0)
419
d1eef45d 420#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 421 do { \
422 unsigned long _tmp; \
423 \
dda96d8f
AK		 424 __asm__ __volatile__ ( \
425 _PRE_EFLAGS("0", "3", "2") \
426 _op _suffix " %1; " \
427 _POST_EFLAGS("0", "3", "2") \
d1eef45d 428 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 429 "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK)); \
431 } while (0)
432
433/* Instruction has only one explicit operand (no source operand). */
d1eef45d 434#define emulate_1op(ctxt, _op) \
dda96d8f 435 do { \
d1eef45d
AK		 436 switch ((ctxt)->dst.bytes) { \
437 case 1: __emulate_1op(ctxt, _op, "b"); break; \
438 case 2: __emulate_1op(ctxt, _op, "w"); break; \
439 case 4: __emulate_1op(ctxt, _op, "l"); break; \
440 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 441 } \
442 } while (0)
443
b7d491e7
AK		 444#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
445#define FOP_RET "ret \n\t"
446
447#define FOP_START(op) \
448 extern void em_##op(struct fastop *fake); \
449 asm(".pushsection .text, \"ax\" \n\t" \
450 ".global em_" #op " \n\t" \
451 FOP_ALIGN \
452 "em_" #op ": \n\t"
453
454#define FOP_END \
455 ".popsection")
456
457#define FOP1E(op, dst) \
458 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
459
460#define FASTOP1(op) \
461 FOP_START(op) \
462 FOP1E(op##b, al) \
463 FOP1E(op##w, ax) \
464 FOP1E(op##l, eax) \
465 ON64(FOP1E(op##q, rax)) \
466 FOP_END
467
f7857f35
AK		 468#define FOP2E(op, dst, src) \
469 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
470
471#define FASTOP2(op) \
472 FOP_START(op) \
473 FOP2E(op##b, al, bl) \
474 FOP2E(op##w, ax, bx) \
475 FOP2E(op##l, eax, ebx) \
476 ON64(FOP2E(op##q, rax, rbx)) \
477 FOP_END
478
e8f2b1d6 479#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 480 do { \
481 unsigned long _tmp; \
dd856efa
AK		 482 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \
483 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \
f6b3597b
AK		 484 \
485 __asm__ __volatile__ ( \
486 _PRE_EFLAGS("0", "5", "1") \
487 "1: \n\t" \
488 _op _suffix " %6; " \
489 "2: \n\t" \
490 _POST_EFLAGS("0", "5", "1") \
491 ".pushsection .fixup,\"ax\" \n\t" \
492 "3: movb $1, %4 \n\t" \
493 "jmp 2b \n\t" \
494 ".popsection \n\t" \
495 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 496 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
497 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
cb7cb286 498 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \
f6b3597b
AK		 499 } while (0)
500
3f9f53b0 501/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 502#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 503 do { \
e8f2b1d6 504 switch((ctxt)->src.bytes) { \
7295261c 505 case 1: \
e8f2b1d6 506 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 507 break; \
508 case 2: \
e8f2b1d6 509 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 510 break; \
511 case 4: \
e8f2b1d6 512 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 513 break; \
514 case 8: ON64( \
e8f2b1d6 515 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 516 break; \
517 } \
518 } while (0)
519
8a76d7f2
JR		 520static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
521 enum x86_intercept intercept,
522 enum x86_intercept_stage stage)
523{
524 struct x86_instruction_info info = {
525 .intercept = intercept,
9dac77fa
AK		 526 .rep_prefix = ctxt->rep_prefix,
527 .modrm_mod = ctxt->modrm_mod,
528 .modrm_reg = ctxt->modrm_reg,
529 .modrm_rm = ctxt->modrm_rm,
530 .src_val = ctxt->src.val64,
531 .src_bytes = ctxt->src.bytes,
532 .dst_bytes = ctxt->dst.bytes,
533 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 534 .next_rip = ctxt->eip,
535 };
536
2953538e 537 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 538}
539
f47cfa31
AK		 540static void assign_masked(ulong *dest, ulong src, ulong mask)
541{
542 *dest = (*dest & ~mask) | (src & mask);
543}
544
9dac77fa 545static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 546{
9dac77fa 547 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 548}
549
f47cfa31
AK		 550static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
551{
552 u16 sel;
553 struct desc_struct ss;
554
555 if (ctxt->mode == X86EMUL_MODE_PROT64)
556 return ~0UL;
557 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
558 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
559}
560
612e89f0
AK		 561static int stack_size(struct x86_emulate_ctxt *ctxt)
562{
563 return (__fls(stack_mask(ctxt)) + 1) >> 3;
564}
565
6aa8b732 566/* Access/update address held in a register, based on addressing mode. */
e4706772 567static inline unsigned long
9dac77fa 568address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 569{
9dac77fa 570 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 571 return reg;
572 else
9dac77fa 573 return reg & ad_mask(ctxt);
e4706772
HH		 574}
575
576static inline unsigned long
9dac77fa 577register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 578{
9dac77fa 579 return address_mask(ctxt, reg);
e4706772
HH		 580}
581
5ad105e5
AK		 582static void masked_increment(ulong *reg, ulong mask, int inc)
583{
584 assign_masked(reg, *reg + inc, mask);
585}
586
7a957275 587static inline void
9dac77fa 588register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 589{
5ad105e5
AK		 590 ulong mask;
591
9dac77fa 592 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 593 mask = ~0UL;
7a957275 594 else
5ad105e5
AK		 595 mask = ad_mask(ctxt);
596 masked_increment(reg, mask, inc);
597}
598
599static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
600{
dd856efa 601 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 602}
6aa8b732 603
9dac77fa 604static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 605{
9dac77fa 606 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 607}
098c937b 608
56697687
AK		 609static u32 desc_limit_scaled(struct desc_struct *desc)
610{
611 u32 limit = get_desc_limit(desc);
612
613 return desc->g ? (limit << 12) | 0xfff : limit;
614}
615
9dac77fa 616static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 617{
9dac77fa
AK		 618 ctxt->has_seg_override = true;
619 ctxt->seg_override = seg;
7a5b56df
AK		 620}
621
7b105ca2 622static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 623{
624 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
625 return 0;
626
7b105ca2 627 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 628}
629
9dac77fa 630static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 631{
9dac77fa 632 if (!ctxt->has_seg_override)
7a5b56df
AK		 633 return 0;
634
9dac77fa 635 return ctxt->seg_override;
7a5b56df
AK		 636}
637
35d3d4a1
AK		 638static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
639 u32 error, bool valid)
54b8486f 640{
da9cb575
AK		 641 ctxt->exception.vector = vec;
642 ctxt->exception.error_code = error;
643 ctxt->exception.error_code_valid = valid;
35d3d4a1 644 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 645}
646
3b88e41a
JR		 647static int emulate_db(struct x86_emulate_ctxt *ctxt)
648{
649 return emulate_exception(ctxt, DB_VECTOR, 0, false);
650}
651
35d3d4a1 652static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 653{
35d3d4a1 654 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 655}
656
618ff15d
AK		 657static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
658{
659 return emulate_exception(ctxt, SS_VECTOR, err, true);
660}
661
35d3d4a1 662static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 663{
35d3d4a1 664 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 665}
666
35d3d4a1 667static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 668{
35d3d4a1 669 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 670}
671
34d1f490
AK		 672static int emulate_de(struct x86_emulate_ctxt *ctxt)
673{
35d3d4a1 674 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 675}
676
1253791d
AK		 677static int emulate_nm(struct x86_emulate_ctxt *ctxt)
678{
679 return emulate_exception(ctxt, NM_VECTOR, 0, false);
680}
681
1aa36616
AK		 682static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
683{
684 u16 selector;
685 struct desc_struct desc;
686
687 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
688 return selector;
689}
690
691static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
692 unsigned seg)
693{
694 u16 dummy;
695 u32 base3;
696 struct desc_struct desc;
697
698 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
699 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
700}
701
1c11b376
AK		 702/*
703 * x86 defines three classes of vector instructions: explicitly
704 * aligned, explicitly unaligned, and the rest, which change behaviour
705 * depending on whether they're AVX encoded or not.
706 *
707 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
708 * subject to the same check.
709 */
710static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
711{
712 if (likely(size < 16))
713 return false;
714
715 if (ctxt->d & Aligned)
716 return true;
717 else if (ctxt->d & Unaligned)
718 return false;
719 else if (ctxt->d & Avx)
720 return false;
721 else
722 return true;
723}
724
3d9b938e 725static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 726 struct segmented_address addr,
3d9b938e 727 unsigned size, bool write, bool fetch,
52fd8b44
AK		 728 ulong *linear)
729{
618ff15d
AK		 730 struct desc_struct desc;
731 bool usable;
52fd8b44 732 ulong la;
618ff15d 733 u32 lim;
1aa36616 734 u16 sel;
3a78a4f4 735 unsigned cpl;
52fd8b44 736
7b105ca2 737 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 738 switch (ctxt->mode) {
618ff15d
AK		 739 case X86EMUL_MODE_PROT64:
740 if (((signed long)la << 16) >> 16 != la)
741 return emulate_gp(ctxt, 0);
742 break;
743 default:
1aa36616
AK		 744 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
745 addr.seg);
618ff15d
AK		 746 if (!usable)
747 goto bad;
58b7825b
GN		 748 /* code segment in protected mode or read-only data segment */
749 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
750 || !(desc.type & 2)) && write)
618ff15d
AK		 751 goto bad;
752 /* unreadable code segment */
3d9b938e 753 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 754 goto bad;
755 lim = desc_limit_scaled(&desc);
756 if ((desc.type & 8) || !(desc.type & 4)) {
757 /* expand-up segment */
758 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
759 goto bad;
760 } else {
fc058680 761 /* expand-down segment */
618ff15d
AK		 762 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
763 goto bad;
764 lim = desc.d ? 0xffffffff : 0xffff;
765 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
766 goto bad;
767 }
717746e3 768 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 769 if (!(desc.type & 8)) {
770 /* data segment */
771 if (cpl > desc.dpl)
772 goto bad;
773 } else if ((desc.type & 8) && !(desc.type & 4)) {
774 /* nonconforming code segment */
775 if (cpl != desc.dpl)
776 goto bad;
777 } else if ((desc.type & 8) && (desc.type & 4)) {
778 /* conforming code segment */
779 if (cpl < desc.dpl)
780 goto bad;
781 }
782 break;
783 }
9dac77fa 784 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 785 la &= (u32)-1;
1c11b376
AK		 786 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
787 return emulate_gp(ctxt, 0);
52fd8b44
AK		 788 *linear = la;
789 return X86EMUL_CONTINUE;
618ff15d
AK		 790bad:
791 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 792 return emulate_ss(ctxt, sel);
618ff15d 793 else
0afbe2f8 794 return emulate_gp(ctxt, sel);
52fd8b44
AK		 795}
796
3d9b938e
NE		 797static int linearize(struct x86_emulate_ctxt *ctxt,
798 struct segmented_address addr,
799 unsigned size, bool write,
800 ulong *linear)
801{
802 return __linearize(ctxt, addr, size, write, false, linear);
803}
804
805
3ca3ac4d
AK		 806static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
807 struct segmented_address addr,
808 void *data,
809 unsigned size)
810{
9fa088f4
AK		 811 int rc;
812 ulong linear;
813
83b8795a 814 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 815 if (rc != X86EMUL_CONTINUE)
816 return rc;
0f65dd70 817 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 818}
819
807941b1
TY		 820/*
821 * Fetch the next byte of the instruction being emulated which is pointed to
822 * by ctxt->_eip, then increment ctxt->_eip.
823 *
824 * Also prefetch the remaining bytes of the instruction without crossing page
825 * boundary if they are not in fetch_cache yet.
826 */
827static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 828{
9dac77fa 829 struct fetch_cache *fc = &ctxt->fetch;
62266869 830 int rc;
2fb53ad8 831 int size, cur_size;
62266869 832
807941b1 833 if (ctxt->_eip == fc->end) {
3d9b938e 834 unsigned long linear;
807941b1
TY		 835 struct segmented_address addr = { .seg = VCPU_SREG_CS,
836 .ea = ctxt->_eip };
2fb53ad8 837 cur_size = fc->end - fc->start;
807941b1
TY		 838 size = min(15UL - cur_size,
839 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 840 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 841 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 842 return rc;
ef5d75cc
TY		 843 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
844 size, &ctxt->exception);
7d88bb48 845 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 846 return rc;
2fb53ad8 847 fc->end += size;
62266869 848 }
807941b1
TY		 849 *dest = fc->data[ctxt->_eip - fc->start];
850 ctxt->_eip++;
3e2815e9 851 return X86EMUL_CONTINUE;
62266869
AK		 852}
853
854static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 855 void *dest, unsigned size)
62266869 856{
3e2815e9 857 int rc;
62266869 858
eb3c79e6 859 /* x86 instructions are limited to 15 bytes. */
7d88bb48 860 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 861 return X86EMUL_UNHANDLEABLE;
62266869 862 while (size--) {
807941b1 863 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 864 if (rc != X86EMUL_CONTINUE)
62266869
AK		 865 return rc;
866 }
3e2815e9 867 return X86EMUL_CONTINUE;
62266869
AK		 868}
869
67cbc90d 870/* Fetch next part of the instruction being emulated. */
e85a1085 871#define insn_fetch(_type, _ctxt) \
67cbc90d 872({ unsigned long _x; \
e85a1085 873 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 874 if (rc != X86EMUL_CONTINUE) \
875 goto done; \
67cbc90d
TY		 876 (_type)_x; \
877})
878
807941b1
TY		 879#define insn_fetch_arr(_arr, _size, _ctxt) \
880({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 881 if (rc != X86EMUL_CONTINUE) \
882 goto done; \
67cbc90d
TY		 883})
884
1e3c5cb0
RR		 885/*
886 * Given the 'reg' portion of a ModRM byte, and a register block, return a
887 * pointer into the block that addresses the relevant register.
888 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
889 */
dd856efa 890static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
1e3c5cb0 891 int highbyte_regs)
6aa8b732
AK		 892{
893 void *p;
894
6aa8b732 895 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 896 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
897 else
898 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 899 return p;
900}
901
902static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 903 struct segmented_address addr,
6aa8b732
AK		 904 u16 *size, unsigned long *address, int op_bytes)
905{
906 int rc;
907
908 if (op_bytes == 2)
909 op_bytes = 3;
910 *address = 0;
3ca3ac4d 911 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 912 if (rc != X86EMUL_CONTINUE)
6aa8b732 913 return rc;
30b31ab6 914 addr.ea += 2;
3ca3ac4d 915 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 916 return rc;
917}
918
bbe9abbd
NK		 919static int test_cc(unsigned int condition, unsigned int flags)
920{
921 int rc = 0;
922
923 switch ((condition & 15) >> 1) {
924 case 0: /* o */
925 rc |= (flags & EFLG_OF);
926 break;
927 case 1: /* b/c/nae */
928 rc |= (flags & EFLG_CF);
929 break;
930 case 2: /* z/e */
931 rc |= (flags & EFLG_ZF);
932 break;
933 case 3: /* be/na */
934 rc |= (flags & (EFLG_CF|EFLG_ZF));
935 break;
936 case 4: /* s */
937 rc |= (flags & EFLG_SF);
938 break;
939 case 5: /* p/pe */
940 rc |= (flags & EFLG_PF);
941 break;
942 case 7: /* le/ng */
943 rc |= (flags & EFLG_ZF);
944 /* fall through */
945 case 6: /* l/nge */
946 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
947 break;
948 }
949
950 /* Odd condition identifiers (lsb == 1) have inverted sense. */
951 return (!!rc ^ (condition & 1));
952}
953
91ff3cb4
AK		 954static void fetch_register_operand(struct operand *op)
955{
956 switch (op->bytes) {
957 case 1:
958 op->val = *(u8 *)op->addr.reg;
959 break;
960 case 2:
961 op->val = *(u16 *)op->addr.reg;
962 break;
963 case 4:
964 op->val = *(u32 *)op->addr.reg;
965 break;
966 case 8:
967 op->val = *(u64 *)op->addr.reg;
968 break;
969 }
970}
971
1253791d
AK		 972static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
973{
974 ctxt->ops->get_fpu(ctxt);
975 switch (reg) {
89a87c67
MK		 976 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
977 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
978 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
979 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
980 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
981 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
982 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
983 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 984#ifdef CONFIG_X86_64
89a87c67
MK		 985 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
986 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
987 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
988 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
989 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
990 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
991 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
992 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 993#endif
994 default: BUG();
995 }
996 ctxt->ops->put_fpu(ctxt);
997}
998
999static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1000 int reg)
1001{
1002 ctxt->ops->get_fpu(ctxt);
1003 switch (reg) {
89a87c67
MK		 1004 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1005 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1006 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1007 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1008 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1009 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1010 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1011 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1012#ifdef CONFIG_X86_64
89a87c67
MK		 1013 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1014 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1015 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1016 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1017 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1018 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1019 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1020 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1021#endif
1022 default: BUG();
1023 }
1024 ctxt->ops->put_fpu(ctxt);
1025}
1026
cbe2c9d3
AK		 1027static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1028{
1029 ctxt->ops->get_fpu(ctxt);
1030 switch (reg) {
1031 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1032 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1033 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1034 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1035 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1036 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1037 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1038 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1039 default: BUG();
1040 }
1041 ctxt->ops->put_fpu(ctxt);
1042}
1043
1044static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1045{
1046 ctxt->ops->get_fpu(ctxt);
1047 switch (reg) {
1048 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1049 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1050 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1051 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1052 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1053 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1054 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1055 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1056 default: BUG();
1057 }
1058 ctxt->ops->put_fpu(ctxt);
1059}
1060
045a282c
GN		 1061static int em_fninit(struct x86_emulate_ctxt *ctxt)
1062{
1063 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1064 return emulate_nm(ctxt);
1065
1066 ctxt->ops->get_fpu(ctxt);
1067 asm volatile("fninit");
1068 ctxt->ops->put_fpu(ctxt);
1069 return X86EMUL_CONTINUE;
1070}
1071
1072static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1073{
1074 u16 fcw;
1075
1076 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1077 return emulate_nm(ctxt);
1078
1079 ctxt->ops->get_fpu(ctxt);
1080 asm volatile("fnstcw %0": "+m"(fcw));
1081 ctxt->ops->put_fpu(ctxt);
1082
1083 /* force 2 byte destination */
1084 ctxt->dst.bytes = 2;
1085 ctxt->dst.val = fcw;
1086
1087 return X86EMUL_CONTINUE;
1088}
1089
1090static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1091{
1092 u16 fsw;
1093
1094 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1095 return emulate_nm(ctxt);
1096
1097 ctxt->ops->get_fpu(ctxt);
1098 asm volatile("fnstsw %0": "+m"(fsw));
1099 ctxt->ops->put_fpu(ctxt);
1100
1101 /* force 2 byte destination */
1102 ctxt->dst.bytes = 2;
1103 ctxt->dst.val = fsw;
1104
1105 return X86EMUL_CONTINUE;
1106}
1107
1253791d 1108static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1109 struct operand *op)
3c118e24 1110{
9dac77fa
AK		 1111 unsigned reg = ctxt->modrm_reg;
1112 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 1113
9dac77fa
AK		 1114 if (!(ctxt->d & ModRM))
1115 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1116
9dac77fa 1117 if (ctxt->d & Sse) {
1253791d
AK		 1118 op->type = OP_XMM;
1119 op->bytes = 16;
1120 op->addr.xmm = reg;
1121 read_sse_reg(ctxt, &op->vec_val, reg);
1122 return;
1123 }
cbe2c9d3
AK		 1124 if (ctxt->d & Mmx) {
1125 reg &= 7;
1126 op->type = OP_MM;
1127 op->bytes = 8;
1128 op->addr.mm = reg;
1129 return;
1130 }
1253791d 1131
3c118e24 1132 op->type = OP_REG;
2adb5ad9 1133 if (ctxt->d & ByteOp) {
dd856efa 1134 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
3c118e24
AK		 1135 op->bytes = 1;
1136 } else {
dd856efa 1137 op->addr.reg = decode_register(ctxt, reg, 0);
9dac77fa 1138 op->bytes = ctxt->op_bytes;
3c118e24 1139 }
91ff3cb4 1140 fetch_register_operand(op);
3c118e24
AK		 1141 op->orig_val = op->val;
1142}
1143
a6e3407b
AK		 1144static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1145{
1146 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1147 ctxt->modrm_seg = VCPU_SREG_SS;
1148}
1149
1c73ef66 1150static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1151 struct operand *op)
1c73ef66 1152{
1c73ef66 1153 u8 sib;
f5b4edcd 1154 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1155 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1156 ulong modrm_ea = 0;
1c73ef66 1157
9dac77fa
AK		 1158 if (ctxt->rex_prefix) {
1159 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1160 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1161 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1162 }
1163
9dac77fa
AK		 1164 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1165 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1166 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1167 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1168
9dac77fa 1169 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1170 op->type = OP_REG;
9dac77fa 1171 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 1172 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
9dac77fa 1173 if (ctxt->d & Sse) {
1253791d
AK		 1174 op->type = OP_XMM;
1175 op->bytes = 16;
9dac77fa
AK		 1176 op->addr.xmm = ctxt->modrm_rm;
1177 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1178 return rc;
1179 }
cbe2c9d3
AK		 1180 if (ctxt->d & Mmx) {
1181 op->type = OP_MM;
1182 op->bytes = 8;
1183 op->addr.xmm = ctxt->modrm_rm & 7;
1184 return rc;
1185 }
2dbd0dd7 1186 fetch_register_operand(op);
1c73ef66
AK		 1187 return rc;
1188 }
1189
2dbd0dd7
AK		 1190 op->type = OP_MEM;
1191
9dac77fa 1192 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1193 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1194 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1195 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1196 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1197
1198 /* 16-bit ModR/M decode. */
9dac77fa 1199 switch (ctxt->modrm_mod) {
1c73ef66 1200 case 0:
9dac77fa 1201 if (ctxt->modrm_rm == 6)
e85a1085 1202 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1203 break;
1204 case 1:
e85a1085 1205 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1206 break;
1207 case 2:
e85a1085 1208 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1209 break;
1210 }
9dac77fa 1211 switch (ctxt->modrm_rm) {
1c73ef66 1212 case 0:
2dbd0dd7 1213 modrm_ea += bx + si;
1c73ef66
AK		 1214 break;
1215 case 1:
2dbd0dd7 1216 modrm_ea += bx + di;
1c73ef66
AK		 1217 break;
1218 case 2:
2dbd0dd7 1219 modrm_ea += bp + si;
1c73ef66
AK		 1220 break;
1221 case 3:
2dbd0dd7 1222 modrm_ea += bp + di;
1c73ef66
AK		 1223 break;
1224 case 4:
2dbd0dd7 1225 modrm_ea += si;
1c73ef66
AK		 1226 break;
1227 case 5:
2dbd0dd7 1228 modrm_ea += di;
1c73ef66
AK		 1229 break;
1230 case 6:
9dac77fa 1231 if (ctxt->modrm_mod != 0)
2dbd0dd7 1232 modrm_ea += bp;
1c73ef66
AK		 1233 break;
1234 case 7:
2dbd0dd7 1235 modrm_ea += bx;
1c73ef66
AK		 1236 break;
1237 }
9dac77fa
AK		 1238 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1239 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1240 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1241 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1242 } else {
1243 /* 32/64-bit ModR/M decode. */
9dac77fa 1244 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1245 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1246 index_reg |= (sib >> 3) & 7;
1247 base_reg |= sib & 7;
1248 scale = sib >> 6;
1249
9dac77fa 1250 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1251 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1252 else {
dd856efa 1253 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1254 adjust_modrm_seg(ctxt, base_reg);
1255 }
dc71d0f1 1256 if (index_reg != 4)
dd856efa 1257 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1258 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1259 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1260 ctxt->rip_relative = 1;
a6e3407b
AK		 1261 } else {
1262 base_reg = ctxt->modrm_rm;
dd856efa 1263 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1264 adjust_modrm_seg(ctxt, base_reg);
1265 }
9dac77fa 1266 switch (ctxt->modrm_mod) {
1c73ef66 1267 case 0:
9dac77fa 1268 if (ctxt->modrm_rm == 5)
e85a1085 1269 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1270 break;
1271 case 1:
e85a1085 1272 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1273 break;
1274 case 2:
e85a1085 1275 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1276 break;
1277 }
1278 }
90de84f5 1279 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1280done:
1281 return rc;
1282}
1283
1284static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1285 struct operand *op)
1c73ef66 1286{
3e2815e9 1287 int rc = X86EMUL_CONTINUE;
1c73ef66 1288
2dbd0dd7 1289 op->type = OP_MEM;
9dac77fa 1290 switch (ctxt->ad_bytes) {
1c73ef66 1291 case 2:
e85a1085 1292 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1293 break;
1294 case 4:
e85a1085 1295 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1296 break;
1297 case 8:
e85a1085 1298 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1299 break;
1300 }
1301done:
1302 return rc;
1303}
1304
9dac77fa 1305static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1306{
7129eeca 1307 long sv = 0, mask;
35c843c4 1308
9dac77fa
AK		 1309 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1310 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1311
9dac77fa
AK		 1312 if (ctxt->src.bytes == 2)
1313 sv = (s16)ctxt->src.val & (s16)mask;
1314 else if (ctxt->src.bytes == 4)
1315 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1316
9dac77fa 1317 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1318 }
ba7ff2b7
WY		 1319
1320 /* only subword offset */
9dac77fa 1321 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1322}
1323
dde7e6d1 1324static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1325 unsigned long addr, void *dest, unsigned size)
6aa8b732 1326{
dde7e6d1 1327 int rc;
9dac77fa 1328 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1329
f23b070e
XG		 1330 if (mc->pos < mc->end)
1331 goto read_cached;
6aa8b732 1332
f23b070e
XG		 1333 WARN_ON((mc->end + size) >= sizeof(mc->data));
1334
1335 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1336 &ctxt->exception);
1337 if (rc != X86EMUL_CONTINUE)
1338 return rc;
1339
1340 mc->end += size;
1341
1342read_cached:
1343 memcpy(dest, mc->data + mc->pos, size);
1344 mc->pos += size;
dde7e6d1
AK		 1345 return X86EMUL_CONTINUE;
1346}
6aa8b732 1347
3ca3ac4d
AK		 1348static int segmented_read(struct x86_emulate_ctxt *ctxt,
1349 struct segmented_address addr,
1350 void *data,
1351 unsigned size)
1352{
9fa088f4
AK		 1353 int rc;
1354 ulong linear;
1355
83b8795a 1356 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1357 if (rc != X86EMUL_CONTINUE)
1358 return rc;
7b105ca2 1359 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1360}
1361
1362static int segmented_write(struct x86_emulate_ctxt *ctxt,
1363 struct segmented_address addr,
1364 const void *data,
1365 unsigned size)
1366{
9fa088f4
AK		 1367 int rc;
1368 ulong linear;
1369
83b8795a 1370 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1371 if (rc != X86EMUL_CONTINUE)
1372 return rc;
0f65dd70
AK		 1373 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1374 &ctxt->exception);
3ca3ac4d
AK		 1375}
1376
1377static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1378 struct segmented_address addr,
1379 const void *orig_data, const void *data,
1380 unsigned size)
1381{
9fa088f4
AK		 1382 int rc;
1383 ulong linear;
1384
83b8795a 1385 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1386 if (rc != X86EMUL_CONTINUE)
1387 return rc;
0f65dd70
AK		 1388 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1389 size, &ctxt->exception);
3ca3ac4d
AK		 1390}
1391
dde7e6d1 1392static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1393 unsigned int size, unsigned short port,
1394 void *dest)
1395{
9dac77fa 1396 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1397
dde7e6d1 1398 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1399 unsigned int in_page, n;
9dac77fa 1400 unsigned int count = ctxt->rep_prefix ?
dd856efa 1401 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1402 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1403 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1404 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1405 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1406 count);
1407 if (n == 0)
1408 n = 1;
1409 rc->pos = rc->end = 0;
7b105ca2 1410 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1411 return 0;
1412 rc->end = n * size;
6aa8b732
AK		 1413 }
1414
b3356bf0
GN		 1415 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1416 ctxt->dst.data = rc->data + rc->pos;
1417 ctxt->dst.type = OP_MEM_STR;
1418 ctxt->dst.count = (rc->end - rc->pos) / size;
1419 rc->pos = rc->end;
1420 } else {
1421 memcpy(dest, rc->data + rc->pos, size);
1422 rc->pos += size;
1423 }
dde7e6d1
AK		 1424 return 1;
1425}
6aa8b732 1426
7f3d35fd
KW		 1427static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1428 u16 index, struct desc_struct *desc)
1429{
1430 struct desc_ptr dt;
1431 ulong addr;
1432
1433 ctxt->ops->get_idt(ctxt, &dt);
1434
1435 if (dt.size < index * 8 + 7)
1436 return emulate_gp(ctxt, index << 3 | 0x2);
1437
1438 addr = dt.address + index * 8;
1439 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1440 &ctxt->exception);
1441}
1442
dde7e6d1 1443static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1444 u16 selector, struct desc_ptr *dt)
1445{
0225fb50 1446 const struct x86_emulate_ops *ops = ctxt->ops;
7b105ca2 1447
dde7e6d1
AK		 1448 if (selector & 1 << 2) {
1449 struct desc_struct desc;
1aa36616
AK		 1450 u16 sel;
1451
dde7e6d1 1452 memset (dt, 0, sizeof *dt);
1aa36616 1453 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1454 return;
e09d082c 1455
dde7e6d1
AK		 1456 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1457 dt->address = get_desc_base(&desc);
1458 } else
4bff1e86 1459 ops->get_gdt(ctxt, dt);
dde7e6d1 1460}
120df890 1461
dde7e6d1
AK		 1462/* allowed just for 8 bytes segments */
1463static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1464 u16 selector, struct desc_struct *desc,
1465 ulong *desc_addr_p)
dde7e6d1
AK		 1466{
1467 struct desc_ptr dt;
1468 u16 index = selector >> 3;
dde7e6d1 1469 ulong addr;
120df890 1470
7b105ca2 1471 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1472
35d3d4a1
AK		 1473 if (dt.size < index * 8 + 7)
1474 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1475
e919464b 1476 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1477 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1478 &ctxt->exception);
dde7e6d1 1479}
ef65c889 1480
dde7e6d1
AK		 1481/* allowed just for 8 bytes segments */
1482static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1483 u16 selector, struct desc_struct *desc)
1484{
1485 struct desc_ptr dt;
1486 u16 index = selector >> 3;
dde7e6d1 1487 ulong addr;
6aa8b732 1488
7b105ca2 1489 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1490
35d3d4a1
AK		 1491 if (dt.size < index * 8 + 7)
1492 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1493
dde7e6d1 1494 addr = dt.address + index * 8;
7b105ca2
TY		 1495 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1496 &ctxt->exception);
dde7e6d1 1497}
c7e75a3d 1498
5601d05b 1499/* Does not support long mode */
dde7e6d1 1500static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1501 u16 selector, int seg)
1502{
869be99c 1503 struct desc_struct seg_desc, old_desc;
dde7e6d1
AK		 1504 u8 dpl, rpl, cpl;
1505 unsigned err_vec = GP_VECTOR;
1506 u32 err_code = 0;
1507 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1508 ulong desc_addr;
dde7e6d1 1509 int ret;
03ebebeb 1510 u16 dummy;
69f55cb1 1511
dde7e6d1 1512 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1513
dde7e6d1
AK		 1514 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1515 || ctxt->mode == X86EMUL_MODE_REAL) {
1516 /* set real mode segment descriptor */
03ebebeb 1517 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1518 set_desc_base(&seg_desc, selector << 4);
dde7e6d1
AK		 1519 goto load;
1520 }
1521
79d5b4c3
AK		 1522 rpl = selector & 3;
1523 cpl = ctxt->ops->cpl(ctxt);
1524
1525 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1526 if ((seg == VCPU_SREG_CS
1527 || (seg == VCPU_SREG_SS
1528 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1529 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1530 && null_selector)
1531 goto exception;
1532
1533 /* TR should be in GDT only */
1534 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1535 goto exception;
1536
1537 if (null_selector) /* for NULL selector skip all following checks */
1538 goto load;
1539
e919464b 1540 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1541 if (ret != X86EMUL_CONTINUE)
1542 return ret;
1543
1544 err_code = selector & 0xfffc;
1545 err_vec = GP_VECTOR;
1546
fc058680 1547 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1548 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1549 goto exception;
1550
1551 if (!seg_desc.p) {
1552 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1553 goto exception;
1554 }
1555
dde7e6d1 1556 dpl = seg_desc.dpl;
dde7e6d1
AK		 1557
1558 switch (seg) {
1559 case VCPU_SREG_SS:
1560 /*
1561 * segment is not a writable data segment or segment
1562 * selector's RPL != CPL or segment selector's RPL != CPL
1563 */
1564 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1565 goto exception;
6aa8b732 1566 break;
dde7e6d1
AK		 1567 case VCPU_SREG_CS:
1568 if (!(seg_desc.type & 8))
1569 goto exception;
1570
1571 if (seg_desc.type & 4) {
1572 /* conforming */
1573 if (dpl > cpl)
1574 goto exception;
1575 } else {
1576 /* nonconforming */
1577 if (rpl > cpl || dpl != cpl)
1578 goto exception;
1579 }
1580 /* CS(RPL) <- CPL */
1581 selector = (selector & 0xfffc) | cpl;
6aa8b732 1582 break;
dde7e6d1
AK		 1583 case VCPU_SREG_TR:
1584 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1585 goto exception;
869be99c
AK		 1586 old_desc = seg_desc;
1587 seg_desc.type |= 2; /* busy */
1588 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1589 sizeof(seg_desc), &ctxt->exception);
1590 if (ret != X86EMUL_CONTINUE)
1591 return ret;
dde7e6d1
AK		 1592 break;
1593 case VCPU_SREG_LDTR:
1594 if (seg_desc.s || seg_desc.type != 2)
1595 goto exception;
1596 break;
1597 default: /* DS, ES, FS, or GS */
4e62417b 1598 /*
dde7e6d1
AK		 1599 * segment is not a data or readable code segment or
1600 * ((segment is a data or nonconforming code segment)
1601 * and (both RPL and CPL > DPL))
4e62417b 1602 */
dde7e6d1
AK		 1603 if ((seg_desc.type & 0xa) == 0x8 ||
1604 (((seg_desc.type & 0xc) != 0xc) &&
1605 (rpl > dpl && cpl > dpl)))
1606 goto exception;
6aa8b732 1607 break;
dde7e6d1
AK		 1608 }
1609
1610 if (seg_desc.s) {
1611 /* mark segment as accessed */
1612 seg_desc.type |= 1;
7b105ca2 1613 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1614 if (ret != X86EMUL_CONTINUE)
1615 return ret;
1616 }
1617load:
7b105ca2 1618 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1619 return X86EMUL_CONTINUE;
1620exception:
1621 emulate_exception(ctxt, err_vec, err_code, true);
1622 return X86EMUL_PROPAGATE_FAULT;
1623}
1624
31be40b3
WY		 1625static void write_register_operand(struct operand *op)
1626{
1627 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1628 switch (op->bytes) {
1629 case 1:
1630 *(u8 *)op->addr.reg = (u8)op->val;
1631 break;
1632 case 2:
1633 *(u16 *)op->addr.reg = (u16)op->val;
1634 break;
1635 case 4:
1636 *op->addr.reg = (u32)op->val;
1637 break; /* 64b: zero-extend */
1638 case 8:
1639 *op->addr.reg = op->val;
1640 break;
1641 }
1642}
1643
adddcecf 1644static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1645{
1646 int rc;
dde7e6d1 1647
b6744dc3
AK		 1648 if (ctxt->d & NoWrite)
1649 return X86EMUL_CONTINUE;
1650
9dac77fa 1651 switch (ctxt->dst.type) {
dde7e6d1 1652 case OP_REG:
9dac77fa 1653 write_register_operand(&ctxt->dst);
6aa8b732 1654 break;
dde7e6d1 1655 case OP_MEM:
9dac77fa 1656 if (ctxt->lock_prefix)
3ca3ac4d 1657 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1658 ctxt->dst.addr.mem,
1659 &ctxt->dst.orig_val,
1660 &ctxt->dst.val,
1661 ctxt->dst.bytes);
341de7e3 1662 else
3ca3ac4d 1663 rc = segmented_write(ctxt,
9dac77fa
AK		 1664 ctxt->dst.addr.mem,
1665 &ctxt->dst.val,
1666 ctxt->dst.bytes);
dde7e6d1
AK		 1667 if (rc != X86EMUL_CONTINUE)
1668 return rc;
a682e354 1669 break;
b3356bf0
GN		 1670 case OP_MEM_STR:
1671 rc = segmented_write(ctxt,
1672 ctxt->dst.addr.mem,
1673 ctxt->dst.data,
1674 ctxt->dst.bytes * ctxt->dst.count);
1675 if (rc != X86EMUL_CONTINUE)
1676 return rc;
1677 break;
1253791d 1678 case OP_XMM:
9dac77fa 1679 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1680 break;
cbe2c9d3
AK		 1681 case OP_MM:
1682 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1683 break;
dde7e6d1
AK		 1684 case OP_NONE:
1685 /* no writeback */
414e6277 1686 break;
dde7e6d1 1687 default:
414e6277 1688 break;
6aa8b732 1689 }
dde7e6d1
AK		 1690 return X86EMUL_CONTINUE;
1691}
6aa8b732 1692
51ddff50 1693static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1694{
4179bb02 1695 struct segmented_address addr;
0dc8d10f 1696
5ad105e5 1697 rsp_increment(ctxt, -bytes);
dd856efa 1698 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1699 addr.seg = VCPU_SREG_SS;
1700
51ddff50
AK		 1701 return segmented_write(ctxt, addr, data, bytes);
1702}
1703
1704static int em_push(struct x86_emulate_ctxt *ctxt)
1705{
4179bb02 1706 /* Disable writeback. */
9dac77fa 1707 ctxt->dst.type = OP_NONE;
51ddff50 1708 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1709}
69f55cb1 1710
dde7e6d1 1711static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1712 void *dest, int len)
1713{
dde7e6d1 1714 int rc;
90de84f5 1715 struct segmented_address addr;
8b4caf66 1716
dd856efa 1717 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1718 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1719 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1720 if (rc != X86EMUL_CONTINUE)
1721 return rc;
1722
5ad105e5 1723 rsp_increment(ctxt, len);
dde7e6d1 1724 return rc;
8b4caf66
LV		 1725}
1726
c54fe504
TY		 1727static int em_pop(struct x86_emulate_ctxt *ctxt)
1728{
9dac77fa 1729 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1730}
1731
dde7e6d1 1732static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1733 void *dest, int len)
9de41573
GN		 1734{
1735 int rc;
dde7e6d1
AK		 1736 unsigned long val, change_mask;
1737 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1738 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1739
3b9be3bf 1740 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1741 if (rc != X86EMUL_CONTINUE)
1742 return rc;
9de41573 1743
dde7e6d1
AK		 1744 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1745 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1746
dde7e6d1
AK		 1747 switch(ctxt->mode) {
1748 case X86EMUL_MODE_PROT64:
1749 case X86EMUL_MODE_PROT32:
1750 case X86EMUL_MODE_PROT16:
1751 if (cpl == 0)
1752 change_mask |= EFLG_IOPL;
1753 if (cpl <= iopl)
1754 change_mask |= EFLG_IF;
1755 break;
1756 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1757 if (iopl < 3)
1758 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1759 change_mask |= EFLG_IF;
1760 break;
1761 default: /* real mode */
1762 change_mask |= (EFLG_IOPL | EFLG_IF);
1763 break;
9de41573 1764 }
dde7e6d1
AK		 1765
1766 *(unsigned long *)dest =
1767 (ctxt->eflags & ~change_mask) | (val & change_mask);
1768
1769 return rc;
9de41573
GN		 1770}
1771
62aaa2f0
TY		 1772static int em_popf(struct x86_emulate_ctxt *ctxt)
1773{
9dac77fa
AK		 1774 ctxt->dst.type = OP_REG;
1775 ctxt->dst.addr.reg = &ctxt->eflags;
1776 ctxt->dst.bytes = ctxt->op_bytes;
1777 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1778}
1779
612e89f0
AK		 1780static int em_enter(struct x86_emulate_ctxt *ctxt)
1781{
1782 int rc;
1783 unsigned frame_size = ctxt->src.val;
1784 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1785 ulong rbp;
612e89f0
AK		 1786
1787 if (nesting_level)
1788 return X86EMUL_UNHANDLEABLE;
1789
dd856efa
AK		 1790 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1791 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1792 if (rc != X86EMUL_CONTINUE)
1793 return rc;
dd856efa 1794 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1795 stack_mask(ctxt));
dd856efa
AK		 1796 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1797 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1798 stack_mask(ctxt));
1799 return X86EMUL_CONTINUE;
1800}
1801
f47cfa31
AK		 1802static int em_leave(struct x86_emulate_ctxt *ctxt)
1803{
dd856efa 1804 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1805 stack_mask(ctxt));
dd856efa 1806 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1807}
1808
1cd196ea 1809static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1810{
1cd196ea
AK		 1811 int seg = ctxt->src2.val;
1812
9dac77fa 1813 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1814
4487b3b4 1815 return em_push(ctxt);
7b262e90
GN		 1816}
1817
1cd196ea 1818static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1819{
1cd196ea 1820 int seg = ctxt->src2.val;
dde7e6d1
AK		 1821 unsigned long selector;
1822 int rc;
38ba30ba 1823
9dac77fa 1824 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1825 if (rc != X86EMUL_CONTINUE)
1826 return rc;
1827
7b105ca2 1828 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1829 return rc;
38ba30ba
GN		 1830}
1831
b96a7fad 1832static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1833{
dd856efa 1834 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1835 int rc = X86EMUL_CONTINUE;
1836 int reg = VCPU_REGS_RAX;
38ba30ba 1837
dde7e6d1
AK		 1838 while (reg <= VCPU_REGS_RDI) {
1839 (reg == VCPU_REGS_RSP) ?
dd856efa 1840 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1841
4487b3b4 1842 rc = em_push(ctxt);
dde7e6d1
AK		 1843 if (rc != X86EMUL_CONTINUE)
1844 return rc;
38ba30ba 1845
dde7e6d1 1846 ++reg;
38ba30ba 1847 }
38ba30ba 1848
dde7e6d1 1849 return rc;
38ba30ba
GN		 1850}
1851
62aaa2f0
TY		 1852static int em_pushf(struct x86_emulate_ctxt *ctxt)
1853{
9dac77fa 1854 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1855 return em_push(ctxt);
1856}
1857
b96a7fad 1858static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1859{
dde7e6d1
AK		 1860 int rc = X86EMUL_CONTINUE;
1861 int reg = VCPU_REGS_RDI;
38ba30ba 1862
dde7e6d1
AK		 1863 while (reg >= VCPU_REGS_RAX) {
1864 if (reg == VCPU_REGS_RSP) {
5ad105e5 1865 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1866 --reg;
1867 }
38ba30ba 1868
dd856efa 1869 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1870 if (rc != X86EMUL_CONTINUE)
1871 break;
1872 --reg;
38ba30ba 1873 }
dde7e6d1 1874 return rc;
38ba30ba
GN		 1875}
1876
dd856efa 1877static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1878{
0225fb50 1879 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1880 int rc;
6e154e56
MG		 1881 struct desc_ptr dt;
1882 gva_t cs_addr;
1883 gva_t eip_addr;
1884 u16 cs, eip;
6e154e56
MG		 1885
1886 /* TODO: Add limit checks */
9dac77fa 1887 ctxt->src.val = ctxt->eflags;
4487b3b4 1888 rc = em_push(ctxt);
5c56e1cf
AK		 1889 if (rc != X86EMUL_CONTINUE)
1890 return rc;
6e154e56
MG		 1891
1892 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1893
9dac77fa 1894 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1895 rc = em_push(ctxt);
5c56e1cf
AK		 1896 if (rc != X86EMUL_CONTINUE)
1897 return rc;
6e154e56 1898
9dac77fa 1899 ctxt->src.val = ctxt->_eip;
4487b3b4 1900 rc = em_push(ctxt);
5c56e1cf
AK		 1901 if (rc != X86EMUL_CONTINUE)
1902 return rc;
1903
4bff1e86 1904 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1905
1906 eip_addr = dt.address + (irq << 2);
1907 cs_addr = dt.address + (irq << 2) + 2;
1908
0f65dd70 1909 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
0f65dd70 1913 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1914 if (rc != X86EMUL_CONTINUE)
1915 return rc;
1916
7b105ca2 1917 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1918 if (rc != X86EMUL_CONTINUE)
1919 return rc;
1920
9dac77fa 1921 ctxt->_eip = eip;
6e154e56
MG		 1922
1923 return rc;
1924}
1925
dd856efa
AK		 1926int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1927{
1928 int rc;
1929
1930 invalidate_registers(ctxt);
1931 rc = __emulate_int_real(ctxt, irq);
1932 if (rc == X86EMUL_CONTINUE)
1933 writeback_registers(ctxt);
1934 return rc;
1935}
1936
7b105ca2 1937static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1938{
1939 switch(ctxt->mode) {
1940 case X86EMUL_MODE_REAL:
dd856efa 1941 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1942 case X86EMUL_MODE_VM86:
1943 case X86EMUL_MODE_PROT16:
1944 case X86EMUL_MODE_PROT32:
1945 case X86EMUL_MODE_PROT64:
1946 default:
1947 /* Protected mode interrupts unimplemented yet */
1948 return X86EMUL_UNHANDLEABLE;
1949 }
1950}
1951
7b105ca2 1952static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1953{
dde7e6d1
AK		 1954 int rc = X86EMUL_CONTINUE;
1955 unsigned long temp_eip = 0;
1956 unsigned long temp_eflags = 0;
1957 unsigned long cs = 0;
1958 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1959 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1960 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1961 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1962
dde7e6d1 1963 /* TODO: Add stack limit check */
38ba30ba 1964
9dac77fa 1965 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1966
dde7e6d1
AK		 1967 if (rc != X86EMUL_CONTINUE)
1968 return rc;
38ba30ba 1969
35d3d4a1
AK		 1970 if (temp_eip & ~0xffff)
1971 return emulate_gp(ctxt, 0);
38ba30ba 1972
9dac77fa 1973 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1974
dde7e6d1
AK		 1975 if (rc != X86EMUL_CONTINUE)
1976 return rc;
38ba30ba 1977
9dac77fa 1978 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1979
dde7e6d1
AK		 1980 if (rc != X86EMUL_CONTINUE)
1981 return rc;
38ba30ba 1982
7b105ca2 1983 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1984
dde7e6d1
AK		 1985 if (rc != X86EMUL_CONTINUE)
1986 return rc;
38ba30ba 1987
9dac77fa 1988 ctxt->_eip = temp_eip;
38ba30ba 1989
38ba30ba 1990
9dac77fa 1991 if (ctxt->op_bytes == 4)
dde7e6d1 1992 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1993 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1994 ctxt->eflags &= ~0xffff;
1995 ctxt->eflags |= temp_eflags;
38ba30ba 1996 }
dde7e6d1
AK		 1997
1998 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1999 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2000
2001 return rc;
38ba30ba
GN		 2002}
2003
e01991e7 2004static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2005{
dde7e6d1
AK		 2006 switch(ctxt->mode) {
2007 case X86EMUL_MODE_REAL:
7b105ca2 2008 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2009 case X86EMUL_MODE_VM86:
2010 case X86EMUL_MODE_PROT16:
2011 case X86EMUL_MODE_PROT32:
2012 case X86EMUL_MODE_PROT64:
c37eda13 2013 default:
dde7e6d1
AK		 2014 /* iret from protected mode unimplemented yet */
2015 return X86EMUL_UNHANDLEABLE;
c37eda13 2016 }
c37eda13
WY		 2017}
2018
d2f62766
TY		 2019static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2020{
d2f62766
TY		 2021 int rc;
2022 unsigned short sel;
2023
9dac77fa 2024 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2025
7b105ca2 2026 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 2027 if (rc != X86EMUL_CONTINUE)
2028 return rc;
2029
9dac77fa
AK		 2030 ctxt->_eip = 0;
2031 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 2032 return X86EMUL_CONTINUE;
2033}
2034
51187683 2035static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2036{
9dac77fa 2037 switch (ctxt->modrm_reg) {
8cdbd2c9 2038 case 0: /* rol */
a31b9cea 2039 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 2040 break;
2041 case 1: /* ror */
a31b9cea 2042 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 2043 break;
2044 case 2: /* rcl */
a31b9cea 2045 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 2046 break;
2047 case 3: /* rcr */
a31b9cea 2048 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 2049 break;
2050 case 4: /* sal/shl */
2051 case 6: /* sal/shl */
a31b9cea 2052 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 2053 break;
2054 case 5: /* shr */
a31b9cea 2055 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 2056 break;
2057 case 7: /* sar */
a31b9cea 2058 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 2059 break;
2060 }
51187683 2061 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2062}
2063
45a1467d
AK		 2064FASTOP1(not);
2065FASTOP1(neg);
3329ece1
AK		 2066
2067static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
2068{
2069 u8 ex = 0;
2070
2071 emulate_1op_rax_rdx(ctxt, "mul", ex);
2072 return X86EMUL_CONTINUE;
2073}
2074
2075static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
2076{
2077 u8 ex = 0;
2078
2079 emulate_1op_rax_rdx(ctxt, "imul", ex);
2080 return X86EMUL_CONTINUE;
2081}
2082
2083static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2084{
34d1f490 2085 u8 de = 0;
8cdbd2c9 2086
3329ece1
AK		 2087 emulate_1op_rax_rdx(ctxt, "div", de);
2088 if (de)
2089 return emulate_de(ctxt);
2090 return X86EMUL_CONTINUE;
2091}
2092
2093static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
2094{
2095 u8 de = 0;
2096
2097 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 2098 if (de)
2099 return emulate_de(ctxt);
8c5eee30 2100 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2101}
2102
51187683 2103static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2104{
4179bb02 2105 int rc = X86EMUL_CONTINUE;
8cdbd2c9 2106
9dac77fa 2107 switch (ctxt->modrm_reg) {
8cdbd2c9 2108 case 0: /* inc */
d1eef45d 2109 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 2110 break;
2111 case 1: /* dec */
d1eef45d 2112 emulate_1op(ctxt, "dec");
8cdbd2c9 2113 break;
d19292e4
MG		 2114 case 2: /* call near abs */ {
2115 long int old_eip;
9dac77fa
AK		 2116 old_eip = ctxt->_eip;
2117 ctxt->_eip = ctxt->src.val;
2118 ctxt->src.val = old_eip;
4487b3b4 2119 rc = em_push(ctxt);
d19292e4
MG		 2120 break;
2121 }
8cdbd2c9 2122 case 4: /* jmp abs */
9dac77fa 2123 ctxt->_eip = ctxt->src.val;
8cdbd2c9 2124 break;
d2f62766
TY		 2125 case 5: /* jmp far */
2126 rc = em_jmp_far(ctxt);
2127 break;
8cdbd2c9 2128 case 6: /* push */
4487b3b4 2129 rc = em_push(ctxt);
8cdbd2c9 2130 break;
8cdbd2c9 2131 }
4179bb02 2132 return rc;
8cdbd2c9
LV		 2133}
2134
e0dac408 2135static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2136{
9dac77fa 2137 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2138
dd856efa
AK		 2139 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2140 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2141 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2142 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2143 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2144 } else {
dd856efa
AK		 2145 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2146 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2147
05f086f8 2148 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2149 }
1b30eaa8 2150 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2151}
2152
ebda02c2
TY		 2153static int em_ret(struct x86_emulate_ctxt *ctxt)
2154{
9dac77fa
AK		 2155 ctxt->dst.type = OP_REG;
2156 ctxt->dst.addr.reg = &ctxt->_eip;
2157 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2158 return em_pop(ctxt);
2159}
2160
e01991e7 2161static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2162{
a77ab5ea
AK		 2163 int rc;
2164 unsigned long cs;
2165
9dac77fa 2166 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2167 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2168 return rc;
9dac77fa
AK		 2169 if (ctxt->op_bytes == 4)
2170 ctxt->_eip = (u32)ctxt->_eip;
2171 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2172 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2173 return rc;
7b105ca2 2174 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2175 return rc;
2176}
2177
e940b5c2
TY		 2178static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2179{
2180 /* Save real source value, then compare EAX against destination. */
2181 ctxt->src.orig_val = ctxt->src.val;
dd856efa 2182 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2183 emulate_2op_SrcV(ctxt, "cmp");
2184
2185 if (ctxt->eflags & EFLG_ZF) {
2186 /* Success: write back to memory. */
2187 ctxt->dst.val = ctxt->src.orig_val;
2188 } else {
2189 /* Failure: write the value we saw to EAX. */
2190 ctxt->dst.type = OP_REG;
dd856efa 2191 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
e940b5c2
TY		 2192 }
2193 return X86EMUL_CONTINUE;
2194}
2195
d4b4325f 2196static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2197{
d4b4325f 2198 int seg = ctxt->src2.val;
09b5f4d3
WY		 2199 unsigned short sel;
2200 int rc;
2201
9dac77fa 2202 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2203
7b105ca2 2204 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2205 if (rc != X86EMUL_CONTINUE)
2206 return rc;
2207
9dac77fa 2208 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2209 return rc;
2210}
2211
7b105ca2 2212static void
e66bb2cc 2213setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2214 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2215{
e66bb2cc 2216 cs->l = 0; /* will be adjusted later */
79168fd1 2217 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2218 cs->g = 1; /* 4kb granularity */
79168fd1 2219 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2220 cs->type = 0x0b; /* Read, Execute, Accessed */
2221 cs->s = 1;
2222 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2223 cs->p = 1;
2224 cs->d = 1;
99245b50 2225 cs->avl = 0;
e66bb2cc 2226
79168fd1
GN		 2227 set_desc_base(ss, 0); /* flat segment */
2228 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2229 ss->g = 1; /* 4kb granularity */
2230 ss->s = 1;
2231 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2232 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2233 ss->dpl = 0;
79168fd1 2234 ss->p = 1;
99245b50
GN		 2235 ss->l = 0;
2236 ss->avl = 0;
e66bb2cc
AP		 2237}
2238
1a18a69b
AK		 2239static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2240{
2241 u32 eax, ebx, ecx, edx;
2242
2243 eax = ecx = 0;
0017f93a
AK		 2244 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2245 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2246 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2247 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2248}
2249
c2226fc9
SB		 2250static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2251{
0225fb50 2252 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2253 u32 eax, ebx, ecx, edx;
2254
2255 /*
2256 * syscall should always be enabled in longmode - so only become
2257 * vendor specific (cpuid) if other modes are active...
2258 */
2259 if (ctxt->mode == X86EMUL_MODE_PROT64)
2260 return true;
2261
2262 eax = 0x00000000;
2263 ecx = 0x00000000;
0017f93a
AK		 2264 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2265 /*
2266 * Intel ("GenuineIntel")
2267 * remark: Intel CPUs only support "syscall" in 64bit
2268 * longmode. Also an 64bit guest with a
2269 * 32bit compat-app running will #UD !! While this
2270 * behaviour can be fixed (by emulating) into AMD
2271 * response - CPUs of AMD can't behave like Intel.
2272 */
2273 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2274 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2275 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2276 return false;
2277
2278 /* AMD ("AuthenticAMD") */
2279 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2280 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2281 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2282 return true;
2283
2284 /* AMD ("AMDisbetter!") */
2285 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2286 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2287 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2288 return true;
c2226fc9
SB		 2289
2290 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2291 return false;
2292}
2293
e01991e7 2294static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2295{
0225fb50 2296 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2297 struct desc_struct cs, ss;
e66bb2cc 2298 u64 msr_data;
79168fd1 2299 u16 cs_sel, ss_sel;
c2ad2bb3 2300 u64 efer = 0;
e66bb2cc
AP		 2301
2302 /* syscall is not available in real mode */
2e901c4c 2303 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2304 ctxt->mode == X86EMUL_MODE_VM86)
2305 return emulate_ud(ctxt);
e66bb2cc 2306
c2226fc9
SB		 2307 if (!(em_syscall_is_enabled(ctxt)))
2308 return emulate_ud(ctxt);
2309
c2ad2bb3 2310 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2311 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2312
c2226fc9
SB		 2313 if (!(efer & EFER_SCE))
2314 return emulate_ud(ctxt);
2315
717746e3 2316 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2317 msr_data >>= 32;
79168fd1
GN		 2318 cs_sel = (u16)(msr_data & 0xfffc);
2319 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2320
c2ad2bb3 2321 if (efer & EFER_LMA) {
79168fd1 2322 cs.d = 0;
e66bb2cc
AP		 2323 cs.l = 1;
2324 }
1aa36616
AK		 2325 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2326 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2327
dd856efa 2328 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2329 if (efer & EFER_LMA) {
e66bb2cc 2330#ifdef CONFIG_X86_64
dd856efa 2331 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2332
717746e3 2333 ops->get_msr(ctxt,
3fb1b5db
GN		 2334 ctxt->mode == X86EMUL_MODE_PROT64 ?
2335 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2336 ctxt->_eip = msr_data;
e66bb2cc 2337
717746e3 2338 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2339 ctxt->eflags &= ~(msr_data | EFLG_RF);
2340#endif
2341 } else {
2342 /* legacy mode */
717746e3 2343 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2344 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2345
2346 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2347 }
2348
e54cfa97 2349 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2350}
2351
e01991e7 2352static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2353{
0225fb50 2354 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2355 struct desc_struct cs, ss;
8c604352 2356 u64 msr_data;
79168fd1 2357 u16 cs_sel, ss_sel;
c2ad2bb3 2358 u64 efer = 0;
8c604352 2359
7b105ca2 2360 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2361 /* inject #GP if in real mode */
35d3d4a1
AK		 2362 if (ctxt->mode == X86EMUL_MODE_REAL)
2363 return emulate_gp(ctxt, 0);
8c604352 2364
1a18a69b
AK		 2365 /*
2366 * Not recognized on AMD in compat mode (but is recognized in legacy
2367 * mode).
2368 */
2369 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2370 && !vendor_intel(ctxt))
2371 return emulate_ud(ctxt);
2372
8c604352
AP		 2373 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2374 * Therefore, we inject an #UD.
2375 */
35d3d4a1
AK		 2376 if (ctxt->mode == X86EMUL_MODE_PROT64)
2377 return emulate_ud(ctxt);
8c604352 2378
7b105ca2 2379 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2380
717746e3 2381 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2382 switch (ctxt->mode) {
2383 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2384 if ((msr_data & 0xfffc) == 0x0)
2385 return emulate_gp(ctxt, 0);
8c604352
AP		 2386 break;
2387 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2388 if (msr_data == 0x0)
2389 return emulate_gp(ctxt, 0);
8c604352 2390 break;
9d1b39a9
GN		 2391 default:
2392 break;
8c604352
AP		 2393 }
2394
2395 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2396 cs_sel = (u16)msr_data;
2397 cs_sel &= ~SELECTOR_RPL_MASK;
2398 ss_sel = cs_sel + 8;
2399 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2400 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2401 cs.d = 0;
8c604352
AP		 2402 cs.l = 1;
2403 }
2404
1aa36616
AK		 2405 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2406 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2407
717746e3 2408 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2409 ctxt->_eip = msr_data;
8c604352 2410
717746e3 2411 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2412 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2413
e54cfa97 2414 return X86EMUL_CONTINUE;
8c604352
AP		 2415}
2416
e01991e7 2417static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2418{
0225fb50 2419 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2420 struct desc_struct cs, ss;
4668f050
AP		 2421 u64 msr_data;
2422 int usermode;
1249b96e 2423 u16 cs_sel = 0, ss_sel = 0;
4668f050 2424
a0044755
GN		 2425 /* inject #GP if in real mode or Virtual 8086 mode */
2426 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2427 ctxt->mode == X86EMUL_MODE_VM86)
2428 return emulate_gp(ctxt, 0);
4668f050 2429
7b105ca2 2430 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2431
9dac77fa 2432 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2433 usermode = X86EMUL_MODE_PROT64;
2434 else
2435 usermode = X86EMUL_MODE_PROT32;
2436
2437 cs.dpl = 3;
2438 ss.dpl = 3;
717746e3 2439 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2440 switch (usermode) {
2441 case X86EMUL_MODE_PROT32:
79168fd1 2442 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2443 if ((msr_data & 0xfffc) == 0x0)
2444 return emulate_gp(ctxt, 0);
79168fd1 2445 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2446 break;
2447 case X86EMUL_MODE_PROT64:
79168fd1 2448 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2449 if (msr_data == 0x0)
2450 return emulate_gp(ctxt, 0);
79168fd1
GN		 2451 ss_sel = cs_sel + 8;
2452 cs.d = 0;
4668f050
AP		 2453 cs.l = 1;
2454 break;
2455 }
79168fd1
GN		 2456 cs_sel |= SELECTOR_RPL_MASK;
2457 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2458
1aa36616
AK		 2459 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2460 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2461
dd856efa
AK		 2462 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2463 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2464
e54cfa97 2465 return X86EMUL_CONTINUE;
4668f050
AP		 2466}
2467
7b105ca2 2468static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2469{
2470 int iopl;
2471 if (ctxt->mode == X86EMUL_MODE_REAL)
2472 return false;
2473 if (ctxt->mode == X86EMUL_MODE_VM86)
2474 return true;
2475 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2476 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2477}
2478
2479static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2480 u16 port, u16 len)
2481{
0225fb50 2482 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2483 struct desc_struct tr_seg;
5601d05b 2484 u32 base3;
f850e2e6 2485 int r;
1aa36616 2486 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2487 unsigned mask = (1 << len) - 1;
5601d05b 2488 unsigned long base;
f850e2e6 2489
1aa36616 2490 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2491 if (!tr_seg.p)
f850e2e6 2492 return false;
79168fd1 2493 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2494 return false;
5601d05b
GN		 2495 base = get_desc_base(&tr_seg);
2496#ifdef CONFIG_X86_64
2497 base |= ((u64)base3) << 32;
2498#endif
0f65dd70 2499 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2500 if (r != X86EMUL_CONTINUE)
2501 return false;
79168fd1 2502 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2503 return false;
0f65dd70 2504 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2505 if (r != X86EMUL_CONTINUE)
2506 return false;
2507 if ((perm >> bit_idx) & mask)
2508 return false;
2509 return true;
2510}
2511
2512static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2513 u16 port, u16 len)
2514{
4fc40f07
GN		 2515 if (ctxt->perm_ok)
2516 return true;
2517
7b105ca2
TY		 2518 if (emulator_bad_iopl(ctxt))
2519 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2520 return false;
4fc40f07
GN		 2521
2522 ctxt->perm_ok = true;
2523
f850e2e6
GN		 2524 return true;
2525}
2526
38ba30ba 2527static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2528 struct tss_segment_16 *tss)
2529{
9dac77fa 2530 tss->ip = ctxt->_eip;
38ba30ba 2531 tss->flag = ctxt->eflags;
dd856efa
AK		 2532 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2533 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2534 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2535 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2536 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2537 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2538 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2539 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2540
1aa36616
AK		 2541 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2542 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2543 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2544 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2545 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2546}
2547
2548static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2549 struct tss_segment_16 *tss)
2550{
38ba30ba
GN		 2551 int ret;
2552
9dac77fa 2553 ctxt->_eip = tss->ip;
38ba30ba 2554 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2555 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2556 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2557 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2558 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2559 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2560 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2561 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2562 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2563
2564 /*
2565 * SDM says that segment selectors are loaded before segment
2566 * descriptors
2567 */
1aa36616
AK		 2568 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2569 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2570 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2571 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2572 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2573
2574 /*
fc058680 2575 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2576 * it is handled in a context of new task
2577 */
7b105ca2 2578 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2579 if (ret != X86EMUL_CONTINUE)
2580 return ret;
7b105ca2 2581 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2582 if (ret != X86EMUL_CONTINUE)
2583 return ret;
7b105ca2 2584 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2585 if (ret != X86EMUL_CONTINUE)
2586 return ret;
7b105ca2 2587 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2588 if (ret != X86EMUL_CONTINUE)
2589 return ret;
7b105ca2 2590 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2591 if (ret != X86EMUL_CONTINUE)
2592 return ret;
2593
2594 return X86EMUL_CONTINUE;
2595}
2596
2597static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2598 u16 tss_selector, u16 old_tss_sel,
2599 ulong old_tss_base, struct desc_struct *new_desc)
2600{
0225fb50 2601 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2602 struct tss_segment_16 tss_seg;
2603 int ret;
bcc55cba 2604 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2605
0f65dd70 2606 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2607 &ctxt->exception);
db297e3d 2608 if (ret != X86EMUL_CONTINUE)
38ba30ba 2609 /* FIXME: need to provide precise fault address */
38ba30ba 2610 return ret;
38ba30ba 2611
7b105ca2 2612 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2613
0f65dd70 2614 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2615 &ctxt->exception);
db297e3d 2616 if (ret != X86EMUL_CONTINUE)
38ba30ba 2617 /* FIXME: need to provide precise fault address */
38ba30ba 2618 return ret;
38ba30ba 2619
0f65dd70 2620 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2621 &ctxt->exception);
db297e3d 2622 if (ret != X86EMUL_CONTINUE)
38ba30ba 2623 /* FIXME: need to provide precise fault address */
38ba30ba 2624 return ret;
38ba30ba
GN		 2625
2626 if (old_tss_sel != 0xffff) {
2627 tss_seg.prev_task_link = old_tss_sel;
2628
0f65dd70 2629 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2630 &tss_seg.prev_task_link,
2631 sizeof tss_seg.prev_task_link,
0f65dd70 2632 &ctxt->exception);
db297e3d 2633 if (ret != X86EMUL_CONTINUE)
38ba30ba 2634 /* FIXME: need to provide precise fault address */
38ba30ba 2635 return ret;
38ba30ba
GN		 2636 }
2637
7b105ca2 2638 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2639}
2640
2641static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2642 struct tss_segment_32 *tss)
2643{
7b105ca2 2644 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2645 tss->eip = ctxt->_eip;
38ba30ba 2646 tss->eflags = ctxt->eflags;
dd856efa
AK		 2647 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2648 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2649 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2650 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2651 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2652 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2653 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2654 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2655
1aa36616
AK		 2656 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2657 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2658 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2659 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2660 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2661 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2662 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2663}
2664
2665static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2666 struct tss_segment_32 *tss)
2667{
38ba30ba
GN		 2668 int ret;
2669
7b105ca2 2670 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2671 return emulate_gp(ctxt, 0);
9dac77fa 2672 ctxt->_eip = tss->eip;
38ba30ba 2673 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2674
2675 /* General purpose registers */
dd856efa
AK		 2676 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2677 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2678 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2679 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2680 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2681 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2682 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2683 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2684
2685 /*
2686 * SDM says that segment selectors are loaded before segment
2687 * descriptors
2688 */
1aa36616
AK		 2689 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2690 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2691 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2692 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2693 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2694 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2695 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2696
4cee4798
KW		 2697 /*
2698 * If we're switching between Protected Mode and VM86, we need to make
2699 * sure to update the mode before loading the segment descriptors so
2700 * that the selectors are interpreted correctly.
2701 *
2702 * Need to get rflags to the vcpu struct immediately because it
2703 * influences the CPL which is checked at least when loading the segment
2704 * descriptors and when pushing an error code to the new kernel stack.
2705 *
2706 * TODO Introduce a separate ctxt->ops->set_cpl callback
2707 */
2708 if (ctxt->eflags & X86_EFLAGS_VM)
2709 ctxt->mode = X86EMUL_MODE_VM86;
2710 else
2711 ctxt->mode = X86EMUL_MODE_PROT32;
2712
2713 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2714
38ba30ba
GN		 2715 /*
2716 * Now load segment descriptors. If fault happenes at this stage
2717 * it is handled in a context of new task
2718 */
7b105ca2 2719 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2720 if (ret != X86EMUL_CONTINUE)
2721 return ret;
7b105ca2 2722 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2723 if (ret != X86EMUL_CONTINUE)
2724 return ret;
7b105ca2 2725 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
7b105ca2 2728 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2729 if (ret != X86EMUL_CONTINUE)
2730 return ret;
7b105ca2 2731 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2732 if (ret != X86EMUL_CONTINUE)
2733 return ret;
7b105ca2 2734 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2735 if (ret != X86EMUL_CONTINUE)
2736 return ret;
7b105ca2 2737 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2738 if (ret != X86EMUL_CONTINUE)
2739 return ret;
2740
2741 return X86EMUL_CONTINUE;
2742}
2743
2744static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2745 u16 tss_selector, u16 old_tss_sel,
2746 ulong old_tss_base, struct desc_struct *new_desc)
2747{
0225fb50 2748 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2749 struct tss_segment_32 tss_seg;
2750 int ret;
bcc55cba 2751 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2752
0f65dd70 2753 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2754 &ctxt->exception);
db297e3d 2755 if (ret != X86EMUL_CONTINUE)
38ba30ba 2756 /* FIXME: need to provide precise fault address */
38ba30ba 2757 return ret;
38ba30ba 2758
7b105ca2 2759 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2760
0f65dd70 2761 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2762 &ctxt->exception);
db297e3d 2763 if (ret != X86EMUL_CONTINUE)
38ba30ba 2764 /* FIXME: need to provide precise fault address */
38ba30ba 2765 return ret;
38ba30ba 2766
0f65dd70 2767 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2768 &ctxt->exception);
db297e3d 2769 if (ret != X86EMUL_CONTINUE)
38ba30ba 2770 /* FIXME: need to provide precise fault address */
38ba30ba 2771 return ret;
38ba30ba
GN		 2772
2773 if (old_tss_sel != 0xffff) {
2774 tss_seg.prev_task_link = old_tss_sel;
2775
0f65dd70 2776 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2777 &tss_seg.prev_task_link,
2778 sizeof tss_seg.prev_task_link,
0f65dd70 2779 &ctxt->exception);
db297e3d 2780 if (ret != X86EMUL_CONTINUE)
38ba30ba 2781 /* FIXME: need to provide precise fault address */
38ba30ba 2782 return ret;
38ba30ba
GN		 2783 }
2784
7b105ca2 2785 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2786}
2787
2788static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2789 u16 tss_selector, int idt_index, int reason,
e269fb21 2790 bool has_error_code, u32 error_code)
38ba30ba 2791{
0225fb50 2792 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2793 struct desc_struct curr_tss_desc, next_tss_desc;
2794 int ret;
1aa36616 2795 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2796 ulong old_tss_base =
4bff1e86 2797 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2798 u32 desc_limit;
e919464b 2799 ulong desc_addr;
38ba30ba
GN		 2800
2801 /* FIXME: old_tss_base == ~0 ? */
2802
e919464b 2803 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2804 if (ret != X86EMUL_CONTINUE)
2805 return ret;
e919464b 2806 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2807 if (ret != X86EMUL_CONTINUE)
2808 return ret;
2809
2810 /* FIXME: check that next_tss_desc is tss */
2811
7f3d35fd
KW		 2812 /*
2813 * Check privileges. The three cases are task switch caused by...
2814 *
2815 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2816 * 2. Exception/IRQ/iret: No check is performed
fc058680 2817 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2818 */
2819 if (reason == TASK_SWITCH_GATE) {
2820 if (idt_index != -1) {
2821 /* Software interrupts */
2822 struct desc_struct task_gate_desc;
2823 int dpl;
2824
2825 ret = read_interrupt_descriptor(ctxt, idt_index,
2826 &task_gate_desc);
2827 if (ret != X86EMUL_CONTINUE)
2828 return ret;
2829
2830 dpl = task_gate_desc.dpl;
2831 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2832 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2833 }
2834 } else if (reason != TASK_SWITCH_IRET) {
2835 int dpl = next_tss_desc.dpl;
2836 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2837 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2838 }
2839
7f3d35fd 2840
ceffb459
GN		 2841 desc_limit = desc_limit_scaled(&next_tss_desc);
2842 if (!next_tss_desc.p ||
2843 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2844 desc_limit < 0x2b)) {
54b8486f 2845 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2846 return X86EMUL_PROPAGATE_FAULT;
2847 }
2848
2849 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2850 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2851 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2852 }
2853
2854 if (reason == TASK_SWITCH_IRET)
2855 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2856
2857 /* set back link to prev task only if NT bit is set in eflags
fc058680 2858 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2859 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2860 old_tss_sel = 0xffff;
2861
2862 if (next_tss_desc.type & 8)
7b105ca2 2863 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2864 old_tss_base, &next_tss_desc);
2865 else
7b105ca2 2866 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2867 old_tss_base, &next_tss_desc);
0760d448
JK		 2868 if (ret != X86EMUL_CONTINUE)
2869 return ret;
38ba30ba
GN		 2870
2871 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2872 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2873
2874 if (reason != TASK_SWITCH_IRET) {
2875 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2876 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2877 }
2878
717746e3 2879 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2880 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2881
e269fb21 2882 if (has_error_code) {
9dac77fa
AK		 2883 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2884 ctxt->lock_prefix = 0;
2885 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2886 ret = em_push(ctxt);
e269fb21
JK		 2887 }
2888
38ba30ba
GN		 2889 return ret;
2890}
2891
2892int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2893 u16 tss_selector, int idt_index, int reason,
e269fb21 2894 bool has_error_code, u32 error_code)
38ba30ba 2895{
38ba30ba
GN		 2896 int rc;
2897
dd856efa 2898 invalidate_registers(ctxt);
9dac77fa
AK		 2899 ctxt->_eip = ctxt->eip;
2900 ctxt->dst.type = OP_NONE;
38ba30ba 2901
7f3d35fd 2902 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2903 has_error_code, error_code);
38ba30ba 2904
dd856efa 2905 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2906 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2907 writeback_registers(ctxt);
2908 }
38ba30ba 2909
a0c0ab2f 2910 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2911}
2912
f3bd64c6
GN		 2913static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2914 struct operand *op)
a682e354 2915{
b3356bf0 2916 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2917
dd856efa
AK		 2918 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2919 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2920}
2921
7af04fc0
AK		 2922static int em_das(struct x86_emulate_ctxt *ctxt)
2923{
7af04fc0
AK		 2924 u8 al, old_al;
2925 bool af, cf, old_cf;
2926
2927 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2928 al = ctxt->dst.val;
7af04fc0
AK		 2929
2930 old_al = al;
2931 old_cf = cf;
2932 cf = false;
2933 af = ctxt->eflags & X86_EFLAGS_AF;
2934 if ((al & 0x0f) > 9 || af) {
2935 al -= 6;
2936 cf = old_cf | (al >= 250);
2937 af = true;
2938 } else {
2939 af = false;
2940 }
2941 if (old_al > 0x99 || old_cf) {
2942 al -= 0x60;
2943 cf = true;
2944 }
2945
9dac77fa 2946 ctxt->dst.val = al;
7af04fc0 2947 /* Set PF, ZF, SF */
9dac77fa
AK		 2948 ctxt->src.type = OP_IMM;
2949 ctxt->src.val = 0;
2950 ctxt->src.bytes = 1;
a31b9cea 2951 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2952 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2953 if (cf)
2954 ctxt->eflags |= X86_EFLAGS_CF;
2955 if (af)
2956 ctxt->eflags |= X86_EFLAGS_AF;
2957 return X86EMUL_CONTINUE;
2958}
2959
7f662273
GN		 2960static int em_aad(struct x86_emulate_ctxt *ctxt)
2961{
2962 u8 al = ctxt->dst.val & 0xff;
2963 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2964
2965 al = (al + (ah * ctxt->src.val)) & 0xff;
2966
2967 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2968
2969 ctxt->eflags &= ~(X86_EFLAGS_PF | X86_EFLAGS_SF | X86_EFLAGS_ZF);
2970
2971 if (!al)
2972 ctxt->eflags |= X86_EFLAGS_ZF;
2973 if (!(al & 1))
2974 ctxt->eflags |= X86_EFLAGS_PF;
2975 if (al & 0x80)
2976 ctxt->eflags |= X86_EFLAGS_SF;
2977
2978 return X86EMUL_CONTINUE;
2979}
2980
d4ddafcd
TY		 2981static int em_call(struct x86_emulate_ctxt *ctxt)
2982{
2983 long rel = ctxt->src.val;
2984
2985 ctxt->src.val = (unsigned long)ctxt->_eip;
2986 jmp_rel(ctxt, rel);
2987 return em_push(ctxt);
2988}
2989
0ef753b8
AK		 2990static int em_call_far(struct x86_emulate_ctxt *ctxt)
2991{
0ef753b8
AK		 2992 u16 sel, old_cs;
2993 ulong old_eip;
2994 int rc;
2995
1aa36616 2996 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2997 old_eip = ctxt->_eip;
0ef753b8 2998
9dac77fa 2999 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 3000 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 3001 return X86EMUL_CONTINUE;
3002
9dac77fa
AK		 3003 ctxt->_eip = 0;
3004 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 3005
9dac77fa 3006 ctxt->src.val = old_cs;
4487b3b4 3007 rc = em_push(ctxt);
0ef753b8
AK		 3008 if (rc != X86EMUL_CONTINUE)
3009 return rc;
3010
9dac77fa 3011 ctxt->src.val = old_eip;
4487b3b4 3012 return em_push(ctxt);
0ef753b8
AK		 3013}
3014
40ece7c7
AK		 3015static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3016{
40ece7c7
AK		 3017 int rc;
3018
9dac77fa
AK		 3019 ctxt->dst.type = OP_REG;
3020 ctxt->dst.addr.reg = &ctxt->_eip;
3021 ctxt->dst.bytes = ctxt->op_bytes;
3022 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 3023 if (rc != X86EMUL_CONTINUE)
3024 return rc;
5ad105e5 3025 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3026 return X86EMUL_CONTINUE;
3027}
3028
fb864fbc
AK		 3029FASTOP2(add);
3030FASTOP2(or);
3031FASTOP2(adc);
3032FASTOP2(sbb);
3033FASTOP2(and);
3034FASTOP2(sub);
3035FASTOP2(xor);
3036FASTOP2(cmp);
3037FASTOP2(test);
9f21ca59 3038
e4f973ae
TY		 3039static int em_xchg(struct x86_emulate_ctxt *ctxt)
3040{
e4f973ae 3041 /* Write back the register source. */
9dac77fa
AK		 3042 ctxt->src.val = ctxt->dst.val;
3043 write_register_operand(&ctxt->src);
e4f973ae
TY		 3044
3045 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3046 ctxt->dst.val = ctxt->src.orig_val;
3047 ctxt->lock_prefix = 1;
e4f973ae
TY		 3048 return X86EMUL_CONTINUE;
3049}
3050
5c82aa29 3051static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 3052{
a31b9cea 3053 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 3054 return X86EMUL_CONTINUE;
3055}
3056
5c82aa29
AK		 3057static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3058{
9dac77fa 3059 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 3060 return em_imul(ctxt);
3061}
3062
61429142
AK		 3063static int em_cwd(struct x86_emulate_ctxt *ctxt)
3064{
9dac77fa
AK		 3065 ctxt->dst.type = OP_REG;
3066 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3067 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3068 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3069
3070 return X86EMUL_CONTINUE;
3071}
3072
48bb5d3c
AK		 3073static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3074{
48bb5d3c
AK		 3075 u64 tsc = 0;
3076
717746e3 3077 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3078 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3079 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3080 return X86EMUL_CONTINUE;
3081}
3082
222d21aa
AK		 3083static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3084{
3085 u64 pmc;
3086
dd856efa 3087 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3088 return emulate_gp(ctxt, 0);
dd856efa
AK		 3089 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3090 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3091 return X86EMUL_CONTINUE;
3092}
3093
b9eac5f4
AK		 3094static int em_mov(struct x86_emulate_ctxt *ctxt)
3095{
49597d81 3096 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 3097 return X86EMUL_CONTINUE;
3098}
3099
bc00f8d2
TY		 3100static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3101{
3102 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3103 return emulate_gp(ctxt, 0);
3104
3105 /* Disable writeback. */
3106 ctxt->dst.type = OP_NONE;
3107 return X86EMUL_CONTINUE;
3108}
3109
3110static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3111{
3112 unsigned long val;
3113
3114 if (ctxt->mode == X86EMUL_MODE_PROT64)
3115 val = ctxt->src.val & ~0ULL;
3116 else
3117 val = ctxt->src.val & ~0U;
3118
3119 /* #UD condition is already handled. */
3120 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3121 return emulate_gp(ctxt, 0);
3122
3123 /* Disable writeback. */
3124 ctxt->dst.type = OP_NONE;
3125 return X86EMUL_CONTINUE;
3126}
3127
e1e210b0
TY		 3128static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3129{
3130 u64 msr_data;
3131
dd856efa
AK		 3132 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3133 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3134 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3135 return emulate_gp(ctxt, 0);
3136
3137 return X86EMUL_CONTINUE;
3138}
3139
3140static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3141{
3142 u64 msr_data;
3143
dd856efa 3144 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3145 return emulate_gp(ctxt, 0);
3146
dd856efa
AK		 3147 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3148 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3149 return X86EMUL_CONTINUE;
3150}
3151
1bd5f469
TY		 3152static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3153{
9dac77fa 3154 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3155 return emulate_ud(ctxt);
3156
9dac77fa 3157 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3158 return X86EMUL_CONTINUE;
3159}
3160
3161static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3162{
9dac77fa 3163 u16 sel = ctxt->src.val;
1bd5f469 3164
9dac77fa 3165 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3166 return emulate_ud(ctxt);
3167
9dac77fa 3168 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3169 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3170
3171 /* Disable writeback. */
9dac77fa
AK		 3172 ctxt->dst.type = OP_NONE;
3173 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3174}
3175
a14e579f
AK		 3176static int em_lldt(struct x86_emulate_ctxt *ctxt)
3177{
3178 u16 sel = ctxt->src.val;
3179
3180 /* Disable writeback. */
3181 ctxt->dst.type = OP_NONE;
3182 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3183}
3184
80890006
AK		 3185static int em_ltr(struct x86_emulate_ctxt *ctxt)
3186{
3187 u16 sel = ctxt->src.val;
3188
3189 /* Disable writeback. */
3190 ctxt->dst.type = OP_NONE;
3191 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3192}
3193
38503911
AK		 3194static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3195{
9fa088f4
AK		 3196 int rc;
3197 ulong linear;
3198
9dac77fa 3199 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3200 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3201 ctxt->ops->invlpg(ctxt, linear);
38503911 3202 /* Disable writeback. */
9dac77fa 3203 ctxt->dst.type = OP_NONE;
38503911
AK		 3204 return X86EMUL_CONTINUE;
3205}
3206
2d04a05b
AK		 3207static int em_clts(struct x86_emulate_ctxt *ctxt)
3208{
3209 ulong cr0;
3210
3211 cr0 = ctxt->ops->get_cr(ctxt, 0);
3212 cr0 &= ~X86_CR0_TS;
3213 ctxt->ops->set_cr(ctxt, 0, cr0);
3214 return X86EMUL_CONTINUE;
3215}
3216
26d05cc7
AK		 3217static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3218{
26d05cc7
AK		 3219 int rc;
3220
9dac77fa 3221 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3222 return X86EMUL_UNHANDLEABLE;
3223
3224 rc = ctxt->ops->fix_hypercall(ctxt);
3225 if (rc != X86EMUL_CONTINUE)
3226 return rc;
3227
3228 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3229 ctxt->_eip = ctxt->eip;
26d05cc7 3230 /* Disable writeback. */
9dac77fa 3231 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3232 return X86EMUL_CONTINUE;
3233}
3234
96051572
AK		 3235static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3236 void (*get)(struct x86_emulate_ctxt *ctxt,
3237 struct desc_ptr *ptr))
3238{
3239 struct desc_ptr desc_ptr;
3240
3241 if (ctxt->mode == X86EMUL_MODE_PROT64)
3242 ctxt->op_bytes = 8;
3243 get(ctxt, &desc_ptr);
3244 if (ctxt->op_bytes == 2) {
3245 ctxt->op_bytes = 4;
3246 desc_ptr.address &= 0x00ffffff;
3247 }
3248 /* Disable writeback. */
3249 ctxt->dst.type = OP_NONE;
3250 return segmented_write(ctxt, ctxt->dst.addr.mem,
3251 &desc_ptr, 2 + ctxt->op_bytes);
3252}
3253
3254static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3255{
3256 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3257}
3258
3259static int em_sidt(struct x86_emulate_ctxt *ctxt)
3260{
3261 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3262}
3263
26d05cc7
AK		 3264static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3265{
26d05cc7
AK		 3266 struct desc_ptr desc_ptr;
3267 int rc;
3268
510425ff
AK		 3269 if (ctxt->mode == X86EMUL_MODE_PROT64)
3270 ctxt->op_bytes = 8;
9dac77fa 3271 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3272 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3273 ctxt->op_bytes);
26d05cc7
AK		 3274 if (rc != X86EMUL_CONTINUE)
3275 return rc;
3276 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3277 /* Disable writeback. */
9dac77fa 3278 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3279 return X86EMUL_CONTINUE;
3280}
3281
5ef39c71 3282static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3283{
26d05cc7
AK		 3284 int rc;
3285
5ef39c71
AK		 3286 rc = ctxt->ops->fix_hypercall(ctxt);
3287
26d05cc7 3288 /* Disable writeback. */
9dac77fa 3289 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3290 return rc;
3291}
3292
3293static int em_lidt(struct x86_emulate_ctxt *ctxt)
3294{
26d05cc7
AK		 3295 struct desc_ptr desc_ptr;
3296 int rc;
3297
510425ff
AK		 3298 if (ctxt->mode == X86EMUL_MODE_PROT64)
3299 ctxt->op_bytes = 8;
9dac77fa 3300 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3301 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3302 ctxt->op_bytes);
26d05cc7
AK		 3303 if (rc != X86EMUL_CONTINUE)
3304 return rc;
3305 ctxt->ops->set_idt(ctxt, &desc_ptr);
3306 /* Disable writeback. */
9dac77fa 3307 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3308 return X86EMUL_CONTINUE;
3309}
3310
3311static int em_smsw(struct x86_emulate_ctxt *ctxt)
3312{
9dac77fa
AK		 3313 ctxt->dst.bytes = 2;
3314 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3315 return X86EMUL_CONTINUE;
3316}
3317
3318static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3319{
26d05cc7 3320 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3321 | (ctxt->src.val & 0x0f));
3322 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3323 return X86EMUL_CONTINUE;
3324}
3325
d06e03ad
TY		 3326static int em_loop(struct x86_emulate_ctxt *ctxt)
3327{
dd856efa
AK		 3328 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3329 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3330 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3331 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3332
3333 return X86EMUL_CONTINUE;
3334}
3335
3336static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3337{
dd856efa 3338 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3339 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3340
3341 return X86EMUL_CONTINUE;
3342}
3343
d7841a4b
TY		 3344static int em_in(struct x86_emulate_ctxt *ctxt)
3345{
3346 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3347 &ctxt->dst.val))
3348 return X86EMUL_IO_NEEDED;
3349
3350 return X86EMUL_CONTINUE;
3351}
3352
3353static int em_out(struct x86_emulate_ctxt *ctxt)
3354{
3355 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3356 &ctxt->src.val, 1);
3357 /* Disable writeback. */
3358 ctxt->dst.type = OP_NONE;
3359 return X86EMUL_CONTINUE;
3360}
3361
f411e6cd
TY		 3362static int em_cli(struct x86_emulate_ctxt *ctxt)
3363{
3364 if (emulator_bad_iopl(ctxt))
3365 return emulate_gp(ctxt, 0);
3366
3367 ctxt->eflags &= ~X86_EFLAGS_IF;
3368 return X86EMUL_CONTINUE;
3369}
3370
3371static int em_sti(struct x86_emulate_ctxt *ctxt)
3372{
3373 if (emulator_bad_iopl(ctxt))
3374 return emulate_gp(ctxt, 0);
3375
3376 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3377 ctxt->eflags |= X86_EFLAGS_IF;
3378 return X86EMUL_CONTINUE;
3379}
3380
ce7faab2
TY		 3381static int em_bt(struct x86_emulate_ctxt *ctxt)
3382{
3383 /* Disable writeback. */
3384 ctxt->dst.type = OP_NONE;
3385 /* only subword offset */
3386 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3387
3388 emulate_2op_SrcV_nobyte(ctxt, "bt");
3389 return X86EMUL_CONTINUE;
3390}
3391
3392static int em_bts(struct x86_emulate_ctxt *ctxt)
3393{
3394 emulate_2op_SrcV_nobyte(ctxt, "bts");
3395 return X86EMUL_CONTINUE;
3396}
3397
3398static int em_btr(struct x86_emulate_ctxt *ctxt)
3399{
3400 emulate_2op_SrcV_nobyte(ctxt, "btr");
3401 return X86EMUL_CONTINUE;
3402}
3403
3404static int em_btc(struct x86_emulate_ctxt *ctxt)
3405{
3406 emulate_2op_SrcV_nobyte(ctxt, "btc");
3407 return X86EMUL_CONTINUE;
3408}
3409
ff227392
TY		 3410static int em_bsf(struct x86_emulate_ctxt *ctxt)
3411{
d54e4237 3412 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3413 return X86EMUL_CONTINUE;
3414}
3415
3416static int em_bsr(struct x86_emulate_ctxt *ctxt)
3417{
d54e4237 3418 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3419 return X86EMUL_CONTINUE;
3420}
3421
6d6eede4
AK		 3422static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3423{
3424 u32 eax, ebx, ecx, edx;
3425
dd856efa
AK		 3426 eax = reg_read(ctxt, VCPU_REGS_RAX);
3427 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3428 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3429 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3430 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3431 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3432 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3433 return X86EMUL_CONTINUE;
3434}
3435
2dd7caa0
AK		 3436static int em_lahf(struct x86_emulate_ctxt *ctxt)
3437{
dd856efa
AK		 3438 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3439 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3440 return X86EMUL_CONTINUE;
3441}
3442
9299836e
AK		 3443static int em_bswap(struct x86_emulate_ctxt *ctxt)
3444{
3445 switch (ctxt->op_bytes) {
3446#ifdef CONFIG_X86_64
3447 case 8:
3448 asm("bswap %0" : "+r"(ctxt->dst.val));
3449 break;
3450#endif
3451 default:
3452 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3453 break;
3454 }
3455 return X86EMUL_CONTINUE;
3456}
3457
cfec82cb
JR		 3458static bool valid_cr(int nr)
3459{
3460 switch (nr) {
3461 case 0:
3462 case 2 ... 4:
3463 case 8:
3464 return true;
3465 default:
3466 return false;
3467 }
3468}
3469
3470static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3471{
9dac77fa 3472 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3473 return emulate_ud(ctxt);
3474
3475 return X86EMUL_CONTINUE;
3476}
3477
3478static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3479{
9dac77fa
AK		 3480 u64 new_val = ctxt->src.val64;
3481 int cr = ctxt->modrm_reg;
c2ad2bb3 3482 u64 efer = 0;
cfec82cb
JR		 3483
3484 static u64 cr_reserved_bits[] = {
3485 0xffffffff00000000ULL,
3486 0, 0, 0, /* CR3 checked later */
3487 CR4_RESERVED_BITS,
3488 0, 0, 0,
3489 CR8_RESERVED_BITS,
3490 };
3491
3492 if (!valid_cr(cr))
3493 return emulate_ud(ctxt);
3494
3495 if (new_val & cr_reserved_bits[cr])
3496 return emulate_gp(ctxt, 0);
3497
3498 switch (cr) {
3499 case 0: {
c2ad2bb3 3500 u64 cr4;
cfec82cb
JR		 3501 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3502 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3503 return emulate_gp(ctxt, 0);
3504
717746e3
AK		 3505 cr4 = ctxt->ops->get_cr(ctxt, 4);
3506 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3507
3508 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3509 !(cr4 & X86_CR4_PAE))
3510 return emulate_gp(ctxt, 0);
3511
3512 break;
3513 }
3514 case 3: {
3515 u64 rsvd = 0;
3516
c2ad2bb3
AK		 3517 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3518 if (efer & EFER_LMA)
cfec82cb 3519 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3520 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3521 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3522 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3523 rsvd = CR3_NONPAE_RESERVED_BITS;
3524
3525 if (new_val & rsvd)
3526 return emulate_gp(ctxt, 0);
3527
3528 break;
3529 }
3530 case 4: {
717746e3 3531 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3532
3533 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3534 return emulate_gp(ctxt, 0);
3535
3536 break;
3537 }
3538 }
3539
3540 return X86EMUL_CONTINUE;
3541}
3542
3b88e41a
JR		 3543static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3544{
3545 unsigned long dr7;
3546
717746e3 3547 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3548
3549 /* Check if DR7.Global_Enable is set */
3550 return dr7 & (1 << 13);
3551}
3552
3553static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3554{
9dac77fa 3555 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3556 u64 cr4;
3557
3558 if (dr > 7)
3559 return emulate_ud(ctxt);
3560
717746e3 3561 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3562 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3563 return emulate_ud(ctxt);
3564
3565 if (check_dr7_gd(ctxt))
3566 return emulate_db(ctxt);
3567
3568 return X86EMUL_CONTINUE;
3569}
3570
3571static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3572{
9dac77fa
AK		 3573 u64 new_val = ctxt->src.val64;
3574 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3575
3576 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3577 return emulate_gp(ctxt, 0);
3578
3579 return check_dr_read(ctxt);
3580}
3581
01de8b09
JR		 3582static int check_svme(struct x86_emulate_ctxt *ctxt)
3583{
3584 u64 efer;
3585
717746e3 3586 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3587
3588 if (!(efer & EFER_SVME))
3589 return emulate_ud(ctxt);
3590
3591 return X86EMUL_CONTINUE;
3592}
3593
3594static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3595{
dd856efa 3596 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3597
3598 /* Valid physical address? */
d4224449 3599 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3600 return emulate_gp(ctxt, 0);
3601
3602 return check_svme(ctxt);
3603}
3604
d7eb8203
JR		 3605static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3606{
717746e3 3607 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3608
717746e3 3609 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3610 return emulate_ud(ctxt);
3611
3612 return X86EMUL_CONTINUE;
3613}
3614
8061252e
JR		 3615static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3616{
717746e3 3617 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3618 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3619
717746e3 3620 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3621 (rcx > 3))
3622 return emulate_gp(ctxt, 0);
3623
3624 return X86EMUL_CONTINUE;
3625}
3626
f6511935
JR		 3627static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3628{
9dac77fa
AK		 3629 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3630 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3631 return emulate_gp(ctxt, 0);
3632
3633 return X86EMUL_CONTINUE;
3634}
3635
3636static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3637{
9dac77fa
AK		 3638 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3639 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3640 return emulate_gp(ctxt, 0);
3641
3642 return X86EMUL_CONTINUE;
3643}
3644
73fba5f4 3645#define D(_y) { .flags = (_y) }
c4f035c6 3646#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3647#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3648 .check_perm = (_p) }
73fba5f4 3649#define N D(0)
01de8b09 3650#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3651#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3652#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3653#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3654#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3655#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3656#define II(_f, _e, _i) \
3657 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3658#define IIP(_f, _e, _i, _p) \
3659 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3660 .check_perm = (_p) }
aa97bb48 3661#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3662
8d8f4e9f 3663#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3664#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3665#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3666#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3667#define I2bvIP(_f, _e, _i, _p) \
3668 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3669
fb864fbc
AK		 3670#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3671 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3672 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3673
fd0a0d82 3674static const struct opcode group7_rm1[] = {
1c2545be
TY		 3675 DI(SrcNone | Priv, monitor),
3676 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3677 N, N, N, N, N, N,
3678};
3679
fd0a0d82 3680static const struct opcode group7_rm3[] = {
1c2545be
TY		 3681 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3682 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3683 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3684 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3685 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3686 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3687 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3688 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3689};
6230f7fc 3690
fd0a0d82 3691static const struct opcode group7_rm7[] = {
d7eb8203 3692 N,
1c2545be 3693 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3694 N, N, N, N, N, N,
3695};
d67fc27a 3696
fd0a0d82 3697static const struct opcode group1[] = {
fb864fbc
AK		 3698 F(Lock, em_add),
3699 F(Lock | PageTable, em_or),
3700 F(Lock, em_adc),
3701 F(Lock, em_sbb),
3702 F(Lock | PageTable, em_and),
3703 F(Lock, em_sub),
3704 F(Lock, em_xor),
3705 F(NoWrite, em_cmp),
73fba5f4
AK		 3706};
3707
fd0a0d82 3708static const struct opcode group1A[] = {
1c2545be 3709 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3710};
3711
fd0a0d82 3712static const struct opcode group3[] = {
fb864fbc
AK		 3713 F(DstMem | SrcImm | NoWrite, em_test),
3714 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3715 F(DstMem | SrcNone | Lock, em_not),
3716 F(DstMem | SrcNone | Lock, em_neg),
1c2545be
TY		 3717 I(SrcMem, em_mul_ex),
3718 I(SrcMem, em_imul_ex),
3719 I(SrcMem, em_div_ex),
3720 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3721};
3722
fd0a0d82 3723static const struct opcode group4[] = {
1c2545be
TY		 3724 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3725 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3726 N, N, N, N, N, N,
3727};
3728
fd0a0d82 3729static const struct opcode group5[] = {
1c2545be
TY		 3730 I(DstMem | SrcNone | Lock, em_grp45),
3731 I(DstMem | SrcNone | Lock, em_grp45),
3732 I(SrcMem | Stack, em_grp45),
3733 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3734 I(SrcMem | Stack, em_grp45),
3735 I(SrcMemFAddr | ImplicitOps, em_grp45),
3736 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3737};
3738
fd0a0d82 3739static const struct opcode group6[] = {
1c2545be
TY		 3740 DI(Prot, sldt),
3741 DI(Prot, str),
a14e579f 3742 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3743 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3744 N, N, N, N,
3745};
3746
fd0a0d82 3747static const struct group_dual group7 = { {
96051572
AK		 3748 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3749 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3750 II(SrcMem | Priv, em_lgdt, lgdt),
3751 II(SrcMem | Priv, em_lidt, lidt),
3752 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3753 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3754 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3755}, {
1c2545be 3756 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3757 EXT(0, group7_rm1),
01de8b09 3758 N, EXT(0, group7_rm3),
1c2545be
TY		 3759 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3760 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3761 EXT(0, group7_rm7),
73fba5f4
AK		 3762} };
3763
fd0a0d82 3764static const struct opcode group8[] = {
73fba5f4 3765 N, N, N, N,
1c2545be
TY		 3766 I(DstMem | SrcImmByte, em_bt),
3767 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3768 I(DstMem | SrcImmByte | Lock, em_btr),
3769 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3770};
3771
fd0a0d82 3772static const struct group_dual group9 = { {
1c2545be 3773 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3774}, {
3775 N, N, N, N, N, N, N, N,
3776} };
3777
fd0a0d82 3778static const struct opcode group11[] = {
1c2545be 3779 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3780 X7(D(Undefined)),
a4d4a7c1
AK		 3781};
3782
fd0a0d82 3783static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3784 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3785};
3786
fd0a0d82 3787static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3788 I(0, em_mov), N, N, N,
3789};
3790
045a282c
GN		 3791static const struct escape escape_d9 = { {
3792 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3793}, {
3794 /* 0xC0 - 0xC7 */
3795 N, N, N, N, N, N, N, N,
3796 /* 0xC8 - 0xCF */
3797 N, N, N, N, N, N, N, N,
3798 /* 0xD0 - 0xC7 */
3799 N, N, N, N, N, N, N, N,
3800 /* 0xD8 - 0xDF */
3801 N, N, N, N, N, N, N, N,
3802 /* 0xE0 - 0xE7 */
3803 N, N, N, N, N, N, N, N,
3804 /* 0xE8 - 0xEF */
3805 N, N, N, N, N, N, N, N,
3806 /* 0xF0 - 0xF7 */
3807 N, N, N, N, N, N, N, N,
3808 /* 0xF8 - 0xFF */
3809 N, N, N, N, N, N, N, N,
3810} };
3811
3812static const struct escape escape_db = { {
3813 N, N, N, N, N, N, N, N,
3814}, {
3815 /* 0xC0 - 0xC7 */
3816 N, N, N, N, N, N, N, N,
3817 /* 0xC8 - 0xCF */
3818 N, N, N, N, N, N, N, N,
3819 /* 0xD0 - 0xC7 */
3820 N, N, N, N, N, N, N, N,
3821 /* 0xD8 - 0xDF */
3822 N, N, N, N, N, N, N, N,
3823 /* 0xE0 - 0xE7 */
3824 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3825 /* 0xE8 - 0xEF */
3826 N, N, N, N, N, N, N, N,
3827 /* 0xF0 - 0xF7 */
3828 N, N, N, N, N, N, N, N,
3829 /* 0xF8 - 0xFF */
3830 N, N, N, N, N, N, N, N,
3831} };
3832
3833static const struct escape escape_dd = { {
3834 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3835}, {
3836 /* 0xC0 - 0xC7 */
3837 N, N, N, N, N, N, N, N,
3838 /* 0xC8 - 0xCF */
3839 N, N, N, N, N, N, N, N,
3840 /* 0xD0 - 0xC7 */
3841 N, N, N, N, N, N, N, N,
3842 /* 0xD8 - 0xDF */
3843 N, N, N, N, N, N, N, N,
3844 /* 0xE0 - 0xE7 */
3845 N, N, N, N, N, N, N, N,
3846 /* 0xE8 - 0xEF */
3847 N, N, N, N, N, N, N, N,
3848 /* 0xF0 - 0xF7 */
3849 N, N, N, N, N, N, N, N,
3850 /* 0xF8 - 0xFF */
3851 N, N, N, N, N, N, N, N,
3852} };
3853
fd0a0d82 3854static const struct opcode opcode_table[256] = {
73fba5f4 3855 /* 0x00 - 0x07 */
fb864fbc 3856 F6ALU(Lock, em_add),
1cd196ea
AK		 3857 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3858 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3859 /* 0x08 - 0x0F */
fb864fbc 3860 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3861 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3862 N,
73fba5f4 3863 /* 0x10 - 0x17 */
fb864fbc 3864 F6ALU(Lock, em_adc),
1cd196ea
AK		 3865 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3866 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3867 /* 0x18 - 0x1F */
fb864fbc 3868 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3869 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3870 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3871 /* 0x20 - 0x27 */
fb864fbc 3872 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3873 /* 0x28 - 0x2F */
fb864fbc 3874 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3875 /* 0x30 - 0x37 */
fb864fbc 3876 F6ALU(Lock, em_xor), N, N,
73fba5f4 3877 /* 0x38 - 0x3F */
fb864fbc 3878 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4
AK		 3879 /* 0x40 - 0x4F */
3880 X16(D(DstReg)),
3881 /* 0x50 - 0x57 */
63540382 3882 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3883 /* 0x58 - 0x5F */
c54fe504 3884 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3885 /* 0x60 - 0x67 */
b96a7fad
TY		 3886 I(ImplicitOps | Stack | No64, em_pusha),
3887 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3888 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3889 N, N, N, N,
3890 /* 0x68 - 0x6F */
d46164db
AK		 3891 I(SrcImm | Mov | Stack, em_push),
3892 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3893 I(SrcImmByte | Mov | Stack, em_push),
3894 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3895 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3896 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3897 /* 0x70 - 0x7F */
3898 X16(D(SrcImmByte)),
3899 /* 0x80 - 0x87 */
1c2545be
TY		 3900 G(ByteOp | DstMem | SrcImm, group1),
3901 G(DstMem | SrcImm, group1),
3902 G(ByteOp | DstMem | SrcImm | No64, group1),
3903 G(DstMem | SrcImmByte, group1),
fb864fbc 3904 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3905 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3906 /* 0x88 - 0x8F */
d5ae7ce8 3907 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3908 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3909 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3910 D(ModRM | SrcMem | NoAccess | DstReg),
3911 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3912 G(0, group1A),
73fba5f4 3913 /* 0x90 - 0x97 */
bf608f88 3914 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3915 /* 0x98 - 0x9F */
61429142 3916 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3917 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3918 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3919 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3920 /* 0xA0 - 0xA7 */
b9eac5f4 3921 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3922 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3923 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3924 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3925 /* 0xA8 - 0xAF */
fb864fbc 3926 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3927 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3928 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3929 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3930 /* 0xB0 - 0xB7 */
b9eac5f4 3931 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3932 /* 0xB8 - 0xBF */
5e2c6883 3933 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3934 /* 0xC0 - 0xC7 */
d2c6c7ad 3935 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3936 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3937 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3938 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3939 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3940 G(ByteOp, group11), G(0, group11),
73fba5f4 3941 /* 0xC8 - 0xCF */
612e89f0
AK		 3942 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3943 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3944 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3945 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3946 /* 0xD0 - 0xD7 */
d2c6c7ad 3947 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
7f662273 3948 N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
73fba5f4 3949 /* 0xD8 - 0xDF */
045a282c 3950 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3951 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3952 X3(I(SrcImmByte, em_loop)),
3953 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3954 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3955 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3956 /* 0xE8 - 0xEF */
d4ddafcd 3957 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3958 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3959 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3960 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3961 /* 0xF0 - 0xF7 */
bf608f88 3962 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3963 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3964 G(ByteOp, group3), G(0, group3),
73fba5f4 3965 /* 0xF8 - 0xFF */
f411e6cd
TY		 3966 D(ImplicitOps), D(ImplicitOps),
3967 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3968 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3969};
3970
fd0a0d82 3971static const struct opcode twobyte_table[256] = {
73fba5f4 3972 /* 0x00 - 0x0F */
dee6bb70 3973 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3974 N, I(ImplicitOps | VendorSpecific, em_syscall),
3975 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3976 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3977 N, D(ImplicitOps | ModRM), N, N,
3978 /* 0x10 - 0x1F */
3979 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3980 /* 0x20 - 0x2F */
cfec82cb 3981 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3982 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3983 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3984 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3985 N, N, N, N,
3e114eb4
AK		 3986 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3987 N, N, N, N,
73fba5f4 3988 /* 0x30 - 0x3F */
e1e210b0 3989 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3990 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3991 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3992 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3993 I(ImplicitOps | VendorSpecific, em_sysenter),
3994 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3995 N, N,
73fba5f4
AK		 3996 N, N, N, N, N, N, N, N,
3997 /* 0x40 - 0x4F */
3998 X16(D(DstReg | SrcMem | ModRM | Mov)),
3999 /* 0x50 - 0x5F */
4000 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4001 /* 0x60 - 0x6F */
aa97bb48
AK		 4002 N, N, N, N,
4003 N, N, N, N,
4004 N, N, N, N,
4005 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4006 /* 0x70 - 0x7F */
aa97bb48
AK		 4007 N, N, N, N,
4008 N, N, N, N,
4009 N, N, N, N,
4010 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 4011 /* 0x80 - 0x8F */
4012 X16(D(SrcImm)),
4013 /* 0x90 - 0x9F */
ee45b58e 4014 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4015 /* 0xA0 - 0xA7 */
1cd196ea 4016 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 4017 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 4018 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4019 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
4020 /* 0xA8 - 0xAF */
1cd196ea 4021 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4022 DI(ImplicitOps, rsm),
ce7faab2 4023 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 4024 D(DstMem | SrcReg | Src2ImmByte | ModRM),
4025 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 4026 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4027 /* 0xB0 - 0xB7 */
e940b5c2 4028 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4029 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 4030 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4031 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4032 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4033 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4034 /* 0xB8 - 0xBF */
4035 N, N,
ce7faab2
TY		 4036 G(BitOp, group8),
4037 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 4038 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4039 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4040 /* 0xC0 - 0xC7 */
739ae406 4041 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 4042 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 4043 N, N, N, GD(0, &group9),
9299836e
AK		 4044 /* 0xC8 - 0xCF */
4045 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4046 /* 0xD0 - 0xDF */
4047 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4048 /* 0xE0 - 0xEF */
4049 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4050 /* 0xF0 - 0xFF */
4051 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4052};
4053
4054#undef D
4055#undef N
4056#undef G
4057#undef GD
4058#undef I
aa97bb48 4059#undef GP
01de8b09 4060#undef EXT
73fba5f4 4061
8d8f4e9f 4062#undef D2bv
f6511935 4063#undef D2bvIP
8d8f4e9f 4064#undef I2bv
d7841a4b 4065#undef I2bvIP
d67fc27a 4066#undef I6ALU
8d8f4e9f 4067
9dac77fa 4068static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4069{
4070 unsigned size;
4071
9dac77fa 4072 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4073 if (size == 8)
4074 size = 4;
4075 return size;
4076}
4077
4078static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4079 unsigned size, bool sign_extension)
4080{
39f21ee5
AK		 4081 int rc = X86EMUL_CONTINUE;
4082
4083 op->type = OP_IMM;
4084 op->bytes = size;
9dac77fa 4085 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4086 /* NB. Immediates are sign-extended as necessary. */
4087 switch (op->bytes) {
4088 case 1:
e85a1085 4089 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4090 break;
4091 case 2:
e85a1085 4092 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4093 break;
4094 case 4:
e85a1085 4095 op->val = insn_fetch(s32, ctxt);
39f21ee5 4096 break;
5e2c6883
NA		 4097 case 8:
4098 op->val = insn_fetch(s64, ctxt);
4099 break;
39f21ee5
AK		 4100 }
4101 if (!sign_extension) {
4102 switch (op->bytes) {
4103 case 1:
4104 op->val &= 0xff;
4105 break;
4106 case 2:
4107 op->val &= 0xffff;
4108 break;
4109 case 4:
4110 op->val &= 0xffffffff;
4111 break;
4112 }
4113 }
4114done:
4115 return rc;
4116}
4117
a9945549
AK		 4118static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4119 unsigned d)
4120{
4121 int rc = X86EMUL_CONTINUE;
4122
4123 switch (d) {
4124 case OpReg:
2adb5ad9 4125 decode_register_operand(ctxt, op);
a9945549
AK		 4126 break;
4127 case OpImmUByte:
608aabe3 4128 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4129 break;
4130 case OpMem:
41ddf978 4131 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4132 mem_common:
4133 *op = ctxt->memop;
4134 ctxt->memopp = op;
4135 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4136 fetch_bit_operand(ctxt);
4137 op->orig_val = op->val;
4138 break;
41ddf978
AK		 4139 case OpMem64:
4140 ctxt->memop.bytes = 8;
4141 goto mem_common;
a9945549
AK		 4142 case OpAcc:
4143 op->type = OP_REG;
4144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4145 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4146 fetch_register_operand(op);
4147 op->orig_val = op->val;
4148 break;
4149 case OpDI:
4150 op->type = OP_MEM;
4151 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4152 op->addr.mem.ea =
dd856efa 4153 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4154 op->addr.mem.seg = VCPU_SREG_ES;
4155 op->val = 0;
b3356bf0 4156 op->count = 1;
a9945549
AK		 4157 break;
4158 case OpDX:
4159 op->type = OP_REG;
4160 op->bytes = 2;
dd856efa 4161 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4162 fetch_register_operand(op);
4163 break;
4dd6a57d
AK		 4164 case OpCL:
4165 op->bytes = 1;
dd856efa 4166 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4167 break;
4168 case OpImmByte:
4169 rc = decode_imm(ctxt, op, 1, true);
4170 break;
4171 case OpOne:
4172 op->bytes = 1;
4173 op->val = 1;
4174 break;
4175 case OpImm:
4176 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4177 break;
5e2c6883
NA		 4178 case OpImm64:
4179 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4180 break;
28867cee
AK		 4181 case OpMem8:
4182 ctxt->memop.bytes = 1;
4183 goto mem_common;
0fe59128
AK		 4184 case OpMem16:
4185 ctxt->memop.bytes = 2;
4186 goto mem_common;
4187 case OpMem32:
4188 ctxt->memop.bytes = 4;
4189 goto mem_common;
4190 case OpImmU16:
4191 rc = decode_imm(ctxt, op, 2, false);
4192 break;
4193 case OpImmU:
4194 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4195 break;
4196 case OpSI:
4197 op->type = OP_MEM;
4198 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4199 op->addr.mem.ea =
dd856efa 4200 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4201 op->addr.mem.seg = seg_override(ctxt);
4202 op->val = 0;
b3356bf0 4203 op->count = 1;
0fe59128
AK		 4204 break;
4205 case OpImmFAddr:
4206 op->type = OP_IMM;
4207 op->addr.mem.ea = ctxt->_eip;
4208 op->bytes = ctxt->op_bytes + 2;
4209 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4210 break;
4211 case OpMemFAddr:
4212 ctxt->memop.bytes = ctxt->op_bytes + 2;
4213 goto mem_common;
c191a7a0
AK		 4214 case OpES:
4215 op->val = VCPU_SREG_ES;
4216 break;
4217 case OpCS:
4218 op->val = VCPU_SREG_CS;
4219 break;
4220 case OpSS:
4221 op->val = VCPU_SREG_SS;
4222 break;
4223 case OpDS:
4224 op->val = VCPU_SREG_DS;
4225 break;
4226 case OpFS:
4227 op->val = VCPU_SREG_FS;
4228 break;
4229 case OpGS:
4230 op->val = VCPU_SREG_GS;
4231 break;
a9945549
AK		 4232 case OpImplicit:
4233 /* Special instructions do their own operand decoding. */
4234 default:
4235 op->type = OP_NONE; /* Disable writeback. */
4236 break;
4237 }
4238
4239done:
4240 return rc;
4241}
4242
ef5d75cc 4243int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4244{
dde7e6d1
AK		 4245 int rc = X86EMUL_CONTINUE;
4246 int mode = ctxt->mode;
46561646 4247 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4248 bool op_prefix = false;
46561646 4249 struct opcode opcode;
dde7e6d1 4250
f09ed83e
AK		 4251 ctxt->memop.type = OP_NONE;
4252 ctxt->memopp = NULL;
9dac77fa
AK		 4253 ctxt->_eip = ctxt->eip;
4254 ctxt->fetch.start = ctxt->_eip;
4255 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 4256 if (insn_len > 0)
9dac77fa 4257 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4258
4259 switch (mode) {
4260 case X86EMUL_MODE_REAL:
4261 case X86EMUL_MODE_VM86:
4262 case X86EMUL_MODE_PROT16:
4263 def_op_bytes = def_ad_bytes = 2;
4264 break;
4265 case X86EMUL_MODE_PROT32:
4266 def_op_bytes = def_ad_bytes = 4;
4267 break;
4268#ifdef CONFIG_X86_64
4269 case X86EMUL_MODE_PROT64:
4270 def_op_bytes = 4;
4271 def_ad_bytes = 8;
4272 break;
4273#endif
4274 default:
1d2887e2 4275 return EMULATION_FAILED;
dde7e6d1
AK		 4276 }
4277
9dac77fa
AK		 4278 ctxt->op_bytes = def_op_bytes;
4279 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4280
4281 /* Legacy prefixes. */
4282 for (;;) {
e85a1085 4283 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4284 case 0x66: /* operand-size override */
0d7cdee8 4285 op_prefix = true;
dde7e6d1 4286 /* switch between 2/4 bytes */
9dac77fa 4287 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4288 break;
4289 case 0x67: /* address-size override */
4290 if (mode == X86EMUL_MODE_PROT64)
4291 /* switch between 4/8 bytes */
9dac77fa 4292 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4293 else
4294 /* switch between 2/4 bytes */
9dac77fa 4295 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4296 break;
4297 case 0x26: /* ES override */
4298 case 0x2e: /* CS override */
4299 case 0x36: /* SS override */
4300 case 0x3e: /* DS override */
9dac77fa 4301 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4302 break;
4303 case 0x64: /* FS override */
4304 case 0x65: /* GS override */
9dac77fa 4305 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4306 break;
4307 case 0x40 ... 0x4f: /* REX */
4308 if (mode != X86EMUL_MODE_PROT64)
4309 goto done_prefixes;
9dac77fa 4310 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4311 continue;
4312 case 0xf0: /* LOCK */
9dac77fa 4313 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4314 break;
4315 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4316 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4317 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4318 break;
4319 default:
4320 goto done_prefixes;
4321 }
4322
4323 /* Any legacy prefix after a REX prefix nullifies its effect. */
4324
9dac77fa 4325 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4326 }
4327
4328done_prefixes:
4329
4330 /* REX prefix. */
9dac77fa
AK		 4331 if (ctxt->rex_prefix & 8)
4332 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4333
4334 /* Opcode byte(s). */
9dac77fa 4335 opcode = opcode_table[ctxt->b];
d3ad6243 4336 /* Two-byte opcode? */
9dac77fa
AK		 4337 if (ctxt->b == 0x0f) {
4338 ctxt->twobyte = 1;
e85a1085 4339 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4340 opcode = twobyte_table[ctxt->b];
dde7e6d1 4341 }
9dac77fa 4342 ctxt->d = opcode.flags;
dde7e6d1 4343
9f4260e7
TY		 4344 if (ctxt->d & ModRM)
4345 ctxt->modrm = insn_fetch(u8, ctxt);
4346
9dac77fa
AK		 4347 while (ctxt->d & GroupMask) {
4348 switch (ctxt->d & GroupMask) {
46561646 4349 case Group:
9dac77fa 4350 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4351 opcode = opcode.u.group[goffset];
4352 break;
4353 case GroupDual:
9dac77fa
AK		 4354 goffset = (ctxt->modrm >> 3) & 7;
4355 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4356 opcode = opcode.u.gdual->mod3[goffset];
4357 else
4358 opcode = opcode.u.gdual->mod012[goffset];
4359 break;
4360 case RMExt:
9dac77fa 4361 goffset = ctxt->modrm & 7;
01de8b09 4362 opcode = opcode.u.group[goffset];
46561646
AK		 4363 break;
4364 case Prefix:
9dac77fa 4365 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4366 return EMULATION_FAILED;
9dac77fa 4367 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4368 switch (simd_prefix) {
4369 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4370 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4371 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4372 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4373 }
4374 break;
045a282c
GN		 4375 case Escape:
4376 if (ctxt->modrm > 0xbf)
4377 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4378 else
4379 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4380 break;
46561646 4381 default:
1d2887e2 4382 return EMULATION_FAILED;
0d7cdee8 4383 }
46561646 4384
b1ea50b2 4385 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4386 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4387 }
4388
9dac77fa
AK		 4389 ctxt->execute = opcode.u.execute;
4390 ctxt->check_perm = opcode.check_perm;
4391 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4392
4393 /* Unrecognised? */
9dac77fa 4394 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4395 return EMULATION_FAILED;
dde7e6d1 4396
9dac77fa 4397 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4398 return EMULATION_FAILED;
d867162c 4399
9dac77fa
AK		 4400 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4401 ctxt->op_bytes = 8;
dde7e6d1 4402
9dac77fa 4403 if (ctxt->d & Op3264) {
7f9b4b75 4404 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4405 ctxt->op_bytes = 8;
7f9b4b75 4406 else
9dac77fa 4407 ctxt->op_bytes = 4;
7f9b4b75
AK		 4408 }
4409
9dac77fa
AK		 4410 if (ctxt->d & Sse)
4411 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4412 else if (ctxt->d & Mmx)
4413 ctxt->op_bytes = 8;
1253791d 4414
dde7e6d1 4415 /* ModRM and SIB bytes. */
9dac77fa 4416 if (ctxt->d & ModRM) {
f09ed83e 4417 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4418 if (!ctxt->has_seg_override)
4419 set_seg_override(ctxt, ctxt->modrm_seg);
4420 } else if (ctxt->d & MemAbs)
f09ed83e 4421 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4422 if (rc != X86EMUL_CONTINUE)
4423 goto done;
4424
9dac77fa
AK		 4425 if (!ctxt->has_seg_override)
4426 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4427
f09ed83e 4428 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4429
f09ed83e
AK		 4430 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4431 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4432
dde7e6d1
AK		 4433 /*
4434 * Decode and fetch the source operand: register, memory
4435 * or immediate.
4436 */
0fe59128 4437 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4438 if (rc != X86EMUL_CONTINUE)
4439 goto done;
4440
dde7e6d1
AK		 4441 /*
4442 * Decode and fetch the second source operand: register, memory
4443 * or immediate.
4444 */
4dd6a57d 4445 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4446 if (rc != X86EMUL_CONTINUE)
4447 goto done;
4448
dde7e6d1 4449 /* Decode and fetch the destination operand: register or memory. */
a9945549 4450 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4451
4452done:
f09ed83e
AK		 4453 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4454 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4455
1d2887e2 4456 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4457}
4458
1cb3f3ae
XG		 4459bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4460{
4461 return ctxt->d & PageTable;
4462}
4463
3e2f65d5
GN		 4464static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4465{
3e2f65d5
GN		 4466 /* The second termination condition only applies for REPE
4467 * and REPNE. Test if the repeat string operation prefix is
4468 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4469 * corresponding termination condition according to:
4470 * - if REPE/REPZ and ZF = 0 then done
4471 * - if REPNE/REPNZ and ZF = 1 then done
4472 */
9dac77fa
AK		 4473 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4474 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4475 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4476 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4477 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4478 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4479 return true;
4480
4481 return false;
4482}
4483
cbe2c9d3
AK		 4484static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4485{
4486 bool fault = false;
4487
4488 ctxt->ops->get_fpu(ctxt);
4489 asm volatile("1: fwait \n\t"
4490 "2: \n\t"
4491 ".pushsection .fixup,\"ax\" \n\t"
4492 "3: \n\t"
4493 "movb $1, %[fault] \n\t"
4494 "jmp 2b \n\t"
4495 ".popsection \n\t"
4496 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4497 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4498 ctxt->ops->put_fpu(ctxt);
4499
4500 if (unlikely(fault))
4501 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4502
4503 return X86EMUL_CONTINUE;
4504}
4505
4506static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4507 struct operand *op)
4508{
4509 if (op->type == OP_MM)
4510 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4511}
4512
e28bbd44
AK		 4513static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4514{
4515 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4516 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4517 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4518 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
4519 : "c"(ctxt->src2.val), [fastop]"S"(fop));
4520 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4521 return X86EMUL_CONTINUE;
4522}
dd856efa 4523
7b105ca2 4524int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4525{
0225fb50 4526 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4527 int rc = X86EMUL_CONTINUE;
9dac77fa 4528 int saved_dst_type = ctxt->dst.type;
8b4caf66 4529
9dac77fa 4530 ctxt->mem_read.pos = 0;
310b5d30 4531
9dac77fa 4532 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4533 rc = emulate_ud(ctxt);
1161624f
GN		 4534 goto done;
4535 }
4536
d380a5e4 4537 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4538 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4539 rc = emulate_ud(ctxt);
d380a5e4
GN		 4540 goto done;
4541 }
4542
9dac77fa 4543 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4544 rc = emulate_ud(ctxt);
081bca0e
AK		 4545 goto done;
4546 }
4547
cbe2c9d3
AK		 4548 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4549 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4550 rc = emulate_ud(ctxt);
4551 goto done;
4552 }
4553
cbe2c9d3 4554 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4555 rc = emulate_nm(ctxt);
4556 goto done;
4557 }
4558
cbe2c9d3
AK		 4559 if (ctxt->d & Mmx) {
4560 rc = flush_pending_x87_faults(ctxt);
4561 if (rc != X86EMUL_CONTINUE)
4562 goto done;
4563 /*
4564 * Now that we know the fpu is exception safe, we can fetch
4565 * operands from it.
4566 */
4567 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4568 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4569 if (!(ctxt->d & Mov))
4570 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4571 }
4572
9dac77fa
AK		 4573 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4574 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4575 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4576 if (rc != X86EMUL_CONTINUE)
4577 goto done;
4578 }
4579
e92805ac 4580 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4581 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4582 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4583 goto done;
4584 }
4585
8ea7d6ae 4586 /* Instruction can only be executed in protected mode */
9d1b39a9 4587 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4588 rc = emulate_ud(ctxt);
4589 goto done;
4590 }
4591
d09beabd 4592 /* Do instruction specific permission checks */
9dac77fa
AK		 4593 if (ctxt->check_perm) {
4594 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4595 if (rc != X86EMUL_CONTINUE)
4596 goto done;
4597 }
4598
9dac77fa
AK		 4599 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4600 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4601 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4602 if (rc != X86EMUL_CONTINUE)
4603 goto done;
4604 }
4605
9dac77fa 4606 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4607 /* All REP prefixes have the same first termination condition */
dd856efa 4608 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4609 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4610 goto done;
4611 }
b9fa9d6b
AK		 4612 }
4613
9dac77fa
AK		 4614 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4615 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4616 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4617 if (rc != X86EMUL_CONTINUE)
8b4caf66 4618 goto done;
9dac77fa 4619 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4620 }
4621
9dac77fa
AK		 4622 if (ctxt->src2.type == OP_MEM) {
4623 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4624 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4625 if (rc != X86EMUL_CONTINUE)
4626 goto done;
4627 }
4628
9dac77fa 4629 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4630 goto special_insn;
4631
4632
9dac77fa 4633 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4634 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4635 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4636 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4637 if (rc != X86EMUL_CONTINUE)
4638 goto done;
038e51de 4639 }
9dac77fa 4640 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4641
018a98db
AK		 4642special_insn:
4643
9dac77fa
AK		 4644 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4645 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4646 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4647 if (rc != X86EMUL_CONTINUE)
4648 goto done;
4649 }
4650
9dac77fa 4651 if (ctxt->execute) {
e28bbd44
AK		 4652 if (ctxt->d & Fastop) {
4653 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4654 rc = fastop(ctxt, fop);
4655 if (rc != X86EMUL_CONTINUE)
4656 goto done;
4657 goto writeback;
4658 }
9dac77fa 4659 rc = ctxt->execute(ctxt);
ef65c889
AK		 4660 if (rc != X86EMUL_CONTINUE)
4661 goto done;
4662 goto writeback;
4663 }
4664
9dac77fa 4665 if (ctxt->twobyte)
6aa8b732
AK		 4666 goto twobyte_insn;
4667
9dac77fa 4668 switch (ctxt->b) {
33615aa9 4669 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4670 emulate_1op(ctxt, "inc");
33615aa9
AK		 4671 break;
4672 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4673 emulate_1op(ctxt, "dec");
33615aa9 4674 break;
6aa8b732 4675 case 0x63: /* movsxd */
8b4caf66 4676 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4677 goto cannot_emulate;
9dac77fa 4678 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4679 break;
b2833e3c 4680 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4681 if (test_cc(ctxt->b, ctxt->eflags))
4682 jmp_rel(ctxt, ctxt->src.val);
018a98db 4683 break;
7e0b54b1 4684 case 0x8d: /* lea r16/r32, m */
9dac77fa 4685 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4686 break;
3d9e77df 4687 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4688 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4689 break;
e4f973ae
TY		 4690 rc = em_xchg(ctxt);
4691 break;
e8b6fa70 4692 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4693 switch (ctxt->op_bytes) {
4694 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4695 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4696 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4697 }
4698 break;
018a98db 4699 case 0xc0 ... 0xc1:
51187683 4700 rc = em_grp2(ctxt);
018a98db 4701 break;
6e154e56 4702 case 0xcc: /* int3 */
5c5df76b
TY		 4703 rc = emulate_int(ctxt, 3);
4704 break;
6e154e56 4705 case 0xcd: /* int n */
9dac77fa 4706 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4707 break;
4708 case 0xce: /* into */
5c5df76b
TY		 4709 if (ctxt->eflags & EFLG_OF)
4710 rc = emulate_int(ctxt, 4);
6e154e56 4711 break;
018a98db 4712 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4713 rc = em_grp2(ctxt);
018a98db
AK		 4714 break;
4715 case 0xd2 ... 0xd3: /* Grp2 */
dd856efa 4716 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
51187683 4717 rc = em_grp2(ctxt);
018a98db 4718 break;
1a52e051 4719 case 0xe9: /* jmp rel */
db5b0762 4720 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4721 jmp_rel(ctxt, ctxt->src.val);
4722 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4723 break;
111de5d6 4724 case 0xf4: /* hlt */
6c3287f7 4725 ctxt->ops->halt(ctxt);
19fdfa0d 4726 break;
111de5d6
AK		 4727 case 0xf5: /* cmc */
4728 /* complement carry flag from eflags reg */
4729 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4730 break;
4731 case 0xf8: /* clc */
4732 ctxt->eflags &= ~EFLG_CF;
111de5d6 4733 break;
8744aa9a
MG		 4734 case 0xf9: /* stc */
4735 ctxt->eflags |= EFLG_CF;
4736 break;
fb4616f4
MG		 4737 case 0xfc: /* cld */
4738 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4739 break;
4740 case 0xfd: /* std */
4741 ctxt->eflags |= EFLG_DF;
fb4616f4 4742 break;
91269b8f
AK		 4743 default:
4744 goto cannot_emulate;
6aa8b732 4745 }
018a98db 4746
7d9ddaed
AK		 4747 if (rc != X86EMUL_CONTINUE)
4748 goto done;
4749
018a98db 4750writeback:
adddcecf 4751 rc = writeback(ctxt);
1b30eaa8 4752 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4753 goto done;
4754
5cd21917
GN		 4755 /*
4756 * restore dst type in case the decoding will be reused
4757 * (happens for string instruction )
4758 */
9dac77fa 4759 ctxt->dst.type = saved_dst_type;
5cd21917 4760
9dac77fa 4761 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4762 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4763
9dac77fa 4764 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4765 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4766
9dac77fa 4767 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4768 unsigned int count;
9dac77fa 4769 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4770 if ((ctxt->d & SrcMask) == SrcSI)
4771 count = ctxt->src.count;
4772 else
4773 count = ctxt->dst.count;
4774 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4775 -count);
3e2f65d5 4776
d2ddd1c4
GN		 4777 if (!string_insn_completed(ctxt)) {
4778 /*
4779 * Re-enter guest when pio read ahead buffer is empty
4780 * or, if it is not used, after each 1024 iteration.
4781 */
dd856efa 4782 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4783 (r->end == 0 || r->end != r->pos)) {
4784 /*
4785 * Reset read cache. Usually happens before
4786 * decode, but since instruction is restarted
4787 * we have to do it here.
4788 */
9dac77fa 4789 ctxt->mem_read.end = 0;
dd856efa 4790 writeback_registers(ctxt);
d2ddd1c4
GN		 4791 return EMULATION_RESTART;
4792 }
4793 goto done; /* skip rip writeback */
0fa6ccbd 4794 }
5cd21917 4795 }
d2ddd1c4 4796
9dac77fa 4797 ctxt->eip = ctxt->_eip;
018a98db
AK		 4798
4799done:
da9cb575
AK		 4800 if (rc == X86EMUL_PROPAGATE_FAULT)
4801 ctxt->have_exception = true;
775fde86
JR		 4802 if (rc == X86EMUL_INTERCEPTED)
4803 return EMULATION_INTERCEPTED;
4804
dd856efa
AK		 4805 if (rc == X86EMUL_CONTINUE)
4806 writeback_registers(ctxt);
4807
d2ddd1c4 4808 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4809
4810twobyte_insn:
9dac77fa 4811 switch (ctxt->b) {
018a98db 4812 case 0x09: /* wbinvd */
cfb22375 4813 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4814 break;
4815 case 0x08: /* invd */
018a98db
AK		 4816 case 0x0d: /* GrpP (prefetch) */
4817 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4818 break;
4819 case 0x20: /* mov cr, reg */
9dac77fa 4820 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4821 break;
6aa8b732 4822 case 0x21: /* mov from dr to reg */
9dac77fa 4823 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4824 break;
6aa8b732 4825 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4826 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4827 if (!test_cc(ctxt->b, ctxt->eflags))
4828 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4829 break;
b2833e3c 4830 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4831 if (test_cc(ctxt->b, ctxt->eflags))
4832 jmp_rel(ctxt, ctxt->src.val);
018a98db 4833 break;
ee45b58e 4834 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4835 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4836 break;
9bf8ea42
GT		 4837 case 0xa4: /* shld imm8, r, r/m */
4838 case 0xa5: /* shld cl, r, r/m */
761441b9 4839 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4840 break;
9bf8ea42
GT		 4841 case 0xac: /* shrd imm8, r, r/m */
4842 case 0xad: /* shrd cl, r, r/m */
761441b9 4843 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4844 break;
2a7c5b8b
GC		 4845 case 0xae: /* clflush */
4846 break;
6aa8b732 4847 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4848 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4849 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4850 : (u16) ctxt->src.val;
6aa8b732 4851 break;
6aa8b732 4852 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4853 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4854 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4855 (s16) ctxt->src.val;
6aa8b732 4856 break;
92f738a5 4857 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4858 emulate_2op_SrcV(ctxt, "add");
92f738a5 4859 /* Write back the register source. */
9dac77fa
AK		 4860 ctxt->src.val = ctxt->dst.orig_val;
4861 write_register_operand(&ctxt->src);
92f738a5 4862 break;
a012e65a 4863 case 0xc3: /* movnti */
9dac77fa
AK		 4864 ctxt->dst.bytes = ctxt->op_bytes;
4865 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4866 (u64) ctxt->src.val;
a012e65a 4867 break;
91269b8f
AK		 4868 default:
4869 goto cannot_emulate;
6aa8b732 4870 }
7d9ddaed
AK		 4871
4872 if (rc != X86EMUL_CONTINUE)
4873 goto done;
4874
6aa8b732
AK		 4875 goto writeback;
4876
4877cannot_emulate:
a0c0ab2f 4878 return EMULATION_FAILED;
6aa8b732 4879}
dd856efa
AK		 4880
4881void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4882{
4883 invalidate_registers(ctxt);
4884}
4885
4886void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4887{
4888 writeback_registers(ctxt);
4889}
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