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KVM: x86: Update emulator context mode if SYSENTER xfers to 64-bit mode
[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / emulate.c
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20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
6aa8b732 2/******************************************************************************
56e82318 3 * emulate.c
6aa8b732
AK		 4 *
5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 *
7 * Copyright (c) 2005 Keir Fraser
8 *
9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 10 * privileged instructions:
6aa8b732
AK		 11 *
12 * Copyright (C) 2006 Qumranet
9611c187 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 14 *
15 * Avi Kivity <avi@qumranet.com>
16 * Yaniv Kamay <yaniv@qumranet.com>
17 *
6aa8b732
AK		 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
19 */
20
edf88417 21#include <linux/kvm_host.h>
5fdbf976 22#include "kvm_cache_regs.h"
2f728d66 23#include "kvm_emulate.h"
b7d491e7 24#include <linux/stringify.h>
a7baead7 25#include <asm/fpu/api.h>
3db176d5 26#include <asm/debugreg.h>
1a29b5b7 27#include <asm/nospec-branch.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
d1cd3ce9 31#include "mmu.h"
2d7921c4 32#include "pmu.h"
e99f0507 33
a9945549
AK		 34/*
35 * Operand types
36 */
b1ea50b2
AK		 37#define OpNone 0ull
38#define OpImplicit 1ull /* No generic decode */
39#define OpReg 2ull /* Register */
40#define OpMem 3ull /* Memory */
41#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
42#define OpDI 5ull /* ES:DI/EDI/RDI */
43#define OpMem64 6ull /* Memory, 64-bit */
44#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
45#define OpDX 8ull /* DX register */
4dd6a57d
AK		 46#define OpCL 9ull /* CL register (for shifts) */
47#define OpImmByte 10ull /* 8-bit sign extended immediate */
48#define OpOne 11ull /* Implied 1 */
5e2c6883 49#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 50#define OpMem16 13ull /* Memory operand (16-bit). */
51#define OpMem32 14ull /* Memory operand (32-bit). */
52#define OpImmU 15ull /* Immediate operand, zero extended */
53#define OpSI 16ull /* SI/ESI/RSI */
54#define OpImmFAddr 17ull /* Immediate far address */
55#define OpMemFAddr 18ull /* Far address in memory */
56#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 57#define OpES 20ull /* ES */
58#define OpCS 21ull /* CS */
59#define OpSS 22ull /* SS */
60#define OpDS 23ull /* DS */
61#define OpFS 24ull /* FS */
62#define OpGS 25ull /* GS */
28867cee 63#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 64#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 65#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 66#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
67#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 68
69#define OpBits 5 /* Width of operand field */
b1ea50b2 70#define OpMask ((1ull << OpBits) - 1)
a9945549 71
6aa8b732
AK		 72/*
73 * Opcode effective-address decode tables.
74 * Note that we only emulate instructions that have at least one memory
75 * operand (excluding implicit stack references). We assume that stack
76 * references and instruction fetches will never occur in special memory
77 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
78 * not be handled.
79 */
80
81/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 82#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 83/* Destination operand type. */
a9945549
AK		 84#define DstShift 1
85#define ImplicitOps (OpImplicit << DstShift)
86#define DstReg (OpReg << DstShift)
87#define DstMem (OpMem << DstShift)
88#define DstAcc (OpAcc << DstShift)
89#define DstDI (OpDI << DstShift)
90#define DstMem64 (OpMem64 << DstShift)
16bebefe 91#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 92#define DstImmUByte (OpImmUByte << DstShift)
93#define DstDX (OpDX << DstShift)
820207c8 94#define DstAccLo (OpAccLo << DstShift)
a9945549 95#define DstMask (OpMask << DstShift)
6aa8b732 96/* Source operand type. */
0fe59128
AK		 97#define SrcShift 6
98#define SrcNone (OpNone << SrcShift)
99#define SrcReg (OpReg << SrcShift)
100#define SrcMem (OpMem << SrcShift)
101#define SrcMem16 (OpMem16 << SrcShift)
102#define SrcMem32 (OpMem32 << SrcShift)
103#define SrcImm (OpImm << SrcShift)
104#define SrcImmByte (OpImmByte << SrcShift)
105#define SrcOne (OpOne << SrcShift)
106#define SrcImmUByte (OpImmUByte << SrcShift)
107#define SrcImmU (OpImmU << SrcShift)
108#define SrcSI (OpSI << SrcShift)
7fa57952 109#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 110#define SrcImmFAddr (OpImmFAddr << SrcShift)
111#define SrcMemFAddr (OpMemFAddr << SrcShift)
112#define SrcAcc (OpAcc << SrcShift)
113#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 114#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 115#define SrcDX (OpDX << SrcShift)
28867cee 116#define SrcMem8 (OpMem8 << SrcShift)
820207c8 117#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 118#define SrcMask (OpMask << SrcShift)
221192bd
MT		 119#define BitOp (1<<11)
120#define MemAbs (1<<12) /* Memory operand is absolute displacement */
121#define String (1<<13) /* String instruction (rep capable) */
122#define Stack (1<<14) /* Stack instruction (push/pop) */
123#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
124#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
125#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
126#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
127#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 128#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 129#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 130#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 131#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 132/* Generic ModRM decode. */
133#define ModRM (1<<19)
134/* Destination is only written; never read. */
135#define Mov (1<<20)
d8769fed 136/* Misc flags */
8ea7d6ae 137#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 138#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 139#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 140#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 141#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 142#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 143#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 144#define No64 (1<<28)
d5ae7ce8 145#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 146#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 147/* Source 2 operand type */
0b789eee 148#define Src2Shift (31)
4dd6a57d 149#define Src2None (OpNone << Src2Shift)
ab2c5ce6 150#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 151#define Src2CL (OpCL << Src2Shift)
152#define Src2ImmByte (OpImmByte << Src2Shift)
153#define Src2One (OpOne << Src2Shift)
154#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 155#define Src2ES (OpES << Src2Shift)
156#define Src2CS (OpCS << Src2Shift)
157#define Src2SS (OpSS << Src2Shift)
158#define Src2DS (OpDS << Src2Shift)
159#define Src2FS (OpFS << Src2Shift)
160#define Src2GS (OpGS << Src2Shift)
4dd6a57d 161#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 162#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 163#define AlignMask ((u64)7 << 41)
1c11b376 164#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 165#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
166#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
167#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 168#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 169#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 170#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 171#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 172#define Intercept ((u64)1 << 48) /* Has valid intercept field */
173#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 174#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 175#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 176#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 177#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
0f89b207 178#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
6aa8b732 179
820207c8 180#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 181
d0e53325
AK		 182#define X2(x...) x, x
183#define X3(x...) X2(x), x
184#define X4(x...) X2(x), X2(x)
185#define X5(x...) X4(x), x
186#define X6(x...) X4(x), X2(x)
187#define X7(x...) X4(x), X3(x)
188#define X8(x...) X4(x), X4(x)
189#define X16(x...) X8(x), X8(x)
83babbca 190
e28bbd44
AK		 191#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
192#define FASTOP_SIZE 8
193
d65b1dee 194struct opcode {
b1ea50b2
AK		 195 u64 flags : 56;
196 u64 intercept : 8;
120df890 197 union {
ef65c889 198 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 199 const struct opcode *group;
200 const struct group_dual *gdual;
201 const struct gprefix *gprefix;
045a282c 202 const struct escape *esc;
39f062ff 203 const struct instr_dual *idual;
2276b511 204 const struct mode_dual *mdual;
e28bbd44 205 void (*fastop)(struct fastop *fake);
120df890 206 } u;
d09beabd 207 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 208};
209
210struct group_dual {
211 struct opcode mod012[8];
212 struct opcode mod3[8];
d65b1dee
AK		 213};
214
0d7cdee8
AK		 215struct gprefix {
216 struct opcode pfx_no;
217 struct opcode pfx_66;
218 struct opcode pfx_f2;
219 struct opcode pfx_f3;
220};
221
045a282c
GN		 222struct escape {
223 struct opcode op[8];
224 struct opcode high[64];
225};
226
39f062ff
NA		 227struct instr_dual {
228 struct opcode mod012;
229 struct opcode mod3;
230};
231
2276b511
NA		 232struct mode_dual {
233 struct opcode mode32;
234 struct opcode mode64;
235};
236
62bd430e 237#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 238
3dc4bc4f
NA		 239enum x86_transfer_type {
240 X86_TRANSFER_NONE,
241 X86_TRANSFER_CALL_JMP,
242 X86_TRANSFER_RET,
243 X86_TRANSFER_TASK_SWITCH,
244};
245
dd856efa
AK		 246static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
247{
248 if (!(ctxt->regs_valid & (1 << nr))) {
249 ctxt->regs_valid |= 1 << nr;
250 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
251 }
252 return ctxt->_regs[nr];
253}
254
255static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
256{
257 ctxt->regs_valid |= 1 << nr;
258 ctxt->regs_dirty |= 1 << nr;
259 return &ctxt->_regs[nr];
260}
261
262static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
263{
264 reg_read(ctxt, nr);
265 return reg_write(ctxt, nr);
266}
267
268static void writeback_registers(struct x86_emulate_ctxt *ctxt)
269{
270 unsigned reg;
271
272 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
273 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
274}
275
276static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
277{
278 ctxt->regs_dirty = 0;
279 ctxt->regs_valid = 0;
280}
281
6aa8b732
AK		 282/*
283 * These EFLAGS bits are restored from saved value during emulation, and
284 * any changes are written back to the saved value after emulation.
285 */
0efb0440
NA		 286#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
287 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 288
dda96d8f
AK		 289#ifdef CONFIG_X86_64
290#define ON64(x) x
291#else
292#define ON64(x)
293#endif
294
b78a8552
QC		 295/*
296 * fastop functions have a special calling convention:
297 *
298 * dst: rax (in/out)
299 * src: rdx (in/out)
300 * src2: rcx (in)
301 * flags: rflags (in/out)
302 * ex: rsi (in:fastop pointer, out:zero if exception)
303 *
304 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
305 * different operand sizes can be reached by calculation, rather than a jump
306 * table (which would be bigger than the code).
307 */
3009afc6 308static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop);
4d758349 309
d99a6ce7 310#define __FOP_FUNC(name) \
1482a082
JP		 311 ".align " __stringify(FASTOP_SIZE) " \n\t" \
312 ".type " name ", @function \n\t" \
313 name ":\n\t"
314
d99a6ce7
JP		 315#define FOP_FUNC(name) \
316 __FOP_FUNC(#name)
317
318#define __FOP_RET(name) \
319 "ret \n\t" \
320 ".size " name ", .-" name "\n\t"
321
322#define FOP_RET(name) \
323 __FOP_RET(#name)
b7d491e7
AK		 324
325#define FOP_START(op) \
326 extern void em_##op(struct fastop *fake); \
327 asm(".pushsection .text, \"ax\" \n\t" \
328 ".global em_" #op " \n\t" \
d99a6ce7
JP		 329 ".align " __stringify(FASTOP_SIZE) " \n\t" \
330 "em_" #op ":\n\t"
b7d491e7
AK		 331
332#define FOP_END \
333 ".popsection")
334
d99a6ce7
JP		 335#define __FOPNOP(name) \
336 __FOP_FUNC(name) \
337 __FOP_RET(name)
338
1482a082 339#define FOPNOP() \
d99a6ce7 340 __FOPNOP(__stringify(__UNIQUE_ID(nop)))
0bdea068 341
b7d491e7 342#define FOP1E(op, dst) \
d99a6ce7
JP		 343 __FOP_FUNC(#op "_" #dst) \
344 "10: " #op " %" #dst " \n\t" \
345 __FOP_RET(#op "_" #dst)
b8c0b6ae
AK		 346
347#define FOP1EEX(op, dst) \
348 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 349
350#define FASTOP1(op) \
351 FOP_START(op) \
352 FOP1E(op##b, al) \
353 FOP1E(op##w, ax) \
354 FOP1E(op##l, eax) \
355 ON64(FOP1E(op##q, rax)) \
356 FOP_END
357
b9fa409b
AK		 358/* 1-operand, using src2 (for MUL/DIV r/m) */
359#define FASTOP1SRC2(op, name) \
360 FOP_START(name) \
361 FOP1E(op, cl) \
362 FOP1E(op, cx) \
363 FOP1E(op, ecx) \
364 ON64(FOP1E(op, rcx)) \
365 FOP_END
366
b8c0b6ae
AK		 367/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
368#define FASTOP1SRC2EX(op, name) \
369 FOP_START(name) \
370 FOP1EEX(op, cl) \
371 FOP1EEX(op, cx) \
372 FOP1EEX(op, ecx) \
373 ON64(FOP1EEX(op, rcx)) \
374 FOP_END
375
f7857f35 376#define FOP2E(op, dst, src) \
d99a6ce7
JP		 377 __FOP_FUNC(#op "_" #dst "_" #src) \
378 #op " %" #src ", %" #dst " \n\t" \
379 __FOP_RET(#op "_" #dst "_" #src)
f7857f35
AK		 380
381#define FASTOP2(op) \
382 FOP_START(op) \
017da7b6
AK		 383 FOP2E(op##b, al, dl) \
384 FOP2E(op##w, ax, dx) \
385 FOP2E(op##l, eax, edx) \
386 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 387 FOP_END
388
11c363ba
AK		 389/* 2 operand, word only */
390#define FASTOP2W(op) \
391 FOP_START(op) \
392 FOPNOP() \
017da7b6
AK		 393 FOP2E(op##w, ax, dx) \
394 FOP2E(op##l, eax, edx) \
395 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 396 FOP_END
397
007a3b54
AK		 398/* 2 operand, src is CL */
399#define FASTOP2CL(op) \
400 FOP_START(op) \
401 FOP2E(op##b, al, cl) \
402 FOP2E(op##w, ax, cl) \
403 FOP2E(op##l, eax, cl) \
404 ON64(FOP2E(op##q, rax, cl)) \
405 FOP_END
406
5aca3722
NA		 407/* 2 operand, src and dest are reversed */
408#define FASTOP2R(op, name) \
409 FOP_START(name) \
410 FOP2E(op##b, dl, al) \
411 FOP2E(op##w, dx, ax) \
412 FOP2E(op##l, edx, eax) \
413 ON64(FOP2E(op##q, rdx, rax)) \
414 FOP_END
415
0bdea068 416#define FOP3E(op, dst, src, src2) \
d99a6ce7
JP		 417 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
418 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\
419 __FOP_RET(#op "_" #dst "_" #src "_" #src2)
0bdea068
AK		 420
421/* 3-operand, word-only, src2=cl */
422#define FASTOP3WCL(op) \
423 FOP_START(op) \
424 FOPNOP() \
017da7b6
AK		 425 FOP3E(op##w, ax, dx, cl) \
426 FOP3E(op##l, eax, edx, cl) \
427 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 428 FOP_END
429
9ae9feba 430/* Special case for SETcc - 1 instruction per cc */
1482a082
JP		 431#define FOP_SETCC(op) \
432 ".align 4 \n\t" \
433 ".type " #op ", @function \n\t" \
434 #op ": \n\t" \
435 #op " %al \n\t" \
d99a6ce7 436 __FOP_RET(#op)
9ae9feba 437
f26e6016
JP		 438asm(".pushsection .fixup, \"ax\"\n"
439 ".global kvm_fastop_exception \n"
440 "kvm_fastop_exception: xor %esi, %esi; ret\n"
441 ".popsection");
b8c0b6ae 442
9ae9feba
AK		 443FOP_START(setcc)
444FOP_SETCC(seto)
445FOP_SETCC(setno)
446FOP_SETCC(setc)
447FOP_SETCC(setnc)
448FOP_SETCC(setz)
449FOP_SETCC(setnz)
450FOP_SETCC(setbe)
451FOP_SETCC(setnbe)
452FOP_SETCC(sets)
453FOP_SETCC(setns)
454FOP_SETCC(setp)
455FOP_SETCC(setnp)
456FOP_SETCC(setl)
457FOP_SETCC(setnl)
458FOP_SETCC(setle)
459FOP_SETCC(setnle)
460FOP_END;
461
d99a6ce7
JP		 462FOP_START(salc)
463FOP_FUNC(salc)
464"pushf; sbb %al, %al; popf \n\t"
465FOP_RET(salc)
326f578f
PB		 466FOP_END;
467
aabba3c6
RK		 468/*
469 * XXX: inoutclob user must know where the argument is being expanded.
e9666d10 470 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault.
aabba3c6
RK		 471 */
472#define asm_safe(insn, inoutclob...) \
473({ \
474 int _fault = 0; \
475 \
476 asm volatile("1:" insn "\n" \
477 "2:\n" \
478 ".pushsection .fixup, \"ax\"\n" \
479 "3: movl $1, %[_fault]\n" \
480 " jmp 2b\n" \
481 ".popsection\n" \
482 _ASM_EXTABLE(1b, 3b) \
483 : [_fault] "+qm"(_fault) inoutclob ); \
484 \
485 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
486})
487
8a76d7f2
JR		 488static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
489 enum x86_intercept intercept,
490 enum x86_intercept_stage stage)
491{
492 struct x86_instruction_info info = {
493 .intercept = intercept,
9dac77fa
AK		 494 .rep_prefix = ctxt->rep_prefix,
495 .modrm_mod = ctxt->modrm_mod,
496 .modrm_reg = ctxt->modrm_reg,
497 .modrm_rm = ctxt->modrm_rm,
498 .src_val = ctxt->src.val64,
6cbc5f5a 499 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 500 .src_bytes = ctxt->src.bytes,
501 .dst_bytes = ctxt->dst.bytes,
502 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 503 .next_rip = ctxt->eip,
504 };
505
2953538e 506 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 507}
508
f47cfa31
AK		 509static void assign_masked(ulong *dest, ulong src, ulong mask)
510{
511 *dest = (*dest & ~mask) | (src & mask);
512}
513
6fd8e127
NA		 514static void assign_register(unsigned long *reg, u64 val, int bytes)
515{
516 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
517 switch (bytes) {
518 case 1:
519 *(u8 *)reg = (u8)val;
520 break;
521 case 2:
522 *(u16 *)reg = (u16)val;
523 break;
524 case 4:
525 *reg = (u32)val;
526 break; /* 64b: zero-extend */
527 case 8:
528 *reg = val;
529 break;
530 }
531}
532
9dac77fa 533static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 534{
9dac77fa 535 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 536}
537
f47cfa31
AK		 538static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
539{
540 u16 sel;
541 struct desc_struct ss;
542
543 if (ctxt->mode == X86EMUL_MODE_PROT64)
544 return ~0UL;
545 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
546 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
547}
548
612e89f0
AK		 549static int stack_size(struct x86_emulate_ctxt *ctxt)
550{
551 return (__fls(stack_mask(ctxt)) + 1) >> 3;
552}
553
6aa8b732 554/* Access/update address held in a register, based on addressing mode. */
e4706772 555static inline unsigned long
9dac77fa 556address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 557{
9dac77fa 558 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 559 return reg;
560 else
9dac77fa 561 return reg & ad_mask(ctxt);
e4706772
HH		 562}
563
564static inline unsigned long
01485a22 565register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 566{
01485a22 567 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 568}
569
5ad105e5
AK		 570static void masked_increment(ulong *reg, ulong mask, int inc)
571{
572 assign_masked(reg, *reg + inc, mask);
573}
574
7a957275 575static inline void
01485a22 576register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 577{
ee122a71 578 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 579
ee122a71 580 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 581}
582
583static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
584{
dd856efa 585 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 586}
6aa8b732 587
56697687
AK		 588static u32 desc_limit_scaled(struct desc_struct *desc)
589{
590 u32 limit = get_desc_limit(desc);
591
592 return desc->g ? (limit << 12) | 0xfff : limit;
593}
594
7b105ca2 595static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 596{
597 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
598 return 0;
599
7b105ca2 600 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 601}
602
35d3d4a1
AK		 603static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
604 u32 error, bool valid)
54b8486f 605{
e0ad0b47 606 WARN_ON(vec > 0x1f);
da9cb575
AK		 607 ctxt->exception.vector = vec;
608 ctxt->exception.error_code = error;
609 ctxt->exception.error_code_valid = valid;
35d3d4a1 610 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 611}
612
3b88e41a
JR		 613static int emulate_db(struct x86_emulate_ctxt *ctxt)
614{
615 return emulate_exception(ctxt, DB_VECTOR, 0, false);
616}
617
35d3d4a1 618static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 619{
35d3d4a1 620 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 621}
622
618ff15d
AK		 623static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
624{
625 return emulate_exception(ctxt, SS_VECTOR, err, true);
626}
627
35d3d4a1 628static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 629{
35d3d4a1 630 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 631}
632
35d3d4a1 633static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 634{
35d3d4a1 635 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 636}
637
34d1f490
AK		 638static int emulate_de(struct x86_emulate_ctxt *ctxt)
639{
35d3d4a1 640 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 641}
642
1253791d
AK		 643static int emulate_nm(struct x86_emulate_ctxt *ctxt)
644{
645 return emulate_exception(ctxt, NM_VECTOR, 0, false);
646}
647
1aa36616
AK		 648static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
649{
650 u16 selector;
651 struct desc_struct desc;
652
653 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
654 return selector;
655}
656
657static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
658 unsigned seg)
659{
660 u16 dummy;
661 u32 base3;
662 struct desc_struct desc;
663
664 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
665 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
666}
667
f0ed4760
SC		 668static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
669{
670 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
671}
672
673static inline bool emul_is_noncanonical_address(u64 la,
674 struct x86_emulate_ctxt *ctxt)
675{
676 return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
677}
678
1c11b376
AK		 679/*
680 * x86 defines three classes of vector instructions: explicitly
681 * aligned, explicitly unaligned, and the rest, which change behaviour
682 * depending on whether they're AVX encoded or not.
683 *
684 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 685 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
686 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 687 */
d3fe959f 688static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 689{
48520187 690 u64 alignment = ctxt->d & AlignMask;
1c11b376 691
1c11b376 692 if (likely(size < 16))
d3fe959f 693 return 1;
1c11b376 694
48520187
RK		 695 switch (alignment) {
696 case Unaligned:
697 case Avx:
d3fe959f 698 return 1;
48520187 699 case Aligned16:
d3fe959f 700 return 16;
48520187
RK		 701 case Aligned:
702 default:
d3fe959f 703 return size;
48520187 704 }
1c11b376
AK		 705}
706
d09155d2
PB		 707static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
708 struct segmented_address addr,
709 unsigned *max_size, unsigned size,
710 bool write, bool fetch,
d50eaa18 711 enum x86emul_mode mode, ulong *linear)
52fd8b44 712{
618ff15d
AK		 713 struct desc_struct desc;
714 bool usable;
52fd8b44 715 ulong la;
618ff15d 716 u32 lim;
1aa36616 717 u16 sel;
fd8cb433 718 u8 va_bits;
52fd8b44 719
7b105ca2 720 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 721 *max_size = 0;
d50eaa18 722 switch (mode) {
618ff15d 723 case X86EMUL_MODE_PROT64:
0c1d77f4 724 *linear = la;
fd8cb433
YZ		 725 va_bits = ctxt_virt_addr_bits(ctxt);
726 if (get_canonical(la, va_bits) != la)
abc7d8a4 727 goto bad;
fd56e154 728
fd8cb433 729 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
fd56e154
PB		 730 if (size > *max_size)
731 goto bad;
618ff15d
AK		 732 break;
733 default:
0c1d77f4 734 *linear = la = (u32)la;
1aa36616
AK		 735 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
736 addr.seg);
618ff15d
AK		 737 if (!usable)
738 goto bad;
58b7825b
GN		 739 /* code segment in protected mode or read-only data segment */
740 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
741 || !(desc.type & 2)) && write)
618ff15d
AK		 742 goto bad;
743 /* unreadable code segment */
3d9b938e 744 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 745 goto bad;
746 lim = desc_limit_scaled(&desc);
997b0412 747 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 748 /* expand-down segment */
fd56e154 749 if (addr.ea <= lim)
618ff15d
AK		 750 goto bad;
751 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 752 }
997b0412
PB		 753 if (addr.ea > lim)
754 goto bad;
bac15531
NA		 755 if (lim == 0xffffffff)
756 *max_size = ~0u;
757 else {
758 *max_size = (u64)lim + 1 - addr.ea;
759 if (size > *max_size)
760 goto bad;
761 }
618ff15d
AK		 762 break;
763 }
d3fe959f 764 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 765 return emulate_gp(ctxt, 0);
52fd8b44 766 return X86EMUL_CONTINUE;
618ff15d
AK		 767bad:
768 if (addr.seg == VCPU_SREG_SS)
3606189f 769 return emulate_ss(ctxt, 0);
618ff15d 770 else
3606189f 771 return emulate_gp(ctxt, 0);
52fd8b44
AK		 772}
773
3d9b938e
NE		 774static int linearize(struct x86_emulate_ctxt *ctxt,
775 struct segmented_address addr,
776 unsigned size, bool write,
777 ulong *linear)
778{
fd56e154 779 unsigned max_size;
d50eaa18
NA		 780 return __linearize(ctxt, addr, &max_size, size, write, false,
781 ctxt->mode, linear);
3d9b938e
NE		 782}
783
d50eaa18
NA		 784static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
785 enum x86emul_mode mode)
786{
787 ulong linear;
788 int rc;
789 unsigned max_size;
790 struct segmented_address addr = { .seg = VCPU_SREG_CS,
791 .ea = dst };
792
793 if (ctxt->op_bytes != sizeof(unsigned long))
794 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
795 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
796 if (rc == X86EMUL_CONTINUE)
797 ctxt->_eip = addr.ea;
798 return rc;
799}
800
801static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
802{
803 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 804}
805
d50eaa18
NA		 806static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
807 const struct desc_struct *cs_desc)
808{
809 enum x86emul_mode mode = ctxt->mode;
82268083 810 int rc;
d50eaa18
NA		 811
812#ifdef CONFIG_X86_64
82268083
NA		 813 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
814 if (cs_desc->l) {
815 u64 efer = 0;
d50eaa18 816
82268083
NA		 817 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
818 if (efer & EFER_LMA)
819 mode = X86EMUL_MODE_PROT64;
820 } else
821 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 822 }
823#endif
824 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
825 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 826 rc = assign_eip(ctxt, dst, mode);
827 if (rc == X86EMUL_CONTINUE)
828 ctxt->mode = mode;
829 return rc;
d50eaa18
NA		 830}
831
832static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
833{
834 return assign_eip_near(ctxt, ctxt->_eip + rel);
835}
3d9b938e 836
79367a65
PB		 837static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear,
838 void *data, unsigned size)
839{
3c9fa24c 840 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 841}
842
843static int linear_write_system(struct x86_emulate_ctxt *ctxt,
844 ulong linear, void *data,
845 unsigned int size)
846{
3c9fa24c 847 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true);
79367a65
PB		 848}
849
3ca3ac4d
AK		 850static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
851 struct segmented_address addr,
852 void *data,
853 unsigned size)
854{
9fa088f4
AK		 855 int rc;
856 ulong linear;
857
83b8795a 858 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 859 if (rc != X86EMUL_CONTINUE)
860 return rc;
3c9fa24c 861 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false);
3ca3ac4d
AK		 862}
863
129a72a0
SR		 864static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
865 struct segmented_address addr,
866 void *data,
867 unsigned int size)
868{
869 int rc;
870 ulong linear;
871
872 rc = linearize(ctxt, addr, size, true, &linear);
873 if (rc != X86EMUL_CONTINUE)
874 return rc;
3c9fa24c 875 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false);
129a72a0
SR		 876}
877
807941b1 878/*
285ca9e9 879 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 880 * boundary if they are not in fetch_cache yet.
881 */
9506d57d 882static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 883{
62266869 884 int rc;
fd56e154 885 unsigned size, max_size;
285ca9e9 886 unsigned long linear;
17052f16 887 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 888 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 889 .ea = ctxt->eip + cur_size };
890
fd56e154
PB		 891 /*
892 * We do not know exactly how many bytes will be needed, and
893 * __linearize is expensive, so fetch as much as possible. We
894 * just have to avoid going beyond the 15 byte limit, the end
895 * of the segment, or the end of the page.
896 *
897 * __linearize is called with size 0 so that it does not do any
898 * boundary check itself. Instead, we use max_size to check
899 * against op_size.
900 */
d50eaa18
NA		 901 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
902 &linear);
719d5a9b
PB		 903 if (unlikely(rc != X86EMUL_CONTINUE))
904 return rc;
905
fd56e154 906 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 907 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 908
909 /*
910 * One instruction can only straddle two pages,
911 * and one has been loaded at the beginning of
912 * x86_decode_insn. So, if not enough bytes
913 * still, we must have hit the 15-byte boundary.
914 */
915 if (unlikely(size < op_size))
fd56e154
PB		 916 return emulate_gp(ctxt, 0);
917
17052f16 918 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 919 size, &ctxt->exception);
920 if (unlikely(rc != X86EMUL_CONTINUE))
921 return rc;
17052f16 922 ctxt->fetch.end += size;
3e2815e9 923 return X86EMUL_CONTINUE;
62266869
AK		 924}
925
9506d57d
PB		 926static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
927 unsigned size)
62266869 928{
08da44ae
NA		 929 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
930
931 if (unlikely(done_size < size))
932 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 933 else
934 return X86EMUL_CONTINUE;
62266869
AK		 935}
936
67cbc90d 937/* Fetch next part of the instruction being emulated. */
e85a1085 938#define insn_fetch(_type, _ctxt) \
9506d57d 939({ _type _x; \
9506d57d
PB		 940 \
941 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 942 if (rc != X86EMUL_CONTINUE) \
943 goto done; \
9506d57d 944 ctxt->_eip += sizeof(_type); \
8616abc2 945 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
17052f16 946 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 947 _x; \
67cbc90d
TY		 948})
949
807941b1 950#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 951({ \
9506d57d 952 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 953 if (rc != X86EMUL_CONTINUE) \
954 goto done; \
9506d57d 955 ctxt->_eip += (_size); \
17052f16
PB		 956 memcpy(_arr, ctxt->fetch.ptr, _size); \
957 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 958})
959
1e3c5cb0
RR		 960/*
961 * Given the 'reg' portion of a ModRM byte, and a register block, return a
962 * pointer into the block that addresses the relevant register.
963 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
964 */
dd856efa 965static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 966 int byteop)
6aa8b732
AK		 967{
968 void *p;
aa9ac1a6 969 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 970
6aa8b732 971 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 972 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
973 else
974 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 975 return p;
976}
977
978static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 979 struct segmented_address addr,
6aa8b732
AK		 980 u16 *size, unsigned long *address, int op_bytes)
981{
982 int rc;
983
984 if (op_bytes == 2)
985 op_bytes = 3;
986 *address = 0;
3ca3ac4d 987 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 988 if (rc != X86EMUL_CONTINUE)
6aa8b732 989 return rc;
30b31ab6 990 addr.ea += 2;
3ca3ac4d 991 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 992 return rc;
993}
994
34b77652
AK		 995FASTOP2(add);
996FASTOP2(or);
997FASTOP2(adc);
998FASTOP2(sbb);
999FASTOP2(and);
1000FASTOP2(sub);
1001FASTOP2(xor);
1002FASTOP2(cmp);
1003FASTOP2(test);
1004
b9fa409b
AK		 1005FASTOP1SRC2(mul, mul_ex);
1006FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 1007FASTOP1SRC2EX(div, div_ex);
1008FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 1009
34b77652
AK		 1010FASTOP3WCL(shld);
1011FASTOP3WCL(shrd);
1012
1013FASTOP2W(imul);
1014
1015FASTOP1(not);
1016FASTOP1(neg);
1017FASTOP1(inc);
1018FASTOP1(dec);
1019
1020FASTOP2CL(rol);
1021FASTOP2CL(ror);
1022FASTOP2CL(rcl);
1023FASTOP2CL(rcr);
1024FASTOP2CL(shl);
1025FASTOP2CL(shr);
1026FASTOP2CL(sar);
1027
1028FASTOP2W(bsf);
1029FASTOP2W(bsr);
1030FASTOP2W(bt);
1031FASTOP2W(bts);
1032FASTOP2W(btr);
1033FASTOP2W(btc);
1034
e47a5f5f
AK		 1035FASTOP2(xadd);
1036
5aca3722
NA		 1037FASTOP2R(cmp, cmp_r);
1038
900efe20
NA		 1039static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1040{
1041 /* If src is zero, do not writeback, but update flags */
1042 if (ctxt->src.val == 0)
1043 ctxt->dst.type = OP_NONE;
1044 return fastop(ctxt, em_bsf);
1045}
1046
1047static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1048{
1049 /* If src is zero, do not writeback, but update flags */
1050 if (ctxt->src.val == 0)
1051 ctxt->dst.type = OP_NONE;
1052 return fastop(ctxt, em_bsr);
1053}
1054
cb7390fe 1055static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1056{
9ae9feba
AK		 1057 u8 rc;
1058 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1059
9ae9feba 1060 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1a29b5b7
PZ		 1061 asm("push %[flags]; popf; " CALL_NOSPEC
1062 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
9ae9feba 1063 return rc;
bbe9abbd
NK		 1064}
1065
91ff3cb4
AK		 1066static void fetch_register_operand(struct operand *op)
1067{
1068 switch (op->bytes) {
1069 case 1:
1070 op->val = *(u8 *)op->addr.reg;
1071 break;
1072 case 2:
1073 op->val = *(u16 *)op->addr.reg;
1074 break;
1075 case 4:
1076 op->val = *(u32 *)op->addr.reg;
1077 break;
1078 case 8:
1079 op->val = *(u64 *)op->addr.reg;
1080 break;
1081 }
1082}
1083
a7baead7
SC		 1084static void emulator_get_fpu(void)
1085{
1086 fpregs_lock();
1087
1088 fpregs_assert_state_consistent();
1089 if (test_thread_flag(TIF_NEED_FPU_LOAD))
1090 switch_fpu_return();
1091}
1092
1093static void emulator_put_fpu(void)
1094{
1095 fpregs_unlock();
1096}
1097
c0a21c3f 1098static void read_sse_reg(sse128_t *data, int reg)
1253791d 1099{
a7baead7 1100 emulator_get_fpu();
1253791d 1101 switch (reg) {
89a87c67
MK		 1102 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1103 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1104 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1105 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1106 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1107 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1108 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1109 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1110#ifdef CONFIG_X86_64
89a87c67
MK		 1111 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1112 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1113 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1114 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1115 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1116 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1117 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1118 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1119#endif
1120 default: BUG();
1121 }
a7baead7 1122 emulator_put_fpu();
1253791d
AK		 1123}
1124
c0a21c3f 1125static void write_sse_reg(sse128_t *data, int reg)
1253791d 1126{
a7baead7 1127 emulator_get_fpu();
1253791d 1128 switch (reg) {
89a87c67
MK		 1129 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1130 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1131 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1132 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1133 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1134 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1135 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1136 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1137#ifdef CONFIG_X86_64
89a87c67
MK		 1138 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1139 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1140 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1141 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1142 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1143 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1144 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1145 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1146#endif
1147 default: BUG();
1148 }
a7baead7 1149 emulator_put_fpu();
1253791d
AK		 1150}
1151
c0a21c3f 1152static void read_mmx_reg(u64 *data, int reg)
cbe2c9d3 1153{
a7baead7 1154 emulator_get_fpu();
cbe2c9d3
AK		 1155 switch (reg) {
1156 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1157 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1158 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1159 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1160 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1161 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1162 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1163 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1164 default: BUG();
1165 }
a7baead7 1166 emulator_put_fpu();
cbe2c9d3
AK		 1167}
1168
c0a21c3f 1169static void write_mmx_reg(u64 *data, int reg)
cbe2c9d3 1170{
a7baead7 1171 emulator_get_fpu();
cbe2c9d3
AK		 1172 switch (reg) {
1173 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1174 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1175 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1176 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1177 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1178 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1179 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1180 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1181 default: BUG();
1182 }
a7baead7 1183 emulator_put_fpu();
cbe2c9d3
AK		 1184}
1185
045a282c
GN		 1186static int em_fninit(struct x86_emulate_ctxt *ctxt)
1187{
1188 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1189 return emulate_nm(ctxt);
1190
a7baead7 1191 emulator_get_fpu();
045a282c 1192 asm volatile("fninit");
a7baead7 1193 emulator_put_fpu();
045a282c
GN		 1194 return X86EMUL_CONTINUE;
1195}
1196
1197static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1198{
1199 u16 fcw;
1200
1201 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1202 return emulate_nm(ctxt);
1203
a7baead7 1204 emulator_get_fpu();
045a282c 1205 asm volatile("fnstcw %0": "+m"(fcw));
a7baead7 1206 emulator_put_fpu();
045a282c 1207
045a282c
GN		 1208 ctxt->dst.val = fcw;
1209
1210 return X86EMUL_CONTINUE;
1211}
1212
1213static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1214{
1215 u16 fsw;
1216
1217 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1218 return emulate_nm(ctxt);
1219
a7baead7 1220 emulator_get_fpu();
045a282c 1221 asm volatile("fnstsw %0": "+m"(fsw));
a7baead7 1222 emulator_put_fpu();
045a282c 1223
045a282c
GN		 1224 ctxt->dst.val = fsw;
1225
1226 return X86EMUL_CONTINUE;
1227}
1228
1253791d 1229static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1230 struct operand *op)
3c118e24 1231{
9dac77fa 1232 unsigned reg = ctxt->modrm_reg;
33615aa9 1233
9dac77fa
AK		 1234 if (!(ctxt->d & ModRM))
1235 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1236
9dac77fa 1237 if (ctxt->d & Sse) {
1253791d
AK		 1238 op->type = OP_XMM;
1239 op->bytes = 16;
1240 op->addr.xmm = reg;
c0a21c3f 1241 read_sse_reg(&op->vec_val, reg);
1253791d
AK		 1242 return;
1243 }
cbe2c9d3
AK		 1244 if (ctxt->d & Mmx) {
1245 reg &= 7;
1246 op->type = OP_MM;
1247 op->bytes = 8;
1248 op->addr.mm = reg;
1249 return;
1250 }
1253791d 1251
3c118e24 1252 op->type = OP_REG;
6d4d85ec
GN		 1253 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1254 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1255
91ff3cb4 1256 fetch_register_operand(op);
3c118e24
AK		 1257 op->orig_val = op->val;
1258}
1259
a6e3407b
AK		 1260static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1261{
1262 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1263 ctxt->modrm_seg = VCPU_SREG_SS;
1264}
1265
1c73ef66 1266static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1267 struct operand *op)
1c73ef66 1268{
1c73ef66 1269 u8 sib;
02357bdc 1270 int index_reg, base_reg, scale;
3e2815e9 1271 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1272 ulong modrm_ea = 0;
1c73ef66 1273
02357bdc
BD		 1274 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1275 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1276 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1277
02357bdc 1278 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1279 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1280 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1281 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1282
9b88ae99 1283 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1284 op->type = OP_REG;
9dac77fa 1285 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1286 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1287 ctxt->d & ByteOp);
9dac77fa 1288 if (ctxt->d & Sse) {
1253791d
AK		 1289 op->type = OP_XMM;
1290 op->bytes = 16;
9dac77fa 1291 op->addr.xmm = ctxt->modrm_rm;
c0a21c3f 1292 read_sse_reg(&op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1293 return rc;
1294 }
cbe2c9d3
AK		 1295 if (ctxt->d & Mmx) {
1296 op->type = OP_MM;
1297 op->bytes = 8;
bdc90722 1298 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1299 return rc;
1300 }
2dbd0dd7 1301 fetch_register_operand(op);
1c73ef66
AK		 1302 return rc;
1303 }
1304
2dbd0dd7
AK		 1305 op->type = OP_MEM;
1306
9dac77fa 1307 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1308 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1309 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1310 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1311 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1312
1313 /* 16-bit ModR/M decode. */
9dac77fa 1314 switch (ctxt->modrm_mod) {
1c73ef66 1315 case 0:
9dac77fa 1316 if (ctxt->modrm_rm == 6)
e85a1085 1317 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1318 break;
1319 case 1:
e85a1085 1320 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1321 break;
1322 case 2:
e85a1085 1323 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1324 break;
1325 }
9dac77fa 1326 switch (ctxt->modrm_rm) {
1c73ef66 1327 case 0:
2dbd0dd7 1328 modrm_ea += bx + si;
1c73ef66
AK		 1329 break;
1330 case 1:
2dbd0dd7 1331 modrm_ea += bx + di;
1c73ef66
AK		 1332 break;
1333 case 2:
2dbd0dd7 1334 modrm_ea += bp + si;
1c73ef66
AK		 1335 break;
1336 case 3:
2dbd0dd7 1337 modrm_ea += bp + di;
1c73ef66
AK		 1338 break;
1339 case 4:
2dbd0dd7 1340 modrm_ea += si;
1c73ef66
AK		 1341 break;
1342 case 5:
2dbd0dd7 1343 modrm_ea += di;
1c73ef66
AK		 1344 break;
1345 case 6:
9dac77fa 1346 if (ctxt->modrm_mod != 0)
2dbd0dd7 1347 modrm_ea += bp;
1c73ef66
AK		 1348 break;
1349 case 7:
2dbd0dd7 1350 modrm_ea += bx;
1c73ef66
AK		 1351 break;
1352 }
9dac77fa
AK		 1353 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1354 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1355 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1356 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1357 } else {
1358 /* 32/64-bit ModR/M decode. */
9dac77fa 1359 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1360 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1361 index_reg |= (sib >> 3) & 7;
1362 base_reg |= sib & 7;
1363 scale = sib >> 6;
1364
9dac77fa 1365 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1366 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1367 else {
dd856efa 1368 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1369 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1370 /* Increment ESP on POP [ESP] */
1371 if ((ctxt->d & IncSP) &&
1372 base_reg == VCPU_REGS_RSP)
1373 modrm_ea += ctxt->op_bytes;
a6e3407b 1374 }
dc71d0f1 1375 if (index_reg != 4)
dd856efa 1376 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1377 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1378 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1379 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1380 ctxt->rip_relative = 1;
a6e3407b
AK		 1381 } else {
1382 base_reg = ctxt->modrm_rm;
dd856efa 1383 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1384 adjust_modrm_seg(ctxt, base_reg);
1385 }
9dac77fa 1386 switch (ctxt->modrm_mod) {
1c73ef66 1387 case 1:
e85a1085 1388 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1389 break;
1390 case 2:
e85a1085 1391 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1392 break;
1393 }
1394 }
90de84f5 1395 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1396 if (ctxt->ad_bytes != 8)
1397 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1398
1c73ef66
AK		 1399done:
1400 return rc;
1401}
1402
1403static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1404 struct operand *op)
1c73ef66 1405{
3e2815e9 1406 int rc = X86EMUL_CONTINUE;
1c73ef66 1407
2dbd0dd7 1408 op->type = OP_MEM;
9dac77fa 1409 switch (ctxt->ad_bytes) {
1c73ef66 1410 case 2:
e85a1085 1411 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1412 break;
1413 case 4:
e85a1085 1414 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1415 break;
1416 case 8:
e85a1085 1417 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1418 break;
1419 }
1420done:
1421 return rc;
1422}
1423
9dac77fa 1424static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1425{
7129eeca 1426 long sv = 0, mask;
35c843c4 1427
9dac77fa 1428 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1429 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1430
9dac77fa
AK		 1431 if (ctxt->src.bytes == 2)
1432 sv = (s16)ctxt->src.val & (s16)mask;
1433 else if (ctxt->src.bytes == 4)
1434 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1435 else
1436 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1437
1c1c35ae
NA		 1438 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1439 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1440 }
ba7ff2b7
WY		 1441
1442 /* only subword offset */
9dac77fa 1443 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1444}
1445
dde7e6d1 1446static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1447 unsigned long addr, void *dest, unsigned size)
6aa8b732 1448{
dde7e6d1 1449 int rc;
9dac77fa 1450 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1451
f23b070e
XG		 1452 if (mc->pos < mc->end)
1453 goto read_cached;
6aa8b732 1454
f23b070e
XG		 1455 WARN_ON((mc->end + size) >= sizeof(mc->data));
1456
1457 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1458 &ctxt->exception);
1459 if (rc != X86EMUL_CONTINUE)
1460 return rc;
1461
1462 mc->end += size;
1463
1464read_cached:
1465 memcpy(dest, mc->data + mc->pos, size);
1466 mc->pos += size;
dde7e6d1
AK		 1467 return X86EMUL_CONTINUE;
1468}
6aa8b732 1469
3ca3ac4d
AK		 1470static int segmented_read(struct x86_emulate_ctxt *ctxt,
1471 struct segmented_address addr,
1472 void *data,
1473 unsigned size)
1474{
9fa088f4
AK		 1475 int rc;
1476 ulong linear;
1477
83b8795a 1478 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1479 if (rc != X86EMUL_CONTINUE)
1480 return rc;
7b105ca2 1481 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1482}
1483
1484static int segmented_write(struct x86_emulate_ctxt *ctxt,
1485 struct segmented_address addr,
1486 const void *data,
1487 unsigned size)
1488{
9fa088f4
AK		 1489 int rc;
1490 ulong linear;
1491
83b8795a 1492 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1493 if (rc != X86EMUL_CONTINUE)
1494 return rc;
0f65dd70
AK		 1495 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1496 &ctxt->exception);
3ca3ac4d
AK		 1497}
1498
1499static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1500 struct segmented_address addr,
1501 const void *orig_data, const void *data,
1502 unsigned size)
1503{
9fa088f4
AK		 1504 int rc;
1505 ulong linear;
1506
83b8795a 1507 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1508 if (rc != X86EMUL_CONTINUE)
1509 return rc;
0f65dd70
AK		 1510 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1511 size, &ctxt->exception);
3ca3ac4d
AK		 1512}
1513
dde7e6d1 1514static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1515 unsigned int size, unsigned short port,
1516 void *dest)
1517{
9dac77fa 1518 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1519
dde7e6d1 1520 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1521 unsigned int in_page, n;
9dac77fa 1522 unsigned int count = ctxt->rep_prefix ?
dd856efa 1523 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1524 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1525 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1526 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1527 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1528 if (n == 0)
1529 n = 1;
1530 rc->pos = rc->end = 0;
7b105ca2 1531 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1532 return 0;
1533 rc->end = n * size;
6aa8b732
AK		 1534 }
1535
e6e39f04 1536 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1537 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1538 ctxt->dst.data = rc->data + rc->pos;
1539 ctxt->dst.type = OP_MEM_STR;
1540 ctxt->dst.count = (rc->end - rc->pos) / size;
1541 rc->pos = rc->end;
1542 } else {
1543 memcpy(dest, rc->data + rc->pos, size);
1544 rc->pos += size;
1545 }
dde7e6d1
AK		 1546 return 1;
1547}
6aa8b732 1548
7f3d35fd
KW		 1549static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1550 u16 index, struct desc_struct *desc)
1551{
1552 struct desc_ptr dt;
1553 ulong addr;
1554
1555 ctxt->ops->get_idt(ctxt, &dt);
1556
1557 if (dt.size < index * 8 + 7)
1558 return emulate_gp(ctxt, index << 3 | 0x2);
1559
1560 addr = dt.address + index * 8;
0e96f31e 1561 return linear_read_system(ctxt, addr, desc, sizeof(*desc));
7f3d35fd
KW		 1562}
1563
dde7e6d1 1564static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1565 u16 selector, struct desc_ptr *dt)
1566{
0225fb50 1567 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1568 u32 base3 = 0;
7b105ca2 1569
dde7e6d1
AK		 1570 if (selector & 1 << 2) {
1571 struct desc_struct desc;
1aa36616
AK		 1572 u16 sel;
1573
0e96f31e 1574 memset(dt, 0, sizeof(*dt));
2eedcac8
NA		 1575 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1576 VCPU_SREG_LDTR))
dde7e6d1 1577 return;
e09d082c 1578
dde7e6d1 1579 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1580 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1581 } else
4bff1e86 1582 ops->get_gdt(ctxt, dt);
dde7e6d1 1583}
120df890 1584
edccda7c
NA		 1585static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1586 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1587{
1588 struct desc_ptr dt;
1589 u16 index = selector >> 3;
dde7e6d1 1590 ulong addr;
120df890 1591
7b105ca2 1592 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1593
35d3d4a1
AK		 1594 if (dt.size < index * 8 + 7)
1595 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1596
edccda7c
NA		 1597 addr = dt.address + index * 8;
1598
1599#ifdef CONFIG_X86_64
1600 if (addr >> 32 != 0) {
1601 u64 efer = 0;
1602
1603 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1604 if (!(efer & EFER_LMA))
1605 addr &= (u32)-1;
1606 }
1607#endif
1608
1609 *desc_addr_p = addr;
1610 return X86EMUL_CONTINUE;
1611}
1612
1613/* allowed just for 8 bytes segments */
1614static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1615 u16 selector, struct desc_struct *desc,
1616 ulong *desc_addr_p)
1617{
1618 int rc;
1619
1620 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1621 if (rc != X86EMUL_CONTINUE)
1622 return rc;
1623
79367a65 1624 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc));
dde7e6d1 1625}
ef65c889 1626
dde7e6d1
AK		 1627/* allowed just for 8 bytes segments */
1628static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1629 u16 selector, struct desc_struct *desc)
1630{
edccda7c 1631 int rc;
dde7e6d1 1632 ulong addr;
6aa8b732 1633
edccda7c
NA		 1634 rc = get_descriptor_ptr(ctxt, selector, &addr);
1635 if (rc != X86EMUL_CONTINUE)
1636 return rc;
6aa8b732 1637
0e96f31e 1638 return linear_write_system(ctxt, addr, desc, sizeof(*desc));
dde7e6d1 1639}
c7e75a3d 1640
2356aaeb 1641static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1642 u16 selector, int seg, u8 cpl,
3dc4bc4f 1643 enum x86_transfer_type transfer,
d1442d85 1644 struct desc_struct *desc)
dde7e6d1 1645{
869be99c 1646 struct desc_struct seg_desc, old_desc;
2356aaeb 1647 u8 dpl, rpl;
dde7e6d1
AK		 1648 unsigned err_vec = GP_VECTOR;
1649 u32 err_code = 0;
1650 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1651 ulong desc_addr;
dde7e6d1 1652 int ret;
03ebebeb 1653 u16 dummy;
e37a75a1 1654 u32 base3 = 0;
69f55cb1 1655
0e96f31e 1656 memset(&seg_desc, 0, sizeof(seg_desc));
69f55cb1 1657
f8da94e9
KW		 1658 if (ctxt->mode == X86EMUL_MODE_REAL) {
1659 /* set real mode segment descriptor (keep limit etc. for
1660 * unreal mode) */
03ebebeb 1661 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1662 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1663 goto load;
f8da94e9
KW		 1664 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1665 /* VM86 needs a clean new segment descriptor */
1666 set_desc_base(&seg_desc, selector << 4);
1667 set_desc_limit(&seg_desc, 0xffff);
1668 seg_desc.type = 3;
1669 seg_desc.p = 1;
1670 seg_desc.s = 1;
1671 seg_desc.dpl = 3;
1672 goto load;
dde7e6d1
AK		 1673 }
1674
79d5b4c3 1675 rpl = selector & 3;
79d5b4c3 1676
dde7e6d1
AK		 1677 /* TR should be in GDT only */
1678 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1679 goto exception;
1680
33ab9110
PB		 1681 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1682 if (null_selector) {
1683 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1684 goto exception;
1685
1686 if (seg == VCPU_SREG_SS) {
1687 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1688 goto exception;
1689
1690 /*
1691 * ctxt->ops->set_segment expects the CPL to be in
1692 * SS.DPL, so fake an expand-up 32-bit data segment.
1693 */
1694 seg_desc.type = 3;
1695 seg_desc.p = 1;
1696 seg_desc.s = 1;
1697 seg_desc.dpl = cpl;
1698 seg_desc.d = 1;
1699 seg_desc.g = 1;
1700 }
1701
1702 /* Skip all following checks */
dde7e6d1 1703 goto load;
33ab9110 1704 }
dde7e6d1 1705
e919464b 1706 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1707 if (ret != X86EMUL_CONTINUE)
1708 return ret;
1709
1710 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1711 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1712 GP_VECTOR;
dde7e6d1 1713
fc058680 1714 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1715 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1716 if (transfer == X86_TRANSFER_CALL_JMP)
1717 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1718 goto exception;
3dc4bc4f 1719 }
dde7e6d1
AK		 1720
1721 if (!seg_desc.p) {
1722 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1723 goto exception;
1724 }
1725
dde7e6d1 1726 dpl = seg_desc.dpl;
dde7e6d1
AK		 1727
1728 switch (seg) {
1729 case VCPU_SREG_SS:
1730 /*
1731 * segment is not a writable data segment or segment
1732 * selector's RPL != CPL or segment selector's RPL != CPL
1733 */
1734 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1735 goto exception;
6aa8b732 1736 break;
dde7e6d1
AK		 1737 case VCPU_SREG_CS:
1738 if (!(seg_desc.type & 8))
1739 goto exception;
1740
1741 if (seg_desc.type & 4) {
1742 /* conforming */
1743 if (dpl > cpl)
1744 goto exception;
1745 } else {
1746 /* nonconforming */
1747 if (rpl > cpl || dpl != cpl)
1748 goto exception;
1749 }
040c8dc8
NA		 1750 /* in long-mode d/b must be clear if l is set */
1751 if (seg_desc.d && seg_desc.l) {
1752 u64 efer = 0;
1753
1754 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1755 if (efer & EFER_LMA)
1756 goto exception;
1757 }
1758
dde7e6d1
AK		 1759 /* CS(RPL) <- CPL */
1760 selector = (selector & 0xfffc) | cpl;
6aa8b732 1761 break;
dde7e6d1
AK		 1762 case VCPU_SREG_TR:
1763 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1764 goto exception;
869be99c
AK		 1765 old_desc = seg_desc;
1766 seg_desc.type |= 2; /* busy */
1767 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1768 sizeof(seg_desc), &ctxt->exception);
1769 if (ret != X86EMUL_CONTINUE)
1770 return ret;
dde7e6d1
AK		 1771 break;
1772 case VCPU_SREG_LDTR:
1773 if (seg_desc.s || seg_desc.type != 2)
1774 goto exception;
1775 break;
1776 default: /* DS, ES, FS, or GS */
4e62417b 1777 /*
dde7e6d1
AK		 1778 * segment is not a data or readable code segment or
1779 * ((segment is a data or nonconforming code segment)
1780 * and (both RPL and CPL > DPL))
4e62417b 1781 */
dde7e6d1
AK		 1782 if ((seg_desc.type & 0xa) == 0x8 ||
1783 (((seg_desc.type & 0xc) != 0xc) &&
1784 (rpl > dpl && cpl > dpl)))
1785 goto exception;
6aa8b732 1786 break;
dde7e6d1
AK		 1787 }
1788
1789 if (seg_desc.s) {
1790 /* mark segment as accessed */
e2cefa74
NA		 1791 if (!(seg_desc.type & 1)) {
1792 seg_desc.type |= 1;
1793 ret = write_segment_descriptor(ctxt, selector,
1794 &seg_desc);
1795 if (ret != X86EMUL_CONTINUE)
1796 return ret;
1797 }
e37a75a1 1798 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
79367a65 1799 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3));
e37a75a1
NA		 1800 if (ret != X86EMUL_CONTINUE)
1801 return ret;
fd8cb433
YZ		 1802 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
1803 ((u64)base3 << 32), ctxt))
9a9abf6b 1804 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1805 }
1806load:
e37a75a1 1807 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1808 if (desc)
1809 *desc = seg_desc;
dde7e6d1
AK		 1810 return X86EMUL_CONTINUE;
1811exception:
592f0858 1812 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1813}
1814
2356aaeb
PB		 1815static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1816 u16 selector, int seg)
1817{
1818 u8 cpl = ctxt->ops->cpl(ctxt);
33ab9110
PB		 1819
1820 /*
1821 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1822 * they can load it at CPL<3 (Intel's manual says only LSS can,
1823 * but it's wrong).
1824 *
1825 * However, the Intel manual says that putting IST=1/DPL=3 in
1826 * an interrupt gate will result in SS=3 (the AMD manual instead
1827 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1828 * and only forbid it here.
1829 */
1830 if (seg == VCPU_SREG_SS && selector == 3 &&
1831 ctxt->mode == X86EMUL_MODE_PROT64)
1832 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1833
3dc4bc4f
NA		 1834 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1835 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1836}
1837
31be40b3
WY		 1838static void write_register_operand(struct operand *op)
1839{
6fd8e127 1840 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1841}
1842
fb32b1ed 1843static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1844{
fb32b1ed 1845 switch (op->type) {
dde7e6d1 1846 case OP_REG:
fb32b1ed 1847 write_register_operand(op);
6aa8b732 1848 break;
dde7e6d1 1849 case OP_MEM:
9dac77fa 1850 if (ctxt->lock_prefix)
f5f87dfb
PB		 1851 return segmented_cmpxchg(ctxt,
1852 op->addr.mem,
1853 &op->orig_val,
1854 &op->val,
1855 op->bytes);
1856 else
1857 return segmented_write(ctxt,
fb32b1ed 1858 op->addr.mem,
fb32b1ed
AK		 1859 &op->val,
1860 op->bytes);
a682e354 1861 break;
b3356bf0 1862 case OP_MEM_STR:
f5f87dfb
PB		 1863 return segmented_write(ctxt,
1864 op->addr.mem,
1865 op->data,
1866 op->bytes * op->count);
b3356bf0 1867 break;
1253791d 1868 case OP_XMM:
c0a21c3f 1869 write_sse_reg(&op->vec_val, op->addr.xmm);
1253791d 1870 break;
cbe2c9d3 1871 case OP_MM:
c0a21c3f 1872 write_mmx_reg(&op->mm_val, op->addr.mm);
cbe2c9d3 1873 break;
dde7e6d1
AK		 1874 case OP_NONE:
1875 /* no writeback */
414e6277 1876 break;
dde7e6d1 1877 default:
414e6277 1878 break;
6aa8b732 1879 }
dde7e6d1
AK		 1880 return X86EMUL_CONTINUE;
1881}
6aa8b732 1882
51ddff50 1883static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1884{
4179bb02 1885 struct segmented_address addr;
0dc8d10f 1886
5ad105e5 1887 rsp_increment(ctxt, -bytes);
dd856efa 1888 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1889 addr.seg = VCPU_SREG_SS;
1890
51ddff50
AK		 1891 return segmented_write(ctxt, addr, data, bytes);
1892}
1893
1894static int em_push(struct x86_emulate_ctxt *ctxt)
1895{
4179bb02 1896 /* Disable writeback. */
9dac77fa 1897 ctxt->dst.type = OP_NONE;
51ddff50 1898 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1899}
69f55cb1 1900
dde7e6d1 1901static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1902 void *dest, int len)
1903{
dde7e6d1 1904 int rc;
90de84f5 1905 struct segmented_address addr;
8b4caf66 1906
dd856efa 1907 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1908 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1909 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1910 if (rc != X86EMUL_CONTINUE)
1911 return rc;
1912
5ad105e5 1913 rsp_increment(ctxt, len);
dde7e6d1 1914 return rc;
8b4caf66
LV		 1915}
1916
c54fe504
TY		 1917static int em_pop(struct x86_emulate_ctxt *ctxt)
1918{
9dac77fa 1919 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1920}
1921
dde7e6d1 1922static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1923 void *dest, int len)
9de41573
GN		 1924{
1925 int rc;
dde7e6d1 1926 unsigned long val, change_mask;
0efb0440 1927 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1928 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1929
3b9be3bf 1930 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1931 if (rc != X86EMUL_CONTINUE)
1932 return rc;
9de41573 1933
0efb0440
NA		 1934 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1935 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1936 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1937 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1938
dde7e6d1
AK		 1939 switch(ctxt->mode) {
1940 case X86EMUL_MODE_PROT64:
1941 case X86EMUL_MODE_PROT32:
1942 case X86EMUL_MODE_PROT16:
1943 if (cpl == 0)
0efb0440 1944 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1945 if (cpl <= iopl)
0efb0440 1946 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1947 break;
1948 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1949 if (iopl < 3)
1950 return emulate_gp(ctxt, 0);
0efb0440 1951 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1952 break;
1953 default: /* real mode */
0efb0440 1954 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1955 break;
9de41573 1956 }
dde7e6d1
AK		 1957
1958 *(unsigned long *)dest =
1959 (ctxt->eflags & ~change_mask) | (val & change_mask);
1960
1961 return rc;
9de41573
GN		 1962}
1963
62aaa2f0
TY		 1964static int em_popf(struct x86_emulate_ctxt *ctxt)
1965{
9dac77fa
AK		 1966 ctxt->dst.type = OP_REG;
1967 ctxt->dst.addr.reg = &ctxt->eflags;
1968 ctxt->dst.bytes = ctxt->op_bytes;
1969 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1970}
1971
612e89f0
AK		 1972static int em_enter(struct x86_emulate_ctxt *ctxt)
1973{
1974 int rc;
1975 unsigned frame_size = ctxt->src.val;
1976 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1977 ulong rbp;
612e89f0
AK		 1978
1979 if (nesting_level)
1980 return X86EMUL_UNHANDLEABLE;
1981
dd856efa
AK		 1982 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1983 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
dd856efa 1986 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1987 stack_mask(ctxt));
dd856efa
AK		 1988 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1989 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1990 stack_mask(ctxt));
1991 return X86EMUL_CONTINUE;
1992}
1993
f47cfa31
AK		 1994static int em_leave(struct x86_emulate_ctxt *ctxt)
1995{
dd856efa 1996 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1997 stack_mask(ctxt));
dd856efa 1998 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1999}
2000
1cd196ea 2001static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 2002{
1cd196ea
AK		 2003 int seg = ctxt->src2.val;
2004
9dac77fa 2005 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 2006 if (ctxt->op_bytes == 4) {
2007 rsp_increment(ctxt, -2);
2008 ctxt->op_bytes = 2;
2009 }
7b262e90 2010
4487b3b4 2011 return em_push(ctxt);
7b262e90
GN		 2012}
2013
1cd196ea 2014static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 2015{
1cd196ea 2016 int seg = ctxt->src2.val;
dde7e6d1
AK		 2017 unsigned long selector;
2018 int rc;
38ba30ba 2019
3313bc4e 2020 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 2021 if (rc != X86EMUL_CONTINUE)
2022 return rc;
2023
a5457e7b
PB		 2024 if (ctxt->modrm_reg == VCPU_SREG_SS)
2025 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 2026 if (ctxt->op_bytes > 2)
2027 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 2028
7b105ca2 2029 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 2030 return rc;
38ba30ba
GN		 2031}
2032
b96a7fad 2033static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 2034{
dd856efa 2035 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 2036 int rc = X86EMUL_CONTINUE;
2037 int reg = VCPU_REGS_RAX;
38ba30ba 2038
dde7e6d1
AK		 2039 while (reg <= VCPU_REGS_RDI) {
2040 (reg == VCPU_REGS_RSP) ?
dd856efa 2041 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 2042
4487b3b4 2043 rc = em_push(ctxt);
dde7e6d1
AK		 2044 if (rc != X86EMUL_CONTINUE)
2045 return rc;
38ba30ba 2046
dde7e6d1 2047 ++reg;
38ba30ba 2048 }
38ba30ba 2049
dde7e6d1 2050 return rc;
38ba30ba
GN		 2051}
2052
62aaa2f0
TY		 2053static int em_pushf(struct x86_emulate_ctxt *ctxt)
2054{
0efb0440 2055 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 2056 return em_push(ctxt);
2057}
2058
b96a7fad 2059static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 2060{
dde7e6d1
AK		 2061 int rc = X86EMUL_CONTINUE;
2062 int reg = VCPU_REGS_RDI;
6fd8e127 2063 u32 val;
38ba30ba 2064
dde7e6d1
AK		 2065 while (reg >= VCPU_REGS_RAX) {
2066 if (reg == VCPU_REGS_RSP) {
5ad105e5 2067 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 2068 --reg;
2069 }
38ba30ba 2070
6fd8e127 2071 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 2072 if (rc != X86EMUL_CONTINUE)
2073 break;
6fd8e127 2074 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 2075 --reg;
38ba30ba 2076 }
dde7e6d1 2077 return rc;
38ba30ba
GN		 2078}
2079
dd856efa 2080static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 2081{
0225fb50 2082 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 2083 int rc;
6e154e56
MG		 2084 struct desc_ptr dt;
2085 gva_t cs_addr;
2086 gva_t eip_addr;
2087 u16 cs, eip;
6e154e56
MG		 2088
2089 /* TODO: Add limit checks */
9dac77fa 2090 ctxt->src.val = ctxt->eflags;
4487b3b4 2091 rc = em_push(ctxt);
5c56e1cf
AK		 2092 if (rc != X86EMUL_CONTINUE)
2093 return rc;
6e154e56 2094
0efb0440 2095 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2096
9dac77fa 2097 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2098 rc = em_push(ctxt);
5c56e1cf
AK		 2099 if (rc != X86EMUL_CONTINUE)
2100 return rc;
6e154e56 2101
9dac77fa 2102 ctxt->src.val = ctxt->_eip;
4487b3b4 2103 rc = em_push(ctxt);
5c56e1cf
AK		 2104 if (rc != X86EMUL_CONTINUE)
2105 return rc;
2106
4bff1e86 2107 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2108
2109 eip_addr = dt.address + (irq << 2);
2110 cs_addr = dt.address + (irq << 2) + 2;
2111
79367a65 2112 rc = linear_read_system(ctxt, cs_addr, &cs, 2);
6e154e56
MG		 2113 if (rc != X86EMUL_CONTINUE)
2114 return rc;
2115
79367a65 2116 rc = linear_read_system(ctxt, eip_addr, &eip, 2);
6e154e56
MG		 2117 if (rc != X86EMUL_CONTINUE)
2118 return rc;
2119
7b105ca2 2120 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2121 if (rc != X86EMUL_CONTINUE)
2122 return rc;
2123
9dac77fa 2124 ctxt->_eip = eip;
6e154e56
MG		 2125
2126 return rc;
2127}
2128
dd856efa
AK		 2129int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2130{
2131 int rc;
2132
2133 invalidate_registers(ctxt);
2134 rc = __emulate_int_real(ctxt, irq);
2135 if (rc == X86EMUL_CONTINUE)
2136 writeback_registers(ctxt);
2137 return rc;
2138}
2139
7b105ca2 2140static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2141{
2142 switch(ctxt->mode) {
2143 case X86EMUL_MODE_REAL:
dd856efa 2144 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2145 case X86EMUL_MODE_VM86:
2146 case X86EMUL_MODE_PROT16:
2147 case X86EMUL_MODE_PROT32:
2148 case X86EMUL_MODE_PROT64:
2149 default:
2150 /* Protected mode interrupts unimplemented yet */
2151 return X86EMUL_UNHANDLEABLE;
2152 }
2153}
2154
7b105ca2 2155static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2156{
dde7e6d1
AK		 2157 int rc = X86EMUL_CONTINUE;
2158 unsigned long temp_eip = 0;
2159 unsigned long temp_eflags = 0;
2160 unsigned long cs = 0;
0efb0440
NA		 2161 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2162 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2163 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2164 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2165 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2166 X86_EFLAGS_FIXED;
0efb0440
NA		 2167 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2168 X86_EFLAGS_VIP;
38ba30ba 2169
dde7e6d1 2170 /* TODO: Add stack limit check */
38ba30ba 2171
9dac77fa 2172 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2173
dde7e6d1
AK		 2174 if (rc != X86EMUL_CONTINUE)
2175 return rc;
38ba30ba 2176
35d3d4a1
AK		 2177 if (temp_eip & ~0xffff)
2178 return emulate_gp(ctxt, 0);
38ba30ba 2179
9dac77fa 2180 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2181
dde7e6d1
AK		 2182 if (rc != X86EMUL_CONTINUE)
2183 return rc;
38ba30ba 2184
9dac77fa 2185 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2186
dde7e6d1
AK		 2187 if (rc != X86EMUL_CONTINUE)
2188 return rc;
38ba30ba 2189
7b105ca2 2190 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2191
dde7e6d1
AK		 2192 if (rc != X86EMUL_CONTINUE)
2193 return rc;
38ba30ba 2194
9dac77fa 2195 ctxt->_eip = temp_eip;
38ba30ba 2196
9dac77fa 2197 if (ctxt->op_bytes == 4)
dde7e6d1 2198 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2199 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2200 ctxt->eflags &= ~0xffff;
2201 ctxt->eflags |= temp_eflags;
38ba30ba 2202 }
dde7e6d1
AK		 2203
2204 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2205 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2206 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2207
2208 return rc;
38ba30ba
GN		 2209}
2210
e01991e7 2211static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2212{
dde7e6d1
AK		 2213 switch(ctxt->mode) {
2214 case X86EMUL_MODE_REAL:
7b105ca2 2215 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2216 case X86EMUL_MODE_VM86:
2217 case X86EMUL_MODE_PROT16:
2218 case X86EMUL_MODE_PROT32:
2219 case X86EMUL_MODE_PROT64:
c37eda13 2220 default:
dde7e6d1
AK		 2221 /* iret from protected mode unimplemented yet */
2222 return X86EMUL_UNHANDLEABLE;
c37eda13 2223 }
c37eda13
WY		 2224}
2225
d2f62766
TY		 2226static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2227{
d2f62766 2228 int rc;
2117d539
RK		 2229 unsigned short sel;
2230 struct desc_struct new_desc;
d1442d85
NA		 2231 u8 cpl = ctxt->ops->cpl(ctxt);
2232
9dac77fa 2233 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2234
3dc4bc4f
NA		 2235 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2236 X86_TRANSFER_CALL_JMP,
d1442d85 2237 &new_desc);
d2f62766
TY		 2238 if (rc != X86EMUL_CONTINUE)
2239 return rc;
2240
d50eaa18 2241 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2117d539
RK		 2242 /* Error handling is not implemented. */
2243 if (rc != X86EMUL_CONTINUE)
2244 return X86EMUL_UNHANDLEABLE;
2245
d1442d85 2246 return rc;
d2f62766
TY		 2247}
2248
f7784046 2249static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2250{
f7784046
NA		 2251 return assign_eip_near(ctxt, ctxt->src.val);
2252}
8cdbd2c9 2253
f7784046
NA		 2254static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2255{
2256 int rc;
2257 long int old_eip;
2258
2259 old_eip = ctxt->_eip;
2260 rc = assign_eip_near(ctxt, ctxt->src.val);
2261 if (rc != X86EMUL_CONTINUE)
2262 return rc;
2263 ctxt->src.val = old_eip;
2264 rc = em_push(ctxt);
4179bb02 2265 return rc;
8cdbd2c9
LV		 2266}
2267
e0dac408 2268static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2269{
9dac77fa 2270 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2271
aaa05f24
NA		 2272 if (ctxt->dst.bytes == 16)
2273 return X86EMUL_UNHANDLEABLE;
2274
dd856efa
AK		 2275 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2276 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2277 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2278 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2279 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2280 } else {
dd856efa
AK		 2281 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2282 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2283
0efb0440 2284 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2285 }
1b30eaa8 2286 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2287}
2288
ebda02c2
TY		 2289static int em_ret(struct x86_emulate_ctxt *ctxt)
2290{
234f3ce4
NA		 2291 int rc;
2292 unsigned long eip;
2293
2294 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2295 if (rc != X86EMUL_CONTINUE)
2296 return rc;
2297
2298 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2299}
2300
e01991e7 2301static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2302{
a77ab5ea 2303 int rc;
d1442d85 2304 unsigned long eip, cs;
9e8919ae 2305 int cpl = ctxt->ops->cpl(ctxt);
2117d539 2306 struct desc_struct new_desc;
a77ab5ea 2307
d1442d85 2308 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2309 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2310 return rc;
9dac77fa 2311 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2312 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2313 return rc;
9e8919ae
NA		 2314 /* Outer-privilege level return is not implemented */
2315 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2316 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2317 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2318 X86_TRANSFER_RET,
d1442d85
NA		 2319 &new_desc);
2320 if (rc != X86EMUL_CONTINUE)
2321 return rc;
d50eaa18 2322 rc = assign_eip_far(ctxt, eip, &new_desc);
2117d539
RK		 2323 /* Error handling is not implemented. */
2324 if (rc != X86EMUL_CONTINUE)
2325 return X86EMUL_UNHANDLEABLE;
2326
a77ab5ea
AK		 2327 return rc;
2328}
2329
3261107e
BR		 2330static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2331{
2332 int rc;
2333
2334 rc = em_ret_far(ctxt);
2335 if (rc != X86EMUL_CONTINUE)
2336 return rc;
2337 rsp_increment(ctxt, ctxt->src.val);
2338 return X86EMUL_CONTINUE;
2339}
2340
e940b5c2
TY		 2341static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2342{
2343 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2344 ctxt->dst.orig_val = ctxt->dst.val;
2345 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2346 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2347 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2348 fastop(ctxt, em_cmp);
e940b5c2 2349
0efb0440 2350 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2351 /* Success: write back to memory; no update of EAX */
2352 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2353 ctxt->dst.val = ctxt->src.orig_val;
2354 } else {
2355 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2356 ctxt->src.type = OP_REG;
2357 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2358 ctxt->src.val = ctxt->dst.orig_val;
2359 /* Create write-cycle to dest by writing the same value */
37c564f2 2360 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2361 }
2362 return X86EMUL_CONTINUE;
2363}
2364
d4b4325f 2365static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2366{
d4b4325f 2367 int seg = ctxt->src2.val;
09b5f4d3
WY		 2368 unsigned short sel;
2369 int rc;
2370
9dac77fa 2371 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2372
7b105ca2 2373 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2374 if (rc != X86EMUL_CONTINUE)
2375 return rc;
2376
9dac77fa 2377 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2378 return rc;
2379}
2380
660a5d51
PB		 2381static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2382{
b68f3cc7 2383#ifdef CONFIG_X86_64
5ae78e95 2384 return ctxt->ops->guest_has_long_mode(ctxt);
b68f3cc7
SC		 2385#else
2386 return false;
2387#endif
660a5d51
PB		 2388}
2389
660a5d51
PB		 2390static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2391{
2392 desc->g = (flags >> 23) & 1;
2393 desc->d = (flags >> 22) & 1;
2394 desc->l = (flags >> 21) & 1;
2395 desc->avl = (flags >> 20) & 1;
2396 desc->p = (flags >> 15) & 1;
2397 desc->dpl = (flags >> 13) & 3;
2398 desc->s = (flags >> 12) & 1;
2399 desc->type = (flags >> 8) & 15;
2400}
2401
ed19321f
SC		 2402static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate,
2403 int n)
660a5d51
PB		 2404{
2405 struct desc_struct desc;
2406 int offset;
2407 u16 selector;
2408
ed19321f 2409 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4);
660a5d51
PB		 2410
2411 if (n < 3)
2412 offset = 0x7f84 + n * 12;
2413 else
2414 offset = 0x7f2c + (n - 3) * 12;
2415
ed19321f
SC		 2416 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2417 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2418 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset));
660a5d51
PB		 2419 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2420 return X86EMUL_CONTINUE;
2421}
2422
b68f3cc7 2423#ifdef CONFIG_X86_64
ed19321f
SC		 2424static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate,
2425 int n)
660a5d51
PB		 2426{
2427 struct desc_struct desc;
2428 int offset;
2429 u16 selector;
2430 u32 base3;
2431
2432 offset = 0x7e00 + n * 16;
2433
ed19321f
SC		 2434 selector = GET_SMSTATE(u16, smstate, offset);
2435 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8);
2436 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4));
2437 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8));
2438 base3 = GET_SMSTATE(u32, smstate, offset + 12);
660a5d51
PB		 2439
2440 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2441 return X86EMUL_CONTINUE;
2442}
b68f3cc7 2443#endif
660a5d51
PB		 2444
2445static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
fae1a3e7 2446 u64 cr0, u64 cr3, u64 cr4)
660a5d51
PB		 2447{
2448 int bad;
fae1a3e7
PB		 2449 u64 pcid;
2450
2451 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */
2452 pcid = 0;
2453 if (cr4 & X86_CR4_PCIDE) {
2454 pcid = cr3 & 0xfff;
2455 cr3 &= ~0xfff;
2456 }
2457
2458 bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2459 if (bad)
2460 return X86EMUL_UNHANDLEABLE;
660a5d51
PB		 2461
2462 /*
2463 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2464 * Then enable protected mode. However, PCID cannot be enabled
2465 * if EFER.LMA=0, so set it separately.
2466 */
2467 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2468 if (bad)
2469 return X86EMUL_UNHANDLEABLE;
2470
2471 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2472 if (bad)
2473 return X86EMUL_UNHANDLEABLE;
2474
2475 if (cr4 & X86_CR4_PCIDE) {
2476 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2477 if (bad)
2478 return X86EMUL_UNHANDLEABLE;
fae1a3e7
PB		 2479 if (pcid) {
2480 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2481 if (bad)
2482 return X86EMUL_UNHANDLEABLE;
2483 }
2484
660a5d51
PB		 2485 }
2486
2487 return X86EMUL_CONTINUE;
2488}
2489
ed19321f
SC		 2490static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt,
2491 const char *smstate)
660a5d51
PB		 2492{
2493 struct desc_struct desc;
2494 struct desc_ptr dt;
2495 u16 selector;
fae1a3e7 2496 u32 val, cr0, cr3, cr4;
660a5d51
PB		 2497 int i;
2498
ed19321f
SC		 2499 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc);
2500 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8);
2501 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED;
2502 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0);
660a5d51
PB		 2503
2504 for (i = 0; i < 8; i++)
ed19321f 2505 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4);
660a5d51 2506
ed19321f 2507 val = GET_SMSTATE(u32, smstate, 0x7fcc);
37f66bbe
ML		 2508
2509 if (ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1))
2510 return X86EMUL_UNHANDLEABLE;
2511
ed19321f 2512 val = GET_SMSTATE(u32, smstate, 0x7fc8);
37f66bbe
ML		 2513
2514 if (ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1))
2515 return X86EMUL_UNHANDLEABLE;
660a5d51 2516
ed19321f
SC		 2517 selector = GET_SMSTATE(u32, smstate, 0x7fc4);
2518 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64));
2519 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60));
2520 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c));
660a5d51
PB		 2521 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2522
ed19321f
SC		 2523 selector = GET_SMSTATE(u32, smstate, 0x7fc0);
2524 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80));
2525 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c));
2526 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78));
660a5d51
PB		 2527 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2528
ed19321f
SC		 2529 dt.address = GET_SMSTATE(u32, smstate, 0x7f74);
2530 dt.size = GET_SMSTATE(u32, smstate, 0x7f70);
660a5d51
PB		 2531 ctxt->ops->set_gdt(ctxt, &dt);
2532
ed19321f
SC		 2533 dt.address = GET_SMSTATE(u32, smstate, 0x7f58);
2534 dt.size = GET_SMSTATE(u32, smstate, 0x7f54);
660a5d51
PB		 2535 ctxt->ops->set_idt(ctxt, &dt);
2536
2537 for (i = 0; i < 6; i++) {
ed19321f 2538 int r = rsm_load_seg_32(ctxt, smstate, i);
660a5d51
PB		 2539 if (r != X86EMUL_CONTINUE)
2540 return r;
2541 }
2542
ed19321f 2543 cr4 = GET_SMSTATE(u32, smstate, 0x7f14);
660a5d51 2544
ed19321f 2545 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8));
660a5d51 2546
fae1a3e7 2547 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
660a5d51
PB		 2548}
2549
b68f3cc7 2550#ifdef CONFIG_X86_64
ed19321f
SC		 2551static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt,
2552 const char *smstate)
660a5d51
PB		 2553{
2554 struct desc_struct desc;
2555 struct desc_ptr dt;
fae1a3e7 2556 u64 val, cr0, cr3, cr4;
660a5d51
PB		 2557 u32 base3;
2558 u16 selector;
b10d92a5 2559 int i, r;
660a5d51
PB		 2560
2561 for (i = 0; i < 16; i++)
ed19321f 2562 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8);
660a5d51 2563
ed19321f
SC		 2564 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78);
2565 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED;
660a5d51 2566
ed19321f 2567 val = GET_SMSTATE(u32, smstate, 0x7f68);
37f66bbe
ML		 2568
2569 if (ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1))
2570 return X86EMUL_UNHANDLEABLE;
2571
ed19321f 2572 val = GET_SMSTATE(u32, smstate, 0x7f60);
37f66bbe
ML		 2573
2574 if (ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1))
2575 return X86EMUL_UNHANDLEABLE;
660a5d51 2576
ed19321f
SC		 2577 cr0 = GET_SMSTATE(u64, smstate, 0x7f58);
2578 cr3 = GET_SMSTATE(u64, smstate, 0x7f50);
2579 cr4 = GET_SMSTATE(u64, smstate, 0x7f48);
2580 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00));
2581 val = GET_SMSTATE(u64, smstate, 0x7ed0);
37f66bbe
ML		 2582
2583 if (ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA))
2584 return X86EMUL_UNHANDLEABLE;
660a5d51 2585
ed19321f
SC		 2586 selector = GET_SMSTATE(u32, smstate, 0x7e90);
2587 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8);
2588 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94));
2589 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98));
2590 base3 = GET_SMSTATE(u32, smstate, 0x7e9c);
660a5d51
PB		 2591 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2592
ed19321f
SC		 2593 dt.size = GET_SMSTATE(u32, smstate, 0x7e84);
2594 dt.address = GET_SMSTATE(u64, smstate, 0x7e88);
660a5d51
PB		 2595 ctxt->ops->set_idt(ctxt, &dt);
2596
ed19321f
SC		 2597 selector = GET_SMSTATE(u32, smstate, 0x7e70);
2598 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8);
2599 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74));
2600 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78));
2601 base3 = GET_SMSTATE(u32, smstate, 0x7e7c);
660a5d51
PB		 2602 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2603
ed19321f
SC		 2604 dt.size = GET_SMSTATE(u32, smstate, 0x7e64);
2605 dt.address = GET_SMSTATE(u64, smstate, 0x7e68);
660a5d51
PB		 2606 ctxt->ops->set_gdt(ctxt, &dt);
2607
fae1a3e7 2608 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
b10d92a5
PB		 2609 if (r != X86EMUL_CONTINUE)
2610 return r;
2611
660a5d51 2612 for (i = 0; i < 6; i++) {
ed19321f 2613 r = rsm_load_seg_64(ctxt, smstate, i);
660a5d51
PB		 2614 if (r != X86EMUL_CONTINUE)
2615 return r;
2616 }
2617
b10d92a5 2618 return X86EMUL_CONTINUE;
660a5d51 2619}
b68f3cc7 2620#endif
660a5d51 2621
64d60670
PB		 2622static int em_rsm(struct x86_emulate_ctxt *ctxt)
2623{
660a5d51 2624 unsigned long cr0, cr4, efer;
ed19321f 2625 char buf[512];
660a5d51
PB		 2626 u64 smbase;
2627 int ret;
2628
6ed071f0 2629 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
64d60670
PB		 2630 return emulate_ud(ctxt);
2631
ed19321f
SC		 2632 smbase = ctxt->ops->get_smbase(ctxt);
2633
2634 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf));
2635 if (ret != X86EMUL_CONTINUE)
2636 return X86EMUL_UNHANDLEABLE;
2637
9ec19493
SC		 2638 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2639 ctxt->ops->set_nmi_mask(ctxt, false);
2640
2641 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2642 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
2643
660a5d51
PB		 2644 /*
2645 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2646 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2647 * supports long mode.
660a5d51 2648 */
89651a3d
PB		 2649 if (emulator_has_longmode(ctxt)) {
2650 struct desc_struct cs_desc;
2651
2652 /* Zero CR4.PCIDE before CR0.PG. */
8f4dc2e7
SC		 2653 cr4 = ctxt->ops->get_cr(ctxt, 4);
2654 if (cr4 & X86_CR4_PCIDE)
89651a3d 2655 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
89651a3d
PB		 2656
2657 /* A 32-bit code segment is required to clear EFER.LMA. */
2658 memset(&cs_desc, 0, sizeof(cs_desc));
2659 cs_desc.type = 0xb;
2660 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2661 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2662 }
2663
2664 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2665 cr0 = ctxt->ops->get_cr(ctxt, 0);
2666 if (cr0 & X86_CR0_PE)
2667 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d 2668
8f4dc2e7
SC		 2669 if (emulator_has_longmode(ctxt)) {
2670 /* Clear CR4.PAE before clearing EFER.LME. */
2671 cr4 = ctxt->ops->get_cr(ctxt, 4);
2672 if (cr4 & X86_CR4_PAE)
2673 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2674
2675 /* And finally go back to 32-bit mode. */
2676 efer = 0;
2677 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2678 }
660a5d51 2679
0234bf88
LP		 2680 /*
2681 * Give pre_leave_smm() a chance to make ISA-specific changes to the
2682 * vCPU state (e.g. enter guest mode) before loading state from the SMM
2683 * state-save area.
2684 */
ed19321f 2685 if (ctxt->ops->pre_leave_smm(ctxt, buf))
0234bf88
LP		 2686 return X86EMUL_UNHANDLEABLE;
2687
b68f3cc7 2688#ifdef CONFIG_X86_64
660a5d51 2689 if (emulator_has_longmode(ctxt))
ed19321f 2690 ret = rsm_load_state_64(ctxt, buf);
660a5d51 2691 else
b68f3cc7 2692#endif
ed19321f 2693 ret = rsm_load_state_32(ctxt, buf);
660a5d51
PB		 2694
2695 if (ret != X86EMUL_CONTINUE) {
2696 /* FIXME: should triple fault */
2697 return X86EMUL_UNHANDLEABLE;
2698 }
2699
c5833c7a
SC		 2700 ctxt->ops->post_leave_smm(ctxt);
2701
660a5d51 2702 return X86EMUL_CONTINUE;
64d60670
PB		 2703}
2704
7b105ca2 2705static void
e66bb2cc 2706setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2707 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2708{
e66bb2cc 2709 cs->l = 0; /* will be adjusted later */
79168fd1 2710 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2711 cs->g = 1; /* 4kb granularity */
79168fd1 2712 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2713 cs->type = 0x0b; /* Read, Execute, Accessed */
2714 cs->s = 1;
2715 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2716 cs->p = 1;
2717 cs->d = 1;
99245b50 2718 cs->avl = 0;
e66bb2cc 2719
79168fd1
GN		 2720 set_desc_base(ss, 0); /* flat segment */
2721 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2722 ss->g = 1; /* 4kb granularity */
2723 ss->s = 1;
2724 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2725 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2726 ss->dpl = 0;
79168fd1 2727 ss->p = 1;
99245b50
GN		 2728 ss->l = 0;
2729 ss->avl = 0;
e66bb2cc
AP		 2730}
2731
1a18a69b
AK		 2732static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2733{
2734 u32 eax, ebx, ecx, edx;
2735
2736 eax = ecx = 0;
f91af517 2737 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
15608ed0 2738 return is_guest_vendor_intel(ebx, ecx, edx);
1a18a69b
AK		 2739}
2740
c2226fc9
SB		 2741static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2742{
0225fb50 2743 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2744 u32 eax, ebx, ecx, edx;
2745
2746 /*
2747 * syscall should always be enabled in longmode - so only become
2748 * vendor specific (cpuid) if other modes are active...
2749 */
2750 if (ctxt->mode == X86EMUL_MODE_PROT64)
2751 return true;
2752
2753 eax = 0x00000000;
2754 ecx = 0x00000000;
f91af517 2755 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
0017f93a 2756 /*
15608ed0
SC		 2757 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a
2758 * 64bit guest with a 32bit compat-app running will #UD !! While this
2759 * behaviour can be fixed (by emulating) into AMD response - CPUs of
2760 * AMD can't behave like Intel.
0017f93a 2761 */
15608ed0 2762 if (is_guest_vendor_intel(ebx, ecx, edx))
0017f93a
AK		 2763 return false;
2764
15608ed0
SC		 2765 if (is_guest_vendor_amd(ebx, ecx, edx) ||
2766 is_guest_vendor_hygon(ebx, ecx, edx))
b8f4abb6
PW		 2767 return true;
2768
2769 /*
2770 * default: (not Intel, not AMD, not Hygon), apply Intel's
2771 * stricter rules...
2772 */
c2226fc9
SB		 2773 return false;
2774}
2775
e01991e7 2776static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2777{
0225fb50 2778 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2779 struct desc_struct cs, ss;
e66bb2cc 2780 u64 msr_data;
79168fd1 2781 u16 cs_sel, ss_sel;
c2ad2bb3 2782 u64 efer = 0;
e66bb2cc
AP		 2783
2784 /* syscall is not available in real mode */
2e901c4c 2785 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2786 ctxt->mode == X86EMUL_MODE_VM86)
2787 return emulate_ud(ctxt);
e66bb2cc 2788
c2226fc9
SB		 2789 if (!(em_syscall_is_enabled(ctxt)))
2790 return emulate_ud(ctxt);
2791
c2ad2bb3 2792 ops->get_msr(ctxt, MSR_EFER, &efer);
c2226fc9
SB		 2793 if (!(efer & EFER_SCE))
2794 return emulate_ud(ctxt);
2795
5b4ce93a 2796 setup_syscalls_segments(ctxt, &cs, &ss);
717746e3 2797 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2798 msr_data >>= 32;
79168fd1
GN		 2799 cs_sel = (u16)(msr_data & 0xfffc);
2800 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2801
c2ad2bb3 2802 if (efer & EFER_LMA) {
79168fd1 2803 cs.d = 0;
e66bb2cc
AP		 2804 cs.l = 1;
2805 }
1aa36616
AK		 2806 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2807 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2808
dd856efa 2809 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2810 if (efer & EFER_LMA) {
e66bb2cc 2811#ifdef CONFIG_X86_64
6c6cb69b 2812 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2813
717746e3 2814 ops->get_msr(ctxt,
3fb1b5db
GN		 2815 ctxt->mode == X86EMUL_MODE_PROT64 ?
2816 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2817 ctxt->_eip = msr_data;
e66bb2cc 2818
717746e3 2819 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2820 ctxt->eflags &= ~msr_data;
35fd68a3 2821 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2822#endif
2823 } else {
2824 /* legacy mode */
717746e3 2825 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2826 ctxt->_eip = (u32)msr_data;
e66bb2cc 2827
0efb0440 2828 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2829 }
2830
c8401dda 2831 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
e54cfa97 2832 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2833}
2834
e01991e7 2835static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2836{
0225fb50 2837 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2838 struct desc_struct cs, ss;
8c604352 2839 u64 msr_data;
79168fd1 2840 u16 cs_sel, ss_sel;
c2ad2bb3 2841 u64 efer = 0;
8c604352 2842
7b105ca2 2843 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2844 /* inject #GP if in real mode */
35d3d4a1
AK		 2845 if (ctxt->mode == X86EMUL_MODE_REAL)
2846 return emulate_gp(ctxt, 0);
8c604352 2847
1a18a69b
AK		 2848 /*
2849 * Not recognized on AMD in compat mode (but is recognized in legacy
2850 * mode).
2851 */
f3747379 2852 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2853 && !vendor_intel(ctxt))
2854 return emulate_ud(ctxt);
2855
b2c9d43e 2856 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2857 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2858 return X86EMUL_UNHANDLEABLE;
8c604352 2859
717746e3 2860 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2861 if ((msr_data & 0xfffc) == 0x0)
2862 return emulate_gp(ctxt, 0);
8c604352 2863
5b4ce93a 2864 setup_syscalls_segments(ctxt, &cs, &ss);
0efb0440 2865 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2866 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2867 ss_sel = cs_sel + 8;
f3747379 2868 if (efer & EFER_LMA) {
79168fd1 2869 cs.d = 0;
8c604352
AP		 2870 cs.l = 1;
2871 }
2872
1aa36616
AK		 2873 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2874 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2875
717746e3 2876 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2877 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2878
717746e3 2879 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2880 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2881 (u32)msr_data;
943dea8a
SC		 2882 if (efer & EFER_LMA)
2883 ctxt->mode = X86EMUL_MODE_PROT64;
8c604352 2884
e54cfa97 2885 return X86EMUL_CONTINUE;
8c604352
AP		 2886}
2887
e01991e7 2888static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2889{
0225fb50 2890 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2891 struct desc_struct cs, ss;
234f3ce4 2892 u64 msr_data, rcx, rdx;
4668f050 2893 int usermode;
1249b96e 2894 u16 cs_sel = 0, ss_sel = 0;
4668f050 2895
a0044755
GN		 2896 /* inject #GP if in real mode or Virtual 8086 mode */
2897 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2898 ctxt->mode == X86EMUL_MODE_VM86)
2899 return emulate_gp(ctxt, 0);
4668f050 2900
7b105ca2 2901 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2902
9dac77fa 2903 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2904 usermode = X86EMUL_MODE_PROT64;
2905 else
2906 usermode = X86EMUL_MODE_PROT32;
2907
234f3ce4
NA		 2908 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2909 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2910
4668f050
AP		 2911 cs.dpl = 3;
2912 ss.dpl = 3;
717746e3 2913 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2914 switch (usermode) {
2915 case X86EMUL_MODE_PROT32:
79168fd1 2916 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2917 if ((msr_data & 0xfffc) == 0x0)
2918 return emulate_gp(ctxt, 0);
79168fd1 2919 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2920 rcx = (u32)rcx;
2921 rdx = (u32)rdx;
4668f050
AP		 2922 break;
2923 case X86EMUL_MODE_PROT64:
79168fd1 2924 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2925 if (msr_data == 0x0)
2926 return emulate_gp(ctxt, 0);
79168fd1
GN		 2927 ss_sel = cs_sel + 8;
2928 cs.d = 0;
4668f050 2929 cs.l = 1;
fd8cb433
YZ		 2930 if (emul_is_noncanonical_address(rcx, ctxt) ||
2931 emul_is_noncanonical_address(rdx, ctxt))
234f3ce4 2932 return emulate_gp(ctxt, 0);
4668f050
AP		 2933 break;
2934 }
b32a9918
NA		 2935 cs_sel |= SEGMENT_RPL_MASK;
2936 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2937
1aa36616
AK		 2938 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2939 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2940
234f3ce4
NA		 2941 ctxt->_eip = rdx;
2942 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2943
e54cfa97 2944 return X86EMUL_CONTINUE;
4668f050
AP		 2945}
2946
7b105ca2 2947static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2948{
2949 int iopl;
2950 if (ctxt->mode == X86EMUL_MODE_REAL)
2951 return false;
2952 if (ctxt->mode == X86EMUL_MODE_VM86)
2953 return true;
0efb0440 2954 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2955 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2956}
2957
9a29d449
LA		 2958#define VMWARE_PORT_VMPORT (0x5658)
2959#define VMWARE_PORT_VMRPC (0x5659)
2960
f850e2e6 2961static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2962 u16 port, u16 len)
2963{
0225fb50 2964 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2965 struct desc_struct tr_seg;
5601d05b 2966 u32 base3;
f850e2e6 2967 int r;
1aa36616 2968 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2969 unsigned mask = (1 << len) - 1;
5601d05b 2970 unsigned long base;
f850e2e6 2971
9a29d449
LA		 2972 /*
2973 * VMware allows access to these ports even if denied
2974 * by TSS I/O permission bitmap. Mimic behavior.
2975 */
2976 if (enable_vmware_backdoor &&
2977 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
2978 return true;
2979
1aa36616 2980 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2981 if (!tr_seg.p)
f850e2e6 2982 return false;
79168fd1 2983 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2984 return false;
5601d05b
GN		 2985 base = get_desc_base(&tr_seg);
2986#ifdef CONFIG_X86_64
2987 base |= ((u64)base3) << 32;
2988#endif
3c9fa24c 2989 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true);
f850e2e6
GN		 2990 if (r != X86EMUL_CONTINUE)
2991 return false;
79168fd1 2992 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2993 return false;
3c9fa24c 2994 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true);
f850e2e6
GN		 2995 if (r != X86EMUL_CONTINUE)
2996 return false;
2997 if ((perm >> bit_idx) & mask)
2998 return false;
2999 return true;
3000}
3001
3002static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 3003 u16 port, u16 len)
3004{
4fc40f07
GN		 3005 if (ctxt->perm_ok)
3006 return true;
3007
7b105ca2
TY		 3008 if (emulator_bad_iopl(ctxt))
3009 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 3010 return false;
4fc40f07
GN		 3011
3012 ctxt->perm_ok = true;
3013
f850e2e6
GN		 3014 return true;
3015}
3016
428e3d08
NA		 3017static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
3018{
3019 /*
3020 * Intel CPUs mask the counter and pointers in quite strange
3021 * manner when ECX is zero due to REP-string optimizations.
3022 */
3023#ifdef CONFIG_X86_64
3024 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
3025 return;
3026
3027 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
3028
3029 switch (ctxt->b) {
3030 case 0xa4: /* movsb */
3031 case 0xa5: /* movsd/w */
3032 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
df561f66 3033 fallthrough;
428e3d08
NA		 3034 case 0xaa: /* stosb */
3035 case 0xab: /* stosd/w */
3036 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
3037 }
3038#endif
3039}
3040
38ba30ba 3041static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3042 struct tss_segment_16 *tss)
3043{
9dac77fa 3044 tss->ip = ctxt->_eip;
38ba30ba 3045 tss->flag = ctxt->eflags;
dd856efa
AK		 3046 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
3047 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
3048 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
3049 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
3050 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
3051 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
3052 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
3053 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3054
1aa36616
AK		 3055 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3056 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3057 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3058 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3059 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 3060}
3061
3062static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3063 struct tss_segment_16 *tss)
3064{
38ba30ba 3065 int ret;
2356aaeb 3066 u8 cpl;
38ba30ba 3067
9dac77fa 3068 ctxt->_eip = tss->ip;
38ba30ba 3069 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 3070 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
3071 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
3072 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
3073 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
3074 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
3075 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
3076 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
3077 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 3078
3079 /*
3080 * SDM says that segment selectors are loaded before segment
3081 * descriptors
3082 */
1aa36616
AK		 3083 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3084 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3085 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3086 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3087 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 3088
2356aaeb
PB		 3089 cpl = tss->cs & 3;
3090
38ba30ba 3091 /*
fc058680 3092 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 3093 * it is handled in a context of new task
3094 */
d1442d85 3095 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 3096 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3097 if (ret != X86EMUL_CONTINUE)
3098 return ret;
d1442d85 3099 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3100 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3101 if (ret != X86EMUL_CONTINUE)
3102 return ret;
d1442d85 3103 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3104 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3105 if (ret != X86EMUL_CONTINUE)
3106 return ret;
d1442d85 3107 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3108 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3109 if (ret != X86EMUL_CONTINUE)
3110 return ret;
d1442d85 3111 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3112 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3113 if (ret != X86EMUL_CONTINUE)
3114 return ret;
3115
3116 return X86EMUL_CONTINUE;
3117}
3118
3119static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3120 u16 tss_selector, u16 old_tss_sel,
3121 ulong old_tss_base, struct desc_struct *new_desc)
3122{
3123 struct tss_segment_16 tss_seg;
3124 int ret;
bcc55cba 3125 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 3126
0e96f31e 3127 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3128 if (ret != X86EMUL_CONTINUE)
38ba30ba 3129 return ret;
38ba30ba 3130
7b105ca2 3131 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3132
0e96f31e 3133 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3134 if (ret != X86EMUL_CONTINUE)
38ba30ba 3135 return ret;
38ba30ba 3136
0e96f31e 3137 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3138 if (ret != X86EMUL_CONTINUE)
38ba30ba 3139 return ret;
38ba30ba
GN		 3140
3141 if (old_tss_sel != 0xffff) {
3142 tss_seg.prev_task_link = old_tss_sel;
3143
79367a65
PB		 3144 ret = linear_write_system(ctxt, new_tss_base,
3145 &tss_seg.prev_task_link,
0e96f31e 3146 sizeof(tss_seg.prev_task_link));
db297e3d 3147 if (ret != X86EMUL_CONTINUE)
38ba30ba 3148 return ret;
38ba30ba
GN		 3149 }
3150
7b105ca2 3151 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3152}
3153
3154static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3155 struct tss_segment_32 *tss)
3156{
5c7411e2 3157 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3158 tss->eip = ctxt->_eip;
38ba30ba 3159 tss->eflags = ctxt->eflags;
dd856efa
AK		 3160 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3161 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3162 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3163 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3164 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3165 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3166 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3167 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3168
1aa36616
AK		 3169 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3170 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3171 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3172 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3173 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3174 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3175}
3176
3177static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3178 struct tss_segment_32 *tss)
3179{
38ba30ba 3180 int ret;
2356aaeb 3181 u8 cpl;
38ba30ba 3182
7b105ca2 3183 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3184 return emulate_gp(ctxt, 0);
9dac77fa 3185 ctxt->_eip = tss->eip;
38ba30ba 3186 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3187
3188 /* General purpose registers */
dd856efa
AK		 3189 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3190 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3191 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3192 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3193 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3194 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3195 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3196 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3197
3198 /*
3199 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3200 * descriptors. This is important because CPL checks will
3201 * use CS.RPL.
38ba30ba 3202 */
1aa36616
AK		 3203 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3204 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3205 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3206 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3207 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3208 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3209 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3210
4cee4798
KW		 3211 /*
3212 * If we're switching between Protected Mode and VM86, we need to make
3213 * sure to update the mode before loading the segment descriptors so
3214 * that the selectors are interpreted correctly.
4cee4798 3215 */
2356aaeb 3216 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3217 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3218 cpl = 3;
3219 } else {
4cee4798 3220 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3221 cpl = tss->cs & 3;
3222 }
4cee4798 3223
38ba30ba
GN		 3224 /*
3225 * Now load segment descriptors. If fault happenes at this stage
3226 * it is handled in a context of new task
3227 */
d1442d85 3228 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3229 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3230 if (ret != X86EMUL_CONTINUE)
3231 return ret;
d1442d85 3232 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3233 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3234 if (ret != X86EMUL_CONTINUE)
3235 return ret;
d1442d85 3236 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3237 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3238 if (ret != X86EMUL_CONTINUE)
3239 return ret;
d1442d85 3240 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3241 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3242 if (ret != X86EMUL_CONTINUE)
3243 return ret;
d1442d85 3244 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3245 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3246 if (ret != X86EMUL_CONTINUE)
3247 return ret;
d1442d85 3248 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3249 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3250 if (ret != X86EMUL_CONTINUE)
3251 return ret;
d1442d85 3252 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3253 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3254
2f729b10 3255 return ret;
38ba30ba
GN		 3256}
3257
3258static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3259 u16 tss_selector, u16 old_tss_sel,
3260 ulong old_tss_base, struct desc_struct *new_desc)
3261{
3262 struct tss_segment_32 tss_seg;
3263 int ret;
bcc55cba 3264 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3265 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3266 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3267
0e96f31e 3268 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3269 if (ret != X86EMUL_CONTINUE)
38ba30ba 3270 return ret;
38ba30ba 3271
7b105ca2 3272 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3273
5c7411e2 3274 /* Only GP registers and segment selectors are saved */
79367a65
PB		 3275 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3276 ldt_sel_offset - eip_offset);
db297e3d 3277 if (ret != X86EMUL_CONTINUE)
38ba30ba 3278 return ret;
38ba30ba 3279
0e96f31e 3280 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
db297e3d 3281 if (ret != X86EMUL_CONTINUE)
38ba30ba 3282 return ret;
38ba30ba
GN		 3283
3284 if (old_tss_sel != 0xffff) {
3285 tss_seg.prev_task_link = old_tss_sel;
3286
79367a65
PB		 3287 ret = linear_write_system(ctxt, new_tss_base,
3288 &tss_seg.prev_task_link,
0e96f31e 3289 sizeof(tss_seg.prev_task_link));
db297e3d 3290 if (ret != X86EMUL_CONTINUE)
38ba30ba 3291 return ret;
38ba30ba
GN		 3292 }
3293
7b105ca2 3294 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3295}
3296
3297static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3298 u16 tss_selector, int idt_index, int reason,
e269fb21 3299 bool has_error_code, u32 error_code)
38ba30ba 3300{
0225fb50 3301 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3302 struct desc_struct curr_tss_desc, next_tss_desc;
3303 int ret;
1aa36616 3304 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3305 ulong old_tss_base =
4bff1e86 3306 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3307 u32 desc_limit;
3db176d5 3308 ulong desc_addr, dr7;
38ba30ba
GN		 3309
3310 /* FIXME: old_tss_base == ~0 ? */
3311
e919464b 3312 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3313 if (ret != X86EMUL_CONTINUE)
3314 return ret;
e919464b 3315 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3316 if (ret != X86EMUL_CONTINUE)
3317 return ret;
3318
3319 /* FIXME: check that next_tss_desc is tss */
3320
7f3d35fd
KW		 3321 /*
3322 * Check privileges. The three cases are task switch caused by...
3323 *
3324 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3325 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3326 * 3. jmp/call to TSS/task-gate: No check is performed since the
3327 * hardware checks it before exiting.
7f3d35fd
KW		 3328 */
3329 if (reason == TASK_SWITCH_GATE) {
3330 if (idt_index != -1) {
3331 /* Software interrupts */
3332 struct desc_struct task_gate_desc;
3333 int dpl;
3334
3335 ret = read_interrupt_descriptor(ctxt, idt_index,
3336 &task_gate_desc);
3337 if (ret != X86EMUL_CONTINUE)
3338 return ret;
3339
3340 dpl = task_gate_desc.dpl;
3341 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3342 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3343 }
38ba30ba
GN		 3344 }
3345
ceffb459
GN		 3346 desc_limit = desc_limit_scaled(&next_tss_desc);
3347 if (!next_tss_desc.p ||
3348 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3349 desc_limit < 0x2b)) {
592f0858 3350 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3351 }
3352
3353 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3354 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3355 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3356 }
3357
3358 if (reason == TASK_SWITCH_IRET)
3359 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3360
3361 /* set back link to prev task only if NT bit is set in eflags
fc058680 3362 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3363 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3364 old_tss_sel = 0xffff;
3365
3366 if (next_tss_desc.type & 8)
7b105ca2 3367 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3368 old_tss_base, &next_tss_desc);
3369 else
7b105ca2 3370 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3371 old_tss_base, &next_tss_desc);
0760d448
JK		 3372 if (ret != X86EMUL_CONTINUE)
3373 return ret;
38ba30ba
GN		 3374
3375 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3376 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3377
3378 if (reason != TASK_SWITCH_IRET) {
3379 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3380 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3381 }
3382
717746e3 3383 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3384 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3385
e269fb21 3386 if (has_error_code) {
9dac77fa
AK		 3387 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3388 ctxt->lock_prefix = 0;
3389 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3390 ret = em_push(ctxt);
e269fb21
JK		 3391 }
3392
3db176d5
NA		 3393 ops->get_dr(ctxt, 7, &dr7);
3394 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3395
38ba30ba
GN		 3396 return ret;
3397}
3398
3399int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3400 u16 tss_selector, int idt_index, int reason,
e269fb21 3401 bool has_error_code, u32 error_code)
38ba30ba 3402{
38ba30ba
GN		 3403 int rc;
3404
dd856efa 3405 invalidate_registers(ctxt);
9dac77fa
AK		 3406 ctxt->_eip = ctxt->eip;
3407 ctxt->dst.type = OP_NONE;
38ba30ba 3408
7f3d35fd 3409 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3410 has_error_code, error_code);
38ba30ba 3411
dd856efa 3412 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3413 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3414 writeback_registers(ctxt);
3415 }
38ba30ba 3416
a0c0ab2f 3417 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3418}
3419
f3bd64c6
GN		 3420static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3421 struct operand *op)
a682e354 3422{
0efb0440 3423 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3424
01485a22
PB		 3425 register_address_increment(ctxt, reg, df * op->bytes);
3426 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3427}
3428
7af04fc0
AK		 3429static int em_das(struct x86_emulate_ctxt *ctxt)
3430{
7af04fc0
AK		 3431 u8 al, old_al;
3432 bool af, cf, old_cf;
3433
3434 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3435 al = ctxt->dst.val;
7af04fc0
AK		 3436
3437 old_al = al;
3438 old_cf = cf;
3439 cf = false;
3440 af = ctxt->eflags & X86_EFLAGS_AF;
3441 if ((al & 0x0f) > 9 || af) {
3442 al -= 6;
3443 cf = old_cf | (al >= 250);
3444 af = true;
3445 } else {
3446 af = false;
3447 }
3448 if (old_al > 0x99 || old_cf) {
3449 al -= 0x60;
3450 cf = true;
3451 }
3452
9dac77fa 3453 ctxt->dst.val = al;
7af04fc0 3454 /* Set PF, ZF, SF */
9dac77fa
AK		 3455 ctxt->src.type = OP_IMM;
3456 ctxt->src.val = 0;
3457 ctxt->src.bytes = 1;
158de57f 3458 fastop(ctxt, em_or);
7af04fc0
AK		 3459 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3460 if (cf)
3461 ctxt->eflags |= X86_EFLAGS_CF;
3462 if (af)
3463 ctxt->eflags |= X86_EFLAGS_AF;
3464 return X86EMUL_CONTINUE;
3465}
3466
a035d5c6
PB		 3467static int em_aam(struct x86_emulate_ctxt *ctxt)
3468{
3469 u8 al, ah;
3470
3471 if (ctxt->src.val == 0)
3472 return emulate_de(ctxt);
3473
3474 al = ctxt->dst.val & 0xff;
3475 ah = al / ctxt->src.val;
3476 al %= ctxt->src.val;
3477
3478 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3479
3480 /* Set PF, ZF, SF */
3481 ctxt->src.type = OP_IMM;
3482 ctxt->src.val = 0;
3483 ctxt->src.bytes = 1;
3484 fastop(ctxt, em_or);
3485
3486 return X86EMUL_CONTINUE;
3487}
3488
7f662273
GN		 3489static int em_aad(struct x86_emulate_ctxt *ctxt)
3490{
3491 u8 al = ctxt->dst.val & 0xff;
3492 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3493
3494 al = (al + (ah * ctxt->src.val)) & 0xff;
3495
3496 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3497
f583c29b
GN		 3498 /* Set PF, ZF, SF */
3499 ctxt->src.type = OP_IMM;
3500 ctxt->src.val = 0;
3501 ctxt->src.bytes = 1;
3502 fastop(ctxt, em_or);
7f662273
GN		 3503
3504 return X86EMUL_CONTINUE;
3505}
3506
d4ddafcd
TY		 3507static int em_call(struct x86_emulate_ctxt *ctxt)
3508{
234f3ce4 3509 int rc;
d4ddafcd
TY		 3510 long rel = ctxt->src.val;
3511
3512 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3513 rc = jmp_rel(ctxt, rel);
3514 if (rc != X86EMUL_CONTINUE)
3515 return rc;
d4ddafcd
TY		 3516 return em_push(ctxt);
3517}
3518
0ef753b8
AK		 3519static int em_call_far(struct x86_emulate_ctxt *ctxt)
3520{
0ef753b8
AK		 3521 u16 sel, old_cs;
3522 ulong old_eip;
3523 int rc;
d1442d85
NA		 3524 struct desc_struct old_desc, new_desc;
3525 const struct x86_emulate_ops *ops = ctxt->ops;
3526 int cpl = ctxt->ops->cpl(ctxt);
82268083 3527 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3528
9dac77fa 3529 old_eip = ctxt->_eip;
d1442d85 3530 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3531
9dac77fa 3532 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3533 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3534 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3535 if (rc != X86EMUL_CONTINUE)
80976dbb 3536 return rc;
0ef753b8 3537
d50eaa18 3538 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3539 if (rc != X86EMUL_CONTINUE)
3540 goto fail;
0ef753b8 3541
9dac77fa 3542 ctxt->src.val = old_cs;
4487b3b4 3543 rc = em_push(ctxt);
0ef753b8 3544 if (rc != X86EMUL_CONTINUE)
d1442d85 3545 goto fail;
0ef753b8 3546
9dac77fa 3547 ctxt->src.val = old_eip;
d1442d85
NA		 3548 rc = em_push(ctxt);
3549 /* If we failed, we tainted the memory, but the very least we should
3550 restore cs */
82268083
NA		 3551 if (rc != X86EMUL_CONTINUE) {
3552 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3553 goto fail;
82268083 3554 }
d1442d85
NA		 3555 return rc;
3556fail:
3557 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3558 ctxt->mode = prev_mode;
d1442d85
NA		 3559 return rc;
3560
0ef753b8
AK		 3561}
3562
40ece7c7
AK		 3563static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3564{
40ece7c7 3565 int rc;
234f3ce4 3566 unsigned long eip;
40ece7c7 3567
234f3ce4
NA		 3568 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3569 if (rc != X86EMUL_CONTINUE)
3570 return rc;
3571 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3572 if (rc != X86EMUL_CONTINUE)
3573 return rc;
5ad105e5 3574 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3575 return X86EMUL_CONTINUE;
3576}
3577
e4f973ae
TY		 3578static int em_xchg(struct x86_emulate_ctxt *ctxt)
3579{
e4f973ae 3580 /* Write back the register source. */
9dac77fa
AK		 3581 ctxt->src.val = ctxt->dst.val;
3582 write_register_operand(&ctxt->src);
e4f973ae
TY		 3583
3584 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3585 ctxt->dst.val = ctxt->src.orig_val;
3586 ctxt->lock_prefix = 1;
e4f973ae
TY		 3587 return X86EMUL_CONTINUE;
3588}
3589
5c82aa29
AK		 3590static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3591{
9dac77fa 3592 ctxt->dst.val = ctxt->src2.val;
4d758349 3593 return fastop(ctxt, em_imul);
5c82aa29
AK		 3594}
3595
61429142
AK		 3596static int em_cwd(struct x86_emulate_ctxt *ctxt)
3597{
9dac77fa
AK		 3598 ctxt->dst.type = OP_REG;
3599 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3600 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3601 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3602
3603 return X86EMUL_CONTINUE;
3604}
3605
fb6d4d34
PB		 3606static int em_rdpid(struct x86_emulate_ctxt *ctxt)
3607{
3608 u64 tsc_aux = 0;
3609
3610 if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
a9e2e0ae 3611 return emulate_ud(ctxt);
fb6d4d34
PB		 3612 ctxt->dst.val = tsc_aux;
3613 return X86EMUL_CONTINUE;
3614}
3615
48bb5d3c
AK		 3616static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3617{
48bb5d3c
AK		 3618 u64 tsc = 0;
3619
717746e3 3620 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3621 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3622 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3623 return X86EMUL_CONTINUE;
3624}
3625
222d21aa
AK		 3626static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3627{
3628 u64 pmc;
3629
dd856efa 3630 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3631 return emulate_gp(ctxt, 0);
dd856efa
AK		 3632 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3633 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3634 return X86EMUL_CONTINUE;
3635}
3636
b9eac5f4
AK		 3637static int em_mov(struct x86_emulate_ctxt *ctxt)
3638{
54cfdb3e 3639 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3640 return X86EMUL_CONTINUE;
3641}
3642
84cffe49
BP		 3643static int em_movbe(struct x86_emulate_ctxt *ctxt)
3644{
84cffe49
BP		 3645 u16 tmp;
3646
5ae78e95 3647 if (!ctxt->ops->guest_has_movbe(ctxt))
84cffe49
BP		 3648 return emulate_ud(ctxt);
3649
3650 switch (ctxt->op_bytes) {
3651 case 2:
3652 /*
3653 * From MOVBE definition: "...When the operand size is 16 bits,
3654 * the upper word of the destination register remains unchanged
3655 * ..."
3656 *
3657 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3658 * rules so we have to do the operation almost per hand.
3659 */
3660 tmp = (u16)ctxt->src.val;
3661 ctxt->dst.val &= ~0xffffUL;
3662 ctxt->dst.val |= (unsigned long)swab16(tmp);
3663 break;
3664 case 4:
3665 ctxt->dst.val = swab32((u32)ctxt->src.val);
3666 break;
3667 case 8:
3668 ctxt->dst.val = swab64(ctxt->src.val);
3669 break;
3670 default:
592f0858 3671 BUG();
84cffe49
BP		 3672 }
3673 return X86EMUL_CONTINUE;
3674}
3675
bc00f8d2
TY		 3676static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3677{
3678 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3679 return emulate_gp(ctxt, 0);
3680
3681 /* Disable writeback. */
3682 ctxt->dst.type = OP_NONE;
3683 return X86EMUL_CONTINUE;
3684}
3685
3686static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3687{
3688 unsigned long val;
3689
3690 if (ctxt->mode == X86EMUL_MODE_PROT64)
3691 val = ctxt->src.val & ~0ULL;
3692 else
3693 val = ctxt->src.val & ~0U;
3694
3695 /* #UD condition is already handled. */
3696 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3697 return emulate_gp(ctxt, 0);
3698
3699 /* Disable writeback. */
3700 ctxt->dst.type = OP_NONE;
3701 return X86EMUL_CONTINUE;
3702}
3703
e1e210b0
TY		 3704static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3705{
1ae09954 3706 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
e1e210b0 3707 u64 msr_data;
1ae09954 3708 int r;
e1e210b0 3709
dd856efa
AK		 3710 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3711 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
1ae09954
AG		 3712 r = ctxt->ops->set_msr(ctxt, msr_index, msr_data);
3713
3714 if (r == X86EMUL_IO_NEEDED)
3715 return r;
3716
7dffecaf 3717 if (r > 0)
e1e210b0
TY		 3718 return emulate_gp(ctxt, 0);
3719
7dffecaf 3720 return r < 0 ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE;
e1e210b0
TY		 3721}
3722
3723static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3724{
1ae09954 3725 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
e1e210b0 3726 u64 msr_data;
1ae09954
AG		 3727 int r;
3728
3729 r = ctxt->ops->get_msr(ctxt, msr_index, &msr_data);
3730
3731 if (r == X86EMUL_IO_NEEDED)
3732 return r;
e1e210b0 3733
1ae09954 3734 if (r)
e1e210b0
TY		 3735 return emulate_gp(ctxt, 0);
3736
dd856efa
AK		 3737 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3738 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3739 return X86EMUL_CONTINUE;
3740}
3741
dd307d01 3742static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
1bd5f469 3743{
dd307d01
PB		 3744 if (segment > VCPU_SREG_GS &&
3745 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3746 ctxt->ops->cpl(ctxt) > 0)
3747 return emulate_gp(ctxt, 0);
1bd5f469 3748
dd307d01 3749 ctxt->dst.val = get_segment_selector(ctxt, segment);
b5bbf10e
NA		 3750 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3751 ctxt->dst.bytes = 2;
1bd5f469
TY		 3752 return X86EMUL_CONTINUE;
3753}
3754
dd307d01
PB		 3755static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3756{
3757 if (ctxt->modrm_reg > VCPU_SREG_GS)
3758 return emulate_ud(ctxt);
3759
3760 return em_store_sreg(ctxt, ctxt->modrm_reg);
3761}
3762
1bd5f469
TY		 3763static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3764{
9dac77fa 3765 u16 sel = ctxt->src.val;
1bd5f469 3766
9dac77fa 3767 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3768 return emulate_ud(ctxt);
3769
9dac77fa 3770 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3771 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3772
3773 /* Disable writeback. */
9dac77fa
AK		 3774 ctxt->dst.type = OP_NONE;
3775 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3776}
3777
dd307d01
PB		 3778static int em_sldt(struct x86_emulate_ctxt *ctxt)
3779{
3780 return em_store_sreg(ctxt, VCPU_SREG_LDTR);
3781}
3782
a14e579f
AK		 3783static int em_lldt(struct x86_emulate_ctxt *ctxt)
3784{
3785 u16 sel = ctxt->src.val;
3786
3787 /* Disable writeback. */
3788 ctxt->dst.type = OP_NONE;
3789 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3790}
3791
dd307d01
PB		 3792static int em_str(struct x86_emulate_ctxt *ctxt)
3793{
3794 return em_store_sreg(ctxt, VCPU_SREG_TR);
3795}
3796
80890006
AK		 3797static int em_ltr(struct x86_emulate_ctxt *ctxt)
3798{
3799 u16 sel = ctxt->src.val;
3800
3801 /* Disable writeback. */
3802 ctxt->dst.type = OP_NONE;
3803 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3804}
3805
38503911
AK		 3806static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3807{
9fa088f4
AK		 3808 int rc;
3809 ulong linear;
3810
9dac77fa 3811 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3812 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3813 ctxt->ops->invlpg(ctxt, linear);
38503911 3814 /* Disable writeback. */
9dac77fa 3815 ctxt->dst.type = OP_NONE;
38503911
AK		 3816 return X86EMUL_CONTINUE;
3817}
3818
2d04a05b
AK		 3819static int em_clts(struct x86_emulate_ctxt *ctxt)
3820{
3821 ulong cr0;
3822
3823 cr0 = ctxt->ops->get_cr(ctxt, 0);
3824 cr0 &= ~X86_CR0_TS;
3825 ctxt->ops->set_cr(ctxt, 0, cr0);
3826 return X86EMUL_CONTINUE;
3827}
3828
b34a8051 3829static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3830{
0f54a321 3831 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3832
26d05cc7
AK		 3833 if (rc != X86EMUL_CONTINUE)
3834 return rc;
3835
3836 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3837 ctxt->_eip = ctxt->eip;
26d05cc7 3838 /* Disable writeback. */
9dac77fa 3839 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3840 return X86EMUL_CONTINUE;
3841}
3842
96051572
AK		 3843static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3844 void (*get)(struct x86_emulate_ctxt *ctxt,
3845 struct desc_ptr *ptr))
3846{
3847 struct desc_ptr desc_ptr;
3848
ae3e61e1
PB		 3849 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3850 ctxt->ops->cpl(ctxt) > 0)
3851 return emulate_gp(ctxt, 0);
3852
96051572
AK		 3853 if (ctxt->mode == X86EMUL_MODE_PROT64)
3854 ctxt->op_bytes = 8;
3855 get(ctxt, &desc_ptr);
3856 if (ctxt->op_bytes == 2) {
3857 ctxt->op_bytes = 4;
3858 desc_ptr.address &= 0x00ffffff;
3859 }
3860 /* Disable writeback. */
3861 ctxt->dst.type = OP_NONE;
129a72a0
SR		 3862 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3863 &desc_ptr, 2 + ctxt->op_bytes);
96051572
AK		 3864}
3865
3866static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3867{
3868 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3869}
3870
3871static int em_sidt(struct x86_emulate_ctxt *ctxt)
3872{
3873 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3874}
3875
5b7f6a1e 3876static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3877{
26d05cc7
AK		 3878 struct desc_ptr desc_ptr;
3879 int rc;
3880
510425ff
AK		 3881 if (ctxt->mode == X86EMUL_MODE_PROT64)
3882 ctxt->op_bytes = 8;
9dac77fa 3883 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3884 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3885 ctxt->op_bytes);
26d05cc7
AK		 3886 if (rc != X86EMUL_CONTINUE)
3887 return rc;
9a9abf6b 3888 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
fd8cb433 3889 emul_is_noncanonical_address(desc_ptr.address, ctxt))
9a9abf6b 3890 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3891 if (lgdt)
3892 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3893 else
3894 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3895 /* Disable writeback. */
9dac77fa 3896 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3897 return X86EMUL_CONTINUE;
3898}
3899
5b7f6a1e
NA		 3900static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3901{
3902 return em_lgdt_lidt(ctxt, true);
3903}
3904
26d05cc7
AK		 3905static int em_lidt(struct x86_emulate_ctxt *ctxt)
3906{
5b7f6a1e 3907 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3908}
3909
3910static int em_smsw(struct x86_emulate_ctxt *ctxt)
3911{
ae3e61e1
PB		 3912 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3913 ctxt->ops->cpl(ctxt) > 0)
3914 return emulate_gp(ctxt, 0);
3915
32e94d06
NA		 3916 if (ctxt->dst.type == OP_MEM)
3917 ctxt->dst.bytes = 2;
9dac77fa 3918 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3919 return X86EMUL_CONTINUE;
3920}
3921
3922static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3923{
26d05cc7 3924 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3925 | (ctxt->src.val & 0x0f));
3926 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3927 return X86EMUL_CONTINUE;
3928}
3929
d06e03ad
TY		 3930static int em_loop(struct x86_emulate_ctxt *ctxt)
3931{
234f3ce4
NA		 3932 int rc = X86EMUL_CONTINUE;
3933
01485a22 3934 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3935 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3936 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3937 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3938
234f3ce4 3939 return rc;
d06e03ad
TY		 3940}
3941
3942static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3943{
234f3ce4
NA		 3944 int rc = X86EMUL_CONTINUE;
3945
dd856efa 3946 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3947 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3948
234f3ce4 3949 return rc;
d06e03ad
TY		 3950}
3951
d7841a4b
TY		 3952static int em_in(struct x86_emulate_ctxt *ctxt)
3953{
3954 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3955 &ctxt->dst.val))
3956 return X86EMUL_IO_NEEDED;
3957
3958 return X86EMUL_CONTINUE;
3959}
3960
3961static int em_out(struct x86_emulate_ctxt *ctxt)
3962{
3963 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3964 &ctxt->src.val, 1);
3965 /* Disable writeback. */
3966 ctxt->dst.type = OP_NONE;
3967 return X86EMUL_CONTINUE;
3968}
3969
f411e6cd
TY		 3970static int em_cli(struct x86_emulate_ctxt *ctxt)
3971{
3972 if (emulator_bad_iopl(ctxt))
3973 return emulate_gp(ctxt, 0);
3974
3975 ctxt->eflags &= ~X86_EFLAGS_IF;
3976 return X86EMUL_CONTINUE;
3977}
3978
3979static int em_sti(struct x86_emulate_ctxt *ctxt)
3980{
3981 if (emulator_bad_iopl(ctxt))
3982 return emulate_gp(ctxt, 0);
3983
3984 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3985 ctxt->eflags |= X86_EFLAGS_IF;
3986 return X86EMUL_CONTINUE;
3987}
3988
6d6eede4
AK		 3989static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3990{
3991 u32 eax, ebx, ecx, edx;
db2336a8
KH		 3992 u64 msr = 0;
3993
3994 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3995 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3996 ctxt->ops->cpl(ctxt)) {
3997 return emulate_gp(ctxt, 0);
3998 }
6d6eede4 3999
dd856efa
AK		 4000 eax = reg_read(ctxt, VCPU_REGS_RAX);
4001 ecx = reg_read(ctxt, VCPU_REGS_RCX);
f91af517 4002 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
dd856efa
AK		 4003 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
4004 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
4005 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
4006 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 4007 return X86EMUL_CONTINUE;
4008}
4009
98f73630
PB		 4010static int em_sahf(struct x86_emulate_ctxt *ctxt)
4011{
4012 u32 flags;
4013
0efb0440
NA		 4014 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4015 X86_EFLAGS_SF;
98f73630
PB		 4016 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
4017
4018 ctxt->eflags &= ~0xffUL;
4019 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
4020 return X86EMUL_CONTINUE;
4021}
4022
2dd7caa0
AK		 4023static int em_lahf(struct x86_emulate_ctxt *ctxt)
4024{
dd856efa
AK		 4025 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
4026 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 4027 return X86EMUL_CONTINUE;
4028}
4029
9299836e
AK		 4030static int em_bswap(struct x86_emulate_ctxt *ctxt)
4031{
4032 switch (ctxt->op_bytes) {
4033#ifdef CONFIG_X86_64
4034 case 8:
4035 asm("bswap %0" : "+r"(ctxt->dst.val));
4036 break;
4037#endif
4038 default:
4039 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
4040 break;
4041 }
4042 return X86EMUL_CONTINUE;
4043}
4044
13e457e0
NA		 4045static int em_clflush(struct x86_emulate_ctxt *ctxt)
4046{
4047 /* emulating clflush regardless of cpuid */
4048 return X86EMUL_CONTINUE;
4049}
4050
51b958e5
DE		 4051static int em_clflushopt(struct x86_emulate_ctxt *ctxt)
4052{
4053 /* emulating clflushopt regardless of cpuid */
4054 return X86EMUL_CONTINUE;
4055}
4056
2276b511
NA		 4057static int em_movsxd(struct x86_emulate_ctxt *ctxt)
4058{
4059 ctxt->dst.val = (s32) ctxt->src.val;
4060 return X86EMUL_CONTINUE;
4061}
4062
283c95d0
RK		 4063static int check_fxsr(struct x86_emulate_ctxt *ctxt)
4064{
5ae78e95 4065 if (!ctxt->ops->guest_has_fxsr(ctxt))
283c95d0
RK		 4066 return emulate_ud(ctxt);
4067
4068 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
4069 return emulate_nm(ctxt);
4070
4071 /*
4072 * Don't emulate a case that should never be hit, instead of working
4073 * around a lack of fxsave64/fxrstor64 on old compilers.
4074 */
4075 if (ctxt->mode >= X86EMUL_MODE_PROT64)
4076 return X86EMUL_UNHANDLEABLE;
4077
4078 return X86EMUL_CONTINUE;
4079}
4080
9d643f63
ND		 4081/*
4082 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
4083 * and restore MXCSR.
4084 */
4085static size_t __fxstate_size(int nregs)
4086{
4087 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
4088}
4089
4090static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
4091{
4092 bool cr4_osfxsr;
4093 if (ctxt->mode == X86EMUL_MODE_PROT64)
4094 return __fxstate_size(16);
4095
4096 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
4097 return __fxstate_size(cr4_osfxsr ? 8 : 0);
4098}
4099
283c95d0
RK		 4100/*
4101 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
4102 * 1) 16 bit mode
4103 * 2) 32 bit mode
4104 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
4105 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
4106 * save and restore
4107 * 3) 64-bit mode with REX.W prefix
4108 * - like (2), but XMM 8-15 are being saved and restored
4109 * 4) 64-bit mode without REX.W prefix
4110 * - like (3), but FIP and FDP are 64 bit
4111 *
4112 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
4113 * desired result. (4) is not emulated.
4114 *
4115 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
4116 * and FPU DS) should match.
4117 */
4118static int em_fxsave(struct x86_emulate_ctxt *ctxt)
4119{
4120 struct fxregs_state fx_state;
283c95d0
RK		 4121 int rc;
4122
4123 rc = check_fxsr(ctxt);
4124 if (rc != X86EMUL_CONTINUE)
4125 return rc;
4126
a7baead7
SC		 4127 emulator_get_fpu();
4128
283c95d0
RK		 4129 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4130
a7baead7
SC		 4131 emulator_put_fpu();
4132
283c95d0
RK		 4133 if (rc != X86EMUL_CONTINUE)
4134 return rc;
4135
9d643f63
ND		 4136 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4137 fxstate_size(ctxt));
283c95d0
RK		 4138}
4139
4d772cb8
DH		 4140/*
4141 * FXRSTOR might restore XMM registers not provided by the guest. Fill
4142 * in the host registers (via FXSAVE) instead, so they won't be modified.
4143 * (preemption has to stay disabled until FXRSTOR).
4144 *
4145 * Use noinline to keep the stack for other functions called by callers small.
4146 */
4147static noinline int fxregs_fixup(struct fxregs_state *fx_state,
4148 const size_t used_size)
4149{
4150 struct fxregs_state fx_tmp;
4151 int rc;
4152
4153 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
4154 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
4155 __fxstate_size(16) - used_size);
4156
4157 return rc;
4158}
4159
283c95d0
RK		 4160static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4161{
4162 struct fxregs_state fx_state;
4163 int rc;
9d643f63 4164 size_t size;
283c95d0
RK		 4165
4166 rc = check_fxsr(ctxt);
4167 if (rc != X86EMUL_CONTINUE)
4168 return rc;
4169
4d772cb8
DH		 4170 size = fxstate_size(ctxt);
4171 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4172 if (rc != X86EMUL_CONTINUE)
4173 return rc;
4174
a7baead7
SC		 4175 emulator_get_fpu();
4176
9d643f63 4177 if (size < __fxstate_size(16)) {
4d772cb8 4178 rc = fxregs_fixup(&fx_state, size);
9d643f63
ND		 4179 if (rc != X86EMUL_CONTINUE)
4180 goto out;
4181 }
283c95d0 4182
9d643f63
ND		 4183 if (fx_state.mxcsr >> 16) {
4184 rc = emulate_gp(ctxt, 0);
4185 goto out;
4186 }
283c95d0
RK		 4187
4188 if (rc == X86EMUL_CONTINUE)
4189 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4190
9d643f63 4191out:
a7baead7
SC		 4192 emulator_put_fpu();
4193
283c95d0
RK		 4194 return rc;
4195}
4196
02d4160f
VK		 4197static int em_xsetbv(struct x86_emulate_ctxt *ctxt)
4198{
4199 u32 eax, ecx, edx;
4200
4201 eax = reg_read(ctxt, VCPU_REGS_RAX);
4202 edx = reg_read(ctxt, VCPU_REGS_RDX);
4203 ecx = reg_read(ctxt, VCPU_REGS_RCX);
4204
4205 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax))
4206 return emulate_gp(ctxt, 0);
4207
4208 return X86EMUL_CONTINUE;
4209}
4210
cfec82cb
JR		 4211static bool valid_cr(int nr)
4212{
4213 switch (nr) {
4214 case 0:
4215 case 2 ... 4:
4216 case 8:
4217 return true;
4218 default:
4219 return false;
4220 }
4221}
4222
4223static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4224{
9dac77fa 4225 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4226 return emulate_ud(ctxt);
4227
4228 return X86EMUL_CONTINUE;
4229}
4230
4231static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4232{
9dac77fa
AK		 4233 u64 new_val = ctxt->src.val64;
4234 int cr = ctxt->modrm_reg;
c2ad2bb3 4235 u64 efer = 0;
cfec82cb
JR		 4236
4237 static u64 cr_reserved_bits[] = {
4238 0xffffffff00000000ULL,
4239 0, 0, 0, /* CR3 checked later */
4240 CR4_RESERVED_BITS,
4241 0, 0, 0,
4242 CR8_RESERVED_BITS,
4243 };
4244
4245 if (!valid_cr(cr))
4246 return emulate_ud(ctxt);
4247
4248 if (new_val & cr_reserved_bits[cr])
4249 return emulate_gp(ctxt, 0);
4250
4251 switch (cr) {
4252 case 0: {
c2ad2bb3 4253 u64 cr4;
cfec82cb
JR		 4254 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4255 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4256 return emulate_gp(ctxt, 0);
4257
717746e3
AK		 4258 cr4 = ctxt->ops->get_cr(ctxt, 4);
4259 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4260
4261 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4262 !(cr4 & X86_CR4_PAE))
4263 return emulate_gp(ctxt, 0);
4264
4265 break;
4266 }
4267 case 3: {
4268 u64 rsvd = 0;
4269
c2ad2bb3 4270 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
d1cd3ce9
YZ		 4271 if (efer & EFER_LMA) {
4272 u64 maxphyaddr;
d6500149 4273 u32 eax, ebx, ecx, edx;
d1cd3ce9 4274
d6500149
YZ		 4275 eax = 0x80000008;
4276 ecx = 0;
4277 if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
f91af517 4278 &edx, true))
d1cd3ce9
YZ		 4279 maxphyaddr = eax & 0xff;
4280 else
4281 maxphyaddr = 36;
a780a3ea
WL		 4282 rsvd = rsvd_bits(maxphyaddr, 63);
4283 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE)
208320ba 4284 rsvd &= ~X86_CR3_PCID_NOFLUSH;
d1cd3ce9 4285 }
cfec82cb
JR		 4286
4287 if (new_val & rsvd)
4288 return emulate_gp(ctxt, 0);
4289
4290 break;
4291 }
4292 case 4: {
717746e3 4293 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4294
4295 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4296 return emulate_gp(ctxt, 0);
4297
4298 break;
4299 }
4300 }
4301
4302 return X86EMUL_CONTINUE;
4303}
4304
3b88e41a
JR		 4305static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4306{
4307 unsigned long dr7;
4308
717746e3 4309 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 4310
4311 /* Check if DR7.Global_Enable is set */
4312 return dr7 & (1 << 13);
4313}
4314
4315static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4316{
9dac77fa 4317 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4318 u64 cr4;
4319
4320 if (dr > 7)
4321 return emulate_ud(ctxt);
4322
717746e3 4323 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4324 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4325 return emulate_ud(ctxt);
4326
6d2a0526
NA		 4327 if (check_dr7_gd(ctxt)) {
4328 ulong dr6;
4329
4330 ctxt->ops->get_dr(ctxt, 6, &dr6);
1fc5d194 4331 dr6 &= ~DR_TRAP_BITS;
6d2a0526
NA		 4332 dr6 |= DR6_BD | DR6_RTM;
4333 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4334 return emulate_db(ctxt);
6d2a0526 4335 }
3b88e41a
JR		 4336
4337 return X86EMUL_CONTINUE;
4338}
4339
4340static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4341{
9dac77fa
AK		 4342 u64 new_val = ctxt->src.val64;
4343 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4344
4345 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4346 return emulate_gp(ctxt, 0);
4347
4348 return check_dr_read(ctxt);
4349}
4350
01de8b09
JR		 4351static int check_svme(struct x86_emulate_ctxt *ctxt)
4352{
92ceb767 4353 u64 efer = 0;
01de8b09 4354
717746e3 4355 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4356
4357 if (!(efer & EFER_SVME))
4358 return emulate_ud(ctxt);
4359
4360 return X86EMUL_CONTINUE;
4361}
4362
4363static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4364{
dd856efa 4365 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4366
4367 /* Valid physical address? */
d4224449 4368 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4369 return emulate_gp(ctxt, 0);
4370
4371 return check_svme(ctxt);
4372}
4373
d7eb8203
JR		 4374static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4375{
717746e3 4376 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4377
717746e3 4378 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 4379 return emulate_ud(ctxt);
4380
4381 return X86EMUL_CONTINUE;
4382}
4383
8061252e
JR		 4384static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4385{
717746e3 4386 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4387 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4388
2d7921c4
AM		 4389 /*
4390 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
4391 * in Ring3 when CR4.PCE=0.
4392 */
4393 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
4394 return X86EMUL_CONTINUE;
4395
717746e3 4396 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4397 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4398 return emulate_gp(ctxt, 0);
4399
4400 return X86EMUL_CONTINUE;
4401}
4402
f6511935
JR		 4403static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4404{
9dac77fa
AK		 4405 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4406 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4407 return emulate_gp(ctxt, 0);
4408
4409 return X86EMUL_CONTINUE;
4410}
4411
4412static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4413{
9dac77fa
AK		 4414 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4415 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4416 return emulate_gp(ctxt, 0);
4417
4418 return X86EMUL_CONTINUE;
4419}
4420
73fba5f4 4421#define D(_y) { .flags = (_y) }
d40a6898
PB		 4422#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4423#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4424 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4425#define N D(NotImpl)
01de8b09 4426#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4427#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4428#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4429#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4430#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4431#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4432#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4433#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4434#define II(_f, _e, _i) \
d40a6898 4435 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4436#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4437 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4438 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4439#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4440
8d8f4e9f 4441#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4442#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4443#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4444#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4445#define I2bvIP(_f, _e, _i, _p) \
4446 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4447
fb864fbc
AK		 4448#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4449 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4450 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4451
0f54a321
NA		 4452static const struct opcode group7_rm0[] = {
4453 N,
b34a8051 4454 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4455 N, N, N, N, N, N,
4456};
4457
fd0a0d82 4458static const struct opcode group7_rm1[] = {
1c2545be
TY		 4459 DI(SrcNone | Priv, monitor),
4460 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4461 N, N, N, N, N, N,
4462};
4463
02d4160f
VK		 4464static const struct opcode group7_rm2[] = {
4465 N,
4466 II(ImplicitOps | Priv, em_xsetbv, xsetbv),
4467 N, N, N, N, N, N,
4468};
4469
fd0a0d82 4470static const struct opcode group7_rm3[] = {
1c2545be 4471 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4472 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4473 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4474 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4475 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4476 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4477 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4478 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4479};
6230f7fc 4480
fd0a0d82 4481static const struct opcode group7_rm7[] = {
d7eb8203 4482 N,
1c2545be 4483 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4484 N, N, N, N, N, N,
4485};
d67fc27a 4486
fd0a0d82 4487static const struct opcode group1[] = {
fb864fbc
AK		 4488 F(Lock, em_add),
4489 F(Lock | PageTable, em_or),
4490 F(Lock, em_adc),
4491 F(Lock, em_sbb),
4492 F(Lock | PageTable, em_and),
4493 F(Lock, em_sub),
4494 F(Lock, em_xor),
4495 F(NoWrite, em_cmp),
73fba5f4
AK		 4496};
4497
fd0a0d82 4498static const struct opcode group1A[] = {
0f89b207 4499 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4500};
4501
007a3b54
AK		 4502static const struct opcode group2[] = {
4503 F(DstMem | ModRM, em_rol),
4504 F(DstMem | ModRM, em_ror),
4505 F(DstMem | ModRM, em_rcl),
4506 F(DstMem | ModRM, em_rcr),
4507 F(DstMem | ModRM, em_shl),
4508 F(DstMem | ModRM, em_shr),
4509 F(DstMem | ModRM, em_shl),
4510 F(DstMem | ModRM, em_sar),
4511};
4512
fd0a0d82 4513static const struct opcode group3[] = {
fb864fbc
AK		 4514 F(DstMem | SrcImm | NoWrite, em_test),
4515 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4516 F(DstMem | SrcNone | Lock, em_not),
4517 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4518 F(DstXacc | Src2Mem, em_mul_ex),
4519 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4520 F(DstXacc | Src2Mem, em_div_ex),
4521 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4522};
4523
fd0a0d82 4524static const struct opcode group4[] = {
95413dc4
AK		 4525 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4526 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4527 N, N, N, N, N, N,
4528};
4529
fd0a0d82 4530static const struct opcode group5[] = {
95413dc4
AK		 4531 F(DstMem | SrcNone | Lock, em_inc),
4532 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4533 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4534 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4535 I(SrcMem | NearBranch, em_jmp_abs),
f7784046 4536 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
0f89b207 4537 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
73fba5f4
AK		 4538};
4539
fd0a0d82 4540static const struct opcode group6[] = {
dd307d01
PB		 4541 II(Prot | DstMem, em_sldt, sldt),
4542 II(Prot | DstMem, em_str, str),
a14e579f 4543 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4544 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4545 N, N, N, N,
4546};
4547
fd0a0d82 4548static const struct group_dual group7 = { {
606b1c3e
NA		 4549 II(Mov | DstMem, em_sgdt, sgdt),
4550 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4551 II(SrcMem | Priv, em_lgdt, lgdt),
4552 II(SrcMem | Priv, em_lidt, lidt),
4553 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4554 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4555 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4556}, {
0f54a321 4557 EXT(0, group7_rm0),
5ef39c71 4558 EXT(0, group7_rm1),
02d4160f
VK		 4559 EXT(0, group7_rm2),
4560 EXT(0, group7_rm3),
1c2545be
TY		 4561 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4562 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4563 EXT(0, group7_rm7),
73fba5f4
AK		 4564} };
4565
fd0a0d82 4566static const struct opcode group8[] = {
73fba5f4 4567 N, N, N, N,
11c363ba
AK		 4568 F(DstMem | SrcImmByte | NoWrite, em_bt),
4569 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4570 F(DstMem | SrcImmByte | Lock, em_btr),
4571 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4572};
4573
fb6d4d34
PB		 4574/*
4575 * The "memory" destination is actually always a register, since we come
4576 * from the register case of group9.
4577 */
4578static const struct gprefix pfx_0f_c7_7 = {
4579 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
4580};
4581
4582
fd0a0d82 4583static const struct group_dual group9 = { {
1c2545be 4584 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4 4585}, {
fb6d4d34
PB		 4586 N, N, N, N, N, N, N,
4587 GP(0, &pfx_0f_c7_7),
73fba5f4
AK		 4588} };
4589
fd0a0d82 4590static const struct opcode group11[] = {
1c2545be 4591 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4592 X7(D(Undefined)),
a4d4a7c1
AK		 4593};
4594
13e457e0 4595static const struct gprefix pfx_0f_ae_7 = {
51b958e5 4596 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N,
13e457e0
NA		 4597};
4598
4599static const struct group_dual group15 = { {
283c95d0
RK		 4600 I(ModRM | Aligned16, em_fxsave),
4601 I(ModRM | Aligned16, em_fxrstor),
4602 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4603}, {
4604 N, N, N, N, N, N, N, N,
4605} };
4606
fd0a0d82 4607static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4608 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4609};
4610
39f062ff
NA		 4611static const struct instr_dual instr_dual_0f_2b = {
4612 I(0, em_mov), N
4613};
4614
d5b77069 4615static const struct gprefix pfx_0f_2b = {
39f062ff 4616 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4617};
4618
29916968
SF		 4619static const struct gprefix pfx_0f_10_0f_11 = {
4620 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
4621};
4622
27ce8258 4623static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4624 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4625};
4626
0a37027e
AW		 4627static const struct gprefix pfx_0f_e7 = {
4628 N, I(Sse, em_mov), N, N,
4629};
4630
045a282c 4631static const struct escape escape_d9 = { {
16bebefe 4632 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4633}, {
4634 /* 0xC0 - 0xC7 */
4635 N, N, N, N, N, N, N, N,
4636 /* 0xC8 - 0xCF */
4637 N, N, N, N, N, N, N, N,
4638 /* 0xD0 - 0xC7 */
4639 N, N, N, N, N, N, N, N,
4640 /* 0xD8 - 0xDF */
4641 N, N, N, N, N, N, N, N,
4642 /* 0xE0 - 0xE7 */
4643 N, N, N, N, N, N, N, N,
4644 /* 0xE8 - 0xEF */
4645 N, N, N, N, N, N, N, N,
4646 /* 0xF0 - 0xF7 */
4647 N, N, N, N, N, N, N, N,
4648 /* 0xF8 - 0xFF */
4649 N, N, N, N, N, N, N, N,
4650} };
4651
4652static const struct escape escape_db = { {
4653 N, N, N, N, N, N, N, N,
4654}, {
4655 /* 0xC0 - 0xC7 */
4656 N, N, N, N, N, N, N, N,
4657 /* 0xC8 - 0xCF */
4658 N, N, N, N, N, N, N, N,
4659 /* 0xD0 - 0xC7 */
4660 N, N, N, N, N, N, N, N,
4661 /* 0xD8 - 0xDF */
4662 N, N, N, N, N, N, N, N,
4663 /* 0xE0 - 0xE7 */
4664 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4665 /* 0xE8 - 0xEF */
4666 N, N, N, N, N, N, N, N,
4667 /* 0xF0 - 0xF7 */
4668 N, N, N, N, N, N, N, N,
4669 /* 0xF8 - 0xFF */
4670 N, N, N, N, N, N, N, N,
4671} };
4672
4673static const struct escape escape_dd = { {
16bebefe 4674 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4675}, {
4676 /* 0xC0 - 0xC7 */
4677 N, N, N, N, N, N, N, N,
4678 /* 0xC8 - 0xCF */
4679 N, N, N, N, N, N, N, N,
4680 /* 0xD0 - 0xC7 */
4681 N, N, N, N, N, N, N, N,
4682 /* 0xD8 - 0xDF */
4683 N, N, N, N, N, N, N, N,
4684 /* 0xE0 - 0xE7 */
4685 N, N, N, N, N, N, N, N,
4686 /* 0xE8 - 0xEF */
4687 N, N, N, N, N, N, N, N,
4688 /* 0xF0 - 0xF7 */
4689 N, N, N, N, N, N, N, N,
4690 /* 0xF8 - 0xFF */
4691 N, N, N, N, N, N, N, N,
4692} };
4693
39f062ff
NA		 4694static const struct instr_dual instr_dual_0f_c3 = {
4695 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4696};
4697
2276b511
NA		 4698static const struct mode_dual mode_dual_63 = {
4699 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4700};
4701
fd0a0d82 4702static const struct opcode opcode_table[256] = {
73fba5f4 4703 /* 0x00 - 0x07 */
fb864fbc 4704 F6ALU(Lock, em_add),
1cd196ea
AK		 4705 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4706 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4707 /* 0x08 - 0x0F */
fb864fbc 4708 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4709 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4710 N,
73fba5f4 4711 /* 0x10 - 0x17 */
fb864fbc 4712 F6ALU(Lock, em_adc),
1cd196ea
AK		 4713 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4714 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4715 /* 0x18 - 0x1F */
fb864fbc 4716 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4717 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4718 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4719 /* 0x20 - 0x27 */
fb864fbc 4720 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4721 /* 0x28 - 0x2F */
fb864fbc 4722 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4723 /* 0x30 - 0x37 */
fb864fbc 4724 F6ALU(Lock, em_xor), N, N,
73fba5f4 4725 /* 0x38 - 0x3F */
fb864fbc 4726 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4727 /* 0x40 - 0x4F */
95413dc4 4728 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4729 /* 0x50 - 0x57 */
63540382 4730 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4731 /* 0x58 - 0x5F */
c54fe504 4732 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4733 /* 0x60 - 0x67 */
b96a7fad
TY		 4734 I(ImplicitOps | Stack | No64, em_pusha),
4735 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4736 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4737 N, N, N, N,
4738 /* 0x68 - 0x6F */
d46164db
AK		 4739 I(SrcImm | Mov | Stack, em_push),
4740 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4741 I(SrcImmByte | Mov | Stack, em_push),
4742 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4743 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4744 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4745 /* 0x70 - 0x7F */
58b7075d 4746 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4747 /* 0x80 - 0x87 */
1c2545be
TY		 4748 G(ByteOp | DstMem | SrcImm, group1),
4749 G(DstMem | SrcImm, group1),
4750 G(ByteOp | DstMem | SrcImm | No64, group1),
4751 G(DstMem | SrcImmByte, group1),
fb864fbc 4752 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4753 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4754 /* 0x88 - 0x8F */
d5ae7ce8 4755 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4756 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4757 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4758 D(ModRM | SrcMem | NoAccess | DstReg),
4759 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4760 G(0, group1A),
73fba5f4 4761 /* 0x90 - 0x97 */
bf608f88 4762 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4763 /* 0x98 - 0x9F */
61429142 4764 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4765 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4766 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4767 II(ImplicitOps | Stack, em_popf, popf),
4768 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4769 /* 0xA0 - 0xA7 */
b9eac5f4 4770 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4771 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
0f89b207
TL		 4772 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4773 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
73fba5f4 4774 /* 0xA8 - 0xAF */
fb864fbc 4775 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4776 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4777 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4778 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4779 /* 0xB0 - 0xB7 */
b9eac5f4 4780 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4781 /* 0xB8 - 0xBF */
5e2c6883 4782 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4783 /* 0xC0 - 0xC7 */
007a3b54 4784 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4785 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4786 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4787 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4788 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4789 G(ByteOp, group11), G(0, group11),
73fba5f4 4790 /* 0xC8 - 0xCF */
612e89f0 4791 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4792 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4793 I(ImplicitOps, em_ret_far),
3c6e276f 4794 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4795 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4796 /* 0xD0 - 0xD7 */
007a3b54
AK		 4797 G(Src2One | ByteOp, group2), G(Src2One, group2),
4798 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4799 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4800 I(DstAcc | SrcImmUByte | No64, em_aad),
4801 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4802 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4803 /* 0xD8 - 0xDF */
045a282c 4804 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4805 /* 0xE0 - 0xE7 */
58b7075d
NA		 4806 X3(I(SrcImmByte | NearBranch, em_loop)),
4807 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4808 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4809 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4810 /* 0xE8 - 0xEF */
58b7075d
NA		 4811 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4812 I(SrcImmFAddr | No64, em_jmp_far),
4813 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4814 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4815 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4816 /* 0xF0 - 0xF7 */
bf608f88 4817 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4818 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4819 G(ByteOp, group3), G(0, group3),
73fba5f4 4820 /* 0xF8 - 0xFF */
f411e6cd
TY		 4821 D(ImplicitOps), D(ImplicitOps),
4822 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4823 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4824};
4825
fd0a0d82 4826static const struct opcode twobyte_table[256] = {
73fba5f4 4827 /* 0x00 - 0x0F */
dee6bb70 4828 G(0, group6), GD(0, &group7), N, N,
b51e974f 4829 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4830 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4831 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4832 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4833 /* 0x10 - 0x1F */
29916968
SF		 4834 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
4835 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
4836 N, N, N, N, N, N,
34d2618d
PB		 4837 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */
4838 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4839 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4840 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4841 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4842 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */
73fba5f4 4843 /* 0x20 - 0x2F */
9b88ae99
NA		 4844 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4845 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4846 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4847 check_cr_write),
4848 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4849 check_dr_write),
73fba5f4 4850 N, N, N, N,
27ce8258
IM		 4851 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4852 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4853 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4854 N, N, N, N,
73fba5f4 4855 /* 0x30 - 0x3F */
e1e210b0 4856 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4857 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4858 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4859 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4860 I(ImplicitOps | EmulateOnUD, em_sysenter),
4861 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4862 N, N,
73fba5f4
AK		 4863 N, N, N, N, N, N, N, N,
4864 /* 0x40 - 0x4F */
140bad89 4865 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4866 /* 0x50 - 0x5F */
4867 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4868 /* 0x60 - 0x6F */
aa97bb48
AK		 4869 N, N, N, N,
4870 N, N, N, N,
4871 N, N, N, N,
4872 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4873 /* 0x70 - 0x7F */
aa97bb48
AK		 4874 N, N, N, N,
4875 N, N, N, N,
4876 N, N, N, N,
4877 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4878 /* 0x80 - 0x8F */
58b7075d 4879 X16(D(SrcImm | NearBranch)),
73fba5f4 4880 /* 0x90 - 0x9F */
ee45b58e 4881 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4882 /* 0xA0 - 0xA7 */
1cd196ea 4883 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4884 II(ImplicitOps, em_cpuid, cpuid),
4885 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4886 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4887 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4888 /* 0xA8 - 0xAF */
1cd196ea 4889 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4890 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4891 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4892 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4893 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4894 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4895 /* 0xB0 - 0xB7 */
2fcf5c8a 4896 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4897 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4898 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4899 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4900 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4901 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4902 /* 0xB8 - 0xBF */
4903 N, N,
ce7faab2 4904 G(BitOp, group8),
11c363ba 4905 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4906 I(DstReg | SrcMem | ModRM, em_bsf_c),
4907 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4908 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4909 /* 0xC0 - 0xC7 */
e47a5f5f 4910 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4911 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4912 N, N, N, GD(0, &group9),
9299836e
AK		 4913 /* 0xC8 - 0xCF */
4914 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4915 /* 0xD0 - 0xDF */
4916 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4917 /* 0xE0 - 0xEF */
0a37027e
AW		 4918 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4919 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4920 /* 0xF0 - 0xFF */
4921 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4922};
4923
39f062ff
NA		 4924static const struct instr_dual instr_dual_0f_38_f0 = {
4925 I(DstReg | SrcMem | Mov, em_movbe), N
4926};
4927
4928static const struct instr_dual instr_dual_0f_38_f1 = {
4929 I(DstMem | SrcReg | Mov, em_movbe), N
4930};
4931
0bc5eedb 4932static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4933 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4934};
4935
4936static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4937 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4938};
4939
4940/*
4941 * Insns below are selected by the prefix which indexed by the third opcode
4942 * byte.
4943 */
4944static const struct opcode opcode_map_0f_38[256] = {
4945 /* 0x00 - 0x7f */
4946 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4947 /* 0x80 - 0xef */
4948 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4949 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4950 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4951 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4952 /* 0xf2 - 0xff */
4953 N, N, X4(N), X8(N)
0bc5eedb
BP		 4954};
4955
73fba5f4
AK		 4956#undef D
4957#undef N
4958#undef G
4959#undef GD
4960#undef I
aa97bb48 4961#undef GP
01de8b09 4962#undef EXT
2276b511 4963#undef MD
2b42fce6 4964#undef ID
73fba5f4 4965
8d8f4e9f 4966#undef D2bv
f6511935 4967#undef D2bvIP
8d8f4e9f 4968#undef I2bv
d7841a4b 4969#undef I2bvIP
d67fc27a 4970#undef I6ALU
8d8f4e9f 4971
9dac77fa 4972static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4973{
4974 unsigned size;
4975
9dac77fa 4976 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4977 if (size == 8)
4978 size = 4;
4979 return size;
4980}
4981
4982static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4983 unsigned size, bool sign_extension)
4984{
39f21ee5
AK		 4985 int rc = X86EMUL_CONTINUE;
4986
4987 op->type = OP_IMM;
4988 op->bytes = size;
9dac77fa 4989 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4990 /* NB. Immediates are sign-extended as necessary. */
4991 switch (op->bytes) {
4992 case 1:
e85a1085 4993 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4994 break;
4995 case 2:
e85a1085 4996 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4997 break;
4998 case 4:
e85a1085 4999 op->val = insn_fetch(s32, ctxt);
39f21ee5 5000 break;
5e2c6883
NA		 5001 case 8:
5002 op->val = insn_fetch(s64, ctxt);
5003 break;
39f21ee5
AK		 5004 }
5005 if (!sign_extension) {
5006 switch (op->bytes) {
5007 case 1:
5008 op->val &= 0xff;
5009 break;
5010 case 2:
5011 op->val &= 0xffff;
5012 break;
5013 case 4:
5014 op->val &= 0xffffffff;
5015 break;
5016 }
5017 }
5018done:
5019 return rc;
5020}
5021
a9945549
AK		 5022static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
5023 unsigned d)
5024{
5025 int rc = X86EMUL_CONTINUE;
5026
5027 switch (d) {
5028 case OpReg:
2adb5ad9 5029 decode_register_operand(ctxt, op);
a9945549
AK		 5030 break;
5031 case OpImmUByte:
608aabe3 5032 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 5033 break;
5034 case OpMem:
41ddf978 5035 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 5036 mem_common:
5037 *op = ctxt->memop;
5038 ctxt->memopp = op;
96888977 5039 if (ctxt->d & BitOp)
a9945549
AK		 5040 fetch_bit_operand(ctxt);
5041 op->orig_val = op->val;
5042 break;
41ddf978 5043 case OpMem64:
aaa05f24 5044 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 5045 goto mem_common;
a9945549
AK		 5046 case OpAcc:
5047 op->type = OP_REG;
5048 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 5049 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 5050 fetch_register_operand(op);
5051 op->orig_val = op->val;
5052 break;
820207c8
AK		 5053 case OpAccLo:
5054 op->type = OP_REG;
5055 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
5056 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
5057 fetch_register_operand(op);
5058 op->orig_val = op->val;
5059 break;
5060 case OpAccHi:
5061 if (ctxt->d & ByteOp) {
5062 op->type = OP_NONE;
5063 break;
5064 }
5065 op->type = OP_REG;
5066 op->bytes = ctxt->op_bytes;
5067 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
5068 fetch_register_operand(op);
5069 op->orig_val = op->val;
5070 break;
a9945549
AK		 5071 case OpDI:
5072 op->type = OP_MEM;
5073 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5074 op->addr.mem.ea =
01485a22 5075 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 5076 op->addr.mem.seg = VCPU_SREG_ES;
5077 op->val = 0;
b3356bf0 5078 op->count = 1;
a9945549
AK		 5079 break;
5080 case OpDX:
5081 op->type = OP_REG;
5082 op->bytes = 2;
dd856efa 5083 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 5084 fetch_register_operand(op);
5085 break;
4dd6a57d 5086 case OpCL:
d29b9d7e 5087 op->type = OP_IMM;
4dd6a57d 5088 op->bytes = 1;
dd856efa 5089 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 5090 break;
5091 case OpImmByte:
5092 rc = decode_imm(ctxt, op, 1, true);
5093 break;
5094 case OpOne:
d29b9d7e 5095 op->type = OP_IMM;
4dd6a57d
AK		 5096 op->bytes = 1;
5097 op->val = 1;
5098 break;
5099 case OpImm:
5100 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
5101 break;
5e2c6883
NA		 5102 case OpImm64:
5103 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
5104 break;
28867cee
AK		 5105 case OpMem8:
5106 ctxt->memop.bytes = 1;
660696d1 5107 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 5108 ctxt->memop.addr.reg = decode_register(ctxt,
5109 ctxt->modrm_rm, true);
660696d1
GN		 5110 fetch_register_operand(&ctxt->memop);
5111 }
28867cee 5112 goto mem_common;
0fe59128
AK		 5113 case OpMem16:
5114 ctxt->memop.bytes = 2;
5115 goto mem_common;
5116 case OpMem32:
5117 ctxt->memop.bytes = 4;
5118 goto mem_common;
5119 case OpImmU16:
5120 rc = decode_imm(ctxt, op, 2, false);
5121 break;
5122 case OpImmU:
5123 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
5124 break;
5125 case OpSI:
5126 op->type = OP_MEM;
5127 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5128 op->addr.mem.ea =
01485a22 5129 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 5130 op->addr.mem.seg = ctxt->seg_override;
0fe59128 5131 op->val = 0;
b3356bf0 5132 op->count = 1;
0fe59128 5133 break;
7fa57952
PB		 5134 case OpXLat:
5135 op->type = OP_MEM;
5136 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5137 op->addr.mem.ea =
01485a22 5138 address_mask(ctxt,
7fa57952
PB		 5139 reg_read(ctxt, VCPU_REGS_RBX) +
5140 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 5141 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 5142 op->val = 0;
5143 break;
0fe59128
AK		 5144 case OpImmFAddr:
5145 op->type = OP_IMM;
5146 op->addr.mem.ea = ctxt->_eip;
5147 op->bytes = ctxt->op_bytes + 2;
5148 insn_fetch_arr(op->valptr, op->bytes, ctxt);
5149 break;
5150 case OpMemFAddr:
5151 ctxt->memop.bytes = ctxt->op_bytes + 2;
5152 goto mem_common;
c191a7a0 5153 case OpES:
d29b9d7e 5154 op->type = OP_IMM;
c191a7a0
AK		 5155 op->val = VCPU_SREG_ES;
5156 break;
5157 case OpCS:
d29b9d7e 5158 op->type = OP_IMM;
c191a7a0
AK		 5159 op->val = VCPU_SREG_CS;
5160 break;
5161 case OpSS:
d29b9d7e 5162 op->type = OP_IMM;
c191a7a0
AK		 5163 op->val = VCPU_SREG_SS;
5164 break;
5165 case OpDS:
d29b9d7e 5166 op->type = OP_IMM;
c191a7a0
AK		 5167 op->val = VCPU_SREG_DS;
5168 break;
5169 case OpFS:
d29b9d7e 5170 op->type = OP_IMM;
c191a7a0
AK		 5171 op->val = VCPU_SREG_FS;
5172 break;
5173 case OpGS:
d29b9d7e 5174 op->type = OP_IMM;
c191a7a0
AK		 5175 op->val = VCPU_SREG_GS;
5176 break;
a9945549
AK		 5177 case OpImplicit:
5178 /* Special instructions do their own operand decoding. */
5179 default:
5180 op->type = OP_NONE; /* Disable writeback. */
5181 break;
5182 }
5183
5184done:
5185 return rc;
5186}
5187
ef5d75cc 5188int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 5189{
dde7e6d1
AK		 5190 int rc = X86EMUL_CONTINUE;
5191 int mode = ctxt->mode;
46561646 5192 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 5193 bool op_prefix = false;
573e80fe 5194 bool has_seg_override = false;
46561646 5195 struct opcode opcode;
3853be26
WL		 5196 u16 dummy;
5197 struct desc_struct desc;
dde7e6d1 5198
f09ed83e
AK		 5199 ctxt->memop.type = OP_NONE;
5200 ctxt->memopp = NULL;
9dac77fa 5201 ctxt->_eip = ctxt->eip;
17052f16
PB		 5202 ctxt->fetch.ptr = ctxt->fetch.data;
5203 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 5204 ctxt->opcode_len = 1;
342993f9 5205 ctxt->intercept = x86_intercept_none;
dc25e89e 5206 if (insn_len > 0)
9dac77fa 5207 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 5208 else {
9506d57d 5209 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9 5210 if (rc != X86EMUL_CONTINUE)
016cd759 5211 goto done;
285ca9e9 5212 }
dde7e6d1
AK		 5213
5214 switch (mode) {
5215 case X86EMUL_MODE_REAL:
5216 case X86EMUL_MODE_VM86:
3853be26
WL		 5217 def_op_bytes = def_ad_bytes = 2;
5218 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5219 if (desc.d)
5220 def_op_bytes = def_ad_bytes = 4;
5221 break;
dde7e6d1
AK		 5222 case X86EMUL_MODE_PROT16:
5223 def_op_bytes = def_ad_bytes = 2;
5224 break;
5225 case X86EMUL_MODE_PROT32:
5226 def_op_bytes = def_ad_bytes = 4;
5227 break;
5228#ifdef CONFIG_X86_64
5229 case X86EMUL_MODE_PROT64:
5230 def_op_bytes = 4;
5231 def_ad_bytes = 8;
5232 break;
5233#endif
5234 default:
1d2887e2 5235 return EMULATION_FAILED;
dde7e6d1
AK		 5236 }
5237
9dac77fa
AK		 5238 ctxt->op_bytes = def_op_bytes;
5239 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 5240
5241 /* Legacy prefixes. */
5242 for (;;) {
e85a1085 5243 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 5244 case 0x66: /* operand-size override */
0d7cdee8 5245 op_prefix = true;
dde7e6d1 5246 /* switch between 2/4 bytes */
9dac77fa 5247 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 5248 break;
5249 case 0x67: /* address-size override */
5250 if (mode == X86EMUL_MODE_PROT64)
5251 /* switch between 4/8 bytes */
9dac77fa 5252 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 5253 else
5254 /* switch between 2/4 bytes */
9dac77fa 5255 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5256 break;
5257 case 0x26: /* ES override */
125ffc5e
MP		 5258 has_seg_override = true;
5259 ctxt->seg_override = VCPU_SREG_ES;
5260 break;
dde7e6d1 5261 case 0x2e: /* CS override */
125ffc5e
MP		 5262 has_seg_override = true;
5263 ctxt->seg_override = VCPU_SREG_CS;
5264 break;
dde7e6d1 5265 case 0x36: /* SS override */
125ffc5e
MP		 5266 has_seg_override = true;
5267 ctxt->seg_override = VCPU_SREG_SS;
5268 break;
dde7e6d1 5269 case 0x3e: /* DS override */
573e80fe 5270 has_seg_override = true;
125ffc5e 5271 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1
AK		 5272 break;
5273 case 0x64: /* FS override */
125ffc5e
MP		 5274 has_seg_override = true;
5275 ctxt->seg_override = VCPU_SREG_FS;
5276 break;
dde7e6d1 5277 case 0x65: /* GS override */
573e80fe 5278 has_seg_override = true;
125ffc5e 5279 ctxt->seg_override = VCPU_SREG_GS;
dde7e6d1
AK		 5280 break;
5281 case 0x40 ... 0x4f: /* REX */
5282 if (mode != X86EMUL_MODE_PROT64)
5283 goto done_prefixes;
9dac77fa 5284 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5285 continue;
5286 case 0xf0: /* LOCK */
9dac77fa 5287 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5288 break;
5289 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5290 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5291 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5292 break;
5293 default:
5294 goto done_prefixes;
5295 }
5296
5297 /* Any legacy prefix after a REX prefix nullifies its effect. */
5298
9dac77fa 5299 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5300 }
5301
5302done_prefixes:
5303
5304 /* REX prefix. */
9dac77fa
AK		 5305 if (ctxt->rex_prefix & 8)
5306 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5307
5308 /* Opcode byte(s). */
9dac77fa 5309 opcode = opcode_table[ctxt->b];
d3ad6243 5310 /* Two-byte opcode? */
9dac77fa 5311 if (ctxt->b == 0x0f) {
1ce19dc1 5312 ctxt->opcode_len = 2;
e85a1085 5313 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5314 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5315
5316 /* 0F_38 opcode map */
5317 if (ctxt->b == 0x38) {
5318 ctxt->opcode_len = 3;
5319 ctxt->b = insn_fetch(u8, ctxt);
5320 opcode = opcode_map_0f_38[ctxt->b];
5321 }
dde7e6d1 5322 }
9dac77fa 5323 ctxt->d = opcode.flags;
dde7e6d1 5324
9f4260e7
TY		 5325 if (ctxt->d & ModRM)
5326 ctxt->modrm = insn_fetch(u8, ctxt);
5327
7fe864dc
NA		 5328 /* vex-prefix instructions are not implemented */
5329 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5330 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5331 ctxt->d = NotImpl;
5332 }
5333
9dac77fa
AK		 5334 while (ctxt->d & GroupMask) {
5335 switch (ctxt->d & GroupMask) {
46561646 5336 case Group:
9dac77fa 5337 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5338 opcode = opcode.u.group[goffset];
5339 break;
5340 case GroupDual:
9dac77fa
AK		 5341 goffset = (ctxt->modrm >> 3) & 7;
5342 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5343 opcode = opcode.u.gdual->mod3[goffset];
5344 else
5345 opcode = opcode.u.gdual->mod012[goffset];
5346 break;
5347 case RMExt:
9dac77fa 5348 goffset = ctxt->modrm & 7;
01de8b09 5349 opcode = opcode.u.group[goffset];
46561646
AK		 5350 break;
5351 case Prefix:
9dac77fa 5352 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5353 return EMULATION_FAILED;
9dac77fa 5354 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5355 switch (simd_prefix) {
5356 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5357 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5358 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5359 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5360 }
5361 break;
045a282c 5362 case Escape:
3c9053a2
MP		 5363 if (ctxt->modrm > 0xbf) {
5364 size_t size = ARRAY_SIZE(opcode.u.esc->high);
5365 u32 index = array_index_nospec(
5366 ctxt->modrm - 0xc0, size);
5367
5368 opcode = opcode.u.esc->high[index];
5369 } else {
045a282c 5370 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
3c9053a2 5371 }
045a282c 5372 break;
39f062ff
NA		 5373 case InstrDual:
5374 if ((ctxt->modrm >> 6) == 3)
5375 opcode = opcode.u.idual->mod3;
5376 else
5377 opcode = opcode.u.idual->mod012;
5378 break;
2276b511
NA		 5379 case ModeDual:
5380 if (ctxt->mode == X86EMUL_MODE_PROT64)
5381 opcode = opcode.u.mdual->mode64;
5382 else
5383 opcode = opcode.u.mdual->mode32;
5384 break;
46561646 5385 default:
1d2887e2 5386 return EMULATION_FAILED;
0d7cdee8 5387 }
46561646 5388
b1ea50b2 5389 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5390 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5391 }
5392
e24186e0
PB		 5393 /* Unrecognised? */
5394 if (ctxt->d == 0)
5395 return EMULATION_FAILED;
5396
9dac77fa 5397 ctxt->execute = opcode.u.execute;
dde7e6d1 5398
3a6095a0
NA		 5399 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5400 return EMULATION_FAILED;
5401
d40a6898 5402 if (unlikely(ctxt->d &
ed9aad21
NA		 5403 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5404 No16))) {
d40a6898
PB		 5405 /*
5406 * These are copied unconditionally here, and checked unconditionally
5407 * in x86_emulate_insn.
5408 */
5409 ctxt->check_perm = opcode.check_perm;
5410 ctxt->intercept = opcode.intercept;
dde7e6d1 5411
d40a6898
PB		 5412 if (ctxt->d & NotImpl)
5413 return EMULATION_FAILED;
d867162c 5414
58b7075d
NA		 5415 if (mode == X86EMUL_MODE_PROT64) {
5416 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5417 ctxt->op_bytes = 8;
5418 else if (ctxt->d & NearBranch)
5419 ctxt->op_bytes = 8;
5420 }
7f9b4b75 5421
d40a6898
PB		 5422 if (ctxt->d & Op3264) {
5423 if (mode == X86EMUL_MODE_PROT64)
5424 ctxt->op_bytes = 8;
5425 else
5426 ctxt->op_bytes = 4;
5427 }
5428
ed9aad21
NA		 5429 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5430 ctxt->op_bytes = 4;
5431
d40a6898
PB		 5432 if (ctxt->d & Sse)
5433 ctxt->op_bytes = 16;
5434 else if (ctxt->d & Mmx)
5435 ctxt->op_bytes = 8;
5436 }
1253791d 5437
dde7e6d1 5438 /* ModRM and SIB bytes. */
9dac77fa 5439 if (ctxt->d & ModRM) {
f09ed83e 5440 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5441 if (!has_seg_override) {
5442 has_seg_override = true;
5443 ctxt->seg_override = ctxt->modrm_seg;
5444 }
9dac77fa 5445 } else if (ctxt->d & MemAbs)
f09ed83e 5446 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5447 if (rc != X86EMUL_CONTINUE)
5448 goto done;
5449
573e80fe
BD		 5450 if (!has_seg_override)
5451 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5452
573e80fe 5453 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5454
dde7e6d1
AK		 5455 /*
5456 * Decode and fetch the source operand: register, memory
5457 * or immediate.
5458 */
0fe59128 5459 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5460 if (rc != X86EMUL_CONTINUE)
5461 goto done;
5462
dde7e6d1
AK		 5463 /*
5464 * Decode and fetch the second source operand: register, memory
5465 * or immediate.
5466 */
4dd6a57d 5467 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5468 if (rc != X86EMUL_CONTINUE)
5469 goto done;
5470
dde7e6d1 5471 /* Decode and fetch the destination operand: register or memory. */
a9945549 5472 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5473
d9092f52 5474 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5475 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5476 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5477
a430c916 5478done:
c8848cee
JD		 5479 if (rc == X86EMUL_PROPAGATE_FAULT)
5480 ctxt->have_exception = true;
1d2887e2 5481 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5482}
5483
1cb3f3ae
XG		 5484bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5485{
5486 return ctxt->d & PageTable;
5487}
5488
3e2f65d5
GN		 5489static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5490{
3e2f65d5
GN		 5491 /* The second termination condition only applies for REPE
5492 * and REPNE. Test if the repeat string operation prefix is
5493 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5494 * corresponding termination condition according to:
5495 * - if REPE/REPZ and ZF = 0 then done
5496 * - if REPNE/REPNZ and ZF = 1 then done
5497 */
9dac77fa
AK		 5498 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5499 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5500 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5501 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5502 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5503 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5504 return true;
5505
5506 return false;
5507}
5508
cbe2c9d3
AK		 5509static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5510{
aabba3c6 5511 int rc;
cbe2c9d3 5512
a7baead7 5513 emulator_get_fpu();
aabba3c6 5514 rc = asm_safe("fwait");
a7baead7 5515 emulator_put_fpu();
cbe2c9d3 5516
aabba3c6 5517 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5518 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5519
5520 return X86EMUL_CONTINUE;
5521}
5522
c0a21c3f 5523static void fetch_possible_mmx_operand(struct operand *op)
cbe2c9d3
AK		 5524{
5525 if (op->type == OP_MM)
c0a21c3f 5526 read_mmx_reg(&op->mm_val, op->addr.mm);
cbe2c9d3
AK		 5527}
5528
3009afc6 5529static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop)
e28bbd44
AK		 5530{
5531 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5532
b9fa409b
AK		 5533 if (!(ctxt->d & ByteOp))
5534 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5535
1a29b5b7 5536 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
b8c0b6ae 5537 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
1a29b5b7 5538 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
b8c0b6ae 5539 : "c"(ctxt->src2.val));
4548f63e 5540
e28bbd44 5541 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5542 if (!fop) /* exception is returned in fop variable */
5543 return emulate_de(ctxt);
e28bbd44
AK		 5544 return X86EMUL_CONTINUE;
5545}
dd856efa 5546
1498507a
BD		 5547void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5548{
573e80fe
BD		 5549 memset(&ctxt->rip_relative, 0,
5550 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5551
1498507a
BD		 5552 ctxt->io_read.pos = 0;
5553 ctxt->io_read.end = 0;
1498507a
BD		 5554 ctxt->mem_read.end = 0;
5555}
5556
7b105ca2 5557int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5558{
0225fb50 5559 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5560 int rc = X86EMUL_CONTINUE;
9dac77fa 5561 int saved_dst_type = ctxt->dst.type;
6ed071f0 5562 unsigned emul_flags;
8b4caf66 5563
9dac77fa 5564 ctxt->mem_read.pos = 0;
310b5d30 5565
e24186e0
PB		 5566 /* LOCK prefix is allowed only with some instructions */
5567 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5568 rc = emulate_ud(ctxt);
1161624f
GN		 5569 goto done;
5570 }
5571
e24186e0 5572 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5573 rc = emulate_ud(ctxt);
d380a5e4
GN		 5574 goto done;
5575 }
5576
6ed071f0 5577 emul_flags = ctxt->ops->get_hflags(ctxt);
d40a6898
PB		 5578 if (unlikely(ctxt->d &
5579 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5580 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5581 (ctxt->d & Undefined)) {
5582 rc = emulate_ud(ctxt);
5583 goto done;
5584 }
1253791d 5585
d40a6898
PB		 5586 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5587 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5588 rc = emulate_ud(ctxt);
cbe2c9d3 5589 goto done;
d40a6898 5590 }
cbe2c9d3 5591
d40a6898
PB		 5592 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5593 rc = emulate_nm(ctxt);
c4f035c6 5594 goto done;
d40a6898 5595 }
c4f035c6 5596
d40a6898
PB		 5597 if (ctxt->d & Mmx) {
5598 rc = flush_pending_x87_faults(ctxt);
5599 if (rc != X86EMUL_CONTINUE)
5600 goto done;
5601 /*
5602 * Now that we know the fpu is exception safe, we can fetch
5603 * operands from it.
5604 */
c0a21c3f
SC		 5605 fetch_possible_mmx_operand(&ctxt->src);
5606 fetch_possible_mmx_operand(&ctxt->src2);
d40a6898 5607 if (!(ctxt->d & Mov))
c0a21c3f 5608 fetch_possible_mmx_operand(&ctxt->dst);
d40a6898 5609 }
e92805ac 5610
6ed071f0 5611 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5612 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5613 X86_ICPT_PRE_EXCEPT);
5614 if (rc != X86EMUL_CONTINUE)
5615 goto done;
5616 }
8ea7d6ae 5617
64a38292
NA		 5618 /* Instruction can only be executed in protected mode */
5619 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5620 rc = emulate_ud(ctxt);
5621 goto done;
5622 }
5623
d40a6898
PB		 5624 /* Privileged instruction can be executed only in CPL=0 */
5625 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5626 if (ctxt->d & PrivUD)
5627 rc = emulate_ud(ctxt);
5628 else
5629 rc = emulate_gp(ctxt, 0);
d09beabd 5630 goto done;
d40a6898 5631 }
d09beabd 5632
d40a6898 5633 /* Do instruction specific permission checks */
685bbf4a 5634 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5635 rc = ctxt->check_perm(ctxt);
5636 if (rc != X86EMUL_CONTINUE)
5637 goto done;
5638 }
5639
6ed071f0 5640 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5641 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5642 X86_ICPT_POST_EXCEPT);
5643 if (rc != X86EMUL_CONTINUE)
5644 goto done;
5645 }
5646
5647 if (ctxt->rep_prefix && (ctxt->d & String)) {
5648 /* All REP prefixes have the same first termination condition */
5649 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5650 string_registers_quirk(ctxt);
d40a6898 5651 ctxt->eip = ctxt->_eip;
0efb0440 5652 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5653 goto done;
5654 }
b9fa9d6b 5655 }
b9fa9d6b
AK		 5656 }
5657
9dac77fa
AK		 5658 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5659 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5660 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5661 if (rc != X86EMUL_CONTINUE)
8b4caf66 5662 goto done;
9dac77fa 5663 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5664 }
5665
9dac77fa
AK		 5666 if (ctxt->src2.type == OP_MEM) {
5667 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5668 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5669 if (rc != X86EMUL_CONTINUE)
5670 goto done;
5671 }
5672
9dac77fa 5673 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5674 goto special_insn;
5675
5676
9dac77fa 5677 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5678 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5679 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5680 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5681 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5682 if (!(ctxt->d & NoWrite) &&
5683 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5684 ctxt->exception.vector == PF_VECTOR)
5685 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5686 goto done;
c205fb7d 5687 }
038e51de 5688 }
4ff6f8e6
PB		 5689 /* Copy full 64-bit value for CMPXCHG8B. */
5690 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5691
018a98db
AK		 5692special_insn:
5693
6ed071f0 5694 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5695 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5696 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5697 if (rc != X86EMUL_CONTINUE)
5698 goto done;
5699 }
5700
b9a1ecb9 5701 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5702 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5703 else
0efb0440 5704 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5705
9dac77fa 5706 if (ctxt->execute) {
3009afc6 5707 if (ctxt->d & Fastop)
b78a8552 5708 rc = fastop(ctxt, ctxt->fop);
3009afc6 5709 else
52db3698 5710 rc = ctxt->execute(ctxt);
ef65c889
AK		 5711 if (rc != X86EMUL_CONTINUE)
5712 goto done;
5713 goto writeback;
5714 }
5715
1ce19dc1 5716 if (ctxt->opcode_len == 2)
6aa8b732 5717 goto twobyte_insn;
0bc5eedb
BP		 5718 else if (ctxt->opcode_len == 3)
5719 goto threebyte_insn;
6aa8b732 5720
9dac77fa 5721 switch (ctxt->b) {
b2833e3c 5722 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5723 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5724 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5725 break;
7e0b54b1 5726 case 0x8d: /* lea r16/r32, m */
9dac77fa 5727 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5728 break;
3d9e77df 5729 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5730 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5731 ctxt->dst.type = OP_NONE;
5732 else
5733 rc = em_xchg(ctxt);
e4f973ae 5734 break;
e8b6fa70 5735 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5736 switch (ctxt->op_bytes) {
5737 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5738 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5739 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5740 }
5741 break;
6e154e56 5742 case 0xcc: /* int3 */
5c5df76b
TY		 5743 rc = emulate_int(ctxt, 3);
5744 break;
6e154e56 5745 case 0xcd: /* int n */
9dac77fa 5746 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5747 break;
5748 case 0xce: /* into */
0efb0440 5749 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5750 rc = emulate_int(ctxt, 4);
6e154e56 5751 break;
1a52e051 5752 case 0xe9: /* jmp rel */
db5b0762 5753 case 0xeb: /* jmp rel short */
234f3ce4 5754 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5755 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5756 break;
111de5d6 5757 case 0xf4: /* hlt */
6c3287f7 5758 ctxt->ops->halt(ctxt);
19fdfa0d 5759 break;
111de5d6
AK		 5760 case 0xf5: /* cmc */
5761 /* complement carry flag from eflags reg */
0efb0440 5762 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5763 break;
5764 case 0xf8: /* clc */
0efb0440 5765 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5766 break;
8744aa9a 5767 case 0xf9: /* stc */
0efb0440 5768 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5769 break;
fb4616f4 5770 case 0xfc: /* cld */
0efb0440 5771 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5772 break;
5773 case 0xfd: /* std */
0efb0440 5774 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5775 break;
91269b8f
AK		 5776 default:
5777 goto cannot_emulate;
6aa8b732 5778 }
018a98db 5779
7d9ddaed
AK		 5780 if (rc != X86EMUL_CONTINUE)
5781 goto done;
5782
018a98db 5783writeback:
fb32b1ed
AK		 5784 if (ctxt->d & SrcWrite) {
5785 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5786 rc = writeback(ctxt, &ctxt->src);
5787 if (rc != X86EMUL_CONTINUE)
5788 goto done;
5789 }
ee212297
NA		 5790 if (!(ctxt->d & NoWrite)) {
5791 rc = writeback(ctxt, &ctxt->dst);
5792 if (rc != X86EMUL_CONTINUE)
5793 goto done;
5794 }
018a98db 5795
5cd21917
GN		 5796 /*
5797 * restore dst type in case the decoding will be reused
5798 * (happens for string instruction )
5799 */
9dac77fa 5800 ctxt->dst.type = saved_dst_type;
5cd21917 5801
9dac77fa 5802 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5803 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5804
9dac77fa 5805 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5806 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5807
9dac77fa 5808 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5809 unsigned int count;
9dac77fa 5810 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5811 if ((ctxt->d & SrcMask) == SrcSI)
5812 count = ctxt->src.count;
5813 else
5814 count = ctxt->dst.count;
01485a22 5815 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5816
d2ddd1c4
GN		 5817 if (!string_insn_completed(ctxt)) {
5818 /*
5819 * Re-enter guest when pio read ahead buffer is empty
5820 * or, if it is not used, after each 1024 iteration.
5821 */
dd856efa 5822 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5823 (r->end == 0 || r->end != r->pos)) {
5824 /*
5825 * Reset read cache. Usually happens before
5826 * decode, but since instruction is restarted
5827 * we have to do it here.
5828 */
9dac77fa 5829 ctxt->mem_read.end = 0;
dd856efa 5830 writeback_registers(ctxt);
d2ddd1c4
GN		 5831 return EMULATION_RESTART;
5832 }
5833 goto done; /* skip rip writeback */
0fa6ccbd 5834 }
0efb0440 5835 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5836 }
d2ddd1c4 5837
9dac77fa 5838 ctxt->eip = ctxt->_eip;
fede8076
PB		 5839 if (ctxt->mode != X86EMUL_MODE_PROT64)
5840 ctxt->eip = (u32)ctxt->_eip;
018a98db
AK		 5841
5842done:
e0ad0b47
PB		 5843 if (rc == X86EMUL_PROPAGATE_FAULT) {
5844 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5845 ctxt->have_exception = true;
e0ad0b47 5846 }
775fde86
JR		 5847 if (rc == X86EMUL_INTERCEPTED)
5848 return EMULATION_INTERCEPTED;
5849
dd856efa
AK		 5850 if (rc == X86EMUL_CONTINUE)
5851 writeback_registers(ctxt);
5852
d2ddd1c4 5853 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5854
5855twobyte_insn:
9dac77fa 5856 switch (ctxt->b) {
018a98db 5857 case 0x09: /* wbinvd */
cfb22375 5858 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5859 break;
5860 case 0x08: /* invd */
018a98db
AK		 5861 case 0x0d: /* GrpP (prefetch) */
5862 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5863 case 0x1f: /* nop */
018a98db
AK		 5864 break;
5865 case 0x20: /* mov cr, reg */
9dac77fa 5866 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5867 break;
6aa8b732 5868 case 0x21: /* mov from dr to reg */
9dac77fa 5869 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5870 break;
6aa8b732 5871 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5872 if (test_cc(ctxt->b, ctxt->eflags))
5873 ctxt->dst.val = ctxt->src.val;
b91aa14d 5874 else if (ctxt->op_bytes != 4)
9dac77fa 5875 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5876 break;
b2833e3c 5877 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5878 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5879 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5880 break;
ee45b58e 5881 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5882 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5883 break;
6aa8b732 5884 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5885 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5886 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5887 : (u16) ctxt->src.val;
6aa8b732 5888 break;
6aa8b732 5889 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5890 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5891 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5892 (s16) ctxt->src.val;
6aa8b732 5893 break;
91269b8f
AK		 5894 default:
5895 goto cannot_emulate;
6aa8b732 5896 }
7d9ddaed 5897
0bc5eedb
BP		 5898threebyte_insn:
5899
7d9ddaed
AK		 5900 if (rc != X86EMUL_CONTINUE)
5901 goto done;
5902
6aa8b732
AK		 5903 goto writeback;
5904
5905cannot_emulate:
a0c0ab2f 5906 return EMULATION_FAILED;
6aa8b732 5907}
dd856efa
AK		 5908
5909void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5910{
5911 invalidate_registers(ctxt);
5912}
5913
5914void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5915{
5916 writeback_registers(ctxt);
5917}
0f89b207
TL		 5918
5919bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5920{
5921 if (ctxt->rep_prefix && (ctxt->d & String))
5922 return false;
5923
5924 if (ctxt->d & TwoMemOp)
5925 return false;
5926
5927 return true;
5928}
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