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KVM: x86 emulator: move interruptibility state tracking out of emulator
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
38ba30ba 36#include "tss.h"
e99f0507 37
6aa8b732
AK		 38/*
39 * Opcode effective-address decode tables.
40 * Note that we only emulate instructions that have at least one memory
41 * operand (excluding implicit stack references). We assume that stack
42 * references and instruction fetches will never occur in special memory
43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
44 * not be handled.
45 */
46
47/* Operand sizes: 8-bit operands or specified/overridden size. */
48#define ByteOp (1<<0) /* 8-bit operands. */
49/* Destination operand type. */
50#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
51#define DstReg (2<<1) /* Register operand. */
52#define DstMem (3<<1) /* Memory operand. */
9c9fddd0 53#define DstAcc (4<<1) /* Destination Accumulator */
a682e354 54#define DstDI (5<<1) /* Destination is in ES:(E)DI */
6550e1f1 55#define DstMem64 (6<<1) /* 64bit memory operand */
9c9fddd0 56#define DstMask (7<<1)
6aa8b732 57/* Source operand type. */
9c9fddd0
GT		 58#define SrcNone (0<<4) /* No source operand. */
59#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
60#define SrcReg (1<<4) /* Register operand. */
61#define SrcMem (2<<4) /* Memory operand. */
62#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
63#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
64#define SrcImm (5<<4) /* Immediate operand. */
65#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 66#define SrcOne (7<<4) /* Implied '1' */
341de7e3 67#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 68#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 69#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 70#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
71#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
341de7e3 72#define SrcMask (0xf<<4)
6aa8b732 73/* Generic ModRM decode. */
341de7e3 74#define ModRM (1<<8)
6aa8b732 75/* Destination is only written; never read. */
341de7e3
GN		 76#define Mov (1<<9)
77#define BitOp (1<<10)
78#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 79#define String (1<<12) /* String instruction (rep capable) */
80#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 81#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
82#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
83#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 84/* Misc flags */
d380a5e4 85#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 86#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 87#define No64 (1<<28)
0dc8d10f
GT		 88/* Source 2 operand type */
89#define Src2None (0<<29)
90#define Src2CL (1<<29)
91#define Src2ImmByte (2<<29)
92#define Src2One (3<<29)
93#define Src2Mask (7<<29)
6aa8b732 94
43bb19cd 95enum {
1d6ad207 96 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 97 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 98 Group8, Group9,
43bb19cd
AK		 99};
100
45ed60b3 101static u32 opcode_table[256] = {
6aa8b732 102 /* 0x00 - 0x07 */
d380a5e4 103 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 105 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 106 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 107 /* 0x08 - 0x0F */
d380a5e4 108 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 110 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
111 ImplicitOps | Stack | No64, 0,
6aa8b732 112 /* 0x10 - 0x17 */
d380a5e4 113 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 115 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 116 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 117 /* 0x18 - 0x1F */
d380a5e4 118 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 120 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 121 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732 122 /* 0x20 - 0x27 */
d380a5e4 123 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732 124 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 125 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732 126 /* 0x28 - 0x2F */
d380a5e4 127 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 128 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
129 0, 0, 0, 0,
130 /* 0x30 - 0x37 */
d380a5e4 131 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 132 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
133 0, 0, 0, 0,
134 /* 0x38 - 0x3F */
135 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
136 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 137 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
138 0, 0,
d77a2507 139 /* 0x40 - 0x47 */
33615aa9 140 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 141 /* 0x48 - 0x4F */
33615aa9 142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 143 /* 0x50 - 0x57 */
6e3d5dfb
AK		 144 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
145 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 146 /* 0x58 - 0x5F */
6e3d5dfb
AK		 147 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
148 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 149 /* 0x60 - 0x67 */
abcf14b5
MG		 150 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
151 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 152 0, 0, 0, 0,
153 /* 0x68 - 0x6F */
91ed7a0e 154 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
7972995b
GN		 155 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */
156 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */
55bebde4 157 /* 0x70 - 0x77 */
b2833e3c
GN		 158 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
159 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 160 /* 0x78 - 0x7F */
b2833e3c
GN		 161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
162 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 163 /* 0x80 - 0x87 */
1d6ad207
AK		 164 Group | Group1_80, Group | Group1_81,
165 Group | Group1_82, Group | Group1_83,
6aa8b732 166 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
d380a5e4 167 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
6aa8b732
AK		 168 /* 0x88 - 0x8F */
169 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
170 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 171 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
054fe9f6 172 ImplicitOps | SrcMem | ModRM, Group | Group1A,
b13354f8
MG		 173 /* 0x90 - 0x97 */
174 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
175 /* 0x98 - 0x9F */
414e6277 176 0, 0, SrcImmFAddr | No64, 0,
0654169e 177 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 178 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 179 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
180 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
a682e354
GN		 181 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String,
182 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String,
6aa8b732 183 /* 0xA8 - 0xAF */
a682e354
GN		 184 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String,
185 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String,
186 ByteOp | DstDI | String, DstDI | String,
a5e2e82b
MG		 187 /* 0xB0 - 0xB7 */
188 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
189 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
192 /* 0xB8 - 0xBF */
193 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
194 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 197 /* 0xC0 - 0xC7 */
d9413cd7 198 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 199 0, ImplicitOps | Stack, 0, 0,
d9413cd7 200 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 201 /* 0xC8 - 0xCF */
e637b823 202 0, 0, 0, ImplicitOps | Stack,
d8769fed 203 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 204 /* 0xD0 - 0xD7 */
205 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
206 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
207 0, 0, 0, 0,
208 /* 0xD8 - 0xDF */
209 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 210 /* 0xE0 - 0xE7 */
a6a3034c 211 0, 0, 0, 0,
cf8f70bf
GN		 212 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
213 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc,
098c937b 214 /* 0xE8 - 0xEF */
d53c4777 215 SrcImm | Stack, SrcImm | ImplicitOps,
414e6277 216 SrcImmFAddr | No64, SrcImmByte | ImplicitOps,
cf8f70bf
GN		 217 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
218 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc,
6aa8b732
AK		 219 /* 0xF0 - 0xF7 */
220 0, 0, 0, 0,
e92805ac 221 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 222 /* 0xF8 - 0xFF */
b284be57 223 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 224 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 225};
226
45ed60b3 227static u32 twobyte_table[256] = {
6aa8b732 228 /* 0x00 - 0x0F */
e92805ac
GN		 229 0, Group | GroupDual | Group7, 0, 0,
230 0, ImplicitOps, ImplicitOps | Priv, 0,
231 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
232 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 233 /* 0x10 - 0x1F */
234 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
235 /* 0x20 - 0x2F */
e92805ac
GN		 236 ModRM | ImplicitOps | Priv, ModRM | Priv,
237 ModRM | ImplicitOps | Priv, ModRM | Priv,
238 0, 0, 0, 0,
6aa8b732
AK		 239 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0x30 - 0x3F */
e92805ac
GN		 241 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
242 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 243 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 244 /* 0x40 - 0x47 */
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
249 /* 0x48 - 0x4F */
250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
251 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
254 /* 0x50 - 0x5F */
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
256 /* 0x60 - 0x6F */
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
258 /* 0x70 - 0x7F */
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0x80 - 0x8F */
b2833e3c
GN		 261 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
262 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 263 /* 0x90 - 0x9F */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xA0 - 0xA7 */
0934ac9d
MG		 266 ImplicitOps | Stack, ImplicitOps | Stack,
267 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 268 DstMem | SrcReg | Src2ImmByte | ModRM,
269 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 270 /* 0xA8 - 0xAF */
0934ac9d 271 ImplicitOps | Stack, ImplicitOps | Stack,
d380a5e4 272 0, DstMem | SrcReg | ModRM | BitOp | Lock,
9bf8ea42
GT		 273 DstMem | SrcReg | Src2ImmByte | ModRM,
274 DstMem | SrcReg | Src2CL | ModRM,
275 ModRM, 0,
6aa8b732 276 /* 0xB0 - 0xB7 */
d380a5e4
GN		 277 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock,
278 0, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 279 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
280 DstReg | SrcMem16 | ModRM | Mov,
281 /* 0xB8 - 0xBF */
d380a5e4
GN		 282 0, 0,
283 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock,
6aa8b732
AK		 284 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
285 DstReg | SrcMem16 | ModRM | Mov,
286 /* 0xC0 - 0xCF */
60a29d4e
GN		 287 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
288 0, 0, 0, Group | GroupDual | Group9,
a012e65a 289 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 290 /* 0xD0 - 0xDF */
291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
292 /* 0xE0 - 0xEF */
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
294 /* 0xF0 - 0xFF */
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
296};
297
45ed60b3 298static u32 group_table[] = {
1d6ad207 299 [Group1_80*8] =
d380a5e4
GN		 300 ByteOp | DstMem | SrcImm | ModRM | Lock,
301 ByteOp | DstMem | SrcImm | ModRM | Lock,
302 ByteOp | DstMem | SrcImm | ModRM | Lock,
303 ByteOp | DstMem | SrcImm | ModRM | Lock,
304 ByteOp | DstMem | SrcImm | ModRM | Lock,
305 ByteOp | DstMem | SrcImm | ModRM | Lock,
306 ByteOp | DstMem | SrcImm | ModRM | Lock,
307 ByteOp | DstMem | SrcImm | ModRM,
1d6ad207 308 [Group1_81*8] =
d380a5e4
GN		 309 DstMem | SrcImm | ModRM | Lock,
310 DstMem | SrcImm | ModRM | Lock,
311 DstMem | SrcImm | ModRM | Lock,
312 DstMem | SrcImm | ModRM | Lock,
313 DstMem | SrcImm | ModRM | Lock,
314 DstMem | SrcImm | ModRM | Lock,
315 DstMem | SrcImm | ModRM | Lock,
316 DstMem | SrcImm | ModRM,
1d6ad207 317 [Group1_82*8] =
e424e191
GN		 318 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
319 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock,
325 ByteOp | DstMem | SrcImm | ModRM | No64,
1d6ad207 326 [Group1_83*8] =
d380a5e4
GN		 327 DstMem | SrcImmByte | ModRM | Lock,
328 DstMem | SrcImmByte | ModRM | Lock,
329 DstMem | SrcImmByte | ModRM | Lock,
330 DstMem | SrcImmByte | ModRM | Lock,
331 DstMem | SrcImmByte | ModRM | Lock,
332 DstMem | SrcImmByte | ModRM | Lock,
333 DstMem | SrcImmByte | ModRM | Lock,
334 DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 335 [Group1A*8] =
336 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 337 [Group3_Byte*8] =
338 ByteOp | SrcImm | DstMem | ModRM, 0,
339 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
340 0, 0, 0, 0,
341 [Group3*8] =
41afa025 342 DstMem | SrcImm | ModRM, 0,
6eb06cb2 343 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 344 0, 0, 0, 0,
fd60754e
AK		 345 [Group4*8] =
346 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
347 0, 0, 0, 0, 0, 0,
348 [Group5*8] =
d19292e4
MG		 349 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
350 SrcMem | ModRM | Stack, 0,
414e6277 351 SrcMem | ModRM | Stack, SrcMemFAddr | ModRM | ImplicitOps,
ea79849d 352 SrcMem | ModRM | Stack, 0,
d95058a1 353 [Group7*8] =
e92805ac 354 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 355 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 356 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 357 [Group8*8] =
358 0, 0, 0, 0,
d380a5e4
GN		 359 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock,
360 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock,
60a29d4e 361 [Group9*8] =
6550e1f1 362 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 363};
364
45ed60b3 365static u32 group2_table[] = {
d95058a1 366 [Group7*8] =
835e6b80 367 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv,
16286d08 368 SrcNone | ModRM | DstMem | Mov, 0,
835e6b80 369 SrcMem16 | ModRM | Mov | Priv, 0,
60a29d4e
GN		 370 [Group9*8] =
371 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 372};
373
6aa8b732 374/* EFLAGS bit definitions. */
d4c6a154
GN		 375#define EFLG_ID (1<<21)
376#define EFLG_VIP (1<<20)
377#define EFLG_VIF (1<<19)
378#define EFLG_AC (1<<18)
b1d86143
AP		 379#define EFLG_VM (1<<17)
380#define EFLG_RF (1<<16)
d4c6a154
GN		 381#define EFLG_IOPL (3<<12)
382#define EFLG_NT (1<<14)
6aa8b732
AK		 383#define EFLG_OF (1<<11)
384#define EFLG_DF (1<<10)
b1d86143 385#define EFLG_IF (1<<9)
d4c6a154 386#define EFLG_TF (1<<8)
6aa8b732
AK		 387#define EFLG_SF (1<<7)
388#define EFLG_ZF (1<<6)
389#define EFLG_AF (1<<4)
390#define EFLG_PF (1<<2)
391#define EFLG_CF (1<<0)
392
393/*
394 * Instruction emulation:
395 * Most instructions are emulated directly via a fragment of inline assembly
396 * code. This allows us to save/restore EFLAGS and thus very easily pick up
397 * any modified flags.
398 */
399
05b3e0c2 400#if defined(CONFIG_X86_64)
6aa8b732
AK		 401#define _LO32 "k" /* force 32-bit operand */
402#define _STK "%%rsp" /* stack pointer */
403#elif defined(__i386__)
404#define _LO32 "" /* force 32-bit operand */
405#define _STK "%%esp" /* stack pointer */
406#endif
407
408/*
409 * These EFLAGS bits are restored from saved value during emulation, and
410 * any changes are written back to the saved value after emulation.
411 */
412#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
413
414/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 415#define _PRE_EFLAGS(_sav, _msk, _tmp) \
416 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
417 "movl %"_sav",%"_LO32 _tmp"; " \
418 "push %"_tmp"; " \
419 "push %"_tmp"; " \
420 "movl %"_msk",%"_LO32 _tmp"; " \
421 "andl %"_LO32 _tmp",("_STK"); " \
422 "pushf; " \
423 "notl %"_LO32 _tmp"; " \
424 "andl %"_LO32 _tmp",("_STK"); " \
425 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
426 "pop %"_tmp"; " \
427 "orl %"_LO32 _tmp",("_STK"); " \
428 "popf; " \
429 "pop %"_sav"; "
6aa8b732
AK		 430
431/* After executing instruction: write-back necessary bits in EFLAGS. */
432#define _POST_EFLAGS(_sav, _msk, _tmp) \
433 /* _sav |= EFLAGS & _msk; */ \
434 "pushf; " \
435 "pop %"_tmp"; " \
436 "andl %"_msk",%"_LO32 _tmp"; " \
437 "orl %"_LO32 _tmp",%"_sav"; "
438
dda96d8f
AK		 439#ifdef CONFIG_X86_64
440#define ON64(x) x
441#else
442#define ON64(x)
443#endif
444
6b7ad61f
AK		 445#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
446 do { \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "4", "2") \
449 _op _suffix " %"_x"3,%1; " \
450 _POST_EFLAGS("0", "4", "2") \
451 : "=m" (_eflags), "=m" ((_dst).val), \
452 "=&r" (_tmp) \
453 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 454 } while (0)
6b7ad61f
AK		 455
456
6aa8b732
AK		 457/* Raw emulation: instruction has two explicit operands. */
458#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 459 do { \
460 unsigned long _tmp; \
461 \
462 switch ((_dst).bytes) { \
463 case 2: \
464 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
465 break; \
466 case 4: \
467 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
468 break; \
469 case 8: \
470 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
471 break; \
472 } \
6aa8b732
AK		 473 } while (0)
474
475#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
476 do { \
6b7ad61f 477 unsigned long _tmp; \
d77c26fc 478 switch ((_dst).bytes) { \
6aa8b732 479 case 1: \
6b7ad61f 480 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 481 break; \
482 default: \
483 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
484 _wx, _wy, _lx, _ly, _qx, _qy); \
485 break; \
486 } \
487 } while (0)
488
489/* Source operand is byte-sized and may be restricted to just %cl. */
490#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
491 __emulate_2op(_op, _src, _dst, _eflags, \
492 "b", "c", "b", "c", "b", "c", "b", "c")
493
494/* Source operand is byte, word, long or quad sized. */
495#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
496 __emulate_2op(_op, _src, _dst, _eflags, \
497 "b", "q", "w", "r", _LO32, "r", "", "r")
498
499/* Source operand is word, long or quad sized. */
500#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
501 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
502 "w", "r", _LO32, "r", "", "r")
503
d175226a
GT		 504/* Instruction has three operands and one operand is stored in ECX register */
505#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
506 do { \
507 unsigned long _tmp; \
508 _type _clv = (_cl).val; \
509 _type _srcv = (_src).val; \
510 _type _dstv = (_dst).val; \
511 \
512 __asm__ __volatile__ ( \
513 _PRE_EFLAGS("0", "5", "2") \
514 _op _suffix " %4,%1 \n" \
515 _POST_EFLAGS("0", "5", "2") \
516 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
517 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
518 ); \
519 \
520 (_cl).val = (unsigned long) _clv; \
521 (_src).val = (unsigned long) _srcv; \
522 (_dst).val = (unsigned long) _dstv; \
523 } while (0)
524
525#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
526 do { \
527 switch ((_dst).bytes) { \
528 case 2: \
529 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
530 "w", unsigned short); \
531 break; \
532 case 4: \
533 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
534 "l", unsigned int); \
535 break; \
536 case 8: \
537 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
538 "q", unsigned long)); \
539 break; \
540 } \
541 } while (0)
542
dda96d8f 543#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 544 do { \
545 unsigned long _tmp; \
546 \
dda96d8f
AK		 547 __asm__ __volatile__ ( \
548 _PRE_EFLAGS("0", "3", "2") \
549 _op _suffix " %1; " \
550 _POST_EFLAGS("0", "3", "2") \
551 : "=m" (_eflags), "+m" ((_dst).val), \
552 "=&r" (_tmp) \
553 : "i" (EFLAGS_MASK)); \
554 } while (0)
555
556/* Instruction has only one explicit operand (no source operand). */
557#define emulate_1op(_op, _dst, _eflags) \
558 do { \
d77c26fc 559 switch ((_dst).bytes) { \
dda96d8f
AK		 560 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
561 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
562 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
563 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 564 } \
565 } while (0)
566
6aa8b732
AK		 567/* Fetch next part of the instruction being emulated. */
568#define insn_fetch(_type, _size, _eip) \
569({ unsigned long _x; \
62266869 570 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 571 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 572 goto done; \
573 (_eip) += (_size); \
574 (_type)_x; \
575})
576
414e6277
GN		 577#define insn_fetch_arr(_arr, _size, _eip) \
578({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
579 if (rc != X86EMUL_CONTINUE) \
580 goto done; \
581 (_eip) += (_size); \
582})
583
ddcb2885
HH		 584static inline unsigned long ad_mask(struct decode_cache *c)
585{
586 return (1UL << (c->ad_bytes << 3)) - 1;
587}
588
6aa8b732 589/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 590static inline unsigned long
591address_mask(struct decode_cache *c, unsigned long reg)
592{
593 if (c->ad_bytes == sizeof(unsigned long))
594 return reg;
595 else
596 return reg & ad_mask(c);
597}
598
599static inline unsigned long
600register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
601{
602 return base + address_mask(c, reg);
603}
604
7a957275
HH		 605static inline void
606register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
607{
608 if (c->ad_bytes == sizeof(unsigned long))
609 *reg += inc;
610 else
611 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
612}
6aa8b732 613
7a957275
HH		 614static inline void jmp_rel(struct decode_cache *c, int rel)
615{
616 register_address_increment(c, &c->eip, rel);
617}
098c937b 618
7a5b56df
AK		 619static void set_seg_override(struct decode_cache *c, int seg)
620{
621 c->has_seg_override = true;
622 c->seg_override = seg;
623}
624
79168fd1
GN		 625static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
626 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 627{
628 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
629 return 0;
630
79168fd1 631 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 632}
633
634static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 635 struct x86_emulate_ops *ops,
7a5b56df
AK		 636 struct decode_cache *c)
637{
638 if (!c->has_seg_override)
639 return 0;
640
79168fd1 641 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 642}
643
79168fd1
GN		 644static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
645 struct x86_emulate_ops *ops)
7a5b56df 646{
79168fd1 647 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 648}
649
79168fd1
GN		 650static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
651 struct x86_emulate_ops *ops)
7a5b56df 652{
79168fd1 653 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 654}
655
62266869
AK		 656static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
657 struct x86_emulate_ops *ops,
2fb53ad8 658 unsigned long eip, u8 *dest)
62266869
AK		 659{
660 struct fetch_cache *fc = &ctxt->decode.fetch;
661 int rc;
2fb53ad8 662 int size, cur_size;
62266869 663
2fb53ad8
AK		 664 if (eip == fc->end) {
665 cur_size = fc->end - fc->start;
666 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
667 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
668 size, ctxt->vcpu, NULL);
3e2815e9 669 if (rc != X86EMUL_CONTINUE)
62266869 670 return rc;
2fb53ad8 671 fc->end += size;
62266869 672 }
2fb53ad8 673 *dest = fc->data[eip - fc->start];
3e2815e9 674 return X86EMUL_CONTINUE;
62266869
AK		 675}
676
677static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680{
3e2815e9 681 int rc;
62266869 682
eb3c79e6 683 /* x86 instructions are limited to 15 bytes. */
063db061 684 if (eip + size - ctxt->eip > 15)
eb3c79e6 685 return X86EMUL_UNHANDLEABLE;
62266869
AK		 686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 688 if (rc != X86EMUL_CONTINUE)
62266869
AK		 689 return rc;
690 }
3e2815e9 691 return X86EMUL_CONTINUE;
62266869
AK		 692}
693
1e3c5cb0
RR		 694/*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
6aa8b732
AK		 701{
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708}
709
710static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 void *ptr,
713 u16 *size, unsigned long *address, int op_bytes)
714{
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
cebff02b 720 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 721 ctxt->vcpu, NULL);
1b30eaa8 722 if (rc != X86EMUL_CONTINUE)
6aa8b732 723 return rc;
cebff02b 724 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 725 ctxt->vcpu, NULL);
6aa8b732
AK		 726 return rc;
727}
728
bbe9abbd
NK		 729static int test_cc(unsigned int condition, unsigned int flags)
730{
731 int rc = 0;
732
733 switch ((condition & 15) >> 1) {
734 case 0: /* o */
735 rc |= (flags & EFLG_OF);
736 break;
737 case 1: /* b/c/nae */
738 rc |= (flags & EFLG_CF);
739 break;
740 case 2: /* z/e */
741 rc |= (flags & EFLG_ZF);
742 break;
743 case 3: /* be/na */
744 rc |= (flags & (EFLG_CF|EFLG_ZF));
745 break;
746 case 4: /* s */
747 rc |= (flags & EFLG_SF);
748 break;
749 case 5: /* p/pe */
750 rc |= (flags & EFLG_PF);
751 break;
752 case 7: /* le/ng */
753 rc |= (flags & EFLG_ZF);
754 /* fall through */
755 case 6: /* l/nge */
756 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
757 break;
758 }
759
760 /* Odd condition identifiers (lsb == 1) have inverted sense. */
761 return (!!rc ^ (condition & 1));
762}
763
3c118e24
AK		 764static void decode_register_operand(struct operand *op,
765 struct decode_cache *c,
3c118e24
AK		 766 int inhibit_bytereg)
767{
33615aa9 768 unsigned reg = c->modrm_reg;
9f1ef3f8 769 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 770
771 if (!(c->d & ModRM))
772 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 773 op->type = OP_REG;
774 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 775 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 776 op->val = *(u8 *)op->ptr;
777 op->bytes = 1;
778 } else {
33615aa9 779 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 780 op->bytes = c->op_bytes;
781 switch (op->bytes) {
782 case 2:
783 op->val = *(u16 *)op->ptr;
784 break;
785 case 4:
786 op->val = *(u32 *)op->ptr;
787 break;
788 case 8:
789 op->val = *(u64 *) op->ptr;
790 break;
791 }
792 }
793 op->orig_val = op->val;
794}
795
1c73ef66
AK		 796static int decode_modrm(struct x86_emulate_ctxt *ctxt,
797 struct x86_emulate_ops *ops)
798{
799 struct decode_cache *c = &ctxt->decode;
800 u8 sib;
f5b4edcd 801 int index_reg = 0, base_reg = 0, scale;
3e2815e9 802 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 803
804 if (c->rex_prefix) {
805 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
806 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
807 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
808 }
809
810 c->modrm = insn_fetch(u8, 1, c->eip);
811 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
812 c->modrm_reg |= (c->modrm & 0x38) >> 3;
813 c->modrm_rm |= (c->modrm & 0x07);
814 c->modrm_ea = 0;
815 c->use_modrm_ea = 1;
816
817 if (c->modrm_mod == 3) {
107d6d2e
AK		 818 c->modrm_ptr = decode_register(c->modrm_rm,
819 c->regs, c->d & ByteOp);
820 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 821 return rc;
822 }
823
824 if (c->ad_bytes == 2) {
825 unsigned bx = c->regs[VCPU_REGS_RBX];
826 unsigned bp = c->regs[VCPU_REGS_RBP];
827 unsigned si = c->regs[VCPU_REGS_RSI];
828 unsigned di = c->regs[VCPU_REGS_RDI];
829
830 /* 16-bit ModR/M decode. */
831 switch (c->modrm_mod) {
832 case 0:
833 if (c->modrm_rm == 6)
834 c->modrm_ea += insn_fetch(u16, 2, c->eip);
835 break;
836 case 1:
837 c->modrm_ea += insn_fetch(s8, 1, c->eip);
838 break;
839 case 2:
840 c->modrm_ea += insn_fetch(u16, 2, c->eip);
841 break;
842 }
843 switch (c->modrm_rm) {
844 case 0:
845 c->modrm_ea += bx + si;
846 break;
847 case 1:
848 c->modrm_ea += bx + di;
849 break;
850 case 2:
851 c->modrm_ea += bp + si;
852 break;
853 case 3:
854 c->modrm_ea += bp + di;
855 break;
856 case 4:
857 c->modrm_ea += si;
858 break;
859 case 5:
860 c->modrm_ea += di;
861 break;
862 case 6:
863 if (c->modrm_mod != 0)
864 c->modrm_ea += bp;
865 break;
866 case 7:
867 c->modrm_ea += bx;
868 break;
869 }
870 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
871 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 872 if (!c->has_seg_override)
873 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 874 c->modrm_ea = (u16)c->modrm_ea;
875 } else {
876 /* 32/64-bit ModR/M decode. */
84411d85 877 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 878 sib = insn_fetch(u8, 1, c->eip);
879 index_reg |= (sib >> 3) & 7;
880 base_reg |= sib & 7;
881 scale = sib >> 6;
882
dc71d0f1
AK		 883 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
884 c->modrm_ea += insn_fetch(s32, 4, c->eip);
885 else
1c73ef66 886 c->modrm_ea += c->regs[base_reg];
dc71d0f1 887 if (index_reg != 4)
1c73ef66 888 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 889 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
890 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 891 c->rip_relative = 1;
84411d85 892 } else
1c73ef66 893 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 894 switch (c->modrm_mod) {
895 case 0:
896 if (c->modrm_rm == 5)
897 c->modrm_ea += insn_fetch(s32, 4, c->eip);
898 break;
899 case 1:
900 c->modrm_ea += insn_fetch(s8, 1, c->eip);
901 break;
902 case 2:
903 c->modrm_ea += insn_fetch(s32, 4, c->eip);
904 break;
905 }
906 }
1c73ef66
AK		 907done:
908 return rc;
909}
910
911static int decode_abs(struct x86_emulate_ctxt *ctxt,
912 struct x86_emulate_ops *ops)
913{
914 struct decode_cache *c = &ctxt->decode;
3e2815e9 915 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 916
917 switch (c->ad_bytes) {
918 case 2:
919 c->modrm_ea = insn_fetch(u16, 2, c->eip);
920 break;
921 case 4:
922 c->modrm_ea = insn_fetch(u32, 4, c->eip);
923 break;
924 case 8:
925 c->modrm_ea = insn_fetch(u64, 8, c->eip);
926 break;
927 }
928done:
929 return rc;
930}
931
6aa8b732 932int
8b4caf66 933x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 934{
e4e03ded 935 struct decode_cache *c = &ctxt->decode;
3e2815e9 936 int rc = X86EMUL_CONTINUE;
6aa8b732 937 int mode = ctxt->mode;
e09d082c 938 int def_op_bytes, def_ad_bytes, group;
6aa8b732 939
6aa8b732 940
5cd21917
GN		 941 /* we cannot decode insn before we complete previous rep insn */
942 WARN_ON(ctxt->restart);
943
063db061 944 c->eip = ctxt->eip;
2fb53ad8 945 c->fetch.start = c->fetch.end = c->eip;
79168fd1 946 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
6aa8b732
AK		 947
948 switch (mode) {
949 case X86EMUL_MODE_REAL:
a0044755 950 case X86EMUL_MODE_VM86:
6aa8b732 951 case X86EMUL_MODE_PROT16:
f21b8bf4 952 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 953 break;
954 case X86EMUL_MODE_PROT32:
f21b8bf4 955 def_op_bytes = def_ad_bytes = 4;
6aa8b732 956 break;
05b3e0c2 957#ifdef CONFIG_X86_64
6aa8b732 958 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 959 def_op_bytes = 4;
960 def_ad_bytes = 8;
6aa8b732
AK		 961 break;
962#endif
963 default:
964 return -1;
965 }
966
f21b8bf4
AK		 967 c->op_bytes = def_op_bytes;
968 c->ad_bytes = def_ad_bytes;
969
6aa8b732 970 /* Legacy prefixes. */
b4c6abfe 971 for (;;) {
e4e03ded 972 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 973 case 0x66: /* operand-size override */
f21b8bf4
AK		 974 /* switch between 2/4 bytes */
975 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 976 break;
977 case 0x67: /* address-size override */
978 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 979 /* switch between 4/8 bytes */
f21b8bf4 980 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 981 else
e4e03ded 982 /* switch between 2/4 bytes */
f21b8bf4 983 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 984 break;
7a5b56df 985 case 0x26: /* ES override */
6aa8b732 986 case 0x2e: /* CS override */
7a5b56df 987 case 0x36: /* SS override */
6aa8b732 988 case 0x3e: /* DS override */
7a5b56df 989 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 990 break;
991 case 0x64: /* FS override */
6aa8b732 992 case 0x65: /* GS override */
7a5b56df 993 set_seg_override(c, c->b & 7);
6aa8b732 994 break;
b4c6abfe
LV		 995 case 0x40 ... 0x4f: /* REX */
996 if (mode != X86EMUL_MODE_PROT64)
997 goto done_prefixes;
33615aa9 998 c->rex_prefix = c->b;
b4c6abfe 999 continue;
6aa8b732 1000 case 0xf0: /* LOCK */
e4e03ded 1001 c->lock_prefix = 1;
6aa8b732 1002 break;
ae6200ba 1003 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 1004 c->rep_prefix = REPNE_PREFIX;
1005 break;
6aa8b732 1006 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 1007 c->rep_prefix = REPE_PREFIX;
6aa8b732 1008 break;
6aa8b732
AK		 1009 default:
1010 goto done_prefixes;
1011 }
b4c6abfe
LV		 1012
1013 /* Any legacy prefix after a REX prefix nullifies its effect. */
1014
33615aa9 1015 c->rex_prefix = 0;
6aa8b732
AK		 1016 }
1017
1018done_prefixes:
1019
1020 /* REX prefix. */
1c73ef66 1021 if (c->rex_prefix)
33615aa9 1022 if (c->rex_prefix & 8)
e4e03ded 1023 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 1024
1025 /* Opcode byte(s). */
e4e03ded
LV		 1026 c->d = opcode_table[c->b];
1027 if (c->d == 0) {
6aa8b732 1028 /* Two-byte opcode? */
e4e03ded
LV		 1029 if (c->b == 0x0f) {
1030 c->twobyte = 1;
1031 c->b = insn_fetch(u8, 1, c->eip);
1032 c->d = twobyte_table[c->b];
6aa8b732 1033 }
e09d082c 1034 }
6aa8b732 1035
e09d082c
AK		 1036 if (c->d & Group) {
1037 group = c->d & GroupMask;
1038 c->modrm = insn_fetch(u8, 1, c->eip);
1039 --c->eip;
1040
1041 group = (group << 3) + ((c->modrm >> 3) & 7);
1042 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1043 c->d = group2_table[group];
1044 else
1045 c->d = group_table[group];
1046 }
1047
1048 /* Unrecognised? */
1049 if (c->d == 0) {
1050 DPRINTF("Cannot emulate %02x\n", c->b);
1051 return -1;
6aa8b732
AK		 1052 }
1053
6e3d5dfb
AK		 1054 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1055 c->op_bytes = 8;
1056
6aa8b732 1057 /* ModRM and SIB bytes. */
1c73ef66
AK		 1058 if (c->d & ModRM)
1059 rc = decode_modrm(ctxt, ops);
1060 else if (c->d & MemAbs)
1061 rc = decode_abs(ctxt, ops);
3e2815e9 1062 if (rc != X86EMUL_CONTINUE)
1c73ef66 1063 goto done;
6aa8b732 1064
7a5b56df
AK		 1065 if (!c->has_seg_override)
1066 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1067
7a5b56df 1068 if (!(!c->twobyte && c->b == 0x8d))
79168fd1 1069 c->modrm_ea += seg_override_base(ctxt, ops, c);
c7e75a3d
AK		 1070
1071 if (c->ad_bytes != 8)
1072 c->modrm_ea = (u32)c->modrm_ea;
69f55cb1
GN		 1073
1074 if (c->rip_relative)
1075 c->modrm_ea += c->eip;
1076
6aa8b732
AK		 1077 /*
1078 * Decode and fetch the source operand: register, memory
1079 * or immediate.
1080 */
e4e03ded 1081 switch (c->d & SrcMask) {
6aa8b732
AK		 1082 case SrcNone:
1083 break;
1084 case SrcReg:
9f1ef3f8 1085 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1086 break;
1087 case SrcMem16:
e4e03ded 1088 c->src.bytes = 2;
6aa8b732
AK		 1089 goto srcmem_common;
1090 case SrcMem32:
e4e03ded 1091 c->src.bytes = 4;
6aa8b732
AK		 1092 goto srcmem_common;
1093 case SrcMem:
e4e03ded
LV		 1094 c->src.bytes = (c->d & ByteOp) ? 1 :
1095 c->op_bytes;
b85b9ee9 1096 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1097 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1098 break;
d77c26fc 1099 srcmem_common:
4e62417b
AJ		 1100 /*
1101 * For instructions with a ModR/M byte, switch to register
1102 * access if Mod = 3.
1103 */
e4e03ded
LV		 1104 if ((c->d & ModRM) && c->modrm_mod == 3) {
1105 c->src.type = OP_REG;
66b85505 1106 c->src.val = c->modrm_val;
107d6d2e 1107 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1108 break;
1109 }
e4e03ded 1110 c->src.type = OP_MEM;
69f55cb1
GN		 1111 c->src.ptr = (unsigned long *)c->modrm_ea;
1112 c->src.val = 0;
6aa8b732
AK		 1113 break;
1114 case SrcImm:
c9eaf20f 1115 case SrcImmU:
e4e03ded
LV		 1116 c->src.type = OP_IMM;
1117 c->src.ptr = (unsigned long *)c->eip;
1118 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1119 if (c->src.bytes == 8)
1120 c->src.bytes = 4;
6aa8b732 1121 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1122 switch (c->src.bytes) {
6aa8b732 1123 case 1:
e4e03ded 1124 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1125 break;
1126 case 2:
e4e03ded 1127 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1128 break;
1129 case 4:
e4e03ded 1130 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1131 break;
1132 }
c9eaf20f
AK		 1133 if ((c->d & SrcMask) == SrcImmU) {
1134 switch (c->src.bytes) {
1135 case 1:
1136 c->src.val &= 0xff;
1137 break;
1138 case 2:
1139 c->src.val &= 0xffff;
1140 break;
1141 case 4:
1142 c->src.val &= 0xffffffff;
1143 break;
1144 }
1145 }
6aa8b732
AK		 1146 break;
1147 case SrcImmByte:
341de7e3 1148 case SrcImmUByte:
e4e03ded
LV		 1149 c->src.type = OP_IMM;
1150 c->src.ptr = (unsigned long *)c->eip;
1151 c->src.bytes = 1;
341de7e3
GN		 1152 if ((c->d & SrcMask) == SrcImmByte)
1153 c->src.val = insn_fetch(s8, 1, c->eip);
1154 else
1155 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1156 break;
bfcadf83
GT		 1157 case SrcOne:
1158 c->src.bytes = 1;
1159 c->src.val = 1;
1160 break;
a682e354
GN		 1161 case SrcSI:
1162 c->src.type = OP_MEM;
1163 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1164 c->src.ptr = (unsigned long *)
79168fd1 1165 register_address(c, seg_override_base(ctxt, ops, c),
a682e354
GN		 1166 c->regs[VCPU_REGS_RSI]);
1167 c->src.val = 0;
1168 break;
414e6277
GN		 1169 case SrcImmFAddr:
1170 c->src.type = OP_IMM;
1171 c->src.ptr = (unsigned long *)c->eip;
1172 c->src.bytes = c->op_bytes + 2;
1173 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1174 break;
1175 case SrcMemFAddr:
1176 c->src.type = OP_MEM;
1177 c->src.ptr = (unsigned long *)c->modrm_ea;
1178 c->src.bytes = c->op_bytes + 2;
1179 break;
6aa8b732
AK		 1180 }
1181
0dc8d10f
GT		 1182 /*
1183 * Decode and fetch the second source operand: register, memory
1184 * or immediate.
1185 */
1186 switch (c->d & Src2Mask) {
1187 case Src2None:
1188 break;
1189 case Src2CL:
1190 c->src2.bytes = 1;
1191 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1192 break;
1193 case Src2ImmByte:
1194 c->src2.type = OP_IMM;
1195 c->src2.ptr = (unsigned long *)c->eip;
1196 c->src2.bytes = 1;
1197 c->src2.val = insn_fetch(u8, 1, c->eip);
1198 break;
1199 case Src2One:
1200 c->src2.bytes = 1;
1201 c->src2.val = 1;
1202 break;
1203 }
1204
038e51de 1205 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1206 switch (c->d & DstMask) {
038e51de
AK		 1207 case ImplicitOps:
1208 /* Special instructions do their own operand decoding. */
8b4caf66 1209 return 0;
038e51de 1210 case DstReg:
9f1ef3f8 1211 decode_register_operand(&c->dst, c,
3c118e24 1212 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1213 break;
1214 case DstMem:
6550e1f1 1215 case DstMem64:
e4e03ded 1216 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1217 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1218 c->dst.type = OP_REG;
66b85505 1219 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1220 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1221 break;
1222 }
8b4caf66 1223 c->dst.type = OP_MEM;
69f55cb1 1224 c->dst.ptr = (unsigned long *)c->modrm_ea;
6550e1f1
GN		 1225 if ((c->d & DstMask) == DstMem64)
1226 c->dst.bytes = 8;
1227 else
1228 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
69f55cb1
GN		 1229 c->dst.val = 0;
1230 if (c->d & BitOp) {
1231 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1232
1233 c->dst.ptr = (void *)c->dst.ptr +
1234 (c->src.val & mask) / 8;
1235 }
8b4caf66 1236 break;
9c9fddd0
GT		 1237 case DstAcc:
1238 c->dst.type = OP_REG;
d6d367d6 1239 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
9c9fddd0 1240 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
d6d367d6 1241 switch (c->dst.bytes) {
9c9fddd0
GT		 1242 case 1:
1243 c->dst.val = *(u8 *)c->dst.ptr;
1244 break;
1245 case 2:
1246 c->dst.val = *(u16 *)c->dst.ptr;
1247 break;
1248 case 4:
1249 c->dst.val = *(u32 *)c->dst.ptr;
1250 break;
d6d367d6
GN		 1251 case 8:
1252 c->dst.val = *(u64 *)c->dst.ptr;
1253 break;
9c9fddd0
GT		 1254 }
1255 c->dst.orig_val = c->dst.val;
1256 break;
a682e354
GN		 1257 case DstDI:
1258 c->dst.type = OP_MEM;
1259 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1260 c->dst.ptr = (unsigned long *)
79168fd1 1261 register_address(c, es_base(ctxt, ops),
a682e354
GN		 1262 c->regs[VCPU_REGS_RDI]);
1263 c->dst.val = 0;
1264 break;
8b4caf66
LV		 1265 }
1266
1267done:
1268 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1269}
1270
9de41573
GN		 1271static int read_emulated(struct x86_emulate_ctxt *ctxt,
1272 struct x86_emulate_ops *ops,
1273 unsigned long addr, void *dest, unsigned size)
1274{
1275 int rc;
1276 struct read_cache *mc = &ctxt->decode.mem_read;
8fe681e9 1277 u32 err;
9de41573
GN		 1278
1279 while (size) {
1280 int n = min(size, 8u);
1281 size -= n;
1282 if (mc->pos < mc->end)
1283 goto read_cached;
1284
8fe681e9
GN		 1285 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1286 ctxt->vcpu);
1287 if (rc == X86EMUL_PROPAGATE_FAULT)
1288 kvm_inject_page_fault(ctxt->vcpu, addr, err);
9de41573
GN		 1289 if (rc != X86EMUL_CONTINUE)
1290 return rc;
1291 mc->end += n;
1292
1293 read_cached:
1294 memcpy(dest, mc->data + mc->pos, n);
1295 mc->pos += n;
1296 dest += n;
1297 addr += n;
1298 }
1299 return X86EMUL_CONTINUE;
1300}
1301
7b262e90
GN		 1302static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1303 struct x86_emulate_ops *ops,
1304 unsigned int size, unsigned short port,
1305 void *dest)
1306{
1307 struct read_cache *rc = &ctxt->decode.io_read;
1308
1309 if (rc->pos == rc->end) { /* refill pio read ahead */
1310 struct decode_cache *c = &ctxt->decode;
1311 unsigned int in_page, n;
1312 unsigned int count = c->rep_prefix ?
1313 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1314 in_page = (ctxt->eflags & EFLG_DF) ?
1315 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1316 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1317 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1318 count);
1319 if (n == 0)
1320 n = 1;
1321 rc->pos = rc->end = 0;
1322 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1323 return 0;
1324 rc->end = n * size;
1325 }
1326
1327 memcpy(dest, rc->data + rc->pos, size);
1328 rc->pos += size;
1329 return 1;
1330}
1331
38ba30ba
GN		 1332static u32 desc_limit_scaled(struct desc_struct *desc)
1333{
1334 u32 limit = get_desc_limit(desc);
1335
1336 return desc->g ? (limit << 12) | 0xfff : limit;
1337}
1338
1339static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1340 struct x86_emulate_ops *ops,
1341 u16 selector, struct desc_ptr *dt)
1342{
1343 if (selector & 1 << 2) {
1344 struct desc_struct desc;
1345 memset (dt, 0, sizeof *dt);
1346 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1347 return;
1348
1349 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1350 dt->address = get_desc_base(&desc);
1351 } else
1352 ops->get_gdt(dt, ctxt->vcpu);
1353}
1354
1355/* allowed just for 8 bytes segments */
1356static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1357 struct x86_emulate_ops *ops,
1358 u16 selector, struct desc_struct *desc)
1359{
1360 struct desc_ptr dt;
1361 u16 index = selector >> 3;
1362 int ret;
1363 u32 err;
1364 ulong addr;
1365
1366 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1367
1368 if (dt.size < index * 8 + 7) {
1369 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1370 return X86EMUL_PROPAGATE_FAULT;
1371 }
1372 addr = dt.address + index * 8;
1373 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1374 if (ret == X86EMUL_PROPAGATE_FAULT)
1375 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1376
1377 return ret;
1378}
1379
1380/* allowed just for 8 bytes segments */
1381static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1382 struct x86_emulate_ops *ops,
1383 u16 selector, struct desc_struct *desc)
1384{
1385 struct desc_ptr dt;
1386 u16 index = selector >> 3;
1387 u32 err;
1388 ulong addr;
1389 int ret;
1390
1391 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1392
1393 if (dt.size < index * 8 + 7) {
1394 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc);
1395 return X86EMUL_PROPAGATE_FAULT;
1396 }
1397
1398 addr = dt.address + index * 8;
1399 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1400 if (ret == X86EMUL_PROPAGATE_FAULT)
1401 kvm_inject_page_fault(ctxt->vcpu, addr, err);
1402
1403 return ret;
1404}
1405
1406static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1407 struct x86_emulate_ops *ops,
1408 u16 selector, int seg)
1409{
1410 struct desc_struct seg_desc;
1411 u8 dpl, rpl, cpl;
1412 unsigned err_vec = GP_VECTOR;
1413 u32 err_code = 0;
1414 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1415 int ret;
1416
1417 memset(&seg_desc, 0, sizeof seg_desc);
1418
1419 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1420 || ctxt->mode == X86EMUL_MODE_REAL) {
1421 /* set real mode segment descriptor */
1422 set_desc_base(&seg_desc, selector << 4);
1423 set_desc_limit(&seg_desc, 0xffff);
1424 seg_desc.type = 3;
1425 seg_desc.p = 1;
1426 seg_desc.s = 1;
1427 goto load;
1428 }
1429
1430 /* NULL selector is not valid for TR, CS and SS */
1431 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1432 && null_selector)
1433 goto exception;
1434
1435 /* TR should be in GDT only */
1436 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1437 goto exception;
1438
1439 if (null_selector) /* for NULL selector skip all following checks */
1440 goto load;
1441
1442 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1443 if (ret != X86EMUL_CONTINUE)
1444 return ret;
1445
1446 err_code = selector & 0xfffc;
1447 err_vec = GP_VECTOR;
1448
1449 /* can't load system descriptor into segment selecor */
1450 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1451 goto exception;
1452
1453 if (!seg_desc.p) {
1454 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1455 goto exception;
1456 }
1457
1458 rpl = selector & 3;
1459 dpl = seg_desc.dpl;
1460 cpl = ops->cpl(ctxt->vcpu);
1461
1462 switch (seg) {
1463 case VCPU_SREG_SS:
1464 /*
1465 * segment is not a writable data segment or segment
1466 * selector's RPL != CPL or segment selector's RPL != CPL
1467 */
1468 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1469 goto exception;
1470 break;
1471 case VCPU_SREG_CS:
1472 if (!(seg_desc.type & 8))
1473 goto exception;
1474
1475 if (seg_desc.type & 4) {
1476 /* conforming */
1477 if (dpl > cpl)
1478 goto exception;
1479 } else {
1480 /* nonconforming */
1481 if (rpl > cpl || dpl != cpl)
1482 goto exception;
1483 }
1484 /* CS(RPL) <- CPL */
1485 selector = (selector & 0xfffc) | cpl;
1486 break;
1487 case VCPU_SREG_TR:
1488 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1489 goto exception;
1490 break;
1491 case VCPU_SREG_LDTR:
1492 if (seg_desc.s || seg_desc.type != 2)
1493 goto exception;
1494 break;
1495 default: /* DS, ES, FS, or GS */
1496 /*
1497 * segment is not a data or readable code segment or
1498 * ((segment is a data or nonconforming code segment)
1499 * and (both RPL and CPL > DPL))
1500 */
1501 if ((seg_desc.type & 0xa) == 0x8 ||
1502 (((seg_desc.type & 0xc) != 0xc) &&
1503 (rpl > dpl && cpl > dpl)))
1504 goto exception;
1505 break;
1506 }
1507
1508 if (seg_desc.s) {
1509 /* mark segment as accessed */
1510 seg_desc.type |= 1;
1511 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1512 if (ret != X86EMUL_CONTINUE)
1513 return ret;
1514 }
1515load:
1516 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1517 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1518 return X86EMUL_CONTINUE;
1519exception:
1520 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code);
1521 return X86EMUL_PROPAGATE_FAULT;
1522}
1523
79168fd1
GN		 1524static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1525 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1526{
1527 struct decode_cache *c = &ctxt->decode;
1528
1529 c->dst.type = OP_MEM;
1530 c->dst.bytes = c->op_bytes;
1531 c->dst.val = c->src.val;
7a957275 1532 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
79168fd1 1533 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
8cdbd2c9
LV		 1534 c->regs[VCPU_REGS_RSP]);
1535}
1536
faa5a3ae 1537static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1538 struct x86_emulate_ops *ops,
1539 void *dest, int len)
8cdbd2c9
LV		 1540{
1541 struct decode_cache *c = &ctxt->decode;
1542 int rc;
1543
79168fd1 1544 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
9de41573
GN		 1545 c->regs[VCPU_REGS_RSP]),
1546 dest, len);
b60d513c 1547 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1548 return rc;
1549
350f69dc 1550 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1551 return rc;
1552}
8cdbd2c9 1553
d4c6a154
GN		 1554static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1555 struct x86_emulate_ops *ops,
1556 void *dest, int len)
1557{
1558 int rc;
1559 unsigned long val, change_mask;
1560 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1561 int cpl = ops->cpl(ctxt->vcpu);
d4c6a154
GN		 1562
1563 rc = emulate_pop(ctxt, ops, &val, len);
1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
1567 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1568 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1569
1570 switch(ctxt->mode) {
1571 case X86EMUL_MODE_PROT64:
1572 case X86EMUL_MODE_PROT32:
1573 case X86EMUL_MODE_PROT16:
1574 if (cpl == 0)
1575 change_mask |= EFLG_IOPL;
1576 if (cpl <= iopl)
1577 change_mask |= EFLG_IF;
1578 break;
1579 case X86EMUL_MODE_VM86:
1580 if (iopl < 3) {
1581 kvm_inject_gp(ctxt->vcpu, 0);
1582 return X86EMUL_PROPAGATE_FAULT;
1583 }
1584 change_mask |= EFLG_IF;
1585 break;
1586 default: /* real mode */
1587 change_mask |= (EFLG_IOPL | EFLG_IF);
1588 break;
1589 }
1590
1591 *(unsigned long *)dest =
1592 (ctxt->eflags & ~change_mask) | (val & change_mask);
1593
1594 return rc;
1595}
1596
79168fd1
GN		 1597static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1598 struct x86_emulate_ops *ops, int seg)
0934ac9d
MG		 1599{
1600 struct decode_cache *c = &ctxt->decode;
0934ac9d 1601
79168fd1 1602 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
0934ac9d 1603
79168fd1 1604 emulate_push(ctxt, ops);
0934ac9d
MG		 1605}
1606
1607static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1608 struct x86_emulate_ops *ops, int seg)
1609{
1610 struct decode_cache *c = &ctxt->decode;
1611 unsigned long selector;
1612 int rc;
1613
1614 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1b30eaa8 1615 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 1616 return rc;
1617
2e873022 1618 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
0934ac9d
MG		 1619 return rc;
1620}
1621
79168fd1
GN		 1622static void emulate_pusha(struct x86_emulate_ctxt *ctxt,
1623 struct x86_emulate_ops *ops)
abcf14b5
MG		 1624{
1625 struct decode_cache *c = &ctxt->decode;
1626 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1627 int reg = VCPU_REGS_RAX;
1628
1629 while (reg <= VCPU_REGS_RDI) {
1630 (reg == VCPU_REGS_RSP) ?
1631 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1632
79168fd1 1633 emulate_push(ctxt, ops);
abcf14b5
MG		 1634 ++reg;
1635 }
1636}
1637
1638static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1639 struct x86_emulate_ops *ops)
1640{
1641 struct decode_cache *c = &ctxt->decode;
1b30eaa8 1642 int rc = X86EMUL_CONTINUE;
abcf14b5
MG		 1643 int reg = VCPU_REGS_RDI;
1644
1645 while (reg >= VCPU_REGS_RAX) {
1646 if (reg == VCPU_REGS_RSP) {
1647 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1648 c->op_bytes);
1649 --reg;
1650 }
1651
1652 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1b30eaa8 1653 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 1654 break;
1655 --reg;
1656 }
1657 return rc;
1658}
1659
faa5a3ae
AK		 1660static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1661 struct x86_emulate_ops *ops)
1662{
1663 struct decode_cache *c = &ctxt->decode;
faa5a3ae 1664
1b30eaa8 1665 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1666}
1667
05f086f8 1668static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1669{
05f086f8 1670 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1671 switch (c->modrm_reg) {
1672 case 0: /* rol */
05f086f8 1673 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1674 break;
1675 case 1: /* ror */
05f086f8 1676 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1677 break;
1678 case 2: /* rcl */
05f086f8 1679 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1680 break;
1681 case 3: /* rcr */
05f086f8 1682 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1683 break;
1684 case 4: /* sal/shl */
1685 case 6: /* sal/shl */
05f086f8 1686 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1687 break;
1688 case 5: /* shr */
05f086f8 1689 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1690 break;
1691 case 7: /* sar */
05f086f8 1692 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1693 break;
1694 }
1695}
1696
1697static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1698 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1699{
1700 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1701
1702 switch (c->modrm_reg) {
1703 case 0 ... 1: /* test */
05f086f8 1704 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1705 break;
1706 case 2: /* not */
1707 c->dst.val = ~c->dst.val;
1708 break;
1709 case 3: /* neg */
05f086f8 1710 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1711 break;
1712 default:
aca06a83 1713 return 0;
8cdbd2c9 1714 }
aca06a83 1715 return 1;
8cdbd2c9
LV		 1716}
1717
1718static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1719 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1720{
1721 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1722
1723 switch (c->modrm_reg) {
1724 case 0: /* inc */
05f086f8 1725 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1726 break;
1727 case 1: /* dec */
05f086f8 1728 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1729 break;
d19292e4
MG		 1730 case 2: /* call near abs */ {
1731 long int old_eip;
1732 old_eip = c->eip;
1733 c->eip = c->src.val;
1734 c->src.val = old_eip;
79168fd1 1735 emulate_push(ctxt, ops);
d19292e4
MG		 1736 break;
1737 }
8cdbd2c9 1738 case 4: /* jmp abs */
fd60754e 1739 c->eip = c->src.val;
8cdbd2c9
LV		 1740 break;
1741 case 6: /* push */
79168fd1 1742 emulate_push(ctxt, ops);
8cdbd2c9 1743 break;
8cdbd2c9 1744 }
1b30eaa8 1745 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1746}
1747
1748static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1749 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1750{
1751 struct decode_cache *c = &ctxt->decode;
6550e1f1 1752 u64 old = c->dst.orig_val;
8cdbd2c9
LV		 1753
1754 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1755 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1756
1757 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1758 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1759 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1760 } else {
6550e1f1 1761 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
8cdbd2c9
LV		 1762 (u32) c->regs[VCPU_REGS_RBX];
1763
05f086f8 1764 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1765 }
1b30eaa8 1766 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1767}
1768
a77ab5ea
AK		 1769static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1770 struct x86_emulate_ops *ops)
1771{
1772 struct decode_cache *c = &ctxt->decode;
1773 int rc;
1774 unsigned long cs;
1775
1776 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1777 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1778 return rc;
1779 if (c->op_bytes == 4)
1780 c->eip = (u32)c->eip;
1781 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1782 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1783 return rc;
2e873022 1784 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1785 return rc;
1786}
1787
8cdbd2c9
LV		 1788static inline int writeback(struct x86_emulate_ctxt *ctxt,
1789 struct x86_emulate_ops *ops)
1790{
1791 int rc;
1792 struct decode_cache *c = &ctxt->decode;
8fe681e9 1793 u32 err;
8cdbd2c9
LV		 1794
1795 switch (c->dst.type) {
1796 case OP_REG:
1797 /* The 4-byte case *is* correct:
1798 * in 64-bit mode we zero-extend.
1799 */
1800 switch (c->dst.bytes) {
1801 case 1:
1802 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1803 break;
1804 case 2:
1805 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1806 break;
1807 case 4:
1808 *c->dst.ptr = (u32)c->dst.val;
1809 break; /* 64b: zero-ext */
1810 case 8:
1811 *c->dst.ptr = c->dst.val;
1812 break;
1813 }
1814 break;
1815 case OP_MEM:
1816 if (c->lock_prefix)
1817 rc = ops->cmpxchg_emulated(
1818 (unsigned long)c->dst.ptr,
1819 &c->dst.orig_val,
1820 &c->dst.val,
1821 c->dst.bytes,
8fe681e9 1822 &err,
8cdbd2c9
LV		 1823 ctxt->vcpu);
1824 else
1825 rc = ops->write_emulated(
1826 (unsigned long)c->dst.ptr,
1827 &c->dst.val,
1828 c->dst.bytes,
8fe681e9 1829 &err,
8cdbd2c9 1830 ctxt->vcpu);
8fe681e9
GN		 1831 if (rc == X86EMUL_PROPAGATE_FAULT)
1832 kvm_inject_page_fault(ctxt->vcpu,
1833 (unsigned long)c->dst.ptr, err);
b60d513c 1834 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1835 return rc;
a01af5ec
LV		 1836 break;
1837 case OP_NONE:
1838 /* no writeback */
1839 break;
8cdbd2c9
LV		 1840 default:
1841 break;
1842 }
1b30eaa8 1843 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1844}
1845
e66bb2cc
AP		 1846static inline void
1847setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1848 struct x86_emulate_ops *ops, struct desc_struct *cs,
1849 struct desc_struct *ss)
e66bb2cc 1850{
79168fd1
GN		 1851 memset(cs, 0, sizeof(struct desc_struct));
1852 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1853 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1854
1855 cs->l = 0; /* will be adjusted later */
79168fd1 1856 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1857 cs->g = 1; /* 4kb granularity */
79168fd1 1858 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1859 cs->type = 0x0b; /* Read, Execute, Accessed */
1860 cs->s = 1;
1861 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1862 cs->p = 1;
1863 cs->d = 1;
e66bb2cc 1864
79168fd1
GN		 1865 set_desc_base(ss, 0); /* flat segment */
1866 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1867 ss->g = 1; /* 4kb granularity */
1868 ss->s = 1;
1869 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1870 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1871 ss->dpl = 0;
79168fd1 1872 ss->p = 1;
e66bb2cc
AP		 1873}
1874
1875static int
3fb1b5db 1876emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1877{
1878 struct decode_cache *c = &ctxt->decode;
79168fd1 1879 struct desc_struct cs, ss;
e66bb2cc 1880 u64 msr_data;
79168fd1 1881 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1882
1883 /* syscall is not available in real mode */
2e901c4c
GN		 1884 if (ctxt->mode == X86EMUL_MODE_REAL ||
1885 ctxt->mode == X86EMUL_MODE_VM86) {
1886 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1887 return X86EMUL_PROPAGATE_FAULT;
1888 }
e66bb2cc 1889
79168fd1 1890 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1891
3fb1b5db 1892 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1893 msr_data >>= 32;
79168fd1
GN		 1894 cs_sel = (u16)(msr_data & 0xfffc);
1895 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1896
1897 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1898 cs.d = 0;
e66bb2cc
AP		 1899 cs.l = 1;
1900 }
79168fd1
GN		 1901 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1902 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1903 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1904 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1905
1906 c->regs[VCPU_REGS_RCX] = c->eip;
1907 if (is_long_mode(ctxt->vcpu)) {
1908#ifdef CONFIG_X86_64
1909 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1910
3fb1b5db
GN		 1911 ops->get_msr(ctxt->vcpu,
1912 ctxt->mode == X86EMUL_MODE_PROT64 ?
1913 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1914 c->eip = msr_data;
1915
3fb1b5db 1916 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1917 ctxt->eflags &= ~(msr_data | EFLG_RF);
1918#endif
1919 } else {
1920 /* legacy mode */
3fb1b5db 1921 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1922 c->eip = (u32)msr_data;
1923
1924 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1925 }
1926
e54cfa97 1927 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1928}
1929
8c604352 1930static int
3fb1b5db 1931emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1932{
1933 struct decode_cache *c = &ctxt->decode;
79168fd1 1934 struct desc_struct cs, ss;
8c604352 1935 u64 msr_data;
79168fd1 1936 u16 cs_sel, ss_sel;
8c604352 1937
a0044755
GN		 1938 /* inject #GP if in real mode */
1939 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352 1940 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 1941 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1942 }
1943
1944 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1945 * Therefore, we inject an #UD.
1946 */
2e901c4c
GN		 1947 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1948 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
1949 return X86EMUL_PROPAGATE_FAULT;
1950 }
8c604352 1951
79168fd1 1952 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1953
3fb1b5db 1954 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1955 switch (ctxt->mode) {
1956 case X86EMUL_MODE_PROT32:
1957 if ((msr_data & 0xfffc) == 0x0) {
1958 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1959 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1960 }
1961 break;
1962 case X86EMUL_MODE_PROT64:
1963 if (msr_data == 0x0) {
1964 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 1965 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1966 }
1967 break;
1968 }
1969
1970 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1971 cs_sel = (u16)msr_data;
1972 cs_sel &= ~SELECTOR_RPL_MASK;
1973 ss_sel = cs_sel + 8;
1974 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1975 if (ctxt->mode == X86EMUL_MODE_PROT64
1976 || is_long_mode(ctxt->vcpu)) {
79168fd1 1977 cs.d = 0;
8c604352
AP		 1978 cs.l = 1;
1979 }
1980
79168fd1
GN		 1981 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1982 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1983 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1984 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1985
3fb1b5db 1986 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1987 c->eip = msr_data;
1988
3fb1b5db 1989 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1990 c->regs[VCPU_REGS_RSP] = msr_data;
1991
e54cfa97 1992 return X86EMUL_CONTINUE;
8c604352
AP		 1993}
1994
4668f050 1995static int
3fb1b5db 1996emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1997{
1998 struct decode_cache *c = &ctxt->decode;
79168fd1 1999 struct desc_struct cs, ss;
4668f050
AP		 2000 u64 msr_data;
2001 int usermode;
79168fd1 2002 u16 cs_sel, ss_sel;
4668f050 2003
a0044755
GN		 2004 /* inject #GP if in real mode or Virtual 8086 mode */
2005 if (ctxt->mode == X86EMUL_MODE_REAL ||
2006 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050 2007 kvm_inject_gp(ctxt->vcpu, 0);
2e901c4c 2008 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 2009 }
2010
79168fd1 2011 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2012
2013 if ((c->rex_prefix & 0x8) != 0x0)
2014 usermode = X86EMUL_MODE_PROT64;
2015 else
2016 usermode = X86EMUL_MODE_PROT32;
2017
2018 cs.dpl = 3;
2019 ss.dpl = 3;
3fb1b5db 2020 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2021 switch (usermode) {
2022 case X86EMUL_MODE_PROT32:
79168fd1 2023 cs_sel = (u16)(msr_data + 16);
4668f050
AP		 2024 if ((msr_data & 0xfffc) == 0x0) {
2025 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 2026 return X86EMUL_PROPAGATE_FAULT;
4668f050 2027 }
79168fd1 2028 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2029 break;
2030 case X86EMUL_MODE_PROT64:
79168fd1 2031 cs_sel = (u16)(msr_data + 32);
4668f050
AP		 2032 if (msr_data == 0x0) {
2033 kvm_inject_gp(ctxt->vcpu, 0);
e54cfa97 2034 return X86EMUL_PROPAGATE_FAULT;
4668f050 2035 }
79168fd1
GN		 2036 ss_sel = cs_sel + 8;
2037 cs.d = 0;
4668f050
AP		 2038 cs.l = 1;
2039 break;
2040 }
79168fd1
GN		 2041 cs_sel |= SELECTOR_RPL_MASK;
2042 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2043
79168fd1
GN		 2044 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2045 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2046 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2047 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 2048
bdb475a3
GN		 2049 c->eip = c->regs[VCPU_REGS_RDX];
2050 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2051
e54cfa97 2052 return X86EMUL_CONTINUE;
4668f050
AP		 2053}
2054
9c537244
GN		 2055static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2056 struct x86_emulate_ops *ops)
f850e2e6
GN		 2057{
2058 int iopl;
2059 if (ctxt->mode == X86EMUL_MODE_REAL)
2060 return false;
2061 if (ctxt->mode == X86EMUL_MODE_VM86)
2062 return true;
2063 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 2064 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 2065}
2066
2067static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2068 struct x86_emulate_ops *ops,
2069 u16 port, u16 len)
2070{
79168fd1 2071 struct desc_struct tr_seg;
f850e2e6
GN		 2072 int r;
2073 u16 io_bitmap_ptr;
2074 u8 perm, bit_idx = port & 0x7;
2075 unsigned mask = (1 << len) - 1;
2076
79168fd1
GN		 2077 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2078 if (!tr_seg.p)
f850e2e6 2079 return false;
79168fd1 2080 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2081 return false;
79168fd1
GN		 2082 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2083 ctxt->vcpu, NULL);
f850e2e6
GN		 2084 if (r != X86EMUL_CONTINUE)
2085 return false;
79168fd1 2086 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2087 return false;
79168fd1
GN		 2088 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2089 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 2090 if (r != X86EMUL_CONTINUE)
2091 return false;
2092 if ((perm >> bit_idx) & mask)
2093 return false;
2094 return true;
2095}
2096
2097static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2098 struct x86_emulate_ops *ops,
2099 u16 port, u16 len)
2100{
9c537244 2101 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2102 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2103 return false;
2104 return true;
2105}
2106
38ba30ba
GN		 2107static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2108 struct x86_emulate_ops *ops,
2109 struct tss_segment_16 *tss)
2110{
2111 struct decode_cache *c = &ctxt->decode;
2112
2113 tss->ip = c->eip;
2114 tss->flag = ctxt->eflags;
2115 tss->ax = c->regs[VCPU_REGS_RAX];
2116 tss->cx = c->regs[VCPU_REGS_RCX];
2117 tss->dx = c->regs[VCPU_REGS_RDX];
2118 tss->bx = c->regs[VCPU_REGS_RBX];
2119 tss->sp = c->regs[VCPU_REGS_RSP];
2120 tss->bp = c->regs[VCPU_REGS_RBP];
2121 tss->si = c->regs[VCPU_REGS_RSI];
2122 tss->di = c->regs[VCPU_REGS_RDI];
2123
2124 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2125 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2126 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2127 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2128 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2129}
2130
2131static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2132 struct x86_emulate_ops *ops,
2133 struct tss_segment_16 *tss)
2134{
2135 struct decode_cache *c = &ctxt->decode;
2136 int ret;
2137
2138 c->eip = tss->ip;
2139 ctxt->eflags = tss->flag | 2;
2140 c->regs[VCPU_REGS_RAX] = tss->ax;
2141 c->regs[VCPU_REGS_RCX] = tss->cx;
2142 c->regs[VCPU_REGS_RDX] = tss->dx;
2143 c->regs[VCPU_REGS_RBX] = tss->bx;
2144 c->regs[VCPU_REGS_RSP] = tss->sp;
2145 c->regs[VCPU_REGS_RBP] = tss->bp;
2146 c->regs[VCPU_REGS_RSI] = tss->si;
2147 c->regs[VCPU_REGS_RDI] = tss->di;
2148
2149 /*
2150 * SDM says that segment selectors are loaded before segment
2151 * descriptors
2152 */
2153 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2154 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2155 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2156 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2157 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2158
2159 /*
2160 * Now load segment descriptors. If fault happenes at this stage
2161 * it is handled in a context of new task
2162 */
2163 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2164 if (ret != X86EMUL_CONTINUE)
2165 return ret;
2166 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2167 if (ret != X86EMUL_CONTINUE)
2168 return ret;
2169 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2170 if (ret != X86EMUL_CONTINUE)
2171 return ret;
2172 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2173 if (ret != X86EMUL_CONTINUE)
2174 return ret;
2175 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2176 if (ret != X86EMUL_CONTINUE)
2177 return ret;
2178
2179 return X86EMUL_CONTINUE;
2180}
2181
2182static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2183 struct x86_emulate_ops *ops,
2184 u16 tss_selector, u16 old_tss_sel,
2185 ulong old_tss_base, struct desc_struct *new_desc)
2186{
2187 struct tss_segment_16 tss_seg;
2188 int ret;
2189 u32 err, new_tss_base = get_desc_base(new_desc);
2190
2191 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2192 &err);
2193 if (ret == X86EMUL_PROPAGATE_FAULT) {
2194 /* FIXME: need to provide precise fault address */
2195 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2196 return ret;
2197 }
2198
2199 save_state_to_tss16(ctxt, ops, &tss_seg);
2200
2201 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2202 &err);
2203 if (ret == X86EMUL_PROPAGATE_FAULT) {
2204 /* FIXME: need to provide precise fault address */
2205 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2206 return ret;
2207 }
2208
2209 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2210 &err);
2211 if (ret == X86EMUL_PROPAGATE_FAULT) {
2212 /* FIXME: need to provide precise fault address */
2213 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2214 return ret;
2215 }
2216
2217 if (old_tss_sel != 0xffff) {
2218 tss_seg.prev_task_link = old_tss_sel;
2219
2220 ret = ops->write_std(new_tss_base,
2221 &tss_seg.prev_task_link,
2222 sizeof tss_seg.prev_task_link,
2223 ctxt->vcpu, &err);
2224 if (ret == X86EMUL_PROPAGATE_FAULT) {
2225 /* FIXME: need to provide precise fault address */
2226 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2227 return ret;
2228 }
2229 }
2230
2231 return load_state_from_tss16(ctxt, ops, &tss_seg);
2232}
2233
2234static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2235 struct x86_emulate_ops *ops,
2236 struct tss_segment_32 *tss)
2237{
2238 struct decode_cache *c = &ctxt->decode;
2239
2240 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2241 tss->eip = c->eip;
2242 tss->eflags = ctxt->eflags;
2243 tss->eax = c->regs[VCPU_REGS_RAX];
2244 tss->ecx = c->regs[VCPU_REGS_RCX];
2245 tss->edx = c->regs[VCPU_REGS_RDX];
2246 tss->ebx = c->regs[VCPU_REGS_RBX];
2247 tss->esp = c->regs[VCPU_REGS_RSP];
2248 tss->ebp = c->regs[VCPU_REGS_RBP];
2249 tss->esi = c->regs[VCPU_REGS_RSI];
2250 tss->edi = c->regs[VCPU_REGS_RDI];
2251
2252 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2253 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2254 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2255 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2256 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2257 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2258 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2259}
2260
2261static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2262 struct x86_emulate_ops *ops,
2263 struct tss_segment_32 *tss)
2264{
2265 struct decode_cache *c = &ctxt->decode;
2266 int ret;
2267
0f12244f
GN		 2268 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
2269 kvm_inject_gp(ctxt->vcpu, 0);
2270 return X86EMUL_PROPAGATE_FAULT;
2271 }
38ba30ba
GN		 2272 c->eip = tss->eip;
2273 ctxt->eflags = tss->eflags | 2;
2274 c->regs[VCPU_REGS_RAX] = tss->eax;
2275 c->regs[VCPU_REGS_RCX] = tss->ecx;
2276 c->regs[VCPU_REGS_RDX] = tss->edx;
2277 c->regs[VCPU_REGS_RBX] = tss->ebx;
2278 c->regs[VCPU_REGS_RSP] = tss->esp;
2279 c->regs[VCPU_REGS_RBP] = tss->ebp;
2280 c->regs[VCPU_REGS_RSI] = tss->esi;
2281 c->regs[VCPU_REGS_RDI] = tss->edi;
2282
2283 /*
2284 * SDM says that segment selectors are loaded before segment
2285 * descriptors
2286 */
2287 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2288 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2289 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2290 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2291 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2292 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2293 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2294
2295 /*
2296 * Now load segment descriptors. If fault happenes at this stage
2297 * it is handled in a context of new task
2298 */
2299 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2300 if (ret != X86EMUL_CONTINUE)
2301 return ret;
2302 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2303 if (ret != X86EMUL_CONTINUE)
2304 return ret;
2305 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2306 if (ret != X86EMUL_CONTINUE)
2307 return ret;
2308 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2309 if (ret != X86EMUL_CONTINUE)
2310 return ret;
2311 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2312 if (ret != X86EMUL_CONTINUE)
2313 return ret;
2314 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2315 if (ret != X86EMUL_CONTINUE)
2316 return ret;
2317 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2318 if (ret != X86EMUL_CONTINUE)
2319 return ret;
2320
2321 return X86EMUL_CONTINUE;
2322}
2323
2324static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2325 struct x86_emulate_ops *ops,
2326 u16 tss_selector, u16 old_tss_sel,
2327 ulong old_tss_base, struct desc_struct *new_desc)
2328{
2329 struct tss_segment_32 tss_seg;
2330 int ret;
2331 u32 err, new_tss_base = get_desc_base(new_desc);
2332
2333 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2334 &err);
2335 if (ret == X86EMUL_PROPAGATE_FAULT) {
2336 /* FIXME: need to provide precise fault address */
2337 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2338 return ret;
2339 }
2340
2341 save_state_to_tss32(ctxt, ops, &tss_seg);
2342
2343 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2344 &err);
2345 if (ret == X86EMUL_PROPAGATE_FAULT) {
2346 /* FIXME: need to provide precise fault address */
2347 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err);
2348 return ret;
2349 }
2350
2351 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2352 &err);
2353 if (ret == X86EMUL_PROPAGATE_FAULT) {
2354 /* FIXME: need to provide precise fault address */
2355 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2356 return ret;
2357 }
2358
2359 if (old_tss_sel != 0xffff) {
2360 tss_seg.prev_task_link = old_tss_sel;
2361
2362 ret = ops->write_std(new_tss_base,
2363 &tss_seg.prev_task_link,
2364 sizeof tss_seg.prev_task_link,
2365 ctxt->vcpu, &err);
2366 if (ret == X86EMUL_PROPAGATE_FAULT) {
2367 /* FIXME: need to provide precise fault address */
2368 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err);
2369 return ret;
2370 }
2371 }
2372
2373 return load_state_from_tss32(ctxt, ops, &tss_seg);
2374}
2375
2376static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2377 struct x86_emulate_ops *ops,
2378 u16 tss_selector, int reason,
2379 bool has_error_code, u32 error_code)
38ba30ba
GN		 2380{
2381 struct desc_struct curr_tss_desc, next_tss_desc;
2382 int ret;
2383 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2384 ulong old_tss_base =
5951c442 2385 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2386 u32 desc_limit;
38ba30ba
GN		 2387
2388 /* FIXME: old_tss_base == ~0 ? */
2389
2390 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2391 if (ret != X86EMUL_CONTINUE)
2392 return ret;
2393 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2394 if (ret != X86EMUL_CONTINUE)
2395 return ret;
2396
2397 /* FIXME: check that next_tss_desc is tss */
2398
2399 if (reason != TASK_SWITCH_IRET) {
2400 if ((tss_selector & 3) > next_tss_desc.dpl ||
2401 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2402 kvm_inject_gp(ctxt->vcpu, 0);
2403 return X86EMUL_PROPAGATE_FAULT;
2404 }
2405 }
2406
ceffb459
GN		 2407 desc_limit = desc_limit_scaled(&next_tss_desc);
2408 if (!next_tss_desc.p ||
2409 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2410 desc_limit < 0x2b)) {
38ba30ba
GN		 2411 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR,
2412 tss_selector & 0xfffc);
2413 return X86EMUL_PROPAGATE_FAULT;
2414 }
2415
2416 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2417 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2418 write_segment_descriptor(ctxt, ops, old_tss_sel,
2419 &curr_tss_desc);
2420 }
2421
2422 if (reason == TASK_SWITCH_IRET)
2423 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2424
2425 /* set back link to prev task only if NT bit is set in eflags
2426 note that old_tss_sel is not used afetr this point */
2427 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2428 old_tss_sel = 0xffff;
2429
2430 if (next_tss_desc.type & 8)
2431 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2432 old_tss_base, &next_tss_desc);
2433 else
2434 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2435 old_tss_base, &next_tss_desc);
0760d448
JK		 2436 if (ret != X86EMUL_CONTINUE)
2437 return ret;
38ba30ba
GN		 2438
2439 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2440 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2441
2442 if (reason != TASK_SWITCH_IRET) {
2443 next_tss_desc.type |= (1 << 1); /* set busy flag */
2444 write_segment_descriptor(ctxt, ops, tss_selector,
2445 &next_tss_desc);
2446 }
2447
2448 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2449 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2450 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2451
e269fb21
JK		 2452 if (has_error_code) {
2453 struct decode_cache *c = &ctxt->decode;
2454
2455 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2456 c->lock_prefix = 0;
2457 c->src.val = (unsigned long) error_code;
79168fd1 2458 emulate_push(ctxt, ops);
e269fb21
JK		 2459 }
2460
38ba30ba
GN		 2461 return ret;
2462}
2463
2464int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2465 struct x86_emulate_ops *ops,
e269fb21
JK		 2466 u16 tss_selector, int reason,
2467 bool has_error_code, u32 error_code)
38ba30ba
GN		 2468{
2469 struct decode_cache *c = &ctxt->decode;
2470 int rc;
2471
38ba30ba 2472 c->eip = ctxt->eip;
e269fb21 2473 c->dst.type = OP_NONE;
38ba30ba 2474
e269fb21
JK		 2475 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2476 has_error_code, error_code);
38ba30ba
GN		 2477
2478 if (rc == X86EMUL_CONTINUE) {
e269fb21 2479 rc = writeback(ctxt, ops);
95c55886
GN		 2480 if (rc == X86EMUL_CONTINUE)
2481 ctxt->eip = c->eip;
38ba30ba
GN		 2482 }
2483
19d04437 2484 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2485}
2486
a682e354 2487static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2488 int reg, struct operand *op)
a682e354
GN		 2489{
2490 struct decode_cache *c = &ctxt->decode;
2491 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2492
d9271123
GN		 2493 register_address_increment(c, &c->regs[reg], df * op->bytes);
2494 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2495}
2496
8b4caf66 2497int
1be3aa47 2498x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 2499{
8b4caf66 2500 u64 msr_data;
8b4caf66 2501 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2502 int rc = X86EMUL_CONTINUE;
5cd21917 2503 int saved_dst_type = c->dst.type;
8b4caf66 2504
9de41573 2505 ctxt->decode.mem_read.pos = 0;
310b5d30 2506
1161624f
GN		 2507 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2508 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2509 goto done;
2510 }
2511
d380a5e4 2512 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2513 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
d380a5e4
GN		 2514 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2515 goto done;
2516 }
2517
e92805ac 2518 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2519 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
e92805ac
GN		 2520 kvm_inject_gp(ctxt->vcpu, 0);
2521 goto done;
2522 }
2523
b9fa9d6b 2524 if (c->rep_prefix && (c->d & String)) {
5cd21917 2525 ctxt->restart = true;
b9fa9d6b 2526 /* All REP prefixes have the same first termination condition */
c73e197b 2527 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2528 string_done:
2529 ctxt->restart = false;
95c55886 2530 ctxt->eip = c->eip;
b9fa9d6b
AK		 2531 goto done;
2532 }
2533 /* The second termination condition only applies for REPE
2534 * and REPNE. Test if the repeat string operation prefix is
2535 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2536 * corresponding termination condition according to:
2537 * - if REPE/REPZ and ZF = 0 then done
2538 * - if REPNE/REPNZ and ZF = 1 then done
2539 */
2540 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2541 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2542 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2543 ((ctxt->eflags & EFLG_ZF) == 0))
2544 goto string_done;
b9fa9d6b 2545 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2546 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2547 goto string_done;
b9fa9d6b 2548 }
063db061 2549 c->eip = ctxt->eip;
b9fa9d6b
AK		 2550 }
2551
8b4caf66 2552 if (c->src.type == OP_MEM) {
9de41573 2553 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2554 c->src.valptr, c->src.bytes);
b60d513c 2555 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 2556 goto done;
2557 c->src.orig_val = c->src.val;
2558 }
2559
e35b7b9c 2560 if (c->src2.type == OP_MEM) {
9de41573
GN		 2561 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2562 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2563 if (rc != X86EMUL_CONTINUE)
2564 goto done;
2565 }
2566
8b4caf66
LV		 2567 if ((c->d & DstMask) == ImplicitOps)
2568 goto special_insn;
2569
2570
69f55cb1
GN		 2571 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2572 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2573 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2574 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2575 if (rc != X86EMUL_CONTINUE)
2576 goto done;
038e51de 2577 }
e4e03ded 2578 c->dst.orig_val = c->dst.val;
038e51de 2579
018a98db
AK		 2580special_insn:
2581
e4e03ded 2582 if (c->twobyte)
6aa8b732
AK		 2583 goto twobyte_insn;
2584
e4e03ded 2585 switch (c->b) {
6aa8b732
AK		 2586 case 0x00 ... 0x05:
2587 add: /* add */
05f086f8 2588 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2589 break;
0934ac9d 2590 case 0x06: /* push es */
79168fd1 2591 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2592 break;
2593 case 0x07: /* pop es */
0934ac9d 2594 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2595 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2596 goto done;
2597 break;
6aa8b732
AK		 2598 case 0x08 ... 0x0d:
2599 or: /* or */
05f086f8 2600 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2601 break;
0934ac9d 2602 case 0x0e: /* push cs */
79168fd1 2603 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2604 break;
6aa8b732
AK		 2605 case 0x10 ... 0x15:
2606 adc: /* adc */
05f086f8 2607 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2608 break;
0934ac9d 2609 case 0x16: /* push ss */
79168fd1 2610 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2611 break;
2612 case 0x17: /* pop ss */
0934ac9d 2613 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2614 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2615 goto done;
2616 break;
6aa8b732
AK		 2617 case 0x18 ... 0x1d:
2618 sbb: /* sbb */
05f086f8 2619 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2620 break;
0934ac9d 2621 case 0x1e: /* push ds */
79168fd1 2622 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2623 break;
2624 case 0x1f: /* pop ds */
0934ac9d 2625 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2626 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2627 goto done;
2628 break;
aa3a816b 2629 case 0x20 ... 0x25:
6aa8b732 2630 and: /* and */
05f086f8 2631 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2632 break;
2633 case 0x28 ... 0x2d:
2634 sub: /* sub */
05f086f8 2635 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2636 break;
2637 case 0x30 ... 0x35:
2638 xor: /* xor */
05f086f8 2639 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2640 break;
2641 case 0x38 ... 0x3d:
2642 cmp: /* cmp */
05f086f8 2643 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2644 break;
33615aa9
AK		 2645 case 0x40 ... 0x47: /* inc r16/r32 */
2646 emulate_1op("inc", c->dst, ctxt->eflags);
2647 break;
2648 case 0x48 ... 0x4f: /* dec r16/r32 */
2649 emulate_1op("dec", c->dst, ctxt->eflags);
2650 break;
2651 case 0x50 ... 0x57: /* push reg */
79168fd1 2652 emulate_push(ctxt, ops);
33615aa9
AK		 2653 break;
2654 case 0x58 ... 0x5f: /* pop reg */
2655 pop_instruction:
350f69dc 2656 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2657 if (rc != X86EMUL_CONTINUE)
33615aa9 2658 goto done;
33615aa9 2659 break;
abcf14b5 2660 case 0x60: /* pusha */
79168fd1 2661 emulate_pusha(ctxt, ops);
abcf14b5
MG		 2662 break;
2663 case 0x61: /* popa */
2664 rc = emulate_popa(ctxt, ops);
1b30eaa8 2665 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2666 goto done;
2667 break;
6aa8b732 2668 case 0x63: /* movsxd */
8b4caf66 2669 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2670 goto cannot_emulate;
e4e03ded 2671 c->dst.val = (s32) c->src.val;
6aa8b732 2672 break;
91ed7a0e 2673 case 0x68: /* push imm */
018a98db 2674 case 0x6a: /* push imm8 */
79168fd1 2675 emulate_push(ctxt, ops);
018a98db
AK		 2676 break;
2677 case 0x6c: /* insb */
2678 case 0x6d: /* insw/insd */
7972995b 2679 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2680 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2681 c->dst.bytes)) {
f850e2e6
GN		 2682 kvm_inject_gp(ctxt->vcpu, 0);
2683 goto done;
2684 }
7b262e90
GN		 2685 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2686 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2687 goto done; /* IO is needed, skip writeback */
2688 break;
018a98db
AK		 2689 case 0x6e: /* outsb */
2690 case 0x6f: /* outsw/outsd */
7972995b 2691 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2692 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2693 c->src.bytes)) {
f850e2e6
GN		 2694 kvm_inject_gp(ctxt->vcpu, 0);
2695 goto done;
2696 }
7972995b
GN		 2697 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2698 &c->src.val, 1, ctxt->vcpu);
2699
2700 c->dst.type = OP_NONE; /* nothing to writeback */
2701 break;
b2833e3c 2702 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2703 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2704 jmp_rel(c, c->src.val);
018a98db 2705 break;
6aa8b732 2706 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2707 switch (c->modrm_reg) {
6aa8b732
AK		 2708 case 0:
2709 goto add;
2710 case 1:
2711 goto or;
2712 case 2:
2713 goto adc;
2714 case 3:
2715 goto sbb;
2716 case 4:
2717 goto and;
2718 case 5:
2719 goto sub;
2720 case 6:
2721 goto xor;
2722 case 7:
2723 goto cmp;
2724 }
2725 break;
2726 case 0x84 ... 0x85:
05f086f8 2727 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2728 break;
2729 case 0x86 ... 0x87: /* xchg */
b13354f8 2730 xchg:
6aa8b732 2731 /* Write back the register source. */
e4e03ded 2732 switch (c->dst.bytes) {
6aa8b732 2733 case 1:
e4e03ded 2734 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2735 break;
2736 case 2:
e4e03ded 2737 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2738 break;
2739 case 4:
e4e03ded 2740 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2741 break; /* 64b reg: zero-extend */
2742 case 8:
e4e03ded 2743 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2744 break;
2745 }
2746 /*
2747 * Write back the memory destination with implicit LOCK
2748 * prefix.
2749 */
e4e03ded
LV		 2750 c->dst.val = c->src.val;
2751 c->lock_prefix = 1;
6aa8b732 2752 break;
6aa8b732 2753 case 0x88 ... 0x8b: /* mov */
7de75248 2754 goto mov;
79168fd1
GN		 2755 case 0x8c: /* mov r/m, sreg */
2756 if (c->modrm_reg > VCPU_SREG_GS) {
5e3ae6c5
GN		 2757 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2758 goto done;
38d5bc6d 2759 }
79168fd1 2760 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2761 break;
7e0b54b1 2762 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2763 c->dst.val = c->modrm_ea;
7e0b54b1 2764 break;
4257198a
GT		 2765 case 0x8e: { /* mov seg, r/m16 */
2766 uint16_t sel;
4257198a
GT		 2767
2768 sel = c->src.val;
8b9f4414 2769
c697518a
GN		 2770 if (c->modrm_reg == VCPU_SREG_CS ||
2771 c->modrm_reg > VCPU_SREG_GS) {
8b9f4414
GN		 2772 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
2773 goto done;
2774 }
2775
310b5d30 2776 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2777 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2778
2e873022 2779 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2780
2781 c->dst.type = OP_NONE; /* Disable writeback. */
2782 break;
2783 }
6aa8b732 2784 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2785 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2786 if (rc != X86EMUL_CONTINUE)
6aa8b732 2787 goto done;
6aa8b732 2788 break;
b13354f8 2789 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2790 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2791 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2792 break;
2793 }
2794 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2795 c->src.type = OP_REG;
2796 c->src.bytes = c->op_bytes;
b13354f8
MG		 2797 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2798 c->src.val = *(c->src.ptr);
2799 goto xchg;
fd2a7608 2800 case 0x9c: /* pushf */
05f086f8 2801 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2802 emulate_push(ctxt, ops);
8cdbd2c9 2803 break;
535eabcf 2804 case 0x9d: /* popf */
2b48cc75 2805 c->dst.type = OP_REG;
05f086f8 2806 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2807 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2808 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2809 if (rc != X86EMUL_CONTINUE)
2810 goto done;
2811 break;
018a98db
AK		 2812 case 0xa0 ... 0xa1: /* mov */
2813 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2814 c->dst.val = c->src.val;
2815 break;
2816 case 0xa2 ... 0xa3: /* mov */
2817 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2818 break;
6aa8b732 2819 case 0xa4 ... 0xa5: /* movs */
a682e354 2820 goto mov;
6aa8b732 2821 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2822 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2823 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2824 goto cmp;
6aa8b732 2825 case 0xaa ... 0xab: /* stos */
e4e03ded 2826 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2827 break;
2828 case 0xac ... 0xad: /* lods */
a682e354 2829 goto mov;
6aa8b732
AK		 2830 case 0xae ... 0xaf: /* scas */
2831 DPRINTF("Urk! I don't handle SCAS.\n");
2832 goto cannot_emulate;
a5e2e82b 2833 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2834 goto mov;
018a98db
AK		 2835 case 0xc0 ... 0xc1:
2836 emulate_grp2(ctxt);
2837 break;
111de5d6 2838 case 0xc3: /* ret */
cf5de4f8 2839 c->dst.type = OP_REG;
111de5d6 2840 c->dst.ptr = &c->eip;
cf5de4f8 2841 c->dst.bytes = c->op_bytes;
111de5d6 2842 goto pop_instruction;
018a98db
AK		 2843 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2844 mov:
2845 c->dst.val = c->src.val;
2846 break;
a77ab5ea
AK		 2847 case 0xcb: /* ret far */
2848 rc = emulate_ret_far(ctxt, ops);
1b30eaa8 2849 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2850 goto done;
2851 break;
018a98db
AK		 2852 case 0xd0 ... 0xd1: /* Grp2 */
2853 c->src.val = 1;
2854 emulate_grp2(ctxt);
2855 break;
2856 case 0xd2 ... 0xd3: /* Grp2 */
2857 c->src.val = c->regs[VCPU_REGS_RCX];
2858 emulate_grp2(ctxt);
2859 break;
a6a3034c
MG		 2860 case 0xe4: /* inb */
2861 case 0xe5: /* in */
cf8f70bf 2862 goto do_io_in;
a6a3034c
MG		 2863 case 0xe6: /* outb */
2864 case 0xe7: /* out */
cf8f70bf 2865 goto do_io_out;
1a52e051 2866 case 0xe8: /* call (near) */ {
d53c4777 2867 long int rel = c->src.val;
e4e03ded 2868 c->src.val = (unsigned long) c->eip;
7a957275 2869 jmp_rel(c, rel);
79168fd1 2870 emulate_push(ctxt, ops);
8cdbd2c9 2871 break;
1a52e051
NK		 2872 }
2873 case 0xe9: /* jmp rel */
954cd36f 2874 goto jmp;
414e6277
GN		 2875 case 0xea: { /* jmp far */
2876 unsigned short sel;
ea79849d 2877 jump_far:
414e6277
GN		 2878 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2879
2880 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 2881 goto done;
954cd36f 2882
414e6277
GN		 2883 c->eip = 0;
2884 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 2885 break;
414e6277 2886 }
954cd36f
GT		 2887 case 0xeb:
2888 jmp: /* jmp rel short */
7a957275 2889 jmp_rel(c, c->src.val);
a01af5ec 2890 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2891 break;
a6a3034c
MG		 2892 case 0xec: /* in al,dx */
2893 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 2894 c->src.val = c->regs[VCPU_REGS_RDX];
2895 do_io_in:
2896 c->dst.bytes = min(c->dst.bytes, 4u);
2897 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
2898 kvm_inject_gp(ctxt->vcpu, 0);
2899 goto done;
2900 }
7b262e90
GN		 2901 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
2902 &c->dst.val))
cf8f70bf
GN		 2903 goto done; /* IO is needed */
2904 break;
a6a3034c
MG		 2905 case 0xee: /* out al,dx */
2906 case 0xef: /* out (e/r)ax,dx */
cf8f70bf
GN		 2907 c->src.val = c->regs[VCPU_REGS_RDX];
2908 do_io_out:
2909 c->dst.bytes = min(c->dst.bytes, 4u);
2910 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
f850e2e6
GN		 2911 kvm_inject_gp(ctxt->vcpu, 0);
2912 goto done;
2913 }
cf8f70bf
GN		 2914 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
2915 ctxt->vcpu);
2916 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 2917 break;
111de5d6 2918 case 0xf4: /* hlt */
ad312c7c 2919 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2920 break;
111de5d6
AK		 2921 case 0xf5: /* cmc */
2922 /* complement carry flag from eflags reg */
2923 ctxt->eflags ^= EFLG_CF;
2924 c->dst.type = OP_NONE; /* Disable writeback. */
2925 break;
018a98db 2926 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 2927 if (!emulate_grp3(ctxt, ops))
2928 goto cannot_emulate;
018a98db 2929 break;
111de5d6
AK		 2930 case 0xf8: /* clc */
2931 ctxt->eflags &= ~EFLG_CF;
2932 c->dst.type = OP_NONE; /* Disable writeback. */
2933 break;
2934 case 0xfa: /* cli */
9c537244 2935 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2936 kvm_inject_gp(ctxt->vcpu, 0);
2937 else {
2938 ctxt->eflags &= ~X86_EFLAGS_IF;
2939 c->dst.type = OP_NONE; /* Disable writeback. */
2940 }
111de5d6
AK		 2941 break;
2942 case 0xfb: /* sti */
9c537244 2943 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2944 kvm_inject_gp(ctxt->vcpu, 0);
2945 else {
95cb2295 2946 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 2947 ctxt->eflags |= X86_EFLAGS_IF;
2948 c->dst.type = OP_NONE; /* Disable writeback. */
2949 }
111de5d6 2950 break;
fb4616f4
MG		 2951 case 0xfc: /* cld */
2952 ctxt->eflags &= ~EFLG_DF;
2953 c->dst.type = OP_NONE; /* Disable writeback. */
2954 break;
2955 case 0xfd: /* std */
2956 ctxt->eflags |= EFLG_DF;
2957 c->dst.type = OP_NONE; /* Disable writeback. */
2958 break;
ea79849d
GN		 2959 case 0xfe: /* Grp4 */
2960 grp45:
018a98db 2961 rc = emulate_grp45(ctxt, ops);
1b30eaa8 2962 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2963 goto done;
2964 break;
ea79849d
GN		 2965 case 0xff: /* Grp5 */
2966 if (c->modrm_reg == 5)
2967 goto jump_far;
2968 goto grp45;
6aa8b732 2969 }
018a98db
AK		 2970
2971writeback:
2972 rc = writeback(ctxt, ops);
1b30eaa8 2973 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 2974 goto done;
2975
5cd21917
GN		 2976 /*
2977 * restore dst type in case the decoding will be reused
2978 * (happens for string instruction )
2979 */
2980 c->dst.type = saved_dst_type;
2981
a682e354 2982 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 2983 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
2984 VCPU_REGS_RSI, &c->src);
a682e354
GN		 2985
2986 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 2987 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
2988 &c->dst);
d9271123 2989
5cd21917 2990 if (c->rep_prefix && (c->d & String)) {
7b262e90 2991 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 2992 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 2993 /*
2994 * Re-enter guest when pio read ahead buffer is empty or,
2995 * if it is not used, after each 1024 iteration.
2996 */
2997 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
2998 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 2999 ctxt->restart = false;
3000 }
9de41573
GN		 3001 /*
3002 * reset read cache here in case string instruction is restared
3003 * without decoding
3004 */
3005 ctxt->decode.mem_read.end = 0;
95c55886 3006 ctxt->eip = c->eip;
018a98db
AK		 3007
3008done:
cb404fe0 3009 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3010
3011twobyte_insn:
e4e03ded 3012 switch (c->b) {
6aa8b732 3013 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3014 switch (c->modrm_reg) {
6aa8b732
AK		 3015 u16 size;
3016 unsigned long address;
3017
aca7f966 3018 case 0: /* vmcall */
e4e03ded 3019 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3020 goto cannot_emulate;
3021
7aa81cc0 3022 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3023 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3024 goto done;
3025
33e3885d 3026 /* Let the processor re-execute the fixed hypercall */
063db061 3027 c->eip = ctxt->eip;
16286d08
AK		 3028 /* Disable writeback. */
3029 c->dst.type = OP_NONE;
aca7f966 3030 break;
6aa8b732 3031 case 2: /* lgdt */
e4e03ded
LV		 3032 rc = read_descriptor(ctxt, ops, c->src.ptr,
3033 &size, &address, c->op_bytes);
1b30eaa8 3034 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3035 goto done;
3036 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3037 /* Disable writeback. */
3038 c->dst.type = OP_NONE;
6aa8b732 3039 break;
aca7f966 3040 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3041 if (c->modrm_mod == 3) {
3042 switch (c->modrm_rm) {
3043 case 1:
3044 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3045 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3046 goto done;
3047 break;
3048 default:
3049 goto cannot_emulate;
3050 }
aca7f966 3051 } else {
e4e03ded 3052 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3053 &size, &address,
e4e03ded 3054 c->op_bytes);
1b30eaa8 3055 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3056 goto done;
3057 realmode_lidt(ctxt->vcpu, size, address);
3058 }
16286d08
AK		 3059 /* Disable writeback. */
3060 c->dst.type = OP_NONE;
6aa8b732
AK		 3061 break;
3062 case 4: /* smsw */
16286d08 3063 c->dst.bytes = 2;
52a46617 3064 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3065 break;
3066 case 6: /* lmsw */
93a152be
GN		 3067 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3068 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3069 c->dst.type = OP_NONE;
6aa8b732 3070 break;
6e1e5ffe
GN		 3071 case 5: /* not defined */
3072 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3073 goto done;
6aa8b732 3074 case 7: /* invlpg*/
69f55cb1 3075 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3076 /* Disable writeback. */
3077 c->dst.type = OP_NONE;
6aa8b732
AK		 3078 break;
3079 default:
3080 goto cannot_emulate;
3081 }
3082 break;
e99f0507 3083 case 0x05: /* syscall */
3fb1b5db 3084 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3085 if (rc != X86EMUL_CONTINUE)
3086 goto done;
e66bb2cc
AP		 3087 else
3088 goto writeback;
e99f0507 3089 break;
018a98db
AK		 3090 case 0x06:
3091 emulate_clts(ctxt->vcpu);
3092 c->dst.type = OP_NONE;
3093 break;
3094 case 0x08: /* invd */
3095 case 0x09: /* wbinvd */
3096 case 0x0d: /* GrpP (prefetch) */
3097 case 0x18: /* Grp16 (prefetch/nop) */
3098 c->dst.type = OP_NONE;
3099 break;
3100 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3101 switch (c->modrm_reg) {
3102 case 1:
3103 case 5 ... 7:
3104 case 9 ... 15:
3105 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3106 goto done;
3107 }
52a46617 3108 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3109 c->dst.type = OP_NONE; /* no writeback */
3110 break;
6aa8b732 3111 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3112 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3113 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3114 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3115 goto done;
3116 }
35aa5375 3117 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3118 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3119 break;
018a98db 3120 case 0x22: /* mov reg, cr */
0f12244f
GN		 3121 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
3122 kvm_inject_gp(ctxt->vcpu, 0);
3123 goto done;
3124 }
018a98db
AK		 3125 c->dst.type = OP_NONE;
3126 break;
6aa8b732 3127 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3128 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3129 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3130 kvm_queue_exception(ctxt->vcpu, UD_VECTOR);
3131 goto done;
3132 }
35aa5375 3133
338dbc97
GN		 3134 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3135 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3136 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3137 /* #UD condition is already handled by the code above */
3138 kvm_inject_gp(ctxt->vcpu, 0);
3139 goto done;
3140 }
3141
a01af5ec 3142 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3143 break;
018a98db
AK		 3144 case 0x30:
3145 /* wrmsr */
3146 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3147 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3148 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
c1a5d4f9 3149 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3150 goto done;
018a98db
AK		 3151 }
3152 rc = X86EMUL_CONTINUE;
3153 c->dst.type = OP_NONE;
3154 break;
3155 case 0x32:
3156 /* rdmsr */
3fb1b5db 3157 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
c1a5d4f9 3158 kvm_inject_gp(ctxt->vcpu, 0);
fd525365 3159 goto done;
018a98db
AK		 3160 } else {
3161 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3162 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3163 }
3164 rc = X86EMUL_CONTINUE;
3165 c->dst.type = OP_NONE;
3166 break;
e99f0507 3167 case 0x34: /* sysenter */
3fb1b5db 3168 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3169 if (rc != X86EMUL_CONTINUE)
3170 goto done;
8c604352
AP		 3171 else
3172 goto writeback;
e99f0507
AP		 3173 break;
3174 case 0x35: /* sysexit */
3fb1b5db 3175 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3176 if (rc != X86EMUL_CONTINUE)
3177 goto done;
4668f050
AP		 3178 else
3179 goto writeback;
e99f0507 3180 break;
6aa8b732 3181 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3182 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3183 if (!test_cc(c->b, ctxt->eflags))
3184 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3185 break;
b2833e3c 3186 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3187 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3188 jmp_rel(c, c->src.val);
018a98db
AK		 3189 c->dst.type = OP_NONE;
3190 break;
0934ac9d 3191 case 0xa0: /* push fs */
79168fd1 3192 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3193 break;
3194 case 0xa1: /* pop fs */
3195 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3196 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3197 goto done;
3198 break;
7de75248
NK		 3199 case 0xa3:
3200 bt: /* bt */
e4f8e039 3201 c->dst.type = OP_NONE;
e4e03ded
LV		 3202 /* only subword offset */
3203 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3204 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3205 break;
9bf8ea42
GT		 3206 case 0xa4: /* shld imm8, r, r/m */
3207 case 0xa5: /* shld cl, r, r/m */
3208 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3209 break;
0934ac9d 3210 case 0xa8: /* push gs */
79168fd1 3211 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3212 break;
3213 case 0xa9: /* pop gs */
3214 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3215 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3216 goto done;
3217 break;
7de75248
NK		 3218 case 0xab:
3219 bts: /* bts */
e4e03ded
LV		 3220 /* only subword offset */
3221 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3222 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3223 break;
9bf8ea42
GT		 3224 case 0xac: /* shrd imm8, r, r/m */
3225 case 0xad: /* shrd cl, r, r/m */
3226 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3227 break;
2a7c5b8b
GC		 3228 case 0xae: /* clflush */
3229 break;
6aa8b732
AK		 3230 case 0xb0 ... 0xb1: /* cmpxchg */
3231 /*
3232 * Save real source value, then compare EAX against
3233 * destination.
3234 */
e4e03ded
LV		 3235 c->src.orig_val = c->src.val;
3236 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3237 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3238 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3239 /* Success: write back to memory. */
e4e03ded 3240 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3241 } else {
3242 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3243 c->dst.type = OP_REG;
3244 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3245 }
3246 break;
6aa8b732
AK		 3247 case 0xb3:
3248 btr: /* btr */
e4e03ded
LV		 3249 /* only subword offset */
3250 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3251 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3252 break;
6aa8b732 3253 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3254 c->dst.bytes = c->op_bytes;
3255 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3256 : (u16) c->src.val;
6aa8b732 3257 break;
6aa8b732 3258 case 0xba: /* Grp8 */
e4e03ded 3259 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3260 case 0:
3261 goto bt;
3262 case 1:
3263 goto bts;
3264 case 2:
3265 goto btr;
3266 case 3:
3267 goto btc;
3268 }
3269 break;
7de75248
NK		 3270 case 0xbb:
3271 btc: /* btc */
e4e03ded
LV		 3272 /* only subword offset */
3273 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3274 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3275 break;
6aa8b732 3276 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3277 c->dst.bytes = c->op_bytes;
3278 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3279 (s16) c->src.val;
6aa8b732 3280 break;
a012e65a 3281 case 0xc3: /* movnti */
e4e03ded
LV		 3282 c->dst.bytes = c->op_bytes;
3283 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3284 (u64) c->src.val;
a012e65a 3285 break;
6aa8b732 3286 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3287 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3288 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3289 goto done;
3290 break;
6aa8b732
AK		 3291 }
3292 goto writeback;
3293
3294cannot_emulate:
e4e03ded 3295 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3296 return -1;
3297}
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