]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/emulate.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Don't mistreat edge-triggered INIT IPI as INIT de-assert. (LAPIC)
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
6aa8b732 145
d0e53325
AK		 146#define X2(x...) x, x
147#define X3(x...) X2(x), x
148#define X4(x...) X2(x), X2(x)
149#define X5(x...) X4(x), x
150#define X6(x...) X4(x), X2(x)
151#define X7(x...) X4(x), X3(x)
152#define X8(x...) X4(x), X4(x)
153#define X16(x...) X8(x), X8(x)
83babbca 154
d65b1dee 155struct opcode {
b1ea50b2
AK		 156 u64 flags : 56;
157 u64 intercept : 8;
120df890 158 union {
ef65c889 159 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 160 struct opcode *group;
161 struct group_dual *gdual;
0d7cdee8 162 struct gprefix *gprefix;
120df890 163 } u;
d09beabd 164 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 165};
166
167struct group_dual {
168 struct opcode mod012[8];
169 struct opcode mod3[8];
d65b1dee
AK		 170};
171
0d7cdee8
AK		 172struct gprefix {
173 struct opcode pfx_no;
174 struct opcode pfx_66;
175 struct opcode pfx_f2;
176 struct opcode pfx_f3;
177};
178
6aa8b732 179/* EFLAGS bit definitions. */
d4c6a154
GN		 180#define EFLG_ID (1<<21)
181#define EFLG_VIP (1<<20)
182#define EFLG_VIF (1<<19)
183#define EFLG_AC (1<<18)
b1d86143
AP		 184#define EFLG_VM (1<<17)
185#define EFLG_RF (1<<16)
d4c6a154
GN		 186#define EFLG_IOPL (3<<12)
187#define EFLG_NT (1<<14)
6aa8b732
AK		 188#define EFLG_OF (1<<11)
189#define EFLG_DF (1<<10)
b1d86143 190#define EFLG_IF (1<<9)
d4c6a154 191#define EFLG_TF (1<<8)
6aa8b732
AK		 192#define EFLG_SF (1<<7)
193#define EFLG_ZF (1<<6)
194#define EFLG_AF (1<<4)
195#define EFLG_PF (1<<2)
196#define EFLG_CF (1<<0)
197
62bd430e
MG		 198#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
199#define EFLG_RESERVED_ONE_MASK 2
200
6aa8b732
AK		 201/*
202 * Instruction emulation:
203 * Most instructions are emulated directly via a fragment of inline assembly
204 * code. This allows us to save/restore EFLAGS and thus very easily pick up
205 * any modified flags.
206 */
207
05b3e0c2 208#if defined(CONFIG_X86_64)
6aa8b732
AK		 209#define _LO32 "k" /* force 32-bit operand */
210#define _STK "%%rsp" /* stack pointer */
211#elif defined(__i386__)
212#define _LO32 "" /* force 32-bit operand */
213#define _STK "%%esp" /* stack pointer */
214#endif
215
216/*
217 * These EFLAGS bits are restored from saved value during emulation, and
218 * any changes are written back to the saved value after emulation.
219 */
220#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
221
222/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 223#define _PRE_EFLAGS(_sav, _msk, _tmp) \
224 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
225 "movl %"_sav",%"_LO32 _tmp"; " \
226 "push %"_tmp"; " \
227 "push %"_tmp"; " \
228 "movl %"_msk",%"_LO32 _tmp"; " \
229 "andl %"_LO32 _tmp",("_STK"); " \
230 "pushf; " \
231 "notl %"_LO32 _tmp"; " \
232 "andl %"_LO32 _tmp",("_STK"); " \
233 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
234 "pop %"_tmp"; " \
235 "orl %"_LO32 _tmp",("_STK"); " \
236 "popf; " \
237 "pop %"_sav"; "
6aa8b732
AK		 238
239/* After executing instruction: write-back necessary bits in EFLAGS. */
240#define _POST_EFLAGS(_sav, _msk, _tmp) \
241 /* _sav |= EFLAGS & _msk; */ \
242 "pushf; " \
243 "pop %"_tmp"; " \
244 "andl %"_msk",%"_LO32 _tmp"; " \
245 "orl %"_LO32 _tmp",%"_sav"; "
246
dda96d8f
AK		 247#ifdef CONFIG_X86_64
248#define ON64(x) x
249#else
250#define ON64(x)
251#endif
252
a31b9cea 253#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 254 do { \
255 __asm__ __volatile__ ( \
256 _PRE_EFLAGS("0", "4", "2") \
257 _op _suffix " %"_x"3,%1; " \
258 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 259 : "=m" ((ctxt)->eflags), \
260 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 261 "=&r" (_tmp) \
a31b9cea 262 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 263 } while (0)
6b7ad61f
AK		 264
265
6aa8b732 266/* Raw emulation: instruction has two explicit operands. */
a31b9cea 267#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 268 do { \
269 unsigned long _tmp; \
270 \
a31b9cea 271 switch ((ctxt)->dst.bytes) { \
6b7ad61f 272 case 2: \
a31b9cea 273 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 274 break; \
275 case 4: \
a31b9cea 276 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 277 break; \
278 case 8: \
a31b9cea 279 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 280 break; \
281 } \
6aa8b732
AK		 282 } while (0)
283
a31b9cea 284#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 285 do { \
6b7ad61f 286 unsigned long _tmp; \
a31b9cea 287 switch ((ctxt)->dst.bytes) { \
6aa8b732 288 case 1: \
a31b9cea 289 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 290 break; \
291 default: \
a31b9cea 292 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 293 _wx, _wy, _lx, _ly, _qx, _qy); \
294 break; \
295 } \
296 } while (0)
297
298/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 299#define emulate_2op_SrcB(ctxt, _op) \
300 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 301
302/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 303#define emulate_2op_SrcV(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 305
306/* Source operand is word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV_nobyte(ctxt, _op) \
308 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 309
d175226a 310/* Instruction has three operands and one operand is stored in ECX register */
29053a60 311#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 312 do { \
313 unsigned long _tmp; \
761441b9
AK		 314 _type _clv = (ctxt)->src2.val; \
315 _type _srcv = (ctxt)->src.val; \
316 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 317 \
318 __asm__ __volatile__ ( \
319 _PRE_EFLAGS("0", "5", "2") \
320 _op _suffix " %4,%1 \n" \
321 _POST_EFLAGS("0", "5", "2") \
761441b9 322 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 323 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
324 ); \
325 \
761441b9
AK		 326 (ctxt)->src2.val = (unsigned long) _clv; \
327 (ctxt)->src2.val = (unsigned long) _srcv; \
328 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 329 } while (0)
330
761441b9 331#define emulate_2op_cl(ctxt, _op) \
7295261c 332 do { \
761441b9 333 switch ((ctxt)->dst.bytes) { \
7295261c 334 case 2: \
29053a60 335 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 336 break; \
337 case 4: \
29053a60 338 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 339 break; \
340 case 8: \
29053a60 341 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 342 break; \
343 } \
d175226a
GT		 344 } while (0)
345
d1eef45d 346#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 347 do { \
348 unsigned long _tmp; \
349 \
dda96d8f
AK		 350 __asm__ __volatile__ ( \
351 _PRE_EFLAGS("0", "3", "2") \
352 _op _suffix " %1; " \
353 _POST_EFLAGS("0", "3", "2") \
d1eef45d 354 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 355 "=&r" (_tmp) \
356 : "i" (EFLAGS_MASK)); \
357 } while (0)
358
359/* Instruction has only one explicit operand (no source operand). */
d1eef45d 360#define emulate_1op(ctxt, _op) \
dda96d8f 361 do { \
d1eef45d
AK		 362 switch ((ctxt)->dst.bytes) { \
363 case 1: __emulate_1op(ctxt, _op, "b"); break; \
364 case 2: __emulate_1op(ctxt, _op, "w"); break; \
365 case 4: __emulate_1op(ctxt, _op, "l"); break; \
366 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 367 } \
368 } while (0)
369
e8f2b1d6 370#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 371 do { \
372 unsigned long _tmp; \
e8f2b1d6
AK		 373 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
374 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 375 \
376 __asm__ __volatile__ ( \
377 _PRE_EFLAGS("0", "5", "1") \
378 "1: \n\t" \
379 _op _suffix " %6; " \
380 "2: \n\t" \
381 _POST_EFLAGS("0", "5", "1") \
382 ".pushsection .fixup,\"ax\" \n\t" \
383 "3: movb $1, %4 \n\t" \
384 "jmp 2b \n\t" \
385 ".popsection \n\t" \
386 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 387 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
388 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
389 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
390 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 391 } while (0)
392
3f9f53b0 393/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 394#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 395 do { \
e8f2b1d6 396 switch((ctxt)->src.bytes) { \
7295261c 397 case 1: \
e8f2b1d6 398 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 399 break; \
400 case 2: \
e8f2b1d6 401 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 402 break; \
403 case 4: \
e8f2b1d6 404 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 405 break; \
406 case 8: ON64( \
e8f2b1d6 407 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 408 break; \
409 } \
410 } while (0)
411
8a76d7f2
JR		 412static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415{
416 struct x86_instruction_info info = {
417 .intercept = intercept,
9dac77fa
AK		 418 .rep_prefix = ctxt->rep_prefix,
419 .modrm_mod = ctxt->modrm_mod,
420 .modrm_reg = ctxt->modrm_reg,
421 .modrm_rm = ctxt->modrm_rm,
422 .src_val = ctxt->src.val64,
423 .src_bytes = ctxt->src.bytes,
424 .dst_bytes = ctxt->dst.bytes,
425 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 426 .next_rip = ctxt->eip,
427 };
428
2953538e 429 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 430}
431
9dac77fa 432static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 433{
9dac77fa 434 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 435}
436
6aa8b732 437/* Access/update address held in a register, based on addressing mode. */
e4706772 438static inline unsigned long
9dac77fa 439address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 440{
9dac77fa 441 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 442 return reg;
443 else
9dac77fa 444 return reg & ad_mask(ctxt);
e4706772
HH		 445}
446
447static inline unsigned long
9dac77fa 448register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 449{
9dac77fa 450 return address_mask(ctxt, reg);
e4706772
HH		 451}
452
7a957275 453static inline void
9dac77fa 454register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 455{
9dac77fa 456 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 457 *reg += inc;
458 else
9dac77fa 459 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 460}
6aa8b732 461
9dac77fa 462static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 463{
9dac77fa 464 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 465}
098c937b 466
56697687
AK		 467static u32 desc_limit_scaled(struct desc_struct *desc)
468{
469 u32 limit = get_desc_limit(desc);
470
471 return desc->g ? (limit << 12) | 0xfff : limit;
472}
473
9dac77fa 474static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 475{
9dac77fa
AK		 476 ctxt->has_seg_override = true;
477 ctxt->seg_override = seg;
7a5b56df
AK		 478}
479
7b105ca2 480static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 481{
482 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
483 return 0;
484
7b105ca2 485 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 486}
487
9dac77fa 488static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 489{
9dac77fa 490 if (!ctxt->has_seg_override)
7a5b56df
AK		 491 return 0;
492
9dac77fa 493 return ctxt->seg_override;
7a5b56df
AK		 494}
495
35d3d4a1
AK		 496static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
497 u32 error, bool valid)
54b8486f 498{
da9cb575
AK		 499 ctxt->exception.vector = vec;
500 ctxt->exception.error_code = error;
501 ctxt->exception.error_code_valid = valid;
35d3d4a1 502 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 503}
504
3b88e41a
JR		 505static int emulate_db(struct x86_emulate_ctxt *ctxt)
506{
507 return emulate_exception(ctxt, DB_VECTOR, 0, false);
508}
509
35d3d4a1 510static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 511{
35d3d4a1 512 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 513}
514
618ff15d
AK		 515static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
516{
517 return emulate_exception(ctxt, SS_VECTOR, err, true);
518}
519
35d3d4a1 520static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 521{
35d3d4a1 522 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 523}
524
35d3d4a1 525static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 528}
529
34d1f490
AK		 530static int emulate_de(struct x86_emulate_ctxt *ctxt)
531{
35d3d4a1 532 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 533}
534
1253791d
AK		 535static int emulate_nm(struct x86_emulate_ctxt *ctxt)
536{
537 return emulate_exception(ctxt, NM_VECTOR, 0, false);
538}
539
1aa36616
AK		 540static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
541{
542 u16 selector;
543 struct desc_struct desc;
544
545 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
546 return selector;
547}
548
549static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
550 unsigned seg)
551{
552 u16 dummy;
553 u32 base3;
554 struct desc_struct desc;
555
556 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
557 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
558}
559
3d9b938e 560static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 561 struct segmented_address addr,
3d9b938e 562 unsigned size, bool write, bool fetch,
52fd8b44
AK		 563 ulong *linear)
564{
618ff15d
AK		 565 struct desc_struct desc;
566 bool usable;
52fd8b44 567 ulong la;
618ff15d 568 u32 lim;
1aa36616 569 u16 sel;
618ff15d 570 unsigned cpl, rpl;
52fd8b44 571
7b105ca2 572 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 573 switch (ctxt->mode) {
574 case X86EMUL_MODE_REAL:
575 break;
576 case X86EMUL_MODE_PROT64:
577 if (((signed long)la << 16) >> 16 != la)
578 return emulate_gp(ctxt, 0);
579 break;
580 default:
1aa36616
AK		 581 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
582 addr.seg);
618ff15d
AK		 583 if (!usable)
584 goto bad;
585 /* code segment or read-only data segment */
586 if (((desc.type & 8) || !(desc.type & 2)) && write)
587 goto bad;
588 /* unreadable code segment */
3d9b938e 589 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 590 goto bad;
591 lim = desc_limit_scaled(&desc);
592 if ((desc.type & 8) || !(desc.type & 4)) {
593 /* expand-up segment */
594 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
595 goto bad;
596 } else {
597 /* exapand-down segment */
598 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
599 goto bad;
600 lim = desc.d ? 0xffffffff : 0xffff;
601 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
602 goto bad;
603 }
717746e3 604 cpl = ctxt->ops->cpl(ctxt);
1aa36616 605 rpl = sel & 3;
618ff15d
AK		 606 cpl = max(cpl, rpl);
607 if (!(desc.type & 8)) {
608 /* data segment */
609 if (cpl > desc.dpl)
610 goto bad;
611 } else if ((desc.type & 8) && !(desc.type & 4)) {
612 /* nonconforming code segment */
613 if (cpl != desc.dpl)
614 goto bad;
615 } else if ((desc.type & 8) && (desc.type & 4)) {
616 /* conforming code segment */
617 if (cpl < desc.dpl)
618 goto bad;
619 }
620 break;
621 }
9dac77fa 622 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 623 la &= (u32)-1;
624 *linear = la;
625 return X86EMUL_CONTINUE;
618ff15d
AK		 626bad:
627 if (addr.seg == VCPU_SREG_SS)
628 return emulate_ss(ctxt, addr.seg);
629 else
630 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 631}
632
3d9b938e
NE		 633static int linearize(struct x86_emulate_ctxt *ctxt,
634 struct segmented_address addr,
635 unsigned size, bool write,
636 ulong *linear)
637{
638 return __linearize(ctxt, addr, size, write, false, linear);
639}
640
641
3ca3ac4d
AK		 642static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
643 struct segmented_address addr,
644 void *data,
645 unsigned size)
646{
9fa088f4
AK		 647 int rc;
648 ulong linear;
649
83b8795a 650 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 651 if (rc != X86EMUL_CONTINUE)
652 return rc;
0f65dd70 653 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 654}
655
807941b1
TY		 656/*
657 * Fetch the next byte of the instruction being emulated which is pointed to
658 * by ctxt->_eip, then increment ctxt->_eip.
659 *
660 * Also prefetch the remaining bytes of the instruction without crossing page
661 * boundary if they are not in fetch_cache yet.
662 */
663static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 664{
9dac77fa 665 struct fetch_cache *fc = &ctxt->fetch;
62266869 666 int rc;
2fb53ad8 667 int size, cur_size;
62266869 668
807941b1 669 if (ctxt->_eip == fc->end) {
3d9b938e 670 unsigned long linear;
807941b1
TY		 671 struct segmented_address addr = { .seg = VCPU_SREG_CS,
672 .ea = ctxt->_eip };
2fb53ad8 673 cur_size = fc->end - fc->start;
807941b1
TY		 674 size = min(15UL - cur_size,
675 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 676 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 677 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 678 return rc;
ef5d75cc
TY		 679 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
680 size, &ctxt->exception);
7d88bb48 681 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 682 return rc;
2fb53ad8 683 fc->end += size;
62266869 684 }
807941b1
TY		 685 *dest = fc->data[ctxt->_eip - fc->start];
686 ctxt->_eip++;
3e2815e9 687 return X86EMUL_CONTINUE;
62266869
AK		 688}
689
690static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 691 void *dest, unsigned size)
62266869 692{
3e2815e9 693 int rc;
62266869 694
eb3c79e6 695 /* x86 instructions are limited to 15 bytes. */
7d88bb48 696 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 697 return X86EMUL_UNHANDLEABLE;
62266869 698 while (size--) {
807941b1 699 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 700 if (rc != X86EMUL_CONTINUE)
62266869
AK		 701 return rc;
702 }
3e2815e9 703 return X86EMUL_CONTINUE;
62266869
AK		 704}
705
67cbc90d 706/* Fetch next part of the instruction being emulated. */
e85a1085 707#define insn_fetch(_type, _ctxt) \
67cbc90d 708({ unsigned long _x; \
e85a1085 709 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 710 if (rc != X86EMUL_CONTINUE) \
711 goto done; \
67cbc90d
TY		 712 (_type)_x; \
713})
714
807941b1
TY		 715#define insn_fetch_arr(_arr, _size, _ctxt) \
716({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 717 if (rc != X86EMUL_CONTINUE) \
718 goto done; \
67cbc90d
TY		 719})
720
1e3c5cb0
RR		 721/*
722 * Given the 'reg' portion of a ModRM byte, and a register block, return a
723 * pointer into the block that addresses the relevant register.
724 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
725 */
726static void *decode_register(u8 modrm_reg, unsigned long *regs,
727 int highbyte_regs)
6aa8b732
AK		 728{
729 void *p;
730
731 p = &regs[modrm_reg];
732 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
733 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
734 return p;
735}
736
737static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 738 struct segmented_address addr,
6aa8b732
AK		 739 u16 *size, unsigned long *address, int op_bytes)
740{
741 int rc;
742
743 if (op_bytes == 2)
744 op_bytes = 3;
745 *address = 0;
3ca3ac4d 746 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 747 if (rc != X86EMUL_CONTINUE)
6aa8b732 748 return rc;
30b31ab6 749 addr.ea += 2;
3ca3ac4d 750 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 751 return rc;
752}
753
bbe9abbd
NK		 754static int test_cc(unsigned int condition, unsigned int flags)
755{
756 int rc = 0;
757
758 switch ((condition & 15) >> 1) {
759 case 0: /* o */
760 rc |= (flags & EFLG_OF);
761 break;
762 case 1: /* b/c/nae */
763 rc |= (flags & EFLG_CF);
764 break;
765 case 2: /* z/e */
766 rc |= (flags & EFLG_ZF);
767 break;
768 case 3: /* be/na */
769 rc |= (flags & (EFLG_CF|EFLG_ZF));
770 break;
771 case 4: /* s */
772 rc |= (flags & EFLG_SF);
773 break;
774 case 5: /* p/pe */
775 rc |= (flags & EFLG_PF);
776 break;
777 case 7: /* le/ng */
778 rc |= (flags & EFLG_ZF);
779 /* fall through */
780 case 6: /* l/nge */
781 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
782 break;
783 }
784
785 /* Odd condition identifiers (lsb == 1) have inverted sense. */
786 return (!!rc ^ (condition & 1));
787}
788
91ff3cb4
AK		 789static void fetch_register_operand(struct operand *op)
790{
791 switch (op->bytes) {
792 case 1:
793 op->val = *(u8 *)op->addr.reg;
794 break;
795 case 2:
796 op->val = *(u16 *)op->addr.reg;
797 break;
798 case 4:
799 op->val = *(u32 *)op->addr.reg;
800 break;
801 case 8:
802 op->val = *(u64 *)op->addr.reg;
803 break;
804 }
805}
806
1253791d
AK		 807static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
808{
809 ctxt->ops->get_fpu(ctxt);
810 switch (reg) {
811 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
812 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
813 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
814 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
815 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
816 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
817 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
818 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
819#ifdef CONFIG_X86_64
820 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
821 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
822 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
823 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
824 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
825 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
826 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
827 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
828#endif
829 default: BUG();
830 }
831 ctxt->ops->put_fpu(ctxt);
832}
833
834static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
835 int reg)
836{
837 ctxt->ops->get_fpu(ctxt);
838 switch (reg) {
839 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
840 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
841 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
842 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
843 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
844 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
845 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
846 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
847#ifdef CONFIG_X86_64
848 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
849 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
850 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
851 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
852 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
853 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
854 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
855 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
856#endif
857 default: BUG();
858 }
859 ctxt->ops->put_fpu(ctxt);
860}
861
862static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 863 struct operand *op)
3c118e24 864{
9dac77fa
AK		 865 unsigned reg = ctxt->modrm_reg;
866 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 867
9dac77fa
AK		 868 if (!(ctxt->d & ModRM))
869 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 870
9dac77fa 871 if (ctxt->d & Sse) {
1253791d
AK		 872 op->type = OP_XMM;
873 op->bytes = 16;
874 op->addr.xmm = reg;
875 read_sse_reg(ctxt, &op->vec_val, reg);
876 return;
877 }
878
3c118e24 879 op->type = OP_REG;
2adb5ad9 880 if (ctxt->d & ByteOp) {
9dac77fa 881 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 882 op->bytes = 1;
883 } else {
9dac77fa
AK		 884 op->addr.reg = decode_register(reg, ctxt->regs, 0);
885 op->bytes = ctxt->op_bytes;
3c118e24 886 }
91ff3cb4 887 fetch_register_operand(op);
3c118e24
AK		 888 op->orig_val = op->val;
889}
890
1c73ef66 891static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 892 struct operand *op)
1c73ef66 893{
1c73ef66 894 u8 sib;
f5b4edcd 895 int index_reg = 0, base_reg = 0, scale;
3e2815e9 896 int rc = X86EMUL_CONTINUE;
2dbd0dd7 897 ulong modrm_ea = 0;
1c73ef66 898
9dac77fa
AK		 899 if (ctxt->rex_prefix) {
900 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
901 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
902 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 903 }
904
e85a1085 905 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 906 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
907 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
908 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
909 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 910
9dac77fa 911 if (ctxt->modrm_mod == 3) {
2dbd0dd7 912 op->type = OP_REG;
9dac77fa
AK		 913 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
914 op->addr.reg = decode_register(ctxt->modrm_rm,
915 ctxt->regs, ctxt->d & ByteOp);
916 if (ctxt->d & Sse) {
1253791d
AK		 917 op->type = OP_XMM;
918 op->bytes = 16;
9dac77fa
AK		 919 op->addr.xmm = ctxt->modrm_rm;
920 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 921 return rc;
922 }
2dbd0dd7 923 fetch_register_operand(op);
1c73ef66
AK		 924 return rc;
925 }
926
2dbd0dd7
AK		 927 op->type = OP_MEM;
928
9dac77fa
AK		 929 if (ctxt->ad_bytes == 2) {
930 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
931 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
932 unsigned si = ctxt->regs[VCPU_REGS_RSI];
933 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 934
935 /* 16-bit ModR/M decode. */
9dac77fa 936 switch (ctxt->modrm_mod) {
1c73ef66 937 case 0:
9dac77fa 938 if (ctxt->modrm_rm == 6)
e85a1085 939 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 940 break;
941 case 1:
e85a1085 942 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 943 break;
944 case 2:
e85a1085 945 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 946 break;
947 }
9dac77fa 948 switch (ctxt->modrm_rm) {
1c73ef66 949 case 0:
2dbd0dd7 950 modrm_ea += bx + si;
1c73ef66
AK		 951 break;
952 case 1:
2dbd0dd7 953 modrm_ea += bx + di;
1c73ef66
AK		 954 break;
955 case 2:
2dbd0dd7 956 modrm_ea += bp + si;
1c73ef66
AK		 957 break;
958 case 3:
2dbd0dd7 959 modrm_ea += bp + di;
1c73ef66
AK		 960 break;
961 case 4:
2dbd0dd7 962 modrm_ea += si;
1c73ef66
AK		 963 break;
964 case 5:
2dbd0dd7 965 modrm_ea += di;
1c73ef66
AK		 966 break;
967 case 6:
9dac77fa 968 if (ctxt->modrm_mod != 0)
2dbd0dd7 969 modrm_ea += bp;
1c73ef66
AK		 970 break;
971 case 7:
2dbd0dd7 972 modrm_ea += bx;
1c73ef66
AK		 973 break;
974 }
9dac77fa
AK		 975 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
976 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
977 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 978 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 979 } else {
980 /* 32/64-bit ModR/M decode. */
9dac77fa 981 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 982 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 983 index_reg |= (sib >> 3) & 7;
984 base_reg |= sib & 7;
985 scale = sib >> 6;
986
9dac77fa 987 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 988 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 989 else
9dac77fa 990 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 991 if (index_reg != 4)
9dac77fa
AK		 992 modrm_ea += ctxt->regs[index_reg] << scale;
993 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 994 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 995 ctxt->rip_relative = 1;
84411d85 996 } else
9dac77fa
AK		 997 modrm_ea += ctxt->regs[ctxt->modrm_rm];
998 switch (ctxt->modrm_mod) {
1c73ef66 999 case 0:
9dac77fa 1000 if (ctxt->modrm_rm == 5)
e85a1085 1001 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1002 break;
1003 case 1:
e85a1085 1004 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1005 break;
1006 case 2:
e85a1085 1007 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1008 break;
1009 }
1010 }
90de84f5 1011 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1012done:
1013 return rc;
1014}
1015
1016static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1017 struct operand *op)
1c73ef66 1018{
3e2815e9 1019 int rc = X86EMUL_CONTINUE;
1c73ef66 1020
2dbd0dd7 1021 op->type = OP_MEM;
9dac77fa 1022 switch (ctxt->ad_bytes) {
1c73ef66 1023 case 2:
e85a1085 1024 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1025 break;
1026 case 4:
e85a1085 1027 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1028 break;
1029 case 8:
e85a1085 1030 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1031 break;
1032 }
1033done:
1034 return rc;
1035}
1036
9dac77fa 1037static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1038{
7129eeca 1039 long sv = 0, mask;
35c843c4 1040
9dac77fa
AK		 1041 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1042 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1043
9dac77fa
AK		 1044 if (ctxt->src.bytes == 2)
1045 sv = (s16)ctxt->src.val & (s16)mask;
1046 else if (ctxt->src.bytes == 4)
1047 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1048
9dac77fa 1049 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1050 }
ba7ff2b7
WY		 1051
1052 /* only subword offset */
9dac77fa 1053 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1054}
1055
dde7e6d1 1056static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1057 unsigned long addr, void *dest, unsigned size)
6aa8b732 1058{
dde7e6d1 1059 int rc;
9dac77fa 1060 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1061
dde7e6d1
AK		 1062 while (size) {
1063 int n = min(size, 8u);
1064 size -= n;
1065 if (mc->pos < mc->end)
1066 goto read_cached;
5cd21917 1067
7b105ca2
TY		 1068 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1069 &ctxt->exception);
dde7e6d1
AK		 1070 if (rc != X86EMUL_CONTINUE)
1071 return rc;
1072 mc->end += n;
6aa8b732 1073
dde7e6d1
AK		 1074 read_cached:
1075 memcpy(dest, mc->data + mc->pos, n);
1076 mc->pos += n;
1077 dest += n;
1078 addr += n;
6aa8b732 1079 }
dde7e6d1
AK		 1080 return X86EMUL_CONTINUE;
1081}
6aa8b732 1082
3ca3ac4d
AK		 1083static int segmented_read(struct x86_emulate_ctxt *ctxt,
1084 struct segmented_address addr,
1085 void *data,
1086 unsigned size)
1087{
9fa088f4
AK		 1088 int rc;
1089 ulong linear;
1090
83b8795a 1091 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1092 if (rc != X86EMUL_CONTINUE)
1093 return rc;
7b105ca2 1094 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1095}
1096
1097static int segmented_write(struct x86_emulate_ctxt *ctxt,
1098 struct segmented_address addr,
1099 const void *data,
1100 unsigned size)
1101{
9fa088f4
AK		 1102 int rc;
1103 ulong linear;
1104
83b8795a 1105 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1106 if (rc != X86EMUL_CONTINUE)
1107 return rc;
0f65dd70
AK		 1108 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1109 &ctxt->exception);
3ca3ac4d
AK		 1110}
1111
1112static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1113 struct segmented_address addr,
1114 const void *orig_data, const void *data,
1115 unsigned size)
1116{
9fa088f4
AK		 1117 int rc;
1118 ulong linear;
1119
83b8795a 1120 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1121 if (rc != X86EMUL_CONTINUE)
1122 return rc;
0f65dd70
AK		 1123 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1124 size, &ctxt->exception);
3ca3ac4d
AK		 1125}
1126
dde7e6d1 1127static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1128 unsigned int size, unsigned short port,
1129 void *dest)
1130{
9dac77fa 1131 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1132
dde7e6d1 1133 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1134 unsigned int in_page, n;
9dac77fa
AK		 1135 unsigned int count = ctxt->rep_prefix ?
1136 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1137 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1138 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1139 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1140 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1141 count);
1142 if (n == 0)
1143 n = 1;
1144 rc->pos = rc->end = 0;
7b105ca2 1145 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1146 return 0;
1147 rc->end = n * size;
6aa8b732
AK		 1148 }
1149
dde7e6d1
AK		 1150 memcpy(dest, rc->data + rc->pos, size);
1151 rc->pos += size;
1152 return 1;
1153}
6aa8b732 1154
dde7e6d1 1155static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1156 u16 selector, struct desc_ptr *dt)
1157{
7b105ca2
TY		 1158 struct x86_emulate_ops *ops = ctxt->ops;
1159
dde7e6d1
AK		 1160 if (selector & 1 << 2) {
1161 struct desc_struct desc;
1aa36616
AK		 1162 u16 sel;
1163
dde7e6d1 1164 memset (dt, 0, sizeof *dt);
1aa36616 1165 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1166 return;
e09d082c 1167
dde7e6d1
AK		 1168 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1169 dt->address = get_desc_base(&desc);
1170 } else
4bff1e86 1171 ops->get_gdt(ctxt, dt);
dde7e6d1 1172}
120df890 1173
dde7e6d1
AK		 1174/* allowed just for 8 bytes segments */
1175static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1176 u16 selector, struct desc_struct *desc)
1177{
1178 struct desc_ptr dt;
1179 u16 index = selector >> 3;
dde7e6d1 1180 ulong addr;
120df890 1181
7b105ca2 1182 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1183
35d3d4a1
AK		 1184 if (dt.size < index * 8 + 7)
1185 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1186
7b105ca2
TY		 1187 addr = dt.address + index * 8;
1188 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1189 &ctxt->exception);
dde7e6d1 1190}
ef65c889 1191
dde7e6d1
AK		 1192/* allowed just for 8 bytes segments */
1193static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1194 u16 selector, struct desc_struct *desc)
1195{
1196 struct desc_ptr dt;
1197 u16 index = selector >> 3;
dde7e6d1 1198 ulong addr;
6aa8b732 1199
7b105ca2 1200 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1201
35d3d4a1
AK		 1202 if (dt.size < index * 8 + 7)
1203 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1204
dde7e6d1 1205 addr = dt.address + index * 8;
7b105ca2
TY		 1206 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1207 &ctxt->exception);
dde7e6d1 1208}
c7e75a3d 1209
5601d05b 1210/* Does not support long mode */
dde7e6d1 1211static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1212 u16 selector, int seg)
1213{
1214 struct desc_struct seg_desc;
1215 u8 dpl, rpl, cpl;
1216 unsigned err_vec = GP_VECTOR;
1217 u32 err_code = 0;
1218 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1219 int ret;
69f55cb1 1220
dde7e6d1 1221 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1222
dde7e6d1
AK		 1223 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1224 || ctxt->mode == X86EMUL_MODE_REAL) {
1225 /* set real mode segment descriptor */
1226 set_desc_base(&seg_desc, selector << 4);
1227 set_desc_limit(&seg_desc, 0xffff);
1228 seg_desc.type = 3;
1229 seg_desc.p = 1;
1230 seg_desc.s = 1;
1231 goto load;
1232 }
1233
1234 /* NULL selector is not valid for TR, CS and SS */
1235 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1236 && null_selector)
1237 goto exception;
1238
1239 /* TR should be in GDT only */
1240 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1241 goto exception;
1242
1243 if (null_selector) /* for NULL selector skip all following checks */
1244 goto load;
1245
7b105ca2 1246 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1247 if (ret != X86EMUL_CONTINUE)
1248 return ret;
1249
1250 err_code = selector & 0xfffc;
1251 err_vec = GP_VECTOR;
1252
1253 /* can't load system descriptor into segment selecor */
1254 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1255 goto exception;
1256
1257 if (!seg_desc.p) {
1258 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1259 goto exception;
1260 }
1261
1262 rpl = selector & 3;
1263 dpl = seg_desc.dpl;
7b105ca2 1264 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1265
1266 switch (seg) {
1267 case VCPU_SREG_SS:
1268 /*
1269 * segment is not a writable data segment or segment
1270 * selector's RPL != CPL or segment selector's RPL != CPL
1271 */
1272 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1273 goto exception;
6aa8b732 1274 break;
dde7e6d1
AK		 1275 case VCPU_SREG_CS:
1276 if (!(seg_desc.type & 8))
1277 goto exception;
1278
1279 if (seg_desc.type & 4) {
1280 /* conforming */
1281 if (dpl > cpl)
1282 goto exception;
1283 } else {
1284 /* nonconforming */
1285 if (rpl > cpl || dpl != cpl)
1286 goto exception;
1287 }
1288 /* CS(RPL) <- CPL */
1289 selector = (selector & 0xfffc) | cpl;
6aa8b732 1290 break;
dde7e6d1
AK		 1291 case VCPU_SREG_TR:
1292 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1293 goto exception;
1294 break;
1295 case VCPU_SREG_LDTR:
1296 if (seg_desc.s || seg_desc.type != 2)
1297 goto exception;
1298 break;
1299 default: /* DS, ES, FS, or GS */
4e62417b 1300 /*
dde7e6d1
AK		 1301 * segment is not a data or readable code segment or
1302 * ((segment is a data or nonconforming code segment)
1303 * and (both RPL and CPL > DPL))
4e62417b 1304 */
dde7e6d1
AK		 1305 if ((seg_desc.type & 0xa) == 0x8 ||
1306 (((seg_desc.type & 0xc) != 0xc) &&
1307 (rpl > dpl && cpl > dpl)))
1308 goto exception;
6aa8b732 1309 break;
dde7e6d1
AK		 1310 }
1311
1312 if (seg_desc.s) {
1313 /* mark segment as accessed */
1314 seg_desc.type |= 1;
7b105ca2 1315 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1316 if (ret != X86EMUL_CONTINUE)
1317 return ret;
1318 }
1319load:
7b105ca2 1320 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1321 return X86EMUL_CONTINUE;
1322exception:
1323 emulate_exception(ctxt, err_vec, err_code, true);
1324 return X86EMUL_PROPAGATE_FAULT;
1325}
1326
31be40b3
WY		 1327static void write_register_operand(struct operand *op)
1328{
1329 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1330 switch (op->bytes) {
1331 case 1:
1332 *(u8 *)op->addr.reg = (u8)op->val;
1333 break;
1334 case 2:
1335 *(u16 *)op->addr.reg = (u16)op->val;
1336 break;
1337 case 4:
1338 *op->addr.reg = (u32)op->val;
1339 break; /* 64b: zero-extend */
1340 case 8:
1341 *op->addr.reg = op->val;
1342 break;
1343 }
1344}
1345
adddcecf 1346static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1347{
1348 int rc;
dde7e6d1 1349
9dac77fa 1350 switch (ctxt->dst.type) {
dde7e6d1 1351 case OP_REG:
9dac77fa 1352 write_register_operand(&ctxt->dst);
6aa8b732 1353 break;
dde7e6d1 1354 case OP_MEM:
9dac77fa 1355 if (ctxt->lock_prefix)
3ca3ac4d 1356 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1357 ctxt->dst.addr.mem,
1358 &ctxt->dst.orig_val,
1359 &ctxt->dst.val,
1360 ctxt->dst.bytes);
341de7e3 1361 else
3ca3ac4d 1362 rc = segmented_write(ctxt,
9dac77fa
AK		 1363 ctxt->dst.addr.mem,
1364 &ctxt->dst.val,
1365 ctxt->dst.bytes);
dde7e6d1
AK		 1366 if (rc != X86EMUL_CONTINUE)
1367 return rc;
a682e354 1368 break;
1253791d 1369 case OP_XMM:
9dac77fa 1370 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1371 break;
dde7e6d1
AK		 1372 case OP_NONE:
1373 /* no writeback */
414e6277 1374 break;
dde7e6d1 1375 default:
414e6277 1376 break;
6aa8b732 1377 }
dde7e6d1
AK		 1378 return X86EMUL_CONTINUE;
1379}
6aa8b732 1380
4487b3b4 1381static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1382{
4179bb02 1383 struct segmented_address addr;
0dc8d10f 1384
9dac77fa
AK		 1385 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1386 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1387 addr.seg = VCPU_SREG_SS;
1388
1389 /* Disable writeback. */
9dac77fa
AK		 1390 ctxt->dst.type = OP_NONE;
1391 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1392}
69f55cb1 1393
dde7e6d1 1394static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1395 void *dest, int len)
1396{
dde7e6d1 1397 int rc;
90de84f5 1398 struct segmented_address addr;
8b4caf66 1399
9dac77fa 1400 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1401 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1402 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1403 if (rc != X86EMUL_CONTINUE)
1404 return rc;
1405
9dac77fa 1406 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1407 return rc;
8b4caf66
LV		 1408}
1409
c54fe504
TY		 1410static int em_pop(struct x86_emulate_ctxt *ctxt)
1411{
9dac77fa 1412 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1413}
1414
dde7e6d1 1415static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1416 void *dest, int len)
9de41573
GN		 1417{
1418 int rc;
dde7e6d1
AK		 1419 unsigned long val, change_mask;
1420 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1421 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1422
3b9be3bf 1423 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1424 if (rc != X86EMUL_CONTINUE)
1425 return rc;
9de41573 1426
dde7e6d1
AK		 1427 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1428 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1429
dde7e6d1
AK		 1430 switch(ctxt->mode) {
1431 case X86EMUL_MODE_PROT64:
1432 case X86EMUL_MODE_PROT32:
1433 case X86EMUL_MODE_PROT16:
1434 if (cpl == 0)
1435 change_mask |= EFLG_IOPL;
1436 if (cpl <= iopl)
1437 change_mask |= EFLG_IF;
1438 break;
1439 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1440 if (iopl < 3)
1441 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1442 change_mask |= EFLG_IF;
1443 break;
1444 default: /* real mode */
1445 change_mask |= (EFLG_IOPL | EFLG_IF);
1446 break;
9de41573 1447 }
dde7e6d1
AK		 1448
1449 *(unsigned long *)dest =
1450 (ctxt->eflags & ~change_mask) | (val & change_mask);
1451
1452 return rc;
9de41573
GN		 1453}
1454
62aaa2f0
TY		 1455static int em_popf(struct x86_emulate_ctxt *ctxt)
1456{
9dac77fa
AK		 1457 ctxt->dst.type = OP_REG;
1458 ctxt->dst.addr.reg = &ctxt->eflags;
1459 ctxt->dst.bytes = ctxt->op_bytes;
1460 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1461}
1462
1cd196ea 1463static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1464{
1cd196ea
AK		 1465 int seg = ctxt->src2.val;
1466
9dac77fa 1467 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1468
4487b3b4 1469 return em_push(ctxt);
7b262e90
GN		 1470}
1471
1cd196ea 1472static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1473{
1cd196ea 1474 int seg = ctxt->src2.val;
dde7e6d1
AK		 1475 unsigned long selector;
1476 int rc;
38ba30ba 1477
9dac77fa 1478 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1479 if (rc != X86EMUL_CONTINUE)
1480 return rc;
1481
7b105ca2 1482 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1483 return rc;
38ba30ba
GN		 1484}
1485
b96a7fad 1486static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1487{
9dac77fa 1488 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1489 int rc = X86EMUL_CONTINUE;
1490 int reg = VCPU_REGS_RAX;
38ba30ba 1491
dde7e6d1
AK		 1492 while (reg <= VCPU_REGS_RDI) {
1493 (reg == VCPU_REGS_RSP) ?
9dac77fa 1494 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1495
4487b3b4 1496 rc = em_push(ctxt);
dde7e6d1
AK		 1497 if (rc != X86EMUL_CONTINUE)
1498 return rc;
38ba30ba 1499
dde7e6d1 1500 ++reg;
38ba30ba 1501 }
38ba30ba 1502
dde7e6d1 1503 return rc;
38ba30ba
GN		 1504}
1505
62aaa2f0
TY		 1506static int em_pushf(struct x86_emulate_ctxt *ctxt)
1507{
9dac77fa 1508 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1509 return em_push(ctxt);
1510}
1511
b96a7fad 1512static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1513{
dde7e6d1
AK		 1514 int rc = X86EMUL_CONTINUE;
1515 int reg = VCPU_REGS_RDI;
38ba30ba 1516
dde7e6d1
AK		 1517 while (reg >= VCPU_REGS_RAX) {
1518 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1519 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1520 ctxt->op_bytes);
dde7e6d1
AK		 1521 --reg;
1522 }
38ba30ba 1523
9dac77fa 1524 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1525 if (rc != X86EMUL_CONTINUE)
1526 break;
1527 --reg;
38ba30ba 1528 }
dde7e6d1 1529 return rc;
38ba30ba
GN		 1530}
1531
7b105ca2 1532int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1533{
7b105ca2 1534 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1535 int rc;
6e154e56
MG		 1536 struct desc_ptr dt;
1537 gva_t cs_addr;
1538 gva_t eip_addr;
1539 u16 cs, eip;
6e154e56
MG		 1540
1541 /* TODO: Add limit checks */
9dac77fa 1542 ctxt->src.val = ctxt->eflags;
4487b3b4 1543 rc = em_push(ctxt);
5c56e1cf
AK		 1544 if (rc != X86EMUL_CONTINUE)
1545 return rc;
6e154e56
MG		 1546
1547 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1548
9dac77fa 1549 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1550 rc = em_push(ctxt);
5c56e1cf
AK		 1551 if (rc != X86EMUL_CONTINUE)
1552 return rc;
6e154e56 1553
9dac77fa 1554 ctxt->src.val = ctxt->_eip;
4487b3b4 1555 rc = em_push(ctxt);
5c56e1cf
AK		 1556 if (rc != X86EMUL_CONTINUE)
1557 return rc;
1558
4bff1e86 1559 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1560
1561 eip_addr = dt.address + (irq << 2);
1562 cs_addr = dt.address + (irq << 2) + 2;
1563
0f65dd70 1564 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1565 if (rc != X86EMUL_CONTINUE)
1566 return rc;
1567
0f65dd70 1568 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1569 if (rc != X86EMUL_CONTINUE)
1570 return rc;
1571
7b105ca2 1572 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1573 if (rc != X86EMUL_CONTINUE)
1574 return rc;
1575
9dac77fa 1576 ctxt->_eip = eip;
6e154e56
MG		 1577
1578 return rc;
1579}
1580
7b105ca2 1581static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1582{
1583 switch(ctxt->mode) {
1584 case X86EMUL_MODE_REAL:
7b105ca2 1585 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1586 case X86EMUL_MODE_VM86:
1587 case X86EMUL_MODE_PROT16:
1588 case X86EMUL_MODE_PROT32:
1589 case X86EMUL_MODE_PROT64:
1590 default:
1591 /* Protected mode interrupts unimplemented yet */
1592 return X86EMUL_UNHANDLEABLE;
1593 }
1594}
1595
7b105ca2 1596static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1597{
dde7e6d1
AK		 1598 int rc = X86EMUL_CONTINUE;
1599 unsigned long temp_eip = 0;
1600 unsigned long temp_eflags = 0;
1601 unsigned long cs = 0;
1602 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1603 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1604 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1605 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1606
dde7e6d1 1607 /* TODO: Add stack limit check */
38ba30ba 1608
9dac77fa 1609 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1610
dde7e6d1
AK		 1611 if (rc != X86EMUL_CONTINUE)
1612 return rc;
38ba30ba 1613
35d3d4a1
AK		 1614 if (temp_eip & ~0xffff)
1615 return emulate_gp(ctxt, 0);
38ba30ba 1616
9dac77fa 1617 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1618
dde7e6d1
AK		 1619 if (rc != X86EMUL_CONTINUE)
1620 return rc;
38ba30ba 1621
9dac77fa 1622 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1623
dde7e6d1
AK		 1624 if (rc != X86EMUL_CONTINUE)
1625 return rc;
38ba30ba 1626
7b105ca2 1627 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1628
dde7e6d1
AK		 1629 if (rc != X86EMUL_CONTINUE)
1630 return rc;
38ba30ba 1631
9dac77fa 1632 ctxt->_eip = temp_eip;
38ba30ba 1633
38ba30ba 1634
9dac77fa 1635 if (ctxt->op_bytes == 4)
dde7e6d1 1636 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1637 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1638 ctxt->eflags &= ~0xffff;
1639 ctxt->eflags |= temp_eflags;
38ba30ba 1640 }
dde7e6d1
AK		 1641
1642 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1643 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1644
1645 return rc;
38ba30ba
GN		 1646}
1647
e01991e7 1648static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1649{
dde7e6d1
AK		 1650 switch(ctxt->mode) {
1651 case X86EMUL_MODE_REAL:
7b105ca2 1652 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1653 case X86EMUL_MODE_VM86:
1654 case X86EMUL_MODE_PROT16:
1655 case X86EMUL_MODE_PROT32:
1656 case X86EMUL_MODE_PROT64:
c37eda13 1657 default:
dde7e6d1
AK		 1658 /* iret from protected mode unimplemented yet */
1659 return X86EMUL_UNHANDLEABLE;
c37eda13 1660 }
c37eda13
WY		 1661}
1662
d2f62766
TY		 1663static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1664{
d2f62766
TY		 1665 int rc;
1666 unsigned short sel;
1667
9dac77fa 1668 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1669
7b105ca2 1670 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1671 if (rc != X86EMUL_CONTINUE)
1672 return rc;
1673
9dac77fa
AK		 1674 ctxt->_eip = 0;
1675 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1676 return X86EMUL_CONTINUE;
1677}
1678
51187683 1679static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1680{
9dac77fa 1681 switch (ctxt->modrm_reg) {
8cdbd2c9 1682 case 0: /* rol */
a31b9cea 1683 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1684 break;
1685 case 1: /* ror */
a31b9cea 1686 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1687 break;
1688 case 2: /* rcl */
a31b9cea 1689 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1690 break;
1691 case 3: /* rcr */
a31b9cea 1692 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1693 break;
1694 case 4: /* sal/shl */
1695 case 6: /* sal/shl */
a31b9cea 1696 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1697 break;
1698 case 5: /* shr */
a31b9cea 1699 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1700 break;
1701 case 7: /* sar */
a31b9cea 1702 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1703 break;
1704 }
51187683 1705 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1706}
1707
3329ece1
AK		 1708static int em_not(struct x86_emulate_ctxt *ctxt)
1709{
1710 ctxt->dst.val = ~ctxt->dst.val;
1711 return X86EMUL_CONTINUE;
1712}
1713
1714static int em_neg(struct x86_emulate_ctxt *ctxt)
1715{
1716 emulate_1op(ctxt, "neg");
1717 return X86EMUL_CONTINUE;
1718}
1719
1720static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1721{
1722 u8 ex = 0;
1723
1724 emulate_1op_rax_rdx(ctxt, "mul", ex);
1725 return X86EMUL_CONTINUE;
1726}
1727
1728static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1729{
1730 u8 ex = 0;
1731
1732 emulate_1op_rax_rdx(ctxt, "imul", ex);
1733 return X86EMUL_CONTINUE;
1734}
1735
1736static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1737{
34d1f490 1738 u8 de = 0;
8cdbd2c9 1739
3329ece1
AK		 1740 emulate_1op_rax_rdx(ctxt, "div", de);
1741 if (de)
1742 return emulate_de(ctxt);
1743 return X86EMUL_CONTINUE;
1744}
1745
1746static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1747{
1748 u8 de = 0;
1749
1750 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1751 if (de)
1752 return emulate_de(ctxt);
8c5eee30 1753 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1754}
1755
51187683 1756static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1757{
4179bb02 1758 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1759
9dac77fa 1760 switch (ctxt->modrm_reg) {
8cdbd2c9 1761 case 0: /* inc */
d1eef45d 1762 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1763 break;
1764 case 1: /* dec */
d1eef45d 1765 emulate_1op(ctxt, "dec");
8cdbd2c9 1766 break;
d19292e4
MG		 1767 case 2: /* call near abs */ {
1768 long int old_eip;
9dac77fa
AK		 1769 old_eip = ctxt->_eip;
1770 ctxt->_eip = ctxt->src.val;
1771 ctxt->src.val = old_eip;
4487b3b4 1772 rc = em_push(ctxt);
d19292e4
MG		 1773 break;
1774 }
8cdbd2c9 1775 case 4: /* jmp abs */
9dac77fa 1776 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1777 break;
d2f62766
TY		 1778 case 5: /* jmp far */
1779 rc = em_jmp_far(ctxt);
1780 break;
8cdbd2c9 1781 case 6: /* push */
4487b3b4 1782 rc = em_push(ctxt);
8cdbd2c9 1783 break;
8cdbd2c9 1784 }
4179bb02 1785 return rc;
8cdbd2c9
LV		 1786}
1787
e0dac408 1788static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1789{
9dac77fa 1790 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1791
9dac77fa
AK		 1792 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1793 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1794 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1795 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1796 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1797 } else {
9dac77fa
AK		 1798 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1799 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1800
05f086f8 1801 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1802 }
1b30eaa8 1803 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1804}
1805
ebda02c2
TY		 1806static int em_ret(struct x86_emulate_ctxt *ctxt)
1807{
9dac77fa
AK		 1808 ctxt->dst.type = OP_REG;
1809 ctxt->dst.addr.reg = &ctxt->_eip;
1810 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1811 return em_pop(ctxt);
1812}
1813
e01991e7 1814static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1815{
a77ab5ea
AK		 1816 int rc;
1817 unsigned long cs;
1818
9dac77fa 1819 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1820 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1821 return rc;
9dac77fa
AK		 1822 if (ctxt->op_bytes == 4)
1823 ctxt->_eip = (u32)ctxt->_eip;
1824 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1825 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1826 return rc;
7b105ca2 1827 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1828 return rc;
1829}
1830
e940b5c2
TY		 1831static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1832{
1833 /* Save real source value, then compare EAX against destination. */
1834 ctxt->src.orig_val = ctxt->src.val;
1835 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
1836 emulate_2op_SrcV(ctxt, "cmp");
1837
1838 if (ctxt->eflags & EFLG_ZF) {
1839 /* Success: write back to memory. */
1840 ctxt->dst.val = ctxt->src.orig_val;
1841 } else {
1842 /* Failure: write the value we saw to EAX. */
1843 ctxt->dst.type = OP_REG;
1844 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
1845 }
1846 return X86EMUL_CONTINUE;
1847}
1848
d4b4325f 1849static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1850{
d4b4325f 1851 int seg = ctxt->src2.val;
09b5f4d3
WY		 1852 unsigned short sel;
1853 int rc;
1854
9dac77fa 1855 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1856
7b105ca2 1857 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1858 if (rc != X86EMUL_CONTINUE)
1859 return rc;
1860
9dac77fa 1861 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1862 return rc;
1863}
1864
7b105ca2 1865static void
e66bb2cc 1866setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1867 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1868{
1aa36616
AK		 1869 u16 selector;
1870
79168fd1 1871 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1872 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1873 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1874
1875 cs->l = 0; /* will be adjusted later */
79168fd1 1876 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1877 cs->g = 1; /* 4kb granularity */
79168fd1 1878 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1879 cs->type = 0x0b; /* Read, Execute, Accessed */
1880 cs->s = 1;
1881 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1882 cs->p = 1;
1883 cs->d = 1;
e66bb2cc 1884
79168fd1
GN		 1885 set_desc_base(ss, 0); /* flat segment */
1886 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1887 ss->g = 1; /* 4kb granularity */
1888 ss->s = 1;
1889 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1890 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1891 ss->dpl = 0;
79168fd1 1892 ss->p = 1;
e66bb2cc
AP		 1893}
1894
c2226fc9
SB		 1895static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
1896{
1897 struct x86_emulate_ops *ops = ctxt->ops;
1898 u32 eax, ebx, ecx, edx;
1899
1900 /*
1901 * syscall should always be enabled in longmode - so only become
1902 * vendor specific (cpuid) if other modes are active...
1903 */
1904 if (ctxt->mode == X86EMUL_MODE_PROT64)
1905 return true;
1906
1907 eax = 0x00000000;
1908 ecx = 0x00000000;
1909 if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) {
1910 /*
1911 * Intel ("GenuineIntel")
1912 * remark: Intel CPUs only support "syscall" in 64bit
1913 * longmode. Also an 64bit guest with a
1914 * 32bit compat-app running will #UD !! While this
1915 * behaviour can be fixed (by emulating) into AMD
1916 * response - CPUs of AMD can't behave like Intel.
1917 */
1918 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
1919 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
1920 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
1921 return false;
1922
1923 /* AMD ("AuthenticAMD") */
1924 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
1925 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
1926 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
1927 return true;
1928
1929 /* AMD ("AMDisbetter!") */
1930 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
1931 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
1932 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
1933 return true;
1934 }
1935
1936 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
1937 return false;
1938}
1939
e01991e7 1940static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1941{
7b105ca2 1942 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1943 struct desc_struct cs, ss;
e66bb2cc 1944 u64 msr_data;
79168fd1 1945 u16 cs_sel, ss_sel;
c2ad2bb3 1946 u64 efer = 0;
e66bb2cc
AP		 1947
1948 /* syscall is not available in real mode */
2e901c4c 1949 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1950 ctxt->mode == X86EMUL_MODE_VM86)
1951 return emulate_ud(ctxt);
e66bb2cc 1952
c2226fc9
SB		 1953 if (!(em_syscall_is_enabled(ctxt)))
1954 return emulate_ud(ctxt);
1955
c2ad2bb3 1956 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1957 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1958
c2226fc9
SB		 1959 if (!(efer & EFER_SCE))
1960 return emulate_ud(ctxt);
1961
717746e3 1962 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1963 msr_data >>= 32;
79168fd1
GN		 1964 cs_sel = (u16)(msr_data & 0xfffc);
1965 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1966
c2ad2bb3 1967 if (efer & EFER_LMA) {
79168fd1 1968 cs.d = 0;
e66bb2cc
AP		 1969 cs.l = 1;
1970 }
1aa36616
AK		 1971 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1972 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1973
9dac77fa 1974 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1975 if (efer & EFER_LMA) {
e66bb2cc 1976#ifdef CONFIG_X86_64
9dac77fa 1977 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1978
717746e3 1979 ops->get_msr(ctxt,
3fb1b5db
GN		 1980 ctxt->mode == X86EMUL_MODE_PROT64 ?
1981 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1982 ctxt->_eip = msr_data;
e66bb2cc 1983
717746e3 1984 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1985 ctxt->eflags &= ~(msr_data | EFLG_RF);
1986#endif
1987 } else {
1988 /* legacy mode */
717746e3 1989 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1990 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1991
1992 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1993 }
1994
e54cfa97 1995 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1996}
1997
e01991e7 1998static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1999{
7b105ca2 2000 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2001 struct desc_struct cs, ss;
8c604352 2002 u64 msr_data;
79168fd1 2003 u16 cs_sel, ss_sel;
c2ad2bb3 2004 u64 efer = 0;
8c604352 2005
7b105ca2 2006 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2007 /* inject #GP if in real mode */
35d3d4a1
AK		 2008 if (ctxt->mode == X86EMUL_MODE_REAL)
2009 return emulate_gp(ctxt, 0);
8c604352
AP		 2010
2011 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2012 * Therefore, we inject an #UD.
2013 */
35d3d4a1
AK		 2014 if (ctxt->mode == X86EMUL_MODE_PROT64)
2015 return emulate_ud(ctxt);
8c604352 2016
7b105ca2 2017 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2018
717746e3 2019 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2020 switch (ctxt->mode) {
2021 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2022 if ((msr_data & 0xfffc) == 0x0)
2023 return emulate_gp(ctxt, 0);
8c604352
AP		 2024 break;
2025 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2026 if (msr_data == 0x0)
2027 return emulate_gp(ctxt, 0);
8c604352
AP		 2028 break;
2029 }
2030
2031 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2032 cs_sel = (u16)msr_data;
2033 cs_sel &= ~SELECTOR_RPL_MASK;
2034 ss_sel = cs_sel + 8;
2035 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2036 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2037 cs.d = 0;
8c604352
AP		 2038 cs.l = 1;
2039 }
2040
1aa36616
AK		 2041 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2042 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2043
717746e3 2044 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2045 ctxt->_eip = msr_data;
8c604352 2046
717746e3 2047 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2048 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2049
e54cfa97 2050 return X86EMUL_CONTINUE;
8c604352
AP		 2051}
2052
e01991e7 2053static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2054{
7b105ca2 2055 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2056 struct desc_struct cs, ss;
4668f050
AP		 2057 u64 msr_data;
2058 int usermode;
1249b96e 2059 u16 cs_sel = 0, ss_sel = 0;
4668f050 2060
a0044755
GN		 2061 /* inject #GP if in real mode or Virtual 8086 mode */
2062 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2063 ctxt->mode == X86EMUL_MODE_VM86)
2064 return emulate_gp(ctxt, 0);
4668f050 2065
7b105ca2 2066 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2067
9dac77fa 2068 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2069 usermode = X86EMUL_MODE_PROT64;
2070 else
2071 usermode = X86EMUL_MODE_PROT32;
2072
2073 cs.dpl = 3;
2074 ss.dpl = 3;
717746e3 2075 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2076 switch (usermode) {
2077 case X86EMUL_MODE_PROT32:
79168fd1 2078 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2079 if ((msr_data & 0xfffc) == 0x0)
2080 return emulate_gp(ctxt, 0);
79168fd1 2081 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2082 break;
2083 case X86EMUL_MODE_PROT64:
79168fd1 2084 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2085 if (msr_data == 0x0)
2086 return emulate_gp(ctxt, 0);
79168fd1
GN		 2087 ss_sel = cs_sel + 8;
2088 cs.d = 0;
4668f050
AP		 2089 cs.l = 1;
2090 break;
2091 }
79168fd1
GN		 2092 cs_sel |= SELECTOR_RPL_MASK;
2093 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2094
1aa36616
AK		 2095 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2096 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2097
9dac77fa
AK		 2098 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2099 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2100
e54cfa97 2101 return X86EMUL_CONTINUE;
4668f050
AP		 2102}
2103
7b105ca2 2104static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2105{
2106 int iopl;
2107 if (ctxt->mode == X86EMUL_MODE_REAL)
2108 return false;
2109 if (ctxt->mode == X86EMUL_MODE_VM86)
2110 return true;
2111 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2112 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2113}
2114
2115static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2116 u16 port, u16 len)
2117{
7b105ca2 2118 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2119 struct desc_struct tr_seg;
5601d05b 2120 u32 base3;
f850e2e6 2121 int r;
1aa36616 2122 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2123 unsigned mask = (1 << len) - 1;
5601d05b 2124 unsigned long base;
f850e2e6 2125
1aa36616 2126 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2127 if (!tr_seg.p)
f850e2e6 2128 return false;
79168fd1 2129 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2130 return false;
5601d05b
GN		 2131 base = get_desc_base(&tr_seg);
2132#ifdef CONFIG_X86_64
2133 base |= ((u64)base3) << 32;
2134#endif
0f65dd70 2135 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2136 if (r != X86EMUL_CONTINUE)
2137 return false;
79168fd1 2138 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2139 return false;
0f65dd70 2140 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2141 if (r != X86EMUL_CONTINUE)
2142 return false;
2143 if ((perm >> bit_idx) & mask)
2144 return false;
2145 return true;
2146}
2147
2148static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2149 u16 port, u16 len)
2150{
4fc40f07
GN		 2151 if (ctxt->perm_ok)
2152 return true;
2153
7b105ca2
TY		 2154 if (emulator_bad_iopl(ctxt))
2155 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2156 return false;
4fc40f07
GN		 2157
2158 ctxt->perm_ok = true;
2159
f850e2e6
GN		 2160 return true;
2161}
2162
38ba30ba 2163static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2164 struct tss_segment_16 *tss)
2165{
9dac77fa 2166 tss->ip = ctxt->_eip;
38ba30ba 2167 tss->flag = ctxt->eflags;
9dac77fa
AK		 2168 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2169 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2170 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2171 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2172 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2173 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2174 tss->si = ctxt->regs[VCPU_REGS_RSI];
2175 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2176
1aa36616
AK		 2177 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2178 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2179 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2180 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2181 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2182}
2183
2184static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2185 struct tss_segment_16 *tss)
2186{
38ba30ba
GN		 2187 int ret;
2188
9dac77fa 2189 ctxt->_eip = tss->ip;
38ba30ba 2190 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2191 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2192 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2193 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2194 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2195 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2196 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2197 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2198 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2199
2200 /*
2201 * SDM says that segment selectors are loaded before segment
2202 * descriptors
2203 */
1aa36616
AK		 2204 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2205 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2206 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2207 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2208 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2209
2210 /*
2211 * Now load segment descriptors. If fault happenes at this stage
2212 * it is handled in a context of new task
2213 */
7b105ca2 2214 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2215 if (ret != X86EMUL_CONTINUE)
2216 return ret;
7b105ca2 2217 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2218 if (ret != X86EMUL_CONTINUE)
2219 return ret;
7b105ca2 2220 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2221 if (ret != X86EMUL_CONTINUE)
2222 return ret;
7b105ca2 2223 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2224 if (ret != X86EMUL_CONTINUE)
2225 return ret;
7b105ca2 2226 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2227 if (ret != X86EMUL_CONTINUE)
2228 return ret;
2229
2230 return X86EMUL_CONTINUE;
2231}
2232
2233static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2234 u16 tss_selector, u16 old_tss_sel,
2235 ulong old_tss_base, struct desc_struct *new_desc)
2236{
7b105ca2 2237 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2238 struct tss_segment_16 tss_seg;
2239 int ret;
bcc55cba 2240 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2241
0f65dd70 2242 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2243 &ctxt->exception);
db297e3d 2244 if (ret != X86EMUL_CONTINUE)
38ba30ba 2245 /* FIXME: need to provide precise fault address */
38ba30ba 2246 return ret;
38ba30ba 2247
7b105ca2 2248 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2249
0f65dd70 2250 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2251 &ctxt->exception);
db297e3d 2252 if (ret != X86EMUL_CONTINUE)
38ba30ba 2253 /* FIXME: need to provide precise fault address */
38ba30ba 2254 return ret;
38ba30ba 2255
0f65dd70 2256 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2257 &ctxt->exception);
db297e3d 2258 if (ret != X86EMUL_CONTINUE)
38ba30ba 2259 /* FIXME: need to provide precise fault address */
38ba30ba 2260 return ret;
38ba30ba
GN		 2261
2262 if (old_tss_sel != 0xffff) {
2263 tss_seg.prev_task_link = old_tss_sel;
2264
0f65dd70 2265 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2266 &tss_seg.prev_task_link,
2267 sizeof tss_seg.prev_task_link,
0f65dd70 2268 &ctxt->exception);
db297e3d 2269 if (ret != X86EMUL_CONTINUE)
38ba30ba 2270 /* FIXME: need to provide precise fault address */
38ba30ba 2271 return ret;
38ba30ba
GN		 2272 }
2273
7b105ca2 2274 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2275}
2276
2277static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2278 struct tss_segment_32 *tss)
2279{
7b105ca2 2280 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2281 tss->eip = ctxt->_eip;
38ba30ba 2282 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2283 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2284 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2285 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2286 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2287 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2288 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2289 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2290 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2291
1aa36616
AK		 2292 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2293 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2294 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2295 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2296 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2297 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2298 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2299}
2300
2301static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2302 struct tss_segment_32 *tss)
2303{
38ba30ba
GN		 2304 int ret;
2305
7b105ca2 2306 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2307 return emulate_gp(ctxt, 0);
9dac77fa 2308 ctxt->_eip = tss->eip;
38ba30ba 2309 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2310 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2311 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2312 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2313 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2314 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2315 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2316 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2317 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2318
2319 /*
2320 * SDM says that segment selectors are loaded before segment
2321 * descriptors
2322 */
1aa36616
AK		 2323 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2324 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2325 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2326 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2327 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2328 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2329 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2330
2331 /*
2332 * Now load segment descriptors. If fault happenes at this stage
2333 * it is handled in a context of new task
2334 */
7b105ca2 2335 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2336 if (ret != X86EMUL_CONTINUE)
2337 return ret;
7b105ca2 2338 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2339 if (ret != X86EMUL_CONTINUE)
2340 return ret;
7b105ca2 2341 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2342 if (ret != X86EMUL_CONTINUE)
2343 return ret;
7b105ca2 2344 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2345 if (ret != X86EMUL_CONTINUE)
2346 return ret;
7b105ca2 2347 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2348 if (ret != X86EMUL_CONTINUE)
2349 return ret;
7b105ca2 2350 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2351 if (ret != X86EMUL_CONTINUE)
2352 return ret;
7b105ca2 2353 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2354 if (ret != X86EMUL_CONTINUE)
2355 return ret;
2356
2357 return X86EMUL_CONTINUE;
2358}
2359
2360static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2361 u16 tss_selector, u16 old_tss_sel,
2362 ulong old_tss_base, struct desc_struct *new_desc)
2363{
7b105ca2 2364 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2365 struct tss_segment_32 tss_seg;
2366 int ret;
bcc55cba 2367 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2368
0f65dd70 2369 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2370 &ctxt->exception);
db297e3d 2371 if (ret != X86EMUL_CONTINUE)
38ba30ba 2372 /* FIXME: need to provide precise fault address */
38ba30ba 2373 return ret;
38ba30ba 2374
7b105ca2 2375 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2376
0f65dd70 2377 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2378 &ctxt->exception);
db297e3d 2379 if (ret != X86EMUL_CONTINUE)
38ba30ba 2380 /* FIXME: need to provide precise fault address */
38ba30ba 2381 return ret;
38ba30ba 2382
0f65dd70 2383 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2384 &ctxt->exception);
db297e3d 2385 if (ret != X86EMUL_CONTINUE)
38ba30ba 2386 /* FIXME: need to provide precise fault address */
38ba30ba 2387 return ret;
38ba30ba
GN		 2388
2389 if (old_tss_sel != 0xffff) {
2390 tss_seg.prev_task_link = old_tss_sel;
2391
0f65dd70 2392 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2393 &tss_seg.prev_task_link,
2394 sizeof tss_seg.prev_task_link,
0f65dd70 2395 &ctxt->exception);
db297e3d 2396 if (ret != X86EMUL_CONTINUE)
38ba30ba 2397 /* FIXME: need to provide precise fault address */
38ba30ba 2398 return ret;
38ba30ba
GN		 2399 }
2400
7b105ca2 2401 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2402}
2403
2404static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2405 u16 tss_selector, int reason,
2406 bool has_error_code, u32 error_code)
38ba30ba 2407{
7b105ca2 2408 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2409 struct desc_struct curr_tss_desc, next_tss_desc;
2410 int ret;
1aa36616 2411 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2412 ulong old_tss_base =
4bff1e86 2413 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2414 u32 desc_limit;
38ba30ba
GN		 2415
2416 /* FIXME: old_tss_base == ~0 ? */
2417
7b105ca2 2418 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2419 if (ret != X86EMUL_CONTINUE)
2420 return ret;
7b105ca2 2421 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2422 if (ret != X86EMUL_CONTINUE)
2423 return ret;
2424
2425 /* FIXME: check that next_tss_desc is tss */
2426
2427 if (reason != TASK_SWITCH_IRET) {
2428 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2429 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2430 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2431 }
2432
ceffb459
GN		 2433 desc_limit = desc_limit_scaled(&next_tss_desc);
2434 if (!next_tss_desc.p ||
2435 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2436 desc_limit < 0x2b)) {
54b8486f 2437 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2438 return X86EMUL_PROPAGATE_FAULT;
2439 }
2440
2441 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2442 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2443 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2444 }
2445
2446 if (reason == TASK_SWITCH_IRET)
2447 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2448
2449 /* set back link to prev task only if NT bit is set in eflags
2450 note that old_tss_sel is not used afetr this point */
2451 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2452 old_tss_sel = 0xffff;
2453
2454 if (next_tss_desc.type & 8)
7b105ca2 2455 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2456 old_tss_base, &next_tss_desc);
2457 else
7b105ca2 2458 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2459 old_tss_base, &next_tss_desc);
0760d448
JK		 2460 if (ret != X86EMUL_CONTINUE)
2461 return ret;
38ba30ba
GN		 2462
2463 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2464 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2465
2466 if (reason != TASK_SWITCH_IRET) {
2467 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2468 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2469 }
2470
717746e3 2471 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2472 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2473
e269fb21 2474 if (has_error_code) {
9dac77fa
AK		 2475 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2476 ctxt->lock_prefix = 0;
2477 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2478 ret = em_push(ctxt);
e269fb21
JK		 2479 }
2480
38ba30ba
GN		 2481 return ret;
2482}
2483
2484int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2485 u16 tss_selector, int reason,
2486 bool has_error_code, u32 error_code)
38ba30ba 2487{
38ba30ba
GN		 2488 int rc;
2489
9dac77fa
AK		 2490 ctxt->_eip = ctxt->eip;
2491 ctxt->dst.type = OP_NONE;
38ba30ba 2492
7b105ca2 2493 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2494 has_error_code, error_code);
38ba30ba 2495
4179bb02 2496 if (rc == X86EMUL_CONTINUE)
9dac77fa 2497 ctxt->eip = ctxt->_eip;
38ba30ba 2498
a0c0ab2f 2499 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2500}
2501
90de84f5 2502static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2503 int reg, struct operand *op)
a682e354 2504{
a682e354
GN		 2505 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2506
9dac77fa
AK		 2507 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2508 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2509 op->addr.mem.seg = seg;
a682e354
GN		 2510}
2511
7af04fc0
AK		 2512static int em_das(struct x86_emulate_ctxt *ctxt)
2513{
7af04fc0
AK		 2514 u8 al, old_al;
2515 bool af, cf, old_cf;
2516
2517 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2518 al = ctxt->dst.val;
7af04fc0
AK		 2519
2520 old_al = al;
2521 old_cf = cf;
2522 cf = false;
2523 af = ctxt->eflags & X86_EFLAGS_AF;
2524 if ((al & 0x0f) > 9 || af) {
2525 al -= 6;
2526 cf = old_cf | (al >= 250);
2527 af = true;
2528 } else {
2529 af = false;
2530 }
2531 if (old_al > 0x99 || old_cf) {
2532 al -= 0x60;
2533 cf = true;
2534 }
2535
9dac77fa 2536 ctxt->dst.val = al;
7af04fc0 2537 /* Set PF, ZF, SF */
9dac77fa
AK		 2538 ctxt->src.type = OP_IMM;
2539 ctxt->src.val = 0;
2540 ctxt->src.bytes = 1;
a31b9cea 2541 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2542 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2543 if (cf)
2544 ctxt->eflags |= X86_EFLAGS_CF;
2545 if (af)
2546 ctxt->eflags |= X86_EFLAGS_AF;
2547 return X86EMUL_CONTINUE;
2548}
2549
d4ddafcd
TY		 2550static int em_call(struct x86_emulate_ctxt *ctxt)
2551{
2552 long rel = ctxt->src.val;
2553
2554 ctxt->src.val = (unsigned long)ctxt->_eip;
2555 jmp_rel(ctxt, rel);
2556 return em_push(ctxt);
2557}
2558
0ef753b8
AK		 2559static int em_call_far(struct x86_emulate_ctxt *ctxt)
2560{
0ef753b8
AK		 2561 u16 sel, old_cs;
2562 ulong old_eip;
2563 int rc;
2564
1aa36616 2565 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2566 old_eip = ctxt->_eip;
0ef753b8 2567
9dac77fa 2568 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2569 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2570 return X86EMUL_CONTINUE;
2571
9dac77fa
AK		 2572 ctxt->_eip = 0;
2573 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2574
9dac77fa 2575 ctxt->src.val = old_cs;
4487b3b4 2576 rc = em_push(ctxt);
0ef753b8
AK		 2577 if (rc != X86EMUL_CONTINUE)
2578 return rc;
2579
9dac77fa 2580 ctxt->src.val = old_eip;
4487b3b4 2581 return em_push(ctxt);
0ef753b8
AK		 2582}
2583
40ece7c7
AK		 2584static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2585{
40ece7c7
AK		 2586 int rc;
2587
9dac77fa
AK		 2588 ctxt->dst.type = OP_REG;
2589 ctxt->dst.addr.reg = &ctxt->_eip;
2590 ctxt->dst.bytes = ctxt->op_bytes;
2591 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2592 if (rc != X86EMUL_CONTINUE)
2593 return rc;
9dac77fa 2594 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2595 return X86EMUL_CONTINUE;
2596}
2597
d67fc27a
TY		 2598static int em_add(struct x86_emulate_ctxt *ctxt)
2599{
a31b9cea 2600 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2601 return X86EMUL_CONTINUE;
2602}
2603
2604static int em_or(struct x86_emulate_ctxt *ctxt)
2605{
a31b9cea 2606 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2607 return X86EMUL_CONTINUE;
2608}
2609
2610static int em_adc(struct x86_emulate_ctxt *ctxt)
2611{
a31b9cea 2612 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2613 return X86EMUL_CONTINUE;
2614}
2615
2616static int em_sbb(struct x86_emulate_ctxt *ctxt)
2617{
a31b9cea 2618 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2619 return X86EMUL_CONTINUE;
2620}
2621
2622static int em_and(struct x86_emulate_ctxt *ctxt)
2623{
a31b9cea 2624 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2625 return X86EMUL_CONTINUE;
2626}
2627
2628static int em_sub(struct x86_emulate_ctxt *ctxt)
2629{
a31b9cea 2630 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2631 return X86EMUL_CONTINUE;
2632}
2633
2634static int em_xor(struct x86_emulate_ctxt *ctxt)
2635{
a31b9cea 2636 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2637 return X86EMUL_CONTINUE;
2638}
2639
2640static int em_cmp(struct x86_emulate_ctxt *ctxt)
2641{
a31b9cea 2642 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2643 /* Disable writeback. */
9dac77fa 2644 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2645 return X86EMUL_CONTINUE;
2646}
2647
9f21ca59
TY		 2648static int em_test(struct x86_emulate_ctxt *ctxt)
2649{
a31b9cea 2650 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2651 /* Disable writeback. */
2652 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2653 return X86EMUL_CONTINUE;
2654}
2655
e4f973ae
TY		 2656static int em_xchg(struct x86_emulate_ctxt *ctxt)
2657{
e4f973ae 2658 /* Write back the register source. */
9dac77fa
AK		 2659 ctxt->src.val = ctxt->dst.val;
2660 write_register_operand(&ctxt->src);
e4f973ae
TY		 2661
2662 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2663 ctxt->dst.val = ctxt->src.orig_val;
2664 ctxt->lock_prefix = 1;
e4f973ae
TY		 2665 return X86EMUL_CONTINUE;
2666}
2667
5c82aa29 2668static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2669{
a31b9cea 2670 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2671 return X86EMUL_CONTINUE;
2672}
2673
5c82aa29
AK		 2674static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2675{
9dac77fa 2676 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2677 return em_imul(ctxt);
2678}
2679
61429142
AK		 2680static int em_cwd(struct x86_emulate_ctxt *ctxt)
2681{
9dac77fa
AK		 2682 ctxt->dst.type = OP_REG;
2683 ctxt->dst.bytes = ctxt->src.bytes;
2684 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2685 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2686
2687 return X86EMUL_CONTINUE;
2688}
2689
48bb5d3c
AK		 2690static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2691{
48bb5d3c
AK		 2692 u64 tsc = 0;
2693
717746e3 2694 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2695 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2696 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2697 return X86EMUL_CONTINUE;
2698}
2699
222d21aa
AK		 2700static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2701{
2702 u64 pmc;
2703
2704 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2705 return emulate_gp(ctxt, 0);
2706 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2707 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2708 return X86EMUL_CONTINUE;
2709}
2710
b9eac5f4
AK		 2711static int em_mov(struct x86_emulate_ctxt *ctxt)
2712{
9dac77fa 2713 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2714 return X86EMUL_CONTINUE;
2715}
2716
bc00f8d2
TY		 2717static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2718{
2719 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2720 return emulate_gp(ctxt, 0);
2721
2722 /* Disable writeback. */
2723 ctxt->dst.type = OP_NONE;
2724 return X86EMUL_CONTINUE;
2725}
2726
2727static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2728{
2729 unsigned long val;
2730
2731 if (ctxt->mode == X86EMUL_MODE_PROT64)
2732 val = ctxt->src.val & ~0ULL;
2733 else
2734 val = ctxt->src.val & ~0U;
2735
2736 /* #UD condition is already handled. */
2737 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2738 return emulate_gp(ctxt, 0);
2739
2740 /* Disable writeback. */
2741 ctxt->dst.type = OP_NONE;
2742 return X86EMUL_CONTINUE;
2743}
2744
e1e210b0
TY		 2745static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2746{
2747 u64 msr_data;
2748
2749 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2750 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2751 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2752 return emulate_gp(ctxt, 0);
2753
2754 return X86EMUL_CONTINUE;
2755}
2756
2757static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2758{
2759 u64 msr_data;
2760
2761 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2762 return emulate_gp(ctxt, 0);
2763
2764 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2765 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2766 return X86EMUL_CONTINUE;
2767}
2768
1bd5f469
TY		 2769static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2770{
9dac77fa 2771 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2772 return emulate_ud(ctxt);
2773
9dac77fa 2774 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2775 return X86EMUL_CONTINUE;
2776}
2777
2778static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2779{
9dac77fa 2780 u16 sel = ctxt->src.val;
1bd5f469 2781
9dac77fa 2782 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2783 return emulate_ud(ctxt);
2784
9dac77fa 2785 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2786 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2787
2788 /* Disable writeback. */
9dac77fa
AK		 2789 ctxt->dst.type = OP_NONE;
2790 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2791}
2792
aa97bb48
AK		 2793static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2794{
9dac77fa 2795 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2796 return X86EMUL_CONTINUE;
2797}
2798
38503911
AK		 2799static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2800{
9fa088f4
AK		 2801 int rc;
2802 ulong linear;
2803
9dac77fa 2804 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2805 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2806 ctxt->ops->invlpg(ctxt, linear);
38503911 2807 /* Disable writeback. */
9dac77fa 2808 ctxt->dst.type = OP_NONE;
38503911
AK		 2809 return X86EMUL_CONTINUE;
2810}
2811
2d04a05b
AK		 2812static int em_clts(struct x86_emulate_ctxt *ctxt)
2813{
2814 ulong cr0;
2815
2816 cr0 = ctxt->ops->get_cr(ctxt, 0);
2817 cr0 &= ~X86_CR0_TS;
2818 ctxt->ops->set_cr(ctxt, 0, cr0);
2819 return X86EMUL_CONTINUE;
2820}
2821
26d05cc7
AK		 2822static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2823{
26d05cc7
AK		 2824 int rc;
2825
9dac77fa 2826 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2827 return X86EMUL_UNHANDLEABLE;
2828
2829 rc = ctxt->ops->fix_hypercall(ctxt);
2830 if (rc != X86EMUL_CONTINUE)
2831 return rc;
2832
2833 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2834 ctxt->_eip = ctxt->eip;
26d05cc7 2835 /* Disable writeback. */
9dac77fa 2836 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2837 return X86EMUL_CONTINUE;
2838}
2839
2840static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2841{
26d05cc7
AK		 2842 struct desc_ptr desc_ptr;
2843 int rc;
2844
9dac77fa 2845 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2846 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2847 ctxt->op_bytes);
26d05cc7
AK		 2848 if (rc != X86EMUL_CONTINUE)
2849 return rc;
2850 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2851 /* Disable writeback. */
9dac77fa 2852 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2853 return X86EMUL_CONTINUE;
2854}
2855
5ef39c71 2856static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2857{
26d05cc7
AK		 2858 int rc;
2859
5ef39c71
AK		 2860 rc = ctxt->ops->fix_hypercall(ctxt);
2861
26d05cc7 2862 /* Disable writeback. */
9dac77fa 2863 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2864 return rc;
2865}
2866
2867static int em_lidt(struct x86_emulate_ctxt *ctxt)
2868{
26d05cc7
AK		 2869 struct desc_ptr desc_ptr;
2870 int rc;
2871
9dac77fa 2872 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2873 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2874 ctxt->op_bytes);
26d05cc7
AK		 2875 if (rc != X86EMUL_CONTINUE)
2876 return rc;
2877 ctxt->ops->set_idt(ctxt, &desc_ptr);
2878 /* Disable writeback. */
9dac77fa 2879 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2880 return X86EMUL_CONTINUE;
2881}
2882
2883static int em_smsw(struct x86_emulate_ctxt *ctxt)
2884{
9dac77fa
AK		 2885 ctxt->dst.bytes = 2;
2886 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2887 return X86EMUL_CONTINUE;
2888}
2889
2890static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2891{
26d05cc7 2892 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2893 | (ctxt->src.val & 0x0f));
2894 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2895 return X86EMUL_CONTINUE;
2896}
2897
d06e03ad
TY		 2898static int em_loop(struct x86_emulate_ctxt *ctxt)
2899{
9dac77fa
AK		 2900 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2901 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2902 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2903 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2904
2905 return X86EMUL_CONTINUE;
2906}
2907
2908static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2909{
9dac77fa
AK		 2910 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2911 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2912
2913 return X86EMUL_CONTINUE;
2914}
2915
d7841a4b
TY		 2916static int em_in(struct x86_emulate_ctxt *ctxt)
2917{
2918 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
2919 &ctxt->dst.val))
2920 return X86EMUL_IO_NEEDED;
2921
2922 return X86EMUL_CONTINUE;
2923}
2924
2925static int em_out(struct x86_emulate_ctxt *ctxt)
2926{
2927 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
2928 &ctxt->src.val, 1);
2929 /* Disable writeback. */
2930 ctxt->dst.type = OP_NONE;
2931 return X86EMUL_CONTINUE;
2932}
2933
f411e6cd
TY		 2934static int em_cli(struct x86_emulate_ctxt *ctxt)
2935{
2936 if (emulator_bad_iopl(ctxt))
2937 return emulate_gp(ctxt, 0);
2938
2939 ctxt->eflags &= ~X86_EFLAGS_IF;
2940 return X86EMUL_CONTINUE;
2941}
2942
2943static int em_sti(struct x86_emulate_ctxt *ctxt)
2944{
2945 if (emulator_bad_iopl(ctxt))
2946 return emulate_gp(ctxt, 0);
2947
2948 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2949 ctxt->eflags |= X86_EFLAGS_IF;
2950 return X86EMUL_CONTINUE;
2951}
2952
ce7faab2
TY		 2953static int em_bt(struct x86_emulate_ctxt *ctxt)
2954{
2955 /* Disable writeback. */
2956 ctxt->dst.type = OP_NONE;
2957 /* only subword offset */
2958 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
2959
2960 emulate_2op_SrcV_nobyte(ctxt, "bt");
2961 return X86EMUL_CONTINUE;
2962}
2963
2964static int em_bts(struct x86_emulate_ctxt *ctxt)
2965{
2966 emulate_2op_SrcV_nobyte(ctxt, "bts");
2967 return X86EMUL_CONTINUE;
2968}
2969
2970static int em_btr(struct x86_emulate_ctxt *ctxt)
2971{
2972 emulate_2op_SrcV_nobyte(ctxt, "btr");
2973 return X86EMUL_CONTINUE;
2974}
2975
2976static int em_btc(struct x86_emulate_ctxt *ctxt)
2977{
2978 emulate_2op_SrcV_nobyte(ctxt, "btc");
2979 return X86EMUL_CONTINUE;
2980}
2981
ff227392
TY		 2982static int em_bsf(struct x86_emulate_ctxt *ctxt)
2983{
2984 u8 zf;
2985
2986 __asm__ ("bsf %2, %0; setz %1"
2987 : "=r"(ctxt->dst.val), "=q"(zf)
2988 : "r"(ctxt->src.val));
2989
2990 ctxt->eflags &= ~X86_EFLAGS_ZF;
2991 if (zf) {
2992 ctxt->eflags |= X86_EFLAGS_ZF;
2993 /* Disable writeback. */
2994 ctxt->dst.type = OP_NONE;
2995 }
2996 return X86EMUL_CONTINUE;
2997}
2998
2999static int em_bsr(struct x86_emulate_ctxt *ctxt)
3000{
3001 u8 zf;
3002
3003 __asm__ ("bsr %2, %0; setz %1"
3004 : "=r"(ctxt->dst.val), "=q"(zf)
3005 : "r"(ctxt->src.val));
3006
3007 ctxt->eflags &= ~X86_EFLAGS_ZF;
3008 if (zf) {
3009 ctxt->eflags |= X86_EFLAGS_ZF;
3010 /* Disable writeback. */
3011 ctxt->dst.type = OP_NONE;
3012 }
3013 return X86EMUL_CONTINUE;
3014}
3015
cfec82cb
JR		 3016static bool valid_cr(int nr)
3017{
3018 switch (nr) {
3019 case 0:
3020 case 2 ... 4:
3021 case 8:
3022 return true;
3023 default:
3024 return false;
3025 }
3026}
3027
3028static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3029{
9dac77fa 3030 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3031 return emulate_ud(ctxt);
3032
3033 return X86EMUL_CONTINUE;
3034}
3035
3036static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3037{
9dac77fa
AK		 3038 u64 new_val = ctxt->src.val64;
3039 int cr = ctxt->modrm_reg;
c2ad2bb3 3040 u64 efer = 0;
cfec82cb
JR		 3041
3042 static u64 cr_reserved_bits[] = {
3043 0xffffffff00000000ULL,
3044 0, 0, 0, /* CR3 checked later */
3045 CR4_RESERVED_BITS,
3046 0, 0, 0,
3047 CR8_RESERVED_BITS,
3048 };
3049
3050 if (!valid_cr(cr))
3051 return emulate_ud(ctxt);
3052
3053 if (new_val & cr_reserved_bits[cr])
3054 return emulate_gp(ctxt, 0);
3055
3056 switch (cr) {
3057 case 0: {
c2ad2bb3 3058 u64 cr4;
cfec82cb
JR		 3059 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3060 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3061 return emulate_gp(ctxt, 0);
3062
717746e3
AK		 3063 cr4 = ctxt->ops->get_cr(ctxt, 4);
3064 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3065
3066 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3067 !(cr4 & X86_CR4_PAE))
3068 return emulate_gp(ctxt, 0);
3069
3070 break;
3071 }
3072 case 3: {
3073 u64 rsvd = 0;
3074
c2ad2bb3
AK		 3075 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3076 if (efer & EFER_LMA)
cfec82cb 3077 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3078 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3079 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3080 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3081 rsvd = CR3_NONPAE_RESERVED_BITS;
3082
3083 if (new_val & rsvd)
3084 return emulate_gp(ctxt, 0);
3085
3086 break;
3087 }
3088 case 4: {
717746e3 3089 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3090
3091 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3092 return emulate_gp(ctxt, 0);
3093
3094 break;
3095 }
3096 }
3097
3098 return X86EMUL_CONTINUE;
3099}
3100
3b88e41a
JR		 3101static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3102{
3103 unsigned long dr7;
3104
717746e3 3105 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3106
3107 /* Check if DR7.Global_Enable is set */
3108 return dr7 & (1 << 13);
3109}
3110
3111static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3112{
9dac77fa 3113 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3114 u64 cr4;
3115
3116 if (dr > 7)
3117 return emulate_ud(ctxt);
3118
717746e3 3119 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3120 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3121 return emulate_ud(ctxt);
3122
3123 if (check_dr7_gd(ctxt))
3124 return emulate_db(ctxt);
3125
3126 return X86EMUL_CONTINUE;
3127}
3128
3129static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3130{
9dac77fa
AK		 3131 u64 new_val = ctxt->src.val64;
3132 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3133
3134 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3135 return emulate_gp(ctxt, 0);
3136
3137 return check_dr_read(ctxt);
3138}
3139
01de8b09
JR		 3140static int check_svme(struct x86_emulate_ctxt *ctxt)
3141{
3142 u64 efer;
3143
717746e3 3144 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3145
3146 if (!(efer & EFER_SVME))
3147 return emulate_ud(ctxt);
3148
3149 return X86EMUL_CONTINUE;
3150}
3151
3152static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3153{
9dac77fa 3154 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3155
3156 /* Valid physical address? */
d4224449 3157 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3158 return emulate_gp(ctxt, 0);
3159
3160 return check_svme(ctxt);
3161}
3162
d7eb8203
JR		 3163static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3164{
717746e3 3165 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3166
717746e3 3167 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3168 return emulate_ud(ctxt);
3169
3170 return X86EMUL_CONTINUE;
3171}
3172
8061252e
JR		 3173static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3174{
717746e3 3175 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3176 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3177
717746e3 3178 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3179 (rcx > 3))
3180 return emulate_gp(ctxt, 0);
3181
3182 return X86EMUL_CONTINUE;
3183}
3184
f6511935
JR		 3185static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3186{
9dac77fa
AK		 3187 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3188 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3189 return emulate_gp(ctxt, 0);
3190
3191 return X86EMUL_CONTINUE;
3192}
3193
3194static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3195{
9dac77fa
AK		 3196 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3197 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3198 return emulate_gp(ctxt, 0);
3199
3200 return X86EMUL_CONTINUE;
3201}
3202
73fba5f4 3203#define D(_y) { .flags = (_y) }
c4f035c6 3204#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3205#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3206 .check_perm = (_p) }
73fba5f4 3207#define N D(0)
01de8b09 3208#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 3209#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3210#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3211#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3212#define II(_f, _e, _i) \
3213 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3214#define IIP(_f, _e, _i, _p) \
3215 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3216 .check_perm = (_p) }
aa97bb48 3217#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3218
8d8f4e9f 3219#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3220#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3221#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3222#define I2bvIP(_f, _e, _i, _p) \
3223 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3224
d67fc27a
TY		 3225#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3226 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3227 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3228
d7eb8203
JR		 3229static struct opcode group7_rm1[] = {
3230 DI(SrcNone | ModRM | Priv, monitor),
3231 DI(SrcNone | ModRM | Priv, mwait),
3232 N, N, N, N, N, N,
3233};
3234
01de8b09
JR		 3235static struct opcode group7_rm3[] = {
3236 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3237 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3238 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3239 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3240 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3241 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3242 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3243 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3244};
6230f7fc 3245
d7eb8203
JR		 3246static struct opcode group7_rm7[] = {
3247 N,
3248 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3249 N, N, N, N, N, N,
3250};
d67fc27a 3251
73fba5f4 3252static struct opcode group1[] = {
d67fc27a 3253 I(Lock, em_add),
d5ae7ce8 3254 I(Lock | PageTable, em_or),
d67fc27a
TY		 3255 I(Lock, em_adc),
3256 I(Lock, em_sbb),
d5ae7ce8 3257 I(Lock | PageTable, em_and),
d67fc27a
TY		 3258 I(Lock, em_sub),
3259 I(Lock, em_xor),
3260 I(0, em_cmp),
73fba5f4
AK		 3261};
3262
3263static struct opcode group1A[] = {
c15af35f 3264 I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3265};
3266
3267static struct opcode group3[] = {
3329ece1
AK		 3268 I(DstMem | SrcImm | ModRM, em_test),
3269 I(DstMem | SrcImm | ModRM, em_test),
3270 I(DstMem | SrcNone | ModRM | Lock, em_not),
3271 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3272 I(SrcMem | ModRM, em_mul_ex),
3273 I(SrcMem | ModRM, em_imul_ex),
3274 I(SrcMem | ModRM, em_div_ex),
3275 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3276};
3277
3278static struct opcode group4[] = {
c04ec839
TY		 3279 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
3280 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45),
73fba5f4
AK		 3281 N, N, N, N, N, N,
3282};
3283
3284static struct opcode group5[] = {
c04ec839
TY		 3285 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3286 I(DstMem | SrcNone | ModRM | Lock, em_grp45),
3287 I(SrcMem | ModRM | Stack, em_grp45),
0ef753b8 3288 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
c04ec839
TY		 3289 I(SrcMem | ModRM | Stack, em_grp45),
3290 I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45),
3291 I(SrcMem | ModRM | Stack, em_grp45), N,
73fba5f4
AK		 3292};
3293
dee6bb70
JR		 3294static struct opcode group6[] = {
3295 DI(ModRM | Prot, sldt),
3296 DI(ModRM | Prot, str),
3297 DI(ModRM | Prot | Priv, lldt),
3298 DI(ModRM | Prot | Priv, ltr),
3299 N, N, N, N,
3300};
3301
73fba5f4 3302static struct group_dual group7 = { {
dee6bb70
JR		 3303 DI(ModRM | Mov | DstMem | Priv, sgdt),
3304 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3305 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3306 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3307 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3308 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3309 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3310}, {
5ef39c71
AK		 3311 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3312 EXT(0, group7_rm1),
01de8b09 3313 N, EXT(0, group7_rm3),
5ef39c71
AK		 3314 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3315 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3316} };
3317
3318static struct opcode group8[] = {
3319 N, N, N, N,
ce7faab2
TY		 3320 I(DstMem | SrcImmByte | ModRM, em_bt),
3321 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts),
3322 I(DstMem | SrcImmByte | ModRM | Lock, em_btr),
3323 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc),
73fba5f4
AK		 3324};
3325
3326static struct group_dual group9 = { {
e0dac408 3327 N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3328}, {
3329 N, N, N, N, N, N, N, N,
3330} };
3331
a4d4a7c1 3332static struct opcode group11[] = {
d5ae7ce8
XG		 3333 I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov),
3334 X7(D(Undefined)),
a4d4a7c1
AK		 3335};
3336
aa97bb48
AK		 3337static struct gprefix pfx_0f_6f_0f_7f = {
3338 N, N, N, I(Sse, em_movdqu),
3339};
3340
73fba5f4
AK		 3341static struct opcode opcode_table[256] = {
3342 /* 0x00 - 0x07 */
d67fc27a 3343 I6ALU(Lock, em_add),
1cd196ea
AK		 3344 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3345 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3346 /* 0x08 - 0x0F */
d5ae7ce8 3347 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3348 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3349 N,
73fba5f4 3350 /* 0x10 - 0x17 */
d67fc27a 3351 I6ALU(Lock, em_adc),
1cd196ea
AK		 3352 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3353 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3354 /* 0x18 - 0x1F */
d67fc27a 3355 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3356 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3357 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3358 /* 0x20 - 0x27 */
d5ae7ce8 3359 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3360 /* 0x28 - 0x2F */
d67fc27a 3361 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3362 /* 0x30 - 0x37 */
d67fc27a 3363 I6ALU(Lock, em_xor), N, N,
73fba5f4 3364 /* 0x38 - 0x3F */
d67fc27a 3365 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3366 /* 0x40 - 0x4F */
3367 X16(D(DstReg)),
3368 /* 0x50 - 0x57 */
63540382 3369 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3370 /* 0x58 - 0x5F */
c54fe504 3371 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3372 /* 0x60 - 0x67 */
b96a7fad
TY		 3373 I(ImplicitOps | Stack | No64, em_pusha),
3374 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3375 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3376 N, N, N, N,
3377 /* 0x68 - 0x6F */
d46164db
AK		 3378 I(SrcImm | Mov | Stack, em_push),
3379 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3380 I(SrcImmByte | Mov | Stack, em_push),
3381 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3382 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3383 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3384 /* 0x70 - 0x7F */
3385 X16(D(SrcImmByte)),
3386 /* 0x80 - 0x87 */
3387 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3388 G(DstMem | SrcImm | ModRM | Group, group1),
3389 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3390 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3391 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3392 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3393 /* 0x88 - 0x8F */
d5ae7ce8 3394 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3395 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3396 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3397 D(ModRM | SrcMem | NoAccess | DstReg),
3398 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3399 G(0, group1A),
73fba5f4 3400 /* 0x90 - 0x97 */
bf608f88 3401 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3402 /* 0x98 - 0x9F */
61429142 3403 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3404 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3405 II(ImplicitOps | Stack, em_pushf, pushf),
3406 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3407 /* 0xA0 - 0xA7 */
b9eac5f4 3408 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3409 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3410 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3411 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3412 /* 0xA8 - 0xAF */
9f21ca59 3413 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3414 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3415 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3416 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3417 /* 0xB0 - 0xB7 */
b9eac5f4 3418 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3419 /* 0xB8 - 0xBF */
b9eac5f4 3420 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3421 /* 0xC0 - 0xC7 */
d2c6c7ad 3422 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3423 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3424 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3425 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3426 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3427 G(ByteOp, group11), G(0, group11),
73fba5f4 3428 /* 0xC8 - 0xCF */
db5b0762 3429 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3430 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3431 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3432 /* 0xD0 - 0xD7 */
d2c6c7ad 3433 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3434 N, N, N, N,
3435 /* 0xD8 - 0xDF */
3436 N, N, N, N, N, N, N, N,
3437 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3438 X3(I(SrcImmByte, em_loop)),
3439 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3440 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3441 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3442 /* 0xE8 - 0xEF */
d4ddafcd 3443 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3444 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3445 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3446 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3447 /* 0xF0 - 0xF7 */
bf608f88 3448 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3449 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3450 G(ByteOp, group3), G(0, group3),
73fba5f4 3451 /* 0xF8 - 0xFF */
f411e6cd
TY		 3452 D(ImplicitOps), D(ImplicitOps),
3453 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3454 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3455};
3456
3457static struct opcode twobyte_table[256] = {
3458 /* 0x00 - 0x0F */
dee6bb70 3459 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3460 N, I(ImplicitOps | VendorSpecific, em_syscall),
3461 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3462 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3463 N, D(ImplicitOps | ModRM), N, N,
3464 /* 0x10 - 0x1F */
3465 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3466 /* 0x20 - 0x2F */
cfec82cb 3467 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3468 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3469 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3470 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4
AK		 3471 N, N, N, N,
3472 N, N, N, N, N, N, N, N,
3473 /* 0x30 - 0x3F */
e1e210b0 3474 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3475 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3476 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3477 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3478 I(ImplicitOps | VendorSpecific, em_sysenter),
3479 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3480 N, N,
73fba5f4
AK		 3481 N, N, N, N, N, N, N, N,
3482 /* 0x40 - 0x4F */
3483 X16(D(DstReg | SrcMem | ModRM | Mov)),
3484 /* 0x50 - 0x5F */
3485 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3486 /* 0x60 - 0x6F */
aa97bb48
AK		 3487 N, N, N, N,
3488 N, N, N, N,
3489 N, N, N, N,
3490 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3491 /* 0x70 - 0x7F */
aa97bb48
AK		 3492 N, N, N, N,
3493 N, N, N, N,
3494 N, N, N, N,
3495 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3496 /* 0x80 - 0x8F */
3497 X16(D(SrcImm)),
3498 /* 0x90 - 0x9F */
ee45b58e 3499 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3500 /* 0xA0 - 0xA7 */
1cd196ea 3501 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
ce7faab2 3502 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3503 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3504 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3505 /* 0xA8 - 0xAF */
1cd196ea 3506 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3507 DI(ImplicitOps, rsm),
ce7faab2 3508 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3509 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3510 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3511 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3512 /* 0xB0 - 0xB7 */
e940b5c2 3513 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3514 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3515 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3516 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3517 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3518 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3519 /* 0xB8 - 0xBF */
3520 N, N,
ce7faab2
TY		 3521 G(BitOp, group8),
3522 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3523 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3524 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3525 /* 0xC0 - 0xCF */
739ae406 3526 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3527 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3528 N, N, N, GD(0, &group9),
3529 N, N, N, N, N, N, N, N,
3530 /* 0xD0 - 0xDF */
3531 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3532 /* 0xE0 - 0xEF */
3533 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3534 /* 0xF0 - 0xFF */
3535 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3536};
3537
3538#undef D
3539#undef N
3540#undef G
3541#undef GD
3542#undef I
aa97bb48 3543#undef GP
01de8b09 3544#undef EXT
73fba5f4 3545
8d8f4e9f 3546#undef D2bv
f6511935 3547#undef D2bvIP
8d8f4e9f 3548#undef I2bv
d7841a4b 3549#undef I2bvIP
d67fc27a 3550#undef I6ALU
8d8f4e9f 3551
9dac77fa 3552static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3553{
3554 unsigned size;
3555
9dac77fa 3556 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3557 if (size == 8)
3558 size = 4;
3559 return size;
3560}
3561
3562static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3563 unsigned size, bool sign_extension)
3564{
39f21ee5
AK		 3565 int rc = X86EMUL_CONTINUE;
3566
3567 op->type = OP_IMM;
3568 op->bytes = size;
9dac77fa 3569 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3570 /* NB. Immediates are sign-extended as necessary. */
3571 switch (op->bytes) {
3572 case 1:
e85a1085 3573 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3574 break;
3575 case 2:
e85a1085 3576 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3577 break;
3578 case 4:
e85a1085 3579 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3580 break;
3581 }
3582 if (!sign_extension) {
3583 switch (op->bytes) {
3584 case 1:
3585 op->val &= 0xff;
3586 break;
3587 case 2:
3588 op->val &= 0xffff;
3589 break;
3590 case 4:
3591 op->val &= 0xffffffff;
3592 break;
3593 }
3594 }
3595done:
3596 return rc;
3597}
3598
a9945549
AK		 3599static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3600 unsigned d)
3601{
3602 int rc = X86EMUL_CONTINUE;
3603
3604 switch (d) {
3605 case OpReg:
2adb5ad9 3606 decode_register_operand(ctxt, op);
a9945549
AK		 3607 break;
3608 case OpImmUByte:
608aabe3 3609 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3610 break;
3611 case OpMem:
41ddf978 3612 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3613 mem_common:
3614 *op = ctxt->memop;
3615 ctxt->memopp = op;
3616 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3617 fetch_bit_operand(ctxt);
3618 op->orig_val = op->val;
3619 break;
41ddf978
AK		 3620 case OpMem64:
3621 ctxt->memop.bytes = 8;
3622 goto mem_common;
a9945549
AK		 3623 case OpAcc:
3624 op->type = OP_REG;
3625 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3626 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3627 fetch_register_operand(op);
3628 op->orig_val = op->val;
3629 break;
3630 case OpDI:
3631 op->type = OP_MEM;
3632 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3633 op->addr.mem.ea =
3634 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3635 op->addr.mem.seg = VCPU_SREG_ES;
3636 op->val = 0;
3637 break;
3638 case OpDX:
3639 op->type = OP_REG;
3640 op->bytes = 2;
3641 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3642 fetch_register_operand(op);
3643 break;
4dd6a57d
AK		 3644 case OpCL:
3645 op->bytes = 1;
3646 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3647 break;
3648 case OpImmByte:
3649 rc = decode_imm(ctxt, op, 1, true);
3650 break;
3651 case OpOne:
3652 op->bytes = 1;
3653 op->val = 1;
3654 break;
3655 case OpImm:
3656 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3657 break;
28867cee
AK		 3658 case OpMem8:
3659 ctxt->memop.bytes = 1;
3660 goto mem_common;
0fe59128
AK		 3661 case OpMem16:
3662 ctxt->memop.bytes = 2;
3663 goto mem_common;
3664 case OpMem32:
3665 ctxt->memop.bytes = 4;
3666 goto mem_common;
3667 case OpImmU16:
3668 rc = decode_imm(ctxt, op, 2, false);
3669 break;
3670 case OpImmU:
3671 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3672 break;
3673 case OpSI:
3674 op->type = OP_MEM;
3675 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3676 op->addr.mem.ea =
3677 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3678 op->addr.mem.seg = seg_override(ctxt);
3679 op->val = 0;
3680 break;
3681 case OpImmFAddr:
3682 op->type = OP_IMM;
3683 op->addr.mem.ea = ctxt->_eip;
3684 op->bytes = ctxt->op_bytes + 2;
3685 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3686 break;
3687 case OpMemFAddr:
3688 ctxt->memop.bytes = ctxt->op_bytes + 2;
3689 goto mem_common;
c191a7a0
AK		 3690 case OpES:
3691 op->val = VCPU_SREG_ES;
3692 break;
3693 case OpCS:
3694 op->val = VCPU_SREG_CS;
3695 break;
3696 case OpSS:
3697 op->val = VCPU_SREG_SS;
3698 break;
3699 case OpDS:
3700 op->val = VCPU_SREG_DS;
3701 break;
3702 case OpFS:
3703 op->val = VCPU_SREG_FS;
3704 break;
3705 case OpGS:
3706 op->val = VCPU_SREG_GS;
3707 break;
a9945549
AK		 3708 case OpImplicit:
3709 /* Special instructions do their own operand decoding. */
3710 default:
3711 op->type = OP_NONE; /* Disable writeback. */
3712 break;
3713 }
3714
3715done:
3716 return rc;
3717}
3718
ef5d75cc 3719int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3720{
dde7e6d1
AK		 3721 int rc = X86EMUL_CONTINUE;
3722 int mode = ctxt->mode;
46561646 3723 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3724 bool op_prefix = false;
46561646 3725 struct opcode opcode;
dde7e6d1 3726
f09ed83e
AK		 3727 ctxt->memop.type = OP_NONE;
3728 ctxt->memopp = NULL;
9dac77fa
AK		 3729 ctxt->_eip = ctxt->eip;
3730 ctxt->fetch.start = ctxt->_eip;
3731 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3732 if (insn_len > 0)
9dac77fa 3733 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3734
3735 switch (mode) {
3736 case X86EMUL_MODE_REAL:
3737 case X86EMUL_MODE_VM86:
3738 case X86EMUL_MODE_PROT16:
3739 def_op_bytes = def_ad_bytes = 2;
3740 break;
3741 case X86EMUL_MODE_PROT32:
3742 def_op_bytes = def_ad_bytes = 4;
3743 break;
3744#ifdef CONFIG_X86_64
3745 case X86EMUL_MODE_PROT64:
3746 def_op_bytes = 4;
3747 def_ad_bytes = 8;
3748 break;
3749#endif
3750 default:
1d2887e2 3751 return EMULATION_FAILED;
dde7e6d1
AK		 3752 }
3753
9dac77fa
AK		 3754 ctxt->op_bytes = def_op_bytes;
3755 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3756
3757 /* Legacy prefixes. */
3758 for (;;) {
e85a1085 3759 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3760 case 0x66: /* operand-size override */
0d7cdee8 3761 op_prefix = true;
dde7e6d1 3762 /* switch between 2/4 bytes */
9dac77fa 3763 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3764 break;
3765 case 0x67: /* address-size override */
3766 if (mode == X86EMUL_MODE_PROT64)
3767 /* switch between 4/8 bytes */
9dac77fa 3768 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3769 else
3770 /* switch between 2/4 bytes */
9dac77fa 3771 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3772 break;
3773 case 0x26: /* ES override */
3774 case 0x2e: /* CS override */
3775 case 0x36: /* SS override */
3776 case 0x3e: /* DS override */
9dac77fa 3777 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3778 break;
3779 case 0x64: /* FS override */
3780 case 0x65: /* GS override */
9dac77fa 3781 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3782 break;
3783 case 0x40 ... 0x4f: /* REX */
3784 if (mode != X86EMUL_MODE_PROT64)
3785 goto done_prefixes;
9dac77fa 3786 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3787 continue;
3788 case 0xf0: /* LOCK */
9dac77fa 3789 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3790 break;
3791 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3792 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3793 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3794 break;
3795 default:
3796 goto done_prefixes;
3797 }
3798
3799 /* Any legacy prefix after a REX prefix nullifies its effect. */
3800
9dac77fa 3801 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3802 }
3803
3804done_prefixes:
3805
3806 /* REX prefix. */
9dac77fa
AK		 3807 if (ctxt->rex_prefix & 8)
3808 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3809
3810 /* Opcode byte(s). */
9dac77fa 3811 opcode = opcode_table[ctxt->b];
d3ad6243 3812 /* Two-byte opcode? */
9dac77fa
AK		 3813 if (ctxt->b == 0x0f) {
3814 ctxt->twobyte = 1;
e85a1085 3815 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3816 opcode = twobyte_table[ctxt->b];
dde7e6d1 3817 }
9dac77fa 3818 ctxt->d = opcode.flags;
dde7e6d1 3819
9dac77fa
AK		 3820 while (ctxt->d & GroupMask) {
3821 switch (ctxt->d & GroupMask) {
46561646 3822 case Group:
e85a1085 3823 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3824 --ctxt->_eip;
3825 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3826 opcode = opcode.u.group[goffset];
3827 break;
3828 case GroupDual:
e85a1085 3829 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3830 --ctxt->_eip;
3831 goffset = (ctxt->modrm >> 3) & 7;
3832 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3833 opcode = opcode.u.gdual->mod3[goffset];
3834 else
3835 opcode = opcode.u.gdual->mod012[goffset];
3836 break;
3837 case RMExt:
9dac77fa 3838 goffset = ctxt->modrm & 7;
01de8b09 3839 opcode = opcode.u.group[goffset];
46561646
AK		 3840 break;
3841 case Prefix:
9dac77fa 3842 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3843 return EMULATION_FAILED;
9dac77fa 3844 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3845 switch (simd_prefix) {
3846 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3847 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3848 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3849 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3850 }
3851 break;
3852 default:
1d2887e2 3853 return EMULATION_FAILED;
0d7cdee8 3854 }
46561646 3855
b1ea50b2 3856 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3857 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3858 }
3859
9dac77fa
AK		 3860 ctxt->execute = opcode.u.execute;
3861 ctxt->check_perm = opcode.check_perm;
3862 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3863
3864 /* Unrecognised? */
9dac77fa 3865 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3866 return EMULATION_FAILED;
dde7e6d1 3867
9dac77fa 3868 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3869 return EMULATION_FAILED;
d867162c 3870
9dac77fa
AK		 3871 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3872 ctxt->op_bytes = 8;
dde7e6d1 3873
9dac77fa 3874 if (ctxt->d & Op3264) {
7f9b4b75 3875 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3876 ctxt->op_bytes = 8;
7f9b4b75 3877 else
9dac77fa 3878 ctxt->op_bytes = 4;
7f9b4b75
AK		 3879 }
3880
9dac77fa
AK		 3881 if (ctxt->d & Sse)
3882 ctxt->op_bytes = 16;
1253791d 3883
dde7e6d1 3884 /* ModRM and SIB bytes. */
9dac77fa 3885 if (ctxt->d & ModRM) {
f09ed83e 3886 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3887 if (!ctxt->has_seg_override)
3888 set_seg_override(ctxt, ctxt->modrm_seg);
3889 } else if (ctxt->d & MemAbs)
f09ed83e 3890 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3891 if (rc != X86EMUL_CONTINUE)
3892 goto done;
3893
9dac77fa
AK		 3894 if (!ctxt->has_seg_override)
3895 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3896
f09ed83e 3897 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3898
f09ed83e
AK		 3899 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3900 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3901
dde7e6d1
AK		 3902 /*
3903 * Decode and fetch the source operand: register, memory
3904 * or immediate.
3905 */
0fe59128 3906 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 3907 if (rc != X86EMUL_CONTINUE)
3908 goto done;
3909
dde7e6d1
AK		 3910 /*
3911 * Decode and fetch the second source operand: register, memory
3912 * or immediate.
3913 */
4dd6a57d 3914 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3915 if (rc != X86EMUL_CONTINUE)
3916 goto done;
3917
dde7e6d1 3918 /* Decode and fetch the destination operand: register or memory. */
a9945549 3919 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3920
3921done:
f09ed83e
AK		 3922 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3923 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3924
1d2887e2 3925 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3926}
3927
1cb3f3ae
XG		 3928bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
3929{
3930 return ctxt->d & PageTable;
3931}
3932
3e2f65d5
GN		 3933static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3934{
3e2f65d5
GN		 3935 /* The second termination condition only applies for REPE
3936 * and REPNE. Test if the repeat string operation prefix is
3937 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3938 * corresponding termination condition according to:
3939 * - if REPE/REPZ and ZF = 0 then done
3940 * - if REPNE/REPNZ and ZF = 1 then done
3941 */
9dac77fa
AK		 3942 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3943 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3944 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3945 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3946 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3947 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3948 return true;
3949
3950 return false;
3951}
3952
7b105ca2 3953int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3954{
9aabc88f 3955 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 3956 int rc = X86EMUL_CONTINUE;
9dac77fa 3957 int saved_dst_type = ctxt->dst.type;
8b4caf66 3958
9dac77fa 3959 ctxt->mem_read.pos = 0;
310b5d30 3960
9dac77fa 3961 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3962 rc = emulate_ud(ctxt);
1161624f
GN		 3963 goto done;
3964 }
3965
d380a5e4 3966 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3967 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3968 rc = emulate_ud(ctxt);
d380a5e4
GN		 3969 goto done;
3970 }
3971
9dac77fa 3972 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3973 rc = emulate_ud(ctxt);
081bca0e
AK		 3974 goto done;
3975 }
3976
9dac77fa 3977 if ((ctxt->d & Sse)
717746e3
AK		 3978 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3979 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3980 rc = emulate_ud(ctxt);
3981 goto done;
3982 }
3983
9dac77fa 3984 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3985 rc = emulate_nm(ctxt);
3986 goto done;
3987 }
3988
9dac77fa
AK		 3989 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3990 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3991 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3992 if (rc != X86EMUL_CONTINUE)
3993 goto done;
3994 }
3995
e92805ac 3996 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3997 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3998 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3999 goto done;
4000 }
4001
8ea7d6ae 4002 /* Instruction can only be executed in protected mode */
9dac77fa 4003 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4004 rc = emulate_ud(ctxt);
4005 goto done;
4006 }
4007
d09beabd 4008 /* Do instruction specific permission checks */
9dac77fa
AK		 4009 if (ctxt->check_perm) {
4010 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4011 if (rc != X86EMUL_CONTINUE)
4012 goto done;
4013 }
4014
9dac77fa
AK		 4015 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4016 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4017 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4018 if (rc != X86EMUL_CONTINUE)
4019 goto done;
4020 }
4021
9dac77fa 4022 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4023 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4024 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4025 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4026 goto done;
4027 }
b9fa9d6b
AK		 4028 }
4029
9dac77fa
AK		 4030 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4031 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4032 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4033 if (rc != X86EMUL_CONTINUE)
8b4caf66 4034 goto done;
9dac77fa 4035 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4036 }
4037
9dac77fa
AK		 4038 if (ctxt->src2.type == OP_MEM) {
4039 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4040 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4041 if (rc != X86EMUL_CONTINUE)
4042 goto done;
4043 }
4044
9dac77fa 4045 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4046 goto special_insn;
4047
4048
9dac77fa 4049 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4050 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4051 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4052 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4053 if (rc != X86EMUL_CONTINUE)
4054 goto done;
038e51de 4055 }
9dac77fa 4056 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4057
018a98db
AK		 4058special_insn:
4059
9dac77fa
AK		 4060 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4061 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4062 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4063 if (rc != X86EMUL_CONTINUE)
4064 goto done;
4065 }
4066
9dac77fa
AK		 4067 if (ctxt->execute) {
4068 rc = ctxt->execute(ctxt);
ef65c889
AK		 4069 if (rc != X86EMUL_CONTINUE)
4070 goto done;
4071 goto writeback;
4072 }
4073
9dac77fa 4074 if (ctxt->twobyte)
6aa8b732
AK		 4075 goto twobyte_insn;
4076
9dac77fa 4077 switch (ctxt->b) {
33615aa9 4078 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4079 emulate_1op(ctxt, "inc");
33615aa9
AK		 4080 break;
4081 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4082 emulate_1op(ctxt, "dec");
33615aa9 4083 break;
6aa8b732 4084 case 0x63: /* movsxd */
8b4caf66 4085 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4086 goto cannot_emulate;
9dac77fa 4087 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4088 break;
b2833e3c 4089 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4090 if (test_cc(ctxt->b, ctxt->eflags))
4091 jmp_rel(ctxt, ctxt->src.val);
018a98db 4092 break;
7e0b54b1 4093 case 0x8d: /* lea r16/r32, m */
9dac77fa 4094 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4095 break;
3d9e77df 4096 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4097 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4098 break;
e4f973ae
TY		 4099 rc = em_xchg(ctxt);
4100 break;
e8b6fa70 4101 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4102 switch (ctxt->op_bytes) {
4103 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4104 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4105 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4106 }
4107 break;
018a98db 4108 case 0xc0 ... 0xc1:
51187683 4109 rc = em_grp2(ctxt);
018a98db 4110 break;
6e154e56 4111 case 0xcc: /* int3 */
5c5df76b
TY		 4112 rc = emulate_int(ctxt, 3);
4113 break;
6e154e56 4114 case 0xcd: /* int n */
9dac77fa 4115 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4116 break;
4117 case 0xce: /* into */
5c5df76b
TY		 4118 if (ctxt->eflags & EFLG_OF)
4119 rc = emulate_int(ctxt, 4);
6e154e56 4120 break;
018a98db 4121 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4122 rc = em_grp2(ctxt);
018a98db
AK		 4123 break;
4124 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4125 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4126 rc = em_grp2(ctxt);
018a98db 4127 break;
1a52e051 4128 case 0xe9: /* jmp rel */
db5b0762 4129 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4130 jmp_rel(ctxt, ctxt->src.val);
4131 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4132 break;
111de5d6 4133 case 0xf4: /* hlt */
6c3287f7 4134 ctxt->ops->halt(ctxt);
19fdfa0d 4135 break;
111de5d6
AK		 4136 case 0xf5: /* cmc */
4137 /* complement carry flag from eflags reg */
4138 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4139 break;
4140 case 0xf8: /* clc */
4141 ctxt->eflags &= ~EFLG_CF;
111de5d6 4142 break;
8744aa9a
MG		 4143 case 0xf9: /* stc */
4144 ctxt->eflags |= EFLG_CF;
4145 break;
fb4616f4
MG		 4146 case 0xfc: /* cld */
4147 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4148 break;
4149 case 0xfd: /* std */
4150 ctxt->eflags |= EFLG_DF;
fb4616f4 4151 break;
91269b8f
AK		 4152 default:
4153 goto cannot_emulate;
6aa8b732 4154 }
018a98db 4155
7d9ddaed
AK		 4156 if (rc != X86EMUL_CONTINUE)
4157 goto done;
4158
018a98db 4159writeback:
adddcecf 4160 rc = writeback(ctxt);
1b30eaa8 4161 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4162 goto done;
4163
5cd21917
GN		 4164 /*
4165 * restore dst type in case the decoding will be reused
4166 * (happens for string instruction )
4167 */
9dac77fa 4168 ctxt->dst.type = saved_dst_type;
5cd21917 4169
9dac77fa
AK		 4170 if ((ctxt->d & SrcMask) == SrcSI)
4171 string_addr_inc(ctxt, seg_override(ctxt),
4172 VCPU_REGS_RSI, &ctxt->src);
a682e354 4173
9dac77fa 4174 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4175 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4176 &ctxt->dst);
d9271123 4177
9dac77fa
AK		 4178 if (ctxt->rep_prefix && (ctxt->d & String)) {
4179 struct read_cache *r = &ctxt->io_read;
4180 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4181
d2ddd1c4
GN		 4182 if (!string_insn_completed(ctxt)) {
4183 /*
4184 * Re-enter guest when pio read ahead buffer is empty
4185 * or, if it is not used, after each 1024 iteration.
4186 */
9dac77fa 4187 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4188 (r->end == 0 || r->end != r->pos)) {
4189 /*
4190 * Reset read cache. Usually happens before
4191 * decode, but since instruction is restarted
4192 * we have to do it here.
4193 */
9dac77fa 4194 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4195 return EMULATION_RESTART;
4196 }
4197 goto done; /* skip rip writeback */
0fa6ccbd 4198 }
5cd21917 4199 }
d2ddd1c4 4200
9dac77fa 4201 ctxt->eip = ctxt->_eip;
018a98db
AK		 4202
4203done:
da9cb575
AK		 4204 if (rc == X86EMUL_PROPAGATE_FAULT)
4205 ctxt->have_exception = true;
775fde86
JR		 4206 if (rc == X86EMUL_INTERCEPTED)
4207 return EMULATION_INTERCEPTED;
4208
d2ddd1c4 4209 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4210
4211twobyte_insn:
9dac77fa 4212 switch (ctxt->b) {
018a98db 4213 case 0x09: /* wbinvd */
cfb22375 4214 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4215 break;
4216 case 0x08: /* invd */
018a98db
AK		 4217 case 0x0d: /* GrpP (prefetch) */
4218 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4219 break;
4220 case 0x20: /* mov cr, reg */
9dac77fa 4221 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4222 break;
6aa8b732 4223 case 0x21: /* mov from dr to reg */
9dac77fa 4224 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4225 break;
6aa8b732 4226 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4227 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4228 if (!test_cc(ctxt->b, ctxt->eflags))
4229 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4230 break;
b2833e3c 4231 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4232 if (test_cc(ctxt->b, ctxt->eflags))
4233 jmp_rel(ctxt, ctxt->src.val);
018a98db 4234 break;
ee45b58e 4235 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4236 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4237 break;
9bf8ea42
GT		 4238 case 0xa4: /* shld imm8, r, r/m */
4239 case 0xa5: /* shld cl, r, r/m */
761441b9 4240 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4241 break;
9bf8ea42
GT		 4242 case 0xac: /* shrd imm8, r, r/m */
4243 case 0xad: /* shrd cl, r, r/m */
761441b9 4244 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4245 break;
2a7c5b8b
GC		 4246 case 0xae: /* clflush */
4247 break;
6aa8b732 4248 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4249 ctxt->dst.bytes = ctxt->op_bytes;
4250 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4251 : (u16) ctxt->src.val;
6aa8b732 4252 break;
6aa8b732 4253 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4254 ctxt->dst.bytes = ctxt->op_bytes;
4255 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4256 (s16) ctxt->src.val;
6aa8b732 4257 break;
92f738a5 4258 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4259 emulate_2op_SrcV(ctxt, "add");
92f738a5 4260 /* Write back the register source. */
9dac77fa
AK		 4261 ctxt->src.val = ctxt->dst.orig_val;
4262 write_register_operand(&ctxt->src);
92f738a5 4263 break;
a012e65a 4264 case 0xc3: /* movnti */
9dac77fa
AK		 4265 ctxt->dst.bytes = ctxt->op_bytes;
4266 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4267 (u64) ctxt->src.val;
a012e65a 4268 break;
91269b8f
AK		 4269 default:
4270 goto cannot_emulate;
6aa8b732 4271 }
7d9ddaed
AK		 4272
4273 if (rc != X86EMUL_CONTINUE)
4274 goto done;
4275
6aa8b732
AK		 4276 goto writeback;
4277
4278cannot_emulate:
a0c0ab2f 4279 return EMULATION_FAILED;
6aa8b732 4280}
ubuntu-bionic-kernel mirror