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KVM: x86: Return error on cmpxchg16b emulation
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstImmUByte (OpImmUByte << DstShift)
90#define DstDX (OpDX << DstShift)
820207c8 91#define DstAccLo (OpAccLo << DstShift)
a9945549 92#define DstMask (OpMask << DstShift)
6aa8b732 93/* Source operand type. */
0fe59128
AK		 94#define SrcShift 6
95#define SrcNone (OpNone << SrcShift)
96#define SrcReg (OpReg << SrcShift)
97#define SrcMem (OpMem << SrcShift)
98#define SrcMem16 (OpMem16 << SrcShift)
99#define SrcMem32 (OpMem32 << SrcShift)
100#define SrcImm (OpImm << SrcShift)
101#define SrcImmByte (OpImmByte << SrcShift)
102#define SrcOne (OpOne << SrcShift)
103#define SrcImmUByte (OpImmUByte << SrcShift)
104#define SrcImmU (OpImmU << SrcShift)
105#define SrcSI (OpSI << SrcShift)
7fa57952 106#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 107#define SrcImmFAddr (OpImmFAddr << SrcShift)
108#define SrcMemFAddr (OpMemFAddr << SrcShift)
109#define SrcAcc (OpAcc << SrcShift)
110#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 111#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 112#define SrcDX (OpDX << SrcShift)
28867cee 113#define SrcMem8 (OpMem8 << SrcShift)
820207c8 114#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 115#define SrcMask (OpMask << SrcShift)
221192bd
MT		 116#define BitOp (1<<11)
117#define MemAbs (1<<12) /* Memory operand is absolute displacement */
118#define String (1<<13) /* String instruction (rep capable) */
119#define Stack (1<<14) /* Stack instruction (push/pop) */
120#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 125#define Escape (5<<15) /* Escape to coprocessor instruction */
221192bd 126#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 127/* Generic ModRM decode. */
128#define ModRM (1<<19)
129/* Destination is only written; never read. */
130#define Mov (1<<20)
d8769fed 131/* Misc flags */
8ea7d6ae 132#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 133#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 134#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 135#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 136#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 137#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 138#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 139#define No64 (1<<28)
d5ae7ce8 140#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 141#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 142/* Source 2 operand type */
0b789eee 143#define Src2Shift (31)
4dd6a57d 144#define Src2None (OpNone << Src2Shift)
ab2c5ce6 145#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 146#define Src2CL (OpCL << Src2Shift)
147#define Src2ImmByte (OpImmByte << Src2Shift)
148#define Src2One (OpOne << Src2Shift)
149#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 150#define Src2ES (OpES << Src2Shift)
151#define Src2CS (OpCS << Src2Shift)
152#define Src2SS (OpSS << Src2Shift)
153#define Src2DS (OpDS << Src2Shift)
154#define Src2FS (OpFS << Src2Shift)
155#define Src2GS (OpGS << Src2Shift)
4dd6a57d 156#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 157#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 158#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 161#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 162#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 163#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 164#define NoMod ((u64)1 << 47) /* Mod field is ignored */
6aa8b732 165
820207c8 166#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 167
d0e53325
AK		 168#define X2(x...) x, x
169#define X3(x...) X2(x), x
170#define X4(x...) X2(x), X2(x)
171#define X5(x...) X4(x), x
172#define X6(x...) X4(x), X2(x)
173#define X7(x...) X4(x), X3(x)
174#define X8(x...) X4(x), X4(x)
175#define X16(x...) X8(x), X8(x)
83babbca 176
e28bbd44
AK		 177#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
178#define FASTOP_SIZE 8
179
180/*
181 * fastop functions have a special calling convention:
182 *
017da7b6
AK		 183 * dst: rax (in/out)
184 * src: rdx (in/out)
e28bbd44
AK		 185 * src2: rcx (in)
186 * flags: rflags (in/out)
b8c0b6ae 187 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 188 *
189 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
190 * different operand sizes can be reached by calculation, rather than a jump
191 * table (which would be bigger than the code).
192 *
193 * fastop functions are declared as taking a never-defined fastop parameter,
194 * so they can't be called from C directly.
195 */
196
197struct fastop;
198
d65b1dee 199struct opcode {
b1ea50b2
AK		 200 u64 flags : 56;
201 u64 intercept : 8;
120df890 202 union {
ef65c889 203 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 204 const struct opcode *group;
205 const struct group_dual *gdual;
206 const struct gprefix *gprefix;
045a282c 207 const struct escape *esc;
e28bbd44 208 void (*fastop)(struct fastop *fake);
120df890 209 } u;
d09beabd 210 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 211};
212
213struct group_dual {
214 struct opcode mod012[8];
215 struct opcode mod3[8];
d65b1dee
AK		 216};
217
0d7cdee8
AK		 218struct gprefix {
219 struct opcode pfx_no;
220 struct opcode pfx_66;
221 struct opcode pfx_f2;
222 struct opcode pfx_f3;
223};
224
045a282c
GN		 225struct escape {
226 struct opcode op[8];
227 struct opcode high[64];
228};
229
6aa8b732 230/* EFLAGS bit definitions. */
d4c6a154
GN		 231#define EFLG_ID (1<<21)
232#define EFLG_VIP (1<<20)
233#define EFLG_VIF (1<<19)
234#define EFLG_AC (1<<18)
b1d86143
AP		 235#define EFLG_VM (1<<17)
236#define EFLG_RF (1<<16)
d4c6a154
GN		 237#define EFLG_IOPL (3<<12)
238#define EFLG_NT (1<<14)
6aa8b732
AK		 239#define EFLG_OF (1<<11)
240#define EFLG_DF (1<<10)
b1d86143 241#define EFLG_IF (1<<9)
d4c6a154 242#define EFLG_TF (1<<8)
6aa8b732
AK		 243#define EFLG_SF (1<<7)
244#define EFLG_ZF (1<<6)
245#define EFLG_AF (1<<4)
246#define EFLG_PF (1<<2)
247#define EFLG_CF (1<<0)
248
62bd430e
MG		 249#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
250#define EFLG_RESERVED_ONE_MASK 2
251
dd856efa
AK		 252static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
253{
254 if (!(ctxt->regs_valid & (1 << nr))) {
255 ctxt->regs_valid |= 1 << nr;
256 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
257 }
258 return ctxt->_regs[nr];
259}
260
261static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
262{
263 ctxt->regs_valid |= 1 << nr;
264 ctxt->regs_dirty |= 1 << nr;
265 return &ctxt->_regs[nr];
266}
267
268static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
269{
270 reg_read(ctxt, nr);
271 return reg_write(ctxt, nr);
272}
273
274static void writeback_registers(struct x86_emulate_ctxt *ctxt)
275{
276 unsigned reg;
277
278 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
279 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
280}
281
282static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
283{
284 ctxt->regs_dirty = 0;
285 ctxt->regs_valid = 0;
286}
287
6aa8b732
AK		 288/*
289 * These EFLAGS bits are restored from saved value during emulation, and
290 * any changes are written back to the saved value after emulation.
291 */
292#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
293
dda96d8f
AK		 294#ifdef CONFIG_X86_64
295#define ON64(x) x
296#else
297#define ON64(x)
298#endif
299
4d758349
AK		 300static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
301
b7d491e7
AK		 302#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
303#define FOP_RET "ret \n\t"
304
305#define FOP_START(op) \
306 extern void em_##op(struct fastop *fake); \
307 asm(".pushsection .text, \"ax\" \n\t" \
308 ".global em_" #op " \n\t" \
309 FOP_ALIGN \
310 "em_" #op ": \n\t"
311
312#define FOP_END \
313 ".popsection")
314
0bdea068
AK		 315#define FOPNOP() FOP_ALIGN FOP_RET
316
b7d491e7 317#define FOP1E(op, dst) \
b8c0b6ae
AK		 318 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
319
320#define FOP1EEX(op, dst) \
321 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 322
323#define FASTOP1(op) \
324 FOP_START(op) \
325 FOP1E(op##b, al) \
326 FOP1E(op##w, ax) \
327 FOP1E(op##l, eax) \
328 ON64(FOP1E(op##q, rax)) \
329 FOP_END
330
b9fa409b
AK		 331/* 1-operand, using src2 (for MUL/DIV r/m) */
332#define FASTOP1SRC2(op, name) \
333 FOP_START(name) \
334 FOP1E(op, cl) \
335 FOP1E(op, cx) \
336 FOP1E(op, ecx) \
337 ON64(FOP1E(op, rcx)) \
338 FOP_END
339
b8c0b6ae
AK		 340/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
341#define FASTOP1SRC2EX(op, name) \
342 FOP_START(name) \
343 FOP1EEX(op, cl) \
344 FOP1EEX(op, cx) \
345 FOP1EEX(op, ecx) \
346 ON64(FOP1EEX(op, rcx)) \
347 FOP_END
348
f7857f35
AK		 349#define FOP2E(op, dst, src) \
350 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
351
352#define FASTOP2(op) \
353 FOP_START(op) \
017da7b6
AK		 354 FOP2E(op##b, al, dl) \
355 FOP2E(op##w, ax, dx) \
356 FOP2E(op##l, eax, edx) \
357 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 358 FOP_END
359
11c363ba
AK		 360/* 2 operand, word only */
361#define FASTOP2W(op) \
362 FOP_START(op) \
363 FOPNOP() \
017da7b6
AK		 364 FOP2E(op##w, ax, dx) \
365 FOP2E(op##l, eax, edx) \
366 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 367 FOP_END
368
007a3b54
AK		 369/* 2 operand, src is CL */
370#define FASTOP2CL(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, cl) \
373 FOP2E(op##w, ax, cl) \
374 FOP2E(op##l, eax, cl) \
375 ON64(FOP2E(op##q, rax, cl)) \
376 FOP_END
377
0bdea068
AK		 378#define FOP3E(op, dst, src, src2) \
379 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
380
381/* 3-operand, word-only, src2=cl */
382#define FASTOP3WCL(op) \
383 FOP_START(op) \
384 FOPNOP() \
017da7b6
AK		 385 FOP3E(op##w, ax, dx, cl) \
386 FOP3E(op##l, eax, edx, cl) \
387 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 388 FOP_END
389
9ae9feba
AK		 390/* Special case for SETcc - 1 instruction per cc */
391#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
392
b8c0b6ae
AK		 393asm(".global kvm_fastop_exception \n"
394 "kvm_fastop_exception: xor %esi, %esi; ret");
395
9ae9feba
AK		 396FOP_START(setcc)
397FOP_SETCC(seto)
398FOP_SETCC(setno)
399FOP_SETCC(setc)
400FOP_SETCC(setnc)
401FOP_SETCC(setz)
402FOP_SETCC(setnz)
403FOP_SETCC(setbe)
404FOP_SETCC(setnbe)
405FOP_SETCC(sets)
406FOP_SETCC(setns)
407FOP_SETCC(setp)
408FOP_SETCC(setnp)
409FOP_SETCC(setl)
410FOP_SETCC(setnl)
411FOP_SETCC(setle)
412FOP_SETCC(setnle)
413FOP_END;
414
326f578f
PB		 415FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
416FOP_END;
417
8a76d7f2
JR		 418static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
419 enum x86_intercept intercept,
420 enum x86_intercept_stage stage)
421{
422 struct x86_instruction_info info = {
423 .intercept = intercept,
9dac77fa
AK		 424 .rep_prefix = ctxt->rep_prefix,
425 .modrm_mod = ctxt->modrm_mod,
426 .modrm_reg = ctxt->modrm_reg,
427 .modrm_rm = ctxt->modrm_rm,
428 .src_val = ctxt->src.val64,
429 .src_bytes = ctxt->src.bytes,
430 .dst_bytes = ctxt->dst.bytes,
431 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 432 .next_rip = ctxt->eip,
433 };
434
2953538e 435 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 436}
437
f47cfa31
AK		 438static void assign_masked(ulong *dest, ulong src, ulong mask)
439{
440 *dest = (*dest & ~mask) | (src & mask);
441}
442
9dac77fa 443static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 444{
9dac77fa 445 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 446}
447
f47cfa31
AK		 448static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
449{
450 u16 sel;
451 struct desc_struct ss;
452
453 if (ctxt->mode == X86EMUL_MODE_PROT64)
454 return ~0UL;
455 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
456 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
457}
458
612e89f0
AK		 459static int stack_size(struct x86_emulate_ctxt *ctxt)
460{
461 return (__fls(stack_mask(ctxt)) + 1) >> 3;
462}
463
6aa8b732 464/* Access/update address held in a register, based on addressing mode. */
e4706772 465static inline unsigned long
9dac77fa 466address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 467{
9dac77fa 468 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 469 return reg;
470 else
9dac77fa 471 return reg & ad_mask(ctxt);
e4706772
HH		 472}
473
474static inline unsigned long
9dac77fa 475register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 476{
9dac77fa 477 return address_mask(ctxt, reg);
e4706772
HH		 478}
479
5ad105e5
AK		 480static void masked_increment(ulong *reg, ulong mask, int inc)
481{
482 assign_masked(reg, *reg + inc, mask);
483}
484
7a957275 485static inline void
9dac77fa 486register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 487{
5ad105e5
AK		 488 ulong mask;
489
9dac77fa 490 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 491 mask = ~0UL;
7a957275 492 else
5ad105e5
AK		 493 mask = ad_mask(ctxt);
494 masked_increment(reg, mask, inc);
495}
496
497static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
498{
dd856efa 499 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 500}
6aa8b732 501
9dac77fa 502static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 503{
9dac77fa 504 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 505}
098c937b 506
56697687
AK		 507static u32 desc_limit_scaled(struct desc_struct *desc)
508{
509 u32 limit = get_desc_limit(desc);
510
511 return desc->g ? (limit << 12) | 0xfff : limit;
512}
513
9dac77fa 514static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 515{
9dac77fa
AK		 516 ctxt->has_seg_override = true;
517 ctxt->seg_override = seg;
7a5b56df
AK		 518}
519
7b105ca2 520static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 521{
522 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
523 return 0;
524
7b105ca2 525 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 526}
527
9dac77fa 528static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 529{
9dac77fa 530 if (!ctxt->has_seg_override)
7a5b56df
AK		 531 return 0;
532
9dac77fa 533 return ctxt->seg_override;
7a5b56df
AK		 534}
535
35d3d4a1
AK		 536static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
537 u32 error, bool valid)
54b8486f 538{
da9cb575
AK		 539 ctxt->exception.vector = vec;
540 ctxt->exception.error_code = error;
541 ctxt->exception.error_code_valid = valid;
35d3d4a1 542 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 543}
544
3b88e41a
JR		 545static int emulate_db(struct x86_emulate_ctxt *ctxt)
546{
547 return emulate_exception(ctxt, DB_VECTOR, 0, false);
548}
549
35d3d4a1 550static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 551{
35d3d4a1 552 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 553}
554
618ff15d
AK		 555static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
556{
557 return emulate_exception(ctxt, SS_VECTOR, err, true);
558}
559
35d3d4a1 560static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 561{
35d3d4a1 562 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 563}
564
35d3d4a1 565static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 566{
35d3d4a1 567 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 568}
569
34d1f490
AK		 570static int emulate_de(struct x86_emulate_ctxt *ctxt)
571{
35d3d4a1 572 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 573}
574
1253791d
AK		 575static int emulate_nm(struct x86_emulate_ctxt *ctxt)
576{
577 return emulate_exception(ctxt, NM_VECTOR, 0, false);
578}
579
1aa36616
AK		 580static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
581{
582 u16 selector;
583 struct desc_struct desc;
584
585 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
586 return selector;
587}
588
589static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
590 unsigned seg)
591{
592 u16 dummy;
593 u32 base3;
594 struct desc_struct desc;
595
596 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
597 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
598}
599
1c11b376
AK		 600/*
601 * x86 defines three classes of vector instructions: explicitly
602 * aligned, explicitly unaligned, and the rest, which change behaviour
603 * depending on whether they're AVX encoded or not.
604 *
605 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
606 * subject to the same check.
607 */
608static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
609{
610 if (likely(size < 16))
611 return false;
612
613 if (ctxt->d & Aligned)
614 return true;
615 else if (ctxt->d & Unaligned)
616 return false;
617 else if (ctxt->d & Avx)
618 return false;
619 else
620 return true;
621}
622
3d9b938e 623static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 624 struct segmented_address addr,
3d9b938e 625 unsigned size, bool write, bool fetch,
52fd8b44
AK		 626 ulong *linear)
627{
618ff15d
AK		 628 struct desc_struct desc;
629 bool usable;
52fd8b44 630 ulong la;
618ff15d 631 u32 lim;
1aa36616 632 u16 sel;
3a78a4f4 633 unsigned cpl;
52fd8b44 634
7b105ca2 635 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d 636 switch (ctxt->mode) {
618ff15d
AK		 637 case X86EMUL_MODE_PROT64:
638 if (((signed long)la << 16) >> 16 != la)
639 return emulate_gp(ctxt, 0);
640 break;
641 default:
1aa36616
AK		 642 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
643 addr.seg);
618ff15d
AK		 644 if (!usable)
645 goto bad;
58b7825b
GN		 646 /* code segment in protected mode or read-only data segment */
647 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
648 || !(desc.type & 2)) && write)
618ff15d
AK		 649 goto bad;
650 /* unreadable code segment */
3d9b938e 651 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 652 goto bad;
653 lim = desc_limit_scaled(&desc);
654 if ((desc.type & 8) || !(desc.type & 4)) {
655 /* expand-up segment */
656 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
657 goto bad;
658 } else {
fc058680 659 /* expand-down segment */
618ff15d
AK		 660 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
661 goto bad;
662 lim = desc.d ? 0xffffffff : 0xffff;
663 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
664 goto bad;
665 }
717746e3 666 cpl = ctxt->ops->cpl(ctxt);
618ff15d
AK		 667 if (!(desc.type & 8)) {
668 /* data segment */
669 if (cpl > desc.dpl)
670 goto bad;
671 } else if ((desc.type & 8) && !(desc.type & 4)) {
672 /* nonconforming code segment */
673 if (cpl != desc.dpl)
674 goto bad;
675 } else if ((desc.type & 8) && (desc.type & 4)) {
676 /* conforming code segment */
677 if (cpl < desc.dpl)
678 goto bad;
679 }
680 break;
681 }
9dac77fa 682 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 683 la &= (u32)-1;
1c11b376
AK		 684 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
685 return emulate_gp(ctxt, 0);
52fd8b44
AK		 686 *linear = la;
687 return X86EMUL_CONTINUE;
618ff15d
AK		 688bad:
689 if (addr.seg == VCPU_SREG_SS)
0afbe2f8 690 return emulate_ss(ctxt, sel);
618ff15d 691 else
0afbe2f8 692 return emulate_gp(ctxt, sel);
52fd8b44
AK		 693}
694
3d9b938e
NE		 695static int linearize(struct x86_emulate_ctxt *ctxt,
696 struct segmented_address addr,
697 unsigned size, bool write,
698 ulong *linear)
699{
700 return __linearize(ctxt, addr, size, write, false, linear);
701}
702
703
3ca3ac4d
AK		 704static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
705 struct segmented_address addr,
706 void *data,
707 unsigned size)
708{
9fa088f4
AK		 709 int rc;
710 ulong linear;
711
83b8795a 712 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 713 if (rc != X86EMUL_CONTINUE)
714 return rc;
0f65dd70 715 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 716}
717
807941b1
TY		 718/*
719 * Fetch the next byte of the instruction being emulated which is pointed to
720 * by ctxt->_eip, then increment ctxt->_eip.
721 *
722 * Also prefetch the remaining bytes of the instruction without crossing page
723 * boundary if they are not in fetch_cache yet.
724 */
725static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 726{
9dac77fa 727 struct fetch_cache *fc = &ctxt->fetch;
62266869 728 int rc;
2fb53ad8 729 int size, cur_size;
62266869 730
807941b1 731 if (ctxt->_eip == fc->end) {
3d9b938e 732 unsigned long linear;
807941b1
TY		 733 struct segmented_address addr = { .seg = VCPU_SREG_CS,
734 .ea = ctxt->_eip };
2fb53ad8 735 cur_size = fc->end - fc->start;
807941b1
TY		 736 size = min(15UL - cur_size,
737 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 738 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 739 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 740 return rc;
ef5d75cc
TY		 741 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
742 size, &ctxt->exception);
7d88bb48 743 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 744 return rc;
2fb53ad8 745 fc->end += size;
62266869 746 }
807941b1
TY		 747 *dest = fc->data[ctxt->_eip - fc->start];
748 ctxt->_eip++;
3e2815e9 749 return X86EMUL_CONTINUE;
62266869
AK		 750}
751
752static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 753 void *dest, unsigned size)
62266869 754{
3e2815e9 755 int rc;
62266869 756
eb3c79e6 757 /* x86 instructions are limited to 15 bytes. */
7d88bb48 758 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 759 return X86EMUL_UNHANDLEABLE;
62266869 760 while (size--) {
807941b1 761 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 762 if (rc != X86EMUL_CONTINUE)
62266869
AK		 763 return rc;
764 }
3e2815e9 765 return X86EMUL_CONTINUE;
62266869
AK		 766}
767
67cbc90d 768/* Fetch next part of the instruction being emulated. */
e85a1085 769#define insn_fetch(_type, _ctxt) \
67cbc90d 770({ unsigned long _x; \
e85a1085 771 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 772 if (rc != X86EMUL_CONTINUE) \
773 goto done; \
67cbc90d
TY		 774 (_type)_x; \
775})
776
807941b1
TY		 777#define insn_fetch_arr(_arr, _size, _ctxt) \
778({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 779 if (rc != X86EMUL_CONTINUE) \
780 goto done; \
67cbc90d
TY		 781})
782
1e3c5cb0
RR		 783/*
784 * Given the 'reg' portion of a ModRM byte, and a register block, return a
785 * pointer into the block that addresses the relevant register.
786 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
787 */
dd856efa 788static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 789 int byteop)
6aa8b732
AK		 790{
791 void *p;
aa9ac1a6 792 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 793
6aa8b732 794 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 795 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
796 else
797 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 798 return p;
799}
800
801static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 802 struct segmented_address addr,
6aa8b732
AK		 803 u16 *size, unsigned long *address, int op_bytes)
804{
805 int rc;
806
807 if (op_bytes == 2)
808 op_bytes = 3;
809 *address = 0;
3ca3ac4d 810 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 811 if (rc != X86EMUL_CONTINUE)
6aa8b732 812 return rc;
30b31ab6 813 addr.ea += 2;
3ca3ac4d 814 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 815 return rc;
816}
817
34b77652
AK		 818FASTOP2(add);
819FASTOP2(or);
820FASTOP2(adc);
821FASTOP2(sbb);
822FASTOP2(and);
823FASTOP2(sub);
824FASTOP2(xor);
825FASTOP2(cmp);
826FASTOP2(test);
827
b9fa409b
AK		 828FASTOP1SRC2(mul, mul_ex);
829FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 830FASTOP1SRC2EX(div, div_ex);
831FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 832
34b77652
AK		 833FASTOP3WCL(shld);
834FASTOP3WCL(shrd);
835
836FASTOP2W(imul);
837
838FASTOP1(not);
839FASTOP1(neg);
840FASTOP1(inc);
841FASTOP1(dec);
842
843FASTOP2CL(rol);
844FASTOP2CL(ror);
845FASTOP2CL(rcl);
846FASTOP2CL(rcr);
847FASTOP2CL(shl);
848FASTOP2CL(shr);
849FASTOP2CL(sar);
850
851FASTOP2W(bsf);
852FASTOP2W(bsr);
853FASTOP2W(bt);
854FASTOP2W(bts);
855FASTOP2W(btr);
856FASTOP2W(btc);
857
e47a5f5f
AK		 858FASTOP2(xadd);
859
9ae9feba 860static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 861{
9ae9feba
AK		 862 u8 rc;
863 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 864
9ae9feba 865 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 866 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 867 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
868 return rc;
bbe9abbd
NK		 869}
870
91ff3cb4
AK		 871static void fetch_register_operand(struct operand *op)
872{
873 switch (op->bytes) {
874 case 1:
875 op->val = *(u8 *)op->addr.reg;
876 break;
877 case 2:
878 op->val = *(u16 *)op->addr.reg;
879 break;
880 case 4:
881 op->val = *(u32 *)op->addr.reg;
882 break;
883 case 8:
884 op->val = *(u64 *)op->addr.reg;
885 break;
886 }
887}
888
1253791d
AK		 889static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
890{
891 ctxt->ops->get_fpu(ctxt);
892 switch (reg) {
89a87c67
MK		 893 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
894 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
895 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
896 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
897 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
898 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
899 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
900 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 901#ifdef CONFIG_X86_64
89a87c67
MK		 902 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
903 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
904 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
905 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
906 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
907 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
908 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
909 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 910#endif
911 default: BUG();
912 }
913 ctxt->ops->put_fpu(ctxt);
914}
915
916static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
917 int reg)
918{
919 ctxt->ops->get_fpu(ctxt);
920 switch (reg) {
89a87c67
MK		 921 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
922 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
923 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
924 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
925 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
926 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
927 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
928 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 929#ifdef CONFIG_X86_64
89a87c67
MK		 930 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
931 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
932 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
933 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
934 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
935 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
936 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
937 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 938#endif
939 default: BUG();
940 }
941 ctxt->ops->put_fpu(ctxt);
942}
943
cbe2c9d3
AK		 944static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
945{
946 ctxt->ops->get_fpu(ctxt);
947 switch (reg) {
948 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
949 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
950 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
951 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
952 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
953 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
954 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
955 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
956 default: BUG();
957 }
958 ctxt->ops->put_fpu(ctxt);
959}
960
961static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
962{
963 ctxt->ops->get_fpu(ctxt);
964 switch (reg) {
965 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
966 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
967 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
968 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
969 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
970 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
971 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
972 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
973 default: BUG();
974 }
975 ctxt->ops->put_fpu(ctxt);
976}
977
045a282c
GN		 978static int em_fninit(struct x86_emulate_ctxt *ctxt)
979{
980 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
981 return emulate_nm(ctxt);
982
983 ctxt->ops->get_fpu(ctxt);
984 asm volatile("fninit");
985 ctxt->ops->put_fpu(ctxt);
986 return X86EMUL_CONTINUE;
987}
988
989static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
990{
991 u16 fcw;
992
993 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
994 return emulate_nm(ctxt);
995
996 ctxt->ops->get_fpu(ctxt);
997 asm volatile("fnstcw %0": "+m"(fcw));
998 ctxt->ops->put_fpu(ctxt);
999
1000 /* force 2 byte destination */
1001 ctxt->dst.bytes = 2;
1002 ctxt->dst.val = fcw;
1003
1004 return X86EMUL_CONTINUE;
1005}
1006
1007static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1008{
1009 u16 fsw;
1010
1011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1012 return emulate_nm(ctxt);
1013
1014 ctxt->ops->get_fpu(ctxt);
1015 asm volatile("fnstsw %0": "+m"(fsw));
1016 ctxt->ops->put_fpu(ctxt);
1017
1018 /* force 2 byte destination */
1019 ctxt->dst.bytes = 2;
1020 ctxt->dst.val = fsw;
1021
1022 return X86EMUL_CONTINUE;
1023}
1024
1253791d 1025static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1026 struct operand *op)
3c118e24 1027{
9dac77fa 1028 unsigned reg = ctxt->modrm_reg;
33615aa9 1029
9dac77fa
AK		 1030 if (!(ctxt->d & ModRM))
1031 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1032
9dac77fa 1033 if (ctxt->d & Sse) {
1253791d
AK		 1034 op->type = OP_XMM;
1035 op->bytes = 16;
1036 op->addr.xmm = reg;
1037 read_sse_reg(ctxt, &op->vec_val, reg);
1038 return;
1039 }
cbe2c9d3
AK		 1040 if (ctxt->d & Mmx) {
1041 reg &= 7;
1042 op->type = OP_MM;
1043 op->bytes = 8;
1044 op->addr.mm = reg;
1045 return;
1046 }
1253791d 1047
3c118e24 1048 op->type = OP_REG;
6d4d85ec
GN		 1049 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1050 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1051
91ff3cb4 1052 fetch_register_operand(op);
3c118e24
AK		 1053 op->orig_val = op->val;
1054}
1055
a6e3407b
AK		 1056static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1057{
1058 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1059 ctxt->modrm_seg = VCPU_SREG_SS;
1060}
1061
1c73ef66 1062static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1063 struct operand *op)
1c73ef66 1064{
1c73ef66 1065 u8 sib;
f5b4edcd 1066 int index_reg = 0, base_reg = 0, scale;
3e2815e9 1067 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1068 ulong modrm_ea = 0;
1c73ef66 1069
9dac77fa
AK		 1070 if (ctxt->rex_prefix) {
1071 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1072 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1073 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1074 }
1075
9dac77fa
AK		 1076 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1077 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1078 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1079 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1080
9b88ae99 1081 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1082 op->type = OP_REG;
9dac77fa 1083 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1084 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1085 ctxt->d & ByteOp);
9dac77fa 1086 if (ctxt->d & Sse) {
1253791d
AK		 1087 op->type = OP_XMM;
1088 op->bytes = 16;
9dac77fa
AK		 1089 op->addr.xmm = ctxt->modrm_rm;
1090 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1091 return rc;
1092 }
cbe2c9d3
AK		 1093 if (ctxt->d & Mmx) {
1094 op->type = OP_MM;
1095 op->bytes = 8;
1096 op->addr.xmm = ctxt->modrm_rm & 7;
1097 return rc;
1098 }
2dbd0dd7 1099 fetch_register_operand(op);
1c73ef66
AK		 1100 return rc;
1101 }
1102
2dbd0dd7
AK		 1103 op->type = OP_MEM;
1104
9dac77fa 1105 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1106 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1107 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1108 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1109 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1110
1111 /* 16-bit ModR/M decode. */
9dac77fa 1112 switch (ctxt->modrm_mod) {
1c73ef66 1113 case 0:
9dac77fa 1114 if (ctxt->modrm_rm == 6)
e85a1085 1115 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1116 break;
1117 case 1:
e85a1085 1118 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1119 break;
1120 case 2:
e85a1085 1121 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1122 break;
1123 }
9dac77fa 1124 switch (ctxt->modrm_rm) {
1c73ef66 1125 case 0:
2dbd0dd7 1126 modrm_ea += bx + si;
1c73ef66
AK		 1127 break;
1128 case 1:
2dbd0dd7 1129 modrm_ea += bx + di;
1c73ef66
AK		 1130 break;
1131 case 2:
2dbd0dd7 1132 modrm_ea += bp + si;
1c73ef66
AK		 1133 break;
1134 case 3:
2dbd0dd7 1135 modrm_ea += bp + di;
1c73ef66
AK		 1136 break;
1137 case 4:
2dbd0dd7 1138 modrm_ea += si;
1c73ef66
AK		 1139 break;
1140 case 5:
2dbd0dd7 1141 modrm_ea += di;
1c73ef66
AK		 1142 break;
1143 case 6:
9dac77fa 1144 if (ctxt->modrm_mod != 0)
2dbd0dd7 1145 modrm_ea += bp;
1c73ef66
AK		 1146 break;
1147 case 7:
2dbd0dd7 1148 modrm_ea += bx;
1c73ef66
AK		 1149 break;
1150 }
9dac77fa
AK		 1151 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1152 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1153 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1154 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1155 } else {
1156 /* 32/64-bit ModR/M decode. */
9dac77fa 1157 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1158 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1159 index_reg |= (sib >> 3) & 7;
1160 base_reg |= sib & 7;
1161 scale = sib >> 6;
1162
9dac77fa 1163 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1164 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1165 else {
dd856efa 1166 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1167 adjust_modrm_seg(ctxt, base_reg);
1168 }
dc71d0f1 1169 if (index_reg != 4)
dd856efa 1170 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1171 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1172 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1173 ctxt->rip_relative = 1;
a6e3407b
AK		 1174 } else {
1175 base_reg = ctxt->modrm_rm;
dd856efa 1176 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1177 adjust_modrm_seg(ctxt, base_reg);
1178 }
9dac77fa 1179 switch (ctxt->modrm_mod) {
1c73ef66 1180 case 0:
9dac77fa 1181 if (ctxt->modrm_rm == 5)
e85a1085 1182 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1183 break;
1184 case 1:
e85a1085 1185 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1186 break;
1187 case 2:
e85a1085 1188 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1189 break;
1190 }
1191 }
90de84f5 1192 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1193done:
1194 return rc;
1195}
1196
1197static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1198 struct operand *op)
1c73ef66 1199{
3e2815e9 1200 int rc = X86EMUL_CONTINUE;
1c73ef66 1201
2dbd0dd7 1202 op->type = OP_MEM;
9dac77fa 1203 switch (ctxt->ad_bytes) {
1c73ef66 1204 case 2:
e85a1085 1205 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1206 break;
1207 case 4:
e85a1085 1208 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1209 break;
1210 case 8:
e85a1085 1211 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1212 break;
1213 }
1214done:
1215 return rc;
1216}
1217
9dac77fa 1218static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1219{
7129eeca 1220 long sv = 0, mask;
35c843c4 1221
9dac77fa
AK		 1222 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1223 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1224
9dac77fa
AK		 1225 if (ctxt->src.bytes == 2)
1226 sv = (s16)ctxt->src.val & (s16)mask;
1227 else if (ctxt->src.bytes == 4)
1228 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1229
9dac77fa 1230 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1231 }
ba7ff2b7
WY		 1232
1233 /* only subword offset */
9dac77fa 1234 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1235}
1236
dde7e6d1 1237static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1238 unsigned long addr, void *dest, unsigned size)
6aa8b732 1239{
dde7e6d1 1240 int rc;
9dac77fa 1241 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1242
f23b070e
XG		 1243 if (mc->pos < mc->end)
1244 goto read_cached;
6aa8b732 1245
f23b070e
XG		 1246 WARN_ON((mc->end + size) >= sizeof(mc->data));
1247
1248 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1249 &ctxt->exception);
1250 if (rc != X86EMUL_CONTINUE)
1251 return rc;
1252
1253 mc->end += size;
1254
1255read_cached:
1256 memcpy(dest, mc->data + mc->pos, size);
1257 mc->pos += size;
dde7e6d1
AK		 1258 return X86EMUL_CONTINUE;
1259}
6aa8b732 1260
3ca3ac4d
AK		 1261static int segmented_read(struct x86_emulate_ctxt *ctxt,
1262 struct segmented_address addr,
1263 void *data,
1264 unsigned size)
1265{
9fa088f4
AK		 1266 int rc;
1267 ulong linear;
1268
83b8795a 1269 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1270 if (rc != X86EMUL_CONTINUE)
1271 return rc;
7b105ca2 1272 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1273}
1274
1275static int segmented_write(struct x86_emulate_ctxt *ctxt,
1276 struct segmented_address addr,
1277 const void *data,
1278 unsigned size)
1279{
9fa088f4
AK		 1280 int rc;
1281 ulong linear;
1282
83b8795a 1283 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1284 if (rc != X86EMUL_CONTINUE)
1285 return rc;
0f65dd70
AK		 1286 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1287 &ctxt->exception);
3ca3ac4d
AK		 1288}
1289
1290static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1291 struct segmented_address addr,
1292 const void *orig_data, const void *data,
1293 unsigned size)
1294{
9fa088f4
AK		 1295 int rc;
1296 ulong linear;
1297
83b8795a 1298 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
0f65dd70
AK		 1301 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1302 size, &ctxt->exception);
3ca3ac4d
AK		 1303}
1304
dde7e6d1 1305static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1306 unsigned int size, unsigned short port,
1307 void *dest)
1308{
9dac77fa 1309 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1310
dde7e6d1 1311 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1312 unsigned int in_page, n;
9dac77fa 1313 unsigned int count = ctxt->rep_prefix ?
dd856efa 1314 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1315 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1316 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1317 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
dde7e6d1
AK		 1318 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1319 count);
1320 if (n == 0)
1321 n = 1;
1322 rc->pos = rc->end = 0;
7b105ca2 1323 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1324 return 0;
1325 rc->end = n * size;
6aa8b732
AK		 1326 }
1327
e6e39f04
NA		 1328 if (ctxt->rep_prefix && (ctxt->d & String) &&
1329 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1330 ctxt->dst.data = rc->data + rc->pos;
1331 ctxt->dst.type = OP_MEM_STR;
1332 ctxt->dst.count = (rc->end - rc->pos) / size;
1333 rc->pos = rc->end;
1334 } else {
1335 memcpy(dest, rc->data + rc->pos, size);
1336 rc->pos += size;
1337 }
dde7e6d1
AK		 1338 return 1;
1339}
6aa8b732 1340
7f3d35fd
KW		 1341static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1342 u16 index, struct desc_struct *desc)
1343{
1344 struct desc_ptr dt;
1345 ulong addr;
1346
1347 ctxt->ops->get_idt(ctxt, &dt);
1348
1349 if (dt.size < index * 8 + 7)
1350 return emulate_gp(ctxt, index << 3 | 0x2);
1351
1352 addr = dt.address + index * 8;
1353 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1354 &ctxt->exception);
1355}
1356
dde7e6d1 1357static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1358 u16 selector, struct desc_ptr *dt)
1359{
0225fb50 1360 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1361 u32 base3 = 0;
7b105ca2 1362
dde7e6d1
AK		 1363 if (selector & 1 << 2) {
1364 struct desc_struct desc;
1aa36616
AK		 1365 u16 sel;
1366
dde7e6d1 1367 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1368 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1369 VCPU_SREG_LDTR))
dde7e6d1 1370 return;
e09d082c 1371
dde7e6d1 1372 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1373 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1374 } else
4bff1e86 1375 ops->get_gdt(ctxt, dt);
dde7e6d1 1376}
120df890 1377
dde7e6d1
AK		 1378/* allowed just for 8 bytes segments */
1379static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1380 u16 selector, struct desc_struct *desc,
1381 ulong *desc_addr_p)
dde7e6d1
AK		 1382{
1383 struct desc_ptr dt;
1384 u16 index = selector >> 3;
dde7e6d1 1385 ulong addr;
120df890 1386
7b105ca2 1387 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1388
35d3d4a1
AK		 1389 if (dt.size < index * 8 + 7)
1390 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1391
e919464b 1392 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1393 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1394 &ctxt->exception);
dde7e6d1 1395}
ef65c889 1396
dde7e6d1
AK		 1397/* allowed just for 8 bytes segments */
1398static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1399 u16 selector, struct desc_struct *desc)
1400{
1401 struct desc_ptr dt;
1402 u16 index = selector >> 3;
dde7e6d1 1403 ulong addr;
6aa8b732 1404
7b105ca2 1405 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1406
35d3d4a1
AK		 1407 if (dt.size < index * 8 + 7)
1408 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1409
dde7e6d1 1410 addr = dt.address + index * 8;
7b105ca2
TY		 1411 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1412 &ctxt->exception);
dde7e6d1 1413}
c7e75a3d 1414
5601d05b 1415/* Does not support long mode */
2356aaeb 1416static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
5045b468 1417 u16 selector, int seg, u8 cpl, bool in_task_switch)
dde7e6d1 1418{
869be99c 1419 struct desc_struct seg_desc, old_desc;
2356aaeb 1420 u8 dpl, rpl;
dde7e6d1
AK		 1421 unsigned err_vec = GP_VECTOR;
1422 u32 err_code = 0;
1423 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1424 ulong desc_addr;
dde7e6d1 1425 int ret;
03ebebeb 1426 u16 dummy;
e37a75a1 1427 u32 base3 = 0;
69f55cb1 1428
dde7e6d1 1429 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1430
f8da94e9
KW		 1431 if (ctxt->mode == X86EMUL_MODE_REAL) {
1432 /* set real mode segment descriptor (keep limit etc. for
1433 * unreal mode) */
03ebebeb 1434 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1435 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1436 goto load;
f8da94e9
KW		 1437 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1438 /* VM86 needs a clean new segment descriptor */
1439 set_desc_base(&seg_desc, selector << 4);
1440 set_desc_limit(&seg_desc, 0xffff);
1441 seg_desc.type = 3;
1442 seg_desc.p = 1;
1443 seg_desc.s = 1;
1444 seg_desc.dpl = 3;
1445 goto load;
dde7e6d1
AK		 1446 }
1447
79d5b4c3 1448 rpl = selector & 3;
79d5b4c3
AK		 1449
1450 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1451 if ((seg == VCPU_SREG_CS
1452 || (seg == VCPU_SREG_SS
1453 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1454 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1455 && null_selector)
1456 goto exception;
1457
1458 /* TR should be in GDT only */
1459 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1460 goto exception;
1461
1462 if (null_selector) /* for NULL selector skip all following checks */
1463 goto load;
1464
e919464b 1465 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1466 if (ret != X86EMUL_CONTINUE)
1467 return ret;
1468
1469 err_code = selector & 0xfffc;
1470 err_vec = GP_VECTOR;
1471
fc058680 1472 /* can't load system descriptor into segment selector */
dde7e6d1
AK		 1473 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1474 goto exception;
1475
1476 if (!seg_desc.p) {
1477 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1478 goto exception;
1479 }
1480
dde7e6d1 1481 dpl = seg_desc.dpl;
dde7e6d1
AK		 1482
1483 switch (seg) {
1484 case VCPU_SREG_SS:
1485 /*
1486 * segment is not a writable data segment or segment
1487 * selector's RPL != CPL or segment selector's RPL != CPL
1488 */
1489 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1490 goto exception;
6aa8b732 1491 break;
dde7e6d1 1492 case VCPU_SREG_CS:
5045b468
PB		 1493 if (in_task_switch && rpl != dpl)
1494 goto exception;
1495
dde7e6d1
AK		 1496 if (!(seg_desc.type & 8))
1497 goto exception;
1498
1499 if (seg_desc.type & 4) {
1500 /* conforming */
1501 if (dpl > cpl)
1502 goto exception;
1503 } else {
1504 /* nonconforming */
1505 if (rpl > cpl || dpl != cpl)
1506 goto exception;
1507 }
1508 /* CS(RPL) <- CPL */
1509 selector = (selector & 0xfffc) | cpl;
6aa8b732 1510 break;
dde7e6d1
AK		 1511 case VCPU_SREG_TR:
1512 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1513 goto exception;
869be99c
AK		 1514 old_desc = seg_desc;
1515 seg_desc.type |= 2; /* busy */
1516 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1517 sizeof(seg_desc), &ctxt->exception);
1518 if (ret != X86EMUL_CONTINUE)
1519 return ret;
dde7e6d1
AK		 1520 break;
1521 case VCPU_SREG_LDTR:
1522 if (seg_desc.s || seg_desc.type != 2)
1523 goto exception;
1524 break;
1525 default: /* DS, ES, FS, or GS */
4e62417b 1526 /*
dde7e6d1
AK		 1527 * segment is not a data or readable code segment or
1528 * ((segment is a data or nonconforming code segment)
1529 * and (both RPL and CPL > DPL))
4e62417b 1530 */
dde7e6d1
AK		 1531 if ((seg_desc.type & 0xa) == 0x8 ||
1532 (((seg_desc.type & 0xc) != 0xc) &&
1533 (rpl > dpl && cpl > dpl)))
1534 goto exception;
6aa8b732 1535 break;
dde7e6d1
AK		 1536 }
1537
1538 if (seg_desc.s) {
1539 /* mark segment as accessed */
1540 seg_desc.type |= 1;
7b105ca2 1541 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1542 if (ret != X86EMUL_CONTINUE)
1543 return ret;
e37a75a1
NA		 1544 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1545 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1546 sizeof(base3), &ctxt->exception);
1547 if (ret != X86EMUL_CONTINUE)
1548 return ret;
dde7e6d1
AK		 1549 }
1550load:
e37a75a1 1551 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
dde7e6d1
AK		 1552 return X86EMUL_CONTINUE;
1553exception:
1554 emulate_exception(ctxt, err_vec, err_code, true);
1555 return X86EMUL_PROPAGATE_FAULT;
1556}
1557
2356aaeb
PB		 1558static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1559 u16 selector, int seg)
1560{
1561 u8 cpl = ctxt->ops->cpl(ctxt);
5045b468 1562 return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
2356aaeb
PB		 1563}
1564
31be40b3
WY		 1565static void write_register_operand(struct operand *op)
1566{
1567 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1568 switch (op->bytes) {
1569 case 1:
1570 *(u8 *)op->addr.reg = (u8)op->val;
1571 break;
1572 case 2:
1573 *(u16 *)op->addr.reg = (u16)op->val;
1574 break;
1575 case 4:
1576 *op->addr.reg = (u32)op->val;
1577 break; /* 64b: zero-extend */
1578 case 8:
1579 *op->addr.reg = op->val;
1580 break;
1581 }
1582}
1583
fb32b1ed 1584static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1
AK		 1585{
1586 int rc;
dde7e6d1 1587
fb32b1ed 1588 switch (op->type) {
dde7e6d1 1589 case OP_REG:
fb32b1ed 1590 write_register_operand(op);
6aa8b732 1591 break;
dde7e6d1 1592 case OP_MEM:
9dac77fa 1593 if (ctxt->lock_prefix)
3ca3ac4d 1594 rc = segmented_cmpxchg(ctxt,
fb32b1ed
AK		 1595 op->addr.mem,
1596 &op->orig_val,
1597 &op->val,
1598 op->bytes);
341de7e3 1599 else
3ca3ac4d 1600 rc = segmented_write(ctxt,
fb32b1ed
AK		 1601 op->addr.mem,
1602 &op->val,
1603 op->bytes);
dde7e6d1
AK		 1604 if (rc != X86EMUL_CONTINUE)
1605 return rc;
a682e354 1606 break;
b3356bf0
GN		 1607 case OP_MEM_STR:
1608 rc = segmented_write(ctxt,
fb32b1ed
AK		 1609 op->addr.mem,
1610 op->data,
1611 op->bytes * op->count);
b3356bf0
GN		 1612 if (rc != X86EMUL_CONTINUE)
1613 return rc;
1614 break;
1253791d 1615 case OP_XMM:
fb32b1ed 1616 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1617 break;
cbe2c9d3 1618 case OP_MM:
fb32b1ed 1619 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1620 break;
dde7e6d1
AK		 1621 case OP_NONE:
1622 /* no writeback */
414e6277 1623 break;
dde7e6d1 1624 default:
414e6277 1625 break;
6aa8b732 1626 }
dde7e6d1
AK		 1627 return X86EMUL_CONTINUE;
1628}
6aa8b732 1629
51ddff50 1630static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1631{
4179bb02 1632 struct segmented_address addr;
0dc8d10f 1633
5ad105e5 1634 rsp_increment(ctxt, -bytes);
dd856efa 1635 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1636 addr.seg = VCPU_SREG_SS;
1637
51ddff50
AK		 1638 return segmented_write(ctxt, addr, data, bytes);
1639}
1640
1641static int em_push(struct x86_emulate_ctxt *ctxt)
1642{
4179bb02 1643 /* Disable writeback. */
9dac77fa 1644 ctxt->dst.type = OP_NONE;
51ddff50 1645 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1646}
69f55cb1 1647
dde7e6d1 1648static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1649 void *dest, int len)
1650{
dde7e6d1 1651 int rc;
90de84f5 1652 struct segmented_address addr;
8b4caf66 1653
dd856efa 1654 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1655 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1656 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1657 if (rc != X86EMUL_CONTINUE)
1658 return rc;
1659
5ad105e5 1660 rsp_increment(ctxt, len);
dde7e6d1 1661 return rc;
8b4caf66
LV		 1662}
1663
c54fe504
TY		 1664static int em_pop(struct x86_emulate_ctxt *ctxt)
1665{
9dac77fa 1666 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1667}
1668
dde7e6d1 1669static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1670 void *dest, int len)
9de41573
GN		 1671{
1672 int rc;
dde7e6d1
AK		 1673 unsigned long val, change_mask;
1674 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1675 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1676
3b9be3bf 1677 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1678 if (rc != X86EMUL_CONTINUE)
1679 return rc;
9de41573 1680
dde7e6d1
AK		 1681 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1682 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1683
dde7e6d1
AK		 1684 switch(ctxt->mode) {
1685 case X86EMUL_MODE_PROT64:
1686 case X86EMUL_MODE_PROT32:
1687 case X86EMUL_MODE_PROT16:
1688 if (cpl == 0)
1689 change_mask |= EFLG_IOPL;
1690 if (cpl <= iopl)
1691 change_mask |= EFLG_IF;
1692 break;
1693 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1694 if (iopl < 3)
1695 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1696 change_mask |= EFLG_IF;
1697 break;
1698 default: /* real mode */
1699 change_mask |= (EFLG_IOPL | EFLG_IF);
1700 break;
9de41573 1701 }
dde7e6d1
AK		 1702
1703 *(unsigned long *)dest =
1704 (ctxt->eflags & ~change_mask) | (val & change_mask);
1705
1706 return rc;
9de41573
GN		 1707}
1708
62aaa2f0
TY		 1709static int em_popf(struct x86_emulate_ctxt *ctxt)
1710{
9dac77fa
AK		 1711 ctxt->dst.type = OP_REG;
1712 ctxt->dst.addr.reg = &ctxt->eflags;
1713 ctxt->dst.bytes = ctxt->op_bytes;
1714 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1715}
1716
612e89f0
AK		 1717static int em_enter(struct x86_emulate_ctxt *ctxt)
1718{
1719 int rc;
1720 unsigned frame_size = ctxt->src.val;
1721 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1722 ulong rbp;
612e89f0
AK		 1723
1724 if (nesting_level)
1725 return X86EMUL_UNHANDLEABLE;
1726
dd856efa
AK		 1727 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1728 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
dd856efa 1731 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1732 stack_mask(ctxt));
dd856efa
AK		 1733 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1734 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1735 stack_mask(ctxt));
1736 return X86EMUL_CONTINUE;
1737}
1738
f47cfa31
AK		 1739static int em_leave(struct x86_emulate_ctxt *ctxt)
1740{
dd856efa 1741 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1742 stack_mask(ctxt));
dd856efa 1743 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1744}
1745
1cd196ea 1746static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1747{
1cd196ea
AK		 1748 int seg = ctxt->src2.val;
1749
9dac77fa 1750 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1751
4487b3b4 1752 return em_push(ctxt);
7b262e90
GN		 1753}
1754
1cd196ea 1755static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1756{
1cd196ea 1757 int seg = ctxt->src2.val;
dde7e6d1
AK		 1758 unsigned long selector;
1759 int rc;
38ba30ba 1760
9dac77fa 1761 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1762 if (rc != X86EMUL_CONTINUE)
1763 return rc;
1764
7b105ca2 1765 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1766 return rc;
38ba30ba
GN		 1767}
1768
b96a7fad 1769static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1770{
dd856efa 1771 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1772 int rc = X86EMUL_CONTINUE;
1773 int reg = VCPU_REGS_RAX;
38ba30ba 1774
dde7e6d1
AK		 1775 while (reg <= VCPU_REGS_RDI) {
1776 (reg == VCPU_REGS_RSP) ?
dd856efa 1777 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1778
4487b3b4 1779 rc = em_push(ctxt);
dde7e6d1
AK		 1780 if (rc != X86EMUL_CONTINUE)
1781 return rc;
38ba30ba 1782
dde7e6d1 1783 ++reg;
38ba30ba 1784 }
38ba30ba 1785
dde7e6d1 1786 return rc;
38ba30ba
GN		 1787}
1788
62aaa2f0
TY		 1789static int em_pushf(struct x86_emulate_ctxt *ctxt)
1790{
9dac77fa 1791 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1792 return em_push(ctxt);
1793}
1794
b96a7fad 1795static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1796{
dde7e6d1
AK		 1797 int rc = X86EMUL_CONTINUE;
1798 int reg = VCPU_REGS_RDI;
38ba30ba 1799
dde7e6d1
AK		 1800 while (reg >= VCPU_REGS_RAX) {
1801 if (reg == VCPU_REGS_RSP) {
5ad105e5 1802 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1803 --reg;
1804 }
38ba30ba 1805
dd856efa 1806 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1807 if (rc != X86EMUL_CONTINUE)
1808 break;
1809 --reg;
38ba30ba 1810 }
dde7e6d1 1811 return rc;
38ba30ba
GN		 1812}
1813
dd856efa 1814static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1815{
0225fb50 1816 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1817 int rc;
6e154e56
MG		 1818 struct desc_ptr dt;
1819 gva_t cs_addr;
1820 gva_t eip_addr;
1821 u16 cs, eip;
6e154e56
MG		 1822
1823 /* TODO: Add limit checks */
9dac77fa 1824 ctxt->src.val = ctxt->eflags;
4487b3b4 1825 rc = em_push(ctxt);
5c56e1cf
AK		 1826 if (rc != X86EMUL_CONTINUE)
1827 return rc;
6e154e56
MG		 1828
1829 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1830
9dac77fa 1831 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1832 rc = em_push(ctxt);
5c56e1cf
AK		 1833 if (rc != X86EMUL_CONTINUE)
1834 return rc;
6e154e56 1835
9dac77fa 1836 ctxt->src.val = ctxt->_eip;
4487b3b4 1837 rc = em_push(ctxt);
5c56e1cf
AK		 1838 if (rc != X86EMUL_CONTINUE)
1839 return rc;
1840
4bff1e86 1841 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1842
1843 eip_addr = dt.address + (irq << 2);
1844 cs_addr = dt.address + (irq << 2) + 2;
1845
0f65dd70 1846 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1847 if (rc != X86EMUL_CONTINUE)
1848 return rc;
1849
0f65dd70 1850 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1851 if (rc != X86EMUL_CONTINUE)
1852 return rc;
1853
7b105ca2 1854 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1855 if (rc != X86EMUL_CONTINUE)
1856 return rc;
1857
9dac77fa 1858 ctxt->_eip = eip;
6e154e56
MG		 1859
1860 return rc;
1861}
1862
dd856efa
AK		 1863int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1864{
1865 int rc;
1866
1867 invalidate_registers(ctxt);
1868 rc = __emulate_int_real(ctxt, irq);
1869 if (rc == X86EMUL_CONTINUE)
1870 writeback_registers(ctxt);
1871 return rc;
1872}
1873
7b105ca2 1874static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1875{
1876 switch(ctxt->mode) {
1877 case X86EMUL_MODE_REAL:
dd856efa 1878 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1879 case X86EMUL_MODE_VM86:
1880 case X86EMUL_MODE_PROT16:
1881 case X86EMUL_MODE_PROT32:
1882 case X86EMUL_MODE_PROT64:
1883 default:
1884 /* Protected mode interrupts unimplemented yet */
1885 return X86EMUL_UNHANDLEABLE;
1886 }
1887}
1888
7b105ca2 1889static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1890{
dde7e6d1
AK		 1891 int rc = X86EMUL_CONTINUE;
1892 unsigned long temp_eip = 0;
1893 unsigned long temp_eflags = 0;
1894 unsigned long cs = 0;
1895 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1896 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1897 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1898 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1899
dde7e6d1 1900 /* TODO: Add stack limit check */
38ba30ba 1901
9dac77fa 1902 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1903
dde7e6d1
AK		 1904 if (rc != X86EMUL_CONTINUE)
1905 return rc;
38ba30ba 1906
35d3d4a1
AK		 1907 if (temp_eip & ~0xffff)
1908 return emulate_gp(ctxt, 0);
38ba30ba 1909
9dac77fa 1910 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1911
dde7e6d1
AK		 1912 if (rc != X86EMUL_CONTINUE)
1913 return rc;
38ba30ba 1914
9dac77fa 1915 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1916
dde7e6d1
AK		 1917 if (rc != X86EMUL_CONTINUE)
1918 return rc;
38ba30ba 1919
7b105ca2 1920 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1921
dde7e6d1
AK		 1922 if (rc != X86EMUL_CONTINUE)
1923 return rc;
38ba30ba 1924
9dac77fa 1925 ctxt->_eip = temp_eip;
38ba30ba 1926
38ba30ba 1927
9dac77fa 1928 if (ctxt->op_bytes == 4)
dde7e6d1 1929 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1930 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1931 ctxt->eflags &= ~0xffff;
1932 ctxt->eflags |= temp_eflags;
38ba30ba 1933 }
dde7e6d1
AK		 1934
1935 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1936 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1937
1938 return rc;
38ba30ba
GN		 1939}
1940
e01991e7 1941static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1942{
dde7e6d1
AK		 1943 switch(ctxt->mode) {
1944 case X86EMUL_MODE_REAL:
7b105ca2 1945 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1946 case X86EMUL_MODE_VM86:
1947 case X86EMUL_MODE_PROT16:
1948 case X86EMUL_MODE_PROT32:
1949 case X86EMUL_MODE_PROT64:
c37eda13 1950 default:
dde7e6d1
AK		 1951 /* iret from protected mode unimplemented yet */
1952 return X86EMUL_UNHANDLEABLE;
c37eda13 1953 }
c37eda13
WY		 1954}
1955
d2f62766
TY		 1956static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1957{
d2f62766
TY		 1958 int rc;
1959 unsigned short sel;
1960
9dac77fa 1961 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1962
7b105ca2 1963 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1964 if (rc != X86EMUL_CONTINUE)
1965 return rc;
1966
9dac77fa
AK		 1967 ctxt->_eip = 0;
1968 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1969 return X86EMUL_CONTINUE;
1970}
1971
51187683 1972static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1973{
4179bb02 1974 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1975
9dac77fa 1976 switch (ctxt->modrm_reg) {
d19292e4
MG		 1977 case 2: /* call near abs */ {
1978 long int old_eip;
9dac77fa
AK		 1979 old_eip = ctxt->_eip;
1980 ctxt->_eip = ctxt->src.val;
1981 ctxt->src.val = old_eip;
4487b3b4 1982 rc = em_push(ctxt);
d19292e4
MG		 1983 break;
1984 }
8cdbd2c9 1985 case 4: /* jmp abs */
9dac77fa 1986 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1987 break;
d2f62766
TY		 1988 case 5: /* jmp far */
1989 rc = em_jmp_far(ctxt);
1990 break;
8cdbd2c9 1991 case 6: /* push */
4487b3b4 1992 rc = em_push(ctxt);
8cdbd2c9 1993 break;
8cdbd2c9 1994 }
4179bb02 1995 return rc;
8cdbd2c9
LV		 1996}
1997
e0dac408 1998static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1999{
9dac77fa 2000 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2001
aaa05f24
NA		 2002 if (ctxt->dst.bytes == 16)
2003 return X86EMUL_UNHANDLEABLE;
2004
dd856efa
AK		 2005 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2006 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2007 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2008 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2009 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2010 } else {
dd856efa
AK		 2011 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2012 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2013
05f086f8 2014 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2015 }
1b30eaa8 2016 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2017}
2018
ebda02c2
TY		 2019static int em_ret(struct x86_emulate_ctxt *ctxt)
2020{
9dac77fa
AK		 2021 ctxt->dst.type = OP_REG;
2022 ctxt->dst.addr.reg = &ctxt->_eip;
2023 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 2024 return em_pop(ctxt);
2025}
2026
e01991e7 2027static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2028{
a77ab5ea
AK		 2029 int rc;
2030 unsigned long cs;
2031
9dac77fa 2032 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 2033 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2034 return rc;
9dac77fa
AK		 2035 if (ctxt->op_bytes == 4)
2036 ctxt->_eip = (u32)ctxt->_eip;
2037 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2038 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2039 return rc;
7b105ca2 2040 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 2041 return rc;
2042}
2043
3261107e
BR		 2044static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2045{
2046 int rc;
2047
2048 rc = em_ret_far(ctxt);
2049 if (rc != X86EMUL_CONTINUE)
2050 return rc;
2051 rsp_increment(ctxt, ctxt->src.val);
2052 return X86EMUL_CONTINUE;
2053}
2054
e940b5c2
TY		 2055static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2056{
2057 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2058 ctxt->dst.orig_val = ctxt->dst.val;
2059 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2060 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2061 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2062 fastop(ctxt, em_cmp);
e940b5c2
TY		 2063
2064 if (ctxt->eflags & EFLG_ZF) {
2065 /* Success: write back to memory. */
2066 ctxt->dst.val = ctxt->src.orig_val;
2067 } else {
2068 /* Failure: write the value we saw to EAX. */
2069 ctxt->dst.type = OP_REG;
dd856efa 2070 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2071 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2072 }
2073 return X86EMUL_CONTINUE;
2074}
2075
d4b4325f 2076static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2077{
d4b4325f 2078 int seg = ctxt->src2.val;
09b5f4d3
WY		 2079 unsigned short sel;
2080 int rc;
2081
9dac77fa 2082 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2083
7b105ca2 2084 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2085 if (rc != X86EMUL_CONTINUE)
2086 return rc;
2087
9dac77fa 2088 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2089 return rc;
2090}
2091
7b105ca2 2092static void
e66bb2cc 2093setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2094 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2095{
e66bb2cc 2096 cs->l = 0; /* will be adjusted later */
79168fd1 2097 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2098 cs->g = 1; /* 4kb granularity */
79168fd1 2099 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2100 cs->type = 0x0b; /* Read, Execute, Accessed */
2101 cs->s = 1;
2102 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2103 cs->p = 1;
2104 cs->d = 1;
99245b50 2105 cs->avl = 0;
e66bb2cc 2106
79168fd1
GN		 2107 set_desc_base(ss, 0); /* flat segment */
2108 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2109 ss->g = 1; /* 4kb granularity */
2110 ss->s = 1;
2111 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2112 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2113 ss->dpl = 0;
79168fd1 2114 ss->p = 1;
99245b50
GN		 2115 ss->l = 0;
2116 ss->avl = 0;
e66bb2cc
AP		 2117}
2118
1a18a69b
AK		 2119static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2120{
2121 u32 eax, ebx, ecx, edx;
2122
2123 eax = ecx = 0;
0017f93a
AK		 2124 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2125 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2126 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2127 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2128}
2129
c2226fc9
SB		 2130static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2131{
0225fb50 2132 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2133 u32 eax, ebx, ecx, edx;
2134
2135 /*
2136 * syscall should always be enabled in longmode - so only become
2137 * vendor specific (cpuid) if other modes are active...
2138 */
2139 if (ctxt->mode == X86EMUL_MODE_PROT64)
2140 return true;
2141
2142 eax = 0x00000000;
2143 ecx = 0x00000000;
0017f93a
AK		 2144 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2145 /*
2146 * Intel ("GenuineIntel")
2147 * remark: Intel CPUs only support "syscall" in 64bit
2148 * longmode. Also an 64bit guest with a
2149 * 32bit compat-app running will #UD !! While this
2150 * behaviour can be fixed (by emulating) into AMD
2151 * response - CPUs of AMD can't behave like Intel.
2152 */
2153 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2154 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2155 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2156 return false;
2157
2158 /* AMD ("AuthenticAMD") */
2159 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2160 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2161 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2162 return true;
2163
2164 /* AMD ("AMDisbetter!") */
2165 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2166 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2167 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2168 return true;
c2226fc9
SB		 2169
2170 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2171 return false;
2172}
2173
e01991e7 2174static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2175{
0225fb50 2176 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2177 struct desc_struct cs, ss;
e66bb2cc 2178 u64 msr_data;
79168fd1 2179 u16 cs_sel, ss_sel;
c2ad2bb3 2180 u64 efer = 0;
e66bb2cc
AP		 2181
2182 /* syscall is not available in real mode */
2e901c4c 2183 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2184 ctxt->mode == X86EMUL_MODE_VM86)
2185 return emulate_ud(ctxt);
e66bb2cc 2186
c2226fc9
SB		 2187 if (!(em_syscall_is_enabled(ctxt)))
2188 return emulate_ud(ctxt);
2189
c2ad2bb3 2190 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2191 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2192
c2226fc9
SB		 2193 if (!(efer & EFER_SCE))
2194 return emulate_ud(ctxt);
2195
717746e3 2196 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2197 msr_data >>= 32;
79168fd1
GN		 2198 cs_sel = (u16)(msr_data & 0xfffc);
2199 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2200
c2ad2bb3 2201 if (efer & EFER_LMA) {
79168fd1 2202 cs.d = 0;
e66bb2cc
AP		 2203 cs.l = 1;
2204 }
1aa36616
AK		 2205 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2206 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2207
dd856efa 2208 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2209 if (efer & EFER_LMA) {
e66bb2cc 2210#ifdef CONFIG_X86_64
dd856efa 2211 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2212
717746e3 2213 ops->get_msr(ctxt,
3fb1b5db
GN		 2214 ctxt->mode == X86EMUL_MODE_PROT64 ?
2215 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2216 ctxt->_eip = msr_data;
e66bb2cc 2217
717746e3 2218 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2219 ctxt->eflags &= ~(msr_data | EFLG_RF);
2220#endif
2221 } else {
2222 /* legacy mode */
717746e3 2223 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2224 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2225
2226 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2227 }
2228
e54cfa97 2229 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2230}
2231
e01991e7 2232static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2233{
0225fb50 2234 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2235 struct desc_struct cs, ss;
8c604352 2236 u64 msr_data;
79168fd1 2237 u16 cs_sel, ss_sel;
c2ad2bb3 2238 u64 efer = 0;
8c604352 2239
7b105ca2 2240 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2241 /* inject #GP if in real mode */
35d3d4a1
AK		 2242 if (ctxt->mode == X86EMUL_MODE_REAL)
2243 return emulate_gp(ctxt, 0);
8c604352 2244
1a18a69b
AK		 2245 /*
2246 * Not recognized on AMD in compat mode (but is recognized in legacy
2247 * mode).
2248 */
2249 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2250 && !vendor_intel(ctxt))
2251 return emulate_ud(ctxt);
2252
8c604352
AP		 2253 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2254 * Therefore, we inject an #UD.
2255 */
35d3d4a1
AK		 2256 if (ctxt->mode == X86EMUL_MODE_PROT64)
2257 return emulate_ud(ctxt);
8c604352 2258
7b105ca2 2259 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2260
717746e3 2261 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2262 switch (ctxt->mode) {
2263 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2264 if ((msr_data & 0xfffc) == 0x0)
2265 return emulate_gp(ctxt, 0);
8c604352
AP		 2266 break;
2267 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2268 if (msr_data == 0x0)
2269 return emulate_gp(ctxt, 0);
8c604352 2270 break;
9d1b39a9
GN		 2271 default:
2272 break;
8c604352
AP		 2273 }
2274
2275 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2276 cs_sel = (u16)msr_data;
2277 cs_sel &= ~SELECTOR_RPL_MASK;
2278 ss_sel = cs_sel + 8;
2279 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2280 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2281 cs.d = 0;
8c604352
AP		 2282 cs.l = 1;
2283 }
2284
1aa36616
AK		 2285 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2286 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2287
717746e3 2288 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2289 ctxt->_eip = msr_data;
8c604352 2290
717746e3 2291 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2292 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2293
e54cfa97 2294 return X86EMUL_CONTINUE;
8c604352
AP		 2295}
2296
e01991e7 2297static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2298{
0225fb50 2299 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2300 struct desc_struct cs, ss;
4668f050
AP		 2301 u64 msr_data;
2302 int usermode;
1249b96e 2303 u16 cs_sel = 0, ss_sel = 0;
4668f050 2304
a0044755
GN		 2305 /* inject #GP if in real mode or Virtual 8086 mode */
2306 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2307 ctxt->mode == X86EMUL_MODE_VM86)
2308 return emulate_gp(ctxt, 0);
4668f050 2309
7b105ca2 2310 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2311
9dac77fa 2312 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2313 usermode = X86EMUL_MODE_PROT64;
2314 else
2315 usermode = X86EMUL_MODE_PROT32;
2316
2317 cs.dpl = 3;
2318 ss.dpl = 3;
717746e3 2319 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2320 switch (usermode) {
2321 case X86EMUL_MODE_PROT32:
79168fd1 2322 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2323 if ((msr_data & 0xfffc) == 0x0)
2324 return emulate_gp(ctxt, 0);
79168fd1 2325 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2326 break;
2327 case X86EMUL_MODE_PROT64:
79168fd1 2328 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2329 if (msr_data == 0x0)
2330 return emulate_gp(ctxt, 0);
79168fd1
GN		 2331 ss_sel = cs_sel + 8;
2332 cs.d = 0;
4668f050
AP		 2333 cs.l = 1;
2334 break;
2335 }
79168fd1
GN		 2336 cs_sel |= SELECTOR_RPL_MASK;
2337 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2338
1aa36616
AK		 2339 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2340 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2341
dd856efa
AK		 2342 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2343 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
4668f050 2344
e54cfa97 2345 return X86EMUL_CONTINUE;
4668f050
AP		 2346}
2347
7b105ca2 2348static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2349{
2350 int iopl;
2351 if (ctxt->mode == X86EMUL_MODE_REAL)
2352 return false;
2353 if (ctxt->mode == X86EMUL_MODE_VM86)
2354 return true;
2355 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2356 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2357}
2358
2359static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2360 u16 port, u16 len)
2361{
0225fb50 2362 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2363 struct desc_struct tr_seg;
5601d05b 2364 u32 base3;
f850e2e6 2365 int r;
1aa36616 2366 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2367 unsigned mask = (1 << len) - 1;
5601d05b 2368 unsigned long base;
f850e2e6 2369
1aa36616 2370 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2371 if (!tr_seg.p)
f850e2e6 2372 return false;
79168fd1 2373 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2374 return false;
5601d05b
GN		 2375 base = get_desc_base(&tr_seg);
2376#ifdef CONFIG_X86_64
2377 base |= ((u64)base3) << 32;
2378#endif
0f65dd70 2379 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2380 if (r != X86EMUL_CONTINUE)
2381 return false;
79168fd1 2382 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2383 return false;
0f65dd70 2384 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2385 if (r != X86EMUL_CONTINUE)
2386 return false;
2387 if ((perm >> bit_idx) & mask)
2388 return false;
2389 return true;
2390}
2391
2392static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2393 u16 port, u16 len)
2394{
4fc40f07
GN		 2395 if (ctxt->perm_ok)
2396 return true;
2397
7b105ca2
TY		 2398 if (emulator_bad_iopl(ctxt))
2399 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2400 return false;
4fc40f07
GN		 2401
2402 ctxt->perm_ok = true;
2403
f850e2e6
GN		 2404 return true;
2405}
2406
38ba30ba 2407static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2408 struct tss_segment_16 *tss)
2409{
9dac77fa 2410 tss->ip = ctxt->_eip;
38ba30ba 2411 tss->flag = ctxt->eflags;
dd856efa
AK		 2412 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2413 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2414 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2415 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2416 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2417 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2418 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2419 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2420
1aa36616
AK		 2421 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2422 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2423 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2424 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2425 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2426}
2427
2428static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2429 struct tss_segment_16 *tss)
2430{
38ba30ba 2431 int ret;
2356aaeb 2432 u8 cpl;
38ba30ba 2433
9dac77fa 2434 ctxt->_eip = tss->ip;
38ba30ba 2435 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2436 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2437 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2438 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2439 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2440 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2441 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2442 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2443 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2444
2445 /*
2446 * SDM says that segment selectors are loaded before segment
2447 * descriptors
2448 */
1aa36616
AK		 2449 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2450 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2451 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2452 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2453 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2454
2356aaeb
PB		 2455 cpl = tss->cs & 3;
2456
38ba30ba 2457 /*
fc058680 2458 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2459 * it is handled in a context of new task
2460 */
5045b468 2461 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2462 if (ret != X86EMUL_CONTINUE)
2463 return ret;
5045b468 2464 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2465 if (ret != X86EMUL_CONTINUE)
2466 return ret;
5045b468 2467 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2468 if (ret != X86EMUL_CONTINUE)
2469 return ret;
5045b468 2470 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2471 if (ret != X86EMUL_CONTINUE)
2472 return ret;
5045b468 2473 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2474 if (ret != X86EMUL_CONTINUE)
2475 return ret;
2476
2477 return X86EMUL_CONTINUE;
2478}
2479
2480static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2481 u16 tss_selector, u16 old_tss_sel,
2482 ulong old_tss_base, struct desc_struct *new_desc)
2483{
0225fb50 2484 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2485 struct tss_segment_16 tss_seg;
2486 int ret;
bcc55cba 2487 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2488
0f65dd70 2489 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2490 &ctxt->exception);
db297e3d 2491 if (ret != X86EMUL_CONTINUE)
38ba30ba 2492 /* FIXME: need to provide precise fault address */
38ba30ba 2493 return ret;
38ba30ba 2494
7b105ca2 2495 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2496
0f65dd70 2497 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2498 &ctxt->exception);
db297e3d 2499 if (ret != X86EMUL_CONTINUE)
38ba30ba 2500 /* FIXME: need to provide precise fault address */
38ba30ba 2501 return ret;
38ba30ba 2502
0f65dd70 2503 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2504 &ctxt->exception);
db297e3d 2505 if (ret != X86EMUL_CONTINUE)
38ba30ba 2506 /* FIXME: need to provide precise fault address */
38ba30ba 2507 return ret;
38ba30ba
GN		 2508
2509 if (old_tss_sel != 0xffff) {
2510 tss_seg.prev_task_link = old_tss_sel;
2511
0f65dd70 2512 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2513 &tss_seg.prev_task_link,
2514 sizeof tss_seg.prev_task_link,
0f65dd70 2515 &ctxt->exception);
db297e3d 2516 if (ret != X86EMUL_CONTINUE)
38ba30ba 2517 /* FIXME: need to provide precise fault address */
38ba30ba 2518 return ret;
38ba30ba
GN		 2519 }
2520
7b105ca2 2521 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2522}
2523
2524static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2525 struct tss_segment_32 *tss)
2526{
5c7411e2 2527 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2528 tss->eip = ctxt->_eip;
38ba30ba 2529 tss->eflags = ctxt->eflags;
dd856efa
AK		 2530 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2531 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2532 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2533 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2534 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2535 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2536 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2537 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2538
1aa36616
AK		 2539 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2540 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2541 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2542 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2543 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2544 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2545}
2546
2547static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2548 struct tss_segment_32 *tss)
2549{
38ba30ba 2550 int ret;
2356aaeb 2551 u8 cpl;
38ba30ba 2552
7b105ca2 2553 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2554 return emulate_gp(ctxt, 0);
9dac77fa 2555 ctxt->_eip = tss->eip;
38ba30ba 2556 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2557
2558 /* General purpose registers */
dd856efa
AK		 2559 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2560 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2561 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2562 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2563 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2564 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2565 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2566 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2567
2568 /*
2569 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2570 * descriptors. This is important because CPL checks will
2571 * use CS.RPL.
38ba30ba 2572 */
1aa36616
AK		 2573 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2574 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2575 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2576 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2577 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2578 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2579 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2580
4cee4798
KW		 2581 /*
2582 * If we're switching between Protected Mode and VM86, we need to make
2583 * sure to update the mode before loading the segment descriptors so
2584 * that the selectors are interpreted correctly.
4cee4798 2585 */
2356aaeb 2586 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2587 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2588 cpl = 3;
2589 } else {
4cee4798 2590 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2591 cpl = tss->cs & 3;
2592 }
4cee4798 2593
38ba30ba
GN		 2594 /*
2595 * Now load segment descriptors. If fault happenes at this stage
2596 * it is handled in a context of new task
2597 */
5045b468 2598 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
38ba30ba
GN		 2599 if (ret != X86EMUL_CONTINUE)
2600 return ret;
5045b468 2601 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
38ba30ba
GN		 2602 if (ret != X86EMUL_CONTINUE)
2603 return ret;
5045b468 2604 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
38ba30ba
GN		 2605 if (ret != X86EMUL_CONTINUE)
2606 return ret;
5045b468 2607 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
38ba30ba
GN		 2608 if (ret != X86EMUL_CONTINUE)
2609 return ret;
5045b468 2610 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
38ba30ba
GN		 2611 if (ret != X86EMUL_CONTINUE)
2612 return ret;
5045b468 2613 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
38ba30ba
GN		 2614 if (ret != X86EMUL_CONTINUE)
2615 return ret;
5045b468 2616 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
38ba30ba
GN		 2617 if (ret != X86EMUL_CONTINUE)
2618 return ret;
2619
2620 return X86EMUL_CONTINUE;
2621}
2622
2623static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2624 u16 tss_selector, u16 old_tss_sel,
2625 ulong old_tss_base, struct desc_struct *new_desc)
2626{
0225fb50 2627 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2628 struct tss_segment_32 tss_seg;
2629 int ret;
bcc55cba 2630 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2631 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2632 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2633
0f65dd70 2634 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2635 &ctxt->exception);
db297e3d 2636 if (ret != X86EMUL_CONTINUE)
38ba30ba 2637 /* FIXME: need to provide precise fault address */
38ba30ba 2638 return ret;
38ba30ba 2639
7b105ca2 2640 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2641
5c7411e2
NA		 2642 /* Only GP registers and segment selectors are saved */
2643 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2644 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2645 if (ret != X86EMUL_CONTINUE)
38ba30ba 2646 /* FIXME: need to provide precise fault address */
38ba30ba 2647 return ret;
38ba30ba 2648
0f65dd70 2649 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2650 &ctxt->exception);
db297e3d 2651 if (ret != X86EMUL_CONTINUE)
38ba30ba 2652 /* FIXME: need to provide precise fault address */
38ba30ba 2653 return ret;
38ba30ba
GN		 2654
2655 if (old_tss_sel != 0xffff) {
2656 tss_seg.prev_task_link = old_tss_sel;
2657
0f65dd70 2658 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2659 &tss_seg.prev_task_link,
2660 sizeof tss_seg.prev_task_link,
0f65dd70 2661 &ctxt->exception);
db297e3d 2662 if (ret != X86EMUL_CONTINUE)
38ba30ba 2663 /* FIXME: need to provide precise fault address */
38ba30ba 2664 return ret;
38ba30ba
GN		 2665 }
2666
7b105ca2 2667 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2668}
2669
2670static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2671 u16 tss_selector, int idt_index, int reason,
e269fb21 2672 bool has_error_code, u32 error_code)
38ba30ba 2673{
0225fb50 2674 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2675 struct desc_struct curr_tss_desc, next_tss_desc;
2676 int ret;
1aa36616 2677 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2678 ulong old_tss_base =
4bff1e86 2679 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2680 u32 desc_limit;
e919464b 2681 ulong desc_addr;
38ba30ba
GN		 2682
2683 /* FIXME: old_tss_base == ~0 ? */
2684
e919464b 2685 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2686 if (ret != X86EMUL_CONTINUE)
2687 return ret;
e919464b 2688 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2689 if (ret != X86EMUL_CONTINUE)
2690 return ret;
2691
2692 /* FIXME: check that next_tss_desc is tss */
2693
7f3d35fd
KW		 2694 /*
2695 * Check privileges. The three cases are task switch caused by...
2696 *
2697 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2698 * 2. Exception/IRQ/iret: No check is performed
fc058680 2699 * 3. jmp/call to TSS: Check against DPL of the TSS
7f3d35fd
KW		 2700 */
2701 if (reason == TASK_SWITCH_GATE) {
2702 if (idt_index != -1) {
2703 /* Software interrupts */
2704 struct desc_struct task_gate_desc;
2705 int dpl;
2706
2707 ret = read_interrupt_descriptor(ctxt, idt_index,
2708 &task_gate_desc);
2709 if (ret != X86EMUL_CONTINUE)
2710 return ret;
2711
2712 dpl = task_gate_desc.dpl;
2713 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2714 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2715 }
2716 } else if (reason != TASK_SWITCH_IRET) {
2717 int dpl = next_tss_desc.dpl;
2718 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2719 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2720 }
2721
7f3d35fd 2722
ceffb459
GN		 2723 desc_limit = desc_limit_scaled(&next_tss_desc);
2724 if (!next_tss_desc.p ||
2725 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2726 desc_limit < 0x2b)) {
54b8486f 2727 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2728 return X86EMUL_PROPAGATE_FAULT;
2729 }
2730
2731 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2732 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2733 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2734 }
2735
2736 if (reason == TASK_SWITCH_IRET)
2737 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2738
2739 /* set back link to prev task only if NT bit is set in eflags
fc058680 2740 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2741 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2742 old_tss_sel = 0xffff;
2743
2744 if (next_tss_desc.type & 8)
7b105ca2 2745 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2746 old_tss_base, &next_tss_desc);
2747 else
7b105ca2 2748 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2749 old_tss_base, &next_tss_desc);
0760d448
JK		 2750 if (ret != X86EMUL_CONTINUE)
2751 return ret;
38ba30ba
GN		 2752
2753 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2754 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2755
2756 if (reason != TASK_SWITCH_IRET) {
2757 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2758 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2759 }
2760
717746e3 2761 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2762 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2763
e269fb21 2764 if (has_error_code) {
9dac77fa
AK		 2765 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2766 ctxt->lock_prefix = 0;
2767 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2768 ret = em_push(ctxt);
e269fb21
JK		 2769 }
2770
38ba30ba
GN		 2771 return ret;
2772}
2773
2774int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2775 u16 tss_selector, int idt_index, int reason,
e269fb21 2776 bool has_error_code, u32 error_code)
38ba30ba 2777{
38ba30ba
GN		 2778 int rc;
2779
dd856efa 2780 invalidate_registers(ctxt);
9dac77fa
AK		 2781 ctxt->_eip = ctxt->eip;
2782 ctxt->dst.type = OP_NONE;
38ba30ba 2783
7f3d35fd 2784 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2785 has_error_code, error_code);
38ba30ba 2786
dd856efa 2787 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2788 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2789 writeback_registers(ctxt);
2790 }
38ba30ba 2791
a0c0ab2f 2792 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2793}
2794
f3bd64c6
GN		 2795static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2796 struct operand *op)
a682e354 2797{
b3356bf0 2798 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2799
dd856efa
AK		 2800 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2801 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
a682e354
GN		 2802}
2803
7af04fc0
AK		 2804static int em_das(struct x86_emulate_ctxt *ctxt)
2805{
7af04fc0
AK		 2806 u8 al, old_al;
2807 bool af, cf, old_cf;
2808
2809 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2810 al = ctxt->dst.val;
7af04fc0
AK		 2811
2812 old_al = al;
2813 old_cf = cf;
2814 cf = false;
2815 af = ctxt->eflags & X86_EFLAGS_AF;
2816 if ((al & 0x0f) > 9 || af) {
2817 al -= 6;
2818 cf = old_cf | (al >= 250);
2819 af = true;
2820 } else {
2821 af = false;
2822 }
2823 if (old_al > 0x99 || old_cf) {
2824 al -= 0x60;
2825 cf = true;
2826 }
2827
9dac77fa 2828 ctxt->dst.val = al;
7af04fc0 2829 /* Set PF, ZF, SF */
9dac77fa
AK		 2830 ctxt->src.type = OP_IMM;
2831 ctxt->src.val = 0;
2832 ctxt->src.bytes = 1;
158de57f 2833 fastop(ctxt, em_or);
7af04fc0
AK		 2834 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2835 if (cf)
2836 ctxt->eflags |= X86_EFLAGS_CF;
2837 if (af)
2838 ctxt->eflags |= X86_EFLAGS_AF;
2839 return X86EMUL_CONTINUE;
2840}
2841
a035d5c6
PB		 2842static int em_aam(struct x86_emulate_ctxt *ctxt)
2843{
2844 u8 al, ah;
2845
2846 if (ctxt->src.val == 0)
2847 return emulate_de(ctxt);
2848
2849 al = ctxt->dst.val & 0xff;
2850 ah = al / ctxt->src.val;
2851 al %= ctxt->src.val;
2852
2853 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2854
2855 /* Set PF, ZF, SF */
2856 ctxt->src.type = OP_IMM;
2857 ctxt->src.val = 0;
2858 ctxt->src.bytes = 1;
2859 fastop(ctxt, em_or);
2860
2861 return X86EMUL_CONTINUE;
2862}
2863
7f662273
GN		 2864static int em_aad(struct x86_emulate_ctxt *ctxt)
2865{
2866 u8 al = ctxt->dst.val & 0xff;
2867 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2868
2869 al = (al + (ah * ctxt->src.val)) & 0xff;
2870
2871 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
2872
f583c29b
GN		 2873 /* Set PF, ZF, SF */
2874 ctxt->src.type = OP_IMM;
2875 ctxt->src.val = 0;
2876 ctxt->src.bytes = 1;
2877 fastop(ctxt, em_or);
7f662273
GN		 2878
2879 return X86EMUL_CONTINUE;
2880}
2881
d4ddafcd
TY		 2882static int em_call(struct x86_emulate_ctxt *ctxt)
2883{
2884 long rel = ctxt->src.val;
2885
2886 ctxt->src.val = (unsigned long)ctxt->_eip;
2887 jmp_rel(ctxt, rel);
2888 return em_push(ctxt);
2889}
2890
0ef753b8
AK		 2891static int em_call_far(struct x86_emulate_ctxt *ctxt)
2892{
0ef753b8
AK		 2893 u16 sel, old_cs;
2894 ulong old_eip;
2895 int rc;
2896
1aa36616 2897 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2898 old_eip = ctxt->_eip;
0ef753b8 2899
9dac77fa 2900 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2901 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2902 return X86EMUL_CONTINUE;
2903
9dac77fa
AK		 2904 ctxt->_eip = 0;
2905 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2906
9dac77fa 2907 ctxt->src.val = old_cs;
4487b3b4 2908 rc = em_push(ctxt);
0ef753b8
AK		 2909 if (rc != X86EMUL_CONTINUE)
2910 return rc;
2911
9dac77fa 2912 ctxt->src.val = old_eip;
4487b3b4 2913 return em_push(ctxt);
0ef753b8
AK		 2914}
2915
40ece7c7
AK		 2916static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2917{
40ece7c7
AK		 2918 int rc;
2919
9dac77fa
AK		 2920 ctxt->dst.type = OP_REG;
2921 ctxt->dst.addr.reg = &ctxt->_eip;
2922 ctxt->dst.bytes = ctxt->op_bytes;
2923 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2924 if (rc != X86EMUL_CONTINUE)
2925 return rc;
5ad105e5 2926 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 2927 return X86EMUL_CONTINUE;
2928}
2929
e4f973ae
TY		 2930static int em_xchg(struct x86_emulate_ctxt *ctxt)
2931{
e4f973ae 2932 /* Write back the register source. */
9dac77fa
AK		 2933 ctxt->src.val = ctxt->dst.val;
2934 write_register_operand(&ctxt->src);
e4f973ae
TY		 2935
2936 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2937 ctxt->dst.val = ctxt->src.orig_val;
2938 ctxt->lock_prefix = 1;
e4f973ae
TY		 2939 return X86EMUL_CONTINUE;
2940}
2941
5c82aa29
AK		 2942static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2943{
9dac77fa 2944 ctxt->dst.val = ctxt->src2.val;
4d758349 2945 return fastop(ctxt, em_imul);
5c82aa29
AK		 2946}
2947
61429142
AK		 2948static int em_cwd(struct x86_emulate_ctxt *ctxt)
2949{
9dac77fa
AK		 2950 ctxt->dst.type = OP_REG;
2951 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 2952 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 2953 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2954
2955 return X86EMUL_CONTINUE;
2956}
2957
48bb5d3c
AK		 2958static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2959{
48bb5d3c
AK		 2960 u64 tsc = 0;
2961
717746e3 2962 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 2963 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
2964 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 2965 return X86EMUL_CONTINUE;
2966}
2967
222d21aa
AK		 2968static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2969{
2970 u64 pmc;
2971
dd856efa 2972 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 2973 return emulate_gp(ctxt, 0);
dd856efa
AK		 2974 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
2975 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 2976 return X86EMUL_CONTINUE;
2977}
2978
b9eac5f4
AK		 2979static int em_mov(struct x86_emulate_ctxt *ctxt)
2980{
49597d81 2981 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2982 return X86EMUL_CONTINUE;
2983}
2984
84cffe49
BP		 2985#define FFL(x) bit(X86_FEATURE_##x)
2986
2987static int em_movbe(struct x86_emulate_ctxt *ctxt)
2988{
2989 u32 ebx, ecx, edx, eax = 1;
2990 u16 tmp;
2991
2992 /*
2993 * Check MOVBE is set in the guest-visible CPUID leaf.
2994 */
2995 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2996 if (!(ecx & FFL(MOVBE)))
2997 return emulate_ud(ctxt);
2998
2999 switch (ctxt->op_bytes) {
3000 case 2:
3001 /*
3002 * From MOVBE definition: "...When the operand size is 16 bits,
3003 * the upper word of the destination register remains unchanged
3004 * ..."
3005 *
3006 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3007 * rules so we have to do the operation almost per hand.
3008 */
3009 tmp = (u16)ctxt->src.val;
3010 ctxt->dst.val &= ~0xffffUL;
3011 ctxt->dst.val |= (unsigned long)swab16(tmp);
3012 break;
3013 case 4:
3014 ctxt->dst.val = swab32((u32)ctxt->src.val);
3015 break;
3016 case 8:
3017 ctxt->dst.val = swab64(ctxt->src.val);
3018 break;
3019 default:
3020 return X86EMUL_PROPAGATE_FAULT;
3021 }
3022 return X86EMUL_CONTINUE;
3023}
3024
bc00f8d2
TY		 3025static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3026{
3027 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3028 return emulate_gp(ctxt, 0);
3029
3030 /* Disable writeback. */
3031 ctxt->dst.type = OP_NONE;
3032 return X86EMUL_CONTINUE;
3033}
3034
3035static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3036{
3037 unsigned long val;
3038
3039 if (ctxt->mode == X86EMUL_MODE_PROT64)
3040 val = ctxt->src.val & ~0ULL;
3041 else
3042 val = ctxt->src.val & ~0U;
3043
3044 /* #UD condition is already handled. */
3045 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3046 return emulate_gp(ctxt, 0);
3047
3048 /* Disable writeback. */
3049 ctxt->dst.type = OP_NONE;
3050 return X86EMUL_CONTINUE;
3051}
3052
e1e210b0
TY		 3053static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3054{
3055 u64 msr_data;
3056
dd856efa
AK		 3057 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3058 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3059 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3060 return emulate_gp(ctxt, 0);
3061
3062 return X86EMUL_CONTINUE;
3063}
3064
3065static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3066{
3067 u64 msr_data;
3068
dd856efa 3069 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3070 return emulate_gp(ctxt, 0);
3071
dd856efa
AK		 3072 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3073 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3074 return X86EMUL_CONTINUE;
3075}
3076
1bd5f469
TY		 3077static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3078{
9dac77fa 3079 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3080 return emulate_ud(ctxt);
3081
9dac77fa 3082 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3083 return X86EMUL_CONTINUE;
3084}
3085
3086static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3087{
9dac77fa 3088 u16 sel = ctxt->src.val;
1bd5f469 3089
9dac77fa 3090 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3091 return emulate_ud(ctxt);
3092
9dac77fa 3093 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3094 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3095
3096 /* Disable writeback. */
9dac77fa
AK		 3097 ctxt->dst.type = OP_NONE;
3098 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3099}
3100
a14e579f
AK		 3101static int em_lldt(struct x86_emulate_ctxt *ctxt)
3102{
3103 u16 sel = ctxt->src.val;
3104
3105 /* Disable writeback. */
3106 ctxt->dst.type = OP_NONE;
3107 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3108}
3109
80890006
AK		 3110static int em_ltr(struct x86_emulate_ctxt *ctxt)
3111{
3112 u16 sel = ctxt->src.val;
3113
3114 /* Disable writeback. */
3115 ctxt->dst.type = OP_NONE;
3116 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3117}
3118
38503911
AK		 3119static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3120{
9fa088f4
AK		 3121 int rc;
3122 ulong linear;
3123
9dac77fa 3124 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3125 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3126 ctxt->ops->invlpg(ctxt, linear);
38503911 3127 /* Disable writeback. */
9dac77fa 3128 ctxt->dst.type = OP_NONE;
38503911
AK		 3129 return X86EMUL_CONTINUE;
3130}
3131
2d04a05b
AK		 3132static int em_clts(struct x86_emulate_ctxt *ctxt)
3133{
3134 ulong cr0;
3135
3136 cr0 = ctxt->ops->get_cr(ctxt, 0);
3137 cr0 &= ~X86_CR0_TS;
3138 ctxt->ops->set_cr(ctxt, 0, cr0);
3139 return X86EMUL_CONTINUE;
3140}
3141
26d05cc7
AK		 3142static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3143{
26d05cc7
AK		 3144 int rc;
3145
9dac77fa 3146 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3147 return X86EMUL_UNHANDLEABLE;
3148
3149 rc = ctxt->ops->fix_hypercall(ctxt);
3150 if (rc != X86EMUL_CONTINUE)
3151 return rc;
3152
3153 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3154 ctxt->_eip = ctxt->eip;
26d05cc7 3155 /* Disable writeback. */
9dac77fa 3156 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3157 return X86EMUL_CONTINUE;
3158}
3159
96051572
AK		 3160static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3161 void (*get)(struct x86_emulate_ctxt *ctxt,
3162 struct desc_ptr *ptr))
3163{
3164 struct desc_ptr desc_ptr;
3165
3166 if (ctxt->mode == X86EMUL_MODE_PROT64)
3167 ctxt->op_bytes = 8;
3168 get(ctxt, &desc_ptr);
3169 if (ctxt->op_bytes == 2) {
3170 ctxt->op_bytes = 4;
3171 desc_ptr.address &= 0x00ffffff;
3172 }
3173 /* Disable writeback. */
3174 ctxt->dst.type = OP_NONE;
3175 return segmented_write(ctxt, ctxt->dst.addr.mem,
3176 &desc_ptr, 2 + ctxt->op_bytes);
3177}
3178
3179static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3180{
3181 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3182}
3183
3184static int em_sidt(struct x86_emulate_ctxt *ctxt)
3185{
3186 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3187}
3188
26d05cc7
AK		 3189static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3190{
26d05cc7
AK		 3191 struct desc_ptr desc_ptr;
3192 int rc;
3193
510425ff
AK		 3194 if (ctxt->mode == X86EMUL_MODE_PROT64)
3195 ctxt->op_bytes = 8;
9dac77fa 3196 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3197 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3198 ctxt->op_bytes);
26d05cc7
AK		 3199 if (rc != X86EMUL_CONTINUE)
3200 return rc;
3201 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3202 /* Disable writeback. */
9dac77fa 3203 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3204 return X86EMUL_CONTINUE;
3205}
3206
5ef39c71 3207static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3208{
26d05cc7
AK		 3209 int rc;
3210
5ef39c71
AK		 3211 rc = ctxt->ops->fix_hypercall(ctxt);
3212
26d05cc7 3213 /* Disable writeback. */
9dac77fa 3214 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3215 return rc;
3216}
3217
3218static int em_lidt(struct x86_emulate_ctxt *ctxt)
3219{
26d05cc7
AK		 3220 struct desc_ptr desc_ptr;
3221 int rc;
3222
510425ff
AK		 3223 if (ctxt->mode == X86EMUL_MODE_PROT64)
3224 ctxt->op_bytes = 8;
9dac77fa 3225 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3226 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3227 ctxt->op_bytes);
26d05cc7
AK		 3228 if (rc != X86EMUL_CONTINUE)
3229 return rc;
3230 ctxt->ops->set_idt(ctxt, &desc_ptr);
3231 /* Disable writeback. */
9dac77fa 3232 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3233 return X86EMUL_CONTINUE;
3234}
3235
3236static int em_smsw(struct x86_emulate_ctxt *ctxt)
3237{
9dac77fa
AK		 3238 ctxt->dst.bytes = 2;
3239 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3240 return X86EMUL_CONTINUE;
3241}
3242
3243static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3244{
26d05cc7 3245 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3246 | (ctxt->src.val & 0x0f));
3247 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3248 return X86EMUL_CONTINUE;
3249}
3250
d06e03ad
TY		 3251static int em_loop(struct x86_emulate_ctxt *ctxt)
3252{
dd856efa
AK		 3253 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3254 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa
AK		 3255 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3256 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3257
3258 return X86EMUL_CONTINUE;
3259}
3260
3261static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3262{
dd856efa 3263 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
9dac77fa 3264 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3265
3266 return X86EMUL_CONTINUE;
3267}
3268
d7841a4b
TY		 3269static int em_in(struct x86_emulate_ctxt *ctxt)
3270{
3271 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3272 &ctxt->dst.val))
3273 return X86EMUL_IO_NEEDED;
3274
3275 return X86EMUL_CONTINUE;
3276}
3277
3278static int em_out(struct x86_emulate_ctxt *ctxt)
3279{
3280 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3281 &ctxt->src.val, 1);
3282 /* Disable writeback. */
3283 ctxt->dst.type = OP_NONE;
3284 return X86EMUL_CONTINUE;
3285}
3286
f411e6cd
TY		 3287static int em_cli(struct x86_emulate_ctxt *ctxt)
3288{
3289 if (emulator_bad_iopl(ctxt))
3290 return emulate_gp(ctxt, 0);
3291
3292 ctxt->eflags &= ~X86_EFLAGS_IF;
3293 return X86EMUL_CONTINUE;
3294}
3295
3296static int em_sti(struct x86_emulate_ctxt *ctxt)
3297{
3298 if (emulator_bad_iopl(ctxt))
3299 return emulate_gp(ctxt, 0);
3300
3301 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3302 ctxt->eflags |= X86_EFLAGS_IF;
3303 return X86EMUL_CONTINUE;
3304}
3305
6d6eede4
AK		 3306static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3307{
3308 u32 eax, ebx, ecx, edx;
3309
dd856efa
AK		 3310 eax = reg_read(ctxt, VCPU_REGS_RAX);
3311 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3312 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3313 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3314 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3315 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3316 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3317 return X86EMUL_CONTINUE;
3318}
3319
98f73630
PB		 3320static int em_sahf(struct x86_emulate_ctxt *ctxt)
3321{
3322 u32 flags;
3323
3324 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3325 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3326
3327 ctxt->eflags &= ~0xffUL;
3328 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3329 return X86EMUL_CONTINUE;
3330}
3331
2dd7caa0
AK		 3332static int em_lahf(struct x86_emulate_ctxt *ctxt)
3333{
dd856efa
AK		 3334 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3335 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3336 return X86EMUL_CONTINUE;
3337}
3338
9299836e
AK		 3339static int em_bswap(struct x86_emulate_ctxt *ctxt)
3340{
3341 switch (ctxt->op_bytes) {
3342#ifdef CONFIG_X86_64
3343 case 8:
3344 asm("bswap %0" : "+r"(ctxt->dst.val));
3345 break;
3346#endif
3347 default:
3348 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3349 break;
3350 }
3351 return X86EMUL_CONTINUE;
3352}
3353
cfec82cb
JR		 3354static bool valid_cr(int nr)
3355{
3356 switch (nr) {
3357 case 0:
3358 case 2 ... 4:
3359 case 8:
3360 return true;
3361 default:
3362 return false;
3363 }
3364}
3365
3366static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3367{
9dac77fa 3368 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3369 return emulate_ud(ctxt);
3370
3371 return X86EMUL_CONTINUE;
3372}
3373
3374static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3375{
9dac77fa
AK		 3376 u64 new_val = ctxt->src.val64;
3377 int cr = ctxt->modrm_reg;
c2ad2bb3 3378 u64 efer = 0;
cfec82cb
JR		 3379
3380 static u64 cr_reserved_bits[] = {
3381 0xffffffff00000000ULL,
3382 0, 0, 0, /* CR3 checked later */
3383 CR4_RESERVED_BITS,
3384 0, 0, 0,
3385 CR8_RESERVED_BITS,
3386 };
3387
3388 if (!valid_cr(cr))
3389 return emulate_ud(ctxt);
3390
3391 if (new_val & cr_reserved_bits[cr])
3392 return emulate_gp(ctxt, 0);
3393
3394 switch (cr) {
3395 case 0: {
c2ad2bb3 3396 u64 cr4;
cfec82cb
JR		 3397 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3398 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3399 return emulate_gp(ctxt, 0);
3400
717746e3
AK		 3401 cr4 = ctxt->ops->get_cr(ctxt, 4);
3402 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3403
3404 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3405 !(cr4 & X86_CR4_PAE))
3406 return emulate_gp(ctxt, 0);
3407
3408 break;
3409 }
3410 case 3: {
3411 u64 rsvd = 0;
3412
c2ad2bb3
AK		 3413 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3414 if (efer & EFER_LMA)
cfec82cb 3415 rsvd = CR3_L_MODE_RESERVED_BITS;
cfec82cb
JR		 3416
3417 if (new_val & rsvd)
3418 return emulate_gp(ctxt, 0);
3419
3420 break;
3421 }
3422 case 4: {
717746e3 3423 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3424
3425 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3426 return emulate_gp(ctxt, 0);
3427
3428 break;
3429 }
3430 }
3431
3432 return X86EMUL_CONTINUE;
3433}
3434
3b88e41a
JR		 3435static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3436{
3437 unsigned long dr7;
3438
717746e3 3439 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3440
3441 /* Check if DR7.Global_Enable is set */
3442 return dr7 & (1 << 13);
3443}
3444
3445static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3446{
9dac77fa 3447 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3448 u64 cr4;
3449
3450 if (dr > 7)
3451 return emulate_ud(ctxt);
3452
717746e3 3453 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3454 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3455 return emulate_ud(ctxt);
3456
3457 if (check_dr7_gd(ctxt))
3458 return emulate_db(ctxt);
3459
3460 return X86EMUL_CONTINUE;
3461}
3462
3463static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3464{
9dac77fa
AK		 3465 u64 new_val = ctxt->src.val64;
3466 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3467
3468 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3469 return emulate_gp(ctxt, 0);
3470
3471 return check_dr_read(ctxt);
3472}
3473
01de8b09
JR		 3474static int check_svme(struct x86_emulate_ctxt *ctxt)
3475{
3476 u64 efer;
3477
717746e3 3478 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3479
3480 if (!(efer & EFER_SVME))
3481 return emulate_ud(ctxt);
3482
3483 return X86EMUL_CONTINUE;
3484}
3485
3486static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3487{
dd856efa 3488 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3489
3490 /* Valid physical address? */
d4224449 3491 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3492 return emulate_gp(ctxt, 0);
3493
3494 return check_svme(ctxt);
3495}
3496
d7eb8203
JR		 3497static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3498{
717746e3 3499 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3500
717746e3 3501 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3502 return emulate_ud(ctxt);
3503
3504 return X86EMUL_CONTINUE;
3505}
3506
8061252e
JR		 3507static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3508{
717746e3 3509 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3510 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3511
717746e3 3512 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3513 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3514 return emulate_gp(ctxt, 0);
3515
3516 return X86EMUL_CONTINUE;
3517}
3518
f6511935
JR		 3519static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3520{
9dac77fa
AK		 3521 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3522 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3523 return emulate_gp(ctxt, 0);
3524
3525 return X86EMUL_CONTINUE;
3526}
3527
3528static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3529{
9dac77fa
AK		 3530 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3531 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3532 return emulate_gp(ctxt, 0);
3533
3534 return X86EMUL_CONTINUE;
3535}
3536
73fba5f4 3537#define D(_y) { .flags = (_y) }
c4f035c6 3538#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3539#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3540 .check_perm = (_p) }
0b789eee 3541#define N D(NotImpl)
01de8b09 3542#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3543#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3544#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
045a282c 3545#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3546#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3547#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6
AK		 3548#define II(_f, _e, _i) \
3549 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3550#define IIP(_f, _e, _i, _p) \
3551 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3552 .check_perm = (_p) }
aa97bb48 3553#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3554
8d8f4e9f 3555#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3556#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3557#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3558#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3559#define I2bvIP(_f, _e, _i, _p) \
3560 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3561
fb864fbc
AK		 3562#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3563 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3564 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3565
fd0a0d82 3566static const struct opcode group7_rm1[] = {
1c2545be
TY		 3567 DI(SrcNone | Priv, monitor),
3568 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3569 N, N, N, N, N, N,
3570};
3571
fd0a0d82 3572static const struct opcode group7_rm3[] = {
1c2545be 3573 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3574 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3575 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3576 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3577 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3578 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3579 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3580 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3581};
6230f7fc 3582
fd0a0d82 3583static const struct opcode group7_rm7[] = {
d7eb8203 3584 N,
1c2545be 3585 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3586 N, N, N, N, N, N,
3587};
d67fc27a 3588
fd0a0d82 3589static const struct opcode group1[] = {
fb864fbc
AK		 3590 F(Lock, em_add),
3591 F(Lock | PageTable, em_or),
3592 F(Lock, em_adc),
3593 F(Lock, em_sbb),
3594 F(Lock | PageTable, em_and),
3595 F(Lock, em_sub),
3596 F(Lock, em_xor),
3597 F(NoWrite, em_cmp),
73fba5f4
AK		 3598};
3599
fd0a0d82 3600static const struct opcode group1A[] = {
1c2545be 3601 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3602};
3603
007a3b54
AK		 3604static const struct opcode group2[] = {
3605 F(DstMem | ModRM, em_rol),
3606 F(DstMem | ModRM, em_ror),
3607 F(DstMem | ModRM, em_rcl),
3608 F(DstMem | ModRM, em_rcr),
3609 F(DstMem | ModRM, em_shl),
3610 F(DstMem | ModRM, em_shr),
3611 F(DstMem | ModRM, em_shl),
3612 F(DstMem | ModRM, em_sar),
3613};
3614
fd0a0d82 3615static const struct opcode group3[] = {
fb864fbc
AK		 3616 F(DstMem | SrcImm | NoWrite, em_test),
3617 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3618 F(DstMem | SrcNone | Lock, em_not),
3619 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3620 F(DstXacc | Src2Mem, em_mul_ex),
3621 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3622 F(DstXacc | Src2Mem, em_div_ex),
3623 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3624};
3625
fd0a0d82 3626static const struct opcode group4[] = {
95413dc4
AK		 3627 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3628 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3629 N, N, N, N, N, N,
3630};
3631
fd0a0d82 3632static const struct opcode group5[] = {
95413dc4
AK		 3633 F(DstMem | SrcNone | Lock, em_inc),
3634 F(DstMem | SrcNone | Lock, em_dec),
1c2545be
TY		 3635 I(SrcMem | Stack, em_grp45),
3636 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3637 I(SrcMem | Stack, em_grp45),
3638 I(SrcMemFAddr | ImplicitOps, em_grp45),
188424ba 3639 I(SrcMem | Stack, em_grp45), D(Undefined),
73fba5f4
AK		 3640};
3641
fd0a0d82 3642static const struct opcode group6[] = {
1c2545be
TY		 3643 DI(Prot, sldt),
3644 DI(Prot, str),
a14e579f 3645 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3646 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3647 N, N, N, N,
3648};
3649
fd0a0d82 3650static const struct group_dual group7 = { {
606b1c3e
NA		 3651 II(Mov | DstMem, em_sgdt, sgdt),
3652 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3653 II(SrcMem | Priv, em_lgdt, lgdt),
3654 II(SrcMem | Priv, em_lidt, lidt),
3655 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3656 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3657 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3658}, {
b51e974f 3659 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
5ef39c71 3660 EXT(0, group7_rm1),
01de8b09 3661 N, EXT(0, group7_rm3),
1c2545be
TY		 3662 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3663 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3664 EXT(0, group7_rm7),
73fba5f4
AK		 3665} };
3666
fd0a0d82 3667static const struct opcode group8[] = {
73fba5f4 3668 N, N, N, N,
11c363ba
AK		 3669 F(DstMem | SrcImmByte | NoWrite, em_bt),
3670 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3671 F(DstMem | SrcImmByte | Lock, em_btr),
3672 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3673};
3674
fd0a0d82 3675static const struct group_dual group9 = { {
1c2545be 3676 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3677}, {
3678 N, N, N, N, N, N, N, N,
3679} };
3680
fd0a0d82 3681static const struct opcode group11[] = {
1c2545be 3682 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3683 X7(D(Undefined)),
a4d4a7c1
AK		 3684};
3685
fd0a0d82 3686static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3687 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3688};
3689
fd0a0d82 3690static const struct gprefix pfx_vmovntpx = {
3e114eb4
AK		 3691 I(0, em_mov), N, N, N,
3692};
3693
27ce8258 3694static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3695 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3696};
3697
045a282c
GN		 3698static const struct escape escape_d9 = { {
3699 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3700}, {
3701 /* 0xC0 - 0xC7 */
3702 N, N, N, N, N, N, N, N,
3703 /* 0xC8 - 0xCF */
3704 N, N, N, N, N, N, N, N,
3705 /* 0xD0 - 0xC7 */
3706 N, N, N, N, N, N, N, N,
3707 /* 0xD8 - 0xDF */
3708 N, N, N, N, N, N, N, N,
3709 /* 0xE0 - 0xE7 */
3710 N, N, N, N, N, N, N, N,
3711 /* 0xE8 - 0xEF */
3712 N, N, N, N, N, N, N, N,
3713 /* 0xF0 - 0xF7 */
3714 N, N, N, N, N, N, N, N,
3715 /* 0xF8 - 0xFF */
3716 N, N, N, N, N, N, N, N,
3717} };
3718
3719static const struct escape escape_db = { {
3720 N, N, N, N, N, N, N, N,
3721}, {
3722 /* 0xC0 - 0xC7 */
3723 N, N, N, N, N, N, N, N,
3724 /* 0xC8 - 0xCF */
3725 N, N, N, N, N, N, N, N,
3726 /* 0xD0 - 0xC7 */
3727 N, N, N, N, N, N, N, N,
3728 /* 0xD8 - 0xDF */
3729 N, N, N, N, N, N, N, N,
3730 /* 0xE0 - 0xE7 */
3731 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3732 /* 0xE8 - 0xEF */
3733 N, N, N, N, N, N, N, N,
3734 /* 0xF0 - 0xF7 */
3735 N, N, N, N, N, N, N, N,
3736 /* 0xF8 - 0xFF */
3737 N, N, N, N, N, N, N, N,
3738} };
3739
3740static const struct escape escape_dd = { {
3741 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3742}, {
3743 /* 0xC0 - 0xC7 */
3744 N, N, N, N, N, N, N, N,
3745 /* 0xC8 - 0xCF */
3746 N, N, N, N, N, N, N, N,
3747 /* 0xD0 - 0xC7 */
3748 N, N, N, N, N, N, N, N,
3749 /* 0xD8 - 0xDF */
3750 N, N, N, N, N, N, N, N,
3751 /* 0xE0 - 0xE7 */
3752 N, N, N, N, N, N, N, N,
3753 /* 0xE8 - 0xEF */
3754 N, N, N, N, N, N, N, N,
3755 /* 0xF0 - 0xF7 */
3756 N, N, N, N, N, N, N, N,
3757 /* 0xF8 - 0xFF */
3758 N, N, N, N, N, N, N, N,
3759} };
3760
fd0a0d82 3761static const struct opcode opcode_table[256] = {
73fba5f4 3762 /* 0x00 - 0x07 */
fb864fbc 3763 F6ALU(Lock, em_add),
1cd196ea
AK		 3764 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3765 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3766 /* 0x08 - 0x0F */
fb864fbc 3767 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3768 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3769 N,
73fba5f4 3770 /* 0x10 - 0x17 */
fb864fbc 3771 F6ALU(Lock, em_adc),
1cd196ea
AK		 3772 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3773 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3774 /* 0x18 - 0x1F */
fb864fbc 3775 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3776 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3777 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3778 /* 0x20 - 0x27 */
fb864fbc 3779 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3780 /* 0x28 - 0x2F */
fb864fbc 3781 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3782 /* 0x30 - 0x37 */
fb864fbc 3783 F6ALU(Lock, em_xor), N, N,
73fba5f4 3784 /* 0x38 - 0x3F */
fb864fbc 3785 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3786 /* 0x40 - 0x4F */
95413dc4 3787 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3788 /* 0x50 - 0x57 */
63540382 3789 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3790 /* 0x58 - 0x5F */
c54fe504 3791 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3792 /* 0x60 - 0x67 */
b96a7fad
TY		 3793 I(ImplicitOps | Stack | No64, em_pusha),
3794 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3795 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3796 N, N, N, N,
3797 /* 0x68 - 0x6F */
d46164db
AK		 3798 I(SrcImm | Mov | Stack, em_push),
3799 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3800 I(SrcImmByte | Mov | Stack, em_push),
3801 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3802 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3803 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3804 /* 0x70 - 0x7F */
3805 X16(D(SrcImmByte)),
3806 /* 0x80 - 0x87 */
1c2545be
TY		 3807 G(ByteOp | DstMem | SrcImm, group1),
3808 G(DstMem | SrcImm, group1),
3809 G(ByteOp | DstMem | SrcImm | No64, group1),
3810 G(DstMem | SrcImmByte, group1),
fb864fbc 3811 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 3812 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3813 /* 0x88 - 0x8F */
d5ae7ce8 3814 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3815 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3816 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3817 D(ModRM | SrcMem | NoAccess | DstReg),
3818 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3819 G(0, group1A),
73fba5f4 3820 /* 0x90 - 0x97 */
bf608f88 3821 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3822 /* 0x98 - 0x9F */
61429142 3823 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3824 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3825 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 3826 II(ImplicitOps | Stack, em_popf, popf),
3827 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 3828 /* 0xA0 - 0xA7 */
b9eac5f4 3829 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3830 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3831 I2bv(SrcSI | DstDI | Mov | String, em_mov),
fb864fbc 3832 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
73fba5f4 3833 /* 0xA8 - 0xAF */
fb864fbc 3834 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 3835 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3836 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
fb864fbc 3837 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
73fba5f4 3838 /* 0xB0 - 0xB7 */
b9eac5f4 3839 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3840 /* 0xB8 - 0xBF */
5e2c6883 3841 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 3842 /* 0xC0 - 0xC7 */
007a3b54 3843 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
40ece7c7 3844 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3845 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3846 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3847 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3848 G(ByteOp, group11), G(0, group11),
73fba5f4 3849 /* 0xC8 - 0xCF */
612e89f0 3850 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 3851 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
3852 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3853 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3854 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3855 /* 0xD0 - 0xD7 */
007a3b54
AK		 3856 G(Src2One | ByteOp, group2), G(Src2One, group2),
3857 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 3858 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 3859 I(DstAcc | SrcImmUByte | No64, em_aad),
3860 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 3861 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 3862 /* 0xD8 - 0xDF */
045a282c 3863 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 3864 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3865 X3(I(SrcImmByte, em_loop)),
3866 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3867 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3868 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3869 /* 0xE8 - 0xEF */
d4ddafcd 3870 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3871 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3872 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3873 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3874 /* 0xF0 - 0xF7 */
bf608f88 3875 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3876 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3877 G(ByteOp, group3), G(0, group3),
73fba5f4 3878 /* 0xF8 - 0xFF */
f411e6cd
TY		 3879 D(ImplicitOps), D(ImplicitOps),
3880 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3881 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3882};
3883
fd0a0d82 3884static const struct opcode twobyte_table[256] = {
73fba5f4 3885 /* 0x00 - 0x0F */
dee6bb70 3886 G(0, group6), GD(0, &group7), N, N,
b51e974f 3887 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 3888 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3889 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3890 N, D(ImplicitOps | ModRM), N, N,
3891 /* 0x10 - 0x1F */
103f98ea
PB		 3892 N, N, N, N, N, N, N, N,
3893 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
73fba5f4 3894 /* 0x20 - 0x2F */
9b88ae99
NA		 3895 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3896 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
3897 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
3898 check_cr_write),
3899 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
3900 check_dr_write),
73fba5f4 3901 N, N, N, N,
27ce8258
IM		 3902 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
3903 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
3904 N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3e114eb4 3905 N, N, N, N,
73fba5f4 3906 /* 0x30 - 0x3F */
e1e210b0 3907 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3908 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3909 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3910 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 3911 I(ImplicitOps | EmulateOnUD, em_sysenter),
3912 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 3913 N, N,
73fba5f4
AK		 3914 N, N, N, N, N, N, N, N,
3915 /* 0x40 - 0x4F */
3916 X16(D(DstReg | SrcMem | ModRM | Mov)),
3917 /* 0x50 - 0x5F */
3918 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3919 /* 0x60 - 0x6F */
aa97bb48
AK		 3920 N, N, N, N,
3921 N, N, N, N,
3922 N, N, N, N,
3923 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3924 /* 0x70 - 0x7F */
aa97bb48
AK		 3925 N, N, N, N,
3926 N, N, N, N,
3927 N, N, N, N,
3928 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3929 /* 0x80 - 0x8F */
3930 X16(D(SrcImm)),
3931 /* 0x90 - 0x9F */
ee45b58e 3932 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3933 /* 0xA0 - 0xA7 */
1cd196ea 3934 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 3935 II(ImplicitOps, em_cpuid, cpuid),
3936 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 3937 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
3938 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 3939 /* 0xA8 - 0xAF */
1cd196ea 3940 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3941 DI(ImplicitOps, rsm),
11c363ba 3942 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 3943 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3944 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4d758349 3945 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3946 /* 0xB0 - 0xB7 */
e940b5c2 3947 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3948 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 3949 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3950 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3951 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3952 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3953 /* 0xB8 - 0xBF */
3954 N, N,
ce7faab2 3955 G(BitOp, group8),
11c363ba
AK		 3956 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3957 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3958 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 3959 /* 0xC0 - 0xC7 */
e47a5f5f 3960 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
92f738a5 3961 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4 3962 N, N, N, GD(0, &group9),
9299836e
AK		 3963 /* 0xC8 - 0xCF */
3964 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 3965 /* 0xD0 - 0xDF */
3966 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3967 /* 0xE0 - 0xEF */
3968 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3969 /* 0xF0 - 0xFF */
3970 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3971};
3972
0bc5eedb 3973static const struct gprefix three_byte_0f_38_f0 = {
84cffe49 3974 I(DstReg | SrcMem | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3975};
3976
3977static const struct gprefix three_byte_0f_38_f1 = {
84cffe49 3978 I(DstMem | SrcReg | Mov, em_movbe), N, N, N
0bc5eedb
BP		 3979};
3980
3981/*
3982 * Insns below are selected by the prefix which indexed by the third opcode
3983 * byte.
3984 */
3985static const struct opcode opcode_map_0f_38[256] = {
3986 /* 0x00 - 0x7f */
3987 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 3988 /* 0x80 - 0xef */
3989 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
3990 /* 0xf0 - 0xf1 */
3991 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
3992 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
3993 /* 0xf2 - 0xff */
3994 N, N, X4(N), X8(N)
0bc5eedb
BP		 3995};
3996
73fba5f4
AK		 3997#undef D
3998#undef N
3999#undef G
4000#undef GD
4001#undef I
aa97bb48 4002#undef GP
01de8b09 4003#undef EXT
73fba5f4 4004
8d8f4e9f 4005#undef D2bv
f6511935 4006#undef D2bvIP
8d8f4e9f 4007#undef I2bv
d7841a4b 4008#undef I2bvIP
d67fc27a 4009#undef I6ALU
8d8f4e9f 4010
9dac77fa 4011static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4012{
4013 unsigned size;
4014
9dac77fa 4015 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4016 if (size == 8)
4017 size = 4;
4018 return size;
4019}
4020
4021static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4022 unsigned size, bool sign_extension)
4023{
39f21ee5
AK		 4024 int rc = X86EMUL_CONTINUE;
4025
4026 op->type = OP_IMM;
4027 op->bytes = size;
9dac77fa 4028 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4029 /* NB. Immediates are sign-extended as necessary. */
4030 switch (op->bytes) {
4031 case 1:
e85a1085 4032 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4033 break;
4034 case 2:
e85a1085 4035 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4036 break;
4037 case 4:
e85a1085 4038 op->val = insn_fetch(s32, ctxt);
39f21ee5 4039 break;
5e2c6883
NA		 4040 case 8:
4041 op->val = insn_fetch(s64, ctxt);
4042 break;
39f21ee5
AK		 4043 }
4044 if (!sign_extension) {
4045 switch (op->bytes) {
4046 case 1:
4047 op->val &= 0xff;
4048 break;
4049 case 2:
4050 op->val &= 0xffff;
4051 break;
4052 case 4:
4053 op->val &= 0xffffffff;
4054 break;
4055 }
4056 }
4057done:
4058 return rc;
4059}
4060
a9945549
AK		 4061static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4062 unsigned d)
4063{
4064 int rc = X86EMUL_CONTINUE;
4065
4066 switch (d) {
4067 case OpReg:
2adb5ad9 4068 decode_register_operand(ctxt, op);
a9945549
AK		 4069 break;
4070 case OpImmUByte:
608aabe3 4071 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4072 break;
4073 case OpMem:
41ddf978 4074 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4075 mem_common:
4076 *op = ctxt->memop;
4077 ctxt->memopp = op;
4078 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 4079 fetch_bit_operand(ctxt);
4080 op->orig_val = op->val;
4081 break;
41ddf978 4082 case OpMem64:
aaa05f24 4083 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4084 goto mem_common;
a9945549
AK		 4085 case OpAcc:
4086 op->type = OP_REG;
4087 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4088 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4089 fetch_register_operand(op);
4090 op->orig_val = op->val;
4091 break;
820207c8
AK		 4092 case OpAccLo:
4093 op->type = OP_REG;
4094 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4095 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4096 fetch_register_operand(op);
4097 op->orig_val = op->val;
4098 break;
4099 case OpAccHi:
4100 if (ctxt->d & ByteOp) {
4101 op->type = OP_NONE;
4102 break;
4103 }
4104 op->type = OP_REG;
4105 op->bytes = ctxt->op_bytes;
4106 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4107 fetch_register_operand(op);
4108 op->orig_val = op->val;
4109 break;
a9945549
AK		 4110 case OpDI:
4111 op->type = OP_MEM;
4112 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4113 op->addr.mem.ea =
dd856efa 4114 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
a9945549
AK		 4115 op->addr.mem.seg = VCPU_SREG_ES;
4116 op->val = 0;
b3356bf0 4117 op->count = 1;
a9945549
AK		 4118 break;
4119 case OpDX:
4120 op->type = OP_REG;
4121 op->bytes = 2;
dd856efa 4122 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4123 fetch_register_operand(op);
4124 break;
4dd6a57d
AK		 4125 case OpCL:
4126 op->bytes = 1;
dd856efa 4127 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4128 break;
4129 case OpImmByte:
4130 rc = decode_imm(ctxt, op, 1, true);
4131 break;
4132 case OpOne:
4133 op->bytes = 1;
4134 op->val = 1;
4135 break;
4136 case OpImm:
4137 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4138 break;
5e2c6883
NA		 4139 case OpImm64:
4140 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4141 break;
28867cee
AK		 4142 case OpMem8:
4143 ctxt->memop.bytes = 1;
660696d1 4144 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4145 ctxt->memop.addr.reg = decode_register(ctxt,
4146 ctxt->modrm_rm, true);
660696d1
GN		 4147 fetch_register_operand(&ctxt->memop);
4148 }
28867cee 4149 goto mem_common;
0fe59128
AK		 4150 case OpMem16:
4151 ctxt->memop.bytes = 2;
4152 goto mem_common;
4153 case OpMem32:
4154 ctxt->memop.bytes = 4;
4155 goto mem_common;
4156 case OpImmU16:
4157 rc = decode_imm(ctxt, op, 2, false);
4158 break;
4159 case OpImmU:
4160 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4161 break;
4162 case OpSI:
4163 op->type = OP_MEM;
4164 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4165 op->addr.mem.ea =
dd856efa 4166 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
0fe59128
AK		 4167 op->addr.mem.seg = seg_override(ctxt);
4168 op->val = 0;
b3356bf0 4169 op->count = 1;
0fe59128 4170 break;
7fa57952
PB		 4171 case OpXLat:
4172 op->type = OP_MEM;
4173 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4174 op->addr.mem.ea =
4175 register_address(ctxt,
4176 reg_read(ctxt, VCPU_REGS_RBX) +
4177 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4178 op->addr.mem.seg = seg_override(ctxt);
4179 op->val = 0;
4180 break;
0fe59128
AK		 4181 case OpImmFAddr:
4182 op->type = OP_IMM;
4183 op->addr.mem.ea = ctxt->_eip;
4184 op->bytes = ctxt->op_bytes + 2;
4185 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4186 break;
4187 case OpMemFAddr:
4188 ctxt->memop.bytes = ctxt->op_bytes + 2;
4189 goto mem_common;
c191a7a0
AK		 4190 case OpES:
4191 op->val = VCPU_SREG_ES;
4192 break;
4193 case OpCS:
4194 op->val = VCPU_SREG_CS;
4195 break;
4196 case OpSS:
4197 op->val = VCPU_SREG_SS;
4198 break;
4199 case OpDS:
4200 op->val = VCPU_SREG_DS;
4201 break;
4202 case OpFS:
4203 op->val = VCPU_SREG_FS;
4204 break;
4205 case OpGS:
4206 op->val = VCPU_SREG_GS;
4207 break;
a9945549
AK		 4208 case OpImplicit:
4209 /* Special instructions do their own operand decoding. */
4210 default:
4211 op->type = OP_NONE; /* Disable writeback. */
4212 break;
4213 }
4214
4215done:
4216 return rc;
4217}
4218
ef5d75cc 4219int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4220{
dde7e6d1
AK		 4221 int rc = X86EMUL_CONTINUE;
4222 int mode = ctxt->mode;
46561646 4223 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4224 bool op_prefix = false;
46561646 4225 struct opcode opcode;
dde7e6d1 4226
f09ed83e
AK		 4227 ctxt->memop.type = OP_NONE;
4228 ctxt->memopp = NULL;
9dac77fa
AK		 4229 ctxt->_eip = ctxt->eip;
4230 ctxt->fetch.start = ctxt->_eip;
4231 ctxt->fetch.end = ctxt->fetch.start + insn_len;
1ce19dc1 4232 ctxt->opcode_len = 1;
dc25e89e 4233 if (insn_len > 0)
9dac77fa 4234 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 4235
4236 switch (mode) {
4237 case X86EMUL_MODE_REAL:
4238 case X86EMUL_MODE_VM86:
4239 case X86EMUL_MODE_PROT16:
4240 def_op_bytes = def_ad_bytes = 2;
4241 break;
4242 case X86EMUL_MODE_PROT32:
4243 def_op_bytes = def_ad_bytes = 4;
4244 break;
4245#ifdef CONFIG_X86_64
4246 case X86EMUL_MODE_PROT64:
4247 def_op_bytes = 4;
4248 def_ad_bytes = 8;
4249 break;
4250#endif
4251 default:
1d2887e2 4252 return EMULATION_FAILED;
dde7e6d1
AK		 4253 }
4254
9dac77fa
AK		 4255 ctxt->op_bytes = def_op_bytes;
4256 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4257
4258 /* Legacy prefixes. */
4259 for (;;) {
e85a1085 4260 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4261 case 0x66: /* operand-size override */
0d7cdee8 4262 op_prefix = true;
dde7e6d1 4263 /* switch between 2/4 bytes */
9dac77fa 4264 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4265 break;
4266 case 0x67: /* address-size override */
4267 if (mode == X86EMUL_MODE_PROT64)
4268 /* switch between 4/8 bytes */
9dac77fa 4269 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4270 else
4271 /* switch between 2/4 bytes */
9dac77fa 4272 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4273 break;
4274 case 0x26: /* ES override */
4275 case 0x2e: /* CS override */
4276 case 0x36: /* SS override */
4277 case 0x3e: /* DS override */
9dac77fa 4278 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4279 break;
4280 case 0x64: /* FS override */
4281 case 0x65: /* GS override */
9dac77fa 4282 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4283 break;
4284 case 0x40 ... 0x4f: /* REX */
4285 if (mode != X86EMUL_MODE_PROT64)
4286 goto done_prefixes;
9dac77fa 4287 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4288 continue;
4289 case 0xf0: /* LOCK */
9dac77fa 4290 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4291 break;
4292 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4293 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4294 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4295 break;
4296 default:
4297 goto done_prefixes;
4298 }
4299
4300 /* Any legacy prefix after a REX prefix nullifies its effect. */
4301
9dac77fa 4302 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4303 }
4304
4305done_prefixes:
4306
4307 /* REX prefix. */
9dac77fa
AK		 4308 if (ctxt->rex_prefix & 8)
4309 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4310
4311 /* Opcode byte(s). */
9dac77fa 4312 opcode = opcode_table[ctxt->b];
d3ad6243 4313 /* Two-byte opcode? */
9dac77fa 4314 if (ctxt->b == 0x0f) {
1ce19dc1 4315 ctxt->opcode_len = 2;
e85a1085 4316 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4317 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4318
4319 /* 0F_38 opcode map */
4320 if (ctxt->b == 0x38) {
4321 ctxt->opcode_len = 3;
4322 ctxt->b = insn_fetch(u8, ctxt);
4323 opcode = opcode_map_0f_38[ctxt->b];
4324 }
dde7e6d1 4325 }
9dac77fa 4326 ctxt->d = opcode.flags;
dde7e6d1 4327
9f4260e7
TY		 4328 if (ctxt->d & ModRM)
4329 ctxt->modrm = insn_fetch(u8, ctxt);
4330
7fe864dc
NA		 4331 /* vex-prefix instructions are not implemented */
4332 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4333 (mode == X86EMUL_MODE_PROT64 ||
4334 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
4335 ctxt->d = NotImpl;
4336 }
4337
9dac77fa
AK		 4338 while (ctxt->d & GroupMask) {
4339 switch (ctxt->d & GroupMask) {
46561646 4340 case Group:
9dac77fa 4341 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4342 opcode = opcode.u.group[goffset];
4343 break;
4344 case GroupDual:
9dac77fa
AK		 4345 goffset = (ctxt->modrm >> 3) & 7;
4346 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4347 opcode = opcode.u.gdual->mod3[goffset];
4348 else
4349 opcode = opcode.u.gdual->mod012[goffset];
4350 break;
4351 case RMExt:
9dac77fa 4352 goffset = ctxt->modrm & 7;
01de8b09 4353 opcode = opcode.u.group[goffset];
46561646
AK		 4354 break;
4355 case Prefix:
9dac77fa 4356 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4357 return EMULATION_FAILED;
9dac77fa 4358 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4359 switch (simd_prefix) {
4360 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4361 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4362 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4363 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4364 }
4365 break;
045a282c
GN		 4366 case Escape:
4367 if (ctxt->modrm > 0xbf)
4368 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4369 else
4370 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4371 break;
46561646 4372 default:
1d2887e2 4373 return EMULATION_FAILED;
0d7cdee8 4374 }
46561646 4375
b1ea50b2 4376 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4377 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4378 }
4379
9dac77fa
AK		 4380 ctxt->execute = opcode.u.execute;
4381 ctxt->check_perm = opcode.check_perm;
4382 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4383
4384 /* Unrecognised? */
1146a78b 4385 if (ctxt->d == 0 || (ctxt->d & NotImpl))
1d2887e2 4386 return EMULATION_FAILED;
dde7e6d1 4387
b51e974f 4388 if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
1d2887e2 4389 return EMULATION_FAILED;
d867162c 4390
9dac77fa
AK		 4391 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4392 ctxt->op_bytes = 8;
dde7e6d1 4393
9dac77fa 4394 if (ctxt->d & Op3264) {
7f9b4b75 4395 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4396 ctxt->op_bytes = 8;
7f9b4b75 4397 else
9dac77fa 4398 ctxt->op_bytes = 4;
7f9b4b75
AK		 4399 }
4400
9dac77fa
AK		 4401 if (ctxt->d & Sse)
4402 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4403 else if (ctxt->d & Mmx)
4404 ctxt->op_bytes = 8;
1253791d 4405
dde7e6d1 4406 /* ModRM and SIB bytes. */
9dac77fa 4407 if (ctxt->d & ModRM) {
f09ed83e 4408 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4409 if (!ctxt->has_seg_override)
4410 set_seg_override(ctxt, ctxt->modrm_seg);
4411 } else if (ctxt->d & MemAbs)
f09ed83e 4412 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4413 if (rc != X86EMUL_CONTINUE)
4414 goto done;
4415
9dac77fa
AK		 4416 if (!ctxt->has_seg_override)
4417 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4418
f09ed83e 4419 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4420
f09ed83e
AK		 4421 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4422 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4423
dde7e6d1
AK		 4424 /*
4425 * Decode and fetch the source operand: register, memory
4426 * or immediate.
4427 */
0fe59128 4428 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4429 if (rc != X86EMUL_CONTINUE)
4430 goto done;
4431
dde7e6d1
AK		 4432 /*
4433 * Decode and fetch the second source operand: register, memory
4434 * or immediate.
4435 */
4dd6a57d 4436 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4437 if (rc != X86EMUL_CONTINUE)
4438 goto done;
4439
dde7e6d1 4440 /* Decode and fetch the destination operand: register or memory. */
a9945549 4441 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4442
4443done:
f09ed83e
AK		 4444 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4445 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4446
1d2887e2 4447 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4448}
4449
1cb3f3ae
XG		 4450bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4451{
4452 return ctxt->d & PageTable;
4453}
4454
3e2f65d5
GN		 4455static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4456{
3e2f65d5
GN		 4457 /* The second termination condition only applies for REPE
4458 * and REPNE. Test if the repeat string operation prefix is
4459 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4460 * corresponding termination condition according to:
4461 * - if REPE/REPZ and ZF = 0 then done
4462 * - if REPNE/REPNZ and ZF = 1 then done
4463 */
9dac77fa
AK		 4464 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4465 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4466 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4467 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4468 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4469 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4470 return true;
4471
4472 return false;
4473}
4474
cbe2c9d3
AK		 4475static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4476{
4477 bool fault = false;
4478
4479 ctxt->ops->get_fpu(ctxt);
4480 asm volatile("1: fwait \n\t"
4481 "2: \n\t"
4482 ".pushsection .fixup,\"ax\" \n\t"
4483 "3: \n\t"
4484 "movb $1, %[fault] \n\t"
4485 "jmp 2b \n\t"
4486 ".popsection \n\t"
4487 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4488 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4489 ctxt->ops->put_fpu(ctxt);
4490
4491 if (unlikely(fault))
4492 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4493
4494 return X86EMUL_CONTINUE;
4495}
4496
4497static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4498 struct operand *op)
4499{
4500 if (op->type == OP_MM)
4501 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4502}
4503
e28bbd44
AK		 4504static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4505{
4506 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4507 if (!(ctxt->d & ByteOp))
4508 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4509 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4510 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4511 [fastop]"+S"(fop)
4512 : "c"(ctxt->src2.val));
e28bbd44 4513 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4514 if (!fop) /* exception is returned in fop variable */
4515 return emulate_de(ctxt);
e28bbd44
AK		 4516 return X86EMUL_CONTINUE;
4517}
dd856efa 4518
7b105ca2 4519int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4520{
0225fb50 4521 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4522 int rc = X86EMUL_CONTINUE;
9dac77fa 4523 int saved_dst_type = ctxt->dst.type;
8b4caf66 4524
9dac77fa 4525 ctxt->mem_read.pos = 0;
310b5d30 4526
1146a78b
GN		 4527 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4528 (ctxt->d & Undefined)) {
35d3d4a1 4529 rc = emulate_ud(ctxt);
1161624f
GN		 4530 goto done;
4531 }
4532
d380a5e4 4533 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4534 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4535 rc = emulate_ud(ctxt);
d380a5e4
GN		 4536 goto done;
4537 }
4538
9dac77fa 4539 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4540 rc = emulate_ud(ctxt);
081bca0e
AK		 4541 goto done;
4542 }
4543
cbe2c9d3
AK		 4544 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4545 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4546 rc = emulate_ud(ctxt);
4547 goto done;
4548 }
4549
cbe2c9d3 4550 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4551 rc = emulate_nm(ctxt);
4552 goto done;
4553 }
4554
cbe2c9d3
AK		 4555 if (ctxt->d & Mmx) {
4556 rc = flush_pending_x87_faults(ctxt);
4557 if (rc != X86EMUL_CONTINUE)
4558 goto done;
4559 /*
4560 * Now that we know the fpu is exception safe, we can fetch
4561 * operands from it.
4562 */
4563 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4564 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4565 if (!(ctxt->d & Mov))
4566 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4567 }
4568
9dac77fa
AK		 4569 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4570 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4571 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4572 if (rc != X86EMUL_CONTINUE)
4573 goto done;
4574 }
4575
e92805ac 4576 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4577 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4578 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4579 goto done;
4580 }
4581
8ea7d6ae 4582 /* Instruction can only be executed in protected mode */
9d1b39a9 4583 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
8ea7d6ae
JR		 4584 rc = emulate_ud(ctxt);
4585 goto done;
4586 }
4587
d09beabd 4588 /* Do instruction specific permission checks */
9dac77fa
AK		 4589 if (ctxt->check_perm) {
4590 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4591 if (rc != X86EMUL_CONTINUE)
4592 goto done;
4593 }
4594
9dac77fa
AK		 4595 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4596 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4597 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4598 if (rc != X86EMUL_CONTINUE)
4599 goto done;
4600 }
4601
9dac77fa 4602 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4603 /* All REP prefixes have the same first termination condition */
dd856efa 4604 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
9dac77fa 4605 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4606 goto done;
4607 }
b9fa9d6b
AK		 4608 }
4609
9dac77fa
AK		 4610 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4611 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4612 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4613 if (rc != X86EMUL_CONTINUE)
8b4caf66 4614 goto done;
9dac77fa 4615 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4616 }
4617
9dac77fa
AK		 4618 if (ctxt->src2.type == OP_MEM) {
4619 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4620 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4621 if (rc != X86EMUL_CONTINUE)
4622 goto done;
4623 }
4624
9dac77fa 4625 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4626 goto special_insn;
4627
4628
9dac77fa 4629 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4630 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4631 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4632 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4633 if (rc != X86EMUL_CONTINUE)
4634 goto done;
038e51de 4635 }
9dac77fa 4636 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4637
018a98db
AK		 4638special_insn:
4639
9dac77fa
AK		 4640 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4641 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4642 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4643 if (rc != X86EMUL_CONTINUE)
4644 goto done;
4645 }
4646
9dac77fa 4647 if (ctxt->execute) {
e28bbd44
AK		 4648 if (ctxt->d & Fastop) {
4649 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4650 rc = fastop(ctxt, fop);
4651 if (rc != X86EMUL_CONTINUE)
4652 goto done;
4653 goto writeback;
4654 }
9dac77fa 4655 rc = ctxt->execute(ctxt);
ef65c889
AK		 4656 if (rc != X86EMUL_CONTINUE)
4657 goto done;
4658 goto writeback;
4659 }
4660
1ce19dc1 4661 if (ctxt->opcode_len == 2)
6aa8b732 4662 goto twobyte_insn;
0bc5eedb
BP		 4663 else if (ctxt->opcode_len == 3)
4664 goto threebyte_insn;
6aa8b732 4665
9dac77fa 4666 switch (ctxt->b) {
6aa8b732 4667 case 0x63: /* movsxd */
8b4caf66 4668 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4669 goto cannot_emulate;
9dac77fa 4670 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4671 break;
b2833e3c 4672 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4673 if (test_cc(ctxt->b, ctxt->eflags))
4674 jmp_rel(ctxt, ctxt->src.val);
018a98db 4675 break;
7e0b54b1 4676 case 0x8d: /* lea r16/r32, m */
9dac77fa 4677 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4678 break;
3d9e77df 4679 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4680 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
34698d8c 4681 break;
e4f973ae
TY		 4682 rc = em_xchg(ctxt);
4683 break;
e8b6fa70 4684 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4685 switch (ctxt->op_bytes) {
4686 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4687 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4688 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4689 }
4690 break;
6e154e56 4691 case 0xcc: /* int3 */
5c5df76b
TY		 4692 rc = emulate_int(ctxt, 3);
4693 break;
6e154e56 4694 case 0xcd: /* int n */
9dac77fa 4695 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4696 break;
4697 case 0xce: /* into */
5c5df76b
TY		 4698 if (ctxt->eflags & EFLG_OF)
4699 rc = emulate_int(ctxt, 4);
6e154e56 4700 break;
1a52e051 4701 case 0xe9: /* jmp rel */
db5b0762 4702 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4703 jmp_rel(ctxt, ctxt->src.val);
4704 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4705 break;
111de5d6 4706 case 0xf4: /* hlt */
6c3287f7 4707 ctxt->ops->halt(ctxt);
19fdfa0d 4708 break;
111de5d6
AK		 4709 case 0xf5: /* cmc */
4710 /* complement carry flag from eflags reg */
4711 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4712 break;
4713 case 0xf8: /* clc */
4714 ctxt->eflags &= ~EFLG_CF;
111de5d6 4715 break;
8744aa9a
MG		 4716 case 0xf9: /* stc */
4717 ctxt->eflags |= EFLG_CF;
4718 break;
fb4616f4
MG		 4719 case 0xfc: /* cld */
4720 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4721 break;
4722 case 0xfd: /* std */
4723 ctxt->eflags |= EFLG_DF;
fb4616f4 4724 break;
91269b8f
AK		 4725 default:
4726 goto cannot_emulate;
6aa8b732 4727 }
018a98db 4728
7d9ddaed
AK		 4729 if (rc != X86EMUL_CONTINUE)
4730 goto done;
4731
018a98db 4732writeback:
fb32b1ed
AK		 4733 if (!(ctxt->d & NoWrite)) {
4734 rc = writeback(ctxt, &ctxt->dst);
4735 if (rc != X86EMUL_CONTINUE)
4736 goto done;
4737 }
4738 if (ctxt->d & SrcWrite) {
4739 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4740 rc = writeback(ctxt, &ctxt->src);
4741 if (rc != X86EMUL_CONTINUE)
4742 goto done;
4743 }
018a98db 4744
5cd21917
GN		 4745 /*
4746 * restore dst type in case the decoding will be reused
4747 * (happens for string instruction )
4748 */
9dac77fa 4749 ctxt->dst.type = saved_dst_type;
5cd21917 4750
9dac77fa 4751 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 4752 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 4753
9dac77fa 4754 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 4755 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 4756
9dac77fa 4757 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 4758 unsigned int count;
9dac77fa 4759 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 4760 if ((ctxt->d & SrcMask) == SrcSI)
4761 count = ctxt->src.count;
4762 else
4763 count = ctxt->dst.count;
4764 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4765 -count);
3e2f65d5 4766
d2ddd1c4
GN		 4767 if (!string_insn_completed(ctxt)) {
4768 /*
4769 * Re-enter guest when pio read ahead buffer is empty
4770 * or, if it is not used, after each 1024 iteration.
4771 */
dd856efa 4772 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 4773 (r->end == 0 || r->end != r->pos)) {
4774 /*
4775 * Reset read cache. Usually happens before
4776 * decode, but since instruction is restarted
4777 * we have to do it here.
4778 */
9dac77fa 4779 ctxt->mem_read.end = 0;
dd856efa 4780 writeback_registers(ctxt);
d2ddd1c4
GN		 4781 return EMULATION_RESTART;
4782 }
4783 goto done; /* skip rip writeback */
0fa6ccbd 4784 }
5cd21917 4785 }
d2ddd1c4 4786
9dac77fa 4787 ctxt->eip = ctxt->_eip;
018a98db
AK		 4788
4789done:
da9cb575
AK		 4790 if (rc == X86EMUL_PROPAGATE_FAULT)
4791 ctxt->have_exception = true;
775fde86
JR		 4792 if (rc == X86EMUL_INTERCEPTED)
4793 return EMULATION_INTERCEPTED;
4794
dd856efa
AK		 4795 if (rc == X86EMUL_CONTINUE)
4796 writeback_registers(ctxt);
4797
d2ddd1c4 4798 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4799
4800twobyte_insn:
9dac77fa 4801 switch (ctxt->b) {
018a98db 4802 case 0x09: /* wbinvd */
cfb22375 4803 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4804 break;
4805 case 0x08: /* invd */
018a98db
AK		 4806 case 0x0d: /* GrpP (prefetch) */
4807 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 4808 case 0x1f: /* nop */
018a98db
AK		 4809 break;
4810 case 0x20: /* mov cr, reg */
9dac77fa 4811 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4812 break;
6aa8b732 4813 case 0x21: /* mov from dr to reg */
9dac77fa 4814 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4815 break;
6aa8b732 4816 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4817 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4818 if (!test_cc(ctxt->b, ctxt->eflags))
4819 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4820 break;
b2833e3c 4821 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4822 if (test_cc(ctxt->b, ctxt->eflags))
4823 jmp_rel(ctxt, ctxt->src.val);
018a98db 4824 break;
ee45b58e 4825 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4826 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4827 break;
2a7c5b8b
GC		 4828 case 0xae: /* clflush */
4829 break;
6aa8b732 4830 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4831 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4832 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4833 : (u16) ctxt->src.val;
6aa8b732 4834 break;
6aa8b732 4835 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4836 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4837 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4838 (s16) ctxt->src.val;
6aa8b732 4839 break;
a012e65a 4840 case 0xc3: /* movnti */
9dac77fa 4841 ctxt->dst.bytes = ctxt->op_bytes;
3b32004a
NA		 4842 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
4843 (u32) ctxt->src.val;
a012e65a 4844 break;
91269b8f
AK		 4845 default:
4846 goto cannot_emulate;
6aa8b732 4847 }
7d9ddaed 4848
0bc5eedb
BP		 4849threebyte_insn:
4850
7d9ddaed
AK		 4851 if (rc != X86EMUL_CONTINUE)
4852 goto done;
4853
6aa8b732
AK		 4854 goto writeback;
4855
4856cannot_emulate:
a0c0ab2f 4857 return EMULATION_FAILED;
6aa8b732 4858}
dd856efa
AK		 4859
4860void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4861{
4862 invalidate_registers(ctxt);
4863}
4864
4865void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4866{
4867 writeback_registers(ctxt);
4868}
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