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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
56e82318 25#include <asm/kvm_emulate.h>
b7d491e7 26#include <linux/stringify.h>
3db176d5 27#include <asm/debugreg.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
d1cd3ce9 31#include "mmu.h"
e99f0507 32
a9945549
AK		 33/*
34 * Operand types
35 */
b1ea50b2
AK		 36#define OpNone 0ull
37#define OpImplicit 1ull /* No generic decode */
38#define OpReg 2ull /* Register */
39#define OpMem 3ull /* Memory */
40#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41#define OpDI 5ull /* ES:DI/EDI/RDI */
42#define OpMem64 6ull /* Memory, 64-bit */
43#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44#define OpDX 8ull /* DX register */
4dd6a57d
AK		 45#define OpCL 9ull /* CL register (for shifts) */
46#define OpImmByte 10ull /* 8-bit sign extended immediate */
47#define OpOne 11ull /* Implied 1 */
5e2c6883 48#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 49#define OpMem16 13ull /* Memory operand (16-bit). */
50#define OpMem32 14ull /* Memory operand (32-bit). */
51#define OpImmU 15ull /* Immediate operand, zero extended */
52#define OpSI 16ull /* SI/ESI/RSI */
53#define OpImmFAddr 17ull /* Immediate far address */
54#define OpMemFAddr 18ull /* Far address in memory */
55#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 56#define OpES 20ull /* ES */
57#define OpCS 21ull /* CS */
58#define OpSS 22ull /* SS */
59#define OpDS 23ull /* DS */
60#define OpFS 24ull /* FS */
61#define OpGS 25ull /* GS */
28867cee 62#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 63#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 64#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 65#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 67
68#define OpBits 5 /* Width of operand field */
b1ea50b2 69#define OpMask ((1ull << OpBits) - 1)
a9945549 70
6aa8b732
AK		 71/*
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
77 * not be handled.
78 */
79
80/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 81#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 82/* Destination operand type. */
a9945549
AK		 83#define DstShift 1
84#define ImplicitOps (OpImplicit << DstShift)
85#define DstReg (OpReg << DstShift)
86#define DstMem (OpMem << DstShift)
87#define DstAcc (OpAcc << DstShift)
88#define DstDI (OpDI << DstShift)
89#define DstMem64 (OpMem64 << DstShift)
16bebefe 90#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 91#define DstImmUByte (OpImmUByte << DstShift)
92#define DstDX (OpDX << DstShift)
820207c8 93#define DstAccLo (OpAccLo << DstShift)
a9945549 94#define DstMask (OpMask << DstShift)
6aa8b732 95/* Source operand type. */
0fe59128
AK		 96#define SrcShift 6
97#define SrcNone (OpNone << SrcShift)
98#define SrcReg (OpReg << SrcShift)
99#define SrcMem (OpMem << SrcShift)
100#define SrcMem16 (OpMem16 << SrcShift)
101#define SrcMem32 (OpMem32 << SrcShift)
102#define SrcImm (OpImm << SrcShift)
103#define SrcImmByte (OpImmByte << SrcShift)
104#define SrcOne (OpOne << SrcShift)
105#define SrcImmUByte (OpImmUByte << SrcShift)
106#define SrcImmU (OpImmU << SrcShift)
107#define SrcSI (OpSI << SrcShift)
7fa57952 108#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 109#define SrcImmFAddr (OpImmFAddr << SrcShift)
110#define SrcMemFAddr (OpMemFAddr << SrcShift)
111#define SrcAcc (OpAcc << SrcShift)
112#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 113#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 114#define SrcDX (OpDX << SrcShift)
28867cee 115#define SrcMem8 (OpMem8 << SrcShift)
820207c8 116#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 117#define SrcMask (OpMask << SrcShift)
221192bd
MT		 118#define BitOp (1<<11)
119#define MemAbs (1<<12) /* Memory operand is absolute displacement */
120#define String (1<<13) /* String instruction (rep capable) */
121#define Stack (1<<14) /* Stack instruction (push/pop) */
122#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 127#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 128#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 129#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 130#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 131/* Generic ModRM decode. */
132#define ModRM (1<<19)
133/* Destination is only written; never read. */
134#define Mov (1<<20)
d8769fed 135/* Misc flags */
8ea7d6ae 136#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 137#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 138#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 139#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 140#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 141#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 142#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 143#define No64 (1<<28)
d5ae7ce8 144#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 145#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 146/* Source 2 operand type */
0b789eee 147#define Src2Shift (31)
4dd6a57d 148#define Src2None (OpNone << Src2Shift)
ab2c5ce6 149#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 150#define Src2CL (OpCL << Src2Shift)
151#define Src2ImmByte (OpImmByte << Src2Shift)
152#define Src2One (OpOne << Src2Shift)
153#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 154#define Src2ES (OpES << Src2Shift)
155#define Src2CS (OpCS << Src2Shift)
156#define Src2SS (OpSS << Src2Shift)
157#define Src2DS (OpDS << Src2Shift)
158#define Src2FS (OpFS << Src2Shift)
159#define Src2GS (OpGS << Src2Shift)
4dd6a57d 160#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 161#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 162#define AlignMask ((u64)7 << 41)
1c11b376 163#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 164#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
165#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
166#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 167#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 168#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 169#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 170#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 171#define Intercept ((u64)1 << 48) /* Has valid intercept field */
172#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 173#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 174#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 175#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 176#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
0f89b207 177#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
6aa8b732 178
820207c8 179#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 180
d0e53325
AK		 181#define X2(x...) x, x
182#define X3(x...) X2(x), x
183#define X4(x...) X2(x), X2(x)
184#define X5(x...) X4(x), x
185#define X6(x...) X4(x), X2(x)
186#define X7(x...) X4(x), X3(x)
187#define X8(x...) X4(x), X4(x)
188#define X16(x...) X8(x), X8(x)
83babbca 189
e28bbd44
AK		 190#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
191#define FASTOP_SIZE 8
192
193/*
194 * fastop functions have a special calling convention:
195 *
017da7b6
AK		 196 * dst: rax (in/out)
197 * src: rdx (in/out)
e28bbd44
AK		 198 * src2: rcx (in)
199 * flags: rflags (in/out)
b8c0b6ae 200 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 201 *
202 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
203 * different operand sizes can be reached by calculation, rather than a jump
204 * table (which would be bigger than the code).
205 *
206 * fastop functions are declared as taking a never-defined fastop parameter,
207 * so they can't be called from C directly.
208 */
209
210struct fastop;
211
d65b1dee 212struct opcode {
b1ea50b2
AK		 213 u64 flags : 56;
214 u64 intercept : 8;
120df890 215 union {
ef65c889 216 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 217 const struct opcode *group;
218 const struct group_dual *gdual;
219 const struct gprefix *gprefix;
045a282c 220 const struct escape *esc;
39f062ff 221 const struct instr_dual *idual;
2276b511 222 const struct mode_dual *mdual;
e28bbd44 223 void (*fastop)(struct fastop *fake);
120df890 224 } u;
d09beabd 225 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 226};
227
228struct group_dual {
229 struct opcode mod012[8];
230 struct opcode mod3[8];
d65b1dee
AK		 231};
232
0d7cdee8
AK		 233struct gprefix {
234 struct opcode pfx_no;
235 struct opcode pfx_66;
236 struct opcode pfx_f2;
237 struct opcode pfx_f3;
238};
239
045a282c
GN		 240struct escape {
241 struct opcode op[8];
242 struct opcode high[64];
243};
244
39f062ff
NA		 245struct instr_dual {
246 struct opcode mod012;
247 struct opcode mod3;
248};
249
2276b511
NA		 250struct mode_dual {
251 struct opcode mode32;
252 struct opcode mode64;
253};
254
62bd430e 255#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 256
3dc4bc4f
NA		 257enum x86_transfer_type {
258 X86_TRANSFER_NONE,
259 X86_TRANSFER_CALL_JMP,
260 X86_TRANSFER_RET,
261 X86_TRANSFER_TASK_SWITCH,
262};
263
dd856efa
AK		 264static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
265{
266 if (!(ctxt->regs_valid & (1 << nr))) {
267 ctxt->regs_valid |= 1 << nr;
268 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
269 }
270 return ctxt->_regs[nr];
271}
272
273static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
274{
275 ctxt->regs_valid |= 1 << nr;
276 ctxt->regs_dirty |= 1 << nr;
277 return &ctxt->_regs[nr];
278}
279
280static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
281{
282 reg_read(ctxt, nr);
283 return reg_write(ctxt, nr);
284}
285
286static void writeback_registers(struct x86_emulate_ctxt *ctxt)
287{
288 unsigned reg;
289
290 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
291 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
292}
293
294static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
295{
296 ctxt->regs_dirty = 0;
297 ctxt->regs_valid = 0;
298}
299
6aa8b732
AK		 300/*
301 * These EFLAGS bits are restored from saved value during emulation, and
302 * any changes are written back to the saved value after emulation.
303 */
0efb0440
NA		 304#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
305 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 306
dda96d8f
AK		 307#ifdef CONFIG_X86_64
308#define ON64(x) x
309#else
310#define ON64(x)
311#endif
312
4d758349
AK		 313static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
314
1482a082
JP		 315#define FOP_FUNC(name) \
316 ".align " __stringify(FASTOP_SIZE) " \n\t" \
317 ".type " name ", @function \n\t" \
318 name ":\n\t"
319
b7d491e7
AK		 320#define FOP_RET "ret \n\t"
321
322#define FOP_START(op) \
323 extern void em_##op(struct fastop *fake); \
324 asm(".pushsection .text, \"ax\" \n\t" \
325 ".global em_" #op " \n\t" \
1482a082 326 FOP_FUNC("em_" #op)
b7d491e7
AK		 327
328#define FOP_END \
329 ".popsection")
330
1482a082
JP		 331#define FOPNOP() \
332 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
333 FOP_RET
0bdea068 334
b7d491e7 335#define FOP1E(op, dst) \
1482a082
JP		 336 FOP_FUNC(#op "_" #dst) \
337 "10: " #op " %" #dst " \n\t" FOP_RET
b8c0b6ae
AK		 338
339#define FOP1EEX(op, dst) \
340 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 341
342#define FASTOP1(op) \
343 FOP_START(op) \
344 FOP1E(op##b, al) \
345 FOP1E(op##w, ax) \
346 FOP1E(op##l, eax) \
347 ON64(FOP1E(op##q, rax)) \
348 FOP_END
349
b9fa409b
AK		 350/* 1-operand, using src2 (for MUL/DIV r/m) */
351#define FASTOP1SRC2(op, name) \
352 FOP_START(name) \
353 FOP1E(op, cl) \
354 FOP1E(op, cx) \
355 FOP1E(op, ecx) \
356 ON64(FOP1E(op, rcx)) \
357 FOP_END
358
b8c0b6ae
AK		 359/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
360#define FASTOP1SRC2EX(op, name) \
361 FOP_START(name) \
362 FOP1EEX(op, cl) \
363 FOP1EEX(op, cx) \
364 FOP1EEX(op, ecx) \
365 ON64(FOP1EEX(op, rcx)) \
366 FOP_END
367
f7857f35 368#define FOP2E(op, dst, src) \
1482a082
JP		 369 FOP_FUNC(#op "_" #dst "_" #src) \
370 #op " %" #src ", %" #dst " \n\t" FOP_RET
f7857f35
AK		 371
372#define FASTOP2(op) \
373 FOP_START(op) \
017da7b6
AK		 374 FOP2E(op##b, al, dl) \
375 FOP2E(op##w, ax, dx) \
376 FOP2E(op##l, eax, edx) \
377 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 378 FOP_END
379
11c363ba
AK		 380/* 2 operand, word only */
381#define FASTOP2W(op) \
382 FOP_START(op) \
383 FOPNOP() \
017da7b6
AK		 384 FOP2E(op##w, ax, dx) \
385 FOP2E(op##l, eax, edx) \
386 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 387 FOP_END
388
007a3b54
AK		 389/* 2 operand, src is CL */
390#define FASTOP2CL(op) \
391 FOP_START(op) \
392 FOP2E(op##b, al, cl) \
393 FOP2E(op##w, ax, cl) \
394 FOP2E(op##l, eax, cl) \
395 ON64(FOP2E(op##q, rax, cl)) \
396 FOP_END
397
5aca3722
NA		 398/* 2 operand, src and dest are reversed */
399#define FASTOP2R(op, name) \
400 FOP_START(name) \
401 FOP2E(op##b, dl, al) \
402 FOP2E(op##w, dx, ax) \
403 FOP2E(op##l, edx, eax) \
404 ON64(FOP2E(op##q, rdx, rax)) \
405 FOP_END
406
0bdea068 407#define FOP3E(op, dst, src, src2) \
1482a082
JP		 408 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
409 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
0bdea068
AK		 410
411/* 3-operand, word-only, src2=cl */
412#define FASTOP3WCL(op) \
413 FOP_START(op) \
414 FOPNOP() \
017da7b6
AK		 415 FOP3E(op##w, ax, dx, cl) \
416 FOP3E(op##l, eax, edx, cl) \
417 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 418 FOP_END
419
9ae9feba 420/* Special case for SETcc - 1 instruction per cc */
1482a082
JP		 421#define FOP_SETCC(op) \
422 ".align 4 \n\t" \
423 ".type " #op ", @function \n\t" \
424 #op ": \n\t" \
425 #op " %al \n\t" \
426 FOP_RET
9ae9feba 427
f26e6016
JP		 428asm(".pushsection .fixup, \"ax\"\n"
429 ".global kvm_fastop_exception \n"
430 "kvm_fastop_exception: xor %esi, %esi; ret\n"
431 ".popsection");
b8c0b6ae 432
9ae9feba
AK		 433FOP_START(setcc)
434FOP_SETCC(seto)
435FOP_SETCC(setno)
436FOP_SETCC(setc)
437FOP_SETCC(setnc)
438FOP_SETCC(setz)
439FOP_SETCC(setnz)
440FOP_SETCC(setbe)
441FOP_SETCC(setnbe)
442FOP_SETCC(sets)
443FOP_SETCC(setns)
444FOP_SETCC(setp)
445FOP_SETCC(setnp)
446FOP_SETCC(setl)
447FOP_SETCC(setnl)
448FOP_SETCC(setle)
449FOP_SETCC(setnle)
450FOP_END;
451
326f578f
PB		 452FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
453FOP_END;
454
aabba3c6
RK		 455/*
456 * XXX: inoutclob user must know where the argument is being expanded.
457 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
458 */
459#define asm_safe(insn, inoutclob...) \
460({ \
461 int _fault = 0; \
462 \
463 asm volatile("1:" insn "\n" \
464 "2:\n" \
465 ".pushsection .fixup, \"ax\"\n" \
466 "3: movl $1, %[_fault]\n" \
467 " jmp 2b\n" \
468 ".popsection\n" \
469 _ASM_EXTABLE(1b, 3b) \
470 : [_fault] "+qm"(_fault) inoutclob ); \
471 \
472 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
473})
474
8a76d7f2
JR		 475static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
476 enum x86_intercept intercept,
477 enum x86_intercept_stage stage)
478{
479 struct x86_instruction_info info = {
480 .intercept = intercept,
9dac77fa
AK		 481 .rep_prefix = ctxt->rep_prefix,
482 .modrm_mod = ctxt->modrm_mod,
483 .modrm_reg = ctxt->modrm_reg,
484 .modrm_rm = ctxt->modrm_rm,
485 .src_val = ctxt->src.val64,
6cbc5f5a 486 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 487 .src_bytes = ctxt->src.bytes,
488 .dst_bytes = ctxt->dst.bytes,
489 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 490 .next_rip = ctxt->eip,
491 };
492
2953538e 493 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 494}
495
f47cfa31
AK		 496static void assign_masked(ulong *dest, ulong src, ulong mask)
497{
498 *dest = (*dest & ~mask) | (src & mask);
499}
500
6fd8e127
NA		 501static void assign_register(unsigned long *reg, u64 val, int bytes)
502{
503 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
504 switch (bytes) {
505 case 1:
506 *(u8 *)reg = (u8)val;
507 break;
508 case 2:
509 *(u16 *)reg = (u16)val;
510 break;
511 case 4:
512 *reg = (u32)val;
513 break; /* 64b: zero-extend */
514 case 8:
515 *reg = val;
516 break;
517 }
518}
519
9dac77fa 520static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 521{
9dac77fa 522 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 523}
524
f47cfa31
AK		 525static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
526{
527 u16 sel;
528 struct desc_struct ss;
529
530 if (ctxt->mode == X86EMUL_MODE_PROT64)
531 return ~0UL;
532 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
533 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
534}
535
612e89f0
AK		 536static int stack_size(struct x86_emulate_ctxt *ctxt)
537{
538 return (__fls(stack_mask(ctxt)) + 1) >> 3;
539}
540
6aa8b732 541/* Access/update address held in a register, based on addressing mode. */
e4706772 542static inline unsigned long
9dac77fa 543address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 544{
9dac77fa 545 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 546 return reg;
547 else
9dac77fa 548 return reg & ad_mask(ctxt);
e4706772
HH		 549}
550
551static inline unsigned long
01485a22 552register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 553{
01485a22 554 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 555}
556
5ad105e5
AK		 557static void masked_increment(ulong *reg, ulong mask, int inc)
558{
559 assign_masked(reg, *reg + inc, mask);
560}
561
7a957275 562static inline void
01485a22 563register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 564{
ee122a71 565 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 566
ee122a71 567 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 568}
569
570static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
571{
dd856efa 572 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 573}
6aa8b732 574
56697687
AK		 575static u32 desc_limit_scaled(struct desc_struct *desc)
576{
577 u32 limit = get_desc_limit(desc);
578
579 return desc->g ? (limit << 12) | 0xfff : limit;
580}
581
7b105ca2 582static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 583{
584 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
585 return 0;
586
7b105ca2 587 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 588}
589
35d3d4a1
AK		 590static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
591 u32 error, bool valid)
54b8486f 592{
e0ad0b47 593 WARN_ON(vec > 0x1f);
da9cb575
AK		 594 ctxt->exception.vector = vec;
595 ctxt->exception.error_code = error;
596 ctxt->exception.error_code_valid = valid;
35d3d4a1 597 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 598}
599
3b88e41a
JR		 600static int emulate_db(struct x86_emulate_ctxt *ctxt)
601{
602 return emulate_exception(ctxt, DB_VECTOR, 0, false);
603}
604
35d3d4a1 605static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 606{
35d3d4a1 607 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 608}
609
618ff15d
AK		 610static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
611{
612 return emulate_exception(ctxt, SS_VECTOR, err, true);
613}
614
35d3d4a1 615static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 616{
35d3d4a1 617 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 618}
619
35d3d4a1 620static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 621{
35d3d4a1 622 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 623}
624
34d1f490
AK		 625static int emulate_de(struct x86_emulate_ctxt *ctxt)
626{
35d3d4a1 627 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 628}
629
1253791d
AK		 630static int emulate_nm(struct x86_emulate_ctxt *ctxt)
631{
632 return emulate_exception(ctxt, NM_VECTOR, 0, false);
633}
634
1aa36616
AK		 635static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
636{
637 u16 selector;
638 struct desc_struct desc;
639
640 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
641 return selector;
642}
643
644static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
645 unsigned seg)
646{
647 u16 dummy;
648 u32 base3;
649 struct desc_struct desc;
650
651 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
652 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
653}
654
1c11b376
AK		 655/*
656 * x86 defines three classes of vector instructions: explicitly
657 * aligned, explicitly unaligned, and the rest, which change behaviour
658 * depending on whether they're AVX encoded or not.
659 *
660 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 661 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
662 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 663 */
d3fe959f 664static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 665{
48520187 666 u64 alignment = ctxt->d & AlignMask;
1c11b376 667
1c11b376 668 if (likely(size < 16))
d3fe959f 669 return 1;
1c11b376 670
48520187
RK		 671 switch (alignment) {
672 case Unaligned:
673 case Avx:
d3fe959f 674 return 1;
48520187 675 case Aligned16:
d3fe959f 676 return 16;
48520187
RK		 677 case Aligned:
678 default:
d3fe959f 679 return size;
48520187 680 }
1c11b376
AK		 681}
682
d09155d2
PB		 683static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
684 struct segmented_address addr,
685 unsigned *max_size, unsigned size,
686 bool write, bool fetch,
d50eaa18 687 enum x86emul_mode mode, ulong *linear)
52fd8b44 688{
618ff15d
AK		 689 struct desc_struct desc;
690 bool usable;
52fd8b44 691 ulong la;
618ff15d 692 u32 lim;
1aa36616 693 u16 sel;
fd8cb433 694 u8 va_bits;
52fd8b44 695
7b105ca2 696 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 697 *max_size = 0;
d50eaa18 698 switch (mode) {
618ff15d 699 case X86EMUL_MODE_PROT64:
0c1d77f4 700 *linear = la;
fd8cb433
YZ		 701 va_bits = ctxt_virt_addr_bits(ctxt);
702 if (get_canonical(la, va_bits) != la)
abc7d8a4 703 goto bad;
fd56e154 704
fd8cb433 705 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
fd56e154
PB		 706 if (size > *max_size)
707 goto bad;
618ff15d
AK		 708 break;
709 default:
0c1d77f4 710 *linear = la = (u32)la;
1aa36616
AK		 711 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
712 addr.seg);
618ff15d
AK		 713 if (!usable)
714 goto bad;
58b7825b
GN		 715 /* code segment in protected mode or read-only data segment */
716 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
717 || !(desc.type & 2)) && write)
618ff15d
AK		 718 goto bad;
719 /* unreadable code segment */
3d9b938e 720 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 721 goto bad;
722 lim = desc_limit_scaled(&desc);
997b0412 723 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 724 /* expand-down segment */
fd56e154 725 if (addr.ea <= lim)
618ff15d
AK		 726 goto bad;
727 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 728 }
997b0412
PB		 729 if (addr.ea > lim)
730 goto bad;
bac15531
NA		 731 if (lim == 0xffffffff)
732 *max_size = ~0u;
733 else {
734 *max_size = (u64)lim + 1 - addr.ea;
735 if (size > *max_size)
736 goto bad;
737 }
618ff15d
AK		 738 break;
739 }
d3fe959f 740 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 741 return emulate_gp(ctxt, 0);
52fd8b44 742 return X86EMUL_CONTINUE;
618ff15d
AK		 743bad:
744 if (addr.seg == VCPU_SREG_SS)
3606189f 745 return emulate_ss(ctxt, 0);
618ff15d 746 else
3606189f 747 return emulate_gp(ctxt, 0);
52fd8b44
AK		 748}
749
3d9b938e
NE		 750static int linearize(struct x86_emulate_ctxt *ctxt,
751 struct segmented_address addr,
752 unsigned size, bool write,
753 ulong *linear)
754{
fd56e154 755 unsigned max_size;
d50eaa18
NA		 756 return __linearize(ctxt, addr, &max_size, size, write, false,
757 ctxt->mode, linear);
3d9b938e
NE		 758}
759
d50eaa18
NA		 760static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
761 enum x86emul_mode mode)
762{
763 ulong linear;
764 int rc;
765 unsigned max_size;
766 struct segmented_address addr = { .seg = VCPU_SREG_CS,
767 .ea = dst };
768
769 if (ctxt->op_bytes != sizeof(unsigned long))
770 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
771 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
772 if (rc == X86EMUL_CONTINUE)
773 ctxt->_eip = addr.ea;
774 return rc;
775}
776
777static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
778{
779 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 780}
781
d50eaa18
NA		 782static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
783 const struct desc_struct *cs_desc)
784{
785 enum x86emul_mode mode = ctxt->mode;
82268083 786 int rc;
d50eaa18
NA		 787
788#ifdef CONFIG_X86_64
82268083
NA		 789 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
790 if (cs_desc->l) {
791 u64 efer = 0;
d50eaa18 792
82268083
NA		 793 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
794 if (efer & EFER_LMA)
795 mode = X86EMUL_MODE_PROT64;
796 } else
797 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 798 }
799#endif
800 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
801 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 802 rc = assign_eip(ctxt, dst, mode);
803 if (rc == X86EMUL_CONTINUE)
804 ctxt->mode = mode;
805 return rc;
d50eaa18
NA		 806}
807
808static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
809{
810 return assign_eip_near(ctxt, ctxt->_eip + rel);
811}
3d9b938e 812
3ca3ac4d
AK		 813static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
814 struct segmented_address addr,
815 void *data,
816 unsigned size)
817{
9fa088f4
AK		 818 int rc;
819 ulong linear;
820
83b8795a 821 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 822 if (rc != X86EMUL_CONTINUE)
823 return rc;
0f65dd70 824 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 825}
826
129a72a0
SR		 827static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
828 struct segmented_address addr,
829 void *data,
830 unsigned int size)
831{
832 int rc;
833 ulong linear;
834
835 rc = linearize(ctxt, addr, size, true, &linear);
836 if (rc != X86EMUL_CONTINUE)
837 return rc;
838 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
839}
840
807941b1 841/*
285ca9e9 842 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 843 * boundary if they are not in fetch_cache yet.
844 */
9506d57d 845static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 846{
62266869 847 int rc;
fd56e154 848 unsigned size, max_size;
285ca9e9 849 unsigned long linear;
17052f16 850 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 851 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 852 .ea = ctxt->eip + cur_size };
853
fd56e154
PB		 854 /*
855 * We do not know exactly how many bytes will be needed, and
856 * __linearize is expensive, so fetch as much as possible. We
857 * just have to avoid going beyond the 15 byte limit, the end
858 * of the segment, or the end of the page.
859 *
860 * __linearize is called with size 0 so that it does not do any
861 * boundary check itself. Instead, we use max_size to check
862 * against op_size.
863 */
d50eaa18
NA		 864 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
865 &linear);
719d5a9b
PB		 866 if (unlikely(rc != X86EMUL_CONTINUE))
867 return rc;
868
fd56e154 869 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 870 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 871
872 /*
873 * One instruction can only straddle two pages,
874 * and one has been loaded at the beginning of
875 * x86_decode_insn. So, if not enough bytes
876 * still, we must have hit the 15-byte boundary.
877 */
878 if (unlikely(size < op_size))
fd56e154
PB		 879 return emulate_gp(ctxt, 0);
880
17052f16 881 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 882 size, &ctxt->exception);
883 if (unlikely(rc != X86EMUL_CONTINUE))
884 return rc;
17052f16 885 ctxt->fetch.end += size;
3e2815e9 886 return X86EMUL_CONTINUE;
62266869
AK		 887}
888
9506d57d
PB		 889static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
890 unsigned size)
62266869 891{
08da44ae
NA		 892 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
893
894 if (unlikely(done_size < size))
895 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 896 else
897 return X86EMUL_CONTINUE;
62266869
AK		 898}
899
67cbc90d 900/* Fetch next part of the instruction being emulated. */
e85a1085 901#define insn_fetch(_type, _ctxt) \
9506d57d 902({ _type _x; \
9506d57d
PB		 903 \
904 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 905 if (rc != X86EMUL_CONTINUE) \
906 goto done; \
9506d57d 907 ctxt->_eip += sizeof(_type); \
8616abc2 908 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
17052f16 909 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 910 _x; \
67cbc90d
TY		 911})
912
807941b1 913#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 914({ \
9506d57d 915 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 916 if (rc != X86EMUL_CONTINUE) \
917 goto done; \
9506d57d 918 ctxt->_eip += (_size); \
17052f16
PB		 919 memcpy(_arr, ctxt->fetch.ptr, _size); \
920 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 921})
922
1e3c5cb0
RR		 923/*
924 * Given the 'reg' portion of a ModRM byte, and a register block, return a
925 * pointer into the block that addresses the relevant register.
926 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
927 */
dd856efa 928static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 929 int byteop)
6aa8b732
AK		 930{
931 void *p;
aa9ac1a6 932 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 933
6aa8b732 934 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 935 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
936 else
937 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 938 return p;
939}
940
941static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 942 struct segmented_address addr,
6aa8b732
AK		 943 u16 *size, unsigned long *address, int op_bytes)
944{
945 int rc;
946
947 if (op_bytes == 2)
948 op_bytes = 3;
949 *address = 0;
3ca3ac4d 950 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 951 if (rc != X86EMUL_CONTINUE)
6aa8b732 952 return rc;
30b31ab6 953 addr.ea += 2;
3ca3ac4d 954 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 955 return rc;
956}
957
34b77652
AK		 958FASTOP2(add);
959FASTOP2(or);
960FASTOP2(adc);
961FASTOP2(sbb);
962FASTOP2(and);
963FASTOP2(sub);
964FASTOP2(xor);
965FASTOP2(cmp);
966FASTOP2(test);
967
b9fa409b
AK		 968FASTOP1SRC2(mul, mul_ex);
969FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 970FASTOP1SRC2EX(div, div_ex);
971FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 972
34b77652
AK		 973FASTOP3WCL(shld);
974FASTOP3WCL(shrd);
975
976FASTOP2W(imul);
977
978FASTOP1(not);
979FASTOP1(neg);
980FASTOP1(inc);
981FASTOP1(dec);
982
983FASTOP2CL(rol);
984FASTOP2CL(ror);
985FASTOP2CL(rcl);
986FASTOP2CL(rcr);
987FASTOP2CL(shl);
988FASTOP2CL(shr);
989FASTOP2CL(sar);
990
991FASTOP2W(bsf);
992FASTOP2W(bsr);
993FASTOP2W(bt);
994FASTOP2W(bts);
995FASTOP2W(btr);
996FASTOP2W(btc);
997
e47a5f5f
AK		 998FASTOP2(xadd);
999
5aca3722
NA		 1000FASTOP2R(cmp, cmp_r);
1001
900efe20
NA		 1002static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1003{
1004 /* If src is zero, do not writeback, but update flags */
1005 if (ctxt->src.val == 0)
1006 ctxt->dst.type = OP_NONE;
1007 return fastop(ctxt, em_bsf);
1008}
1009
1010static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1011{
1012 /* If src is zero, do not writeback, but update flags */
1013 if (ctxt->src.val == 0)
1014 ctxt->dst.type = OP_NONE;
1015 return fastop(ctxt, em_bsr);
1016}
1017
cb7390fe 1018static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1019{
9ae9feba
AK		 1020 u8 rc;
1021 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1022
9ae9feba 1023 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1024 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1025 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1026 return rc;
bbe9abbd
NK		 1027}
1028
91ff3cb4
AK		 1029static void fetch_register_operand(struct operand *op)
1030{
1031 switch (op->bytes) {
1032 case 1:
1033 op->val = *(u8 *)op->addr.reg;
1034 break;
1035 case 2:
1036 op->val = *(u16 *)op->addr.reg;
1037 break;
1038 case 4:
1039 op->val = *(u32 *)op->addr.reg;
1040 break;
1041 case 8:
1042 op->val = *(u64 *)op->addr.reg;
1043 break;
1044 }
1045}
1046
1253791d
AK		 1047static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1048{
1253791d 1049 switch (reg) {
89a87c67
MK		 1050 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1051 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1052 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1053 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1054 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1055 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1056 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1057 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1058#ifdef CONFIG_X86_64
89a87c67
MK		 1059 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1060 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1061 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1062 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1063 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1064 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1065 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1066 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1067#endif
1068 default: BUG();
1069 }
1253791d
AK		 1070}
1071
1072static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1073 int reg)
1074{
1253791d 1075 switch (reg) {
89a87c67
MK		 1076 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1077 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1078 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1079 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1080 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1081 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1082 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1083 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1084#ifdef CONFIG_X86_64
89a87c67
MK		 1085 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1086 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1087 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1088 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1089 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1090 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1091 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1092 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1093#endif
1094 default: BUG();
1095 }
1253791d
AK		 1096}
1097
cbe2c9d3
AK		 1098static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1099{
cbe2c9d3
AK		 1100 switch (reg) {
1101 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1102 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1103 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1104 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1105 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1106 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1107 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1108 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1109 default: BUG();
1110 }
cbe2c9d3
AK		 1111}
1112
1113static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1114{
cbe2c9d3
AK		 1115 switch (reg) {
1116 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1117 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1118 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1119 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1120 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1121 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1122 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1123 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1124 default: BUG();
1125 }
cbe2c9d3
AK		 1126}
1127
045a282c
GN		 1128static int em_fninit(struct x86_emulate_ctxt *ctxt)
1129{
1130 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1131 return emulate_nm(ctxt);
1132
045a282c 1133 asm volatile("fninit");
045a282c
GN		 1134 return X86EMUL_CONTINUE;
1135}
1136
1137static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1138{
1139 u16 fcw;
1140
1141 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1142 return emulate_nm(ctxt);
1143
045a282c 1144 asm volatile("fnstcw %0": "+m"(fcw));
045a282c 1145
045a282c
GN		 1146 ctxt->dst.val = fcw;
1147
1148 return X86EMUL_CONTINUE;
1149}
1150
1151static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1152{
1153 u16 fsw;
1154
1155 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1156 return emulate_nm(ctxt);
1157
045a282c 1158 asm volatile("fnstsw %0": "+m"(fsw));
045a282c 1159
045a282c
GN		 1160 ctxt->dst.val = fsw;
1161
1162 return X86EMUL_CONTINUE;
1163}
1164
1253791d 1165static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1166 struct operand *op)
3c118e24 1167{
9dac77fa 1168 unsigned reg = ctxt->modrm_reg;
33615aa9 1169
9dac77fa
AK		 1170 if (!(ctxt->d & ModRM))
1171 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1172
9dac77fa 1173 if (ctxt->d & Sse) {
1253791d
AK		 1174 op->type = OP_XMM;
1175 op->bytes = 16;
1176 op->addr.xmm = reg;
1177 read_sse_reg(ctxt, &op->vec_val, reg);
1178 return;
1179 }
cbe2c9d3
AK		 1180 if (ctxt->d & Mmx) {
1181 reg &= 7;
1182 op->type = OP_MM;
1183 op->bytes = 8;
1184 op->addr.mm = reg;
1185 return;
1186 }
1253791d 1187
3c118e24 1188 op->type = OP_REG;
6d4d85ec
GN		 1189 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1190 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1191
91ff3cb4 1192 fetch_register_operand(op);
3c118e24
AK		 1193 op->orig_val = op->val;
1194}
1195
a6e3407b
AK		 1196static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1197{
1198 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1199 ctxt->modrm_seg = VCPU_SREG_SS;
1200}
1201
1c73ef66 1202static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1203 struct operand *op)
1c73ef66 1204{
1c73ef66 1205 u8 sib;
02357bdc 1206 int index_reg, base_reg, scale;
3e2815e9 1207 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1208 ulong modrm_ea = 0;
1c73ef66 1209
02357bdc
BD		 1210 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1211 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1212 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1213
02357bdc 1214 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1215 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1216 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1217 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1218
9b88ae99 1219 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1220 op->type = OP_REG;
9dac77fa 1221 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1222 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1223 ctxt->d & ByteOp);
9dac77fa 1224 if (ctxt->d & Sse) {
1253791d
AK		 1225 op->type = OP_XMM;
1226 op->bytes = 16;
9dac77fa
AK		 1227 op->addr.xmm = ctxt->modrm_rm;
1228 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1229 return rc;
1230 }
cbe2c9d3
AK		 1231 if (ctxt->d & Mmx) {
1232 op->type = OP_MM;
1233 op->bytes = 8;
bdc90722 1234 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1235 return rc;
1236 }
2dbd0dd7 1237 fetch_register_operand(op);
1c73ef66
AK		 1238 return rc;
1239 }
1240
2dbd0dd7
AK		 1241 op->type = OP_MEM;
1242
9dac77fa 1243 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1244 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1245 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1246 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1247 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1248
1249 /* 16-bit ModR/M decode. */
9dac77fa 1250 switch (ctxt->modrm_mod) {
1c73ef66 1251 case 0:
9dac77fa 1252 if (ctxt->modrm_rm == 6)
e85a1085 1253 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1254 break;
1255 case 1:
e85a1085 1256 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1257 break;
1258 case 2:
e85a1085 1259 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1260 break;
1261 }
9dac77fa 1262 switch (ctxt->modrm_rm) {
1c73ef66 1263 case 0:
2dbd0dd7 1264 modrm_ea += bx + si;
1c73ef66
AK		 1265 break;
1266 case 1:
2dbd0dd7 1267 modrm_ea += bx + di;
1c73ef66
AK		 1268 break;
1269 case 2:
2dbd0dd7 1270 modrm_ea += bp + si;
1c73ef66
AK		 1271 break;
1272 case 3:
2dbd0dd7 1273 modrm_ea += bp + di;
1c73ef66
AK		 1274 break;
1275 case 4:
2dbd0dd7 1276 modrm_ea += si;
1c73ef66
AK		 1277 break;
1278 case 5:
2dbd0dd7 1279 modrm_ea += di;
1c73ef66
AK		 1280 break;
1281 case 6:
9dac77fa 1282 if (ctxt->modrm_mod != 0)
2dbd0dd7 1283 modrm_ea += bp;
1c73ef66
AK		 1284 break;
1285 case 7:
2dbd0dd7 1286 modrm_ea += bx;
1c73ef66
AK		 1287 break;
1288 }
9dac77fa
AK		 1289 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1290 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1291 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1292 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1293 } else {
1294 /* 32/64-bit ModR/M decode. */
9dac77fa 1295 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1296 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1297 index_reg |= (sib >> 3) & 7;
1298 base_reg |= sib & 7;
1299 scale = sib >> 6;
1300
9dac77fa 1301 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1302 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1303 else {
dd856efa 1304 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1305 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1306 /* Increment ESP on POP [ESP] */
1307 if ((ctxt->d & IncSP) &&
1308 base_reg == VCPU_REGS_RSP)
1309 modrm_ea += ctxt->op_bytes;
a6e3407b 1310 }
dc71d0f1 1311 if (index_reg != 4)
dd856efa 1312 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1313 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1314 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1315 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1316 ctxt->rip_relative = 1;
a6e3407b
AK		 1317 } else {
1318 base_reg = ctxt->modrm_rm;
dd856efa 1319 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1320 adjust_modrm_seg(ctxt, base_reg);
1321 }
9dac77fa 1322 switch (ctxt->modrm_mod) {
1c73ef66 1323 case 1:
e85a1085 1324 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1325 break;
1326 case 2:
e85a1085 1327 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1328 break;
1329 }
1330 }
90de84f5 1331 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1332 if (ctxt->ad_bytes != 8)
1333 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1334
1c73ef66
AK		 1335done:
1336 return rc;
1337}
1338
1339static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1340 struct operand *op)
1c73ef66 1341{
3e2815e9 1342 int rc = X86EMUL_CONTINUE;
1c73ef66 1343
2dbd0dd7 1344 op->type = OP_MEM;
9dac77fa 1345 switch (ctxt->ad_bytes) {
1c73ef66 1346 case 2:
e85a1085 1347 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1348 break;
1349 case 4:
e85a1085 1350 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1351 break;
1352 case 8:
e85a1085 1353 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1354 break;
1355 }
1356done:
1357 return rc;
1358}
1359
9dac77fa 1360static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1361{
7129eeca 1362 long sv = 0, mask;
35c843c4 1363
9dac77fa 1364 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1365 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1366
9dac77fa
AK		 1367 if (ctxt->src.bytes == 2)
1368 sv = (s16)ctxt->src.val & (s16)mask;
1369 else if (ctxt->src.bytes == 4)
1370 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1371 else
1372 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1373
1c1c35ae
NA		 1374 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1375 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1376 }
ba7ff2b7
WY		 1377
1378 /* only subword offset */
9dac77fa 1379 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1380}
1381
dde7e6d1 1382static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1383 unsigned long addr, void *dest, unsigned size)
6aa8b732 1384{
dde7e6d1 1385 int rc;
9dac77fa 1386 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1387
f23b070e
XG		 1388 if (mc->pos < mc->end)
1389 goto read_cached;
6aa8b732 1390
f23b070e
XG		 1391 WARN_ON((mc->end + size) >= sizeof(mc->data));
1392
1393 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1394 &ctxt->exception);
1395 if (rc != X86EMUL_CONTINUE)
1396 return rc;
1397
1398 mc->end += size;
1399
1400read_cached:
1401 memcpy(dest, mc->data + mc->pos, size);
1402 mc->pos += size;
dde7e6d1
AK		 1403 return X86EMUL_CONTINUE;
1404}
6aa8b732 1405
3ca3ac4d
AK		 1406static int segmented_read(struct x86_emulate_ctxt *ctxt,
1407 struct segmented_address addr,
1408 void *data,
1409 unsigned size)
1410{
9fa088f4
AK		 1411 int rc;
1412 ulong linear;
1413
83b8795a 1414 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1415 if (rc != X86EMUL_CONTINUE)
1416 return rc;
7b105ca2 1417 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1418}
1419
1420static int segmented_write(struct x86_emulate_ctxt *ctxt,
1421 struct segmented_address addr,
1422 const void *data,
1423 unsigned size)
1424{
9fa088f4
AK		 1425 int rc;
1426 ulong linear;
1427
83b8795a 1428 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1429 if (rc != X86EMUL_CONTINUE)
1430 return rc;
0f65dd70
AK		 1431 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1432 &ctxt->exception);
3ca3ac4d
AK		 1433}
1434
1435static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1436 struct segmented_address addr,
1437 const void *orig_data, const void *data,
1438 unsigned size)
1439{
9fa088f4
AK		 1440 int rc;
1441 ulong linear;
1442
83b8795a 1443 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1444 if (rc != X86EMUL_CONTINUE)
1445 return rc;
0f65dd70
AK		 1446 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1447 size, &ctxt->exception);
3ca3ac4d
AK		 1448}
1449
dde7e6d1 1450static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1451 unsigned int size, unsigned short port,
1452 void *dest)
1453{
9dac77fa 1454 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1455
dde7e6d1 1456 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1457 unsigned int in_page, n;
9dac77fa 1458 unsigned int count = ctxt->rep_prefix ?
dd856efa 1459 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1460 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1461 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1462 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1463 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1464 if (n == 0)
1465 n = 1;
1466 rc->pos = rc->end = 0;
7b105ca2 1467 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1468 return 0;
1469 rc->end = n * size;
6aa8b732
AK		 1470 }
1471
e6e39f04 1472 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1473 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1474 ctxt->dst.data = rc->data + rc->pos;
1475 ctxt->dst.type = OP_MEM_STR;
1476 ctxt->dst.count = (rc->end - rc->pos) / size;
1477 rc->pos = rc->end;
1478 } else {
1479 memcpy(dest, rc->data + rc->pos, size);
1480 rc->pos += size;
1481 }
dde7e6d1
AK		 1482 return 1;
1483}
6aa8b732 1484
7f3d35fd
KW		 1485static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1486 u16 index, struct desc_struct *desc)
1487{
1488 struct desc_ptr dt;
1489 ulong addr;
1490
1491 ctxt->ops->get_idt(ctxt, &dt);
1492
1493 if (dt.size < index * 8 + 7)
1494 return emulate_gp(ctxt, index << 3 | 0x2);
1495
1496 addr = dt.address + index * 8;
1497 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1498 &ctxt->exception);
1499}
1500
dde7e6d1 1501static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1502 u16 selector, struct desc_ptr *dt)
1503{
0225fb50 1504 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1505 u32 base3 = 0;
7b105ca2 1506
dde7e6d1
AK		 1507 if (selector & 1 << 2) {
1508 struct desc_struct desc;
1aa36616
AK		 1509 u16 sel;
1510
dde7e6d1 1511 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1512 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1513 VCPU_SREG_LDTR))
dde7e6d1 1514 return;
e09d082c 1515
dde7e6d1 1516 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1517 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1518 } else
4bff1e86 1519 ops->get_gdt(ctxt, dt);
dde7e6d1 1520}
120df890 1521
edccda7c
NA		 1522static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1523 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1524{
1525 struct desc_ptr dt;
1526 u16 index = selector >> 3;
dde7e6d1 1527 ulong addr;
120df890 1528
7b105ca2 1529 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1530
35d3d4a1
AK		 1531 if (dt.size < index * 8 + 7)
1532 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1533
edccda7c
NA		 1534 addr = dt.address + index * 8;
1535
1536#ifdef CONFIG_X86_64
1537 if (addr >> 32 != 0) {
1538 u64 efer = 0;
1539
1540 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1541 if (!(efer & EFER_LMA))
1542 addr &= (u32)-1;
1543 }
1544#endif
1545
1546 *desc_addr_p = addr;
1547 return X86EMUL_CONTINUE;
1548}
1549
1550/* allowed just for 8 bytes segments */
1551static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1552 u16 selector, struct desc_struct *desc,
1553 ulong *desc_addr_p)
1554{
1555 int rc;
1556
1557 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1558 if (rc != X86EMUL_CONTINUE)
1559 return rc;
1560
1561 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1562 &ctxt->exception);
dde7e6d1 1563}
ef65c889 1564
dde7e6d1
AK		 1565/* allowed just for 8 bytes segments */
1566static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1567 u16 selector, struct desc_struct *desc)
1568{
edccda7c 1569 int rc;
dde7e6d1 1570 ulong addr;
6aa8b732 1571
edccda7c
NA		 1572 rc = get_descriptor_ptr(ctxt, selector, &addr);
1573 if (rc != X86EMUL_CONTINUE)
1574 return rc;
6aa8b732 1575
7b105ca2
TY		 1576 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1577 &ctxt->exception);
dde7e6d1 1578}
c7e75a3d 1579
2356aaeb 1580static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1581 u16 selector, int seg, u8 cpl,
3dc4bc4f 1582 enum x86_transfer_type transfer,
d1442d85 1583 struct desc_struct *desc)
dde7e6d1 1584{
869be99c 1585 struct desc_struct seg_desc, old_desc;
2356aaeb 1586 u8 dpl, rpl;
dde7e6d1
AK		 1587 unsigned err_vec = GP_VECTOR;
1588 u32 err_code = 0;
1589 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1590 ulong desc_addr;
dde7e6d1 1591 int ret;
03ebebeb 1592 u16 dummy;
e37a75a1 1593 u32 base3 = 0;
69f55cb1 1594
dde7e6d1 1595 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1596
f8da94e9
KW		 1597 if (ctxt->mode == X86EMUL_MODE_REAL) {
1598 /* set real mode segment descriptor (keep limit etc. for
1599 * unreal mode) */
03ebebeb 1600 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1601 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1602 goto load;
f8da94e9
KW		 1603 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1604 /* VM86 needs a clean new segment descriptor */
1605 set_desc_base(&seg_desc, selector << 4);
1606 set_desc_limit(&seg_desc, 0xffff);
1607 seg_desc.type = 3;
1608 seg_desc.p = 1;
1609 seg_desc.s = 1;
1610 seg_desc.dpl = 3;
1611 goto load;
dde7e6d1
AK		 1612 }
1613
79d5b4c3 1614 rpl = selector & 3;
79d5b4c3 1615
dde7e6d1
AK		 1616 /* TR should be in GDT only */
1617 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1618 goto exception;
1619
33ab9110
PB		 1620 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1621 if (null_selector) {
1622 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1623 goto exception;
1624
1625 if (seg == VCPU_SREG_SS) {
1626 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1627 goto exception;
1628
1629 /*
1630 * ctxt->ops->set_segment expects the CPL to be in
1631 * SS.DPL, so fake an expand-up 32-bit data segment.
1632 */
1633 seg_desc.type = 3;
1634 seg_desc.p = 1;
1635 seg_desc.s = 1;
1636 seg_desc.dpl = cpl;
1637 seg_desc.d = 1;
1638 seg_desc.g = 1;
1639 }
1640
1641 /* Skip all following checks */
dde7e6d1 1642 goto load;
33ab9110 1643 }
dde7e6d1 1644
e919464b 1645 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1646 if (ret != X86EMUL_CONTINUE)
1647 return ret;
1648
1649 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1650 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1651 GP_VECTOR;
dde7e6d1 1652
fc058680 1653 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1654 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1655 if (transfer == X86_TRANSFER_CALL_JMP)
1656 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1657 goto exception;
3dc4bc4f 1658 }
dde7e6d1
AK		 1659
1660 if (!seg_desc.p) {
1661 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1662 goto exception;
1663 }
1664
dde7e6d1 1665 dpl = seg_desc.dpl;
dde7e6d1
AK		 1666
1667 switch (seg) {
1668 case VCPU_SREG_SS:
1669 /*
1670 * segment is not a writable data segment or segment
1671 * selector's RPL != CPL or segment selector's RPL != CPL
1672 */
1673 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1674 goto exception;
6aa8b732 1675 break;
dde7e6d1
AK		 1676 case VCPU_SREG_CS:
1677 if (!(seg_desc.type & 8))
1678 goto exception;
1679
1680 if (seg_desc.type & 4) {
1681 /* conforming */
1682 if (dpl > cpl)
1683 goto exception;
1684 } else {
1685 /* nonconforming */
1686 if (rpl > cpl || dpl != cpl)
1687 goto exception;
1688 }
040c8dc8
NA		 1689 /* in long-mode d/b must be clear if l is set */
1690 if (seg_desc.d && seg_desc.l) {
1691 u64 efer = 0;
1692
1693 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1694 if (efer & EFER_LMA)
1695 goto exception;
1696 }
1697
dde7e6d1
AK		 1698 /* CS(RPL) <- CPL */
1699 selector = (selector & 0xfffc) | cpl;
6aa8b732 1700 break;
dde7e6d1
AK		 1701 case VCPU_SREG_TR:
1702 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1703 goto exception;
869be99c
AK		 1704 old_desc = seg_desc;
1705 seg_desc.type |= 2; /* busy */
1706 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1707 sizeof(seg_desc), &ctxt->exception);
1708 if (ret != X86EMUL_CONTINUE)
1709 return ret;
dde7e6d1
AK		 1710 break;
1711 case VCPU_SREG_LDTR:
1712 if (seg_desc.s || seg_desc.type != 2)
1713 goto exception;
1714 break;
1715 default: /* DS, ES, FS, or GS */
4e62417b 1716 /*
dde7e6d1
AK		 1717 * segment is not a data or readable code segment or
1718 * ((segment is a data or nonconforming code segment)
1719 * and (both RPL and CPL > DPL))
4e62417b 1720 */
dde7e6d1
AK		 1721 if ((seg_desc.type & 0xa) == 0x8 ||
1722 (((seg_desc.type & 0xc) != 0xc) &&
1723 (rpl > dpl && cpl > dpl)))
1724 goto exception;
6aa8b732 1725 break;
dde7e6d1
AK		 1726 }
1727
1728 if (seg_desc.s) {
1729 /* mark segment as accessed */
e2cefa74
NA		 1730 if (!(seg_desc.type & 1)) {
1731 seg_desc.type |= 1;
1732 ret = write_segment_descriptor(ctxt, selector,
1733 &seg_desc);
1734 if (ret != X86EMUL_CONTINUE)
1735 return ret;
1736 }
e37a75a1
NA		 1737 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1738 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1739 sizeof(base3), &ctxt->exception);
1740 if (ret != X86EMUL_CONTINUE)
1741 return ret;
fd8cb433
YZ		 1742 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
1743 ((u64)base3 << 32), ctxt))
9a9abf6b 1744 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1745 }
1746load:
e37a75a1 1747 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1748 if (desc)
1749 *desc = seg_desc;
dde7e6d1
AK		 1750 return X86EMUL_CONTINUE;
1751exception:
592f0858 1752 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1753}
1754
2356aaeb
PB		 1755static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1756 u16 selector, int seg)
1757{
1758 u8 cpl = ctxt->ops->cpl(ctxt);
33ab9110
PB		 1759
1760 /*
1761 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1762 * they can load it at CPL<3 (Intel's manual says only LSS can,
1763 * but it's wrong).
1764 *
1765 * However, the Intel manual says that putting IST=1/DPL=3 in
1766 * an interrupt gate will result in SS=3 (the AMD manual instead
1767 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1768 * and only forbid it here.
1769 */
1770 if (seg == VCPU_SREG_SS && selector == 3 &&
1771 ctxt->mode == X86EMUL_MODE_PROT64)
1772 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1773
3dc4bc4f
NA		 1774 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1775 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1776}
1777
31be40b3
WY		 1778static void write_register_operand(struct operand *op)
1779{
6fd8e127 1780 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1781}
1782
fb32b1ed 1783static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1784{
fb32b1ed 1785 switch (op->type) {
dde7e6d1 1786 case OP_REG:
fb32b1ed 1787 write_register_operand(op);
6aa8b732 1788 break;
dde7e6d1 1789 case OP_MEM:
9dac77fa 1790 if (ctxt->lock_prefix)
f5f87dfb
PB		 1791 return segmented_cmpxchg(ctxt,
1792 op->addr.mem,
1793 &op->orig_val,
1794 &op->val,
1795 op->bytes);
1796 else
1797 return segmented_write(ctxt,
fb32b1ed 1798 op->addr.mem,
fb32b1ed
AK		 1799 &op->val,
1800 op->bytes);
a682e354 1801 break;
b3356bf0 1802 case OP_MEM_STR:
f5f87dfb
PB		 1803 return segmented_write(ctxt,
1804 op->addr.mem,
1805 op->data,
1806 op->bytes * op->count);
b3356bf0 1807 break;
1253791d 1808 case OP_XMM:
fb32b1ed 1809 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1810 break;
cbe2c9d3 1811 case OP_MM:
fb32b1ed 1812 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1813 break;
dde7e6d1
AK		 1814 case OP_NONE:
1815 /* no writeback */
414e6277 1816 break;
dde7e6d1 1817 default:
414e6277 1818 break;
6aa8b732 1819 }
dde7e6d1
AK		 1820 return X86EMUL_CONTINUE;
1821}
6aa8b732 1822
51ddff50 1823static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1824{
4179bb02 1825 struct segmented_address addr;
0dc8d10f 1826
5ad105e5 1827 rsp_increment(ctxt, -bytes);
dd856efa 1828 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1829 addr.seg = VCPU_SREG_SS;
1830
51ddff50
AK		 1831 return segmented_write(ctxt, addr, data, bytes);
1832}
1833
1834static int em_push(struct x86_emulate_ctxt *ctxt)
1835{
4179bb02 1836 /* Disable writeback. */
9dac77fa 1837 ctxt->dst.type = OP_NONE;
51ddff50 1838 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1839}
69f55cb1 1840
dde7e6d1 1841static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1842 void *dest, int len)
1843{
dde7e6d1 1844 int rc;
90de84f5 1845 struct segmented_address addr;
8b4caf66 1846
dd856efa 1847 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1848 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1849 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1850 if (rc != X86EMUL_CONTINUE)
1851 return rc;
1852
5ad105e5 1853 rsp_increment(ctxt, len);
dde7e6d1 1854 return rc;
8b4caf66
LV		 1855}
1856
c54fe504
TY		 1857static int em_pop(struct x86_emulate_ctxt *ctxt)
1858{
9dac77fa 1859 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1860}
1861
dde7e6d1 1862static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1863 void *dest, int len)
9de41573
GN		 1864{
1865 int rc;
dde7e6d1 1866 unsigned long val, change_mask;
0efb0440 1867 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1868 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1869
3b9be3bf 1870 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1871 if (rc != X86EMUL_CONTINUE)
1872 return rc;
9de41573 1873
0efb0440
NA		 1874 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1875 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1876 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1877 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1878
dde7e6d1
AK		 1879 switch(ctxt->mode) {
1880 case X86EMUL_MODE_PROT64:
1881 case X86EMUL_MODE_PROT32:
1882 case X86EMUL_MODE_PROT16:
1883 if (cpl == 0)
0efb0440 1884 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1885 if (cpl <= iopl)
0efb0440 1886 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1887 break;
1888 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1889 if (iopl < 3)
1890 return emulate_gp(ctxt, 0);
0efb0440 1891 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1892 break;
1893 default: /* real mode */
0efb0440 1894 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1895 break;
9de41573 1896 }
dde7e6d1
AK		 1897
1898 *(unsigned long *)dest =
1899 (ctxt->eflags & ~change_mask) | (val & change_mask);
1900
1901 return rc;
9de41573
GN		 1902}
1903
62aaa2f0
TY		 1904static int em_popf(struct x86_emulate_ctxt *ctxt)
1905{
9dac77fa
AK		 1906 ctxt->dst.type = OP_REG;
1907 ctxt->dst.addr.reg = &ctxt->eflags;
1908 ctxt->dst.bytes = ctxt->op_bytes;
1909 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1910}
1911
612e89f0
AK		 1912static int em_enter(struct x86_emulate_ctxt *ctxt)
1913{
1914 int rc;
1915 unsigned frame_size = ctxt->src.val;
1916 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1917 ulong rbp;
612e89f0
AK		 1918
1919 if (nesting_level)
1920 return X86EMUL_UNHANDLEABLE;
1921
dd856efa
AK		 1922 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1923 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1924 if (rc != X86EMUL_CONTINUE)
1925 return rc;
dd856efa 1926 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1927 stack_mask(ctxt));
dd856efa
AK		 1928 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1929 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1930 stack_mask(ctxt));
1931 return X86EMUL_CONTINUE;
1932}
1933
f47cfa31
AK		 1934static int em_leave(struct x86_emulate_ctxt *ctxt)
1935{
dd856efa 1936 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1937 stack_mask(ctxt));
dd856efa 1938 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1939}
1940
1cd196ea 1941static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1942{
1cd196ea
AK		 1943 int seg = ctxt->src2.val;
1944
9dac77fa 1945 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1946 if (ctxt->op_bytes == 4) {
1947 rsp_increment(ctxt, -2);
1948 ctxt->op_bytes = 2;
1949 }
7b262e90 1950
4487b3b4 1951 return em_push(ctxt);
7b262e90
GN		 1952}
1953
1cd196ea 1954static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1955{
1cd196ea 1956 int seg = ctxt->src2.val;
dde7e6d1
AK		 1957 unsigned long selector;
1958 int rc;
38ba30ba 1959
3313bc4e 1960 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1961 if (rc != X86EMUL_CONTINUE)
1962 return rc;
1963
a5457e7b
PB		 1964 if (ctxt->modrm_reg == VCPU_SREG_SS)
1965 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1966 if (ctxt->op_bytes > 2)
1967 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1968
7b105ca2 1969 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1970 return rc;
38ba30ba
GN		 1971}
1972
b96a7fad 1973static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1974{
dd856efa 1975 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1976 int rc = X86EMUL_CONTINUE;
1977 int reg = VCPU_REGS_RAX;
38ba30ba 1978
dde7e6d1
AK		 1979 while (reg <= VCPU_REGS_RDI) {
1980 (reg == VCPU_REGS_RSP) ?
dd856efa 1981 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1982
4487b3b4 1983 rc = em_push(ctxt);
dde7e6d1
AK		 1984 if (rc != X86EMUL_CONTINUE)
1985 return rc;
38ba30ba 1986
dde7e6d1 1987 ++reg;
38ba30ba 1988 }
38ba30ba 1989
dde7e6d1 1990 return rc;
38ba30ba
GN		 1991}
1992
62aaa2f0
TY		 1993static int em_pushf(struct x86_emulate_ctxt *ctxt)
1994{
0efb0440 1995 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 1996 return em_push(ctxt);
1997}
1998
b96a7fad 1999static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 2000{
dde7e6d1
AK		 2001 int rc = X86EMUL_CONTINUE;
2002 int reg = VCPU_REGS_RDI;
6fd8e127 2003 u32 val;
38ba30ba 2004
dde7e6d1
AK		 2005 while (reg >= VCPU_REGS_RAX) {
2006 if (reg == VCPU_REGS_RSP) {
5ad105e5 2007 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 2008 --reg;
2009 }
38ba30ba 2010
6fd8e127 2011 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 2012 if (rc != X86EMUL_CONTINUE)
2013 break;
6fd8e127 2014 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 2015 --reg;
38ba30ba 2016 }
dde7e6d1 2017 return rc;
38ba30ba
GN		 2018}
2019
dd856efa 2020static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 2021{
0225fb50 2022 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 2023 int rc;
6e154e56
MG		 2024 struct desc_ptr dt;
2025 gva_t cs_addr;
2026 gva_t eip_addr;
2027 u16 cs, eip;
6e154e56
MG		 2028
2029 /* TODO: Add limit checks */
9dac77fa 2030 ctxt->src.val = ctxt->eflags;
4487b3b4 2031 rc = em_push(ctxt);
5c56e1cf
AK		 2032 if (rc != X86EMUL_CONTINUE)
2033 return rc;
6e154e56 2034
0efb0440 2035 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2036
9dac77fa 2037 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2038 rc = em_push(ctxt);
5c56e1cf
AK		 2039 if (rc != X86EMUL_CONTINUE)
2040 return rc;
6e154e56 2041
9dac77fa 2042 ctxt->src.val = ctxt->_eip;
4487b3b4 2043 rc = em_push(ctxt);
5c56e1cf
AK		 2044 if (rc != X86EMUL_CONTINUE)
2045 return rc;
2046
4bff1e86 2047 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2048
2049 eip_addr = dt.address + (irq << 2);
2050 cs_addr = dt.address + (irq << 2) + 2;
2051
0f65dd70 2052 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 2053 if (rc != X86EMUL_CONTINUE)
2054 return rc;
2055
0f65dd70 2056 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 2057 if (rc != X86EMUL_CONTINUE)
2058 return rc;
2059
7b105ca2 2060 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2061 if (rc != X86EMUL_CONTINUE)
2062 return rc;
2063
9dac77fa 2064 ctxt->_eip = eip;
6e154e56
MG		 2065
2066 return rc;
2067}
2068
dd856efa
AK		 2069int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2070{
2071 int rc;
2072
2073 invalidate_registers(ctxt);
2074 rc = __emulate_int_real(ctxt, irq);
2075 if (rc == X86EMUL_CONTINUE)
2076 writeback_registers(ctxt);
2077 return rc;
2078}
2079
7b105ca2 2080static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2081{
2082 switch(ctxt->mode) {
2083 case X86EMUL_MODE_REAL:
dd856efa 2084 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2085 case X86EMUL_MODE_VM86:
2086 case X86EMUL_MODE_PROT16:
2087 case X86EMUL_MODE_PROT32:
2088 case X86EMUL_MODE_PROT64:
2089 default:
2090 /* Protected mode interrupts unimplemented yet */
2091 return X86EMUL_UNHANDLEABLE;
2092 }
2093}
2094
7b105ca2 2095static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2096{
dde7e6d1
AK		 2097 int rc = X86EMUL_CONTINUE;
2098 unsigned long temp_eip = 0;
2099 unsigned long temp_eflags = 0;
2100 unsigned long cs = 0;
0efb0440
NA		 2101 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2102 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2103 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2104 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2105 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2106 X86_EFLAGS_FIXED;
0efb0440
NA		 2107 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2108 X86_EFLAGS_VIP;
38ba30ba 2109
dde7e6d1 2110 /* TODO: Add stack limit check */
38ba30ba 2111
9dac77fa 2112 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2113
dde7e6d1
AK		 2114 if (rc != X86EMUL_CONTINUE)
2115 return rc;
38ba30ba 2116
35d3d4a1
AK		 2117 if (temp_eip & ~0xffff)
2118 return emulate_gp(ctxt, 0);
38ba30ba 2119
9dac77fa 2120 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2121
dde7e6d1
AK		 2122 if (rc != X86EMUL_CONTINUE)
2123 return rc;
38ba30ba 2124
9dac77fa 2125 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2126
dde7e6d1
AK		 2127 if (rc != X86EMUL_CONTINUE)
2128 return rc;
38ba30ba 2129
7b105ca2 2130 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2131
dde7e6d1
AK		 2132 if (rc != X86EMUL_CONTINUE)
2133 return rc;
38ba30ba 2134
9dac77fa 2135 ctxt->_eip = temp_eip;
38ba30ba 2136
9dac77fa 2137 if (ctxt->op_bytes == 4)
dde7e6d1 2138 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2139 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2140 ctxt->eflags &= ~0xffff;
2141 ctxt->eflags |= temp_eflags;
38ba30ba 2142 }
dde7e6d1
AK		 2143
2144 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2145 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2146 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2147
2148 return rc;
38ba30ba
GN		 2149}
2150
e01991e7 2151static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2152{
dde7e6d1
AK		 2153 switch(ctxt->mode) {
2154 case X86EMUL_MODE_REAL:
7b105ca2 2155 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2156 case X86EMUL_MODE_VM86:
2157 case X86EMUL_MODE_PROT16:
2158 case X86EMUL_MODE_PROT32:
2159 case X86EMUL_MODE_PROT64:
c37eda13 2160 default:
dde7e6d1
AK		 2161 /* iret from protected mode unimplemented yet */
2162 return X86EMUL_UNHANDLEABLE;
c37eda13 2163 }
c37eda13
WY		 2164}
2165
d2f62766
TY		 2166static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2167{
d2f62766 2168 int rc;
2117d539
RK		 2169 unsigned short sel;
2170 struct desc_struct new_desc;
d1442d85
NA		 2171 u8 cpl = ctxt->ops->cpl(ctxt);
2172
9dac77fa 2173 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2174
3dc4bc4f
NA		 2175 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2176 X86_TRANSFER_CALL_JMP,
d1442d85 2177 &new_desc);
d2f62766
TY		 2178 if (rc != X86EMUL_CONTINUE)
2179 return rc;
2180
d50eaa18 2181 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2117d539
RK		 2182 /* Error handling is not implemented. */
2183 if (rc != X86EMUL_CONTINUE)
2184 return X86EMUL_UNHANDLEABLE;
2185
d1442d85 2186 return rc;
d2f62766
TY		 2187}
2188
f7784046 2189static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2190{
f7784046
NA		 2191 return assign_eip_near(ctxt, ctxt->src.val);
2192}
8cdbd2c9 2193
f7784046
NA		 2194static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2195{
2196 int rc;
2197 long int old_eip;
2198
2199 old_eip = ctxt->_eip;
2200 rc = assign_eip_near(ctxt, ctxt->src.val);
2201 if (rc != X86EMUL_CONTINUE)
2202 return rc;
2203 ctxt->src.val = old_eip;
2204 rc = em_push(ctxt);
4179bb02 2205 return rc;
8cdbd2c9
LV		 2206}
2207
e0dac408 2208static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2209{
9dac77fa 2210 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2211
aaa05f24
NA		 2212 if (ctxt->dst.bytes == 16)
2213 return X86EMUL_UNHANDLEABLE;
2214
dd856efa
AK		 2215 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2216 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2217 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2218 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2219 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2220 } else {
dd856efa
AK		 2221 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2222 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2223
0efb0440 2224 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2225 }
1b30eaa8 2226 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2227}
2228
ebda02c2
TY		 2229static int em_ret(struct x86_emulate_ctxt *ctxt)
2230{
234f3ce4
NA		 2231 int rc;
2232 unsigned long eip;
2233
2234 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2235 if (rc != X86EMUL_CONTINUE)
2236 return rc;
2237
2238 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2239}
2240
e01991e7 2241static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2242{
a77ab5ea 2243 int rc;
d1442d85 2244 unsigned long eip, cs;
9e8919ae 2245 int cpl = ctxt->ops->cpl(ctxt);
2117d539 2246 struct desc_struct new_desc;
a77ab5ea 2247
d1442d85 2248 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2249 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2250 return rc;
9dac77fa 2251 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2252 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2253 return rc;
9e8919ae
NA		 2254 /* Outer-privilege level return is not implemented */
2255 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2256 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2257 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2258 X86_TRANSFER_RET,
d1442d85
NA		 2259 &new_desc);
2260 if (rc != X86EMUL_CONTINUE)
2261 return rc;
d50eaa18 2262 rc = assign_eip_far(ctxt, eip, &new_desc);
2117d539
RK		 2263 /* Error handling is not implemented. */
2264 if (rc != X86EMUL_CONTINUE)
2265 return X86EMUL_UNHANDLEABLE;
2266
a77ab5ea
AK		 2267 return rc;
2268}
2269
3261107e
BR		 2270static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2271{
2272 int rc;
2273
2274 rc = em_ret_far(ctxt);
2275 if (rc != X86EMUL_CONTINUE)
2276 return rc;
2277 rsp_increment(ctxt, ctxt->src.val);
2278 return X86EMUL_CONTINUE;
2279}
2280
e940b5c2
TY		 2281static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2282{
2283 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2284 ctxt->dst.orig_val = ctxt->dst.val;
2285 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2286 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2287 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2288 fastop(ctxt, em_cmp);
e940b5c2 2289
0efb0440 2290 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2291 /* Success: write back to memory; no update of EAX */
2292 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2293 ctxt->dst.val = ctxt->src.orig_val;
2294 } else {
2295 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2296 ctxt->src.type = OP_REG;
2297 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2298 ctxt->src.val = ctxt->dst.orig_val;
2299 /* Create write-cycle to dest by writing the same value */
37c564f2 2300 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2301 }
2302 return X86EMUL_CONTINUE;
2303}
2304
d4b4325f 2305static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2306{
d4b4325f 2307 int seg = ctxt->src2.val;
09b5f4d3
WY		 2308 unsigned short sel;
2309 int rc;
2310
9dac77fa 2311 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2312
7b105ca2 2313 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2314 if (rc != X86EMUL_CONTINUE)
2315 return rc;
2316
9dac77fa 2317 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2318 return rc;
2319}
2320
660a5d51
PB		 2321static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2322{
2323 u32 eax, ebx, ecx, edx;
2324
2325 eax = 0x80000001;
2326 ecx = 0;
e911eb3b 2327 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
660a5d51
PB		 2328 return edx & bit(X86_FEATURE_LM);
2329}
2330
2331#define GET_SMSTATE(type, smbase, offset) \
2332 ({ \
2333 type __val; \
f40606b1
RK		 2334 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \
2335 sizeof(__val)); \
660a5d51
PB		 2336 if (r != X86EMUL_CONTINUE) \
2337 return X86EMUL_UNHANDLEABLE; \
2338 __val; \
2339 })
2340
2341static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2342{
2343 desc->g = (flags >> 23) & 1;
2344 desc->d = (flags >> 22) & 1;
2345 desc->l = (flags >> 21) & 1;
2346 desc->avl = (flags >> 20) & 1;
2347 desc->p = (flags >> 15) & 1;
2348 desc->dpl = (flags >> 13) & 3;
2349 desc->s = (flags >> 12) & 1;
2350 desc->type = (flags >> 8) & 15;
2351}
2352
2353static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2354{
2355 struct desc_struct desc;
2356 int offset;
2357 u16 selector;
2358
2359 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2360
2361 if (n < 3)
2362 offset = 0x7f84 + n * 12;
2363 else
2364 offset = 0x7f2c + (n - 3) * 12;
2365
2366 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2367 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2368 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2369 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2370 return X86EMUL_CONTINUE;
2371}
2372
2373static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2374{
2375 struct desc_struct desc;
2376 int offset;
2377 u16 selector;
2378 u32 base3;
2379
2380 offset = 0x7e00 + n * 16;
2381
2382 selector = GET_SMSTATE(u16, smbase, offset);
2383 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2384 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2385 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2386 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2387
2388 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2389 return X86EMUL_CONTINUE;
2390}
2391
2392static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
fae1a3e7 2393 u64 cr0, u64 cr3, u64 cr4)
660a5d51
PB		 2394{
2395 int bad;
fae1a3e7
PB		 2396 u64 pcid;
2397
2398 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */
2399 pcid = 0;
2400 if (cr4 & X86_CR4_PCIDE) {
2401 pcid = cr3 & 0xfff;
2402 cr3 &= ~0xfff;
2403 }
2404
2405 bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2406 if (bad)
2407 return X86EMUL_UNHANDLEABLE;
660a5d51
PB		 2408
2409 /*
2410 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2411 * Then enable protected mode. However, PCID cannot be enabled
2412 * if EFER.LMA=0, so set it separately.
2413 */
2414 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2415 if (bad)
2416 return X86EMUL_UNHANDLEABLE;
2417
2418 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2419 if (bad)
2420 return X86EMUL_UNHANDLEABLE;
2421
2422 if (cr4 & X86_CR4_PCIDE) {
2423 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2424 if (bad)
2425 return X86EMUL_UNHANDLEABLE;
fae1a3e7
PB		 2426 if (pcid) {
2427 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2428 if (bad)
2429 return X86EMUL_UNHANDLEABLE;
2430 }
2431
660a5d51
PB		 2432 }
2433
2434 return X86EMUL_CONTINUE;
2435}
2436
2437static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2438{
2439 struct desc_struct desc;
2440 struct desc_ptr dt;
2441 u16 selector;
fae1a3e7 2442 u32 val, cr0, cr3, cr4;
660a5d51
PB		 2443 int i;
2444
2445 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
fae1a3e7 2446 cr3 = GET_SMSTATE(u32, smbase, 0x7ff8);
660a5d51
PB		 2447 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2448 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2449
2450 for (i = 0; i < 8; i++)
2451 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2452
2453 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2454 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2455 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2456 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2457
2458 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2459 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2460 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2461 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2462 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2463
2464 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2465 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2466 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2467 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2468 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2469
2470 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2471 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2472 ctxt->ops->set_gdt(ctxt, &dt);
2473
2474 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2475 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2476 ctxt->ops->set_idt(ctxt, &dt);
2477
2478 for (i = 0; i < 6; i++) {
2479 int r = rsm_load_seg_32(ctxt, smbase, i);
2480 if (r != X86EMUL_CONTINUE)
2481 return r;
2482 }
2483
2484 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2485
2486 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2487
fae1a3e7 2488 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
660a5d51
PB		 2489}
2490
2491static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2492{
2493 struct desc_struct desc;
2494 struct desc_ptr dt;
fae1a3e7 2495 u64 val, cr0, cr3, cr4;
660a5d51
PB		 2496 u32 base3;
2497 u16 selector;
b10d92a5 2498 int i, r;
660a5d51
PB		 2499
2500 for (i = 0; i < 16; i++)
2501 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2502
2503 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2504 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2505
2506 val = GET_SMSTATE(u32, smbase, 0x7f68);
2507 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2508 val = GET_SMSTATE(u32, smbase, 0x7f60);
2509 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2510
2511 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
fae1a3e7 2512 cr3 = GET_SMSTATE(u64, smbase, 0x7f50);
660a5d51
PB		 2513 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2514 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2515 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2516 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2517
2518 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2519 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2520 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2521 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2522 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2523 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2524
2525 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2526 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2527 ctxt->ops->set_idt(ctxt, &dt);
2528
2529 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2530 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2531 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2532 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2533 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2534 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2535
2536 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2537 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2538 ctxt->ops->set_gdt(ctxt, &dt);
2539
fae1a3e7 2540 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
b10d92a5
PB		 2541 if (r != X86EMUL_CONTINUE)
2542 return r;
2543
660a5d51 2544 for (i = 0; i < 6; i++) {
b10d92a5 2545 r = rsm_load_seg_64(ctxt, smbase, i);
660a5d51
PB		 2546 if (r != X86EMUL_CONTINUE)
2547 return r;
2548 }
2549
b10d92a5 2550 return X86EMUL_CONTINUE;
660a5d51
PB		 2551}
2552
64d60670
PB		 2553static int em_rsm(struct x86_emulate_ctxt *ctxt)
2554{
660a5d51
PB		 2555 unsigned long cr0, cr4, efer;
2556 u64 smbase;
2557 int ret;
2558
6ed071f0 2559 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
64d60670
PB		 2560 return emulate_ud(ctxt);
2561
660a5d51
PB		 2562 /*
2563 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2564 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2565 * supports long mode.
660a5d51 2566 */
89651a3d
PB		 2567 cr4 = ctxt->ops->get_cr(ctxt, 4);
2568 if (emulator_has_longmode(ctxt)) {
2569 struct desc_struct cs_desc;
2570
2571 /* Zero CR4.PCIDE before CR0.PG. */
2572 if (cr4 & X86_CR4_PCIDE) {
2573 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2574 cr4 &= ~X86_CR4_PCIDE;
2575 }
2576
2577 /* A 32-bit code segment is required to clear EFER.LMA. */
2578 memset(&cs_desc, 0, sizeof(cs_desc));
2579 cs_desc.type = 0xb;
2580 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2581 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2582 }
2583
2584 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2585 cr0 = ctxt->ops->get_cr(ctxt, 0);
2586 if (cr0 & X86_CR0_PE)
2587 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d
PB		 2588
2589 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
660a5d51
PB		 2590 if (cr4 & X86_CR4_PAE)
2591 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
89651a3d
PB		 2592
2593 /* And finally go back to 32-bit mode. */
660a5d51
PB		 2594 efer = 0;
2595 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2596
2597 smbase = ctxt->ops->get_smbase(ctxt);
0234bf88
LP		 2598
2599 /*
2600 * Give pre_leave_smm() a chance to make ISA-specific changes to the
2601 * vCPU state (e.g. enter guest mode) before loading state from the SMM
2602 * state-save area.
2603 */
2604 if (ctxt->ops->pre_leave_smm(ctxt, smbase))
2605 return X86EMUL_UNHANDLEABLE;
2606
660a5d51
PB		 2607 if (emulator_has_longmode(ctxt))
2608 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2609 else
2610 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2611
2612 if (ret != X86EMUL_CONTINUE) {
2613 /* FIXME: should triple fault */
2614 return X86EMUL_UNHANDLEABLE;
2615 }
2616
6ed071f0 2617 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
660a5d51
PB		 2618 ctxt->ops->set_nmi_mask(ctxt, false);
2619
6ed071f0
LP		 2620 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2621 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
660a5d51 2622 return X86EMUL_CONTINUE;
64d60670
PB		 2623}
2624
7b105ca2 2625static void
e66bb2cc 2626setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2627 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2628{
e66bb2cc 2629 cs->l = 0; /* will be adjusted later */
79168fd1 2630 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2631 cs->g = 1; /* 4kb granularity */
79168fd1 2632 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2633 cs->type = 0x0b; /* Read, Execute, Accessed */
2634 cs->s = 1;
2635 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2636 cs->p = 1;
2637 cs->d = 1;
99245b50 2638 cs->avl = 0;
e66bb2cc 2639
79168fd1
GN		 2640 set_desc_base(ss, 0); /* flat segment */
2641 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2642 ss->g = 1; /* 4kb granularity */
2643 ss->s = 1;
2644 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2645 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2646 ss->dpl = 0;
79168fd1 2647 ss->p = 1;
99245b50
GN		 2648 ss->l = 0;
2649 ss->avl = 0;
e66bb2cc
AP		 2650}
2651
1a18a69b
AK		 2652static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2653{
2654 u32 eax, ebx, ecx, edx;
2655
2656 eax = ecx = 0;
e911eb3b 2657 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a 2658 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2659 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2660 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2661}
2662
c2226fc9
SB		 2663static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2664{
0225fb50 2665 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2666 u32 eax, ebx, ecx, edx;
2667
2668 /*
2669 * syscall should always be enabled in longmode - so only become
2670 * vendor specific (cpuid) if other modes are active...
2671 */
2672 if (ctxt->mode == X86EMUL_MODE_PROT64)
2673 return true;
2674
2675 eax = 0x00000000;
2676 ecx = 0x00000000;
e911eb3b 2677 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a
AK		 2678 /*
2679 * Intel ("GenuineIntel")
2680 * remark: Intel CPUs only support "syscall" in 64bit
2681 * longmode. Also an 64bit guest with a
2682 * 32bit compat-app running will #UD !! While this
2683 * behaviour can be fixed (by emulating) into AMD
2684 * response - CPUs of AMD can't behave like Intel.
2685 */
2686 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2687 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2688 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2689 return false;
2690
2691 /* AMD ("AuthenticAMD") */
2692 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2693 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2694 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2695 return true;
2696
2697 /* AMD ("AMDisbetter!") */
2698 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2699 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2700 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2701 return true;
c2226fc9
SB		 2702
2703 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2704 return false;
2705}
2706
e01991e7 2707static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2708{
0225fb50 2709 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2710 struct desc_struct cs, ss;
e66bb2cc 2711 u64 msr_data;
79168fd1 2712 u16 cs_sel, ss_sel;
c2ad2bb3 2713 u64 efer = 0;
e66bb2cc
AP		 2714
2715 /* syscall is not available in real mode */
2e901c4c 2716 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2717 ctxt->mode == X86EMUL_MODE_VM86)
2718 return emulate_ud(ctxt);
e66bb2cc 2719
c2226fc9
SB		 2720 if (!(em_syscall_is_enabled(ctxt)))
2721 return emulate_ud(ctxt);
2722
c2ad2bb3 2723 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2724 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2725
c2226fc9
SB		 2726 if (!(efer & EFER_SCE))
2727 return emulate_ud(ctxt);
2728
717746e3 2729 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2730 msr_data >>= 32;
79168fd1
GN		 2731 cs_sel = (u16)(msr_data & 0xfffc);
2732 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2733
c2ad2bb3 2734 if (efer & EFER_LMA) {
79168fd1 2735 cs.d = 0;
e66bb2cc
AP		 2736 cs.l = 1;
2737 }
1aa36616
AK		 2738 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2739 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2740
dd856efa 2741 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2742 if (efer & EFER_LMA) {
e66bb2cc 2743#ifdef CONFIG_X86_64
6c6cb69b 2744 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2745
717746e3 2746 ops->get_msr(ctxt,
3fb1b5db
GN		 2747 ctxt->mode == X86EMUL_MODE_PROT64 ?
2748 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2749 ctxt->_eip = msr_data;
e66bb2cc 2750
717746e3 2751 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2752 ctxt->eflags &= ~msr_data;
35fd68a3 2753 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2754#endif
2755 } else {
2756 /* legacy mode */
717746e3 2757 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2758 ctxt->_eip = (u32)msr_data;
e66bb2cc 2759
0efb0440 2760 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2761 }
2762
c8401dda 2763 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
e54cfa97 2764 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2765}
2766
e01991e7 2767static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2768{
0225fb50 2769 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2770 struct desc_struct cs, ss;
8c604352 2771 u64 msr_data;
79168fd1 2772 u16 cs_sel, ss_sel;
c2ad2bb3 2773 u64 efer = 0;
8c604352 2774
7b105ca2 2775 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2776 /* inject #GP if in real mode */
35d3d4a1
AK		 2777 if (ctxt->mode == X86EMUL_MODE_REAL)
2778 return emulate_gp(ctxt, 0);
8c604352 2779
1a18a69b
AK		 2780 /*
2781 * Not recognized on AMD in compat mode (but is recognized in legacy
2782 * mode).
2783 */
f3747379 2784 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2785 && !vendor_intel(ctxt))
2786 return emulate_ud(ctxt);
2787
b2c9d43e 2788 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2789 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2790 return X86EMUL_UNHANDLEABLE;
8c604352 2791
7b105ca2 2792 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2793
717746e3 2794 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2795 if ((msr_data & 0xfffc) == 0x0)
2796 return emulate_gp(ctxt, 0);
8c604352 2797
0efb0440 2798 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2799 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2800 ss_sel = cs_sel + 8;
f3747379 2801 if (efer & EFER_LMA) {
79168fd1 2802 cs.d = 0;
8c604352
AP		 2803 cs.l = 1;
2804 }
2805
1aa36616
AK		 2806 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2807 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2808
717746e3 2809 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2810 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2811
717746e3 2812 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2813 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2814 (u32)msr_data;
8c604352 2815
e54cfa97 2816 return X86EMUL_CONTINUE;
8c604352
AP		 2817}
2818
e01991e7 2819static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2820{
0225fb50 2821 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2822 struct desc_struct cs, ss;
234f3ce4 2823 u64 msr_data, rcx, rdx;
4668f050 2824 int usermode;
1249b96e 2825 u16 cs_sel = 0, ss_sel = 0;
4668f050 2826
a0044755
GN		 2827 /* inject #GP if in real mode or Virtual 8086 mode */
2828 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2829 ctxt->mode == X86EMUL_MODE_VM86)
2830 return emulate_gp(ctxt, 0);
4668f050 2831
7b105ca2 2832 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2833
9dac77fa 2834 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2835 usermode = X86EMUL_MODE_PROT64;
2836 else
2837 usermode = X86EMUL_MODE_PROT32;
2838
234f3ce4
NA		 2839 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2840 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2841
4668f050
AP		 2842 cs.dpl = 3;
2843 ss.dpl = 3;
717746e3 2844 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2845 switch (usermode) {
2846 case X86EMUL_MODE_PROT32:
79168fd1 2847 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2848 if ((msr_data & 0xfffc) == 0x0)
2849 return emulate_gp(ctxt, 0);
79168fd1 2850 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2851 rcx = (u32)rcx;
2852 rdx = (u32)rdx;
4668f050
AP		 2853 break;
2854 case X86EMUL_MODE_PROT64:
79168fd1 2855 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2856 if (msr_data == 0x0)
2857 return emulate_gp(ctxt, 0);
79168fd1
GN		 2858 ss_sel = cs_sel + 8;
2859 cs.d = 0;
4668f050 2860 cs.l = 1;
fd8cb433
YZ		 2861 if (emul_is_noncanonical_address(rcx, ctxt) ||
2862 emul_is_noncanonical_address(rdx, ctxt))
234f3ce4 2863 return emulate_gp(ctxt, 0);
4668f050
AP		 2864 break;
2865 }
b32a9918
NA		 2866 cs_sel |= SEGMENT_RPL_MASK;
2867 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2868
1aa36616
AK		 2869 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2870 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2871
234f3ce4
NA		 2872 ctxt->_eip = rdx;
2873 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2874
e54cfa97 2875 return X86EMUL_CONTINUE;
4668f050
AP		 2876}
2877
7b105ca2 2878static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2879{
2880 int iopl;
2881 if (ctxt->mode == X86EMUL_MODE_REAL)
2882 return false;
2883 if (ctxt->mode == X86EMUL_MODE_VM86)
2884 return true;
0efb0440 2885 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2886 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2887}
2888
2889static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2890 u16 port, u16 len)
2891{
0225fb50 2892 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2893 struct desc_struct tr_seg;
5601d05b 2894 u32 base3;
f850e2e6 2895 int r;
1aa36616 2896 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2897 unsigned mask = (1 << len) - 1;
5601d05b 2898 unsigned long base;
f850e2e6 2899
1aa36616 2900 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2901 if (!tr_seg.p)
f850e2e6 2902 return false;
79168fd1 2903 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2904 return false;
5601d05b
GN		 2905 base = get_desc_base(&tr_seg);
2906#ifdef CONFIG_X86_64
2907 base |= ((u64)base3) << 32;
2908#endif
0f65dd70 2909 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2910 if (r != X86EMUL_CONTINUE)
2911 return false;
79168fd1 2912 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2913 return false;
0f65dd70 2914 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2915 if (r != X86EMUL_CONTINUE)
2916 return false;
2917 if ((perm >> bit_idx) & mask)
2918 return false;
2919 return true;
2920}
2921
2922static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2923 u16 port, u16 len)
2924{
4fc40f07
GN		 2925 if (ctxt->perm_ok)
2926 return true;
2927
7b105ca2
TY		 2928 if (emulator_bad_iopl(ctxt))
2929 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2930 return false;
4fc40f07
GN		 2931
2932 ctxt->perm_ok = true;
2933
f850e2e6
GN		 2934 return true;
2935}
2936
428e3d08
NA		 2937static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2938{
2939 /*
2940 * Intel CPUs mask the counter and pointers in quite strange
2941 * manner when ECX is zero due to REP-string optimizations.
2942 */
2943#ifdef CONFIG_X86_64
2944 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2945 return;
2946
2947 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2948
2949 switch (ctxt->b) {
2950 case 0xa4: /* movsb */
2951 case 0xa5: /* movsd/w */
2952 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2953 /* fall through */
2954 case 0xaa: /* stosb */
2955 case 0xab: /* stosd/w */
2956 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2957 }
2958#endif
2959}
2960
38ba30ba 2961static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2962 struct tss_segment_16 *tss)
2963{
9dac77fa 2964 tss->ip = ctxt->_eip;
38ba30ba 2965 tss->flag = ctxt->eflags;
dd856efa
AK		 2966 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2967 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2968 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2969 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2970 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2971 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2972 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2973 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2974
1aa36616
AK		 2975 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2976 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2977 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2978 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2979 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2980}
2981
2982static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2983 struct tss_segment_16 *tss)
2984{
38ba30ba 2985 int ret;
2356aaeb 2986 u8 cpl;
38ba30ba 2987
9dac77fa 2988 ctxt->_eip = tss->ip;
38ba30ba 2989 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2990 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2991 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2992 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2993 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2994 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2995 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2996 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2997 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2998
2999 /*
3000 * SDM says that segment selectors are loaded before segment
3001 * descriptors
3002 */
1aa36616
AK		 3003 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3004 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3005 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3006 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3007 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 3008
2356aaeb
PB		 3009 cpl = tss->cs & 3;
3010
38ba30ba 3011 /*
fc058680 3012 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 3013 * it is handled in a context of new task
3014 */
d1442d85 3015 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 3016 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3017 if (ret != X86EMUL_CONTINUE)
3018 return ret;
d1442d85 3019 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3020 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3021 if (ret != X86EMUL_CONTINUE)
3022 return ret;
d1442d85 3023 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3024 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3025 if (ret != X86EMUL_CONTINUE)
3026 return ret;
d1442d85 3027 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3028 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3029 if (ret != X86EMUL_CONTINUE)
3030 return ret;
d1442d85 3031 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3032 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3033 if (ret != X86EMUL_CONTINUE)
3034 return ret;
3035
3036 return X86EMUL_CONTINUE;
3037}
3038
3039static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3040 u16 tss_selector, u16 old_tss_sel,
3041 ulong old_tss_base, struct desc_struct *new_desc)
3042{
0225fb50 3043 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3044 struct tss_segment_16 tss_seg;
3045 int ret;
bcc55cba 3046 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 3047
0f65dd70 3048 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3049 &ctxt->exception);
db297e3d 3050 if (ret != X86EMUL_CONTINUE)
38ba30ba 3051 return ret;
38ba30ba 3052
7b105ca2 3053 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3054
0f65dd70 3055 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3056 &ctxt->exception);
db297e3d 3057 if (ret != X86EMUL_CONTINUE)
38ba30ba 3058 return ret;
38ba30ba 3059
0f65dd70 3060 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3061 &ctxt->exception);
db297e3d 3062 if (ret != X86EMUL_CONTINUE)
38ba30ba 3063 return ret;
38ba30ba
GN		 3064
3065 if (old_tss_sel != 0xffff) {
3066 tss_seg.prev_task_link = old_tss_sel;
3067
0f65dd70 3068 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3069 &tss_seg.prev_task_link,
3070 sizeof tss_seg.prev_task_link,
0f65dd70 3071 &ctxt->exception);
db297e3d 3072 if (ret != X86EMUL_CONTINUE)
38ba30ba 3073 return ret;
38ba30ba
GN		 3074 }
3075
7b105ca2 3076 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3077}
3078
3079static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3080 struct tss_segment_32 *tss)
3081{
5c7411e2 3082 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3083 tss->eip = ctxt->_eip;
38ba30ba 3084 tss->eflags = ctxt->eflags;
dd856efa
AK		 3085 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3086 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3087 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3088 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3089 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3090 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3091 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3092 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3093
1aa36616
AK		 3094 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3095 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3096 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3097 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3098 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3099 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3100}
3101
3102static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3103 struct tss_segment_32 *tss)
3104{
38ba30ba 3105 int ret;
2356aaeb 3106 u8 cpl;
38ba30ba 3107
7b105ca2 3108 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3109 return emulate_gp(ctxt, 0);
9dac77fa 3110 ctxt->_eip = tss->eip;
38ba30ba 3111 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3112
3113 /* General purpose registers */
dd856efa
AK		 3114 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3115 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3116 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3117 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3118 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3119 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3120 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3121 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3122
3123 /*
3124 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3125 * descriptors. This is important because CPL checks will
3126 * use CS.RPL.
38ba30ba 3127 */
1aa36616
AK		 3128 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3129 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3130 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3131 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3132 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3133 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3134 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3135
4cee4798
KW		 3136 /*
3137 * If we're switching between Protected Mode and VM86, we need to make
3138 * sure to update the mode before loading the segment descriptors so
3139 * that the selectors are interpreted correctly.
4cee4798 3140 */
2356aaeb 3141 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3142 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3143 cpl = 3;
3144 } else {
4cee4798 3145 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3146 cpl = tss->cs & 3;
3147 }
4cee4798 3148
38ba30ba
GN		 3149 /*
3150 * Now load segment descriptors. If fault happenes at this stage
3151 * it is handled in a context of new task
3152 */
d1442d85 3153 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3154 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3155 if (ret != X86EMUL_CONTINUE)
3156 return ret;
d1442d85 3157 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3158 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3159 if (ret != X86EMUL_CONTINUE)
3160 return ret;
d1442d85 3161 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3162 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3163 if (ret != X86EMUL_CONTINUE)
3164 return ret;
d1442d85 3165 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3166 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3167 if (ret != X86EMUL_CONTINUE)
3168 return ret;
d1442d85 3169 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3170 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3171 if (ret != X86EMUL_CONTINUE)
3172 return ret;
d1442d85 3173 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3174 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3175 if (ret != X86EMUL_CONTINUE)
3176 return ret;
d1442d85 3177 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3178 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3179
2f729b10 3180 return ret;
38ba30ba
GN		 3181}
3182
3183static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3184 u16 tss_selector, u16 old_tss_sel,
3185 ulong old_tss_base, struct desc_struct *new_desc)
3186{
0225fb50 3187 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3188 struct tss_segment_32 tss_seg;
3189 int ret;
bcc55cba 3190 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3191 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3192 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3193
0f65dd70 3194 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3195 &ctxt->exception);
db297e3d 3196 if (ret != X86EMUL_CONTINUE)
38ba30ba 3197 return ret;
38ba30ba 3198
7b105ca2 3199 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3200
5c7411e2
NA		 3201 /* Only GP registers and segment selectors are saved */
3202 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3203 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 3204 if (ret != X86EMUL_CONTINUE)
38ba30ba 3205 return ret;
38ba30ba 3206
0f65dd70 3207 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3208 &ctxt->exception);
db297e3d 3209 if (ret != X86EMUL_CONTINUE)
38ba30ba 3210 return ret;
38ba30ba
GN		 3211
3212 if (old_tss_sel != 0xffff) {
3213 tss_seg.prev_task_link = old_tss_sel;
3214
0f65dd70 3215 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3216 &tss_seg.prev_task_link,
3217 sizeof tss_seg.prev_task_link,
0f65dd70 3218 &ctxt->exception);
db297e3d 3219 if (ret != X86EMUL_CONTINUE)
38ba30ba 3220 return ret;
38ba30ba
GN		 3221 }
3222
7b105ca2 3223 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3224}
3225
3226static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3227 u16 tss_selector, int idt_index, int reason,
e269fb21 3228 bool has_error_code, u32 error_code)
38ba30ba 3229{
0225fb50 3230 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3231 struct desc_struct curr_tss_desc, next_tss_desc;
3232 int ret;
1aa36616 3233 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3234 ulong old_tss_base =
4bff1e86 3235 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3236 u32 desc_limit;
3db176d5 3237 ulong desc_addr, dr7;
38ba30ba
GN		 3238
3239 /* FIXME: old_tss_base == ~0 ? */
3240
e919464b 3241 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3242 if (ret != X86EMUL_CONTINUE)
3243 return ret;
e919464b 3244 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3245 if (ret != X86EMUL_CONTINUE)
3246 return ret;
3247
3248 /* FIXME: check that next_tss_desc is tss */
3249
7f3d35fd
KW		 3250 /*
3251 * Check privileges. The three cases are task switch caused by...
3252 *
3253 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3254 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3255 * 3. jmp/call to TSS/task-gate: No check is performed since the
3256 * hardware checks it before exiting.
7f3d35fd
KW		 3257 */
3258 if (reason == TASK_SWITCH_GATE) {
3259 if (idt_index != -1) {
3260 /* Software interrupts */
3261 struct desc_struct task_gate_desc;
3262 int dpl;
3263
3264 ret = read_interrupt_descriptor(ctxt, idt_index,
3265 &task_gate_desc);
3266 if (ret != X86EMUL_CONTINUE)
3267 return ret;
3268
3269 dpl = task_gate_desc.dpl;
3270 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3271 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3272 }
38ba30ba
GN		 3273 }
3274
ceffb459
GN		 3275 desc_limit = desc_limit_scaled(&next_tss_desc);
3276 if (!next_tss_desc.p ||
3277 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3278 desc_limit < 0x2b)) {
592f0858 3279 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3280 }
3281
3282 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3283 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3284 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3285 }
3286
3287 if (reason == TASK_SWITCH_IRET)
3288 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3289
3290 /* set back link to prev task only if NT bit is set in eflags
fc058680 3291 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3292 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3293 old_tss_sel = 0xffff;
3294
3295 if (next_tss_desc.type & 8)
7b105ca2 3296 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3297 old_tss_base, &next_tss_desc);
3298 else
7b105ca2 3299 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3300 old_tss_base, &next_tss_desc);
0760d448
JK		 3301 if (ret != X86EMUL_CONTINUE)
3302 return ret;
38ba30ba
GN		 3303
3304 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3305 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3306
3307 if (reason != TASK_SWITCH_IRET) {
3308 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3309 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3310 }
3311
717746e3 3312 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3313 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3314
e269fb21 3315 if (has_error_code) {
9dac77fa
AK		 3316 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3317 ctxt->lock_prefix = 0;
3318 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3319 ret = em_push(ctxt);
e269fb21
JK		 3320 }
3321
3db176d5
NA		 3322 ops->get_dr(ctxt, 7, &dr7);
3323 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3324
38ba30ba
GN		 3325 return ret;
3326}
3327
3328int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3329 u16 tss_selector, int idt_index, int reason,
e269fb21 3330 bool has_error_code, u32 error_code)
38ba30ba 3331{
38ba30ba
GN		 3332 int rc;
3333
dd856efa 3334 invalidate_registers(ctxt);
9dac77fa
AK		 3335 ctxt->_eip = ctxt->eip;
3336 ctxt->dst.type = OP_NONE;
38ba30ba 3337
7f3d35fd 3338 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3339 has_error_code, error_code);
38ba30ba 3340
dd856efa 3341 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3342 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3343 writeback_registers(ctxt);
3344 }
38ba30ba 3345
a0c0ab2f 3346 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3347}
3348
f3bd64c6
GN		 3349static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3350 struct operand *op)
a682e354 3351{
0efb0440 3352 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3353
01485a22
PB		 3354 register_address_increment(ctxt, reg, df * op->bytes);
3355 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3356}
3357
7af04fc0
AK		 3358static int em_das(struct x86_emulate_ctxt *ctxt)
3359{
7af04fc0
AK		 3360 u8 al, old_al;
3361 bool af, cf, old_cf;
3362
3363 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3364 al = ctxt->dst.val;
7af04fc0
AK		 3365
3366 old_al = al;
3367 old_cf = cf;
3368 cf = false;
3369 af = ctxt->eflags & X86_EFLAGS_AF;
3370 if ((al & 0x0f) > 9 || af) {
3371 al -= 6;
3372 cf = old_cf | (al >= 250);
3373 af = true;
3374 } else {
3375 af = false;
3376 }
3377 if (old_al > 0x99 || old_cf) {
3378 al -= 0x60;
3379 cf = true;
3380 }
3381
9dac77fa 3382 ctxt->dst.val = al;
7af04fc0 3383 /* Set PF, ZF, SF */
9dac77fa
AK		 3384 ctxt->src.type = OP_IMM;
3385 ctxt->src.val = 0;
3386 ctxt->src.bytes = 1;
158de57f 3387 fastop(ctxt, em_or);
7af04fc0
AK		 3388 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3389 if (cf)
3390 ctxt->eflags |= X86_EFLAGS_CF;
3391 if (af)
3392 ctxt->eflags |= X86_EFLAGS_AF;
3393 return X86EMUL_CONTINUE;
3394}
3395
a035d5c6
PB		 3396static int em_aam(struct x86_emulate_ctxt *ctxt)
3397{
3398 u8 al, ah;
3399
3400 if (ctxt->src.val == 0)
3401 return emulate_de(ctxt);
3402
3403 al = ctxt->dst.val & 0xff;
3404 ah = al / ctxt->src.val;
3405 al %= ctxt->src.val;
3406
3407 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3408
3409 /* Set PF, ZF, SF */
3410 ctxt->src.type = OP_IMM;
3411 ctxt->src.val = 0;
3412 ctxt->src.bytes = 1;
3413 fastop(ctxt, em_or);
3414
3415 return X86EMUL_CONTINUE;
3416}
3417
7f662273
GN		 3418static int em_aad(struct x86_emulate_ctxt *ctxt)
3419{
3420 u8 al = ctxt->dst.val & 0xff;
3421 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3422
3423 al = (al + (ah * ctxt->src.val)) & 0xff;
3424
3425 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3426
f583c29b
GN		 3427 /* Set PF, ZF, SF */
3428 ctxt->src.type = OP_IMM;
3429 ctxt->src.val = 0;
3430 ctxt->src.bytes = 1;
3431 fastop(ctxt, em_or);
7f662273
GN		 3432
3433 return X86EMUL_CONTINUE;
3434}
3435
d4ddafcd
TY		 3436static int em_call(struct x86_emulate_ctxt *ctxt)
3437{
234f3ce4 3438 int rc;
d4ddafcd
TY		 3439 long rel = ctxt->src.val;
3440
3441 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3442 rc = jmp_rel(ctxt, rel);
3443 if (rc != X86EMUL_CONTINUE)
3444 return rc;
d4ddafcd
TY		 3445 return em_push(ctxt);
3446}
3447
0ef753b8
AK		 3448static int em_call_far(struct x86_emulate_ctxt *ctxt)
3449{
0ef753b8
AK		 3450 u16 sel, old_cs;
3451 ulong old_eip;
3452 int rc;
d1442d85
NA		 3453 struct desc_struct old_desc, new_desc;
3454 const struct x86_emulate_ops *ops = ctxt->ops;
3455 int cpl = ctxt->ops->cpl(ctxt);
82268083 3456 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3457
9dac77fa 3458 old_eip = ctxt->_eip;
d1442d85 3459 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3460
9dac77fa 3461 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3462 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3463 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3464 if (rc != X86EMUL_CONTINUE)
80976dbb 3465 return rc;
0ef753b8 3466
d50eaa18 3467 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3468 if (rc != X86EMUL_CONTINUE)
3469 goto fail;
0ef753b8 3470
9dac77fa 3471 ctxt->src.val = old_cs;
4487b3b4 3472 rc = em_push(ctxt);
0ef753b8 3473 if (rc != X86EMUL_CONTINUE)
d1442d85 3474 goto fail;
0ef753b8 3475
9dac77fa 3476 ctxt->src.val = old_eip;
d1442d85
NA		 3477 rc = em_push(ctxt);
3478 /* If we failed, we tainted the memory, but the very least we should
3479 restore cs */
82268083
NA		 3480 if (rc != X86EMUL_CONTINUE) {
3481 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3482 goto fail;
82268083 3483 }
d1442d85
NA		 3484 return rc;
3485fail:
3486 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3487 ctxt->mode = prev_mode;
d1442d85
NA		 3488 return rc;
3489
0ef753b8
AK		 3490}
3491
40ece7c7
AK		 3492static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3493{
40ece7c7 3494 int rc;
234f3ce4 3495 unsigned long eip;
40ece7c7 3496
234f3ce4
NA		 3497 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3498 if (rc != X86EMUL_CONTINUE)
3499 return rc;
3500 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3501 if (rc != X86EMUL_CONTINUE)
3502 return rc;
5ad105e5 3503 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3504 return X86EMUL_CONTINUE;
3505}
3506
e4f973ae
TY		 3507static int em_xchg(struct x86_emulate_ctxt *ctxt)
3508{
e4f973ae 3509 /* Write back the register source. */
9dac77fa
AK		 3510 ctxt->src.val = ctxt->dst.val;
3511 write_register_operand(&ctxt->src);
e4f973ae
TY		 3512
3513 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3514 ctxt->dst.val = ctxt->src.orig_val;
3515 ctxt->lock_prefix = 1;
e4f973ae
TY		 3516 return X86EMUL_CONTINUE;
3517}
3518
5c82aa29
AK		 3519static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3520{
9dac77fa 3521 ctxt->dst.val = ctxt->src2.val;
4d758349 3522 return fastop(ctxt, em_imul);
5c82aa29
AK		 3523}
3524
61429142
AK		 3525static int em_cwd(struct x86_emulate_ctxt *ctxt)
3526{
9dac77fa
AK		 3527 ctxt->dst.type = OP_REG;
3528 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3529 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3530 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3531
3532 return X86EMUL_CONTINUE;
3533}
3534
48bb5d3c
AK		 3535static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3536{
48bb5d3c
AK		 3537 u64 tsc = 0;
3538
717746e3 3539 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3540 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3541 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3542 return X86EMUL_CONTINUE;
3543}
3544
222d21aa
AK		 3545static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3546{
3547 u64 pmc;
3548
dd856efa 3549 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3550 return emulate_gp(ctxt, 0);
dd856efa
AK		 3551 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3552 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3553 return X86EMUL_CONTINUE;
3554}
3555
b9eac5f4
AK		 3556static int em_mov(struct x86_emulate_ctxt *ctxt)
3557{
54cfdb3e 3558 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3559 return X86EMUL_CONTINUE;
3560}
3561
84cffe49
BP		 3562#define FFL(x) bit(X86_FEATURE_##x)
3563
3564static int em_movbe(struct x86_emulate_ctxt *ctxt)
3565{
3566 u32 ebx, ecx, edx, eax = 1;
3567 u16 tmp;
3568
3569 /*
3570 * Check MOVBE is set in the guest-visible CPUID leaf.
3571 */
e911eb3b 3572 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
84cffe49
BP		 3573 if (!(ecx & FFL(MOVBE)))
3574 return emulate_ud(ctxt);
3575
3576 switch (ctxt->op_bytes) {
3577 case 2:
3578 /*
3579 * From MOVBE definition: "...When the operand size is 16 bits,
3580 * the upper word of the destination register remains unchanged
3581 * ..."
3582 *
3583 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3584 * rules so we have to do the operation almost per hand.
3585 */
3586 tmp = (u16)ctxt->src.val;
3587 ctxt->dst.val &= ~0xffffUL;
3588 ctxt->dst.val |= (unsigned long)swab16(tmp);
3589 break;
3590 case 4:
3591 ctxt->dst.val = swab32((u32)ctxt->src.val);
3592 break;
3593 case 8:
3594 ctxt->dst.val = swab64(ctxt->src.val);
3595 break;
3596 default:
592f0858 3597 BUG();
84cffe49
BP		 3598 }
3599 return X86EMUL_CONTINUE;
3600}
3601
bc00f8d2
TY		 3602static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3603{
3604 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3605 return emulate_gp(ctxt, 0);
3606
3607 /* Disable writeback. */
3608 ctxt->dst.type = OP_NONE;
3609 return X86EMUL_CONTINUE;
3610}
3611
3612static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3613{
3614 unsigned long val;
3615
3616 if (ctxt->mode == X86EMUL_MODE_PROT64)
3617 val = ctxt->src.val & ~0ULL;
3618 else
3619 val = ctxt->src.val & ~0U;
3620
3621 /* #UD condition is already handled. */
3622 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3623 return emulate_gp(ctxt, 0);
3624
3625 /* Disable writeback. */
3626 ctxt->dst.type = OP_NONE;
3627 return X86EMUL_CONTINUE;
3628}
3629
e1e210b0
TY		 3630static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3631{
3632 u64 msr_data;
3633
dd856efa
AK		 3634 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3635 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3636 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3637 return emulate_gp(ctxt, 0);
3638
3639 return X86EMUL_CONTINUE;
3640}
3641
3642static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3643{
3644 u64 msr_data;
3645
dd856efa 3646 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3647 return emulate_gp(ctxt, 0);
3648
dd856efa
AK		 3649 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3650 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3651 return X86EMUL_CONTINUE;
3652}
3653
1bd5f469
TY		 3654static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3655{
9dac77fa 3656 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3657 return emulate_ud(ctxt);
3658
9dac77fa 3659 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3660 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3661 ctxt->dst.bytes = 2;
1bd5f469
TY		 3662 return X86EMUL_CONTINUE;
3663}
3664
3665static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3666{
9dac77fa 3667 u16 sel = ctxt->src.val;
1bd5f469 3668
9dac77fa 3669 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3670 return emulate_ud(ctxt);
3671
9dac77fa 3672 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3673 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3674
3675 /* Disable writeback. */
9dac77fa
AK		 3676 ctxt->dst.type = OP_NONE;
3677 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3678}
3679
a14e579f
AK		 3680static int em_lldt(struct x86_emulate_ctxt *ctxt)
3681{
3682 u16 sel = ctxt->src.val;
3683
3684 /* Disable writeback. */
3685 ctxt->dst.type = OP_NONE;
3686 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3687}
3688
80890006
AK		 3689static int em_ltr(struct x86_emulate_ctxt *ctxt)
3690{
3691 u16 sel = ctxt->src.val;
3692
3693 /* Disable writeback. */
3694 ctxt->dst.type = OP_NONE;
3695 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3696}
3697
38503911
AK		 3698static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3699{
9fa088f4
AK		 3700 int rc;
3701 ulong linear;
3702
9dac77fa 3703 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3704 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3705 ctxt->ops->invlpg(ctxt, linear);
38503911 3706 /* Disable writeback. */
9dac77fa 3707 ctxt->dst.type = OP_NONE;
38503911
AK		 3708 return X86EMUL_CONTINUE;
3709}
3710
2d04a05b
AK		 3711static int em_clts(struct x86_emulate_ctxt *ctxt)
3712{
3713 ulong cr0;
3714
3715 cr0 = ctxt->ops->get_cr(ctxt, 0);
3716 cr0 &= ~X86_CR0_TS;
3717 ctxt->ops->set_cr(ctxt, 0, cr0);
3718 return X86EMUL_CONTINUE;
3719}
3720
b34a8051 3721static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3722{
0f54a321 3723 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3724
26d05cc7
AK		 3725 if (rc != X86EMUL_CONTINUE)
3726 return rc;
3727
3728 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3729 ctxt->_eip = ctxt->eip;
26d05cc7 3730 /* Disable writeback. */
9dac77fa 3731 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3732 return X86EMUL_CONTINUE;
3733}
3734
96051572
AK		 3735static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3736 void (*get)(struct x86_emulate_ctxt *ctxt,
3737 struct desc_ptr *ptr))
3738{
3739 struct desc_ptr desc_ptr;
3740
3741 if (ctxt->mode == X86EMUL_MODE_PROT64)
3742 ctxt->op_bytes = 8;
3743 get(ctxt, &desc_ptr);
3744 if (ctxt->op_bytes == 2) {
3745 ctxt->op_bytes = 4;
3746 desc_ptr.address &= 0x00ffffff;
3747 }
3748 /* Disable writeback. */
3749 ctxt->dst.type = OP_NONE;
129a72a0
SR		 3750 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3751 &desc_ptr, 2 + ctxt->op_bytes);
96051572
AK		 3752}
3753
3754static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3755{
3756 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3757}
3758
3759static int em_sidt(struct x86_emulate_ctxt *ctxt)
3760{
3761 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3762}
3763
5b7f6a1e 3764static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3765{
26d05cc7
AK		 3766 struct desc_ptr desc_ptr;
3767 int rc;
3768
510425ff
AK		 3769 if (ctxt->mode == X86EMUL_MODE_PROT64)
3770 ctxt->op_bytes = 8;
9dac77fa 3771 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3772 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3773 ctxt->op_bytes);
26d05cc7
AK		 3774 if (rc != X86EMUL_CONTINUE)
3775 return rc;
9a9abf6b 3776 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
fd8cb433 3777 emul_is_noncanonical_address(desc_ptr.address, ctxt))
9a9abf6b 3778 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3779 if (lgdt)
3780 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3781 else
3782 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3783 /* Disable writeback. */
9dac77fa 3784 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3785 return X86EMUL_CONTINUE;
3786}
3787
5b7f6a1e
NA		 3788static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3789{
3790 return em_lgdt_lidt(ctxt, true);
3791}
3792
26d05cc7
AK		 3793static int em_lidt(struct x86_emulate_ctxt *ctxt)
3794{
5b7f6a1e 3795 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3796}
3797
3798static int em_smsw(struct x86_emulate_ctxt *ctxt)
3799{
32e94d06
NA		 3800 if (ctxt->dst.type == OP_MEM)
3801 ctxt->dst.bytes = 2;
9dac77fa 3802 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3803 return X86EMUL_CONTINUE;
3804}
3805
3806static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3807{
26d05cc7 3808 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3809 | (ctxt->src.val & 0x0f));
3810 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3811 return X86EMUL_CONTINUE;
3812}
3813
d06e03ad
TY		 3814static int em_loop(struct x86_emulate_ctxt *ctxt)
3815{
234f3ce4
NA		 3816 int rc = X86EMUL_CONTINUE;
3817
01485a22 3818 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3819 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3820 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3821 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3822
234f3ce4 3823 return rc;
d06e03ad
TY		 3824}
3825
3826static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3827{
234f3ce4
NA		 3828 int rc = X86EMUL_CONTINUE;
3829
dd856efa 3830 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3831 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3832
234f3ce4 3833 return rc;
d06e03ad
TY		 3834}
3835
d7841a4b
TY		 3836static int em_in(struct x86_emulate_ctxt *ctxt)
3837{
3838 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3839 &ctxt->dst.val))
3840 return X86EMUL_IO_NEEDED;
3841
3842 return X86EMUL_CONTINUE;
3843}
3844
3845static int em_out(struct x86_emulate_ctxt *ctxt)
3846{
3847 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3848 &ctxt->src.val, 1);
3849 /* Disable writeback. */
3850 ctxt->dst.type = OP_NONE;
3851 return X86EMUL_CONTINUE;
3852}
3853
f411e6cd
TY		 3854static int em_cli(struct x86_emulate_ctxt *ctxt)
3855{
3856 if (emulator_bad_iopl(ctxt))
3857 return emulate_gp(ctxt, 0);
3858
3859 ctxt->eflags &= ~X86_EFLAGS_IF;
3860 return X86EMUL_CONTINUE;
3861}
3862
3863static int em_sti(struct x86_emulate_ctxt *ctxt)
3864{
3865 if (emulator_bad_iopl(ctxt))
3866 return emulate_gp(ctxt, 0);
3867
3868 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3869 ctxt->eflags |= X86_EFLAGS_IF;
3870 return X86EMUL_CONTINUE;
3871}
3872
6d6eede4
AK		 3873static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3874{
3875 u32 eax, ebx, ecx, edx;
db2336a8
KH		 3876 u64 msr = 0;
3877
3878 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3879 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3880 ctxt->ops->cpl(ctxt)) {
3881 return emulate_gp(ctxt, 0);
3882 }
6d6eede4 3883
dd856efa
AK		 3884 eax = reg_read(ctxt, VCPU_REGS_RAX);
3885 ecx = reg_read(ctxt, VCPU_REGS_RCX);
e911eb3b 3886 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
dd856efa
AK		 3887 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3888 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3889 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3890 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3891 return X86EMUL_CONTINUE;
3892}
3893
98f73630
PB		 3894static int em_sahf(struct x86_emulate_ctxt *ctxt)
3895{
3896 u32 flags;
3897
0efb0440
NA		 3898 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3899 X86_EFLAGS_SF;
98f73630
PB		 3900 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3901
3902 ctxt->eflags &= ~0xffUL;
3903 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3904 return X86EMUL_CONTINUE;
3905}
3906
2dd7caa0
AK		 3907static int em_lahf(struct x86_emulate_ctxt *ctxt)
3908{
dd856efa
AK		 3909 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3910 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3911 return X86EMUL_CONTINUE;
3912}
3913
9299836e
AK		 3914static int em_bswap(struct x86_emulate_ctxt *ctxt)
3915{
3916 switch (ctxt->op_bytes) {
3917#ifdef CONFIG_X86_64
3918 case 8:
3919 asm("bswap %0" : "+r"(ctxt->dst.val));
3920 break;
3921#endif
3922 default:
3923 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3924 break;
3925 }
3926 return X86EMUL_CONTINUE;
3927}
3928
13e457e0
NA		 3929static int em_clflush(struct x86_emulate_ctxt *ctxt)
3930{
3931 /* emulating clflush regardless of cpuid */
3932 return X86EMUL_CONTINUE;
3933}
3934
2276b511
NA		 3935static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3936{
3937 ctxt->dst.val = (s32) ctxt->src.val;
3938 return X86EMUL_CONTINUE;
3939}
3940
283c95d0
RK		 3941static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3942{
3943 u32 eax = 1, ebx, ecx = 0, edx;
3944
e911eb3b 3945 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
283c95d0
RK		 3946 if (!(edx & FFL(FXSR)))
3947 return emulate_ud(ctxt);
3948
3949 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3950 return emulate_nm(ctxt);
3951
3952 /*
3953 * Don't emulate a case that should never be hit, instead of working
3954 * around a lack of fxsave64/fxrstor64 on old compilers.
3955 */
3956 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3957 return X86EMUL_UNHANDLEABLE;
3958
3959 return X86EMUL_CONTINUE;
3960}
3961
9d643f63
ND		 3962/*
3963 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
3964 * and restore MXCSR.
3965 */
3966static size_t __fxstate_size(int nregs)
3967{
3968 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
3969}
3970
3971static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
3972{
3973 bool cr4_osfxsr;
3974 if (ctxt->mode == X86EMUL_MODE_PROT64)
3975 return __fxstate_size(16);
3976
3977 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
3978 return __fxstate_size(cr4_osfxsr ? 8 : 0);
3979}
3980
283c95d0
RK		 3981/*
3982 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3983 * 1) 16 bit mode
3984 * 2) 32 bit mode
3985 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3986 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3987 * save and restore
3988 * 3) 64-bit mode with REX.W prefix
3989 * - like (2), but XMM 8-15 are being saved and restored
3990 * 4) 64-bit mode without REX.W prefix
3991 * - like (3), but FIP and FDP are 64 bit
3992 *
3993 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3994 * desired result. (4) is not emulated.
3995 *
3996 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3997 * and FPU DS) should match.
3998 */
3999static int em_fxsave(struct x86_emulate_ctxt *ctxt)
4000{
4001 struct fxregs_state fx_state;
283c95d0
RK		 4002 int rc;
4003
4004 rc = check_fxsr(ctxt);
4005 if (rc != X86EMUL_CONTINUE)
4006 return rc;
4007
283c95d0
RK		 4008 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4009
283c95d0
RK		 4010 if (rc != X86EMUL_CONTINUE)
4011 return rc;
4012
9d643f63
ND		 4013 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4014 fxstate_size(ctxt));
283c95d0
RK		 4015}
4016
4d772cb8
DH		 4017/*
4018 * FXRSTOR might restore XMM registers not provided by the guest. Fill
4019 * in the host registers (via FXSAVE) instead, so they won't be modified.
4020 * (preemption has to stay disabled until FXRSTOR).
4021 *
4022 * Use noinline to keep the stack for other functions called by callers small.
4023 */
4024static noinline int fxregs_fixup(struct fxregs_state *fx_state,
4025 const size_t used_size)
4026{
4027 struct fxregs_state fx_tmp;
4028 int rc;
4029
4030 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
4031 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
4032 __fxstate_size(16) - used_size);
4033
4034 return rc;
4035}
4036
283c95d0
RK		 4037static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4038{
4039 struct fxregs_state fx_state;
4040 int rc;
9d643f63 4041 size_t size;
283c95d0
RK		 4042
4043 rc = check_fxsr(ctxt);
4044 if (rc != X86EMUL_CONTINUE)
4045 return rc;
4046
4d772cb8
DH		 4047 size = fxstate_size(ctxt);
4048 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4049 if (rc != X86EMUL_CONTINUE)
4050 return rc;
4051
9d643f63 4052 if (size < __fxstate_size(16)) {
4d772cb8 4053 rc = fxregs_fixup(&fx_state, size);
9d643f63
ND		 4054 if (rc != X86EMUL_CONTINUE)
4055 goto out;
4056 }
283c95d0 4057
9d643f63
ND		 4058 if (fx_state.mxcsr >> 16) {
4059 rc = emulate_gp(ctxt, 0);
4060 goto out;
4061 }
283c95d0
RK		 4062
4063 if (rc == X86EMUL_CONTINUE)
4064 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4065
9d643f63 4066out:
283c95d0
RK		 4067 return rc;
4068}
4069
cfec82cb
JR		 4070static bool valid_cr(int nr)
4071{
4072 switch (nr) {
4073 case 0:
4074 case 2 ... 4:
4075 case 8:
4076 return true;
4077 default:
4078 return false;
4079 }
4080}
4081
4082static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4083{
9dac77fa 4084 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4085 return emulate_ud(ctxt);
4086
4087 return X86EMUL_CONTINUE;
4088}
4089
4090static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4091{
9dac77fa
AK		 4092 u64 new_val = ctxt->src.val64;
4093 int cr = ctxt->modrm_reg;
c2ad2bb3 4094 u64 efer = 0;
cfec82cb
JR		 4095
4096 static u64 cr_reserved_bits[] = {
4097 0xffffffff00000000ULL,
4098 0, 0, 0, /* CR3 checked later */
4099 CR4_RESERVED_BITS,
4100 0, 0, 0,
4101 CR8_RESERVED_BITS,
4102 };
4103
4104 if (!valid_cr(cr))
4105 return emulate_ud(ctxt);
4106
4107 if (new_val & cr_reserved_bits[cr])
4108 return emulate_gp(ctxt, 0);
4109
4110 switch (cr) {
4111 case 0: {
c2ad2bb3 4112 u64 cr4;
cfec82cb
JR		 4113 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4114 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4115 return emulate_gp(ctxt, 0);
4116
717746e3
AK		 4117 cr4 = ctxt->ops->get_cr(ctxt, 4);
4118 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4119
4120 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4121 !(cr4 & X86_CR4_PAE))
4122 return emulate_gp(ctxt, 0);
4123
4124 break;
4125 }
4126 case 3: {
4127 u64 rsvd = 0;
4128
c2ad2bb3 4129 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
d1cd3ce9
YZ		 4130 if (efer & EFER_LMA) {
4131 u64 maxphyaddr;
d6500149 4132 u32 eax, ebx, ecx, edx;
d1cd3ce9 4133
d6500149
YZ		 4134 eax = 0x80000008;
4135 ecx = 0;
4136 if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
4137 &edx, false))
d1cd3ce9
YZ		 4138 maxphyaddr = eax & 0xff;
4139 else
4140 maxphyaddr = 36;
4141 rsvd = rsvd_bits(maxphyaddr, 62);
4142 }
cfec82cb
JR		 4143
4144 if (new_val & rsvd)
4145 return emulate_gp(ctxt, 0);
4146
4147 break;
4148 }
4149 case 4: {
717746e3 4150 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4151
4152 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4153 return emulate_gp(ctxt, 0);
4154
4155 break;
4156 }
4157 }
4158
4159 return X86EMUL_CONTINUE;
4160}
4161
3b88e41a
JR		 4162static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4163{
4164 unsigned long dr7;
4165
717746e3 4166 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 4167
4168 /* Check if DR7.Global_Enable is set */
4169 return dr7 & (1 << 13);
4170}
4171
4172static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4173{
9dac77fa 4174 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4175 u64 cr4;
4176
4177 if (dr > 7)
4178 return emulate_ud(ctxt);
4179
717746e3 4180 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4181 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4182 return emulate_ud(ctxt);
4183
6d2a0526
NA		 4184 if (check_dr7_gd(ctxt)) {
4185 ulong dr6;
4186
4187 ctxt->ops->get_dr(ctxt, 6, &dr6);
4188 dr6 &= ~15;
4189 dr6 |= DR6_BD | DR6_RTM;
4190 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4191 return emulate_db(ctxt);
6d2a0526 4192 }
3b88e41a
JR		 4193
4194 return X86EMUL_CONTINUE;
4195}
4196
4197static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4198{
9dac77fa
AK		 4199 u64 new_val = ctxt->src.val64;
4200 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4201
4202 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4203 return emulate_gp(ctxt, 0);
4204
4205 return check_dr_read(ctxt);
4206}
4207
01de8b09
JR		 4208static int check_svme(struct x86_emulate_ctxt *ctxt)
4209{
92ceb767 4210 u64 efer = 0;
01de8b09 4211
717746e3 4212 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4213
4214 if (!(efer & EFER_SVME))
4215 return emulate_ud(ctxt);
4216
4217 return X86EMUL_CONTINUE;
4218}
4219
4220static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4221{
dd856efa 4222 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4223
4224 /* Valid physical address? */
d4224449 4225 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4226 return emulate_gp(ctxt, 0);
4227
4228 return check_svme(ctxt);
4229}
4230
d7eb8203
JR		 4231static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4232{
717746e3 4233 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4234
717746e3 4235 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 4236 return emulate_ud(ctxt);
4237
4238 return X86EMUL_CONTINUE;
4239}
4240
8061252e
JR		 4241static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4242{
717746e3 4243 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4244 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4245
717746e3 4246 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4247 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4248 return emulate_gp(ctxt, 0);
4249
4250 return X86EMUL_CONTINUE;
4251}
4252
f6511935
JR		 4253static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4254{
9dac77fa
AK		 4255 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4256 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4257 return emulate_gp(ctxt, 0);
4258
4259 return X86EMUL_CONTINUE;
4260}
4261
4262static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4263{
9dac77fa
AK		 4264 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4265 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4266 return emulate_gp(ctxt, 0);
4267
4268 return X86EMUL_CONTINUE;
4269}
4270
73fba5f4 4271#define D(_y) { .flags = (_y) }
d40a6898
PB		 4272#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4273#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4274 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4275#define N D(NotImpl)
01de8b09 4276#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4277#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4278#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4279#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4280#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4281#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4282#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4283#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4284#define II(_f, _e, _i) \
d40a6898 4285 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4286#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4287 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4288 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4289#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4290
8d8f4e9f 4291#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4292#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4293#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4294#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4295#define I2bvIP(_f, _e, _i, _p) \
4296 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4297
fb864fbc
AK		 4298#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4299 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4300 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4301
0f54a321
NA		 4302static const struct opcode group7_rm0[] = {
4303 N,
b34a8051 4304 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4305 N, N, N, N, N, N,
4306};
4307
fd0a0d82 4308static const struct opcode group7_rm1[] = {
1c2545be
TY		 4309 DI(SrcNone | Priv, monitor),
4310 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4311 N, N, N, N, N, N,
4312};
4313
fd0a0d82 4314static const struct opcode group7_rm3[] = {
1c2545be 4315 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4316 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4317 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4318 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4319 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4320 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4321 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4322 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4323};
6230f7fc 4324
fd0a0d82 4325static const struct opcode group7_rm7[] = {
d7eb8203 4326 N,
1c2545be 4327 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4328 N, N, N, N, N, N,
4329};
d67fc27a 4330
fd0a0d82 4331static const struct opcode group1[] = {
fb864fbc
AK		 4332 F(Lock, em_add),
4333 F(Lock | PageTable, em_or),
4334 F(Lock, em_adc),
4335 F(Lock, em_sbb),
4336 F(Lock | PageTable, em_and),
4337 F(Lock, em_sub),
4338 F(Lock, em_xor),
4339 F(NoWrite, em_cmp),
73fba5f4
AK		 4340};
4341
fd0a0d82 4342static const struct opcode group1A[] = {
0f89b207 4343 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4344};
4345
007a3b54
AK		 4346static const struct opcode group2[] = {
4347 F(DstMem | ModRM, em_rol),
4348 F(DstMem | ModRM, em_ror),
4349 F(DstMem | ModRM, em_rcl),
4350 F(DstMem | ModRM, em_rcr),
4351 F(DstMem | ModRM, em_shl),
4352 F(DstMem | ModRM, em_shr),
4353 F(DstMem | ModRM, em_shl),
4354 F(DstMem | ModRM, em_sar),
4355};
4356
fd0a0d82 4357static const struct opcode group3[] = {
fb864fbc
AK		 4358 F(DstMem | SrcImm | NoWrite, em_test),
4359 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4360 F(DstMem | SrcNone | Lock, em_not),
4361 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4362 F(DstXacc | Src2Mem, em_mul_ex),
4363 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4364 F(DstXacc | Src2Mem, em_div_ex),
4365 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4366};
4367
fd0a0d82 4368static const struct opcode group4[] = {
95413dc4
AK		 4369 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4370 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4371 N, N, N, N, N, N,
4372};
4373
fd0a0d82 4374static const struct opcode group5[] = {
95413dc4
AK		 4375 F(DstMem | SrcNone | Lock, em_inc),
4376 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4377 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4378 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4379 I(SrcMem | NearBranch, em_jmp_abs),
f7784046 4380 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
0f89b207 4381 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
73fba5f4
AK		 4382};
4383
fd0a0d82 4384static const struct opcode group6[] = {
63ea0a49
NA		 4385 DI(Prot | DstMem, sldt),
4386 DI(Prot | DstMem, str),
a14e579f 4387 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4388 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4389 N, N, N, N,
4390};
4391
fd0a0d82 4392static const struct group_dual group7 = { {
606b1c3e
NA		 4393 II(Mov | DstMem, em_sgdt, sgdt),
4394 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4395 II(SrcMem | Priv, em_lgdt, lgdt),
4396 II(SrcMem | Priv, em_lidt, lidt),
4397 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4398 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4399 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4400}, {
0f54a321 4401 EXT(0, group7_rm0),
5ef39c71 4402 EXT(0, group7_rm1),
01de8b09 4403 N, EXT(0, group7_rm3),
1c2545be
TY		 4404 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4405 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4406 EXT(0, group7_rm7),
73fba5f4
AK		 4407} };
4408
fd0a0d82 4409static const struct opcode group8[] = {
73fba5f4 4410 N, N, N, N,
11c363ba
AK		 4411 F(DstMem | SrcImmByte | NoWrite, em_bt),
4412 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4413 F(DstMem | SrcImmByte | Lock, em_btr),
4414 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4415};
4416
fd0a0d82 4417static const struct group_dual group9 = { {
1c2545be 4418 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 4419}, {
4420 N, N, N, N, N, N, N, N,
4421} };
4422
fd0a0d82 4423static const struct opcode group11[] = {
1c2545be 4424 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4425 X7(D(Undefined)),
a4d4a7c1
AK		 4426};
4427
13e457e0 4428static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 4429 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 4430};
4431
4432static const struct group_dual group15 = { {
283c95d0
RK		 4433 I(ModRM | Aligned16, em_fxsave),
4434 I(ModRM | Aligned16, em_fxrstor),
4435 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4436}, {
4437 N, N, N, N, N, N, N, N,
4438} };
4439
fd0a0d82 4440static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4441 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4442};
4443
39f062ff
NA		 4444static const struct instr_dual instr_dual_0f_2b = {
4445 I(0, em_mov), N
4446};
4447
d5b77069 4448static const struct gprefix pfx_0f_2b = {
39f062ff 4449 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4450};
4451
27ce8258 4452static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4453 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4454};
4455
0a37027e
AW		 4456static const struct gprefix pfx_0f_e7 = {
4457 N, I(Sse, em_mov), N, N,
4458};
4459
045a282c 4460static const struct escape escape_d9 = { {
16bebefe 4461 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4462}, {
4463 /* 0xC0 - 0xC7 */
4464 N, N, N, N, N, N, N, N,
4465 /* 0xC8 - 0xCF */
4466 N, N, N, N, N, N, N, N,
4467 /* 0xD0 - 0xC7 */
4468 N, N, N, N, N, N, N, N,
4469 /* 0xD8 - 0xDF */
4470 N, N, N, N, N, N, N, N,
4471 /* 0xE0 - 0xE7 */
4472 N, N, N, N, N, N, N, N,
4473 /* 0xE8 - 0xEF */
4474 N, N, N, N, N, N, N, N,
4475 /* 0xF0 - 0xF7 */
4476 N, N, N, N, N, N, N, N,
4477 /* 0xF8 - 0xFF */
4478 N, N, N, N, N, N, N, N,
4479} };
4480
4481static const struct escape escape_db = { {
4482 N, N, N, N, N, N, N, N,
4483}, {
4484 /* 0xC0 - 0xC7 */
4485 N, N, N, N, N, N, N, N,
4486 /* 0xC8 - 0xCF */
4487 N, N, N, N, N, N, N, N,
4488 /* 0xD0 - 0xC7 */
4489 N, N, N, N, N, N, N, N,
4490 /* 0xD8 - 0xDF */
4491 N, N, N, N, N, N, N, N,
4492 /* 0xE0 - 0xE7 */
4493 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4494 /* 0xE8 - 0xEF */
4495 N, N, N, N, N, N, N, N,
4496 /* 0xF0 - 0xF7 */
4497 N, N, N, N, N, N, N, N,
4498 /* 0xF8 - 0xFF */
4499 N, N, N, N, N, N, N, N,
4500} };
4501
4502static const struct escape escape_dd = { {
16bebefe 4503 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4504}, {
4505 /* 0xC0 - 0xC7 */
4506 N, N, N, N, N, N, N, N,
4507 /* 0xC8 - 0xCF */
4508 N, N, N, N, N, N, N, N,
4509 /* 0xD0 - 0xC7 */
4510 N, N, N, N, N, N, N, N,
4511 /* 0xD8 - 0xDF */
4512 N, N, N, N, N, N, N, N,
4513 /* 0xE0 - 0xE7 */
4514 N, N, N, N, N, N, N, N,
4515 /* 0xE8 - 0xEF */
4516 N, N, N, N, N, N, N, N,
4517 /* 0xF0 - 0xF7 */
4518 N, N, N, N, N, N, N, N,
4519 /* 0xF8 - 0xFF */
4520 N, N, N, N, N, N, N, N,
4521} };
4522
39f062ff
NA		 4523static const struct instr_dual instr_dual_0f_c3 = {
4524 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4525};
4526
2276b511
NA		 4527static const struct mode_dual mode_dual_63 = {
4528 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4529};
4530
fd0a0d82 4531static const struct opcode opcode_table[256] = {
73fba5f4 4532 /* 0x00 - 0x07 */
fb864fbc 4533 F6ALU(Lock, em_add),
1cd196ea
AK		 4534 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4535 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4536 /* 0x08 - 0x0F */
fb864fbc 4537 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4538 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4539 N,
73fba5f4 4540 /* 0x10 - 0x17 */
fb864fbc 4541 F6ALU(Lock, em_adc),
1cd196ea
AK		 4542 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4543 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4544 /* 0x18 - 0x1F */
fb864fbc 4545 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4546 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4547 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4548 /* 0x20 - 0x27 */
fb864fbc 4549 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4550 /* 0x28 - 0x2F */
fb864fbc 4551 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4552 /* 0x30 - 0x37 */
fb864fbc 4553 F6ALU(Lock, em_xor), N, N,
73fba5f4 4554 /* 0x38 - 0x3F */
fb864fbc 4555 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4556 /* 0x40 - 0x4F */
95413dc4 4557 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4558 /* 0x50 - 0x57 */
63540382 4559 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4560 /* 0x58 - 0x5F */
c54fe504 4561 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4562 /* 0x60 - 0x67 */
b96a7fad
TY		 4563 I(ImplicitOps | Stack | No64, em_pusha),
4564 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4565 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4566 N, N, N, N,
4567 /* 0x68 - 0x6F */
d46164db
AK		 4568 I(SrcImm | Mov | Stack, em_push),
4569 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4570 I(SrcImmByte | Mov | Stack, em_push),
4571 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4572 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4573 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4574 /* 0x70 - 0x7F */
58b7075d 4575 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4576 /* 0x80 - 0x87 */
1c2545be
TY		 4577 G(ByteOp | DstMem | SrcImm, group1),
4578 G(DstMem | SrcImm, group1),
4579 G(ByteOp | DstMem | SrcImm | No64, group1),
4580 G(DstMem | SrcImmByte, group1),
fb864fbc 4581 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4582 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4583 /* 0x88 - 0x8F */
d5ae7ce8 4584 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4585 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4586 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4587 D(ModRM | SrcMem | NoAccess | DstReg),
4588 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4589 G(0, group1A),
73fba5f4 4590 /* 0x90 - 0x97 */
bf608f88 4591 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4592 /* 0x98 - 0x9F */
61429142 4593 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4594 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4595 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4596 II(ImplicitOps | Stack, em_popf, popf),
4597 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4598 /* 0xA0 - 0xA7 */
b9eac5f4 4599 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4600 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
0f89b207
TL		 4601 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4602 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
73fba5f4 4603 /* 0xA8 - 0xAF */
fb864fbc 4604 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4605 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4606 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4607 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4608 /* 0xB0 - 0xB7 */
b9eac5f4 4609 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4610 /* 0xB8 - 0xBF */
5e2c6883 4611 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4612 /* 0xC0 - 0xC7 */
007a3b54 4613 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4614 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4615 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4616 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4617 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4618 G(ByteOp, group11), G(0, group11),
73fba5f4 4619 /* 0xC8 - 0xCF */
612e89f0 4620 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4621 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4622 I(ImplicitOps, em_ret_far),
3c6e276f 4623 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4624 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4625 /* 0xD0 - 0xD7 */
007a3b54
AK		 4626 G(Src2One | ByteOp, group2), G(Src2One, group2),
4627 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4628 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4629 I(DstAcc | SrcImmUByte | No64, em_aad),
4630 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4631 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4632 /* 0xD8 - 0xDF */
045a282c 4633 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4634 /* 0xE0 - 0xE7 */
58b7075d
NA		 4635 X3(I(SrcImmByte | NearBranch, em_loop)),
4636 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4637 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4638 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4639 /* 0xE8 - 0xEF */
58b7075d
NA		 4640 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4641 I(SrcImmFAddr | No64, em_jmp_far),
4642 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4643 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4644 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4645 /* 0xF0 - 0xF7 */
bf608f88 4646 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4647 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4648 G(ByteOp, group3), G(0, group3),
73fba5f4 4649 /* 0xF8 - 0xFF */
f411e6cd
TY		 4650 D(ImplicitOps), D(ImplicitOps),
4651 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4652 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4653};
4654
fd0a0d82 4655static const struct opcode twobyte_table[256] = {
73fba5f4 4656 /* 0x00 - 0x0F */
dee6bb70 4657 G(0, group6), GD(0, &group7), N, N,
b51e974f 4658 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4659 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4660 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4661 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4662 /* 0x10 - 0x1F */
103f98ea 4663 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4664 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4665 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4666 /* 0x20 - 0x2F */
9b88ae99
NA		 4667 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4668 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4669 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4670 check_cr_write),
4671 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4672 check_dr_write),
73fba5f4 4673 N, N, N, N,
27ce8258
IM		 4674 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4675 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4676 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4677 N, N, N, N,
73fba5f4 4678 /* 0x30 - 0x3F */
e1e210b0 4679 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4680 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4681 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4682 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4683 I(ImplicitOps | EmulateOnUD, em_sysenter),
4684 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4685 N, N,
73fba5f4
AK		 4686 N, N, N, N, N, N, N, N,
4687 /* 0x40 - 0x4F */
140bad89 4688 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4689 /* 0x50 - 0x5F */
4690 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4691 /* 0x60 - 0x6F */
aa97bb48
AK		 4692 N, N, N, N,
4693 N, N, N, N,
4694 N, N, N, N,
4695 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4696 /* 0x70 - 0x7F */
aa97bb48
AK		 4697 N, N, N, N,
4698 N, N, N, N,
4699 N, N, N, N,
4700 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4701 /* 0x80 - 0x8F */
58b7075d 4702 X16(D(SrcImm | NearBranch)),
73fba5f4 4703 /* 0x90 - 0x9F */
ee45b58e 4704 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4705 /* 0xA0 - 0xA7 */
1cd196ea 4706 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4707 II(ImplicitOps, em_cpuid, cpuid),
4708 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4709 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4710 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4711 /* 0xA8 - 0xAF */
1cd196ea 4712 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4713 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4714 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4715 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4716 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4717 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4718 /* 0xB0 - 0xB7 */
2fcf5c8a 4719 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4720 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4721 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4722 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4723 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4724 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4725 /* 0xB8 - 0xBF */
4726 N, N,
ce7faab2 4727 G(BitOp, group8),
11c363ba 4728 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4729 I(DstReg | SrcMem | ModRM, em_bsf_c),
4730 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4731 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4732 /* 0xC0 - 0xC7 */
e47a5f5f 4733 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4734 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4735 N, N, N, GD(0, &group9),
9299836e
AK		 4736 /* 0xC8 - 0xCF */
4737 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4738 /* 0xD0 - 0xDF */
4739 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4740 /* 0xE0 - 0xEF */
0a37027e
AW		 4741 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4742 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4743 /* 0xF0 - 0xFF */
4744 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4745};
4746
39f062ff
NA		 4747static const struct instr_dual instr_dual_0f_38_f0 = {
4748 I(DstReg | SrcMem | Mov, em_movbe), N
4749};
4750
4751static const struct instr_dual instr_dual_0f_38_f1 = {
4752 I(DstMem | SrcReg | Mov, em_movbe), N
4753};
4754
0bc5eedb 4755static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4756 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4757};
4758
4759static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4760 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4761};
4762
4763/*
4764 * Insns below are selected by the prefix which indexed by the third opcode
4765 * byte.
4766 */
4767static const struct opcode opcode_map_0f_38[256] = {
4768 /* 0x00 - 0x7f */
4769 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4770 /* 0x80 - 0xef */
4771 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4772 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4773 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4774 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4775 /* 0xf2 - 0xff */
4776 N, N, X4(N), X8(N)
0bc5eedb
BP		 4777};
4778
73fba5f4
AK		 4779#undef D
4780#undef N
4781#undef G
4782#undef GD
4783#undef I
aa97bb48 4784#undef GP
01de8b09 4785#undef EXT
2276b511 4786#undef MD
2b42fce6 4787#undef ID
73fba5f4 4788
8d8f4e9f 4789#undef D2bv
f6511935 4790#undef D2bvIP
8d8f4e9f 4791#undef I2bv
d7841a4b 4792#undef I2bvIP
d67fc27a 4793#undef I6ALU
8d8f4e9f 4794
9dac77fa 4795static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4796{
4797 unsigned size;
4798
9dac77fa 4799 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4800 if (size == 8)
4801 size = 4;
4802 return size;
4803}
4804
4805static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4806 unsigned size, bool sign_extension)
4807{
39f21ee5
AK		 4808 int rc = X86EMUL_CONTINUE;
4809
4810 op->type = OP_IMM;
4811 op->bytes = size;
9dac77fa 4812 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4813 /* NB. Immediates are sign-extended as necessary. */
4814 switch (op->bytes) {
4815 case 1:
e85a1085 4816 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4817 break;
4818 case 2:
e85a1085 4819 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4820 break;
4821 case 4:
e85a1085 4822 op->val = insn_fetch(s32, ctxt);
39f21ee5 4823 break;
5e2c6883
NA		 4824 case 8:
4825 op->val = insn_fetch(s64, ctxt);
4826 break;
39f21ee5
AK		 4827 }
4828 if (!sign_extension) {
4829 switch (op->bytes) {
4830 case 1:
4831 op->val &= 0xff;
4832 break;
4833 case 2:
4834 op->val &= 0xffff;
4835 break;
4836 case 4:
4837 op->val &= 0xffffffff;
4838 break;
4839 }
4840 }
4841done:
4842 return rc;
4843}
4844
a9945549
AK		 4845static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4846 unsigned d)
4847{
4848 int rc = X86EMUL_CONTINUE;
4849
4850 switch (d) {
4851 case OpReg:
2adb5ad9 4852 decode_register_operand(ctxt, op);
a9945549
AK		 4853 break;
4854 case OpImmUByte:
608aabe3 4855 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4856 break;
4857 case OpMem:
41ddf978 4858 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4859 mem_common:
4860 *op = ctxt->memop;
4861 ctxt->memopp = op;
96888977 4862 if (ctxt->d & BitOp)
a9945549
AK		 4863 fetch_bit_operand(ctxt);
4864 op->orig_val = op->val;
4865 break;
41ddf978 4866 case OpMem64:
aaa05f24 4867 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4868 goto mem_common;
a9945549
AK		 4869 case OpAcc:
4870 op->type = OP_REG;
4871 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4872 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4873 fetch_register_operand(op);
4874 op->orig_val = op->val;
4875 break;
820207c8
AK		 4876 case OpAccLo:
4877 op->type = OP_REG;
4878 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4879 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4880 fetch_register_operand(op);
4881 op->orig_val = op->val;
4882 break;
4883 case OpAccHi:
4884 if (ctxt->d & ByteOp) {
4885 op->type = OP_NONE;
4886 break;
4887 }
4888 op->type = OP_REG;
4889 op->bytes = ctxt->op_bytes;
4890 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4891 fetch_register_operand(op);
4892 op->orig_val = op->val;
4893 break;
a9945549
AK		 4894 case OpDI:
4895 op->type = OP_MEM;
4896 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4897 op->addr.mem.ea =
01485a22 4898 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4899 op->addr.mem.seg = VCPU_SREG_ES;
4900 op->val = 0;
b3356bf0 4901 op->count = 1;
a9945549
AK		 4902 break;
4903 case OpDX:
4904 op->type = OP_REG;
4905 op->bytes = 2;
dd856efa 4906 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4907 fetch_register_operand(op);
4908 break;
4dd6a57d 4909 case OpCL:
d29b9d7e 4910 op->type = OP_IMM;
4dd6a57d 4911 op->bytes = 1;
dd856efa 4912 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4913 break;
4914 case OpImmByte:
4915 rc = decode_imm(ctxt, op, 1, true);
4916 break;
4917 case OpOne:
d29b9d7e 4918 op->type = OP_IMM;
4dd6a57d
AK		 4919 op->bytes = 1;
4920 op->val = 1;
4921 break;
4922 case OpImm:
4923 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4924 break;
5e2c6883
NA		 4925 case OpImm64:
4926 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4927 break;
28867cee
AK		 4928 case OpMem8:
4929 ctxt->memop.bytes = 1;
660696d1 4930 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4931 ctxt->memop.addr.reg = decode_register(ctxt,
4932 ctxt->modrm_rm, true);
660696d1
GN		 4933 fetch_register_operand(&ctxt->memop);
4934 }
28867cee 4935 goto mem_common;
0fe59128
AK		 4936 case OpMem16:
4937 ctxt->memop.bytes = 2;
4938 goto mem_common;
4939 case OpMem32:
4940 ctxt->memop.bytes = 4;
4941 goto mem_common;
4942 case OpImmU16:
4943 rc = decode_imm(ctxt, op, 2, false);
4944 break;
4945 case OpImmU:
4946 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4947 break;
4948 case OpSI:
4949 op->type = OP_MEM;
4950 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4951 op->addr.mem.ea =
01485a22 4952 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4953 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4954 op->val = 0;
b3356bf0 4955 op->count = 1;
0fe59128 4956 break;
7fa57952
PB		 4957 case OpXLat:
4958 op->type = OP_MEM;
4959 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4960 op->addr.mem.ea =
01485a22 4961 address_mask(ctxt,
7fa57952
PB		 4962 reg_read(ctxt, VCPU_REGS_RBX) +
4963 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4964 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4965 op->val = 0;
4966 break;
0fe59128
AK		 4967 case OpImmFAddr:
4968 op->type = OP_IMM;
4969 op->addr.mem.ea = ctxt->_eip;
4970 op->bytes = ctxt->op_bytes + 2;
4971 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4972 break;
4973 case OpMemFAddr:
4974 ctxt->memop.bytes = ctxt->op_bytes + 2;
4975 goto mem_common;
c191a7a0 4976 case OpES:
d29b9d7e 4977 op->type = OP_IMM;
c191a7a0
AK		 4978 op->val = VCPU_SREG_ES;
4979 break;
4980 case OpCS:
d29b9d7e 4981 op->type = OP_IMM;
c191a7a0
AK		 4982 op->val = VCPU_SREG_CS;
4983 break;
4984 case OpSS:
d29b9d7e 4985 op->type = OP_IMM;
c191a7a0
AK		 4986 op->val = VCPU_SREG_SS;
4987 break;
4988 case OpDS:
d29b9d7e 4989 op->type = OP_IMM;
c191a7a0
AK		 4990 op->val = VCPU_SREG_DS;
4991 break;
4992 case OpFS:
d29b9d7e 4993 op->type = OP_IMM;
c191a7a0
AK		 4994 op->val = VCPU_SREG_FS;
4995 break;
4996 case OpGS:
d29b9d7e 4997 op->type = OP_IMM;
c191a7a0
AK		 4998 op->val = VCPU_SREG_GS;
4999 break;
a9945549
AK		 5000 case OpImplicit:
5001 /* Special instructions do their own operand decoding. */
5002 default:
5003 op->type = OP_NONE; /* Disable writeback. */
5004 break;
5005 }
5006
5007done:
5008 return rc;
5009}
5010
ef5d75cc 5011int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 5012{
dde7e6d1
AK		 5013 int rc = X86EMUL_CONTINUE;
5014 int mode = ctxt->mode;
46561646 5015 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 5016 bool op_prefix = false;
573e80fe 5017 bool has_seg_override = false;
46561646 5018 struct opcode opcode;
3853be26
WL		 5019 u16 dummy;
5020 struct desc_struct desc;
dde7e6d1 5021
f09ed83e
AK		 5022 ctxt->memop.type = OP_NONE;
5023 ctxt->memopp = NULL;
9dac77fa 5024 ctxt->_eip = ctxt->eip;
17052f16
PB		 5025 ctxt->fetch.ptr = ctxt->fetch.data;
5026 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 5027 ctxt->opcode_len = 1;
dc25e89e 5028 if (insn_len > 0)
9dac77fa 5029 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 5030 else {
9506d57d 5031 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 5032 if (rc != X86EMUL_CONTINUE)
5033 return rc;
5034 }
dde7e6d1
AK		 5035
5036 switch (mode) {
5037 case X86EMUL_MODE_REAL:
5038 case X86EMUL_MODE_VM86:
3853be26
WL		 5039 def_op_bytes = def_ad_bytes = 2;
5040 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5041 if (desc.d)
5042 def_op_bytes = def_ad_bytes = 4;
5043 break;
dde7e6d1
AK		 5044 case X86EMUL_MODE_PROT16:
5045 def_op_bytes = def_ad_bytes = 2;
5046 break;
5047 case X86EMUL_MODE_PROT32:
5048 def_op_bytes = def_ad_bytes = 4;
5049 break;
5050#ifdef CONFIG_X86_64
5051 case X86EMUL_MODE_PROT64:
5052 def_op_bytes = 4;
5053 def_ad_bytes = 8;
5054 break;
5055#endif
5056 default:
1d2887e2 5057 return EMULATION_FAILED;
dde7e6d1
AK		 5058 }
5059
9dac77fa
AK		 5060 ctxt->op_bytes = def_op_bytes;
5061 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 5062
5063 /* Legacy prefixes. */
5064 for (;;) {
e85a1085 5065 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 5066 case 0x66: /* operand-size override */
0d7cdee8 5067 op_prefix = true;
dde7e6d1 5068 /* switch between 2/4 bytes */
9dac77fa 5069 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 5070 break;
5071 case 0x67: /* address-size override */
5072 if (mode == X86EMUL_MODE_PROT64)
5073 /* switch between 4/8 bytes */
9dac77fa 5074 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 5075 else
5076 /* switch between 2/4 bytes */
9dac77fa 5077 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5078 break;
5079 case 0x26: /* ES override */
5080 case 0x2e: /* CS override */
5081 case 0x36: /* SS override */
5082 case 0x3e: /* DS override */
573e80fe
BD		 5083 has_seg_override = true;
5084 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 5085 break;
5086 case 0x64: /* FS override */
5087 case 0x65: /* GS override */
573e80fe
BD		 5088 has_seg_override = true;
5089 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 5090 break;
5091 case 0x40 ... 0x4f: /* REX */
5092 if (mode != X86EMUL_MODE_PROT64)
5093 goto done_prefixes;
9dac77fa 5094 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5095 continue;
5096 case 0xf0: /* LOCK */
9dac77fa 5097 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5098 break;
5099 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5100 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5101 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5102 break;
5103 default:
5104 goto done_prefixes;
5105 }
5106
5107 /* Any legacy prefix after a REX prefix nullifies its effect. */
5108
9dac77fa 5109 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5110 }
5111
5112done_prefixes:
5113
5114 /* REX prefix. */
9dac77fa
AK		 5115 if (ctxt->rex_prefix & 8)
5116 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5117
5118 /* Opcode byte(s). */
9dac77fa 5119 opcode = opcode_table[ctxt->b];
d3ad6243 5120 /* Two-byte opcode? */
9dac77fa 5121 if (ctxt->b == 0x0f) {
1ce19dc1 5122 ctxt->opcode_len = 2;
e85a1085 5123 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5124 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5125
5126 /* 0F_38 opcode map */
5127 if (ctxt->b == 0x38) {
5128 ctxt->opcode_len = 3;
5129 ctxt->b = insn_fetch(u8, ctxt);
5130 opcode = opcode_map_0f_38[ctxt->b];
5131 }
dde7e6d1 5132 }
9dac77fa 5133 ctxt->d = opcode.flags;
dde7e6d1 5134
9f4260e7
TY		 5135 if (ctxt->d & ModRM)
5136 ctxt->modrm = insn_fetch(u8, ctxt);
5137
7fe864dc
NA		 5138 /* vex-prefix instructions are not implemented */
5139 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5140 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5141 ctxt->d = NotImpl;
5142 }
5143
9dac77fa
AK		 5144 while (ctxt->d & GroupMask) {
5145 switch (ctxt->d & GroupMask) {
46561646 5146 case Group:
9dac77fa 5147 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5148 opcode = opcode.u.group[goffset];
5149 break;
5150 case GroupDual:
9dac77fa
AK		 5151 goffset = (ctxt->modrm >> 3) & 7;
5152 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5153 opcode = opcode.u.gdual->mod3[goffset];
5154 else
5155 opcode = opcode.u.gdual->mod012[goffset];
5156 break;
5157 case RMExt:
9dac77fa 5158 goffset = ctxt->modrm & 7;
01de8b09 5159 opcode = opcode.u.group[goffset];
46561646
AK		 5160 break;
5161 case Prefix:
9dac77fa 5162 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5163 return EMULATION_FAILED;
9dac77fa 5164 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5165 switch (simd_prefix) {
5166 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5167 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5168 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5169 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5170 }
5171 break;
045a282c
GN		 5172 case Escape:
5173 if (ctxt->modrm > 0xbf)
5174 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5175 else
5176 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5177 break;
39f062ff
NA		 5178 case InstrDual:
5179 if ((ctxt->modrm >> 6) == 3)
5180 opcode = opcode.u.idual->mod3;
5181 else
5182 opcode = opcode.u.idual->mod012;
5183 break;
2276b511
NA		 5184 case ModeDual:
5185 if (ctxt->mode == X86EMUL_MODE_PROT64)
5186 opcode = opcode.u.mdual->mode64;
5187 else
5188 opcode = opcode.u.mdual->mode32;
5189 break;
46561646 5190 default:
1d2887e2 5191 return EMULATION_FAILED;
0d7cdee8 5192 }
46561646 5193
b1ea50b2 5194 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5195 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5196 }
5197
e24186e0
PB		 5198 /* Unrecognised? */
5199 if (ctxt->d == 0)
5200 return EMULATION_FAILED;
5201
9dac77fa 5202 ctxt->execute = opcode.u.execute;
dde7e6d1 5203
3a6095a0
NA		 5204 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5205 return EMULATION_FAILED;
5206
d40a6898 5207 if (unlikely(ctxt->d &
ed9aad21
NA		 5208 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5209 No16))) {
d40a6898
PB		 5210 /*
5211 * These are copied unconditionally here, and checked unconditionally
5212 * in x86_emulate_insn.
5213 */
5214 ctxt->check_perm = opcode.check_perm;
5215 ctxt->intercept = opcode.intercept;
dde7e6d1 5216
d40a6898
PB		 5217 if (ctxt->d & NotImpl)
5218 return EMULATION_FAILED;
d867162c 5219
58b7075d
NA		 5220 if (mode == X86EMUL_MODE_PROT64) {
5221 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5222 ctxt->op_bytes = 8;
5223 else if (ctxt->d & NearBranch)
5224 ctxt->op_bytes = 8;
5225 }
7f9b4b75 5226
d40a6898
PB		 5227 if (ctxt->d & Op3264) {
5228 if (mode == X86EMUL_MODE_PROT64)
5229 ctxt->op_bytes = 8;
5230 else
5231 ctxt->op_bytes = 4;
5232 }
5233
ed9aad21
NA		 5234 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5235 ctxt->op_bytes = 4;
5236
d40a6898
PB		 5237 if (ctxt->d & Sse)
5238 ctxt->op_bytes = 16;
5239 else if (ctxt->d & Mmx)
5240 ctxt->op_bytes = 8;
5241 }
1253791d 5242
dde7e6d1 5243 /* ModRM and SIB bytes. */
9dac77fa 5244 if (ctxt->d & ModRM) {
f09ed83e 5245 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5246 if (!has_seg_override) {
5247 has_seg_override = true;
5248 ctxt->seg_override = ctxt->modrm_seg;
5249 }
9dac77fa 5250 } else if (ctxt->d & MemAbs)
f09ed83e 5251 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5252 if (rc != X86EMUL_CONTINUE)
5253 goto done;
5254
573e80fe
BD		 5255 if (!has_seg_override)
5256 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5257
573e80fe 5258 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5259
dde7e6d1
AK		 5260 /*
5261 * Decode and fetch the source operand: register, memory
5262 * or immediate.
5263 */
0fe59128 5264 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5265 if (rc != X86EMUL_CONTINUE)
5266 goto done;
5267
dde7e6d1
AK		 5268 /*
5269 * Decode and fetch the second source operand: register, memory
5270 * or immediate.
5271 */
4dd6a57d 5272 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5273 if (rc != X86EMUL_CONTINUE)
5274 goto done;
5275
dde7e6d1 5276 /* Decode and fetch the destination operand: register or memory. */
a9945549 5277 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5278
d9092f52 5279 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5280 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5281 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5282
a430c916 5283done:
1d2887e2 5284 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5285}
5286
1cb3f3ae
XG		 5287bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5288{
5289 return ctxt->d & PageTable;
5290}
5291
3e2f65d5
GN		 5292static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5293{
3e2f65d5
GN		 5294 /* The second termination condition only applies for REPE
5295 * and REPNE. Test if the repeat string operation prefix is
5296 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5297 * corresponding termination condition according to:
5298 * - if REPE/REPZ and ZF = 0 then done
5299 * - if REPNE/REPNZ and ZF = 1 then done
5300 */
9dac77fa
AK		 5301 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5302 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5303 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5304 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5305 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5306 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5307 return true;
5308
5309 return false;
5310}
5311
cbe2c9d3
AK		 5312static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5313{
aabba3c6 5314 int rc;
cbe2c9d3 5315
aabba3c6 5316 rc = asm_safe("fwait");
cbe2c9d3 5317
aabba3c6 5318 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5319 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5320
5321 return X86EMUL_CONTINUE;
5322}
5323
5324static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5325 struct operand *op)
5326{
5327 if (op->type == OP_MM)
5328 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5329}
5330
e28bbd44
AK		 5331static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5332{
5333 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5334
b9fa409b
AK		 5335 if (!(ctxt->d & ByteOp))
5336 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5337
e28bbd44 5338 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae 5339 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
f5caf621 5340 [fastop]"+S"(fop), ASM_CALL_CONSTRAINT
b8c0b6ae 5341 : "c"(ctxt->src2.val));
4548f63e 5342
e28bbd44 5343 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5344 if (!fop) /* exception is returned in fop variable */
5345 return emulate_de(ctxt);
e28bbd44
AK		 5346 return X86EMUL_CONTINUE;
5347}
dd856efa 5348
1498507a
BD		 5349void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5350{
573e80fe
BD		 5351 memset(&ctxt->rip_relative, 0,
5352 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5353
1498507a
BD		 5354 ctxt->io_read.pos = 0;
5355 ctxt->io_read.end = 0;
1498507a
BD		 5356 ctxt->mem_read.end = 0;
5357}
5358
7b105ca2 5359int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5360{
0225fb50 5361 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5362 int rc = X86EMUL_CONTINUE;
9dac77fa 5363 int saved_dst_type = ctxt->dst.type;
6ed071f0 5364 unsigned emul_flags;
8b4caf66 5365
9dac77fa 5366 ctxt->mem_read.pos = 0;
310b5d30 5367
e24186e0
PB		 5368 /* LOCK prefix is allowed only with some instructions */
5369 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5370 rc = emulate_ud(ctxt);
1161624f
GN		 5371 goto done;
5372 }
5373
e24186e0 5374 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5375 rc = emulate_ud(ctxt);
d380a5e4
GN		 5376 goto done;
5377 }
5378
6ed071f0 5379 emul_flags = ctxt->ops->get_hflags(ctxt);
d40a6898
PB		 5380 if (unlikely(ctxt->d &
5381 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5382 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5383 (ctxt->d & Undefined)) {
5384 rc = emulate_ud(ctxt);
5385 goto done;
5386 }
1253791d 5387
d40a6898
PB		 5388 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5389 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5390 rc = emulate_ud(ctxt);
cbe2c9d3 5391 goto done;
d40a6898 5392 }
cbe2c9d3 5393
d40a6898
PB		 5394 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5395 rc = emulate_nm(ctxt);
c4f035c6 5396 goto done;
d40a6898 5397 }
c4f035c6 5398
d40a6898
PB		 5399 if (ctxt->d & Mmx) {
5400 rc = flush_pending_x87_faults(ctxt);
5401 if (rc != X86EMUL_CONTINUE)
5402 goto done;
5403 /*
5404 * Now that we know the fpu is exception safe, we can fetch
5405 * operands from it.
5406 */
5407 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5408 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5409 if (!(ctxt->d & Mov))
5410 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5411 }
e92805ac 5412
6ed071f0 5413 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5414 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5415 X86_ICPT_PRE_EXCEPT);
5416 if (rc != X86EMUL_CONTINUE)
5417 goto done;
5418 }
8ea7d6ae 5419
64a38292
NA		 5420 /* Instruction can only be executed in protected mode */
5421 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5422 rc = emulate_ud(ctxt);
5423 goto done;
5424 }
5425
d40a6898
PB		 5426 /* Privileged instruction can be executed only in CPL=0 */
5427 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5428 if (ctxt->d & PrivUD)
5429 rc = emulate_ud(ctxt);
5430 else
5431 rc = emulate_gp(ctxt, 0);
d09beabd 5432 goto done;
d40a6898 5433 }
d09beabd 5434
d40a6898 5435 /* Do instruction specific permission checks */
685bbf4a 5436 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5437 rc = ctxt->check_perm(ctxt);
5438 if (rc != X86EMUL_CONTINUE)
5439 goto done;
5440 }
5441
6ed071f0 5442 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5443 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5444 X86_ICPT_POST_EXCEPT);
5445 if (rc != X86EMUL_CONTINUE)
5446 goto done;
5447 }
5448
5449 if (ctxt->rep_prefix && (ctxt->d & String)) {
5450 /* All REP prefixes have the same first termination condition */
5451 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5452 string_registers_quirk(ctxt);
d40a6898 5453 ctxt->eip = ctxt->_eip;
0efb0440 5454 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5455 goto done;
5456 }
b9fa9d6b 5457 }
b9fa9d6b
AK		 5458 }
5459
9dac77fa
AK		 5460 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5461 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5462 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5463 if (rc != X86EMUL_CONTINUE)
8b4caf66 5464 goto done;
9dac77fa 5465 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5466 }
5467
9dac77fa
AK		 5468 if (ctxt->src2.type == OP_MEM) {
5469 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5470 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5471 if (rc != X86EMUL_CONTINUE)
5472 goto done;
5473 }
5474
9dac77fa 5475 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5476 goto special_insn;
5477
5478
9dac77fa 5479 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5480 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5481 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5482 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5483 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5484 if (!(ctxt->d & NoWrite) &&
5485 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5486 ctxt->exception.vector == PF_VECTOR)
5487 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5488 goto done;
c205fb7d 5489 }
038e51de 5490 }
4ff6f8e6
PB		 5491 /* Copy full 64-bit value for CMPXCHG8B. */
5492 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5493
018a98db
AK		 5494special_insn:
5495
6ed071f0 5496 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5497 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5498 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5499 if (rc != X86EMUL_CONTINUE)
5500 goto done;
5501 }
5502
b9a1ecb9 5503 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5504 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5505 else
0efb0440 5506 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5507
9dac77fa 5508 if (ctxt->execute) {
e28bbd44
AK		 5509 if (ctxt->d & Fastop) {
5510 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5511 rc = fastop(ctxt, fop);
5512 if (rc != X86EMUL_CONTINUE)
5513 goto done;
5514 goto writeback;
5515 }
9dac77fa 5516 rc = ctxt->execute(ctxt);
ef65c889
AK		 5517 if (rc != X86EMUL_CONTINUE)
5518 goto done;
5519 goto writeback;
5520 }
5521
1ce19dc1 5522 if (ctxt->opcode_len == 2)
6aa8b732 5523 goto twobyte_insn;
0bc5eedb
BP		 5524 else if (ctxt->opcode_len == 3)
5525 goto threebyte_insn;
6aa8b732 5526
9dac77fa 5527 switch (ctxt->b) {
b2833e3c 5528 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5529 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5530 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5531 break;
7e0b54b1 5532 case 0x8d: /* lea r16/r32, m */
9dac77fa 5533 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5534 break;
3d9e77df 5535 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5536 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5537 ctxt->dst.type = OP_NONE;
5538 else
5539 rc = em_xchg(ctxt);
e4f973ae 5540 break;
e8b6fa70 5541 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5542 switch (ctxt->op_bytes) {
5543 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5544 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5545 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5546 }
5547 break;
6e154e56 5548 case 0xcc: /* int3 */
5c5df76b
TY		 5549 rc = emulate_int(ctxt, 3);
5550 break;
6e154e56 5551 case 0xcd: /* int n */
9dac77fa 5552 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5553 break;
5554 case 0xce: /* into */
0efb0440 5555 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5556 rc = emulate_int(ctxt, 4);
6e154e56 5557 break;
1a52e051 5558 case 0xe9: /* jmp rel */
db5b0762 5559 case 0xeb: /* jmp rel short */
234f3ce4 5560 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5561 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5562 break;
111de5d6 5563 case 0xf4: /* hlt */
6c3287f7 5564 ctxt->ops->halt(ctxt);
19fdfa0d 5565 break;
111de5d6
AK		 5566 case 0xf5: /* cmc */
5567 /* complement carry flag from eflags reg */
0efb0440 5568 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5569 break;
5570 case 0xf8: /* clc */
0efb0440 5571 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5572 break;
8744aa9a 5573 case 0xf9: /* stc */
0efb0440 5574 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5575 break;
fb4616f4 5576 case 0xfc: /* cld */
0efb0440 5577 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5578 break;
5579 case 0xfd: /* std */
0efb0440 5580 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5581 break;
91269b8f
AK		 5582 default:
5583 goto cannot_emulate;
6aa8b732 5584 }
018a98db 5585
7d9ddaed
AK		 5586 if (rc != X86EMUL_CONTINUE)
5587 goto done;
5588
018a98db 5589writeback:
fb32b1ed
AK		 5590 if (ctxt->d & SrcWrite) {
5591 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5592 rc = writeback(ctxt, &ctxt->src);
5593 if (rc != X86EMUL_CONTINUE)
5594 goto done;
5595 }
ee212297
NA		 5596 if (!(ctxt->d & NoWrite)) {
5597 rc = writeback(ctxt, &ctxt->dst);
5598 if (rc != X86EMUL_CONTINUE)
5599 goto done;
5600 }
018a98db 5601
5cd21917
GN		 5602 /*
5603 * restore dst type in case the decoding will be reused
5604 * (happens for string instruction )
5605 */
9dac77fa 5606 ctxt->dst.type = saved_dst_type;
5cd21917 5607
9dac77fa 5608 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5609 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5610
9dac77fa 5611 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5612 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5613
9dac77fa 5614 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5615 unsigned int count;
9dac77fa 5616 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5617 if ((ctxt->d & SrcMask) == SrcSI)
5618 count = ctxt->src.count;
5619 else
5620 count = ctxt->dst.count;
01485a22 5621 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5622
d2ddd1c4
GN		 5623 if (!string_insn_completed(ctxt)) {
5624 /*
5625 * Re-enter guest when pio read ahead buffer is empty
5626 * or, if it is not used, after each 1024 iteration.
5627 */
dd856efa 5628 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5629 (r->end == 0 || r->end != r->pos)) {
5630 /*
5631 * Reset read cache. Usually happens before
5632 * decode, but since instruction is restarted
5633 * we have to do it here.
5634 */
9dac77fa 5635 ctxt->mem_read.end = 0;
dd856efa 5636 writeback_registers(ctxt);
d2ddd1c4
GN		 5637 return EMULATION_RESTART;
5638 }
5639 goto done; /* skip rip writeback */
0fa6ccbd 5640 }
0efb0440 5641 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5642 }
d2ddd1c4 5643
9dac77fa 5644 ctxt->eip = ctxt->_eip;
018a98db
AK		 5645
5646done:
e0ad0b47
PB		 5647 if (rc == X86EMUL_PROPAGATE_FAULT) {
5648 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5649 ctxt->have_exception = true;
e0ad0b47 5650 }
775fde86
JR		 5651 if (rc == X86EMUL_INTERCEPTED)
5652 return EMULATION_INTERCEPTED;
5653
dd856efa
AK		 5654 if (rc == X86EMUL_CONTINUE)
5655 writeback_registers(ctxt);
5656
d2ddd1c4 5657 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5658
5659twobyte_insn:
9dac77fa 5660 switch (ctxt->b) {
018a98db 5661 case 0x09: /* wbinvd */
cfb22375 5662 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5663 break;
5664 case 0x08: /* invd */
018a98db
AK		 5665 case 0x0d: /* GrpP (prefetch) */
5666 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5667 case 0x1f: /* nop */
018a98db
AK		 5668 break;
5669 case 0x20: /* mov cr, reg */
9dac77fa 5670 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5671 break;
6aa8b732 5672 case 0x21: /* mov from dr to reg */
9dac77fa 5673 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5674 break;
6aa8b732 5675 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5676 if (test_cc(ctxt->b, ctxt->eflags))
5677 ctxt->dst.val = ctxt->src.val;
b91aa14d 5678 else if (ctxt->op_bytes != 4)
9dac77fa 5679 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5680 break;
b2833e3c 5681 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5682 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5683 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5684 break;
ee45b58e 5685 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5686 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5687 break;
6aa8b732 5688 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5689 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5690 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5691 : (u16) ctxt->src.val;
6aa8b732 5692 break;
6aa8b732 5693 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5694 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5695 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5696 (s16) ctxt->src.val;
6aa8b732 5697 break;
91269b8f
AK		 5698 default:
5699 goto cannot_emulate;
6aa8b732 5700 }
7d9ddaed 5701
0bc5eedb
BP		 5702threebyte_insn:
5703
7d9ddaed
AK		 5704 if (rc != X86EMUL_CONTINUE)
5705 goto done;
5706
6aa8b732
AK		 5707 goto writeback;
5708
5709cannot_emulate:
a0c0ab2f 5710 return EMULATION_FAILED;
6aa8b732 5711}
dd856efa
AK		 5712
5713void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5714{
5715 invalidate_registers(ctxt);
5716}
5717
5718void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5719{
5720 writeback_registers(ctxt);
5721}
0f89b207
TL		 5722
5723bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5724{
5725 if (ctxt->rep_prefix && (ctxt->d & String))
5726 return false;
5727
5728 if (ctxt->d & TwoMemOp)
5729 return false;
5730
5731 return true;
5732}
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