]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/emulate.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86 emulator: Use opcode::execute for MOV to cr/dr
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
0fe59128
AK		 60
61#define OpBits 5 /* Width of operand field */
b1ea50b2 62#define OpMask ((1ull << OpBits) - 1)
a9945549 63
6aa8b732
AK		 64/*
65 * Opcode effective-address decode tables.
66 * Note that we only emulate instructions that have at least one memory
67 * operand (excluding implicit stack references). We assume that stack
68 * references and instruction fetches will never occur in special memory
69 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
70 * not be handled.
71 */
72
73/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 74#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 75/* Destination operand type. */
a9945549
AK		 76#define DstShift 1
77#define ImplicitOps (OpImplicit << DstShift)
78#define DstReg (OpReg << DstShift)
79#define DstMem (OpMem << DstShift)
80#define DstAcc (OpAcc << DstShift)
81#define DstDI (OpDI << DstShift)
82#define DstMem64 (OpMem64 << DstShift)
83#define DstImmUByte (OpImmUByte << DstShift)
84#define DstDX (OpDX << DstShift)
85#define DstMask (OpMask << DstShift)
6aa8b732 86/* Source operand type. */
0fe59128
AK		 87#define SrcShift 6
88#define SrcNone (OpNone << SrcShift)
89#define SrcReg (OpReg << SrcShift)
90#define SrcMem (OpMem << SrcShift)
91#define SrcMem16 (OpMem16 << SrcShift)
92#define SrcMem32 (OpMem32 << SrcShift)
93#define SrcImm (OpImm << SrcShift)
94#define SrcImmByte (OpImmByte << SrcShift)
95#define SrcOne (OpOne << SrcShift)
96#define SrcImmUByte (OpImmUByte << SrcShift)
97#define SrcImmU (OpImmU << SrcShift)
98#define SrcSI (OpSI << SrcShift)
99#define SrcImmFAddr (OpImmFAddr << SrcShift)
100#define SrcMemFAddr (OpMemFAddr << SrcShift)
101#define SrcAcc (OpAcc << SrcShift)
102#define SrcImmU16 (OpImmU16 << SrcShift)
103#define SrcDX (OpDX << SrcShift)
104#define SrcMask (OpMask << SrcShift)
221192bd
MT		 105#define BitOp (1<<11)
106#define MemAbs (1<<12) /* Memory operand is absolute displacement */
107#define String (1<<13) /* String instruction (rep capable) */
108#define Stack (1<<14) /* Stack instruction (push/pop) */
109#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
110#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
111#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
112#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
113#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
114#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 115/* Generic ModRM decode. */
116#define ModRM (1<<19)
117/* Destination is only written; never read. */
118#define Mov (1<<20)
d8769fed 119/* Misc flags */
8ea7d6ae 120#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 121#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 122#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 123#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 124#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 125#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 126#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 127#define No64 (1<<28)
d5ae7ce8 128#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 129/* Source 2 operand type */
d5ae7ce8 130#define Src2Shift (30)
4dd6a57d
AK		 131#define Src2None (OpNone << Src2Shift)
132#define Src2CL (OpCL << Src2Shift)
133#define Src2ImmByte (OpImmByte << Src2Shift)
134#define Src2One (OpOne << Src2Shift)
135#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 136#define Src2ES (OpES << Src2Shift)
137#define Src2CS (OpCS << Src2Shift)
138#define Src2SS (OpSS << Src2Shift)
139#define Src2DS (OpDS << Src2Shift)
140#define Src2FS (OpFS << Src2Shift)
141#define Src2GS (OpGS << Src2Shift)
4dd6a57d 142#define Src2Mask (OpMask << Src2Shift)
6aa8b732 143
d0e53325
AK		 144#define X2(x...) x, x
145#define X3(x...) X2(x), x
146#define X4(x...) X2(x), X2(x)
147#define X5(x...) X4(x), x
148#define X6(x...) X4(x), X2(x)
149#define X7(x...) X4(x), X3(x)
150#define X8(x...) X4(x), X4(x)
151#define X16(x...) X8(x), X8(x)
83babbca 152
d65b1dee 153struct opcode {
b1ea50b2
AK		 154 u64 flags : 56;
155 u64 intercept : 8;
120df890 156 union {
ef65c889 157 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 158 struct opcode *group;
159 struct group_dual *gdual;
0d7cdee8 160 struct gprefix *gprefix;
120df890 161 } u;
d09beabd 162 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 163};
164
165struct group_dual {
166 struct opcode mod012[8];
167 struct opcode mod3[8];
d65b1dee
AK		 168};
169
0d7cdee8
AK		 170struct gprefix {
171 struct opcode pfx_no;
172 struct opcode pfx_66;
173 struct opcode pfx_f2;
174 struct opcode pfx_f3;
175};
176
6aa8b732 177/* EFLAGS bit definitions. */
d4c6a154
GN		 178#define EFLG_ID (1<<21)
179#define EFLG_VIP (1<<20)
180#define EFLG_VIF (1<<19)
181#define EFLG_AC (1<<18)
b1d86143
AP		 182#define EFLG_VM (1<<17)
183#define EFLG_RF (1<<16)
d4c6a154
GN		 184#define EFLG_IOPL (3<<12)
185#define EFLG_NT (1<<14)
6aa8b732
AK		 186#define EFLG_OF (1<<11)
187#define EFLG_DF (1<<10)
b1d86143 188#define EFLG_IF (1<<9)
d4c6a154 189#define EFLG_TF (1<<8)
6aa8b732
AK		 190#define EFLG_SF (1<<7)
191#define EFLG_ZF (1<<6)
192#define EFLG_AF (1<<4)
193#define EFLG_PF (1<<2)
194#define EFLG_CF (1<<0)
195
62bd430e
MG		 196#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
197#define EFLG_RESERVED_ONE_MASK 2
198
6aa8b732
AK		 199/*
200 * Instruction emulation:
201 * Most instructions are emulated directly via a fragment of inline assembly
202 * code. This allows us to save/restore EFLAGS and thus very easily pick up
203 * any modified flags.
204 */
205
05b3e0c2 206#if defined(CONFIG_X86_64)
6aa8b732
AK		 207#define _LO32 "k" /* force 32-bit operand */
208#define _STK "%%rsp" /* stack pointer */
209#elif defined(__i386__)
210#define _LO32 "" /* force 32-bit operand */
211#define _STK "%%esp" /* stack pointer */
212#endif
213
214/*
215 * These EFLAGS bits are restored from saved value during emulation, and
216 * any changes are written back to the saved value after emulation.
217 */
218#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
219
220/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 221#define _PRE_EFLAGS(_sav, _msk, _tmp) \
222 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
223 "movl %"_sav",%"_LO32 _tmp"; " \
224 "push %"_tmp"; " \
225 "push %"_tmp"; " \
226 "movl %"_msk",%"_LO32 _tmp"; " \
227 "andl %"_LO32 _tmp",("_STK"); " \
228 "pushf; " \
229 "notl %"_LO32 _tmp"; " \
230 "andl %"_LO32 _tmp",("_STK"); " \
231 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
232 "pop %"_tmp"; " \
233 "orl %"_LO32 _tmp",("_STK"); " \
234 "popf; " \
235 "pop %"_sav"; "
6aa8b732
AK		 236
237/* After executing instruction: write-back necessary bits in EFLAGS. */
238#define _POST_EFLAGS(_sav, _msk, _tmp) \
239 /* _sav |= EFLAGS & _msk; */ \
240 "pushf; " \
241 "pop %"_tmp"; " \
242 "andl %"_msk",%"_LO32 _tmp"; " \
243 "orl %"_LO32 _tmp",%"_sav"; "
244
dda96d8f
AK		 245#ifdef CONFIG_X86_64
246#define ON64(x) x
247#else
248#define ON64(x)
249#endif
250
a31b9cea 251#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 252 do { \
253 __asm__ __volatile__ ( \
254 _PRE_EFLAGS("0", "4", "2") \
255 _op _suffix " %"_x"3,%1; " \
256 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 257 : "=m" ((ctxt)->eflags), \
258 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 259 "=&r" (_tmp) \
a31b9cea 260 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 261 } while (0)
6b7ad61f
AK		 262
263
6aa8b732 264/* Raw emulation: instruction has two explicit operands. */
a31b9cea 265#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 266 do { \
267 unsigned long _tmp; \
268 \
a31b9cea 269 switch ((ctxt)->dst.bytes) { \
6b7ad61f 270 case 2: \
a31b9cea 271 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 272 break; \
273 case 4: \
a31b9cea 274 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 275 break; \
276 case 8: \
a31b9cea 277 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 278 break; \
279 } \
6aa8b732
AK		 280 } while (0)
281
a31b9cea 282#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 283 do { \
6b7ad61f 284 unsigned long _tmp; \
a31b9cea 285 switch ((ctxt)->dst.bytes) { \
6aa8b732 286 case 1: \
a31b9cea 287 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 288 break; \
289 default: \
a31b9cea 290 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 291 _wx, _wy, _lx, _ly, _qx, _qy); \
292 break; \
293 } \
294 } while (0)
295
296/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 297#define emulate_2op_SrcB(ctxt, _op) \
298 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 299
300/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 301#define emulate_2op_SrcV(ctxt, _op) \
302 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 303
304/* Source operand is word, long or quad sized. */
a31b9cea
AK		 305#define emulate_2op_SrcV_nobyte(ctxt, _op) \
306 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 307
d175226a 308/* Instruction has three operands and one operand is stored in ECX register */
29053a60 309#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 310 do { \
311 unsigned long _tmp; \
761441b9
AK		 312 _type _clv = (ctxt)->src2.val; \
313 _type _srcv = (ctxt)->src.val; \
314 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 315 \
316 __asm__ __volatile__ ( \
317 _PRE_EFLAGS("0", "5", "2") \
318 _op _suffix " %4,%1 \n" \
319 _POST_EFLAGS("0", "5", "2") \
761441b9 320 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 321 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
322 ); \
323 \
761441b9
AK		 324 (ctxt)->src2.val = (unsigned long) _clv; \
325 (ctxt)->src2.val = (unsigned long) _srcv; \
326 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 327 } while (0)
328
761441b9 329#define emulate_2op_cl(ctxt, _op) \
7295261c 330 do { \
761441b9 331 switch ((ctxt)->dst.bytes) { \
7295261c 332 case 2: \
29053a60 333 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 334 break; \
335 case 4: \
29053a60 336 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 337 break; \
338 case 8: \
29053a60 339 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 340 break; \
341 } \
d175226a
GT		 342 } while (0)
343
d1eef45d 344#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 345 do { \
346 unsigned long _tmp; \
347 \
dda96d8f
AK		 348 __asm__ __volatile__ ( \
349 _PRE_EFLAGS("0", "3", "2") \
350 _op _suffix " %1; " \
351 _POST_EFLAGS("0", "3", "2") \
d1eef45d 352 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 353 "=&r" (_tmp) \
354 : "i" (EFLAGS_MASK)); \
355 } while (0)
356
357/* Instruction has only one explicit operand (no source operand). */
d1eef45d 358#define emulate_1op(ctxt, _op) \
dda96d8f 359 do { \
d1eef45d
AK		 360 switch ((ctxt)->dst.bytes) { \
361 case 1: __emulate_1op(ctxt, _op, "b"); break; \
362 case 2: __emulate_1op(ctxt, _op, "w"); break; \
363 case 4: __emulate_1op(ctxt, _op, "l"); break; \
364 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 365 } \
366 } while (0)
367
e8f2b1d6 368#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 369 do { \
370 unsigned long _tmp; \
e8f2b1d6
AK		 371 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
372 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 373 \
374 __asm__ __volatile__ ( \
375 _PRE_EFLAGS("0", "5", "1") \
376 "1: \n\t" \
377 _op _suffix " %6; " \
378 "2: \n\t" \
379 _POST_EFLAGS("0", "5", "1") \
380 ".pushsection .fixup,\"ax\" \n\t" \
381 "3: movb $1, %4 \n\t" \
382 "jmp 2b \n\t" \
383 ".popsection \n\t" \
384 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 385 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
386 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
387 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
388 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 389 } while (0)
390
3f9f53b0 391/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 392#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 393 do { \
e8f2b1d6 394 switch((ctxt)->src.bytes) { \
7295261c 395 case 1: \
e8f2b1d6 396 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 397 break; \
398 case 2: \
e8f2b1d6 399 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 400 break; \
401 case 4: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 403 break; \
404 case 8: ON64( \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 406 break; \
407 } \
408 } while (0)
409
8a76d7f2
JR		 410static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
411 enum x86_intercept intercept,
412 enum x86_intercept_stage stage)
413{
414 struct x86_instruction_info info = {
415 .intercept = intercept,
9dac77fa
AK		 416 .rep_prefix = ctxt->rep_prefix,
417 .modrm_mod = ctxt->modrm_mod,
418 .modrm_reg = ctxt->modrm_reg,
419 .modrm_rm = ctxt->modrm_rm,
420 .src_val = ctxt->src.val64,
421 .src_bytes = ctxt->src.bytes,
422 .dst_bytes = ctxt->dst.bytes,
423 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 424 .next_rip = ctxt->eip,
425 };
426
2953538e 427 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 428}
429
9dac77fa 430static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 431{
9dac77fa 432 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 433}
434
6aa8b732 435/* Access/update address held in a register, based on addressing mode. */
e4706772 436static inline unsigned long
9dac77fa 437address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 438{
9dac77fa 439 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 440 return reg;
441 else
9dac77fa 442 return reg & ad_mask(ctxt);
e4706772
HH		 443}
444
445static inline unsigned long
9dac77fa 446register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 447{
9dac77fa 448 return address_mask(ctxt, reg);
e4706772
HH		 449}
450
7a957275 451static inline void
9dac77fa 452register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 453{
9dac77fa 454 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 455 *reg += inc;
456 else
9dac77fa 457 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 458}
6aa8b732 459
9dac77fa 460static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 461{
9dac77fa 462 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 463}
098c937b 464
56697687
AK		 465static u32 desc_limit_scaled(struct desc_struct *desc)
466{
467 u32 limit = get_desc_limit(desc);
468
469 return desc->g ? (limit << 12) | 0xfff : limit;
470}
471
9dac77fa 472static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 473{
9dac77fa
AK		 474 ctxt->has_seg_override = true;
475 ctxt->seg_override = seg;
7a5b56df
AK		 476}
477
7b105ca2 478static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 479{
480 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
481 return 0;
482
7b105ca2 483 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 484}
485
9dac77fa 486static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 487{
9dac77fa 488 if (!ctxt->has_seg_override)
7a5b56df
AK		 489 return 0;
490
9dac77fa 491 return ctxt->seg_override;
7a5b56df
AK		 492}
493
35d3d4a1
AK		 494static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
495 u32 error, bool valid)
54b8486f 496{
da9cb575
AK		 497 ctxt->exception.vector = vec;
498 ctxt->exception.error_code = error;
499 ctxt->exception.error_code_valid = valid;
35d3d4a1 500 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 501}
502
3b88e41a
JR		 503static int emulate_db(struct x86_emulate_ctxt *ctxt)
504{
505 return emulate_exception(ctxt, DB_VECTOR, 0, false);
506}
507
35d3d4a1 508static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 509{
35d3d4a1 510 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 511}
512
618ff15d
AK		 513static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
514{
515 return emulate_exception(ctxt, SS_VECTOR, err, true);
516}
517
35d3d4a1 518static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 519{
35d3d4a1 520 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 521}
522
35d3d4a1 523static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 524{
35d3d4a1 525 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 526}
527
34d1f490
AK		 528static int emulate_de(struct x86_emulate_ctxt *ctxt)
529{
35d3d4a1 530 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 531}
532
1253791d
AK		 533static int emulate_nm(struct x86_emulate_ctxt *ctxt)
534{
535 return emulate_exception(ctxt, NM_VECTOR, 0, false);
536}
537
1aa36616
AK		 538static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
539{
540 u16 selector;
541 struct desc_struct desc;
542
543 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
544 return selector;
545}
546
547static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
548 unsigned seg)
549{
550 u16 dummy;
551 u32 base3;
552 struct desc_struct desc;
553
554 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
555 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
556}
557
3d9b938e 558static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 559 struct segmented_address addr,
3d9b938e 560 unsigned size, bool write, bool fetch,
52fd8b44
AK		 561 ulong *linear)
562{
618ff15d
AK		 563 struct desc_struct desc;
564 bool usable;
52fd8b44 565 ulong la;
618ff15d 566 u32 lim;
1aa36616 567 u16 sel;
618ff15d 568 unsigned cpl, rpl;
52fd8b44 569
7b105ca2 570 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 571 switch (ctxt->mode) {
572 case X86EMUL_MODE_REAL:
573 break;
574 case X86EMUL_MODE_PROT64:
575 if (((signed long)la << 16) >> 16 != la)
576 return emulate_gp(ctxt, 0);
577 break;
578 default:
1aa36616
AK		 579 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
580 addr.seg);
618ff15d
AK		 581 if (!usable)
582 goto bad;
583 /* code segment or read-only data segment */
584 if (((desc.type & 8) || !(desc.type & 2)) && write)
585 goto bad;
586 /* unreadable code segment */
3d9b938e 587 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 588 goto bad;
589 lim = desc_limit_scaled(&desc);
590 if ((desc.type & 8) || !(desc.type & 4)) {
591 /* expand-up segment */
592 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
593 goto bad;
594 } else {
595 /* exapand-down segment */
596 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
597 goto bad;
598 lim = desc.d ? 0xffffffff : 0xffff;
599 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
600 goto bad;
601 }
717746e3 602 cpl = ctxt->ops->cpl(ctxt);
1aa36616 603 rpl = sel & 3;
618ff15d
AK		 604 cpl = max(cpl, rpl);
605 if (!(desc.type & 8)) {
606 /* data segment */
607 if (cpl > desc.dpl)
608 goto bad;
609 } else if ((desc.type & 8) && !(desc.type & 4)) {
610 /* nonconforming code segment */
611 if (cpl != desc.dpl)
612 goto bad;
613 } else if ((desc.type & 8) && (desc.type & 4)) {
614 /* conforming code segment */
615 if (cpl < desc.dpl)
616 goto bad;
617 }
618 break;
619 }
9dac77fa 620 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44
AK		 621 la &= (u32)-1;
622 *linear = la;
623 return X86EMUL_CONTINUE;
618ff15d
AK		 624bad:
625 if (addr.seg == VCPU_SREG_SS)
626 return emulate_ss(ctxt, addr.seg);
627 else
628 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 629}
630
3d9b938e
NE		 631static int linearize(struct x86_emulate_ctxt *ctxt,
632 struct segmented_address addr,
633 unsigned size, bool write,
634 ulong *linear)
635{
636 return __linearize(ctxt, addr, size, write, false, linear);
637}
638
639
3ca3ac4d
AK		 640static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
641 struct segmented_address addr,
642 void *data,
643 unsigned size)
644{
9fa088f4
AK		 645 int rc;
646 ulong linear;
647
83b8795a 648 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 649 if (rc != X86EMUL_CONTINUE)
650 return rc;
0f65dd70 651 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 652}
653
807941b1
TY		 654/*
655 * Fetch the next byte of the instruction being emulated which is pointed to
656 * by ctxt->_eip, then increment ctxt->_eip.
657 *
658 * Also prefetch the remaining bytes of the instruction without crossing page
659 * boundary if they are not in fetch_cache yet.
660 */
661static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 662{
9dac77fa 663 struct fetch_cache *fc = &ctxt->fetch;
62266869 664 int rc;
2fb53ad8 665 int size, cur_size;
62266869 666
807941b1 667 if (ctxt->_eip == fc->end) {
3d9b938e 668 unsigned long linear;
807941b1
TY		 669 struct segmented_address addr = { .seg = VCPU_SREG_CS,
670 .ea = ctxt->_eip };
2fb53ad8 671 cur_size = fc->end - fc->start;
807941b1
TY		 672 size = min(15UL - cur_size,
673 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 674 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 675 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 676 return rc;
ef5d75cc
TY		 677 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
678 size, &ctxt->exception);
7d88bb48 679 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 680 return rc;
2fb53ad8 681 fc->end += size;
62266869 682 }
807941b1
TY		 683 *dest = fc->data[ctxt->_eip - fc->start];
684 ctxt->_eip++;
3e2815e9 685 return X86EMUL_CONTINUE;
62266869
AK		 686}
687
688static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 689 void *dest, unsigned size)
62266869 690{
3e2815e9 691 int rc;
62266869 692
eb3c79e6 693 /* x86 instructions are limited to 15 bytes. */
7d88bb48 694 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 695 return X86EMUL_UNHANDLEABLE;
62266869 696 while (size--) {
807941b1 697 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 698 if (rc != X86EMUL_CONTINUE)
62266869
AK		 699 return rc;
700 }
3e2815e9 701 return X86EMUL_CONTINUE;
62266869
AK		 702}
703
67cbc90d 704/* Fetch next part of the instruction being emulated. */
e85a1085 705#define insn_fetch(_type, _ctxt) \
67cbc90d 706({ unsigned long _x; \
e85a1085 707 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 708 if (rc != X86EMUL_CONTINUE) \
709 goto done; \
67cbc90d
TY		 710 (_type)_x; \
711})
712
807941b1
TY		 713#define insn_fetch_arr(_arr, _size, _ctxt) \
714({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 715 if (rc != X86EMUL_CONTINUE) \
716 goto done; \
67cbc90d
TY		 717})
718
1e3c5cb0
RR		 719/*
720 * Given the 'reg' portion of a ModRM byte, and a register block, return a
721 * pointer into the block that addresses the relevant register.
722 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
723 */
724static void *decode_register(u8 modrm_reg, unsigned long *regs,
725 int highbyte_regs)
6aa8b732
AK		 726{
727 void *p;
728
729 p = &regs[modrm_reg];
730 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
731 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
732 return p;
733}
734
735static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 736 struct segmented_address addr,
6aa8b732
AK		 737 u16 *size, unsigned long *address, int op_bytes)
738{
739 int rc;
740
741 if (op_bytes == 2)
742 op_bytes = 3;
743 *address = 0;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 745 if (rc != X86EMUL_CONTINUE)
6aa8b732 746 return rc;
30b31ab6 747 addr.ea += 2;
3ca3ac4d 748 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 749 return rc;
750}
751
bbe9abbd
NK		 752static int test_cc(unsigned int condition, unsigned int flags)
753{
754 int rc = 0;
755
756 switch ((condition & 15) >> 1) {
757 case 0: /* o */
758 rc |= (flags & EFLG_OF);
759 break;
760 case 1: /* b/c/nae */
761 rc |= (flags & EFLG_CF);
762 break;
763 case 2: /* z/e */
764 rc |= (flags & EFLG_ZF);
765 break;
766 case 3: /* be/na */
767 rc |= (flags & (EFLG_CF|EFLG_ZF));
768 break;
769 case 4: /* s */
770 rc |= (flags & EFLG_SF);
771 break;
772 case 5: /* p/pe */
773 rc |= (flags & EFLG_PF);
774 break;
775 case 7: /* le/ng */
776 rc |= (flags & EFLG_ZF);
777 /* fall through */
778 case 6: /* l/nge */
779 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
780 break;
781 }
782
783 /* Odd condition identifiers (lsb == 1) have inverted sense. */
784 return (!!rc ^ (condition & 1));
785}
786
91ff3cb4
AK		 787static void fetch_register_operand(struct operand *op)
788{
789 switch (op->bytes) {
790 case 1:
791 op->val = *(u8 *)op->addr.reg;
792 break;
793 case 2:
794 op->val = *(u16 *)op->addr.reg;
795 break;
796 case 4:
797 op->val = *(u32 *)op->addr.reg;
798 break;
799 case 8:
800 op->val = *(u64 *)op->addr.reg;
801 break;
802 }
803}
804
1253791d
AK		 805static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
806{
807 ctxt->ops->get_fpu(ctxt);
808 switch (reg) {
809 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
810 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
811 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
812 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
813 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
814 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
815 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
816 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
817#ifdef CONFIG_X86_64
818 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
819 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
820 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
821 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
822 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
823 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
824 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
825 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
826#endif
827 default: BUG();
828 }
829 ctxt->ops->put_fpu(ctxt);
830}
831
832static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
833 int reg)
834{
835 ctxt->ops->get_fpu(ctxt);
836 switch (reg) {
837 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
838 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
839 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
840 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
841 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
842 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
843 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
844 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
845#ifdef CONFIG_X86_64
846 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
847 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
848 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
849 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
850 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
851 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
852 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
853 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
854#endif
855 default: BUG();
856 }
857 ctxt->ops->put_fpu(ctxt);
858}
859
860static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
861 struct operand *op,
3c118e24
AK		 862 int inhibit_bytereg)
863{
9dac77fa
AK		 864 unsigned reg = ctxt->modrm_reg;
865 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 866
9dac77fa
AK		 867 if (!(ctxt->d & ModRM))
868 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 869
9dac77fa 870 if (ctxt->d & Sse) {
1253791d
AK		 871 op->type = OP_XMM;
872 op->bytes = 16;
873 op->addr.xmm = reg;
874 read_sse_reg(ctxt, &op->vec_val, reg);
875 return;
876 }
877
3c118e24 878 op->type = OP_REG;
9dac77fa
AK		 879 if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
880 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 881 op->bytes = 1;
882 } else {
9dac77fa
AK		 883 op->addr.reg = decode_register(reg, ctxt->regs, 0);
884 op->bytes = ctxt->op_bytes;
3c118e24 885 }
91ff3cb4 886 fetch_register_operand(op);
3c118e24
AK		 887 op->orig_val = op->val;
888}
889
1c73ef66 890static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 891 struct operand *op)
1c73ef66 892{
1c73ef66 893 u8 sib;
f5b4edcd 894 int index_reg = 0, base_reg = 0, scale;
3e2815e9 895 int rc = X86EMUL_CONTINUE;
2dbd0dd7 896 ulong modrm_ea = 0;
1c73ef66 897
9dac77fa
AK		 898 if (ctxt->rex_prefix) {
899 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
900 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
901 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 902 }
903
e85a1085 904 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 905 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
906 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
907 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
908 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 909
9dac77fa 910 if (ctxt->modrm_mod == 3) {
2dbd0dd7 911 op->type = OP_REG;
9dac77fa
AK		 912 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
913 op->addr.reg = decode_register(ctxt->modrm_rm,
914 ctxt->regs, ctxt->d & ByteOp);
915 if (ctxt->d & Sse) {
1253791d
AK		 916 op->type = OP_XMM;
917 op->bytes = 16;
9dac77fa
AK		 918 op->addr.xmm = ctxt->modrm_rm;
919 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 920 return rc;
921 }
2dbd0dd7 922 fetch_register_operand(op);
1c73ef66
AK		 923 return rc;
924 }
925
2dbd0dd7
AK		 926 op->type = OP_MEM;
927
9dac77fa
AK		 928 if (ctxt->ad_bytes == 2) {
929 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
930 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
931 unsigned si = ctxt->regs[VCPU_REGS_RSI];
932 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 933
934 /* 16-bit ModR/M decode. */
9dac77fa 935 switch (ctxt->modrm_mod) {
1c73ef66 936 case 0:
9dac77fa 937 if (ctxt->modrm_rm == 6)
e85a1085 938 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 939 break;
940 case 1:
e85a1085 941 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 942 break;
943 case 2:
e85a1085 944 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 945 break;
946 }
9dac77fa 947 switch (ctxt->modrm_rm) {
1c73ef66 948 case 0:
2dbd0dd7 949 modrm_ea += bx + si;
1c73ef66
AK		 950 break;
951 case 1:
2dbd0dd7 952 modrm_ea += bx + di;
1c73ef66
AK		 953 break;
954 case 2:
2dbd0dd7 955 modrm_ea += bp + si;
1c73ef66
AK		 956 break;
957 case 3:
2dbd0dd7 958 modrm_ea += bp + di;
1c73ef66
AK		 959 break;
960 case 4:
2dbd0dd7 961 modrm_ea += si;
1c73ef66
AK		 962 break;
963 case 5:
2dbd0dd7 964 modrm_ea += di;
1c73ef66
AK		 965 break;
966 case 6:
9dac77fa 967 if (ctxt->modrm_mod != 0)
2dbd0dd7 968 modrm_ea += bp;
1c73ef66
AK		 969 break;
970 case 7:
2dbd0dd7 971 modrm_ea += bx;
1c73ef66
AK		 972 break;
973 }
9dac77fa
AK		 974 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
975 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
976 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 977 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 978 } else {
979 /* 32/64-bit ModR/M decode. */
9dac77fa 980 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 981 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 982 index_reg |= (sib >> 3) & 7;
983 base_reg |= sib & 7;
984 scale = sib >> 6;
985
9dac77fa 986 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 987 modrm_ea += insn_fetch(s32, ctxt);
dc71d0f1 988 else
9dac77fa 989 modrm_ea += ctxt->regs[base_reg];
dc71d0f1 990 if (index_reg != 4)
9dac77fa
AK		 991 modrm_ea += ctxt->regs[index_reg] << scale;
992 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 993 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 994 ctxt->rip_relative = 1;
84411d85 995 } else
9dac77fa
AK		 996 modrm_ea += ctxt->regs[ctxt->modrm_rm];
997 switch (ctxt->modrm_mod) {
1c73ef66 998 case 0:
9dac77fa 999 if (ctxt->modrm_rm == 5)
e85a1085 1000 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1001 break;
1002 case 1:
e85a1085 1003 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1004 break;
1005 case 2:
e85a1085 1006 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1007 break;
1008 }
1009 }
90de84f5 1010 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1011done:
1012 return rc;
1013}
1014
1015static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1016 struct operand *op)
1c73ef66 1017{
3e2815e9 1018 int rc = X86EMUL_CONTINUE;
1c73ef66 1019
2dbd0dd7 1020 op->type = OP_MEM;
9dac77fa 1021 switch (ctxt->ad_bytes) {
1c73ef66 1022 case 2:
e85a1085 1023 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1024 break;
1025 case 4:
e85a1085 1026 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1027 break;
1028 case 8:
e85a1085 1029 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1030 break;
1031 }
1032done:
1033 return rc;
1034}
1035
9dac77fa 1036static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1037{
7129eeca 1038 long sv = 0, mask;
35c843c4 1039
9dac77fa
AK		 1040 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1041 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1042
9dac77fa
AK		 1043 if (ctxt->src.bytes == 2)
1044 sv = (s16)ctxt->src.val & (s16)mask;
1045 else if (ctxt->src.bytes == 4)
1046 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1047
9dac77fa 1048 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1049 }
ba7ff2b7
WY		 1050
1051 /* only subword offset */
9dac77fa 1052 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1053}
1054
dde7e6d1 1055static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1056 unsigned long addr, void *dest, unsigned size)
6aa8b732 1057{
dde7e6d1 1058 int rc;
9dac77fa 1059 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1060
dde7e6d1
AK		 1061 while (size) {
1062 int n = min(size, 8u);
1063 size -= n;
1064 if (mc->pos < mc->end)
1065 goto read_cached;
5cd21917 1066
7b105ca2
TY		 1067 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1068 &ctxt->exception);
dde7e6d1
AK		 1069 if (rc != X86EMUL_CONTINUE)
1070 return rc;
1071 mc->end += n;
6aa8b732 1072
dde7e6d1
AK		 1073 read_cached:
1074 memcpy(dest, mc->data + mc->pos, n);
1075 mc->pos += n;
1076 dest += n;
1077 addr += n;
6aa8b732 1078 }
dde7e6d1
AK		 1079 return X86EMUL_CONTINUE;
1080}
6aa8b732 1081
3ca3ac4d
AK		 1082static int segmented_read(struct x86_emulate_ctxt *ctxt,
1083 struct segmented_address addr,
1084 void *data,
1085 unsigned size)
1086{
9fa088f4
AK		 1087 int rc;
1088 ulong linear;
1089
83b8795a 1090 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1091 if (rc != X86EMUL_CONTINUE)
1092 return rc;
7b105ca2 1093 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1094}
1095
1096static int segmented_write(struct x86_emulate_ctxt *ctxt,
1097 struct segmented_address addr,
1098 const void *data,
1099 unsigned size)
1100{
9fa088f4
AK		 1101 int rc;
1102 ulong linear;
1103
83b8795a 1104 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1105 if (rc != X86EMUL_CONTINUE)
1106 return rc;
0f65dd70
AK		 1107 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1108 &ctxt->exception);
3ca3ac4d
AK		 1109}
1110
1111static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1112 struct segmented_address addr,
1113 const void *orig_data, const void *data,
1114 unsigned size)
1115{
9fa088f4
AK		 1116 int rc;
1117 ulong linear;
1118
83b8795a 1119 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1120 if (rc != X86EMUL_CONTINUE)
1121 return rc;
0f65dd70
AK		 1122 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1123 size, &ctxt->exception);
3ca3ac4d
AK		 1124}
1125
dde7e6d1 1126static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1127 unsigned int size, unsigned short port,
1128 void *dest)
1129{
9dac77fa 1130 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1131
dde7e6d1 1132 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1133 unsigned int in_page, n;
9dac77fa
AK		 1134 unsigned int count = ctxt->rep_prefix ?
1135 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1136 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1137 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1138 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1139 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1140 count);
1141 if (n == 0)
1142 n = 1;
1143 rc->pos = rc->end = 0;
7b105ca2 1144 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1145 return 0;
1146 rc->end = n * size;
6aa8b732
AK		 1147 }
1148
dde7e6d1
AK		 1149 memcpy(dest, rc->data + rc->pos, size);
1150 rc->pos += size;
1151 return 1;
1152}
6aa8b732 1153
dde7e6d1 1154static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1155 u16 selector, struct desc_ptr *dt)
1156{
7b105ca2
TY		 1157 struct x86_emulate_ops *ops = ctxt->ops;
1158
dde7e6d1
AK		 1159 if (selector & 1 << 2) {
1160 struct desc_struct desc;
1aa36616
AK		 1161 u16 sel;
1162
dde7e6d1 1163 memset (dt, 0, sizeof *dt);
1aa36616 1164 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1165 return;
e09d082c 1166
dde7e6d1
AK		 1167 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1168 dt->address = get_desc_base(&desc);
1169 } else
4bff1e86 1170 ops->get_gdt(ctxt, dt);
dde7e6d1 1171}
120df890 1172
dde7e6d1
AK		 1173/* allowed just for 8 bytes segments */
1174static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1175 u16 selector, struct desc_struct *desc)
1176{
1177 struct desc_ptr dt;
1178 u16 index = selector >> 3;
dde7e6d1 1179 ulong addr;
120df890 1180
7b105ca2 1181 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1182
35d3d4a1
AK		 1183 if (dt.size < index * 8 + 7)
1184 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1185
7b105ca2
TY		 1186 addr = dt.address + index * 8;
1187 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1188 &ctxt->exception);
dde7e6d1 1189}
ef65c889 1190
dde7e6d1
AK		 1191/* allowed just for 8 bytes segments */
1192static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1193 u16 selector, struct desc_struct *desc)
1194{
1195 struct desc_ptr dt;
1196 u16 index = selector >> 3;
dde7e6d1 1197 ulong addr;
6aa8b732 1198
7b105ca2 1199 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1200
35d3d4a1
AK		 1201 if (dt.size < index * 8 + 7)
1202 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1203
dde7e6d1 1204 addr = dt.address + index * 8;
7b105ca2
TY		 1205 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1206 &ctxt->exception);
dde7e6d1 1207}
c7e75a3d 1208
5601d05b 1209/* Does not support long mode */
dde7e6d1 1210static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1211 u16 selector, int seg)
1212{
1213 struct desc_struct seg_desc;
1214 u8 dpl, rpl, cpl;
1215 unsigned err_vec = GP_VECTOR;
1216 u32 err_code = 0;
1217 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1218 int ret;
69f55cb1 1219
dde7e6d1 1220 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1221
dde7e6d1
AK		 1222 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1223 || ctxt->mode == X86EMUL_MODE_REAL) {
1224 /* set real mode segment descriptor */
1225 set_desc_base(&seg_desc, selector << 4);
1226 set_desc_limit(&seg_desc, 0xffff);
1227 seg_desc.type = 3;
1228 seg_desc.p = 1;
1229 seg_desc.s = 1;
1230 goto load;
1231 }
1232
1233 /* NULL selector is not valid for TR, CS and SS */
1234 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1235 && null_selector)
1236 goto exception;
1237
1238 /* TR should be in GDT only */
1239 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1240 goto exception;
1241
1242 if (null_selector) /* for NULL selector skip all following checks */
1243 goto load;
1244
7b105ca2 1245 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1246 if (ret != X86EMUL_CONTINUE)
1247 return ret;
1248
1249 err_code = selector & 0xfffc;
1250 err_vec = GP_VECTOR;
1251
1252 /* can't load system descriptor into segment selecor */
1253 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1254 goto exception;
1255
1256 if (!seg_desc.p) {
1257 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1258 goto exception;
1259 }
1260
1261 rpl = selector & 3;
1262 dpl = seg_desc.dpl;
7b105ca2 1263 cpl = ctxt->ops->cpl(ctxt);
dde7e6d1
AK		 1264
1265 switch (seg) {
1266 case VCPU_SREG_SS:
1267 /*
1268 * segment is not a writable data segment or segment
1269 * selector's RPL != CPL or segment selector's RPL != CPL
1270 */
1271 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1272 goto exception;
6aa8b732 1273 break;
dde7e6d1
AK		 1274 case VCPU_SREG_CS:
1275 if (!(seg_desc.type & 8))
1276 goto exception;
1277
1278 if (seg_desc.type & 4) {
1279 /* conforming */
1280 if (dpl > cpl)
1281 goto exception;
1282 } else {
1283 /* nonconforming */
1284 if (rpl > cpl || dpl != cpl)
1285 goto exception;
1286 }
1287 /* CS(RPL) <- CPL */
1288 selector = (selector & 0xfffc) | cpl;
6aa8b732 1289 break;
dde7e6d1
AK		 1290 case VCPU_SREG_TR:
1291 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1292 goto exception;
1293 break;
1294 case VCPU_SREG_LDTR:
1295 if (seg_desc.s || seg_desc.type != 2)
1296 goto exception;
1297 break;
1298 default: /* DS, ES, FS, or GS */
4e62417b 1299 /*
dde7e6d1
AK		 1300 * segment is not a data or readable code segment or
1301 * ((segment is a data or nonconforming code segment)
1302 * and (both RPL and CPL > DPL))
4e62417b 1303 */
dde7e6d1
AK		 1304 if ((seg_desc.type & 0xa) == 0x8 ||
1305 (((seg_desc.type & 0xc) != 0xc) &&
1306 (rpl > dpl && cpl > dpl)))
1307 goto exception;
6aa8b732 1308 break;
dde7e6d1
AK		 1309 }
1310
1311 if (seg_desc.s) {
1312 /* mark segment as accessed */
1313 seg_desc.type |= 1;
7b105ca2 1314 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1315 if (ret != X86EMUL_CONTINUE)
1316 return ret;
1317 }
1318load:
7b105ca2 1319 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1320 return X86EMUL_CONTINUE;
1321exception:
1322 emulate_exception(ctxt, err_vec, err_code, true);
1323 return X86EMUL_PROPAGATE_FAULT;
1324}
1325
31be40b3
WY		 1326static void write_register_operand(struct operand *op)
1327{
1328 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1329 switch (op->bytes) {
1330 case 1:
1331 *(u8 *)op->addr.reg = (u8)op->val;
1332 break;
1333 case 2:
1334 *(u16 *)op->addr.reg = (u16)op->val;
1335 break;
1336 case 4:
1337 *op->addr.reg = (u32)op->val;
1338 break; /* 64b: zero-extend */
1339 case 8:
1340 *op->addr.reg = op->val;
1341 break;
1342 }
1343}
1344
adddcecf 1345static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1346{
1347 int rc;
dde7e6d1 1348
9dac77fa 1349 switch (ctxt->dst.type) {
dde7e6d1 1350 case OP_REG:
9dac77fa 1351 write_register_operand(&ctxt->dst);
6aa8b732 1352 break;
dde7e6d1 1353 case OP_MEM:
9dac77fa 1354 if (ctxt->lock_prefix)
3ca3ac4d 1355 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1356 ctxt->dst.addr.mem,
1357 &ctxt->dst.orig_val,
1358 &ctxt->dst.val,
1359 ctxt->dst.bytes);
341de7e3 1360 else
3ca3ac4d 1361 rc = segmented_write(ctxt,
9dac77fa
AK		 1362 ctxt->dst.addr.mem,
1363 &ctxt->dst.val,
1364 ctxt->dst.bytes);
dde7e6d1
AK		 1365 if (rc != X86EMUL_CONTINUE)
1366 return rc;
a682e354 1367 break;
1253791d 1368 case OP_XMM:
9dac77fa 1369 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1370 break;
dde7e6d1
AK		 1371 case OP_NONE:
1372 /* no writeback */
414e6277 1373 break;
dde7e6d1 1374 default:
414e6277 1375 break;
6aa8b732 1376 }
dde7e6d1
AK		 1377 return X86EMUL_CONTINUE;
1378}
6aa8b732 1379
4487b3b4 1380static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1 1381{
4179bb02 1382 struct segmented_address addr;
0dc8d10f 1383
9dac77fa
AK		 1384 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
1385 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1386 addr.seg = VCPU_SREG_SS;
1387
1388 /* Disable writeback. */
9dac77fa
AK		 1389 ctxt->dst.type = OP_NONE;
1390 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1391}
69f55cb1 1392
dde7e6d1 1393static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1394 void *dest, int len)
1395{
dde7e6d1 1396 int rc;
90de84f5 1397 struct segmented_address addr;
8b4caf66 1398
9dac77fa 1399 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1400 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1401 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1402 if (rc != X86EMUL_CONTINUE)
1403 return rc;
1404
9dac77fa 1405 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1406 return rc;
8b4caf66
LV		 1407}
1408
c54fe504
TY		 1409static int em_pop(struct x86_emulate_ctxt *ctxt)
1410{
9dac77fa 1411 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1412}
1413
dde7e6d1 1414static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1415 void *dest, int len)
9de41573
GN		 1416{
1417 int rc;
dde7e6d1
AK		 1418 unsigned long val, change_mask;
1419 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1420 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1421
3b9be3bf 1422 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1423 if (rc != X86EMUL_CONTINUE)
1424 return rc;
9de41573 1425
dde7e6d1
AK		 1426 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1427 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1428
dde7e6d1
AK		 1429 switch(ctxt->mode) {
1430 case X86EMUL_MODE_PROT64:
1431 case X86EMUL_MODE_PROT32:
1432 case X86EMUL_MODE_PROT16:
1433 if (cpl == 0)
1434 change_mask |= EFLG_IOPL;
1435 if (cpl <= iopl)
1436 change_mask |= EFLG_IF;
1437 break;
1438 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1439 if (iopl < 3)
1440 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1441 change_mask |= EFLG_IF;
1442 break;
1443 default: /* real mode */
1444 change_mask |= (EFLG_IOPL | EFLG_IF);
1445 break;
9de41573 1446 }
dde7e6d1
AK		 1447
1448 *(unsigned long *)dest =
1449 (ctxt->eflags & ~change_mask) | (val & change_mask);
1450
1451 return rc;
9de41573
GN		 1452}
1453
62aaa2f0
TY		 1454static int em_popf(struct x86_emulate_ctxt *ctxt)
1455{
9dac77fa
AK		 1456 ctxt->dst.type = OP_REG;
1457 ctxt->dst.addr.reg = &ctxt->eflags;
1458 ctxt->dst.bytes = ctxt->op_bytes;
1459 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1460}
1461
1cd196ea 1462static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1463{
1cd196ea
AK		 1464 int seg = ctxt->src2.val;
1465
9dac77fa 1466 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1467
4487b3b4 1468 return em_push(ctxt);
7b262e90
GN		 1469}
1470
1cd196ea 1471static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1472{
1cd196ea 1473 int seg = ctxt->src2.val;
dde7e6d1
AK		 1474 unsigned long selector;
1475 int rc;
38ba30ba 1476
9dac77fa 1477 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1478 if (rc != X86EMUL_CONTINUE)
1479 return rc;
1480
7b105ca2 1481 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1482 return rc;
38ba30ba
GN		 1483}
1484
b96a7fad 1485static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1486{
9dac77fa 1487 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1488 int rc = X86EMUL_CONTINUE;
1489 int reg = VCPU_REGS_RAX;
38ba30ba 1490
dde7e6d1
AK		 1491 while (reg <= VCPU_REGS_RDI) {
1492 (reg == VCPU_REGS_RSP) ?
9dac77fa 1493 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1494
4487b3b4 1495 rc = em_push(ctxt);
dde7e6d1
AK		 1496 if (rc != X86EMUL_CONTINUE)
1497 return rc;
38ba30ba 1498
dde7e6d1 1499 ++reg;
38ba30ba 1500 }
38ba30ba 1501
dde7e6d1 1502 return rc;
38ba30ba
GN		 1503}
1504
62aaa2f0
TY		 1505static int em_pushf(struct x86_emulate_ctxt *ctxt)
1506{
9dac77fa 1507 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1508 return em_push(ctxt);
1509}
1510
b96a7fad 1511static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1512{
dde7e6d1
AK		 1513 int rc = X86EMUL_CONTINUE;
1514 int reg = VCPU_REGS_RDI;
38ba30ba 1515
dde7e6d1
AK		 1516 while (reg >= VCPU_REGS_RAX) {
1517 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1518 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1519 ctxt->op_bytes);
dde7e6d1
AK		 1520 --reg;
1521 }
38ba30ba 1522
9dac77fa 1523 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1524 if (rc != X86EMUL_CONTINUE)
1525 break;
1526 --reg;
38ba30ba 1527 }
dde7e6d1 1528 return rc;
38ba30ba
GN		 1529}
1530
7b105ca2 1531int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1532{
7b105ca2 1533 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1534 int rc;
6e154e56
MG		 1535 struct desc_ptr dt;
1536 gva_t cs_addr;
1537 gva_t eip_addr;
1538 u16 cs, eip;
6e154e56
MG		 1539
1540 /* TODO: Add limit checks */
9dac77fa 1541 ctxt->src.val = ctxt->eflags;
4487b3b4 1542 rc = em_push(ctxt);
5c56e1cf
AK		 1543 if (rc != X86EMUL_CONTINUE)
1544 return rc;
6e154e56
MG		 1545
1546 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1547
9dac77fa 1548 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1549 rc = em_push(ctxt);
5c56e1cf
AK		 1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
6e154e56 1552
9dac77fa 1553 ctxt->src.val = ctxt->_eip;
4487b3b4 1554 rc = em_push(ctxt);
5c56e1cf
AK		 1555 if (rc != X86EMUL_CONTINUE)
1556 return rc;
1557
4bff1e86 1558 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1559
1560 eip_addr = dt.address + (irq << 2);
1561 cs_addr = dt.address + (irq << 2) + 2;
1562
0f65dd70 1563 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1564 if (rc != X86EMUL_CONTINUE)
1565 return rc;
1566
0f65dd70 1567 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1568 if (rc != X86EMUL_CONTINUE)
1569 return rc;
1570
7b105ca2 1571 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1572 if (rc != X86EMUL_CONTINUE)
1573 return rc;
1574
9dac77fa 1575 ctxt->_eip = eip;
6e154e56
MG		 1576
1577 return rc;
1578}
1579
7b105ca2 1580static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1581{
1582 switch(ctxt->mode) {
1583 case X86EMUL_MODE_REAL:
7b105ca2 1584 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1585 case X86EMUL_MODE_VM86:
1586 case X86EMUL_MODE_PROT16:
1587 case X86EMUL_MODE_PROT32:
1588 case X86EMUL_MODE_PROT64:
1589 default:
1590 /* Protected mode interrupts unimplemented yet */
1591 return X86EMUL_UNHANDLEABLE;
1592 }
1593}
1594
7b105ca2 1595static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1596{
dde7e6d1
AK		 1597 int rc = X86EMUL_CONTINUE;
1598 unsigned long temp_eip = 0;
1599 unsigned long temp_eflags = 0;
1600 unsigned long cs = 0;
1601 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1602 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1603 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1604 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1605
dde7e6d1 1606 /* TODO: Add stack limit check */
38ba30ba 1607
9dac77fa 1608 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1609
dde7e6d1
AK		 1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
38ba30ba 1612
35d3d4a1
AK		 1613 if (temp_eip & ~0xffff)
1614 return emulate_gp(ctxt, 0);
38ba30ba 1615
9dac77fa 1616 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1617
dde7e6d1
AK		 1618 if (rc != X86EMUL_CONTINUE)
1619 return rc;
38ba30ba 1620
9dac77fa 1621 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1622
dde7e6d1
AK		 1623 if (rc != X86EMUL_CONTINUE)
1624 return rc;
38ba30ba 1625
7b105ca2 1626 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1627
dde7e6d1
AK		 1628 if (rc != X86EMUL_CONTINUE)
1629 return rc;
38ba30ba 1630
9dac77fa 1631 ctxt->_eip = temp_eip;
38ba30ba 1632
38ba30ba 1633
9dac77fa 1634 if (ctxt->op_bytes == 4)
dde7e6d1 1635 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1636 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1637 ctxt->eflags &= ~0xffff;
1638 ctxt->eflags |= temp_eflags;
38ba30ba 1639 }
dde7e6d1
AK		 1640
1641 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1642 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1643
1644 return rc;
38ba30ba
GN		 1645}
1646
e01991e7 1647static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1648{
dde7e6d1
AK		 1649 switch(ctxt->mode) {
1650 case X86EMUL_MODE_REAL:
7b105ca2 1651 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1652 case X86EMUL_MODE_VM86:
1653 case X86EMUL_MODE_PROT16:
1654 case X86EMUL_MODE_PROT32:
1655 case X86EMUL_MODE_PROT64:
c37eda13 1656 default:
dde7e6d1
AK		 1657 /* iret from protected mode unimplemented yet */
1658 return X86EMUL_UNHANDLEABLE;
c37eda13 1659 }
c37eda13
WY		 1660}
1661
d2f62766
TY		 1662static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1663{
d2f62766
TY		 1664 int rc;
1665 unsigned short sel;
1666
9dac77fa 1667 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1668
7b105ca2 1669 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1670 if (rc != X86EMUL_CONTINUE)
1671 return rc;
1672
9dac77fa
AK		 1673 ctxt->_eip = 0;
1674 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1675 return X86EMUL_CONTINUE;
1676}
1677
51187683 1678static int em_grp1a(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1679{
9dac77fa 1680 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
8cdbd2c9
LV		 1681}
1682
51187683 1683static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1684{
9dac77fa 1685 switch (ctxt->modrm_reg) {
8cdbd2c9 1686 case 0: /* rol */
a31b9cea 1687 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1688 break;
1689 case 1: /* ror */
a31b9cea 1690 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1691 break;
1692 case 2: /* rcl */
a31b9cea 1693 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1694 break;
1695 case 3: /* rcr */
a31b9cea 1696 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1697 break;
1698 case 4: /* sal/shl */
1699 case 6: /* sal/shl */
a31b9cea 1700 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1701 break;
1702 case 5: /* shr */
a31b9cea 1703 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1704 break;
1705 case 7: /* sar */
a31b9cea 1706 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1707 break;
1708 }
51187683 1709 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1710}
1711
3329ece1
AK		 1712static int em_not(struct x86_emulate_ctxt *ctxt)
1713{
1714 ctxt->dst.val = ~ctxt->dst.val;
1715 return X86EMUL_CONTINUE;
1716}
1717
1718static int em_neg(struct x86_emulate_ctxt *ctxt)
1719{
1720 emulate_1op(ctxt, "neg");
1721 return X86EMUL_CONTINUE;
1722}
1723
1724static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1725{
1726 u8 ex = 0;
1727
1728 emulate_1op_rax_rdx(ctxt, "mul", ex);
1729 return X86EMUL_CONTINUE;
1730}
1731
1732static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1733{
1734 u8 ex = 0;
1735
1736 emulate_1op_rax_rdx(ctxt, "imul", ex);
1737 return X86EMUL_CONTINUE;
1738}
1739
1740static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1741{
34d1f490 1742 u8 de = 0;
8cdbd2c9 1743
3329ece1
AK		 1744 emulate_1op_rax_rdx(ctxt, "div", de);
1745 if (de)
1746 return emulate_de(ctxt);
1747 return X86EMUL_CONTINUE;
1748}
1749
1750static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1751{
1752 u8 de = 0;
1753
1754 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1755 if (de)
1756 return emulate_de(ctxt);
8c5eee30 1757 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1758}
1759
51187683 1760static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1761{
4179bb02 1762 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1763
9dac77fa 1764 switch (ctxt->modrm_reg) {
8cdbd2c9 1765 case 0: /* inc */
d1eef45d 1766 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1767 break;
1768 case 1: /* dec */
d1eef45d 1769 emulate_1op(ctxt, "dec");
8cdbd2c9 1770 break;
d19292e4
MG		 1771 case 2: /* call near abs */ {
1772 long int old_eip;
9dac77fa
AK		 1773 old_eip = ctxt->_eip;
1774 ctxt->_eip = ctxt->src.val;
1775 ctxt->src.val = old_eip;
4487b3b4 1776 rc = em_push(ctxt);
d19292e4
MG		 1777 break;
1778 }
8cdbd2c9 1779 case 4: /* jmp abs */
9dac77fa 1780 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1781 break;
d2f62766
TY		 1782 case 5: /* jmp far */
1783 rc = em_jmp_far(ctxt);
1784 break;
8cdbd2c9 1785 case 6: /* push */
4487b3b4 1786 rc = em_push(ctxt);
8cdbd2c9 1787 break;
8cdbd2c9 1788 }
4179bb02 1789 return rc;
8cdbd2c9
LV		 1790}
1791
51187683 1792static int em_grp9(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1793{
9dac77fa 1794 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1795
9dac77fa
AK		 1796 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1797 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1798 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1799 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1800 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1801 } else {
9dac77fa
AK		 1802 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1803 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1804
05f086f8 1805 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1806 }
1b30eaa8 1807 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1808}
1809
ebda02c2
TY		 1810static int em_ret(struct x86_emulate_ctxt *ctxt)
1811{
9dac77fa
AK		 1812 ctxt->dst.type = OP_REG;
1813 ctxt->dst.addr.reg = &ctxt->_eip;
1814 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1815 return em_pop(ctxt);
1816}
1817
e01991e7 1818static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1819{
a77ab5ea
AK		 1820 int rc;
1821 unsigned long cs;
1822
9dac77fa 1823 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1824 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1825 return rc;
9dac77fa
AK		 1826 if (ctxt->op_bytes == 4)
1827 ctxt->_eip = (u32)ctxt->_eip;
1828 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1829 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1830 return rc;
7b105ca2 1831 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1832 return rc;
1833}
1834
d4b4325f 1835static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 1836{
d4b4325f 1837 int seg = ctxt->src2.val;
09b5f4d3
WY		 1838 unsigned short sel;
1839 int rc;
1840
9dac77fa 1841 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 1842
7b105ca2 1843 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 1844 if (rc != X86EMUL_CONTINUE)
1845 return rc;
1846
9dac77fa 1847 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 1848 return rc;
1849}
1850
7b105ca2 1851static void
e66bb2cc 1852setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 1853 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 1854{
1aa36616
AK		 1855 u16 selector;
1856
79168fd1 1857 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 1858 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1859 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1860
1861 cs->l = 0; /* will be adjusted later */
79168fd1 1862 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1863 cs->g = 1; /* 4kb granularity */
79168fd1 1864 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1865 cs->type = 0x0b; /* Read, Execute, Accessed */
1866 cs->s = 1;
1867 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1868 cs->p = 1;
1869 cs->d = 1;
e66bb2cc 1870
79168fd1
GN		 1871 set_desc_base(ss, 0); /* flat segment */
1872 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1873 ss->g = 1; /* 4kb granularity */
1874 ss->s = 1;
1875 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1876 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1877 ss->dpl = 0;
79168fd1 1878 ss->p = 1;
e66bb2cc
AP		 1879}
1880
e01991e7 1881static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 1882{
7b105ca2 1883 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1884 struct desc_struct cs, ss;
e66bb2cc 1885 u64 msr_data;
79168fd1 1886 u16 cs_sel, ss_sel;
c2ad2bb3 1887 u64 efer = 0;
e66bb2cc
AP		 1888
1889 /* syscall is not available in real mode */
2e901c4c 1890 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1891 ctxt->mode == X86EMUL_MODE_VM86)
1892 return emulate_ud(ctxt);
e66bb2cc 1893
c2ad2bb3 1894 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 1895 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 1896
717746e3 1897 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1898 msr_data >>= 32;
79168fd1
GN		 1899 cs_sel = (u16)(msr_data & 0xfffc);
1900 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1901
c2ad2bb3 1902 if (efer & EFER_LMA) {
79168fd1 1903 cs.d = 0;
e66bb2cc
AP		 1904 cs.l = 1;
1905 }
1aa36616
AK		 1906 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1907 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 1908
9dac77fa 1909 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 1910 if (efer & EFER_LMA) {
e66bb2cc 1911#ifdef CONFIG_X86_64
9dac77fa 1912 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 1913
717746e3 1914 ops->get_msr(ctxt,
3fb1b5db
GN		 1915 ctxt->mode == X86EMUL_MODE_PROT64 ?
1916 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 1917 ctxt->_eip = msr_data;
e66bb2cc 1918
717746e3 1919 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1920 ctxt->eflags &= ~(msr_data | EFLG_RF);
1921#endif
1922 } else {
1923 /* legacy mode */
717746e3 1924 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 1925 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 1926
1927 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1928 }
1929
e54cfa97 1930 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1931}
1932
e01991e7 1933static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 1934{
7b105ca2 1935 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1936 struct desc_struct cs, ss;
8c604352 1937 u64 msr_data;
79168fd1 1938 u16 cs_sel, ss_sel;
c2ad2bb3 1939 u64 efer = 0;
8c604352 1940
7b105ca2 1941 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1942 /* inject #GP if in real mode */
35d3d4a1
AK		 1943 if (ctxt->mode == X86EMUL_MODE_REAL)
1944 return emulate_gp(ctxt, 0);
8c604352
AP		 1945
1946 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1947 * Therefore, we inject an #UD.
1948 */
35d3d4a1
AK		 1949 if (ctxt->mode == X86EMUL_MODE_PROT64)
1950 return emulate_ud(ctxt);
8c604352 1951
7b105ca2 1952 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 1953
717746e3 1954 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1955 switch (ctxt->mode) {
1956 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1957 if ((msr_data & 0xfffc) == 0x0)
1958 return emulate_gp(ctxt, 0);
8c604352
AP		 1959 break;
1960 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1961 if (msr_data == 0x0)
1962 return emulate_gp(ctxt, 0);
8c604352
AP		 1963 break;
1964 }
1965
1966 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1967 cs_sel = (u16)msr_data;
1968 cs_sel &= ~SELECTOR_RPL_MASK;
1969 ss_sel = cs_sel + 8;
1970 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1971 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1972 cs.d = 0;
8c604352
AP		 1973 cs.l = 1;
1974 }
1975
1aa36616
AK		 1976 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1977 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1978
717746e3 1979 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 1980 ctxt->_eip = msr_data;
8c604352 1981
717746e3 1982 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 1983 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 1984
e54cfa97 1985 return X86EMUL_CONTINUE;
8c604352
AP		 1986}
1987
e01991e7 1988static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 1989{
7b105ca2 1990 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 1991 struct desc_struct cs, ss;
4668f050
AP		 1992 u64 msr_data;
1993 int usermode;
1249b96e 1994 u16 cs_sel = 0, ss_sel = 0;
4668f050 1995
a0044755
GN		 1996 /* inject #GP if in real mode or Virtual 8086 mode */
1997 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1998 ctxt->mode == X86EMUL_MODE_VM86)
1999 return emulate_gp(ctxt, 0);
4668f050 2000
7b105ca2 2001 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2002
9dac77fa 2003 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2004 usermode = X86EMUL_MODE_PROT64;
2005 else
2006 usermode = X86EMUL_MODE_PROT32;
2007
2008 cs.dpl = 3;
2009 ss.dpl = 3;
717746e3 2010 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2011 switch (usermode) {
2012 case X86EMUL_MODE_PROT32:
79168fd1 2013 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2014 if ((msr_data & 0xfffc) == 0x0)
2015 return emulate_gp(ctxt, 0);
79168fd1 2016 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2017 break;
2018 case X86EMUL_MODE_PROT64:
79168fd1 2019 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2020 if (msr_data == 0x0)
2021 return emulate_gp(ctxt, 0);
79168fd1
GN		 2022 ss_sel = cs_sel + 8;
2023 cs.d = 0;
4668f050
AP		 2024 cs.l = 1;
2025 break;
2026 }
79168fd1
GN		 2027 cs_sel |= SELECTOR_RPL_MASK;
2028 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2029
1aa36616
AK		 2030 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2031 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2032
9dac77fa
AK		 2033 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2034 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2035
e54cfa97 2036 return X86EMUL_CONTINUE;
4668f050
AP		 2037}
2038
7b105ca2 2039static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2040{
2041 int iopl;
2042 if (ctxt->mode == X86EMUL_MODE_REAL)
2043 return false;
2044 if (ctxt->mode == X86EMUL_MODE_VM86)
2045 return true;
2046 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2047 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2048}
2049
2050static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2051 u16 port, u16 len)
2052{
7b105ca2 2053 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2054 struct desc_struct tr_seg;
5601d05b 2055 u32 base3;
f850e2e6 2056 int r;
1aa36616 2057 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2058 unsigned mask = (1 << len) - 1;
5601d05b 2059 unsigned long base;
f850e2e6 2060
1aa36616 2061 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2062 if (!tr_seg.p)
f850e2e6 2063 return false;
79168fd1 2064 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2065 return false;
5601d05b
GN		 2066 base = get_desc_base(&tr_seg);
2067#ifdef CONFIG_X86_64
2068 base |= ((u64)base3) << 32;
2069#endif
0f65dd70 2070 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2071 if (r != X86EMUL_CONTINUE)
2072 return false;
79168fd1 2073 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2074 return false;
0f65dd70 2075 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2076 if (r != X86EMUL_CONTINUE)
2077 return false;
2078 if ((perm >> bit_idx) & mask)
2079 return false;
2080 return true;
2081}
2082
2083static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2084 u16 port, u16 len)
2085{
4fc40f07
GN		 2086 if (ctxt->perm_ok)
2087 return true;
2088
7b105ca2
TY		 2089 if (emulator_bad_iopl(ctxt))
2090 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2091 return false;
4fc40f07
GN		 2092
2093 ctxt->perm_ok = true;
2094
f850e2e6
GN		 2095 return true;
2096}
2097
38ba30ba 2098static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2099 struct tss_segment_16 *tss)
2100{
9dac77fa 2101 tss->ip = ctxt->_eip;
38ba30ba 2102 tss->flag = ctxt->eflags;
9dac77fa
AK		 2103 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2104 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2105 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2106 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2107 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2108 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2109 tss->si = ctxt->regs[VCPU_REGS_RSI];
2110 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2111
1aa36616
AK		 2112 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2113 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2114 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2115 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2116 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2117}
2118
2119static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2120 struct tss_segment_16 *tss)
2121{
38ba30ba
GN		 2122 int ret;
2123
9dac77fa 2124 ctxt->_eip = tss->ip;
38ba30ba 2125 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2126 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2127 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2128 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2129 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2130 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2131 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2132 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2133 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2134
2135 /*
2136 * SDM says that segment selectors are loaded before segment
2137 * descriptors
2138 */
1aa36616
AK		 2139 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2140 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2141 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2142 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2143 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2144
2145 /*
2146 * Now load segment descriptors. If fault happenes at this stage
2147 * it is handled in a context of new task
2148 */
7b105ca2 2149 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2150 if (ret != X86EMUL_CONTINUE)
2151 return ret;
7b105ca2 2152 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2153 if (ret != X86EMUL_CONTINUE)
2154 return ret;
7b105ca2 2155 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2156 if (ret != X86EMUL_CONTINUE)
2157 return ret;
7b105ca2 2158 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2159 if (ret != X86EMUL_CONTINUE)
2160 return ret;
7b105ca2 2161 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2162 if (ret != X86EMUL_CONTINUE)
2163 return ret;
2164
2165 return X86EMUL_CONTINUE;
2166}
2167
2168static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2169 u16 tss_selector, u16 old_tss_sel,
2170 ulong old_tss_base, struct desc_struct *new_desc)
2171{
7b105ca2 2172 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2173 struct tss_segment_16 tss_seg;
2174 int ret;
bcc55cba 2175 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2176
0f65dd70 2177 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2178 &ctxt->exception);
db297e3d 2179 if (ret != X86EMUL_CONTINUE)
38ba30ba 2180 /* FIXME: need to provide precise fault address */
38ba30ba 2181 return ret;
38ba30ba 2182
7b105ca2 2183 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2184
0f65dd70 2185 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2186 &ctxt->exception);
db297e3d 2187 if (ret != X86EMUL_CONTINUE)
38ba30ba 2188 /* FIXME: need to provide precise fault address */
38ba30ba 2189 return ret;
38ba30ba 2190
0f65dd70 2191 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2192 &ctxt->exception);
db297e3d 2193 if (ret != X86EMUL_CONTINUE)
38ba30ba 2194 /* FIXME: need to provide precise fault address */
38ba30ba 2195 return ret;
38ba30ba
GN		 2196
2197 if (old_tss_sel != 0xffff) {
2198 tss_seg.prev_task_link = old_tss_sel;
2199
0f65dd70 2200 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2201 &tss_seg.prev_task_link,
2202 sizeof tss_seg.prev_task_link,
0f65dd70 2203 &ctxt->exception);
db297e3d 2204 if (ret != X86EMUL_CONTINUE)
38ba30ba 2205 /* FIXME: need to provide precise fault address */
38ba30ba 2206 return ret;
38ba30ba
GN		 2207 }
2208
7b105ca2 2209 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2210}
2211
2212static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2213 struct tss_segment_32 *tss)
2214{
7b105ca2 2215 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2216 tss->eip = ctxt->_eip;
38ba30ba 2217 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2218 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2219 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2220 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2221 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2222 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2223 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2224 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2225 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2226
1aa36616
AK		 2227 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2228 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2229 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2230 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2231 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2232 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2233 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2234}
2235
2236static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2237 struct tss_segment_32 *tss)
2238{
38ba30ba
GN		 2239 int ret;
2240
7b105ca2 2241 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2242 return emulate_gp(ctxt, 0);
9dac77fa 2243 ctxt->_eip = tss->eip;
38ba30ba 2244 ctxt->eflags = tss->eflags | 2;
9dac77fa
AK		 2245 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2246 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2247 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2248 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2249 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2250 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2251 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2252 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2253
2254 /*
2255 * SDM says that segment selectors are loaded before segment
2256 * descriptors
2257 */
1aa36616
AK		 2258 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2259 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2260 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2261 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2262 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2263 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2264 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2265
2266 /*
2267 * Now load segment descriptors. If fault happenes at this stage
2268 * it is handled in a context of new task
2269 */
7b105ca2 2270 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2271 if (ret != X86EMUL_CONTINUE)
2272 return ret;
7b105ca2 2273 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2274 if (ret != X86EMUL_CONTINUE)
2275 return ret;
7b105ca2 2276 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2277 if (ret != X86EMUL_CONTINUE)
2278 return ret;
7b105ca2 2279 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2280 if (ret != X86EMUL_CONTINUE)
2281 return ret;
7b105ca2 2282 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2283 if (ret != X86EMUL_CONTINUE)
2284 return ret;
7b105ca2 2285 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2286 if (ret != X86EMUL_CONTINUE)
2287 return ret;
7b105ca2 2288 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2289 if (ret != X86EMUL_CONTINUE)
2290 return ret;
2291
2292 return X86EMUL_CONTINUE;
2293}
2294
2295static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2296 u16 tss_selector, u16 old_tss_sel,
2297 ulong old_tss_base, struct desc_struct *new_desc)
2298{
7b105ca2 2299 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2300 struct tss_segment_32 tss_seg;
2301 int ret;
bcc55cba 2302 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2303
0f65dd70 2304 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2305 &ctxt->exception);
db297e3d 2306 if (ret != X86EMUL_CONTINUE)
38ba30ba 2307 /* FIXME: need to provide precise fault address */
38ba30ba 2308 return ret;
38ba30ba 2309
7b105ca2 2310 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2311
0f65dd70 2312 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2313 &ctxt->exception);
db297e3d 2314 if (ret != X86EMUL_CONTINUE)
38ba30ba 2315 /* FIXME: need to provide precise fault address */
38ba30ba 2316 return ret;
38ba30ba 2317
0f65dd70 2318 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2319 &ctxt->exception);
db297e3d 2320 if (ret != X86EMUL_CONTINUE)
38ba30ba 2321 /* FIXME: need to provide precise fault address */
38ba30ba 2322 return ret;
38ba30ba
GN		 2323
2324 if (old_tss_sel != 0xffff) {
2325 tss_seg.prev_task_link = old_tss_sel;
2326
0f65dd70 2327 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2328 &tss_seg.prev_task_link,
2329 sizeof tss_seg.prev_task_link,
0f65dd70 2330 &ctxt->exception);
db297e3d 2331 if (ret != X86EMUL_CONTINUE)
38ba30ba 2332 /* FIXME: need to provide precise fault address */
38ba30ba 2333 return ret;
38ba30ba
GN		 2334 }
2335
7b105ca2 2336 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2337}
2338
2339static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2340 u16 tss_selector, int reason,
2341 bool has_error_code, u32 error_code)
38ba30ba 2342{
7b105ca2 2343 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2344 struct desc_struct curr_tss_desc, next_tss_desc;
2345 int ret;
1aa36616 2346 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2347 ulong old_tss_base =
4bff1e86 2348 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2349 u32 desc_limit;
38ba30ba
GN		 2350
2351 /* FIXME: old_tss_base == ~0 ? */
2352
7b105ca2 2353 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2354 if (ret != X86EMUL_CONTINUE)
2355 return ret;
7b105ca2 2356 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2357 if (ret != X86EMUL_CONTINUE)
2358 return ret;
2359
2360 /* FIXME: check that next_tss_desc is tss */
2361
2362 if (reason != TASK_SWITCH_IRET) {
2363 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2364 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2365 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2366 }
2367
ceffb459
GN		 2368 desc_limit = desc_limit_scaled(&next_tss_desc);
2369 if (!next_tss_desc.p ||
2370 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2371 desc_limit < 0x2b)) {
54b8486f 2372 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2373 return X86EMUL_PROPAGATE_FAULT;
2374 }
2375
2376 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2377 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2378 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2379 }
2380
2381 if (reason == TASK_SWITCH_IRET)
2382 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2383
2384 /* set back link to prev task only if NT bit is set in eflags
2385 note that old_tss_sel is not used afetr this point */
2386 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2387 old_tss_sel = 0xffff;
2388
2389 if (next_tss_desc.type & 8)
7b105ca2 2390 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2391 old_tss_base, &next_tss_desc);
2392 else
7b105ca2 2393 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2394 old_tss_base, &next_tss_desc);
0760d448
JK		 2395 if (ret != X86EMUL_CONTINUE)
2396 return ret;
38ba30ba
GN		 2397
2398 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2399 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2400
2401 if (reason != TASK_SWITCH_IRET) {
2402 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2403 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2404 }
2405
717746e3 2406 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2407 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2408
e269fb21 2409 if (has_error_code) {
9dac77fa
AK		 2410 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2411 ctxt->lock_prefix = 0;
2412 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2413 ret = em_push(ctxt);
e269fb21
JK		 2414 }
2415
38ba30ba
GN		 2416 return ret;
2417}
2418
2419int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2420 u16 tss_selector, int reason,
2421 bool has_error_code, u32 error_code)
38ba30ba 2422{
38ba30ba
GN		 2423 int rc;
2424
9dac77fa
AK		 2425 ctxt->_eip = ctxt->eip;
2426 ctxt->dst.type = OP_NONE;
38ba30ba 2427
7b105ca2 2428 rc = emulator_do_task_switch(ctxt, tss_selector, reason,
e269fb21 2429 has_error_code, error_code);
38ba30ba 2430
4179bb02 2431 if (rc == X86EMUL_CONTINUE)
9dac77fa 2432 ctxt->eip = ctxt->_eip;
38ba30ba 2433
a0c0ab2f 2434 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2435}
2436
90de84f5 2437static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2438 int reg, struct operand *op)
a682e354 2439{
a682e354
GN		 2440 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2441
9dac77fa
AK		 2442 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2443 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2444 op->addr.mem.seg = seg;
a682e354
GN		 2445}
2446
7af04fc0
AK		 2447static int em_das(struct x86_emulate_ctxt *ctxt)
2448{
7af04fc0
AK		 2449 u8 al, old_al;
2450 bool af, cf, old_cf;
2451
2452 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2453 al = ctxt->dst.val;
7af04fc0
AK		 2454
2455 old_al = al;
2456 old_cf = cf;
2457 cf = false;
2458 af = ctxt->eflags & X86_EFLAGS_AF;
2459 if ((al & 0x0f) > 9 || af) {
2460 al -= 6;
2461 cf = old_cf | (al >= 250);
2462 af = true;
2463 } else {
2464 af = false;
2465 }
2466 if (old_al > 0x99 || old_cf) {
2467 al -= 0x60;
2468 cf = true;
2469 }
2470
9dac77fa 2471 ctxt->dst.val = al;
7af04fc0 2472 /* Set PF, ZF, SF */
9dac77fa
AK		 2473 ctxt->src.type = OP_IMM;
2474 ctxt->src.val = 0;
2475 ctxt->src.bytes = 1;
a31b9cea 2476 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2477 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2478 if (cf)
2479 ctxt->eflags |= X86_EFLAGS_CF;
2480 if (af)
2481 ctxt->eflags |= X86_EFLAGS_AF;
2482 return X86EMUL_CONTINUE;
2483}
2484
d4ddafcd
TY		 2485static int em_call(struct x86_emulate_ctxt *ctxt)
2486{
2487 long rel = ctxt->src.val;
2488
2489 ctxt->src.val = (unsigned long)ctxt->_eip;
2490 jmp_rel(ctxt, rel);
2491 return em_push(ctxt);
2492}
2493
0ef753b8
AK		 2494static int em_call_far(struct x86_emulate_ctxt *ctxt)
2495{
0ef753b8
AK		 2496 u16 sel, old_cs;
2497 ulong old_eip;
2498 int rc;
2499
1aa36616 2500 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2501 old_eip = ctxt->_eip;
0ef753b8 2502
9dac77fa 2503 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2504 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2505 return X86EMUL_CONTINUE;
2506
9dac77fa
AK		 2507 ctxt->_eip = 0;
2508 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2509
9dac77fa 2510 ctxt->src.val = old_cs;
4487b3b4 2511 rc = em_push(ctxt);
0ef753b8
AK		 2512 if (rc != X86EMUL_CONTINUE)
2513 return rc;
2514
9dac77fa 2515 ctxt->src.val = old_eip;
4487b3b4 2516 return em_push(ctxt);
0ef753b8
AK		 2517}
2518
40ece7c7
AK		 2519static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2520{
40ece7c7
AK		 2521 int rc;
2522
9dac77fa
AK		 2523 ctxt->dst.type = OP_REG;
2524 ctxt->dst.addr.reg = &ctxt->_eip;
2525 ctxt->dst.bytes = ctxt->op_bytes;
2526 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2527 if (rc != X86EMUL_CONTINUE)
2528 return rc;
9dac77fa 2529 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2530 return X86EMUL_CONTINUE;
2531}
2532
d67fc27a
TY		 2533static int em_add(struct x86_emulate_ctxt *ctxt)
2534{
a31b9cea 2535 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2536 return X86EMUL_CONTINUE;
2537}
2538
2539static int em_or(struct x86_emulate_ctxt *ctxt)
2540{
a31b9cea 2541 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2542 return X86EMUL_CONTINUE;
2543}
2544
2545static int em_adc(struct x86_emulate_ctxt *ctxt)
2546{
a31b9cea 2547 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2548 return X86EMUL_CONTINUE;
2549}
2550
2551static int em_sbb(struct x86_emulate_ctxt *ctxt)
2552{
a31b9cea 2553 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2554 return X86EMUL_CONTINUE;
2555}
2556
2557static int em_and(struct x86_emulate_ctxt *ctxt)
2558{
a31b9cea 2559 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2560 return X86EMUL_CONTINUE;
2561}
2562
2563static int em_sub(struct x86_emulate_ctxt *ctxt)
2564{
a31b9cea 2565 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2566 return X86EMUL_CONTINUE;
2567}
2568
2569static int em_xor(struct x86_emulate_ctxt *ctxt)
2570{
a31b9cea 2571 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2572 return X86EMUL_CONTINUE;
2573}
2574
2575static int em_cmp(struct x86_emulate_ctxt *ctxt)
2576{
a31b9cea 2577 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2578 /* Disable writeback. */
9dac77fa 2579 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2580 return X86EMUL_CONTINUE;
2581}
2582
9f21ca59
TY		 2583static int em_test(struct x86_emulate_ctxt *ctxt)
2584{
a31b9cea 2585 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2586 /* Disable writeback. */
2587 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2588 return X86EMUL_CONTINUE;
2589}
2590
e4f973ae
TY		 2591static int em_xchg(struct x86_emulate_ctxt *ctxt)
2592{
e4f973ae 2593 /* Write back the register source. */
9dac77fa
AK		 2594 ctxt->src.val = ctxt->dst.val;
2595 write_register_operand(&ctxt->src);
e4f973ae
TY		 2596
2597 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2598 ctxt->dst.val = ctxt->src.orig_val;
2599 ctxt->lock_prefix = 1;
e4f973ae
TY		 2600 return X86EMUL_CONTINUE;
2601}
2602
5c82aa29 2603static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2604{
a31b9cea 2605 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2606 return X86EMUL_CONTINUE;
2607}
2608
5c82aa29
AK		 2609static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2610{
9dac77fa 2611 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2612 return em_imul(ctxt);
2613}
2614
61429142
AK		 2615static int em_cwd(struct x86_emulate_ctxt *ctxt)
2616{
9dac77fa
AK		 2617 ctxt->dst.type = OP_REG;
2618 ctxt->dst.bytes = ctxt->src.bytes;
2619 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2620 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2621
2622 return X86EMUL_CONTINUE;
2623}
2624
48bb5d3c
AK		 2625static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2626{
48bb5d3c
AK		 2627 u64 tsc = 0;
2628
717746e3 2629 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2630 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2631 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2632 return X86EMUL_CONTINUE;
2633}
2634
b9eac5f4
AK		 2635static int em_mov(struct x86_emulate_ctxt *ctxt)
2636{
9dac77fa 2637 ctxt->dst.val = ctxt->src.val;
b9eac5f4
AK		 2638 return X86EMUL_CONTINUE;
2639}
2640
bc00f8d2
TY		 2641static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2642{
2643 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2644 return emulate_gp(ctxt, 0);
2645
2646 /* Disable writeback. */
2647 ctxt->dst.type = OP_NONE;
2648 return X86EMUL_CONTINUE;
2649}
2650
2651static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2652{
2653 unsigned long val;
2654
2655 if (ctxt->mode == X86EMUL_MODE_PROT64)
2656 val = ctxt->src.val & ~0ULL;
2657 else
2658 val = ctxt->src.val & ~0U;
2659
2660 /* #UD condition is already handled. */
2661 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2662 return emulate_gp(ctxt, 0);
2663
2664 /* Disable writeback. */
2665 ctxt->dst.type = OP_NONE;
2666 return X86EMUL_CONTINUE;
2667}
2668
1bd5f469
TY		 2669static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2670{
9dac77fa 2671 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2672 return emulate_ud(ctxt);
2673
9dac77fa 2674 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 2675 return X86EMUL_CONTINUE;
2676}
2677
2678static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
2679{
9dac77fa 2680 u16 sel = ctxt->src.val;
1bd5f469 2681
9dac77fa 2682 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2683 return emulate_ud(ctxt);
2684
9dac77fa 2685 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 2686 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2687
2688 /* Disable writeback. */
9dac77fa
AK		 2689 ctxt->dst.type = OP_NONE;
2690 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 2691}
2692
aa97bb48
AK		 2693static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2694{
9dac77fa 2695 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
aa97bb48
AK		 2696 return X86EMUL_CONTINUE;
2697}
2698
38503911
AK		 2699static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2700{
9fa088f4
AK		 2701 int rc;
2702 ulong linear;
2703
9dac77fa 2704 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 2705 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2706 ctxt->ops->invlpg(ctxt, linear);
38503911 2707 /* Disable writeback. */
9dac77fa 2708 ctxt->dst.type = OP_NONE;
38503911
AK		 2709 return X86EMUL_CONTINUE;
2710}
2711
2d04a05b
AK		 2712static int em_clts(struct x86_emulate_ctxt *ctxt)
2713{
2714 ulong cr0;
2715
2716 cr0 = ctxt->ops->get_cr(ctxt, 0);
2717 cr0 &= ~X86_CR0_TS;
2718 ctxt->ops->set_cr(ctxt, 0, cr0);
2719 return X86EMUL_CONTINUE;
2720}
2721
26d05cc7
AK		 2722static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2723{
26d05cc7
AK		 2724 int rc;
2725
9dac77fa 2726 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 2727 return X86EMUL_UNHANDLEABLE;
2728
2729 rc = ctxt->ops->fix_hypercall(ctxt);
2730 if (rc != X86EMUL_CONTINUE)
2731 return rc;
2732
2733 /* Let the processor re-execute the fixed hypercall */
9dac77fa 2734 ctxt->_eip = ctxt->eip;
26d05cc7 2735 /* Disable writeback. */
9dac77fa 2736 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2737 return X86EMUL_CONTINUE;
2738}
2739
2740static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2741{
26d05cc7
AK		 2742 struct desc_ptr desc_ptr;
2743 int rc;
2744
9dac77fa 2745 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 2746 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2747 ctxt->op_bytes);
26d05cc7
AK		 2748 if (rc != X86EMUL_CONTINUE)
2749 return rc;
2750 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2751 /* Disable writeback. */
9dac77fa 2752 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2753 return X86EMUL_CONTINUE;
2754}
2755
5ef39c71 2756static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 2757{
26d05cc7
AK		 2758 int rc;
2759
5ef39c71
AK		 2760 rc = ctxt->ops->fix_hypercall(ctxt);
2761
26d05cc7 2762 /* Disable writeback. */
9dac77fa 2763 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2764 return rc;
2765}
2766
2767static int em_lidt(struct x86_emulate_ctxt *ctxt)
2768{
26d05cc7
AK		 2769 struct desc_ptr desc_ptr;
2770 int rc;
2771
9dac77fa 2772 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 2773 &desc_ptr.size, &desc_ptr.address,
9dac77fa 2774 ctxt->op_bytes);
26d05cc7
AK		 2775 if (rc != X86EMUL_CONTINUE)
2776 return rc;
2777 ctxt->ops->set_idt(ctxt, &desc_ptr);
2778 /* Disable writeback. */
9dac77fa 2779 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2780 return X86EMUL_CONTINUE;
2781}
2782
2783static int em_smsw(struct x86_emulate_ctxt *ctxt)
2784{
9dac77fa
AK		 2785 ctxt->dst.bytes = 2;
2786 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 2787 return X86EMUL_CONTINUE;
2788}
2789
2790static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2791{
26d05cc7 2792 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 2793 | (ctxt->src.val & 0x0f));
2794 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 2795 return X86EMUL_CONTINUE;
2796}
2797
d06e03ad
TY		 2798static int em_loop(struct x86_emulate_ctxt *ctxt)
2799{
9dac77fa
AK		 2800 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
2801 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
2802 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
2803 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2804
2805 return X86EMUL_CONTINUE;
2806}
2807
2808static int em_jcxz(struct x86_emulate_ctxt *ctxt)
2809{
9dac77fa
AK		 2810 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
2811 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 2812
2813 return X86EMUL_CONTINUE;
2814}
2815
d7841a4b
TY		 2816static int em_in(struct x86_emulate_ctxt *ctxt)
2817{
2818 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
2819 &ctxt->dst.val))
2820 return X86EMUL_IO_NEEDED;
2821
2822 return X86EMUL_CONTINUE;
2823}
2824
2825static int em_out(struct x86_emulate_ctxt *ctxt)
2826{
2827 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
2828 &ctxt->src.val, 1);
2829 /* Disable writeback. */
2830 ctxt->dst.type = OP_NONE;
2831 return X86EMUL_CONTINUE;
2832}
2833
f411e6cd
TY		 2834static int em_cli(struct x86_emulate_ctxt *ctxt)
2835{
2836 if (emulator_bad_iopl(ctxt))
2837 return emulate_gp(ctxt, 0);
2838
2839 ctxt->eflags &= ~X86_EFLAGS_IF;
2840 return X86EMUL_CONTINUE;
2841}
2842
2843static int em_sti(struct x86_emulate_ctxt *ctxt)
2844{
2845 if (emulator_bad_iopl(ctxt))
2846 return emulate_gp(ctxt, 0);
2847
2848 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
2849 ctxt->eflags |= X86_EFLAGS_IF;
2850 return X86EMUL_CONTINUE;
2851}
2852
ce7faab2
TY		 2853static int em_bt(struct x86_emulate_ctxt *ctxt)
2854{
2855 /* Disable writeback. */
2856 ctxt->dst.type = OP_NONE;
2857 /* only subword offset */
2858 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
2859
2860 emulate_2op_SrcV_nobyte(ctxt, "bt");
2861 return X86EMUL_CONTINUE;
2862}
2863
2864static int em_bts(struct x86_emulate_ctxt *ctxt)
2865{
2866 emulate_2op_SrcV_nobyte(ctxt, "bts");
2867 return X86EMUL_CONTINUE;
2868}
2869
2870static int em_btr(struct x86_emulate_ctxt *ctxt)
2871{
2872 emulate_2op_SrcV_nobyte(ctxt, "btr");
2873 return X86EMUL_CONTINUE;
2874}
2875
2876static int em_btc(struct x86_emulate_ctxt *ctxt)
2877{
2878 emulate_2op_SrcV_nobyte(ctxt, "btc");
2879 return X86EMUL_CONTINUE;
2880}
2881
cfec82cb
JR		 2882static bool valid_cr(int nr)
2883{
2884 switch (nr) {
2885 case 0:
2886 case 2 ... 4:
2887 case 8:
2888 return true;
2889 default:
2890 return false;
2891 }
2892}
2893
2894static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2895{
9dac77fa 2896 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 2897 return emulate_ud(ctxt);
2898
2899 return X86EMUL_CONTINUE;
2900}
2901
2902static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2903{
9dac77fa
AK		 2904 u64 new_val = ctxt->src.val64;
2905 int cr = ctxt->modrm_reg;
c2ad2bb3 2906 u64 efer = 0;
cfec82cb
JR		 2907
2908 static u64 cr_reserved_bits[] = {
2909 0xffffffff00000000ULL,
2910 0, 0, 0, /* CR3 checked later */
2911 CR4_RESERVED_BITS,
2912 0, 0, 0,
2913 CR8_RESERVED_BITS,
2914 };
2915
2916 if (!valid_cr(cr))
2917 return emulate_ud(ctxt);
2918
2919 if (new_val & cr_reserved_bits[cr])
2920 return emulate_gp(ctxt, 0);
2921
2922 switch (cr) {
2923 case 0: {
c2ad2bb3 2924 u64 cr4;
cfec82cb
JR		 2925 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2926 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2927 return emulate_gp(ctxt, 0);
2928
717746e3
AK		 2929 cr4 = ctxt->ops->get_cr(ctxt, 4);
2930 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2931
2932 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2933 !(cr4 & X86_CR4_PAE))
2934 return emulate_gp(ctxt, 0);
2935
2936 break;
2937 }
2938 case 3: {
2939 u64 rsvd = 0;
2940
c2ad2bb3
AK		 2941 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2942 if (efer & EFER_LMA)
cfec82cb 2943 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2944 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2945 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2946 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2947 rsvd = CR3_NONPAE_RESERVED_BITS;
2948
2949 if (new_val & rsvd)
2950 return emulate_gp(ctxt, 0);
2951
2952 break;
2953 }
2954 case 4: {
c2ad2bb3 2955 u64 cr4;
cfec82cb 2956
717746e3
AK		 2957 cr4 = ctxt->ops->get_cr(ctxt, 4);
2958 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2959
2960 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2961 return emulate_gp(ctxt, 0);
2962
2963 break;
2964 }
2965 }
2966
2967 return X86EMUL_CONTINUE;
2968}
2969
3b88e41a
JR		 2970static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2971{
2972 unsigned long dr7;
2973
717746e3 2974 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2975
2976 /* Check if DR7.Global_Enable is set */
2977 return dr7 & (1 << 13);
2978}
2979
2980static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2981{
9dac77fa 2982 int dr = ctxt->modrm_reg;
3b88e41a
JR		 2983 u64 cr4;
2984
2985 if (dr > 7)
2986 return emulate_ud(ctxt);
2987
717746e3 2988 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2989 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2990 return emulate_ud(ctxt);
2991
2992 if (check_dr7_gd(ctxt))
2993 return emulate_db(ctxt);
2994
2995 return X86EMUL_CONTINUE;
2996}
2997
2998static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2999{
9dac77fa
AK		 3000 u64 new_val = ctxt->src.val64;
3001 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3002
3003 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3004 return emulate_gp(ctxt, 0);
3005
3006 return check_dr_read(ctxt);
3007}
3008
01de8b09
JR		 3009static int check_svme(struct x86_emulate_ctxt *ctxt)
3010{
3011 u64 efer;
3012
717746e3 3013 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3014
3015 if (!(efer & EFER_SVME))
3016 return emulate_ud(ctxt);
3017
3018 return X86EMUL_CONTINUE;
3019}
3020
3021static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3022{
9dac77fa 3023 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3024
3025 /* Valid physical address? */
d4224449 3026 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3027 return emulate_gp(ctxt, 0);
3028
3029 return check_svme(ctxt);
3030}
3031
d7eb8203
JR		 3032static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3033{
717746e3 3034 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3035
717746e3 3036 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3037 return emulate_ud(ctxt);
3038
3039 return X86EMUL_CONTINUE;
3040}
3041
8061252e
JR		 3042static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3043{
717746e3 3044 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3045 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3046
717746e3 3047 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3048 (rcx > 3))
3049 return emulate_gp(ctxt, 0);
3050
3051 return X86EMUL_CONTINUE;
3052}
3053
f6511935
JR		 3054static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3055{
9dac77fa
AK		 3056 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3057 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3058 return emulate_gp(ctxt, 0);
3059
3060 return X86EMUL_CONTINUE;
3061}
3062
3063static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3064{
9dac77fa
AK		 3065 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3066 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3067 return emulate_gp(ctxt, 0);
3068
3069 return X86EMUL_CONTINUE;
3070}
3071
73fba5f4 3072#define D(_y) { .flags = (_y) }
c4f035c6 3073#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3074#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3075 .check_perm = (_p) }
73fba5f4 3076#define N D(0)
01de8b09 3077#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 3078#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 3079#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 3080#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3081#define II(_f, _e, _i) \
3082 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3083#define IIP(_f, _e, _i, _p) \
3084 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3085 .check_perm = (_p) }
aa97bb48 3086#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3087
8d8f4e9f 3088#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3089#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3090#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3091#define I2bvIP(_f, _e, _i, _p) \
3092 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3093
d67fc27a
TY		 3094#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3095 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3096 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3097
d7eb8203
JR		 3098static struct opcode group7_rm1[] = {
3099 DI(SrcNone | ModRM | Priv, monitor),
3100 DI(SrcNone | ModRM | Priv, mwait),
3101 N, N, N, N, N, N,
3102};
3103
01de8b09
JR		 3104static struct opcode group7_rm3[] = {
3105 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3106 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3107 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3108 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3109 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3110 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3111 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3112 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3113};
6230f7fc 3114
d7eb8203
JR		 3115static struct opcode group7_rm7[] = {
3116 N,
3117 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3118 N, N, N, N, N, N,
3119};
d67fc27a 3120
73fba5f4 3121static struct opcode group1[] = {
d67fc27a 3122 I(Lock, em_add),
d5ae7ce8 3123 I(Lock | PageTable, em_or),
d67fc27a
TY		 3124 I(Lock, em_adc),
3125 I(Lock, em_sbb),
d5ae7ce8 3126 I(Lock | PageTable, em_and),
d67fc27a
TY		 3127 I(Lock, em_sub),
3128 I(Lock, em_xor),
3129 I(0, em_cmp),
73fba5f4
AK		 3130};
3131
3132static struct opcode group1A[] = {
3133 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3134};
3135
3136static struct opcode group3[] = {
3329ece1
AK		 3137 I(DstMem | SrcImm | ModRM, em_test),
3138 I(DstMem | SrcImm | ModRM, em_test),
3139 I(DstMem | SrcNone | ModRM | Lock, em_not),
3140 I(DstMem | SrcNone | ModRM | Lock, em_neg),
3141 I(SrcMem | ModRM, em_mul_ex),
3142 I(SrcMem | ModRM, em_imul_ex),
3143 I(SrcMem | ModRM, em_div_ex),
3144 I(SrcMem | ModRM, em_idiv_ex),
73fba5f4
AK		 3145};
3146
3147static struct opcode group4[] = {
3148 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3149 N, N, N, N, N, N,
3150};
3151
3152static struct opcode group5[] = {
3153 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3154 D(SrcMem | ModRM | Stack),
3155 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3156 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3157 D(SrcMem | ModRM | Stack), N,
3158};
3159
dee6bb70
JR		 3160static struct opcode group6[] = {
3161 DI(ModRM | Prot, sldt),
3162 DI(ModRM | Prot, str),
3163 DI(ModRM | Prot | Priv, lldt),
3164 DI(ModRM | Prot | Priv, ltr),
3165 N, N, N, N,
3166};
3167
73fba5f4 3168static struct group_dual group7 = { {
dee6bb70
JR		 3169 DI(ModRM | Mov | DstMem | Priv, sgdt),
3170 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3171 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3172 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3173 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3174 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3175 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3176}, {
5ef39c71
AK		 3177 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3178 EXT(0, group7_rm1),
01de8b09 3179 N, EXT(0, group7_rm3),
5ef39c71
AK		 3180 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3181 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3182} };
3183
3184static struct opcode group8[] = {
3185 N, N, N, N,
ce7faab2
TY		 3186 I(DstMem | SrcImmByte | ModRM, em_bt),
3187 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts),
3188 I(DstMem | SrcImmByte | ModRM | Lock, em_btr),
3189 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc),
73fba5f4
AK		 3190};
3191
3192static struct group_dual group9 = { {
d5ae7ce8 3193 N, D(DstMem64 | ModRM | Lock | PageTable), N, N, N, N, N, N,
73fba5f4
AK		 3194}, {
3195 N, N, N, N, N, N, N, N,
3196} };
3197
a4d4a7c1 3198static struct opcode group11[] = {
d5ae7ce8
XG		 3199 I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov),
3200 X7(D(Undefined)),
a4d4a7c1
AK		 3201};
3202
aa97bb48
AK		 3203static struct gprefix pfx_0f_6f_0f_7f = {
3204 N, N, N, I(Sse, em_movdqu),
3205};
3206
73fba5f4
AK		 3207static struct opcode opcode_table[256] = {
3208 /* 0x00 - 0x07 */
d67fc27a 3209 I6ALU(Lock, em_add),
1cd196ea
AK		 3210 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3211 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3212 /* 0x08 - 0x0F */
d5ae7ce8 3213 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3214 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3215 N,
73fba5f4 3216 /* 0x10 - 0x17 */
d67fc27a 3217 I6ALU(Lock, em_adc),
1cd196ea
AK		 3218 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3219 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3220 /* 0x18 - 0x1F */
d67fc27a 3221 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3222 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3223 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3224 /* 0x20 - 0x27 */
d5ae7ce8 3225 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3226 /* 0x28 - 0x2F */
d67fc27a 3227 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3228 /* 0x30 - 0x37 */
d67fc27a 3229 I6ALU(Lock, em_xor), N, N,
73fba5f4 3230 /* 0x38 - 0x3F */
d67fc27a 3231 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3232 /* 0x40 - 0x4F */
3233 X16(D(DstReg)),
3234 /* 0x50 - 0x57 */
63540382 3235 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3236 /* 0x58 - 0x5F */
c54fe504 3237 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3238 /* 0x60 - 0x67 */
b96a7fad
TY		 3239 I(ImplicitOps | Stack | No64, em_pusha),
3240 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3241 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3242 N, N, N, N,
3243 /* 0x68 - 0x6F */
d46164db
AK		 3244 I(SrcImm | Mov | Stack, em_push),
3245 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3246 I(SrcImmByte | Mov | Stack, em_push),
3247 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
221192bd
MT		 3248 D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3249 D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3250 /* 0x70 - 0x7F */
3251 X16(D(SrcImmByte)),
3252 /* 0x80 - 0x87 */
3253 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3254 G(DstMem | SrcImm | ModRM | Group, group1),
3255 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3256 G(DstMem | SrcImmByte | ModRM | Group, group1),
9f21ca59 3257 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3258 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3259 /* 0x88 - 0x8F */
d5ae7ce8 3260 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3261 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3262 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3263 D(ModRM | SrcMem | NoAccess | DstReg),
3264 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3265 G(0, group1A),
73fba5f4 3266 /* 0x90 - 0x97 */
bf608f88 3267 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3268 /* 0x98 - 0x9F */
61429142 3269 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3270 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3271 II(ImplicitOps | Stack, em_pushf, pushf),
3272 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3273 /* 0xA0 - 0xA7 */
b9eac5f4 3274 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3275 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3276 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3277 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3278 /* 0xA8 - 0xAF */
9f21ca59 3279 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3280 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3281 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3282 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3283 /* 0xB0 - 0xB7 */
b9eac5f4 3284 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3285 /* 0xB8 - 0xBF */
b9eac5f4 3286 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3287 /* 0xC0 - 0xC7 */
d2c6c7ad 3288 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3289 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3290 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3291 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3292 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3293 G(ByteOp, group11), G(0, group11),
73fba5f4 3294 /* 0xC8 - 0xCF */
db5b0762 3295 N, N, N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3296 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3297 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3298 /* 0xD0 - 0xD7 */
d2c6c7ad 3299 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3300 N, N, N, N,
3301 /* 0xD8 - 0xDF */
3302 N, N, N, N, N, N, N, N,
3303 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3304 X3(I(SrcImmByte, em_loop)),
3305 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3306 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3307 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3308 /* 0xE8 - 0xEF */
d4ddafcd 3309 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3310 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3311 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3312 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3313 /* 0xF0 - 0xF7 */
bf608f88 3314 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3315 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3316 G(ByteOp, group3), G(0, group3),
73fba5f4 3317 /* 0xF8 - 0xFF */
f411e6cd
TY		 3318 D(ImplicitOps), D(ImplicitOps),
3319 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3320 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3321};
3322
3323static struct opcode twobyte_table[256] = {
3324 /* 0x00 - 0x0F */
dee6bb70 3325 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3326 N, I(ImplicitOps | VendorSpecific, em_syscall),
3327 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3328 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3329 N, D(ImplicitOps | ModRM), N, N,
3330 /* 0x10 - 0x1F */
3331 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3332 /* 0x20 - 0x2F */
cfec82cb 3333 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3334 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3335 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3336 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4
AK		 3337 N, N, N, N,
3338 N, N, N, N, N, N, N, N,
3339 /* 0x30 - 0x3F */
8061252e
JR		 3340 DI(ImplicitOps | Priv, wrmsr),
3341 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3342 DI(ImplicitOps | Priv, rdmsr),
3343 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
db5b0762
TY		 3344 I(ImplicitOps | VendorSpecific, em_sysenter),
3345 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3346 N, N,
73fba5f4
AK		 3347 N, N, N, N, N, N, N, N,
3348 /* 0x40 - 0x4F */
3349 X16(D(DstReg | SrcMem | ModRM | Mov)),
3350 /* 0x50 - 0x5F */
3351 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3352 /* 0x60 - 0x6F */
aa97bb48
AK		 3353 N, N, N, N,
3354 N, N, N, N,
3355 N, N, N, N,
3356 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3357 /* 0x70 - 0x7F */
aa97bb48
AK		 3358 N, N, N, N,
3359 N, N, N, N,
3360 N, N, N, N,
3361 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3362 /* 0x80 - 0x8F */
3363 X16(D(SrcImm)),
3364 /* 0x90 - 0x9F */
ee45b58e 3365 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3366 /* 0xA0 - 0xA7 */
1cd196ea 3367 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
ce7faab2 3368 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3369 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3370 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3371 /* 0xA8 - 0xAF */
1cd196ea 3372 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3373 DI(ImplicitOps, rsm),
ce7faab2 3374 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3375 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3376 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3377 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3378 /* 0xB0 - 0xB7 */
d5ae7ce8 3379 D2bv(DstMem | SrcReg | ModRM | Lock | PageTable),
d4b4325f 3380 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3381 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3382 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3383 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
09b5f4d3 3384 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3385 /* 0xB8 - 0xBF */
3386 N, N,
ce7faab2
TY		 3387 G(BitOp, group8),
3388 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
d9574a25
WY		 3389 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3390 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3391 /* 0xC0 - 0xCF */
739ae406 3392 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3393 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3394 N, N, N, GD(0, &group9),
3395 N, N, N, N, N, N, N, N,
3396 /* 0xD0 - 0xDF */
3397 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3398 /* 0xE0 - 0xEF */
3399 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3400 /* 0xF0 - 0xFF */
3401 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3402};
3403
3404#undef D
3405#undef N
3406#undef G
3407#undef GD
3408#undef I
aa97bb48 3409#undef GP
01de8b09 3410#undef EXT
73fba5f4 3411
8d8f4e9f 3412#undef D2bv
f6511935 3413#undef D2bvIP
8d8f4e9f 3414#undef I2bv
d7841a4b 3415#undef I2bvIP
d67fc27a 3416#undef I6ALU
8d8f4e9f 3417
9dac77fa 3418static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3419{
3420 unsigned size;
3421
9dac77fa 3422 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3423 if (size == 8)
3424 size = 4;
3425 return size;
3426}
3427
3428static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3429 unsigned size, bool sign_extension)
3430{
39f21ee5
AK		 3431 int rc = X86EMUL_CONTINUE;
3432
3433 op->type = OP_IMM;
3434 op->bytes = size;
9dac77fa 3435 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3436 /* NB. Immediates are sign-extended as necessary. */
3437 switch (op->bytes) {
3438 case 1:
e85a1085 3439 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3440 break;
3441 case 2:
e85a1085 3442 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3443 break;
3444 case 4:
e85a1085 3445 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3446 break;
3447 }
3448 if (!sign_extension) {
3449 switch (op->bytes) {
3450 case 1:
3451 op->val &= 0xff;
3452 break;
3453 case 2:
3454 op->val &= 0xffff;
3455 break;
3456 case 4:
3457 op->val &= 0xffffffff;
3458 break;
3459 }
3460 }
3461done:
3462 return rc;
3463}
3464
a9945549
AK		 3465static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3466 unsigned d)
3467{
3468 int rc = X86EMUL_CONTINUE;
3469
3470 switch (d) {
3471 case OpReg:
3472 decode_register_operand(ctxt, op,
5217973e 3473 op == &ctxt->dst &&
a9945549
AK		 3474 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
3475 break;
3476 case OpImmUByte:
608aabe3 3477 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3478 break;
3479 case OpMem:
41ddf978 3480 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3481 mem_common:
3482 *op = ctxt->memop;
3483 ctxt->memopp = op;
3484 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3485 fetch_bit_operand(ctxt);
3486 op->orig_val = op->val;
3487 break;
41ddf978
AK		 3488 case OpMem64:
3489 ctxt->memop.bytes = 8;
3490 goto mem_common;
a9945549
AK		 3491 case OpAcc:
3492 op->type = OP_REG;
3493 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3494 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3495 fetch_register_operand(op);
3496 op->orig_val = op->val;
3497 break;
3498 case OpDI:
3499 op->type = OP_MEM;
3500 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3501 op->addr.mem.ea =
3502 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3503 op->addr.mem.seg = VCPU_SREG_ES;
3504 op->val = 0;
3505 break;
3506 case OpDX:
3507 op->type = OP_REG;
3508 op->bytes = 2;
3509 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3510 fetch_register_operand(op);
3511 break;
4dd6a57d
AK		 3512 case OpCL:
3513 op->bytes = 1;
3514 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3515 break;
3516 case OpImmByte:
3517 rc = decode_imm(ctxt, op, 1, true);
3518 break;
3519 case OpOne:
3520 op->bytes = 1;
3521 op->val = 1;
3522 break;
3523 case OpImm:
3524 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3525 break;
0fe59128
AK		 3526 case OpMem16:
3527 ctxt->memop.bytes = 2;
3528 goto mem_common;
3529 case OpMem32:
3530 ctxt->memop.bytes = 4;
3531 goto mem_common;
3532 case OpImmU16:
3533 rc = decode_imm(ctxt, op, 2, false);
3534 break;
3535 case OpImmU:
3536 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3537 break;
3538 case OpSI:
3539 op->type = OP_MEM;
3540 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3541 op->addr.mem.ea =
3542 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3543 op->addr.mem.seg = seg_override(ctxt);
3544 op->val = 0;
3545 break;
3546 case OpImmFAddr:
3547 op->type = OP_IMM;
3548 op->addr.mem.ea = ctxt->_eip;
3549 op->bytes = ctxt->op_bytes + 2;
3550 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3551 break;
3552 case OpMemFAddr:
3553 ctxt->memop.bytes = ctxt->op_bytes + 2;
3554 goto mem_common;
c191a7a0
AK		 3555 case OpES:
3556 op->val = VCPU_SREG_ES;
3557 break;
3558 case OpCS:
3559 op->val = VCPU_SREG_CS;
3560 break;
3561 case OpSS:
3562 op->val = VCPU_SREG_SS;
3563 break;
3564 case OpDS:
3565 op->val = VCPU_SREG_DS;
3566 break;
3567 case OpFS:
3568 op->val = VCPU_SREG_FS;
3569 break;
3570 case OpGS:
3571 op->val = VCPU_SREG_GS;
3572 break;
a9945549
AK		 3573 case OpImplicit:
3574 /* Special instructions do their own operand decoding. */
3575 default:
3576 op->type = OP_NONE; /* Disable writeback. */
3577 break;
3578 }
3579
3580done:
3581 return rc;
3582}
3583
ef5d75cc 3584int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3585{
dde7e6d1
AK		 3586 int rc = X86EMUL_CONTINUE;
3587 int mode = ctxt->mode;
46561646 3588 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3589 bool op_prefix = false;
46561646 3590 struct opcode opcode;
dde7e6d1 3591
f09ed83e
AK		 3592 ctxt->memop.type = OP_NONE;
3593 ctxt->memopp = NULL;
9dac77fa
AK		 3594 ctxt->_eip = ctxt->eip;
3595 ctxt->fetch.start = ctxt->_eip;
3596 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3597 if (insn_len > 0)
9dac77fa 3598 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3599
3600 switch (mode) {
3601 case X86EMUL_MODE_REAL:
3602 case X86EMUL_MODE_VM86:
3603 case X86EMUL_MODE_PROT16:
3604 def_op_bytes = def_ad_bytes = 2;
3605 break;
3606 case X86EMUL_MODE_PROT32:
3607 def_op_bytes = def_ad_bytes = 4;
3608 break;
3609#ifdef CONFIG_X86_64
3610 case X86EMUL_MODE_PROT64:
3611 def_op_bytes = 4;
3612 def_ad_bytes = 8;
3613 break;
3614#endif
3615 default:
1d2887e2 3616 return EMULATION_FAILED;
dde7e6d1
AK		 3617 }
3618
9dac77fa
AK		 3619 ctxt->op_bytes = def_op_bytes;
3620 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 3621
3622 /* Legacy prefixes. */
3623 for (;;) {
e85a1085 3624 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 3625 case 0x66: /* operand-size override */
0d7cdee8 3626 op_prefix = true;
dde7e6d1 3627 /* switch between 2/4 bytes */
9dac77fa 3628 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 3629 break;
3630 case 0x67: /* address-size override */
3631 if (mode == X86EMUL_MODE_PROT64)
3632 /* switch between 4/8 bytes */
9dac77fa 3633 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 3634 else
3635 /* switch between 2/4 bytes */
9dac77fa 3636 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 3637 break;
3638 case 0x26: /* ES override */
3639 case 0x2e: /* CS override */
3640 case 0x36: /* SS override */
3641 case 0x3e: /* DS override */
9dac77fa 3642 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 3643 break;
3644 case 0x64: /* FS override */
3645 case 0x65: /* GS override */
9dac77fa 3646 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 3647 break;
3648 case 0x40 ... 0x4f: /* REX */
3649 if (mode != X86EMUL_MODE_PROT64)
3650 goto done_prefixes;
9dac77fa 3651 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 3652 continue;
3653 case 0xf0: /* LOCK */
9dac77fa 3654 ctxt->lock_prefix = 1;
dde7e6d1
AK		 3655 break;
3656 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3657 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 3658 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 3659 break;
3660 default:
3661 goto done_prefixes;
3662 }
3663
3664 /* Any legacy prefix after a REX prefix nullifies its effect. */
3665
9dac77fa 3666 ctxt->rex_prefix = 0;
dde7e6d1
AK		 3667 }
3668
3669done_prefixes:
3670
3671 /* REX prefix. */
9dac77fa
AK		 3672 if (ctxt->rex_prefix & 8)
3673 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3674
3675 /* Opcode byte(s). */
9dac77fa 3676 opcode = opcode_table[ctxt->b];
d3ad6243 3677 /* Two-byte opcode? */
9dac77fa
AK		 3678 if (ctxt->b == 0x0f) {
3679 ctxt->twobyte = 1;
e85a1085 3680 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 3681 opcode = twobyte_table[ctxt->b];
dde7e6d1 3682 }
9dac77fa 3683 ctxt->d = opcode.flags;
dde7e6d1 3684
9dac77fa
AK		 3685 while (ctxt->d & GroupMask) {
3686 switch (ctxt->d & GroupMask) {
46561646 3687 case Group:
e85a1085 3688 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3689 --ctxt->_eip;
3690 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 3691 opcode = opcode.u.group[goffset];
3692 break;
3693 case GroupDual:
e85a1085 3694 ctxt->modrm = insn_fetch(u8, ctxt);
9dac77fa
AK		 3695 --ctxt->_eip;
3696 goffset = (ctxt->modrm >> 3) & 7;
3697 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 3698 opcode = opcode.u.gdual->mod3[goffset];
3699 else
3700 opcode = opcode.u.gdual->mod012[goffset];
3701 break;
3702 case RMExt:
9dac77fa 3703 goffset = ctxt->modrm & 7;
01de8b09 3704 opcode = opcode.u.group[goffset];
46561646
AK		 3705 break;
3706 case Prefix:
9dac77fa 3707 if (ctxt->rep_prefix && op_prefix)
1d2887e2 3708 return EMULATION_FAILED;
9dac77fa 3709 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 3710 switch (simd_prefix) {
3711 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3712 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3713 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3714 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3715 }
3716 break;
3717 default:
1d2887e2 3718 return EMULATION_FAILED;
0d7cdee8 3719 }
46561646 3720
b1ea50b2 3721 ctxt->d &= ~(u64)GroupMask;
9dac77fa 3722 ctxt->d |= opcode.flags;
0d7cdee8
AK		 3723 }
3724
9dac77fa
AK		 3725 ctxt->execute = opcode.u.execute;
3726 ctxt->check_perm = opcode.check_perm;
3727 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 3728
3729 /* Unrecognised? */
9dac77fa 3730 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 3731 return EMULATION_FAILED;
dde7e6d1 3732
9dac77fa 3733 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 3734 return EMULATION_FAILED;
d867162c 3735
9dac77fa
AK		 3736 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
3737 ctxt->op_bytes = 8;
dde7e6d1 3738
9dac77fa 3739 if (ctxt->d & Op3264) {
7f9b4b75 3740 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 3741 ctxt->op_bytes = 8;
7f9b4b75 3742 else
9dac77fa 3743 ctxt->op_bytes = 4;
7f9b4b75
AK		 3744 }
3745
9dac77fa
AK		 3746 if (ctxt->d & Sse)
3747 ctxt->op_bytes = 16;
1253791d 3748
dde7e6d1 3749 /* ModRM and SIB bytes. */
9dac77fa 3750 if (ctxt->d & ModRM) {
f09ed83e 3751 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 3752 if (!ctxt->has_seg_override)
3753 set_seg_override(ctxt, ctxt->modrm_seg);
3754 } else if (ctxt->d & MemAbs)
f09ed83e 3755 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 3756 if (rc != X86EMUL_CONTINUE)
3757 goto done;
3758
9dac77fa
AK		 3759 if (!ctxt->has_seg_override)
3760 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 3761
f09ed83e 3762 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 3763
f09ed83e
AK		 3764 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
3765 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 3766
dde7e6d1
AK		 3767 /*
3768 * Decode and fetch the source operand: register, memory
3769 * or immediate.
3770 */
0fe59128 3771 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 3772 if (rc != X86EMUL_CONTINUE)
3773 goto done;
3774
dde7e6d1
AK		 3775 /*
3776 * Decode and fetch the second source operand: register, memory
3777 * or immediate.
3778 */
4dd6a57d 3779 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 3780 if (rc != X86EMUL_CONTINUE)
3781 goto done;
3782
dde7e6d1 3783 /* Decode and fetch the destination operand: register or memory. */
a9945549 3784 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 3785
3786done:
f09ed83e
AK		 3787 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
3788 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 3789
1d2887e2 3790 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3791}
3792
1cb3f3ae
XG		 3793bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
3794{
3795 return ctxt->d & PageTable;
3796}
3797
3e2f65d5
GN		 3798static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3799{
3e2f65d5
GN		 3800 /* The second termination condition only applies for REPE
3801 * and REPNE. Test if the repeat string operation prefix is
3802 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3803 * corresponding termination condition according to:
3804 * - if REPE/REPZ and ZF = 0 then done
3805 * - if REPNE/REPNZ and ZF = 1 then done
3806 */
9dac77fa
AK		 3807 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
3808 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
3809 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 3810 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 3811 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 3812 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3813 return true;
3814
3815 return false;
3816}
3817
7b105ca2 3818int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3819{
9aabc88f 3820 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3821 u64 msr_data;
1b30eaa8 3822 int rc = X86EMUL_CONTINUE;
9dac77fa 3823 int saved_dst_type = ctxt->dst.type;
8b4caf66 3824
9dac77fa 3825 ctxt->mem_read.pos = 0;
310b5d30 3826
9dac77fa 3827 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 3828 rc = emulate_ud(ctxt);
1161624f
GN		 3829 goto done;
3830 }
3831
d380a5e4 3832 /* LOCK prefix is allowed only with some instructions */
9dac77fa 3833 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 3834 rc = emulate_ud(ctxt);
d380a5e4
GN		 3835 goto done;
3836 }
3837
9dac77fa 3838 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 3839 rc = emulate_ud(ctxt);
081bca0e
AK		 3840 goto done;
3841 }
3842
9dac77fa 3843 if ((ctxt->d & Sse)
717746e3
AK		 3844 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3845 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3846 rc = emulate_ud(ctxt);
3847 goto done;
3848 }
3849
9dac77fa 3850 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3851 rc = emulate_nm(ctxt);
3852 goto done;
3853 }
3854
9dac77fa
AK		 3855 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3856 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3857 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3858 if (rc != X86EMUL_CONTINUE)
3859 goto done;
3860 }
3861
e92805ac 3862 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 3863 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3864 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3865 goto done;
3866 }
3867
8ea7d6ae 3868 /* Instruction can only be executed in protected mode */
9dac77fa 3869 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 3870 rc = emulate_ud(ctxt);
3871 goto done;
3872 }
3873
d09beabd 3874 /* Do instruction specific permission checks */
9dac77fa
AK		 3875 if (ctxt->check_perm) {
3876 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 3877 if (rc != X86EMUL_CONTINUE)
3878 goto done;
3879 }
3880
9dac77fa
AK		 3881 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3882 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3883 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3884 if (rc != X86EMUL_CONTINUE)
3885 goto done;
3886 }
3887
9dac77fa 3888 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 3889 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 3890 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
3891 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 3892 goto done;
3893 }
b9fa9d6b
AK		 3894 }
3895
9dac77fa
AK		 3896 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
3897 rc = segmented_read(ctxt, ctxt->src.addr.mem,
3898 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 3899 if (rc != X86EMUL_CONTINUE)
8b4caf66 3900 goto done;
9dac77fa 3901 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 3902 }
3903
9dac77fa
AK		 3904 if (ctxt->src2.type == OP_MEM) {
3905 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
3906 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 3907 if (rc != X86EMUL_CONTINUE)
3908 goto done;
3909 }
3910
9dac77fa 3911 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 3912 goto special_insn;
3913
3914
9dac77fa 3915 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 3916 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 3917 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
3918 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 3919 if (rc != X86EMUL_CONTINUE)
3920 goto done;
038e51de 3921 }
9dac77fa 3922 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 3923
018a98db
AK		 3924special_insn:
3925
9dac77fa
AK		 3926 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
3927 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 3928 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3929 if (rc != X86EMUL_CONTINUE)
3930 goto done;
3931 }
3932
9dac77fa
AK		 3933 if (ctxt->execute) {
3934 rc = ctxt->execute(ctxt);
ef65c889
AK		 3935 if (rc != X86EMUL_CONTINUE)
3936 goto done;
3937 goto writeback;
3938 }
3939
9dac77fa 3940 if (ctxt->twobyte)
6aa8b732
AK		 3941 goto twobyte_insn;
3942
9dac77fa 3943 switch (ctxt->b) {
33615aa9 3944 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 3945 emulate_1op(ctxt, "inc");
33615aa9
AK		 3946 break;
3947 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 3948 emulate_1op(ctxt, "dec");
33615aa9 3949 break;
6aa8b732 3950 case 0x63: /* movsxd */
8b4caf66 3951 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3952 goto cannot_emulate;
9dac77fa 3953 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 3954 break;
018a98db
AK		 3955 case 0x6c: /* insb */
3956 case 0x6d: /* insw/insd */
9dac77fa 3957 ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
d7841a4b
TY		 3958 rc = em_in(ctxt);
3959 break;
018a98db
AK		 3960 case 0x6e: /* outsb */
3961 case 0x6f: /* outsw/outsd */
9dac77fa 3962 ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
d7841a4b 3963 rc = em_out(ctxt);
7972995b 3964 break;
b2833e3c 3965 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 3966 if (test_cc(ctxt->b, ctxt->eflags))
3967 jmp_rel(ctxt, ctxt->src.val);
018a98db 3968 break;
7e0b54b1 3969 case 0x8d: /* lea r16/r32, m */
9dac77fa 3970 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 3971 break;
6aa8b732 3972 case 0x8f: /* pop (sole member of Grp1a) */
51187683 3973 rc = em_grp1a(ctxt);
6aa8b732 3974 break;
3d9e77df 3975 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 3976 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 3977 break;
e4f973ae
TY		 3978 rc = em_xchg(ctxt);
3979 break;
e8b6fa70 3980 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 3981 switch (ctxt->op_bytes) {
3982 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
3983 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
3984 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 3985 }
3986 break;
018a98db 3987 case 0xc0 ... 0xc1:
51187683 3988 rc = em_grp2(ctxt);
018a98db 3989 break;
6e154e56 3990 case 0xcc: /* int3 */
5c5df76b
TY		 3991 rc = emulate_int(ctxt, 3);
3992 break;
6e154e56 3993 case 0xcd: /* int n */
9dac77fa 3994 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 3995 break;
3996 case 0xce: /* into */
5c5df76b
TY		 3997 if (ctxt->eflags & EFLG_OF)
3998 rc = emulate_int(ctxt, 4);
6e154e56 3999 break;
018a98db 4000 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4001 rc = em_grp2(ctxt);
018a98db
AK		 4002 break;
4003 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4004 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4005 rc = em_grp2(ctxt);
018a98db 4006 break;
1a52e051 4007 case 0xe9: /* jmp rel */
db5b0762 4008 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4009 jmp_rel(ctxt, ctxt->src.val);
4010 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4011 break;
111de5d6 4012 case 0xf4: /* hlt */
6c3287f7 4013 ctxt->ops->halt(ctxt);
19fdfa0d 4014 break;
111de5d6
AK		 4015 case 0xf5: /* cmc */
4016 /* complement carry flag from eflags reg */
4017 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4018 break;
4019 case 0xf8: /* clc */
4020 ctxt->eflags &= ~EFLG_CF;
111de5d6 4021 break;
8744aa9a
MG		 4022 case 0xf9: /* stc */
4023 ctxt->eflags |= EFLG_CF;
4024 break;
fb4616f4
MG		 4025 case 0xfc: /* cld */
4026 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4027 break;
4028 case 0xfd: /* std */
4029 ctxt->eflags |= EFLG_DF;
fb4616f4 4030 break;
ea79849d 4031 case 0xfe: /* Grp4 */
51187683 4032 rc = em_grp45(ctxt);
018a98db 4033 break;
ea79849d 4034 case 0xff: /* Grp5 */
51187683
TY		 4035 rc = em_grp45(ctxt);
4036 break;
91269b8f
AK		 4037 default:
4038 goto cannot_emulate;
6aa8b732 4039 }
018a98db 4040
7d9ddaed
AK		 4041 if (rc != X86EMUL_CONTINUE)
4042 goto done;
4043
018a98db 4044writeback:
adddcecf 4045 rc = writeback(ctxt);
1b30eaa8 4046 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4047 goto done;
4048
5cd21917
GN		 4049 /*
4050 * restore dst type in case the decoding will be reused
4051 * (happens for string instruction )
4052 */
9dac77fa 4053 ctxt->dst.type = saved_dst_type;
5cd21917 4054
9dac77fa
AK		 4055 if ((ctxt->d & SrcMask) == SrcSI)
4056 string_addr_inc(ctxt, seg_override(ctxt),
4057 VCPU_REGS_RSI, &ctxt->src);
a682e354 4058
9dac77fa 4059 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4060 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4061 &ctxt->dst);
d9271123 4062
9dac77fa
AK		 4063 if (ctxt->rep_prefix && (ctxt->d & String)) {
4064 struct read_cache *r = &ctxt->io_read;
4065 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4066
d2ddd1c4
GN		 4067 if (!string_insn_completed(ctxt)) {
4068 /*
4069 * Re-enter guest when pio read ahead buffer is empty
4070 * or, if it is not used, after each 1024 iteration.
4071 */
9dac77fa 4072 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4073 (r->end == 0 || r->end != r->pos)) {
4074 /*
4075 * Reset read cache. Usually happens before
4076 * decode, but since instruction is restarted
4077 * we have to do it here.
4078 */
9dac77fa 4079 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4080 return EMULATION_RESTART;
4081 }
4082 goto done; /* skip rip writeback */
0fa6ccbd 4083 }
5cd21917 4084 }
d2ddd1c4 4085
9dac77fa 4086 ctxt->eip = ctxt->_eip;
018a98db
AK		 4087
4088done:
da9cb575
AK		 4089 if (rc == X86EMUL_PROPAGATE_FAULT)
4090 ctxt->have_exception = true;
775fde86
JR		 4091 if (rc == X86EMUL_INTERCEPTED)
4092 return EMULATION_INTERCEPTED;
4093
d2ddd1c4 4094 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4095
4096twobyte_insn:
9dac77fa 4097 switch (ctxt->b) {
018a98db 4098 case 0x09: /* wbinvd */
cfb22375 4099 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4100 break;
4101 case 0x08: /* invd */
018a98db
AK		 4102 case 0x0d: /* GrpP (prefetch) */
4103 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4104 break;
4105 case 0x20: /* mov cr, reg */
9dac77fa 4106 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4107 break;
6aa8b732 4108 case 0x21: /* mov from dr to reg */
9dac77fa 4109 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4110 break;
018a98db
AK		 4111 case 0x30:
4112 /* wrmsr */
9dac77fa
AK		 4113 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
4114 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
4115 if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4116 emulate_gp(ctxt, 0);
da9cb575 4117 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4118 goto done;
018a98db
AK		 4119 }
4120 rc = X86EMUL_CONTINUE;
018a98db
AK		 4121 break;
4122 case 0x32:
4123 /* rdmsr */
9dac77fa 4124 if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4125 emulate_gp(ctxt, 0);
da9cb575 4126 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4127 goto done;
018a98db 4128 } else {
9dac77fa
AK		 4129 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
4130 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
018a98db
AK		 4131 }
4132 rc = X86EMUL_CONTINUE;
018a98db 4133 break;
6aa8b732 4134 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4135 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4136 if (!test_cc(ctxt->b, ctxt->eflags))
4137 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4138 break;
b2833e3c 4139 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4140 if (test_cc(ctxt->b, ctxt->eflags))
4141 jmp_rel(ctxt, ctxt->src.val);
018a98db 4142 break;
ee45b58e 4143 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4144 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4145 break;
9bf8ea42
GT		 4146 case 0xa4: /* shld imm8, r, r/m */
4147 case 0xa5: /* shld cl, r, r/m */
761441b9 4148 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4149 break;
9bf8ea42
GT		 4150 case 0xac: /* shrd imm8, r, r/m */
4151 case 0xad: /* shrd cl, r, r/m */
761441b9 4152 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4153 break;
2a7c5b8b
GC		 4154 case 0xae: /* clflush */
4155 break;
6aa8b732
AK		 4156 case 0xb0 ... 0xb1: /* cmpxchg */
4157 /*
4158 * Save real source value, then compare EAX against
4159 * destination.
4160 */
9dac77fa
AK		 4161 ctxt->src.orig_val = ctxt->src.val;
4162 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
a31b9cea 4163 emulate_2op_SrcV(ctxt, "cmp");
05f086f8 4164 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4165 /* Success: write back to memory. */
9dac77fa 4166 ctxt->dst.val = ctxt->src.orig_val;
6aa8b732
AK		 4167 } else {
4168 /* Failure: write the value we saw to EAX. */
9dac77fa
AK		 4169 ctxt->dst.type = OP_REG;
4170 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4171 }
4172 break;
6aa8b732 4173 case 0xb6 ... 0xb7: /* movzx */
9dac77fa
AK		 4174 ctxt->dst.bytes = ctxt->op_bytes;
4175 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
4176 : (u16) ctxt->src.val;
6aa8b732 4177 break;
d9574a25
WY		 4178 case 0xbc: { /* bsf */
4179 u8 zf;
4180 __asm__ ("bsf %2, %0; setz %1"
9dac77fa
AK		 4181 : "=r"(ctxt->dst.val), "=q"(zf)
4182 : "r"(ctxt->src.val));
d9574a25
WY		 4183 ctxt->eflags &= ~X86_EFLAGS_ZF;
4184 if (zf) {
4185 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4186 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4187 }
4188 break;
4189 }
4190 case 0xbd: { /* bsr */
4191 u8 zf;
4192 __asm__ ("bsr %2, %0; setz %1"
9dac77fa
AK		 4193 : "=r"(ctxt->dst.val), "=q"(zf)
4194 : "r"(ctxt->src.val));
d9574a25
WY		 4195 ctxt->eflags &= ~X86_EFLAGS_ZF;
4196 if (zf) {
4197 ctxt->eflags |= X86_EFLAGS_ZF;
9dac77fa 4198 ctxt->dst.type = OP_NONE; /* Disable writeback. */
d9574a25
WY		 4199 }
4200 break;
4201 }
6aa8b732 4202 case 0xbe ... 0xbf: /* movsx */
9dac77fa
AK		 4203 ctxt->dst.bytes = ctxt->op_bytes;
4204 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
4205 (s16) ctxt->src.val;
6aa8b732 4206 break;
92f738a5 4207 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4208 emulate_2op_SrcV(ctxt, "add");
92f738a5 4209 /* Write back the register source. */
9dac77fa
AK		 4210 ctxt->src.val = ctxt->dst.orig_val;
4211 write_register_operand(&ctxt->src);
92f738a5 4212 break;
a012e65a 4213 case 0xc3: /* movnti */
9dac77fa
AK		 4214 ctxt->dst.bytes = ctxt->op_bytes;
4215 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4216 (u64) ctxt->src.val;
a012e65a 4217 break;
6aa8b732 4218 case 0xc7: /* Grp9 (cmpxchg8b) */
51187683 4219 rc = em_grp9(ctxt);
8cdbd2c9 4220 break;
91269b8f
AK		 4221 default:
4222 goto cannot_emulate;
6aa8b732 4223 }
7d9ddaed
AK		 4224
4225 if (rc != X86EMUL_CONTINUE)
4226 goto done;
4227
6aa8b732
AK		 4228 goto writeback;
4229
4230cannot_emulate:
a0c0ab2f 4231 return EMULATION_FAILED;
6aa8b732 4232}
ubuntu-bionic-kernel mirror