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KVM: Move assigned device code to own file
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
e99f0507
AP		 35#include "mmu.h" /* for is_long_mode() */
36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed
MG		 78/* Misc flags */
79#define No64 (1<<28)
0dc8d10f
GT		 80/* Source 2 operand type */
81#define Src2None (0<<29)
82#define Src2CL (1<<29)
83#define Src2ImmByte (2<<29)
84#define Src2One (3<<29)
a5f868bd 85#define Src2Imm16 (4<<29)
0dc8d10f 86#define Src2Mask (7<<29)
6aa8b732 87
43bb19cd 88enum {
1d6ad207 89 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 90 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 91};
92
45ed60b3 93static u32 opcode_table[256] = {
6aa8b732
AK		 94 /* 0x00 - 0x07 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 97 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 98 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 99 /* 0x08 - 0x0F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
d8769fed 102 0, 0, ImplicitOps | Stack | No64, 0,
6aa8b732
AK		 103 /* 0x10 - 0x17 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 106 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 107 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 108 /* 0x18 - 0x1F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 112 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 113 /* 0x20 - 0x27 */
114 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
115 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 116 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 117 /* 0x28 - 0x2F */
118 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
119 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
120 0, 0, 0, 0,
121 /* 0x30 - 0x37 */
122 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
123 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
124 0, 0, 0, 0,
125 /* 0x38 - 0x3F */
126 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
127 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 128 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
129 0, 0,
d77a2507 130 /* 0x40 - 0x47 */
33615aa9 131 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 132 /* 0x48 - 0x4F */
33615aa9 133 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 134 /* 0x50 - 0x57 */
6e3d5dfb
AK		 135 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
136 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 137 /* 0x58 - 0x5F */
6e3d5dfb
AK		 138 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
139 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 140 /* 0x60 - 0x67 */
6aa8b732 141 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 142 0, 0, 0, 0,
143 /* 0x68 - 0x6F */
91ed7a0e 144 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 145 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
146 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 147 /* 0x70 - 0x77 */
b2833e3c
GN		 148 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
149 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 150 /* 0x78 - 0x7F */
b2833e3c
GN		 151 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
152 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 153 /* 0x80 - 0x87 */
1d6ad207
AK		 154 Group | Group1_80, Group | Group1_81,
155 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 156 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
157 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
158 /* 0x88 - 0x8F */
159 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
160 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 161 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 162 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 163 /* 0x90 - 0x97 */
164 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
165 /* 0x98 - 0x9F */
d8769fed 166 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 167 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 168 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 169 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
170 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 171 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
172 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 173 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 174 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
175 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
176 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 177 /* 0xB0 - 0xB7 */
178 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
179 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
180 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
181 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
182 /* 0xB8 - 0xBF */
183 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
184 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
185 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
186 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 187 /* 0xC0 - 0xC7 */
d9413cd7 188 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 189 0, ImplicitOps | Stack, 0, 0,
d9413cd7 190 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 191 /* 0xC8 - 0xCF */
e637b823 192 0, 0, 0, ImplicitOps | Stack,
d8769fed 193 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 194 /* 0xD0 - 0xD7 */
195 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
196 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
197 0, 0, 0, 0,
198 /* 0xD8 - 0xDF */
199 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 200 /* 0xE0 - 0xE7 */
a6a3034c 201 0, 0, 0, 0,
84ce66a6
GN		 202 ByteOp | SrcImmUByte, SrcImmUByte,
203 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 204 /* 0xE8 - 0xEF */
d53c4777 205 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 206 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 207 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
208 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 209 /* 0xF0 - 0xF7 */
210 0, 0, 0, 0,
7d858a19 211 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 212 /* 0xF8 - 0xFF */
b284be57 213 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 214 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 215};
216
45ed60b3 217static u32 twobyte_table[256] = {
6aa8b732 218 /* 0x00 - 0x0F */
e99f0507 219 0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
651a3e29 220 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 221 /* 0x10 - 0x1F */
222 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x20 - 0x2F */
224 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
225 0, 0, 0, 0, 0, 0, 0, 0,
226 /* 0x30 - 0x3F */
e99f0507
AP		 227 ImplicitOps, 0, ImplicitOps, 0,
228 ImplicitOps, ImplicitOps, 0, 0,
229 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 230 /* 0x40 - 0x47 */
231 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
232 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
233 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
234 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
235 /* 0x48 - 0x4F */
236 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
237 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
238 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 /* 0x50 - 0x5F */
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0x60 - 0x6F */
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
244 /* 0x70 - 0x7F */
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
246 /* 0x80 - 0x8F */
b2833e3c
GN		 247 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
248 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 249 /* 0x90 - 0x9F */
250 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
251 /* 0xA0 - 0xA7 */
0934ac9d
MG		 252 ImplicitOps | Stack, ImplicitOps | Stack,
253 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 254 DstMem | SrcReg | Src2ImmByte | ModRM,
255 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 256 /* 0xA8 - 0xAF */
0934ac9d
MG		 257 ImplicitOps | Stack, ImplicitOps | Stack,
258 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 259 DstMem | SrcReg | Src2ImmByte | ModRM,
260 DstMem | SrcReg | Src2CL | ModRM,
261 ModRM, 0,
6aa8b732
AK		 262 /* 0xB0 - 0xB7 */
263 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 264 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 265 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
266 DstReg | SrcMem16 | ModRM | Mov,
267 /* 0xB8 - 0xBF */
038e51de 268 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 269 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
270 DstReg | SrcMem16 | ModRM | Mov,
271 /* 0xC0 - 0xCF */
a012e65a
SY		 272 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
273 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 274 /* 0xD0 - 0xDF */
275 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
276 /* 0xE0 - 0xEF */
277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
278 /* 0xF0 - 0xFF */
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
280};
281
45ed60b3 282static u32 group_table[] = {
1d6ad207
AK		 283 [Group1_80*8] =
284 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
285 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
286 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
287 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
288 [Group1_81*8] =
289 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
290 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
291 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
292 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
293 [Group1_82*8] =
294 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
295 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
296 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
297 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
298 [Group1_83*8] =
299 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
300 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
301 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
302 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 303 [Group1A*8] =
304 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 305 [Group3_Byte*8] =
306 ByteOp | SrcImm | DstMem | ModRM, 0,
307 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
308 0, 0, 0, 0,
309 [Group3*8] =
41afa025 310 DstMem | SrcImm | ModRM, 0,
6eb06cb2 311 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 312 0, 0, 0, 0,
fd60754e
AK		 313 [Group4*8] =
314 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
315 0, 0, 0, 0, 0, 0,
316 [Group5*8] =
d19292e4
MG		 317 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
318 SrcMem | ModRM | Stack, 0,
ef46f18e 319 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 320 [Group7*8] =
321 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 322 SrcNone | ModRM | DstMem | Mov, 0,
323 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 324};
325
45ed60b3 326static u32 group2_table[] = {
d95058a1 327 [Group7*8] =
fbce554e 328 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 329 SrcNone | ModRM | DstMem | Mov, 0,
330 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 331};
332
6aa8b732 333/* EFLAGS bit definitions. */
b1d86143
AP		 334#define EFLG_VM (1<<17)
335#define EFLG_RF (1<<16)
6aa8b732
AK		 336#define EFLG_OF (1<<11)
337#define EFLG_DF (1<<10)
b1d86143 338#define EFLG_IF (1<<9)
6aa8b732
AK		 339#define EFLG_SF (1<<7)
340#define EFLG_ZF (1<<6)
341#define EFLG_AF (1<<4)
342#define EFLG_PF (1<<2)
343#define EFLG_CF (1<<0)
344
345/*
346 * Instruction emulation:
347 * Most instructions are emulated directly via a fragment of inline assembly
348 * code. This allows us to save/restore EFLAGS and thus very easily pick up
349 * any modified flags.
350 */
351
05b3e0c2 352#if defined(CONFIG_X86_64)
6aa8b732
AK		 353#define _LO32 "k" /* force 32-bit operand */
354#define _STK "%%rsp" /* stack pointer */
355#elif defined(__i386__)
356#define _LO32 "" /* force 32-bit operand */
357#define _STK "%%esp" /* stack pointer */
358#endif
359
360/*
361 * These EFLAGS bits are restored from saved value during emulation, and
362 * any changes are written back to the saved value after emulation.
363 */
364#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
365
366/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 367#define _PRE_EFLAGS(_sav, _msk, _tmp) \
368 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
369 "movl %"_sav",%"_LO32 _tmp"; " \
370 "push %"_tmp"; " \
371 "push %"_tmp"; " \
372 "movl %"_msk",%"_LO32 _tmp"; " \
373 "andl %"_LO32 _tmp",("_STK"); " \
374 "pushf; " \
375 "notl %"_LO32 _tmp"; " \
376 "andl %"_LO32 _tmp",("_STK"); " \
377 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
378 "pop %"_tmp"; " \
379 "orl %"_LO32 _tmp",("_STK"); " \
380 "popf; " \
381 "pop %"_sav"; "
6aa8b732
AK		 382
383/* After executing instruction: write-back necessary bits in EFLAGS. */
384#define _POST_EFLAGS(_sav, _msk, _tmp) \
385 /* _sav |= EFLAGS & _msk; */ \
386 "pushf; " \
387 "pop %"_tmp"; " \
388 "andl %"_msk",%"_LO32 _tmp"; " \
389 "orl %"_LO32 _tmp",%"_sav"; "
390
dda96d8f
AK		 391#ifdef CONFIG_X86_64
392#define ON64(x) x
393#else
394#define ON64(x)
395#endif
396
6b7ad61f
AK		 397#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
398 do { \
399 __asm__ __volatile__ ( \
400 _PRE_EFLAGS("0", "4", "2") \
401 _op _suffix " %"_x"3,%1; " \
402 _POST_EFLAGS("0", "4", "2") \
403 : "=m" (_eflags), "=m" ((_dst).val), \
404 "=&r" (_tmp) \
405 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 406 } while (0)
6b7ad61f
AK		 407
408
6aa8b732
AK		 409/* Raw emulation: instruction has two explicit operands. */
410#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 411 do { \
412 unsigned long _tmp; \
413 \
414 switch ((_dst).bytes) { \
415 case 2: \
416 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
417 break; \
418 case 4: \
419 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
420 break; \
421 case 8: \
422 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
423 break; \
424 } \
6aa8b732
AK		 425 } while (0)
426
427#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
428 do { \
6b7ad61f 429 unsigned long _tmp; \
d77c26fc 430 switch ((_dst).bytes) { \
6aa8b732 431 case 1: \
6b7ad61f 432 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 433 break; \
434 default: \
435 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
436 _wx, _wy, _lx, _ly, _qx, _qy); \
437 break; \
438 } \
439 } while (0)
440
441/* Source operand is byte-sized and may be restricted to just %cl. */
442#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
443 __emulate_2op(_op, _src, _dst, _eflags, \
444 "b", "c", "b", "c", "b", "c", "b", "c")
445
446/* Source operand is byte, word, long or quad sized. */
447#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
448 __emulate_2op(_op, _src, _dst, _eflags, \
449 "b", "q", "w", "r", _LO32, "r", "", "r")
450
451/* Source operand is word, long or quad sized. */
452#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
453 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
454 "w", "r", _LO32, "r", "", "r")
455
d175226a
GT		 456/* Instruction has three operands and one operand is stored in ECX register */
457#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
458 do { \
459 unsigned long _tmp; \
460 _type _clv = (_cl).val; \
461 _type _srcv = (_src).val; \
462 _type _dstv = (_dst).val; \
463 \
464 __asm__ __volatile__ ( \
465 _PRE_EFLAGS("0", "5", "2") \
466 _op _suffix " %4,%1 \n" \
467 _POST_EFLAGS("0", "5", "2") \
468 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
469 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
470 ); \
471 \
472 (_cl).val = (unsigned long) _clv; \
473 (_src).val = (unsigned long) _srcv; \
474 (_dst).val = (unsigned long) _dstv; \
475 } while (0)
476
477#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
478 do { \
479 switch ((_dst).bytes) { \
480 case 2: \
481 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
482 "w", unsigned short); \
483 break; \
484 case 4: \
485 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
486 "l", unsigned int); \
487 break; \
488 case 8: \
489 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
490 "q", unsigned long)); \
491 break; \
492 } \
493 } while (0)
494
dda96d8f 495#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 496 do { \
497 unsigned long _tmp; \
498 \
dda96d8f
AK		 499 __asm__ __volatile__ ( \
500 _PRE_EFLAGS("0", "3", "2") \
501 _op _suffix " %1; " \
502 _POST_EFLAGS("0", "3", "2") \
503 : "=m" (_eflags), "+m" ((_dst).val), \
504 "=&r" (_tmp) \
505 : "i" (EFLAGS_MASK)); \
506 } while (0)
507
508/* Instruction has only one explicit operand (no source operand). */
509#define emulate_1op(_op, _dst, _eflags) \
510 do { \
d77c26fc 511 switch ((_dst).bytes) { \
dda96d8f
AK		 512 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
513 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
514 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
515 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 516 } \
517 } while (0)
518
6aa8b732
AK		 519/* Fetch next part of the instruction being emulated. */
520#define insn_fetch(_type, _size, _eip) \
521({ unsigned long _x; \
62266869 522 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 523 if (rc != 0) \
6aa8b732
AK		 524 goto done; \
525 (_eip) += (_size); \
526 (_type)_x; \
527})
528
ddcb2885
HH		 529static inline unsigned long ad_mask(struct decode_cache *c)
530{
531 return (1UL << (c->ad_bytes << 3)) - 1;
532}
533
6aa8b732 534/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 535static inline unsigned long
536address_mask(struct decode_cache *c, unsigned long reg)
537{
538 if (c->ad_bytes == sizeof(unsigned long))
539 return reg;
540 else
541 return reg & ad_mask(c);
542}
543
544static inline unsigned long
545register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
546{
547 return base + address_mask(c, reg);
548}
549
7a957275
HH		 550static inline void
551register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
552{
553 if (c->ad_bytes == sizeof(unsigned long))
554 *reg += inc;
555 else
556 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
557}
6aa8b732 558
7a957275
HH		 559static inline void jmp_rel(struct decode_cache *c, int rel)
560{
561 register_address_increment(c, &c->eip, rel);
562}
098c937b 563
7a5b56df
AK		 564static void set_seg_override(struct decode_cache *c, int seg)
565{
566 c->has_seg_override = true;
567 c->seg_override = seg;
568}
569
570static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
571{
572 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
573 return 0;
574
575 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
576}
577
578static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
579 struct decode_cache *c)
580{
581 if (!c->has_seg_override)
582 return 0;
583
584 return seg_base(ctxt, c->seg_override);
585}
586
587static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
588{
589 return seg_base(ctxt, VCPU_SREG_ES);
590}
591
592static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
593{
594 return seg_base(ctxt, VCPU_SREG_SS);
595}
596
62266869
AK		 597static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
598 struct x86_emulate_ops *ops,
599 unsigned long linear, u8 *dest)
600{
601 struct fetch_cache *fc = &ctxt->decode.fetch;
602 int rc;
603 int size;
604
605 if (linear < fc->start || linear >= fc->end) {
606 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
607 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
608 if (rc)
609 return rc;
610 fc->start = linear;
611 fc->end = linear + size;
612 }
613 *dest = fc->data[linear - fc->start];
614 return 0;
615}
616
617static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
618 struct x86_emulate_ops *ops,
619 unsigned long eip, void *dest, unsigned size)
620{
621 int rc = 0;
622
623 eip += ctxt->cs_base;
624 while (size--) {
625 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
626 if (rc)
627 return rc;
628 }
629 return 0;
630}
631
1e3c5cb0
RR		 632/*
633 * Given the 'reg' portion of a ModRM byte, and a register block, return a
634 * pointer into the block that addresses the relevant register.
635 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
636 */
637static void *decode_register(u8 modrm_reg, unsigned long *regs,
638 int highbyte_regs)
6aa8b732
AK		 639{
640 void *p;
641
642 p = &regs[modrm_reg];
643 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
644 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
645 return p;
646}
647
648static int read_descriptor(struct x86_emulate_ctxt *ctxt,
649 struct x86_emulate_ops *ops,
650 void *ptr,
651 u16 *size, unsigned long *address, int op_bytes)
652{
653 int rc;
654
655 if (op_bytes == 2)
656 op_bytes = 3;
657 *address = 0;
cebff02b
LV		 658 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
659 ctxt->vcpu);
6aa8b732
AK		 660 if (rc)
661 return rc;
cebff02b
LV		 662 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
663 ctxt->vcpu);
6aa8b732
AK		 664 return rc;
665}
666
bbe9abbd
NK		 667static int test_cc(unsigned int condition, unsigned int flags)
668{
669 int rc = 0;
670
671 switch ((condition & 15) >> 1) {
672 case 0: /* o */
673 rc |= (flags & EFLG_OF);
674 break;
675 case 1: /* b/c/nae */
676 rc |= (flags & EFLG_CF);
677 break;
678 case 2: /* z/e */
679 rc |= (flags & EFLG_ZF);
680 break;
681 case 3: /* be/na */
682 rc |= (flags & (EFLG_CF|EFLG_ZF));
683 break;
684 case 4: /* s */
685 rc |= (flags & EFLG_SF);
686 break;
687 case 5: /* p/pe */
688 rc |= (flags & EFLG_PF);
689 break;
690 case 7: /* le/ng */
691 rc |= (flags & EFLG_ZF);
692 /* fall through */
693 case 6: /* l/nge */
694 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
695 break;
696 }
697
698 /* Odd condition identifiers (lsb == 1) have inverted sense. */
699 return (!!rc ^ (condition & 1));
700}
701
3c118e24
AK		 702static void decode_register_operand(struct operand *op,
703 struct decode_cache *c,
3c118e24
AK		 704 int inhibit_bytereg)
705{
33615aa9 706 unsigned reg = c->modrm_reg;
9f1ef3f8 707 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 708
709 if (!(c->d & ModRM))
710 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 711 op->type = OP_REG;
712 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 713 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 714 op->val = *(u8 *)op->ptr;
715 op->bytes = 1;
716 } else {
33615aa9 717 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 718 op->bytes = c->op_bytes;
719 switch (op->bytes) {
720 case 2:
721 op->val = *(u16 *)op->ptr;
722 break;
723 case 4:
724 op->val = *(u32 *)op->ptr;
725 break;
726 case 8:
727 op->val = *(u64 *) op->ptr;
728 break;
729 }
730 }
731 op->orig_val = op->val;
732}
733
1c73ef66
AK		 734static int decode_modrm(struct x86_emulate_ctxt *ctxt,
735 struct x86_emulate_ops *ops)
736{
737 struct decode_cache *c = &ctxt->decode;
738 u8 sib;
f5b4edcd 739 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 740 int rc = 0;
741
742 if (c->rex_prefix) {
743 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
744 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
745 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
746 }
747
748 c->modrm = insn_fetch(u8, 1, c->eip);
749 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
750 c->modrm_reg |= (c->modrm & 0x38) >> 3;
751 c->modrm_rm |= (c->modrm & 0x07);
752 c->modrm_ea = 0;
753 c->use_modrm_ea = 1;
754
755 if (c->modrm_mod == 3) {
107d6d2e
AK		 756 c->modrm_ptr = decode_register(c->modrm_rm,
757 c->regs, c->d & ByteOp);
758 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 759 return rc;
760 }
761
762 if (c->ad_bytes == 2) {
763 unsigned bx = c->regs[VCPU_REGS_RBX];
764 unsigned bp = c->regs[VCPU_REGS_RBP];
765 unsigned si = c->regs[VCPU_REGS_RSI];
766 unsigned di = c->regs[VCPU_REGS_RDI];
767
768 /* 16-bit ModR/M decode. */
769 switch (c->modrm_mod) {
770 case 0:
771 if (c->modrm_rm == 6)
772 c->modrm_ea += insn_fetch(u16, 2, c->eip);
773 break;
774 case 1:
775 c->modrm_ea += insn_fetch(s8, 1, c->eip);
776 break;
777 case 2:
778 c->modrm_ea += insn_fetch(u16, 2, c->eip);
779 break;
780 }
781 switch (c->modrm_rm) {
782 case 0:
783 c->modrm_ea += bx + si;
784 break;
785 case 1:
786 c->modrm_ea += bx + di;
787 break;
788 case 2:
789 c->modrm_ea += bp + si;
790 break;
791 case 3:
792 c->modrm_ea += bp + di;
793 break;
794 case 4:
795 c->modrm_ea += si;
796 break;
797 case 5:
798 c->modrm_ea += di;
799 break;
800 case 6:
801 if (c->modrm_mod != 0)
802 c->modrm_ea += bp;
803 break;
804 case 7:
805 c->modrm_ea += bx;
806 break;
807 }
808 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
809 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 810 if (!c->has_seg_override)
811 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 812 c->modrm_ea = (u16)c->modrm_ea;
813 } else {
814 /* 32/64-bit ModR/M decode. */
84411d85 815 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 816 sib = insn_fetch(u8, 1, c->eip);
817 index_reg |= (sib >> 3) & 7;
818 base_reg |= sib & 7;
819 scale = sib >> 6;
820
dc71d0f1
AK		 821 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
822 c->modrm_ea += insn_fetch(s32, 4, c->eip);
823 else
1c73ef66 824 c->modrm_ea += c->regs[base_reg];
dc71d0f1 825 if (index_reg != 4)
1c73ef66 826 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 827 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
828 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 829 c->rip_relative = 1;
84411d85 830 } else
1c73ef66 831 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 832 switch (c->modrm_mod) {
833 case 0:
834 if (c->modrm_rm == 5)
835 c->modrm_ea += insn_fetch(s32, 4, c->eip);
836 break;
837 case 1:
838 c->modrm_ea += insn_fetch(s8, 1, c->eip);
839 break;
840 case 2:
841 c->modrm_ea += insn_fetch(s32, 4, c->eip);
842 break;
843 }
844 }
1c73ef66
AK		 845done:
846 return rc;
847}
848
849static int decode_abs(struct x86_emulate_ctxt *ctxt,
850 struct x86_emulate_ops *ops)
851{
852 struct decode_cache *c = &ctxt->decode;
853 int rc = 0;
854
855 switch (c->ad_bytes) {
856 case 2:
857 c->modrm_ea = insn_fetch(u16, 2, c->eip);
858 break;
859 case 4:
860 c->modrm_ea = insn_fetch(u32, 4, c->eip);
861 break;
862 case 8:
863 c->modrm_ea = insn_fetch(u64, 8, c->eip);
864 break;
865 }
866done:
867 return rc;
868}
869
6aa8b732 870int
8b4caf66 871x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 872{
e4e03ded 873 struct decode_cache *c = &ctxt->decode;
6aa8b732 874 int rc = 0;
6aa8b732 875 int mode = ctxt->mode;
e09d082c 876 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 877
878 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 879
e4e03ded 880 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 881 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 882 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 883 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 884
885 switch (mode) {
886 case X86EMUL_MODE_REAL:
887 case X86EMUL_MODE_PROT16:
f21b8bf4 888 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 889 break;
890 case X86EMUL_MODE_PROT32:
f21b8bf4 891 def_op_bytes = def_ad_bytes = 4;
6aa8b732 892 break;
05b3e0c2 893#ifdef CONFIG_X86_64
6aa8b732 894 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 895 def_op_bytes = 4;
896 def_ad_bytes = 8;
6aa8b732
AK		 897 break;
898#endif
899 default:
900 return -1;
901 }
902
f21b8bf4
AK		 903 c->op_bytes = def_op_bytes;
904 c->ad_bytes = def_ad_bytes;
905
6aa8b732 906 /* Legacy prefixes. */
b4c6abfe 907 for (;;) {
e4e03ded 908 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 909 case 0x66: /* operand-size override */
f21b8bf4
AK		 910 /* switch between 2/4 bytes */
911 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 912 break;
913 case 0x67: /* address-size override */
914 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 915 /* switch between 4/8 bytes */
f21b8bf4 916 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 917 else
e4e03ded 918 /* switch between 2/4 bytes */
f21b8bf4 919 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 920 break;
7a5b56df 921 case 0x26: /* ES override */
6aa8b732 922 case 0x2e: /* CS override */
7a5b56df 923 case 0x36: /* SS override */
6aa8b732 924 case 0x3e: /* DS override */
7a5b56df 925 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 926 break;
927 case 0x64: /* FS override */
6aa8b732 928 case 0x65: /* GS override */
7a5b56df 929 set_seg_override(c, c->b & 7);
6aa8b732 930 break;
b4c6abfe
LV		 931 case 0x40 ... 0x4f: /* REX */
932 if (mode != X86EMUL_MODE_PROT64)
933 goto done_prefixes;
33615aa9 934 c->rex_prefix = c->b;
b4c6abfe 935 continue;
6aa8b732 936 case 0xf0: /* LOCK */
e4e03ded 937 c->lock_prefix = 1;
6aa8b732 938 break;
ae6200ba 939 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 940 c->rep_prefix = REPNE_PREFIX;
941 break;
6aa8b732 942 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 943 c->rep_prefix = REPE_PREFIX;
6aa8b732 944 break;
6aa8b732
AK		 945 default:
946 goto done_prefixes;
947 }
b4c6abfe
LV		 948
949 /* Any legacy prefix after a REX prefix nullifies its effect. */
950
33615aa9 951 c->rex_prefix = 0;
6aa8b732
AK		 952 }
953
954done_prefixes:
955
956 /* REX prefix. */
1c73ef66 957 if (c->rex_prefix)
33615aa9 958 if (c->rex_prefix & 8)
e4e03ded 959 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 960
961 /* Opcode byte(s). */
e4e03ded
LV		 962 c->d = opcode_table[c->b];
963 if (c->d == 0) {
6aa8b732 964 /* Two-byte opcode? */
e4e03ded
LV		 965 if (c->b == 0x0f) {
966 c->twobyte = 1;
967 c->b = insn_fetch(u8, 1, c->eip);
968 c->d = twobyte_table[c->b];
6aa8b732 969 }
e09d082c 970 }
6aa8b732 971
d8769fed
MG		 972 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
973 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
974 return -1;
975 }
976
e09d082c
AK		 977 if (c->d & Group) {
978 group = c->d & GroupMask;
979 c->modrm = insn_fetch(u8, 1, c->eip);
980 --c->eip;
981
982 group = (group << 3) + ((c->modrm >> 3) & 7);
983 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
984 c->d = group2_table[group];
985 else
986 c->d = group_table[group];
987 }
988
989 /* Unrecognised? */
990 if (c->d == 0) {
991 DPRINTF("Cannot emulate %02x\n", c->b);
992 return -1;
6aa8b732
AK		 993 }
994
6e3d5dfb
AK		 995 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
996 c->op_bytes = 8;
997
6aa8b732 998 /* ModRM and SIB bytes. */
1c73ef66
AK		 999 if (c->d & ModRM)
1000 rc = decode_modrm(ctxt, ops);
1001 else if (c->d & MemAbs)
1002 rc = decode_abs(ctxt, ops);
1003 if (rc)
1004 goto done;
6aa8b732 1005
7a5b56df
AK		 1006 if (!c->has_seg_override)
1007 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1008
7a5b56df
AK		 1009 if (!(!c->twobyte && c->b == 0x8d))
1010 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1011
1012 if (c->ad_bytes != 8)
1013 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1014 /*
1015 * Decode and fetch the source operand: register, memory
1016 * or immediate.
1017 */
e4e03ded 1018 switch (c->d & SrcMask) {
6aa8b732
AK		 1019 case SrcNone:
1020 break;
1021 case SrcReg:
9f1ef3f8 1022 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1023 break;
1024 case SrcMem16:
e4e03ded 1025 c->src.bytes = 2;
6aa8b732
AK		 1026 goto srcmem_common;
1027 case SrcMem32:
e4e03ded 1028 c->src.bytes = 4;
6aa8b732
AK		 1029 goto srcmem_common;
1030 case SrcMem:
e4e03ded
LV		 1031 c->src.bytes = (c->d & ByteOp) ? 1 :
1032 c->op_bytes;
b85b9ee9 1033 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1034 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1035 break;
d77c26fc 1036 srcmem_common:
4e62417b
AJ		 1037 /*
1038 * For instructions with a ModR/M byte, switch to register
1039 * access if Mod = 3.
1040 */
e4e03ded
LV		 1041 if ((c->d & ModRM) && c->modrm_mod == 3) {
1042 c->src.type = OP_REG;
66b85505 1043 c->src.val = c->modrm_val;
107d6d2e 1044 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1045 break;
1046 }
e4e03ded 1047 c->src.type = OP_MEM;
6aa8b732
AK		 1048 break;
1049 case SrcImm:
c9eaf20f 1050 case SrcImmU:
e4e03ded
LV		 1051 c->src.type = OP_IMM;
1052 c->src.ptr = (unsigned long *)c->eip;
1053 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1054 if (c->src.bytes == 8)
1055 c->src.bytes = 4;
6aa8b732 1056 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1057 switch (c->src.bytes) {
6aa8b732 1058 case 1:
e4e03ded 1059 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1060 break;
1061 case 2:
e4e03ded 1062 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1063 break;
1064 case 4:
e4e03ded 1065 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1066 break;
1067 }
c9eaf20f
AK		 1068 if ((c->d & SrcMask) == SrcImmU) {
1069 switch (c->src.bytes) {
1070 case 1:
1071 c->src.val &= 0xff;
1072 break;
1073 case 2:
1074 c->src.val &= 0xffff;
1075 break;
1076 case 4:
1077 c->src.val &= 0xffffffff;
1078 break;
1079 }
1080 }
6aa8b732
AK		 1081 break;
1082 case SrcImmByte:
341de7e3 1083 case SrcImmUByte:
e4e03ded
LV		 1084 c->src.type = OP_IMM;
1085 c->src.ptr = (unsigned long *)c->eip;
1086 c->src.bytes = 1;
341de7e3
GN		 1087 if ((c->d & SrcMask) == SrcImmByte)
1088 c->src.val = insn_fetch(s8, 1, c->eip);
1089 else
1090 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1091 break;
bfcadf83
GT		 1092 case SrcOne:
1093 c->src.bytes = 1;
1094 c->src.val = 1;
1095 break;
6aa8b732
AK		 1096 }
1097
0dc8d10f
GT		 1098 /*
1099 * Decode and fetch the second source operand: register, memory
1100 * or immediate.
1101 */
1102 switch (c->d & Src2Mask) {
1103 case Src2None:
1104 break;
1105 case Src2CL:
1106 c->src2.bytes = 1;
1107 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1108 break;
1109 case Src2ImmByte:
1110 c->src2.type = OP_IMM;
1111 c->src2.ptr = (unsigned long *)c->eip;
1112 c->src2.bytes = 1;
1113 c->src2.val = insn_fetch(u8, 1, c->eip);
1114 break;
a5f868bd
GN		 1115 case Src2Imm16:
1116 c->src2.type = OP_IMM;
1117 c->src2.ptr = (unsigned long *)c->eip;
1118 c->src2.bytes = 2;
1119 c->src2.val = insn_fetch(u16, 2, c->eip);
1120 break;
0dc8d10f
GT		 1121 case Src2One:
1122 c->src2.bytes = 1;
1123 c->src2.val = 1;
1124 break;
1125 }
1126
038e51de 1127 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1128 switch (c->d & DstMask) {
038e51de
AK		 1129 case ImplicitOps:
1130 /* Special instructions do their own operand decoding. */
8b4caf66 1131 return 0;
038e51de 1132 case DstReg:
9f1ef3f8 1133 decode_register_operand(&c->dst, c,
3c118e24 1134 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1135 break;
1136 case DstMem:
e4e03ded 1137 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1138 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1139 c->dst.type = OP_REG;
66b85505 1140 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1141 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1142 break;
1143 }
8b4caf66
LV		 1144 c->dst.type = OP_MEM;
1145 break;
9c9fddd0
GT		 1146 case DstAcc:
1147 c->dst.type = OP_REG;
1148 c->dst.bytes = c->op_bytes;
1149 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1150 switch (c->op_bytes) {
1151 case 1:
1152 c->dst.val = *(u8 *)c->dst.ptr;
1153 break;
1154 case 2:
1155 c->dst.val = *(u16 *)c->dst.ptr;
1156 break;
1157 case 4:
1158 c->dst.val = *(u32 *)c->dst.ptr;
1159 break;
1160 }
1161 c->dst.orig_val = c->dst.val;
1162 break;
8b4caf66
LV		 1163 }
1164
f5b4edcd
AK		 1165 if (c->rip_relative)
1166 c->modrm_ea += c->eip;
1167
8b4caf66
LV		 1168done:
1169 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1170}
1171
8cdbd2c9
LV		 1172static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1173{
1174 struct decode_cache *c = &ctxt->decode;
1175
1176 c->dst.type = OP_MEM;
1177 c->dst.bytes = c->op_bytes;
1178 c->dst.val = c->src.val;
7a957275 1179 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1180 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1181 c->regs[VCPU_REGS_RSP]);
1182}
1183
faa5a3ae 1184static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1185 struct x86_emulate_ops *ops,
1186 void *dest, int len)
8cdbd2c9
LV		 1187{
1188 struct decode_cache *c = &ctxt->decode;
1189 int rc;
1190
781d0edc
AK		 1191 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1192 c->regs[VCPU_REGS_RSP]),
350f69dc 1193 dest, len, ctxt->vcpu);
8cdbd2c9
LV		 1194 if (rc != 0)
1195 return rc;
1196
350f69dc 1197 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1198 return rc;
1199}
8cdbd2c9 1200
0934ac9d
MG		 1201static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1202{
1203 struct decode_cache *c = &ctxt->decode;
1204 struct kvm_segment segment;
1205
1206 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1207
1208 c->src.val = segment.selector;
1209 emulate_push(ctxt);
1210}
1211
1212static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1213 struct x86_emulate_ops *ops, int seg)
1214{
1215 struct decode_cache *c = &ctxt->decode;
1216 unsigned long selector;
1217 int rc;
1218
1219 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1220 if (rc != 0)
1221 return rc;
1222
1223 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1224 return rc;
1225}
1226
faa5a3ae
AK		 1227static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1228 struct x86_emulate_ops *ops)
1229{
1230 struct decode_cache *c = &ctxt->decode;
1231 int rc;
1232
350f69dc 1233 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1234 if (rc != 0)
1235 return rc;
8cdbd2c9
LV		 1236 return 0;
1237}
1238
05f086f8 1239static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1240{
05f086f8 1241 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1242 switch (c->modrm_reg) {
1243 case 0: /* rol */
05f086f8 1244 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1245 break;
1246 case 1: /* ror */
05f086f8 1247 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1248 break;
1249 case 2: /* rcl */
05f086f8 1250 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1251 break;
1252 case 3: /* rcr */
05f086f8 1253 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1254 break;
1255 case 4: /* sal/shl */
1256 case 6: /* sal/shl */
05f086f8 1257 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1258 break;
1259 case 5: /* shr */
05f086f8 1260 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1261 break;
1262 case 7: /* sar */
05f086f8 1263 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1264 break;
1265 }
1266}
1267
1268static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1269 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1270{
1271 struct decode_cache *c = &ctxt->decode;
1272 int rc = 0;
1273
1274 switch (c->modrm_reg) {
1275 case 0 ... 1: /* test */
05f086f8 1276 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1277 break;
1278 case 2: /* not */
1279 c->dst.val = ~c->dst.val;
1280 break;
1281 case 3: /* neg */
05f086f8 1282 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1283 break;
1284 default:
1285 DPRINTF("Cannot emulate %02x\n", c->b);
1286 rc = X86EMUL_UNHANDLEABLE;
1287 break;
1288 }
8cdbd2c9
LV		 1289 return rc;
1290}
1291
1292static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1293 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1294{
1295 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1296
1297 switch (c->modrm_reg) {
1298 case 0: /* inc */
05f086f8 1299 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1300 break;
1301 case 1: /* dec */
05f086f8 1302 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1303 break;
d19292e4
MG		 1304 case 2: /* call near abs */ {
1305 long int old_eip;
1306 old_eip = c->eip;
1307 c->eip = c->src.val;
1308 c->src.val = old_eip;
1309 emulate_push(ctxt);
1310 break;
1311 }
8cdbd2c9 1312 case 4: /* jmp abs */
fd60754e 1313 c->eip = c->src.val;
8cdbd2c9
LV		 1314 break;
1315 case 6: /* push */
fd60754e 1316 emulate_push(ctxt);
8cdbd2c9 1317 break;
8cdbd2c9
LV		 1318 }
1319 return 0;
1320}
1321
1322static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1323 struct x86_emulate_ops *ops,
e8d8d7fe 1324 unsigned long memop)
8cdbd2c9
LV		 1325{
1326 struct decode_cache *c = &ctxt->decode;
1327 u64 old, new;
1328 int rc;
1329
e8d8d7fe 1330 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1331 if (rc != 0)
1332 return rc;
1333
1334 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1335 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1336
1337 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1338 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1339 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1340
1341 } else {
1342 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1343 (u32) c->regs[VCPU_REGS_RBX];
1344
e8d8d7fe 1345 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1346 if (rc != 0)
1347 return rc;
05f086f8 1348 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1349 }
1350 return 0;
1351}
1352
a77ab5ea
AK		 1353static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1354 struct x86_emulate_ops *ops)
1355{
1356 struct decode_cache *c = &ctxt->decode;
1357 int rc;
1358 unsigned long cs;
1359
1360 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1361 if (rc)
1362 return rc;
1363 if (c->op_bytes == 4)
1364 c->eip = (u32)c->eip;
1365 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1366 if (rc)
1367 return rc;
1368 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1369 return rc;
1370}
1371
8cdbd2c9
LV		 1372static inline int writeback(struct x86_emulate_ctxt *ctxt,
1373 struct x86_emulate_ops *ops)
1374{
1375 int rc;
1376 struct decode_cache *c = &ctxt->decode;
1377
1378 switch (c->dst.type) {
1379 case OP_REG:
1380 /* The 4-byte case *is* correct:
1381 * in 64-bit mode we zero-extend.
1382 */
1383 switch (c->dst.bytes) {
1384 case 1:
1385 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1386 break;
1387 case 2:
1388 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1389 break;
1390 case 4:
1391 *c->dst.ptr = (u32)c->dst.val;
1392 break; /* 64b: zero-ext */
1393 case 8:
1394 *c->dst.ptr = c->dst.val;
1395 break;
1396 }
1397 break;
1398 case OP_MEM:
1399 if (c->lock_prefix)
1400 rc = ops->cmpxchg_emulated(
1401 (unsigned long)c->dst.ptr,
1402 &c->dst.orig_val,
1403 &c->dst.val,
1404 c->dst.bytes,
1405 ctxt->vcpu);
1406 else
1407 rc = ops->write_emulated(
1408 (unsigned long)c->dst.ptr,
1409 &c->dst.val,
1410 c->dst.bytes,
1411 ctxt->vcpu);
1412 if (rc != 0)
1413 return rc;
a01af5ec
LV		 1414 break;
1415 case OP_NONE:
1416 /* no writeback */
1417 break;
8cdbd2c9
LV		 1418 default:
1419 break;
1420 }
1421 return 0;
1422}
1423
a3f9d398 1424static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1425{
1426 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1427 /*
1428 * an sti; sti; sequence only disable interrupts for the first
1429 * instruction. So, if the last instruction, be it emulated or
1430 * not, left the system with the INT_STI flag enabled, it
1431 * means that the last instruction is an sti. We should not
1432 * leave the flag on in this case. The same goes for mov ss
1433 */
1434 if (!(int_shadow & mask))
1435 ctxt->interruptibility = mask;
1436}
1437
e66bb2cc
AP		 1438static inline void
1439setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1440 struct kvm_segment *cs, struct kvm_segment *ss)
1441{
1442 memset(cs, 0, sizeof(struct kvm_segment));
1443 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1444 memset(ss, 0, sizeof(struct kvm_segment));
1445
1446 cs->l = 0; /* will be adjusted later */
1447 cs->base = 0; /* flat segment */
1448 cs->g = 1; /* 4kb granularity */
1449 cs->limit = 0xffffffff; /* 4GB limit */
1450 cs->type = 0x0b; /* Read, Execute, Accessed */
1451 cs->s = 1;
1452 cs->dpl = 0; /* will be adjusted later */
1453 cs->present = 1;
1454 cs->db = 1;
1455
1456 ss->unusable = 0;
1457 ss->base = 0; /* flat segment */
1458 ss->limit = 0xffffffff; /* 4GB limit */
1459 ss->g = 1; /* 4kb granularity */
1460 ss->s = 1;
1461 ss->type = 0x03; /* Read/Write, Accessed */
1462 ss->db = 1; /* 32bit stack segment */
1463 ss->dpl = 0;
1464 ss->present = 1;
1465}
1466
1467static int
1468emulate_syscall(struct x86_emulate_ctxt *ctxt)
1469{
1470 struct decode_cache *c = &ctxt->decode;
1471 struct kvm_segment cs, ss;
1472 u64 msr_data;
1473
1474 /* syscall is not available in real mode */
1475 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
1476 || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE))
1477 return -1;
1478
1479 setup_syscalls_segments(ctxt, &cs, &ss);
1480
1481 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1482 msr_data >>= 32;
1483 cs.selector = (u16)(msr_data & 0xfffc);
1484 ss.selector = (u16)(msr_data + 8);
1485
1486 if (is_long_mode(ctxt->vcpu)) {
1487 cs.db = 0;
1488 cs.l = 1;
1489 }
1490 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1491 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1492
1493 c->regs[VCPU_REGS_RCX] = c->eip;
1494 if (is_long_mode(ctxt->vcpu)) {
1495#ifdef CONFIG_X86_64
1496 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1497
1498 kvm_x86_ops->get_msr(ctxt->vcpu,
1499 ctxt->mode == X86EMUL_MODE_PROT64 ?
1500 MSR_LSTAR : MSR_CSTAR, &msr_data);
1501 c->eip = msr_data;
1502
1503 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1504 ctxt->eflags &= ~(msr_data | EFLG_RF);
1505#endif
1506 } else {
1507 /* legacy mode */
1508 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1509 c->eip = (u32)msr_data;
1510
1511 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1512 }
1513
1514 return 0;
1515}
1516
8c604352
AP		 1517static int
1518emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1519{
1520 struct decode_cache *c = &ctxt->decode;
1521 struct kvm_segment cs, ss;
1522 u64 msr_data;
1523
1524 /* inject #UD if LOCK prefix is used */
1525 if (c->lock_prefix)
1526 return -1;
1527
1528 /* inject #GP if in real mode or paging is disabled */
1529 if (ctxt->mode == X86EMUL_MODE_REAL ||
1530 !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
1531 kvm_inject_gp(ctxt->vcpu, 0);
1532 return -1;
1533 }
1534
1535 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1536 * Therefore, we inject an #UD.
1537 */
1538 if (ctxt->mode == X86EMUL_MODE_PROT64)
1539 return -1;
1540
1541 setup_syscalls_segments(ctxt, &cs, &ss);
1542
1543 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1544 switch (ctxt->mode) {
1545 case X86EMUL_MODE_PROT32:
1546 if ((msr_data & 0xfffc) == 0x0) {
1547 kvm_inject_gp(ctxt->vcpu, 0);
1548 return -1;
1549 }
1550 break;
1551 case X86EMUL_MODE_PROT64:
1552 if (msr_data == 0x0) {
1553 kvm_inject_gp(ctxt->vcpu, 0);
1554 return -1;
1555 }
1556 break;
1557 }
1558
1559 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1560 cs.selector = (u16)msr_data;
1561 cs.selector &= ~SELECTOR_RPL_MASK;
1562 ss.selector = cs.selector + 8;
1563 ss.selector &= ~SELECTOR_RPL_MASK;
1564 if (ctxt->mode == X86EMUL_MODE_PROT64
1565 || is_long_mode(ctxt->vcpu)) {
1566 cs.db = 0;
1567 cs.l = 1;
1568 }
1569
1570 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1571 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1572
1573 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1574 c->eip = msr_data;
1575
1576 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1577 c->regs[VCPU_REGS_RSP] = msr_data;
1578
1579 return 0;
1580}
1581
4668f050
AP		 1582static int
1583emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1584{
1585 struct decode_cache *c = &ctxt->decode;
1586 struct kvm_segment cs, ss;
1587 u64 msr_data;
1588 int usermode;
1589
1590 /* inject #UD if LOCK prefix is used */
1591 if (c->lock_prefix)
1592 return -1;
1593
1594 /* inject #GP if in real mode or paging is disabled */
1595 if (ctxt->mode == X86EMUL_MODE_REAL
1596 || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
1597 kvm_inject_gp(ctxt->vcpu, 0);
1598 return -1;
1599 }
1600
1601 /* sysexit must be called from CPL 0 */
1602 if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
1603 kvm_inject_gp(ctxt->vcpu, 0);
1604 return -1;
1605 }
1606
1607 setup_syscalls_segments(ctxt, &cs, &ss);
1608
1609 if ((c->rex_prefix & 0x8) != 0x0)
1610 usermode = X86EMUL_MODE_PROT64;
1611 else
1612 usermode = X86EMUL_MODE_PROT32;
1613
1614 cs.dpl = 3;
1615 ss.dpl = 3;
1616 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1617 switch (usermode) {
1618 case X86EMUL_MODE_PROT32:
1619 cs.selector = (u16)(msr_data + 16);
1620 if ((msr_data & 0xfffc) == 0x0) {
1621 kvm_inject_gp(ctxt->vcpu, 0);
1622 return -1;
1623 }
1624 ss.selector = (u16)(msr_data + 24);
1625 break;
1626 case X86EMUL_MODE_PROT64:
1627 cs.selector = (u16)(msr_data + 32);
1628 if (msr_data == 0x0) {
1629 kvm_inject_gp(ctxt->vcpu, 0);
1630 return -1;
1631 }
1632 ss.selector = cs.selector + 8;
1633 cs.db = 0;
1634 cs.l = 1;
1635 break;
1636 }
1637 cs.selector |= SELECTOR_RPL_MASK;
1638 ss.selector |= SELECTOR_RPL_MASK;
1639
1640 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1641 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1642
1643 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1644 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1645
1646 return 0;
1647}
1648
8b4caf66 1649int
1be3aa47 1650x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1651{
e8d8d7fe 1652 unsigned long memop = 0;
8b4caf66 1653 u64 msr_data;
3427318f 1654 unsigned long saved_eip = 0;
8b4caf66 1655 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1656 unsigned int port;
1657 int io_dir_in;
1be3aa47 1658 int rc = 0;
8b4caf66 1659
310b5d30
GC		 1660 ctxt->interruptibility = 0;
1661
3427318f
LV		 1662 /* Shadow copy of register state. Committed on successful emulation.
1663 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1664 * modify them.
1665 */
1666
ad312c7c 1667 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1668 saved_eip = c->eip;
1669
c7e75a3d 1670 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1671 memop = c->modrm_ea;
8b4caf66 1672
b9fa9d6b
AK		 1673 if (c->rep_prefix && (c->d & String)) {
1674 /* All REP prefixes have the same first termination condition */
1675 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1676 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1677 goto done;
1678 }
1679 /* The second termination condition only applies for REPE
1680 * and REPNE. Test if the repeat string operation prefix is
1681 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1682 * corresponding termination condition according to:
1683 * - if REPE/REPZ and ZF = 0 then done
1684 * - if REPNE/REPNZ and ZF = 1 then done
1685 */
1686 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1687 (c->b == 0xae) || (c->b == 0xaf)) {
1688 if ((c->rep_prefix == REPE_PREFIX) &&
1689 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1690 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1691 goto done;
1692 }
1693 if ((c->rep_prefix == REPNE_PREFIX) &&
1694 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1695 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1696 goto done;
1697 }
1698 }
1699 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1700 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1701 }
1702
8b4caf66 1703 if (c->src.type == OP_MEM) {
e8d8d7fe 1704 c->src.ptr = (unsigned long *)memop;
8b4caf66 1705 c->src.val = 0;
d77c26fc
MD		 1706 rc = ops->read_emulated((unsigned long)c->src.ptr,
1707 &c->src.val,
1708 c->src.bytes,
1709 ctxt->vcpu);
1710 if (rc != 0)
8b4caf66
LV		 1711 goto done;
1712 c->src.orig_val = c->src.val;
1713 }
1714
1715 if ((c->d & DstMask) == ImplicitOps)
1716 goto special_insn;
1717
1718
1719 if (c->dst.type == OP_MEM) {
e8d8d7fe 1720 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1721 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1722 c->dst.val = 0;
e4e03ded
LV		 1723 if (c->d & BitOp) {
1724 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1725
e4e03ded
LV		 1726 c->dst.ptr = (void *)c->dst.ptr +
1727 (c->src.val & mask) / 8;
038e51de 1728 }
e4e03ded
LV		 1729 if (!(c->d & Mov) &&
1730 /* optimisation - avoid slow emulated read */
1731 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1732 &c->dst.val,
1733 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1734 goto done;
038e51de 1735 }
e4e03ded 1736 c->dst.orig_val = c->dst.val;
038e51de 1737
018a98db
AK		 1738special_insn:
1739
e4e03ded 1740 if (c->twobyte)
6aa8b732
AK		 1741 goto twobyte_insn;
1742
e4e03ded 1743 switch (c->b) {
6aa8b732
AK		 1744 case 0x00 ... 0x05:
1745 add: /* add */
05f086f8 1746 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1747 break;
0934ac9d 1748 case 0x06: /* push es */
0934ac9d
MG		 1749 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1750 break;
1751 case 0x07: /* pop es */
0934ac9d
MG		 1752 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1753 if (rc != 0)
1754 goto done;
1755 break;
6aa8b732
AK		 1756 case 0x08 ... 0x0d:
1757 or: /* or */
05f086f8 1758 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1759 break;
0934ac9d 1760 case 0x0e: /* push cs */
0934ac9d
MG		 1761 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1762 break;
6aa8b732
AK		 1763 case 0x10 ... 0x15:
1764 adc: /* adc */
05f086f8 1765 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1766 break;
0934ac9d 1767 case 0x16: /* push ss */
0934ac9d
MG		 1768 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1769 break;
1770 case 0x17: /* pop ss */
0934ac9d
MG		 1771 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1772 if (rc != 0)
1773 goto done;
1774 break;
6aa8b732
AK		 1775 case 0x18 ... 0x1d:
1776 sbb: /* sbb */
05f086f8 1777 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1778 break;
0934ac9d 1779 case 0x1e: /* push ds */
0934ac9d
MG		 1780 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1781 break;
1782 case 0x1f: /* pop ds */
0934ac9d
MG		 1783 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1784 if (rc != 0)
1785 goto done;
1786 break;
aa3a816b 1787 case 0x20 ... 0x25:
6aa8b732 1788 and: /* and */
05f086f8 1789 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1790 break;
1791 case 0x28 ... 0x2d:
1792 sub: /* sub */
05f086f8 1793 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1794 break;
1795 case 0x30 ... 0x35:
1796 xor: /* xor */
05f086f8 1797 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1798 break;
1799 case 0x38 ... 0x3d:
1800 cmp: /* cmp */
05f086f8 1801 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1802 break;
33615aa9
AK		 1803 case 0x40 ... 0x47: /* inc r16/r32 */
1804 emulate_1op("inc", c->dst, ctxt->eflags);
1805 break;
1806 case 0x48 ... 0x4f: /* dec r16/r32 */
1807 emulate_1op("dec", c->dst, ctxt->eflags);
1808 break;
1809 case 0x50 ... 0x57: /* push reg */
2786b014 1810 emulate_push(ctxt);
33615aa9
AK		 1811 break;
1812 case 0x58 ... 0x5f: /* pop reg */
1813 pop_instruction:
350f69dc 1814 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1815 if (rc != 0)
33615aa9 1816 goto done;
33615aa9 1817 break;
6aa8b732 1818 case 0x63: /* movsxd */
8b4caf66 1819 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1820 goto cannot_emulate;
e4e03ded 1821 c->dst.val = (s32) c->src.val;
6aa8b732 1822 break;
91ed7a0e 1823 case 0x68: /* push imm */
018a98db 1824 case 0x6a: /* push imm8 */
018a98db
AK		 1825 emulate_push(ctxt);
1826 break;
1827 case 0x6c: /* insb */
1828 case 0x6d: /* insw/insd */
851ba692 1829 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1830 1,
1831 (c->d & ByteOp) ? 1 : c->op_bytes,
1832 c->rep_prefix ?
e4706772 1833 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1834 (ctxt->eflags & EFLG_DF),
7a5b56df 1835 register_address(c, es_base(ctxt),
018a98db
AK		 1836 c->regs[VCPU_REGS_RDI]),
1837 c->rep_prefix,
1838 c->regs[VCPU_REGS_RDX]) == 0) {
1839 c->eip = saved_eip;
1840 return -1;
1841 }
1842 return 0;
1843 case 0x6e: /* outsb */
1844 case 0x6f: /* outsw/outsd */
851ba692 1845 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 1846 0,
1847 (c->d & ByteOp) ? 1 : c->op_bytes,
1848 c->rep_prefix ?
e4706772 1849 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1850 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1851 register_address(c,
1852 seg_override_base(ctxt, c),
018a98db
AK		 1853 c->regs[VCPU_REGS_RSI]),
1854 c->rep_prefix,
1855 c->regs[VCPU_REGS_RDX]) == 0) {
1856 c->eip = saved_eip;
1857 return -1;
1858 }
1859 return 0;
b2833e3c 1860 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1861 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1862 jmp_rel(c, c->src.val);
018a98db 1863 break;
6aa8b732 1864 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1865 switch (c->modrm_reg) {
6aa8b732
AK		 1866 case 0:
1867 goto add;
1868 case 1:
1869 goto or;
1870 case 2:
1871 goto adc;
1872 case 3:
1873 goto sbb;
1874 case 4:
1875 goto and;
1876 case 5:
1877 goto sub;
1878 case 6:
1879 goto xor;
1880 case 7:
1881 goto cmp;
1882 }
1883 break;
1884 case 0x84 ... 0x85:
05f086f8 1885 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1886 break;
1887 case 0x86 ... 0x87: /* xchg */
b13354f8 1888 xchg:
6aa8b732 1889 /* Write back the register source. */
e4e03ded 1890 switch (c->dst.bytes) {
6aa8b732 1891 case 1:
e4e03ded 1892 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1893 break;
1894 case 2:
e4e03ded 1895 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1896 break;
1897 case 4:
e4e03ded 1898 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1899 break; /* 64b reg: zero-extend */
1900 case 8:
e4e03ded 1901 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1902 break;
1903 }
1904 /*
1905 * Write back the memory destination with implicit LOCK
1906 * prefix.
1907 */
e4e03ded
LV		 1908 c->dst.val = c->src.val;
1909 c->lock_prefix = 1;
6aa8b732 1910 break;
6aa8b732 1911 case 0x88 ... 0x8b: /* mov */
7de75248 1912 goto mov;
38d5bc6d
GT		 1913 case 0x8c: { /* mov r/m, sreg */
1914 struct kvm_segment segreg;
1915
1916 if (c->modrm_reg <= 5)
1917 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1918 else {
1919 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1920 c->modrm);
1921 goto cannot_emulate;
1922 }
1923 c->dst.val = segreg.selector;
1924 break;
1925 }
7e0b54b1 1926 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1927 c->dst.val = c->modrm_ea;
7e0b54b1 1928 break;
4257198a
GT		 1929 case 0x8e: { /* mov seg, r/m16 */
1930 uint16_t sel;
1931 int type_bits;
1932 int err;
1933
1934 sel = c->src.val;
310b5d30
GC		 1935 if (c->modrm_reg == VCPU_SREG_SS)
1936 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
1937
4257198a
GT		 1938 if (c->modrm_reg <= 5) {
1939 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1940 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1941 type_bits, c->modrm_reg);
1942 } else {
1943 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1944 c->modrm);
1945 goto cannot_emulate;
1946 }
1947
1948 if (err < 0)
1949 goto cannot_emulate;
1950
1951 c->dst.type = OP_NONE; /* Disable writeback. */
1952 break;
1953 }
6aa8b732 1954 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1955 rc = emulate_grp1a(ctxt, ops);
1956 if (rc != 0)
6aa8b732 1957 goto done;
6aa8b732 1958 break;
b13354f8
MG		 1959 case 0x90: /* nop / xchg r8,rax */
1960 if (!(c->rex_prefix & 1)) { /* nop */
1961 c->dst.type = OP_NONE;
1962 break;
1963 }
1964 case 0x91 ... 0x97: /* xchg reg,rax */
1965 c->src.type = c->dst.type = OP_REG;
1966 c->src.bytes = c->dst.bytes = c->op_bytes;
1967 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1968 c->src.val = *(c->src.ptr);
1969 goto xchg;
fd2a7608 1970 case 0x9c: /* pushf */
05f086f8 1971 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1972 emulate_push(ctxt);
1973 break;
535eabcf 1974 case 0x9d: /* popf */
2b48cc75 1975 c->dst.type = OP_REG;
05f086f8 1976 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1977 c->dst.bytes = c->op_bytes;
535eabcf 1978 goto pop_instruction;
018a98db
AK		 1979 case 0xa0 ... 0xa1: /* mov */
1980 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1981 c->dst.val = c->src.val;
1982 break;
1983 case 0xa2 ... 0xa3: /* mov */
1984 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1985 break;
6aa8b732 1986 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1987 c->dst.type = OP_MEM;
1988 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1989 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1990 es_base(ctxt),
e4e03ded 1991 c->regs[VCPU_REGS_RDI]);
e4706772 1992 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1993 seg_override_base(ctxt, c),
e4e03ded
LV		 1994 c->regs[VCPU_REGS_RSI]),
1995 &c->dst.val,
1996 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1997 goto done;
7a957275 1998 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1999 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2000 : c->dst.bytes);
7a957275 2001 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2002 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2003 : c->dst.bytes);
6aa8b732
AK		 2004 break;
2005 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2006 c->src.type = OP_NONE; /* Disable writeback. */
2007 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2008 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2009 seg_override_base(ctxt, c),
d7e5117a
GT		 2010 c->regs[VCPU_REGS_RSI]);
2011 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
2012 &c->src.val,
2013 c->src.bytes,
2014 ctxt->vcpu)) != 0)
2015 goto done;
2016
2017 c->dst.type = OP_NONE; /* Disable writeback. */
2018 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2019 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2020 es_base(ctxt),
d7e5117a
GT		 2021 c->regs[VCPU_REGS_RDI]);
2022 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
2023 &c->dst.val,
2024 c->dst.bytes,
2025 ctxt->vcpu)) != 0)
2026 goto done;
2027
2028 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2029
2030 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2031
7a957275 2032 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2033 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2034 : c->src.bytes);
7a957275 2035 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2036 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2037 : c->dst.bytes);
2038
2039 break;
6aa8b732 2040 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2041 c->dst.type = OP_MEM;
2042 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2043 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2044 es_base(ctxt),
a7e6c88a 2045 c->regs[VCPU_REGS_RDI]);
e4e03ded 2046 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2047 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2048 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2049 : c->dst.bytes);
6aa8b732
AK		 2050 break;
2051 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2052 c->dst.type = OP_REG;
2053 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2054 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 2055 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 2056 seg_override_base(ctxt, c),
a7e6c88a
SY		 2057 c->regs[VCPU_REGS_RSI]),
2058 &c->dst.val,
2059 c->dst.bytes,
2060 ctxt->vcpu)) != 0)
6aa8b732 2061 goto done;
7a957275 2062 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2063 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2064 : c->dst.bytes);
6aa8b732
AK		 2065 break;
2066 case 0xae ... 0xaf: /* scas */
2067 DPRINTF("Urk! I don't handle SCAS.\n");
2068 goto cannot_emulate;
a5e2e82b 2069 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2070 goto mov;
018a98db
AK		 2071 case 0xc0 ... 0xc1:
2072 emulate_grp2(ctxt);
2073 break;
111de5d6 2074 case 0xc3: /* ret */
cf5de4f8 2075 c->dst.type = OP_REG;
111de5d6 2076 c->dst.ptr = &c->eip;
cf5de4f8 2077 c->dst.bytes = c->op_bytes;
111de5d6 2078 goto pop_instruction;
018a98db
AK		 2079 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2080 mov:
2081 c->dst.val = c->src.val;
2082 break;
a77ab5ea
AK		 2083 case 0xcb: /* ret far */
2084 rc = emulate_ret_far(ctxt, ops);
2085 if (rc)
2086 goto done;
2087 break;
018a98db
AK		 2088 case 0xd0 ... 0xd1: /* Grp2 */
2089 c->src.val = 1;
2090 emulate_grp2(ctxt);
2091 break;
2092 case 0xd2 ... 0xd3: /* Grp2 */
2093 c->src.val = c->regs[VCPU_REGS_RCX];
2094 emulate_grp2(ctxt);
2095 break;
a6a3034c
MG		 2096 case 0xe4: /* inb */
2097 case 0xe5: /* in */
84ce66a6 2098 port = c->src.val;
a6a3034c
MG		 2099 io_dir_in = 1;
2100 goto do_io;
2101 case 0xe6: /* outb */
2102 case 0xe7: /* out */
84ce66a6 2103 port = c->src.val;
a6a3034c
MG		 2104 io_dir_in = 0;
2105 goto do_io;
1a52e051 2106 case 0xe8: /* call (near) */ {
d53c4777 2107 long int rel = c->src.val;
e4e03ded 2108 c->src.val = (unsigned long) c->eip;
7a957275 2109 jmp_rel(c, rel);
8cdbd2c9
LV		 2110 emulate_push(ctxt);
2111 break;
1a52e051
NK		 2112 }
2113 case 0xe9: /* jmp rel */
954cd36f 2114 goto jmp;
782b877c
GN		 2115 case 0xea: /* jmp far */
2116 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2117 VCPU_SREG_CS) < 0) {
954cd36f
GT		 2118 DPRINTF("jmp far: Failed to load CS descriptor\n");
2119 goto cannot_emulate;
2120 }
2121
782b877c 2122 c->eip = c->src.val;
954cd36f 2123 break;
954cd36f
GT		 2124 case 0xeb:
2125 jmp: /* jmp rel short */
7a957275 2126 jmp_rel(c, c->src.val);
a01af5ec 2127 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2128 break;
a6a3034c
MG		 2129 case 0xec: /* in al,dx */
2130 case 0xed: /* in (e/r)ax,dx */
2131 port = c->regs[VCPU_REGS_RDX];
2132 io_dir_in = 1;
2133 goto do_io;
2134 case 0xee: /* out al,dx */
2135 case 0xef: /* out (e/r)ax,dx */
2136 port = c->regs[VCPU_REGS_RDX];
2137 io_dir_in = 0;
851ba692 2138 do_io: if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2139 (c->d & ByteOp) ? 1 : c->op_bytes,
2140 port) != 0) {
2141 c->eip = saved_eip;
2142 goto cannot_emulate;
2143 }
e93f36bc 2144 break;
111de5d6 2145 case 0xf4: /* hlt */
ad312c7c 2146 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2147 break;
111de5d6
AK		 2148 case 0xf5: /* cmc */
2149 /* complement carry flag from eflags reg */
2150 ctxt->eflags ^= EFLG_CF;
2151 c->dst.type = OP_NONE; /* Disable writeback. */
2152 break;
018a98db
AK		 2153 case 0xf6 ... 0xf7: /* Grp3 */
2154 rc = emulate_grp3(ctxt, ops);
2155 if (rc != 0)
2156 goto done;
2157 break;
111de5d6
AK		 2158 case 0xf8: /* clc */
2159 ctxt->eflags &= ~EFLG_CF;
2160 c->dst.type = OP_NONE; /* Disable writeback. */
2161 break;
2162 case 0xfa: /* cli */
2163 ctxt->eflags &= ~X86_EFLAGS_IF;
2164 c->dst.type = OP_NONE; /* Disable writeback. */
2165 break;
2166 case 0xfb: /* sti */
310b5d30 2167 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
111de5d6
AK		 2168 ctxt->eflags |= X86_EFLAGS_IF;
2169 c->dst.type = OP_NONE; /* Disable writeback. */
2170 break;
fb4616f4
MG		 2171 case 0xfc: /* cld */
2172 ctxt->eflags &= ~EFLG_DF;
2173 c->dst.type = OP_NONE; /* Disable writeback. */
2174 break;
2175 case 0xfd: /* std */
2176 ctxt->eflags |= EFLG_DF;
2177 c->dst.type = OP_NONE; /* Disable writeback. */
2178 break;
018a98db
AK		 2179 case 0xfe ... 0xff: /* Grp4/Grp5 */
2180 rc = emulate_grp45(ctxt, ops);
2181 if (rc != 0)
2182 goto done;
2183 break;
6aa8b732 2184 }
018a98db
AK		 2185
2186writeback:
2187 rc = writeback(ctxt, ops);
2188 if (rc != 0)
2189 goto done;
2190
2191 /* Commit shadow register state. */
ad312c7c 2192 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2193 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2194
2195done:
2196 if (rc == X86EMUL_UNHANDLEABLE) {
2197 c->eip = saved_eip;
2198 return -1;
2199 }
2200 return 0;
6aa8b732
AK		 2201
2202twobyte_insn:
e4e03ded 2203 switch (c->b) {
6aa8b732 2204 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2205 switch (c->modrm_reg) {
6aa8b732
AK		 2206 u16 size;
2207 unsigned long address;
2208
aca7f966 2209 case 0: /* vmcall */
e4e03ded 2210 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2211 goto cannot_emulate;
2212
7aa81cc0
AL		 2213 rc = kvm_fix_hypercall(ctxt->vcpu);
2214 if (rc)
2215 goto done;
2216
33e3885d 2217 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2218 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2219 /* Disable writeback. */
2220 c->dst.type = OP_NONE;
aca7f966 2221 break;
6aa8b732 2222 case 2: /* lgdt */
e4e03ded
LV		 2223 rc = read_descriptor(ctxt, ops, c->src.ptr,
2224 &size, &address, c->op_bytes);
6aa8b732
AK		 2225 if (rc)
2226 goto done;
2227 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2228 /* Disable writeback. */
2229 c->dst.type = OP_NONE;
6aa8b732 2230 break;
aca7f966 2231 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2232 if (c->modrm_mod == 3) {
2233 switch (c->modrm_rm) {
2234 case 1:
2235 rc = kvm_fix_hypercall(ctxt->vcpu);
2236 if (rc)
2237 goto done;
2238 break;
2239 default:
2240 goto cannot_emulate;
2241 }
aca7f966 2242 } else {
e4e03ded 2243 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2244 &size, &address,
e4e03ded 2245 c->op_bytes);
aca7f966
AL		 2246 if (rc)
2247 goto done;
2248 realmode_lidt(ctxt->vcpu, size, address);
2249 }
16286d08
AK		 2250 /* Disable writeback. */
2251 c->dst.type = OP_NONE;
6aa8b732
AK		 2252 break;
2253 case 4: /* smsw */
16286d08
AK		 2254 c->dst.bytes = 2;
2255 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2256 break;
2257 case 6: /* lmsw */
16286d08
AK		 2258 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2259 &ctxt->eflags);
dc7457ea 2260 c->dst.type = OP_NONE;
6aa8b732
AK		 2261 break;
2262 case 7: /* invlpg*/
e8d8d7fe 2263 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2264 /* Disable writeback. */
2265 c->dst.type = OP_NONE;
6aa8b732
AK		 2266 break;
2267 default:
2268 goto cannot_emulate;
2269 }
2270 break;
e99f0507 2271 case 0x05: /* syscall */
e66bb2cc
AP		 2272 if (emulate_syscall(ctxt) == -1)
2273 goto cannot_emulate;
2274 else
2275 goto writeback;
e99f0507 2276 break;
018a98db
AK		 2277 case 0x06:
2278 emulate_clts(ctxt->vcpu);
2279 c->dst.type = OP_NONE;
2280 break;
2281 case 0x08: /* invd */
2282 case 0x09: /* wbinvd */
2283 case 0x0d: /* GrpP (prefetch) */
2284 case 0x18: /* Grp16 (prefetch/nop) */
2285 c->dst.type = OP_NONE;
2286 break;
2287 case 0x20: /* mov cr, reg */
2288 if (c->modrm_mod != 3)
2289 goto cannot_emulate;
2290 c->regs[c->modrm_rm] =
2291 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2292 c->dst.type = OP_NONE; /* no writeback */
2293 break;
6aa8b732 2294 case 0x21: /* mov from dr to reg */
e4e03ded 2295 if (c->modrm_mod != 3)
6aa8b732 2296 goto cannot_emulate;
8cdbd2c9 2297 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2298 if (rc)
2299 goto cannot_emulate;
2300 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2301 break;
018a98db
AK		 2302 case 0x22: /* mov reg, cr */
2303 if (c->modrm_mod != 3)
2304 goto cannot_emulate;
2305 realmode_set_cr(ctxt->vcpu,
2306 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2307 c->dst.type = OP_NONE;
2308 break;
6aa8b732 2309 case 0x23: /* mov from reg to dr */
e4e03ded 2310 if (c->modrm_mod != 3)
6aa8b732 2311 goto cannot_emulate;
e4e03ded
LV		 2312 rc = emulator_set_dr(ctxt, c->modrm_reg,
2313 c->regs[c->modrm_rm]);
a01af5ec
LV		 2314 if (rc)
2315 goto cannot_emulate;
2316 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2317 break;
018a98db
AK		 2318 case 0x30:
2319 /* wrmsr */
2320 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2321 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2322 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2323 if (rc) {
c1a5d4f9 2324 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2325 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2326 }
2327 rc = X86EMUL_CONTINUE;
2328 c->dst.type = OP_NONE;
2329 break;
2330 case 0x32:
2331 /* rdmsr */
2332 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2333 if (rc) {
c1a5d4f9 2334 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2335 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2336 } else {
2337 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2338 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2339 }
2340 rc = X86EMUL_CONTINUE;
2341 c->dst.type = OP_NONE;
2342 break;
e99f0507 2343 case 0x34: /* sysenter */
8c604352
AP		 2344 if (emulate_sysenter(ctxt) == -1)
2345 goto cannot_emulate;
2346 else
2347 goto writeback;
e99f0507
AP		 2348 break;
2349 case 0x35: /* sysexit */
4668f050
AP		 2350 if (emulate_sysexit(ctxt) == -1)
2351 goto cannot_emulate;
2352 else
2353 goto writeback;
e99f0507 2354 break;
6aa8b732 2355 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2356 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2357 if (!test_cc(c->b, ctxt->eflags))
2358 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2359 break;
b2833e3c 2360 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2361 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2362 jmp_rel(c, c->src.val);
018a98db
AK		 2363 c->dst.type = OP_NONE;
2364 break;
0934ac9d
MG		 2365 case 0xa0: /* push fs */
2366 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2367 break;
2368 case 0xa1: /* pop fs */
2369 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2370 if (rc != 0)
2371 goto done;
2372 break;
7de75248
NK		 2373 case 0xa3:
2374 bt: /* bt */
e4f8e039 2375 c->dst.type = OP_NONE;
e4e03ded
LV		 2376 /* only subword offset */
2377 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2378 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2379 break;
9bf8ea42
GT		 2380 case 0xa4: /* shld imm8, r, r/m */
2381 case 0xa5: /* shld cl, r, r/m */
2382 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2383 break;
0934ac9d
MG		 2384 case 0xa8: /* push gs */
2385 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2386 break;
2387 case 0xa9: /* pop gs */
2388 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2389 if (rc != 0)
2390 goto done;
2391 break;
7de75248
NK		 2392 case 0xab:
2393 bts: /* bts */
e4e03ded
LV		 2394 /* only subword offset */
2395 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2396 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2397 break;
9bf8ea42
GT		 2398 case 0xac: /* shrd imm8, r, r/m */
2399 case 0xad: /* shrd cl, r, r/m */
2400 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2401 break;
2a7c5b8b
GC		 2402 case 0xae: /* clflush */
2403 break;
6aa8b732
AK		 2404 case 0xb0 ... 0xb1: /* cmpxchg */
2405 /*
2406 * Save real source value, then compare EAX against
2407 * destination.
2408 */
e4e03ded
LV		 2409 c->src.orig_val = c->src.val;
2410 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2411 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2412 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2413 /* Success: write back to memory. */
e4e03ded 2414 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2415 } else {
2416 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2417 c->dst.type = OP_REG;
2418 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2419 }
2420 break;
6aa8b732
AK		 2421 case 0xb3:
2422 btr: /* btr */
e4e03ded
LV		 2423 /* only subword offset */
2424 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2425 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2426 break;
6aa8b732 2427 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2428 c->dst.bytes = c->op_bytes;
2429 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2430 : (u16) c->src.val;
6aa8b732 2431 break;
6aa8b732 2432 case 0xba: /* Grp8 */
e4e03ded 2433 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2434 case 0:
2435 goto bt;
2436 case 1:
2437 goto bts;
2438 case 2:
2439 goto btr;
2440 case 3:
2441 goto btc;
2442 }
2443 break;
7de75248
NK		 2444 case 0xbb:
2445 btc: /* btc */
e4e03ded
LV		 2446 /* only subword offset */
2447 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2448 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2449 break;
6aa8b732 2450 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2451 c->dst.bytes = c->op_bytes;
2452 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2453 (s16) c->src.val;
6aa8b732 2454 break;
a012e65a 2455 case 0xc3: /* movnti */
e4e03ded
LV		 2456 c->dst.bytes = c->op_bytes;
2457 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2458 (u64) c->src.val;
a012e65a 2459 break;
6aa8b732 2460 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2461 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2462 if (rc != 0)
2463 goto done;
018a98db 2464 c->dst.type = OP_NONE;
8cdbd2c9 2465 break;
6aa8b732
AK		 2466 }
2467 goto writeback;
2468
2469cannot_emulate:
e4e03ded 2470 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2471 c->eip = saved_eip;
6aa8b732
AK		 2472 return -1;
2473}
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