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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
b7d491e7 | 27 | #include <linux/stringify.h> |
6aa8b732 | 28 | |
3eeb3288 | 29 | #include "x86.h" |
38ba30ba | 30 | #include "tss.h" |
e99f0507 | 31 | |
a9945549 AK |
32 | /* |
33 | * Operand types | |
34 | */ | |
b1ea50b2 AK |
35 | #define OpNone 0ull |
36 | #define OpImplicit 1ull /* No generic decode */ | |
37 | #define OpReg 2ull /* Register */ | |
38 | #define OpMem 3ull /* Memory */ | |
39 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
40 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
41 | #define OpMem64 6ull /* Memory, 64-bit */ | |
42 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
43 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
44 | #define OpCL 9ull /* CL register (for shifts) */ |
45 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
46 | #define OpOne 11ull /* Implied 1 */ | |
5e2c6883 | 47 | #define OpImm 12ull /* Sign extended up to 32-bit immediate */ |
0fe59128 AK |
48 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
49 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
50 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
51 | #define OpSI 16ull /* SI/ESI/RSI */ | |
52 | #define OpImmFAddr 17ull /* Immediate far address */ | |
53 | #define OpMemFAddr 18ull /* Far address in memory */ | |
54 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
55 | #define OpES 20ull /* ES */ |
56 | #define OpCS 21ull /* CS */ | |
57 | #define OpSS 22ull /* SS */ | |
58 | #define OpDS 23ull /* DS */ | |
59 | #define OpFS 24ull /* FS */ | |
60 | #define OpGS 25ull /* GS */ | |
28867cee | 61 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
5e2c6883 | 62 | #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ |
7fa57952 | 63 | #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ |
820207c8 AK |
64 | #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ |
65 | #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ | |
0fe59128 AK |
66 | |
67 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 68 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 69 | |
6aa8b732 AK |
70 | /* |
71 | * Opcode effective-address decode tables. | |
72 | * Note that we only emulate instructions that have at least one memory | |
73 | * operand (excluding implicit stack references). We assume that stack | |
74 | * references and instruction fetches will never occur in special memory | |
75 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
76 | * not be handled. | |
77 | */ | |
78 | ||
79 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 80 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 81 | /* Destination operand type. */ |
a9945549 AK |
82 | #define DstShift 1 |
83 | #define ImplicitOps (OpImplicit << DstShift) | |
84 | #define DstReg (OpReg << DstShift) | |
85 | #define DstMem (OpMem << DstShift) | |
86 | #define DstAcc (OpAcc << DstShift) | |
87 | #define DstDI (OpDI << DstShift) | |
88 | #define DstMem64 (OpMem64 << DstShift) | |
89 | #define DstImmUByte (OpImmUByte << DstShift) | |
90 | #define DstDX (OpDX << DstShift) | |
820207c8 | 91 | #define DstAccLo (OpAccLo << DstShift) |
a9945549 | 92 | #define DstMask (OpMask << DstShift) |
6aa8b732 | 93 | /* Source operand type. */ |
0fe59128 AK |
94 | #define SrcShift 6 |
95 | #define SrcNone (OpNone << SrcShift) | |
96 | #define SrcReg (OpReg << SrcShift) | |
97 | #define SrcMem (OpMem << SrcShift) | |
98 | #define SrcMem16 (OpMem16 << SrcShift) | |
99 | #define SrcMem32 (OpMem32 << SrcShift) | |
100 | #define SrcImm (OpImm << SrcShift) | |
101 | #define SrcImmByte (OpImmByte << SrcShift) | |
102 | #define SrcOne (OpOne << SrcShift) | |
103 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
104 | #define SrcImmU (OpImmU << SrcShift) | |
105 | #define SrcSI (OpSI << SrcShift) | |
7fa57952 | 106 | #define SrcXLat (OpXLat << SrcShift) |
0fe59128 AK |
107 | #define SrcImmFAddr (OpImmFAddr << SrcShift) |
108 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
109 | #define SrcAcc (OpAcc << SrcShift) | |
110 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
5e2c6883 | 111 | #define SrcImm64 (OpImm64 << SrcShift) |
0fe59128 | 112 | #define SrcDX (OpDX << SrcShift) |
28867cee | 113 | #define SrcMem8 (OpMem8 << SrcShift) |
820207c8 | 114 | #define SrcAccHi (OpAccHi << SrcShift) |
0fe59128 | 115 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
116 | #define BitOp (1<<11) |
117 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
118 | #define String (1<<13) /* String instruction (rep capable) */ | |
119 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
120 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
121 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
122 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
123 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
124 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
045a282c | 125 | #define Escape (5<<15) /* Escape to coprocessor instruction */ |
221192bd | 126 | #define Sse (1<<18) /* SSE Vector instruction */ |
20c29ff2 AK |
127 | /* Generic ModRM decode. */ |
128 | #define ModRM (1<<19) | |
129 | /* Destination is only written; never read. */ | |
130 | #define Mov (1<<20) | |
d8769fed | 131 | /* Misc flags */ |
8ea7d6ae | 132 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 133 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 134 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 135 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 136 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 137 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 138 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 139 | #define No64 (1<<28) |
d5ae7ce8 | 140 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0b789eee | 141 | #define NotImpl (1 << 30) /* instruction is not implemented */ |
0dc8d10f | 142 | /* Source 2 operand type */ |
0b789eee | 143 | #define Src2Shift (31) |
4dd6a57d | 144 | #define Src2None (OpNone << Src2Shift) |
ab2c5ce6 | 145 | #define Src2Mem (OpMem << Src2Shift) |
4dd6a57d AK |
146 | #define Src2CL (OpCL << Src2Shift) |
147 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
148 | #define Src2One (OpOne << Src2Shift) | |
149 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
150 | #define Src2ES (OpES << Src2Shift) |
151 | #define Src2CS (OpCS << Src2Shift) | |
152 | #define Src2SS (OpSS << Src2Shift) | |
153 | #define Src2DS (OpDS << Src2Shift) | |
154 | #define Src2FS (OpFS << Src2Shift) | |
155 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 156 | #define Src2Mask (OpMask << Src2Shift) |
cbe2c9d3 | 157 | #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
1c11b376 AK |
158 | #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
159 | #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ | |
160 | #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ | |
e28bbd44 | 161 | #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ |
b6744dc3 | 162 | #define NoWrite ((u64)1 << 45) /* No writeback */ |
fb32b1ed | 163 | #define SrcWrite ((u64)1 << 46) /* Write back src operand */ |
6aa8b732 | 164 | |
820207c8 | 165 | #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) |
6aa8b732 | 166 | |
d0e53325 AK |
167 | #define X2(x...) x, x |
168 | #define X3(x...) X2(x), x | |
169 | #define X4(x...) X2(x), X2(x) | |
170 | #define X5(x...) X4(x), x | |
171 | #define X6(x...) X4(x), X2(x) | |
172 | #define X7(x...) X4(x), X3(x) | |
173 | #define X8(x...) X4(x), X4(x) | |
174 | #define X16(x...) X8(x), X8(x) | |
83babbca | 175 | |
e28bbd44 AK |
176 | #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) |
177 | #define FASTOP_SIZE 8 | |
178 | ||
179 | /* | |
180 | * fastop functions have a special calling convention: | |
181 | * | |
017da7b6 AK |
182 | * dst: rax (in/out) |
183 | * src: rdx (in/out) | |
e28bbd44 AK |
184 | * src2: rcx (in) |
185 | * flags: rflags (in/out) | |
b8c0b6ae | 186 | * ex: rsi (in:fastop pointer, out:zero if exception) |
e28bbd44 AK |
187 | * |
188 | * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for | |
189 | * different operand sizes can be reached by calculation, rather than a jump | |
190 | * table (which would be bigger than the code). | |
191 | * | |
192 | * fastop functions are declared as taking a never-defined fastop parameter, | |
193 | * so they can't be called from C directly. | |
194 | */ | |
195 | ||
196 | struct fastop; | |
197 | ||
d65b1dee | 198 | struct opcode { |
b1ea50b2 AK |
199 | u64 flags : 56; |
200 | u64 intercept : 8; | |
120df890 | 201 | union { |
ef65c889 | 202 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
fd0a0d82 MK |
203 | const struct opcode *group; |
204 | const struct group_dual *gdual; | |
205 | const struct gprefix *gprefix; | |
045a282c | 206 | const struct escape *esc; |
e28bbd44 | 207 | void (*fastop)(struct fastop *fake); |
120df890 | 208 | } u; |
d09beabd | 209 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
210 | }; |
211 | ||
212 | struct group_dual { | |
213 | struct opcode mod012[8]; | |
214 | struct opcode mod3[8]; | |
d65b1dee AK |
215 | }; |
216 | ||
0d7cdee8 AK |
217 | struct gprefix { |
218 | struct opcode pfx_no; | |
219 | struct opcode pfx_66; | |
220 | struct opcode pfx_f2; | |
221 | struct opcode pfx_f3; | |
222 | }; | |
223 | ||
045a282c GN |
224 | struct escape { |
225 | struct opcode op[8]; | |
226 | struct opcode high[64]; | |
227 | }; | |
228 | ||
6aa8b732 | 229 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
230 | #define EFLG_ID (1<<21) |
231 | #define EFLG_VIP (1<<20) | |
232 | #define EFLG_VIF (1<<19) | |
233 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
234 | #define EFLG_VM (1<<17) |
235 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
236 | #define EFLG_IOPL (3<<12) |
237 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
238 | #define EFLG_OF (1<<11) |
239 | #define EFLG_DF (1<<10) | |
b1d86143 | 240 | #define EFLG_IF (1<<9) |
d4c6a154 | 241 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
242 | #define EFLG_SF (1<<7) |
243 | #define EFLG_ZF (1<<6) | |
244 | #define EFLG_AF (1<<4) | |
245 | #define EFLG_PF (1<<2) | |
246 | #define EFLG_CF (1<<0) | |
247 | ||
62bd430e MG |
248 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
249 | #define EFLG_RESERVED_ONE_MASK 2 | |
250 | ||
dd856efa AK |
251 | static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) |
252 | { | |
253 | if (!(ctxt->regs_valid & (1 << nr))) { | |
254 | ctxt->regs_valid |= 1 << nr; | |
255 | ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); | |
256 | } | |
257 | return ctxt->_regs[nr]; | |
258 | } | |
259 | ||
260 | static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
261 | { | |
262 | ctxt->regs_valid |= 1 << nr; | |
263 | ctxt->regs_dirty |= 1 << nr; | |
264 | return &ctxt->_regs[nr]; | |
265 | } | |
266 | ||
267 | static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
268 | { | |
269 | reg_read(ctxt, nr); | |
270 | return reg_write(ctxt, nr); | |
271 | } | |
272 | ||
273 | static void writeback_registers(struct x86_emulate_ctxt *ctxt) | |
274 | { | |
275 | unsigned reg; | |
276 | ||
277 | for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) | |
278 | ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); | |
279 | } | |
280 | ||
281 | static void invalidate_registers(struct x86_emulate_ctxt *ctxt) | |
282 | { | |
283 | ctxt->regs_dirty = 0; | |
284 | ctxt->regs_valid = 0; | |
285 | } | |
286 | ||
6aa8b732 AK |
287 | /* |
288 | * These EFLAGS bits are restored from saved value during emulation, and | |
289 | * any changes are written back to the saved value after emulation. | |
290 | */ | |
291 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
292 | ||
dda96d8f AK |
293 | #ifdef CONFIG_X86_64 |
294 | #define ON64(x) x | |
295 | #else | |
296 | #define ON64(x) | |
297 | #endif | |
298 | ||
4d758349 AK |
299 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); |
300 | ||
b7d491e7 AK |
301 | #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" |
302 | #define FOP_RET "ret \n\t" | |
303 | ||
304 | #define FOP_START(op) \ | |
305 | extern void em_##op(struct fastop *fake); \ | |
306 | asm(".pushsection .text, \"ax\" \n\t" \ | |
307 | ".global em_" #op " \n\t" \ | |
308 | FOP_ALIGN \ | |
309 | "em_" #op ": \n\t" | |
310 | ||
311 | #define FOP_END \ | |
312 | ".popsection") | |
313 | ||
0bdea068 AK |
314 | #define FOPNOP() FOP_ALIGN FOP_RET |
315 | ||
b7d491e7 | 316 | #define FOP1E(op, dst) \ |
b8c0b6ae AK |
317 | FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET |
318 | ||
319 | #define FOP1EEX(op, dst) \ | |
320 | FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) | |
b7d491e7 AK |
321 | |
322 | #define FASTOP1(op) \ | |
323 | FOP_START(op) \ | |
324 | FOP1E(op##b, al) \ | |
325 | FOP1E(op##w, ax) \ | |
326 | FOP1E(op##l, eax) \ | |
327 | ON64(FOP1E(op##q, rax)) \ | |
328 | FOP_END | |
329 | ||
b9fa409b AK |
330 | /* 1-operand, using src2 (for MUL/DIV r/m) */ |
331 | #define FASTOP1SRC2(op, name) \ | |
332 | FOP_START(name) \ | |
333 | FOP1E(op, cl) \ | |
334 | FOP1E(op, cx) \ | |
335 | FOP1E(op, ecx) \ | |
336 | ON64(FOP1E(op, rcx)) \ | |
337 | FOP_END | |
338 | ||
b8c0b6ae AK |
339 | /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ |
340 | #define FASTOP1SRC2EX(op, name) \ | |
341 | FOP_START(name) \ | |
342 | FOP1EEX(op, cl) \ | |
343 | FOP1EEX(op, cx) \ | |
344 | FOP1EEX(op, ecx) \ | |
345 | ON64(FOP1EEX(op, rcx)) \ | |
346 | FOP_END | |
347 | ||
f7857f35 AK |
348 | #define FOP2E(op, dst, src) \ |
349 | FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET | |
350 | ||
351 | #define FASTOP2(op) \ | |
352 | FOP_START(op) \ | |
017da7b6 AK |
353 | FOP2E(op##b, al, dl) \ |
354 | FOP2E(op##w, ax, dx) \ | |
355 | FOP2E(op##l, eax, edx) \ | |
356 | ON64(FOP2E(op##q, rax, rdx)) \ | |
f7857f35 AK |
357 | FOP_END |
358 | ||
11c363ba AK |
359 | /* 2 operand, word only */ |
360 | #define FASTOP2W(op) \ | |
361 | FOP_START(op) \ | |
362 | FOPNOP() \ | |
017da7b6 AK |
363 | FOP2E(op##w, ax, dx) \ |
364 | FOP2E(op##l, eax, edx) \ | |
365 | ON64(FOP2E(op##q, rax, rdx)) \ | |
11c363ba AK |
366 | FOP_END |
367 | ||
007a3b54 AK |
368 | /* 2 operand, src is CL */ |
369 | #define FASTOP2CL(op) \ | |
370 | FOP_START(op) \ | |
371 | FOP2E(op##b, al, cl) \ | |
372 | FOP2E(op##w, ax, cl) \ | |
373 | FOP2E(op##l, eax, cl) \ | |
374 | ON64(FOP2E(op##q, rax, cl)) \ | |
375 | FOP_END | |
376 | ||
0bdea068 AK |
377 | #define FOP3E(op, dst, src, src2) \ |
378 | FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET | |
379 | ||
380 | /* 3-operand, word-only, src2=cl */ | |
381 | #define FASTOP3WCL(op) \ | |
382 | FOP_START(op) \ | |
383 | FOPNOP() \ | |
017da7b6 AK |
384 | FOP3E(op##w, ax, dx, cl) \ |
385 | FOP3E(op##l, eax, edx, cl) \ | |
386 | ON64(FOP3E(op##q, rax, rdx, cl)) \ | |
0bdea068 AK |
387 | FOP_END |
388 | ||
9ae9feba AK |
389 | /* Special case for SETcc - 1 instruction per cc */ |
390 | #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" | |
391 | ||
b8c0b6ae AK |
392 | asm(".global kvm_fastop_exception \n" |
393 | "kvm_fastop_exception: xor %esi, %esi; ret"); | |
394 | ||
9ae9feba AK |
395 | FOP_START(setcc) |
396 | FOP_SETCC(seto) | |
397 | FOP_SETCC(setno) | |
398 | FOP_SETCC(setc) | |
399 | FOP_SETCC(setnc) | |
400 | FOP_SETCC(setz) | |
401 | FOP_SETCC(setnz) | |
402 | FOP_SETCC(setbe) | |
403 | FOP_SETCC(setnbe) | |
404 | FOP_SETCC(sets) | |
405 | FOP_SETCC(setns) | |
406 | FOP_SETCC(setp) | |
407 | FOP_SETCC(setnp) | |
408 | FOP_SETCC(setl) | |
409 | FOP_SETCC(setnl) | |
410 | FOP_SETCC(setle) | |
411 | FOP_SETCC(setnle) | |
412 | FOP_END; | |
413 | ||
326f578f PB |
414 | FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET |
415 | FOP_END; | |
416 | ||
8a76d7f2 JR |
417 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
418 | enum x86_intercept intercept, | |
419 | enum x86_intercept_stage stage) | |
420 | { | |
421 | struct x86_instruction_info info = { | |
422 | .intercept = intercept, | |
9dac77fa AK |
423 | .rep_prefix = ctxt->rep_prefix, |
424 | .modrm_mod = ctxt->modrm_mod, | |
425 | .modrm_reg = ctxt->modrm_reg, | |
426 | .modrm_rm = ctxt->modrm_rm, | |
427 | .src_val = ctxt->src.val64, | |
428 | .src_bytes = ctxt->src.bytes, | |
429 | .dst_bytes = ctxt->dst.bytes, | |
430 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
431 | .next_rip = ctxt->eip, |
432 | }; | |
433 | ||
2953538e | 434 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
435 | } |
436 | ||
f47cfa31 AK |
437 | static void assign_masked(ulong *dest, ulong src, ulong mask) |
438 | { | |
439 | *dest = (*dest & ~mask) | (src & mask); | |
440 | } | |
441 | ||
9dac77fa | 442 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 443 | { |
9dac77fa | 444 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
445 | } |
446 | ||
f47cfa31 AK |
447 | static ulong stack_mask(struct x86_emulate_ctxt *ctxt) |
448 | { | |
449 | u16 sel; | |
450 | struct desc_struct ss; | |
451 | ||
452 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
453 | return ~0UL; | |
454 | ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); | |
455 | return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ | |
456 | } | |
457 | ||
612e89f0 AK |
458 | static int stack_size(struct x86_emulate_ctxt *ctxt) |
459 | { | |
460 | return (__fls(stack_mask(ctxt)) + 1) >> 3; | |
461 | } | |
462 | ||
6aa8b732 | 463 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 464 | static inline unsigned long |
9dac77fa | 465 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 466 | { |
9dac77fa | 467 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
468 | return reg; |
469 | else | |
9dac77fa | 470 | return reg & ad_mask(ctxt); |
e4706772 HH |
471 | } |
472 | ||
473 | static inline unsigned long | |
9dac77fa | 474 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 475 | { |
9dac77fa | 476 | return address_mask(ctxt, reg); |
e4706772 HH |
477 | } |
478 | ||
5ad105e5 AK |
479 | static void masked_increment(ulong *reg, ulong mask, int inc) |
480 | { | |
481 | assign_masked(reg, *reg + inc, mask); | |
482 | } | |
483 | ||
7a957275 | 484 | static inline void |
9dac77fa | 485 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 486 | { |
5ad105e5 AK |
487 | ulong mask; |
488 | ||
9dac77fa | 489 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
5ad105e5 | 490 | mask = ~0UL; |
7a957275 | 491 | else |
5ad105e5 AK |
492 | mask = ad_mask(ctxt); |
493 | masked_increment(reg, mask, inc); | |
494 | } | |
495 | ||
496 | static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) | |
497 | { | |
dd856efa | 498 | masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); |
7a957275 | 499 | } |
6aa8b732 | 500 | |
9dac77fa | 501 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 502 | { |
9dac77fa | 503 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 504 | } |
098c937b | 505 | |
56697687 AK |
506 | static u32 desc_limit_scaled(struct desc_struct *desc) |
507 | { | |
508 | u32 limit = get_desc_limit(desc); | |
509 | ||
510 | return desc->g ? (limit << 12) | 0xfff : limit; | |
511 | } | |
512 | ||
9dac77fa | 513 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 514 | { |
9dac77fa AK |
515 | ctxt->has_seg_override = true; |
516 | ctxt->seg_override = seg; | |
7a5b56df AK |
517 | } |
518 | ||
7b105ca2 | 519 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
520 | { |
521 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
522 | return 0; | |
523 | ||
7b105ca2 | 524 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
525 | } |
526 | ||
9dac77fa | 527 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 528 | { |
9dac77fa | 529 | if (!ctxt->has_seg_override) |
7a5b56df AK |
530 | return 0; |
531 | ||
9dac77fa | 532 | return ctxt->seg_override; |
7a5b56df AK |
533 | } |
534 | ||
35d3d4a1 AK |
535 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
536 | u32 error, bool valid) | |
54b8486f | 537 | { |
da9cb575 AK |
538 | ctxt->exception.vector = vec; |
539 | ctxt->exception.error_code = error; | |
540 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 541 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
542 | } |
543 | ||
3b88e41a JR |
544 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
545 | { | |
546 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
547 | } | |
548 | ||
35d3d4a1 | 549 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 550 | { |
35d3d4a1 | 551 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
552 | } |
553 | ||
618ff15d AK |
554 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
555 | { | |
556 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
557 | } | |
558 | ||
35d3d4a1 | 559 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 560 | { |
35d3d4a1 | 561 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
562 | } |
563 | ||
35d3d4a1 | 564 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 565 | { |
35d3d4a1 | 566 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
567 | } |
568 | ||
34d1f490 AK |
569 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
570 | { | |
35d3d4a1 | 571 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
572 | } |
573 | ||
1253791d AK |
574 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
575 | { | |
576 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
577 | } | |
578 | ||
1aa36616 AK |
579 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
580 | { | |
581 | u16 selector; | |
582 | struct desc_struct desc; | |
583 | ||
584 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
585 | return selector; | |
586 | } | |
587 | ||
588 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
589 | unsigned seg) | |
590 | { | |
591 | u16 dummy; | |
592 | u32 base3; | |
593 | struct desc_struct desc; | |
594 | ||
595 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
596 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
597 | } | |
598 | ||
1c11b376 AK |
599 | /* |
600 | * x86 defines three classes of vector instructions: explicitly | |
601 | * aligned, explicitly unaligned, and the rest, which change behaviour | |
602 | * depending on whether they're AVX encoded or not. | |
603 | * | |
604 | * Also included is CMPXCHG16B which is not a vector instruction, yet it is | |
605 | * subject to the same check. | |
606 | */ | |
607 | static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) | |
608 | { | |
609 | if (likely(size < 16)) | |
610 | return false; | |
611 | ||
612 | if (ctxt->d & Aligned) | |
613 | return true; | |
614 | else if (ctxt->d & Unaligned) | |
615 | return false; | |
616 | else if (ctxt->d & Avx) | |
617 | return false; | |
618 | else | |
619 | return true; | |
620 | } | |
621 | ||
3d9b938e | 622 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 623 | struct segmented_address addr, |
3d9b938e | 624 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
625 | ulong *linear) |
626 | { | |
618ff15d AK |
627 | struct desc_struct desc; |
628 | bool usable; | |
52fd8b44 | 629 | ulong la; |
618ff15d | 630 | u32 lim; |
1aa36616 | 631 | u16 sel; |
3a78a4f4 | 632 | unsigned cpl; |
52fd8b44 | 633 | |
7b105ca2 | 634 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d | 635 | switch (ctxt->mode) { |
618ff15d AK |
636 | case X86EMUL_MODE_PROT64: |
637 | if (((signed long)la << 16) >> 16 != la) | |
638 | return emulate_gp(ctxt, 0); | |
639 | break; | |
640 | default: | |
1aa36616 AK |
641 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
642 | addr.seg); | |
618ff15d AK |
643 | if (!usable) |
644 | goto bad; | |
58b7825b GN |
645 | /* code segment in protected mode or read-only data segment */ |
646 | if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) | |
647 | || !(desc.type & 2)) && write) | |
618ff15d AK |
648 | goto bad; |
649 | /* unreadable code segment */ | |
3d9b938e | 650 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
651 | goto bad; |
652 | lim = desc_limit_scaled(&desc); | |
653 | if ((desc.type & 8) || !(desc.type & 4)) { | |
654 | /* expand-up segment */ | |
655 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
656 | goto bad; | |
657 | } else { | |
fc058680 | 658 | /* expand-down segment */ |
618ff15d AK |
659 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) |
660 | goto bad; | |
661 | lim = desc.d ? 0xffffffff : 0xffff; | |
662 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
663 | goto bad; | |
664 | } | |
717746e3 | 665 | cpl = ctxt->ops->cpl(ctxt); |
618ff15d AK |
666 | if (!(desc.type & 8)) { |
667 | /* data segment */ | |
668 | if (cpl > desc.dpl) | |
669 | goto bad; | |
670 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
671 | /* nonconforming code segment */ | |
672 | if (cpl != desc.dpl) | |
673 | goto bad; | |
674 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
675 | /* conforming code segment */ | |
676 | if (cpl < desc.dpl) | |
677 | goto bad; | |
678 | } | |
679 | break; | |
680 | } | |
9dac77fa | 681 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 | 682 | la &= (u32)-1; |
1c11b376 AK |
683 | if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
684 | return emulate_gp(ctxt, 0); | |
52fd8b44 AK |
685 | *linear = la; |
686 | return X86EMUL_CONTINUE; | |
618ff15d AK |
687 | bad: |
688 | if (addr.seg == VCPU_SREG_SS) | |
0afbe2f8 | 689 | return emulate_ss(ctxt, sel); |
618ff15d | 690 | else |
0afbe2f8 | 691 | return emulate_gp(ctxt, sel); |
52fd8b44 AK |
692 | } |
693 | ||
3d9b938e NE |
694 | static int linearize(struct x86_emulate_ctxt *ctxt, |
695 | struct segmented_address addr, | |
696 | unsigned size, bool write, | |
697 | ulong *linear) | |
698 | { | |
699 | return __linearize(ctxt, addr, size, write, false, linear); | |
700 | } | |
701 | ||
702 | ||
3ca3ac4d AK |
703 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
704 | struct segmented_address addr, | |
705 | void *data, | |
706 | unsigned size) | |
707 | { | |
9fa088f4 AK |
708 | int rc; |
709 | ulong linear; | |
710 | ||
83b8795a | 711 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
712 | if (rc != X86EMUL_CONTINUE) |
713 | return rc; | |
0f65dd70 | 714 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
715 | } |
716 | ||
807941b1 TY |
717 | /* |
718 | * Fetch the next byte of the instruction being emulated which is pointed to | |
719 | * by ctxt->_eip, then increment ctxt->_eip. | |
720 | * | |
721 | * Also prefetch the remaining bytes of the instruction without crossing page | |
722 | * boundary if they are not in fetch_cache yet. | |
723 | */ | |
724 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 725 | { |
9dac77fa | 726 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 727 | int rc; |
2fb53ad8 | 728 | int size, cur_size; |
62266869 | 729 | |
807941b1 | 730 | if (ctxt->_eip == fc->end) { |
3d9b938e | 731 | unsigned long linear; |
807941b1 TY |
732 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
733 | .ea = ctxt->_eip }; | |
2fb53ad8 | 734 | cur_size = fc->end - fc->start; |
807941b1 TY |
735 | size = min(15UL - cur_size, |
736 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 737 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 738 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 739 | return rc; |
ef5d75cc TY |
740 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
741 | size, &ctxt->exception); | |
7d88bb48 | 742 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 743 | return rc; |
2fb53ad8 | 744 | fc->end += size; |
62266869 | 745 | } |
807941b1 TY |
746 | *dest = fc->data[ctxt->_eip - fc->start]; |
747 | ctxt->_eip++; | |
3e2815e9 | 748 | return X86EMUL_CONTINUE; |
62266869 AK |
749 | } |
750 | ||
751 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 752 | void *dest, unsigned size) |
62266869 | 753 | { |
3e2815e9 | 754 | int rc; |
62266869 | 755 | |
eb3c79e6 | 756 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 757 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 758 | return X86EMUL_UNHANDLEABLE; |
62266869 | 759 | while (size--) { |
807941b1 | 760 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 761 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
762 | return rc; |
763 | } | |
3e2815e9 | 764 | return X86EMUL_CONTINUE; |
62266869 AK |
765 | } |
766 | ||
67cbc90d | 767 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 768 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 769 | ({ unsigned long _x; \ |
e85a1085 | 770 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
771 | if (rc != X86EMUL_CONTINUE) \ |
772 | goto done; \ | |
67cbc90d TY |
773 | (_type)_x; \ |
774 | }) | |
775 | ||
807941b1 TY |
776 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
777 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
778 | if (rc != X86EMUL_CONTINUE) \ |
779 | goto done; \ | |
67cbc90d TY |
780 | }) |
781 | ||
1e3c5cb0 RR |
782 | /* |
783 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
784 | * pointer into the block that addresses the relevant register. | |
785 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
786 | */ | |
dd856efa | 787 | static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, |
1e3c5cb0 | 788 | int highbyte_regs) |
6aa8b732 AK |
789 | { |
790 | void *p; | |
791 | ||
6aa8b732 | 792 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
dd856efa AK |
793 | p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; |
794 | else | |
795 | p = reg_rmw(ctxt, modrm_reg); | |
6aa8b732 AK |
796 | return p; |
797 | } | |
798 | ||
799 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 800 | struct segmented_address addr, |
6aa8b732 AK |
801 | u16 *size, unsigned long *address, int op_bytes) |
802 | { | |
803 | int rc; | |
804 | ||
805 | if (op_bytes == 2) | |
806 | op_bytes = 3; | |
807 | *address = 0; | |
3ca3ac4d | 808 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 809 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 810 | return rc; |
30b31ab6 | 811 | addr.ea += 2; |
3ca3ac4d | 812 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
813 | return rc; |
814 | } | |
815 | ||
34b77652 AK |
816 | FASTOP2(add); |
817 | FASTOP2(or); | |
818 | FASTOP2(adc); | |
819 | FASTOP2(sbb); | |
820 | FASTOP2(and); | |
821 | FASTOP2(sub); | |
822 | FASTOP2(xor); | |
823 | FASTOP2(cmp); | |
824 | FASTOP2(test); | |
825 | ||
b9fa409b AK |
826 | FASTOP1SRC2(mul, mul_ex); |
827 | FASTOP1SRC2(imul, imul_ex); | |
b8c0b6ae AK |
828 | FASTOP1SRC2EX(div, div_ex); |
829 | FASTOP1SRC2EX(idiv, idiv_ex); | |
b9fa409b | 830 | |
34b77652 AK |
831 | FASTOP3WCL(shld); |
832 | FASTOP3WCL(shrd); | |
833 | ||
834 | FASTOP2W(imul); | |
835 | ||
836 | FASTOP1(not); | |
837 | FASTOP1(neg); | |
838 | FASTOP1(inc); | |
839 | FASTOP1(dec); | |
840 | ||
841 | FASTOP2CL(rol); | |
842 | FASTOP2CL(ror); | |
843 | FASTOP2CL(rcl); | |
844 | FASTOP2CL(rcr); | |
845 | FASTOP2CL(shl); | |
846 | FASTOP2CL(shr); | |
847 | FASTOP2CL(sar); | |
848 | ||
849 | FASTOP2W(bsf); | |
850 | FASTOP2W(bsr); | |
851 | FASTOP2W(bt); | |
852 | FASTOP2W(bts); | |
853 | FASTOP2W(btr); | |
854 | FASTOP2W(btc); | |
855 | ||
e47a5f5f AK |
856 | FASTOP2(xadd); |
857 | ||
9ae9feba | 858 | static u8 test_cc(unsigned int condition, unsigned long flags) |
bbe9abbd | 859 | { |
9ae9feba AK |
860 | u8 rc; |
861 | void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); | |
bbe9abbd | 862 | |
9ae9feba | 863 | flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; |
3f0c3d0b | 864 | asm("push %[flags]; popf; call *%[fastop]" |
9ae9feba AK |
865 | : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); |
866 | return rc; | |
bbe9abbd NK |
867 | } |
868 | ||
91ff3cb4 AK |
869 | static void fetch_register_operand(struct operand *op) |
870 | { | |
871 | switch (op->bytes) { | |
872 | case 1: | |
873 | op->val = *(u8 *)op->addr.reg; | |
874 | break; | |
875 | case 2: | |
876 | op->val = *(u16 *)op->addr.reg; | |
877 | break; | |
878 | case 4: | |
879 | op->val = *(u32 *)op->addr.reg; | |
880 | break; | |
881 | case 8: | |
882 | op->val = *(u64 *)op->addr.reg; | |
883 | break; | |
884 | } | |
885 | } | |
886 | ||
1253791d AK |
887 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
888 | { | |
889 | ctxt->ops->get_fpu(ctxt); | |
890 | switch (reg) { | |
89a87c67 MK |
891 | case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; |
892 | case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; | |
893 | case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; | |
894 | case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; | |
895 | case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; | |
896 | case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; | |
897 | case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; | |
898 | case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; | |
1253791d | 899 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
900 | case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; |
901 | case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; | |
902 | case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; | |
903 | case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; | |
904 | case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; | |
905 | case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; | |
906 | case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; | |
907 | case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; | |
1253791d AK |
908 | #endif |
909 | default: BUG(); | |
910 | } | |
911 | ctxt->ops->put_fpu(ctxt); | |
912 | } | |
913 | ||
914 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
915 | int reg) | |
916 | { | |
917 | ctxt->ops->get_fpu(ctxt); | |
918 | switch (reg) { | |
89a87c67 MK |
919 | case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; |
920 | case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; | |
921 | case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; | |
922 | case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; | |
923 | case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; | |
924 | case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; | |
925 | case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; | |
926 | case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; | |
1253791d | 927 | #ifdef CONFIG_X86_64 |
89a87c67 MK |
928 | case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; |
929 | case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; | |
930 | case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; | |
931 | case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; | |
932 | case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; | |
933 | case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; | |
934 | case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; | |
935 | case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; | |
1253791d AK |
936 | #endif |
937 | default: BUG(); | |
938 | } | |
939 | ctxt->ops->put_fpu(ctxt); | |
940 | } | |
941 | ||
cbe2c9d3 AK |
942 | static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
943 | { | |
944 | ctxt->ops->get_fpu(ctxt); | |
945 | switch (reg) { | |
946 | case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; | |
947 | case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; | |
948 | case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; | |
949 | case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; | |
950 | case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; | |
951 | case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; | |
952 | case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; | |
953 | case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; | |
954 | default: BUG(); | |
955 | } | |
956 | ctxt->ops->put_fpu(ctxt); | |
957 | } | |
958 | ||
959 | static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) | |
960 | { | |
961 | ctxt->ops->get_fpu(ctxt); | |
962 | switch (reg) { | |
963 | case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; | |
964 | case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; | |
965 | case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; | |
966 | case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; | |
967 | case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; | |
968 | case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; | |
969 | case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; | |
970 | case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; | |
971 | default: BUG(); | |
972 | } | |
973 | ctxt->ops->put_fpu(ctxt); | |
974 | } | |
975 | ||
045a282c GN |
976 | static int em_fninit(struct x86_emulate_ctxt *ctxt) |
977 | { | |
978 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
979 | return emulate_nm(ctxt); | |
980 | ||
981 | ctxt->ops->get_fpu(ctxt); | |
982 | asm volatile("fninit"); | |
983 | ctxt->ops->put_fpu(ctxt); | |
984 | return X86EMUL_CONTINUE; | |
985 | } | |
986 | ||
987 | static int em_fnstcw(struct x86_emulate_ctxt *ctxt) | |
988 | { | |
989 | u16 fcw; | |
990 | ||
991 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
992 | return emulate_nm(ctxt); | |
993 | ||
994 | ctxt->ops->get_fpu(ctxt); | |
995 | asm volatile("fnstcw %0": "+m"(fcw)); | |
996 | ctxt->ops->put_fpu(ctxt); | |
997 | ||
998 | /* force 2 byte destination */ | |
999 | ctxt->dst.bytes = 2; | |
1000 | ctxt->dst.val = fcw; | |
1001 | ||
1002 | return X86EMUL_CONTINUE; | |
1003 | } | |
1004 | ||
1005 | static int em_fnstsw(struct x86_emulate_ctxt *ctxt) | |
1006 | { | |
1007 | u16 fsw; | |
1008 | ||
1009 | if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) | |
1010 | return emulate_nm(ctxt); | |
1011 | ||
1012 | ctxt->ops->get_fpu(ctxt); | |
1013 | asm volatile("fnstsw %0": "+m"(fsw)); | |
1014 | ctxt->ops->put_fpu(ctxt); | |
1015 | ||
1016 | /* force 2 byte destination */ | |
1017 | ctxt->dst.bytes = 2; | |
1018 | ctxt->dst.val = fsw; | |
1019 | ||
1020 | return X86EMUL_CONTINUE; | |
1021 | } | |
1022 | ||
1253791d | 1023 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, |
2adb5ad9 | 1024 | struct operand *op) |
3c118e24 | 1025 | { |
9dac77fa AK |
1026 | unsigned reg = ctxt->modrm_reg; |
1027 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 1028 | |
9dac77fa AK |
1029 | if (!(ctxt->d & ModRM)) |
1030 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 1031 | |
9dac77fa | 1032 | if (ctxt->d & Sse) { |
1253791d AK |
1033 | op->type = OP_XMM; |
1034 | op->bytes = 16; | |
1035 | op->addr.xmm = reg; | |
1036 | read_sse_reg(ctxt, &op->vec_val, reg); | |
1037 | return; | |
1038 | } | |
cbe2c9d3 AK |
1039 | if (ctxt->d & Mmx) { |
1040 | reg &= 7; | |
1041 | op->type = OP_MM; | |
1042 | op->bytes = 8; | |
1043 | op->addr.mm = reg; | |
1044 | return; | |
1045 | } | |
1253791d | 1046 | |
3c118e24 | 1047 | op->type = OP_REG; |
2adb5ad9 | 1048 | if (ctxt->d & ByteOp) { |
dd856efa | 1049 | op->addr.reg = decode_register(ctxt, reg, highbyte_regs); |
3c118e24 AK |
1050 | op->bytes = 1; |
1051 | } else { | |
dd856efa | 1052 | op->addr.reg = decode_register(ctxt, reg, 0); |
9dac77fa | 1053 | op->bytes = ctxt->op_bytes; |
3c118e24 | 1054 | } |
91ff3cb4 | 1055 | fetch_register_operand(op); |
3c118e24 AK |
1056 | op->orig_val = op->val; |
1057 | } | |
1058 | ||
a6e3407b AK |
1059 | static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) |
1060 | { | |
1061 | if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) | |
1062 | ctxt->modrm_seg = VCPU_SREG_SS; | |
1063 | } | |
1064 | ||
1c73ef66 | 1065 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 1066 | struct operand *op) |
1c73ef66 | 1067 | { |
1c73ef66 | 1068 | u8 sib; |
f5b4edcd | 1069 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 1070 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 1071 | ulong modrm_ea = 0; |
1c73ef66 | 1072 | |
9dac77fa AK |
1073 | if (ctxt->rex_prefix) { |
1074 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
1075 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
1076 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
1077 | } |
1078 | ||
9dac77fa AK |
1079 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
1080 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
1081 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
1082 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 1083 | |
9dac77fa | 1084 | if (ctxt->modrm_mod == 3) { |
8acb4207 PB |
1085 | int highbyte_regs = ctxt->rex_prefix == 0; |
1086 | ||
2dbd0dd7 | 1087 | op->type = OP_REG; |
9dac77fa | 1088 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
8acb4207 PB |
1089 | op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, |
1090 | highbyte_regs && (ctxt->d & ByteOp)); | |
9dac77fa | 1091 | if (ctxt->d & Sse) { |
1253791d AK |
1092 | op->type = OP_XMM; |
1093 | op->bytes = 16; | |
9dac77fa AK |
1094 | op->addr.xmm = ctxt->modrm_rm; |
1095 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
1096 | return rc; |
1097 | } | |
cbe2c9d3 AK |
1098 | if (ctxt->d & Mmx) { |
1099 | op->type = OP_MM; | |
1100 | op->bytes = 8; | |
1101 | op->addr.xmm = ctxt->modrm_rm & 7; | |
1102 | return rc; | |
1103 | } | |
2dbd0dd7 | 1104 | fetch_register_operand(op); |
1c73ef66 AK |
1105 | return rc; |
1106 | } | |
1107 | ||
2dbd0dd7 AK |
1108 | op->type = OP_MEM; |
1109 | ||
9dac77fa | 1110 | if (ctxt->ad_bytes == 2) { |
dd856efa AK |
1111 | unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); |
1112 | unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); | |
1113 | unsigned si = reg_read(ctxt, VCPU_REGS_RSI); | |
1114 | unsigned di = reg_read(ctxt, VCPU_REGS_RDI); | |
1c73ef66 AK |
1115 | |
1116 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 1117 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1118 | case 0: |
9dac77fa | 1119 | if (ctxt->modrm_rm == 6) |
e85a1085 | 1120 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1121 | break; |
1122 | case 1: | |
e85a1085 | 1123 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1124 | break; |
1125 | case 2: | |
e85a1085 | 1126 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1127 | break; |
1128 | } | |
9dac77fa | 1129 | switch (ctxt->modrm_rm) { |
1c73ef66 | 1130 | case 0: |
2dbd0dd7 | 1131 | modrm_ea += bx + si; |
1c73ef66 AK |
1132 | break; |
1133 | case 1: | |
2dbd0dd7 | 1134 | modrm_ea += bx + di; |
1c73ef66 AK |
1135 | break; |
1136 | case 2: | |
2dbd0dd7 | 1137 | modrm_ea += bp + si; |
1c73ef66 AK |
1138 | break; |
1139 | case 3: | |
2dbd0dd7 | 1140 | modrm_ea += bp + di; |
1c73ef66 AK |
1141 | break; |
1142 | case 4: | |
2dbd0dd7 | 1143 | modrm_ea += si; |
1c73ef66 AK |
1144 | break; |
1145 | case 5: | |
2dbd0dd7 | 1146 | modrm_ea += di; |
1c73ef66 AK |
1147 | break; |
1148 | case 6: | |
9dac77fa | 1149 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 1150 | modrm_ea += bp; |
1c73ef66 AK |
1151 | break; |
1152 | case 7: | |
2dbd0dd7 | 1153 | modrm_ea += bx; |
1c73ef66 AK |
1154 | break; |
1155 | } | |
9dac77fa AK |
1156 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
1157 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
1158 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 1159 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
1160 | } else { |
1161 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 1162 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 1163 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
1164 | index_reg |= (sib >> 3) & 7; |
1165 | base_reg |= sib & 7; | |
1166 | scale = sib >> 6; | |
1167 | ||
9dac77fa | 1168 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 1169 | modrm_ea += insn_fetch(s32, ctxt); |
a6e3407b | 1170 | else { |
dd856efa | 1171 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1172 | adjust_modrm_seg(ctxt, base_reg); |
1173 | } | |
dc71d0f1 | 1174 | if (index_reg != 4) |
dd856efa | 1175 | modrm_ea += reg_read(ctxt, index_reg) << scale; |
9dac77fa | 1176 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { |
84411d85 | 1177 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 1178 | ctxt->rip_relative = 1; |
a6e3407b AK |
1179 | } else { |
1180 | base_reg = ctxt->modrm_rm; | |
dd856efa | 1181 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1182 | adjust_modrm_seg(ctxt, base_reg); |
1183 | } | |
9dac77fa | 1184 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1185 | case 0: |
9dac77fa | 1186 | if (ctxt->modrm_rm == 5) |
e85a1085 | 1187 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1188 | break; |
1189 | case 1: | |
e85a1085 | 1190 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1191 | break; |
1192 | case 2: | |
e85a1085 | 1193 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1194 | break; |
1195 | } | |
1196 | } | |
90de84f5 | 1197 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
1198 | done: |
1199 | return rc; | |
1200 | } | |
1201 | ||
1202 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1203 | struct operand *op) |
1c73ef66 | 1204 | { |
3e2815e9 | 1205 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1206 | |
2dbd0dd7 | 1207 | op->type = OP_MEM; |
9dac77fa | 1208 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1209 | case 2: |
e85a1085 | 1210 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1211 | break; |
1212 | case 4: | |
e85a1085 | 1213 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1214 | break; |
1215 | case 8: | |
e85a1085 | 1216 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1217 | break; |
1218 | } | |
1219 | done: | |
1220 | return rc; | |
1221 | } | |
1222 | ||
9dac77fa | 1223 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1224 | { |
7129eeca | 1225 | long sv = 0, mask; |
35c843c4 | 1226 | |
9dac77fa AK |
1227 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1228 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1229 | |
9dac77fa AK |
1230 | if (ctxt->src.bytes == 2) |
1231 | sv = (s16)ctxt->src.val & (s16)mask; | |
1232 | else if (ctxt->src.bytes == 4) | |
1233 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1234 | |
9dac77fa | 1235 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1236 | } |
ba7ff2b7 WY |
1237 | |
1238 | /* only subword offset */ | |
9dac77fa | 1239 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1240 | } |
1241 | ||
dde7e6d1 | 1242 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1243 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1244 | { |
dde7e6d1 | 1245 | int rc; |
9dac77fa | 1246 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1247 | |
f23b070e XG |
1248 | if (mc->pos < mc->end) |
1249 | goto read_cached; | |
6aa8b732 | 1250 | |
f23b070e XG |
1251 | WARN_ON((mc->end + size) >= sizeof(mc->data)); |
1252 | ||
1253 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, | |
1254 | &ctxt->exception); | |
1255 | if (rc != X86EMUL_CONTINUE) | |
1256 | return rc; | |
1257 | ||
1258 | mc->end += size; | |
1259 | ||
1260 | read_cached: | |
1261 | memcpy(dest, mc->data + mc->pos, size); | |
1262 | mc->pos += size; | |
dde7e6d1 AK |
1263 | return X86EMUL_CONTINUE; |
1264 | } | |
6aa8b732 | 1265 | |
3ca3ac4d AK |
1266 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1267 | struct segmented_address addr, | |
1268 | void *data, | |
1269 | unsigned size) | |
1270 | { | |
9fa088f4 AK |
1271 | int rc; |
1272 | ulong linear; | |
1273 | ||
83b8795a | 1274 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1275 | if (rc != X86EMUL_CONTINUE) |
1276 | return rc; | |
7b105ca2 | 1277 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1278 | } |
1279 | ||
1280 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1281 | struct segmented_address addr, | |
1282 | const void *data, | |
1283 | unsigned size) | |
1284 | { | |
9fa088f4 AK |
1285 | int rc; |
1286 | ulong linear; | |
1287 | ||
83b8795a | 1288 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1289 | if (rc != X86EMUL_CONTINUE) |
1290 | return rc; | |
0f65dd70 AK |
1291 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1292 | &ctxt->exception); | |
3ca3ac4d AK |
1293 | } |
1294 | ||
1295 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1296 | struct segmented_address addr, | |
1297 | const void *orig_data, const void *data, | |
1298 | unsigned size) | |
1299 | { | |
9fa088f4 AK |
1300 | int rc; |
1301 | ulong linear; | |
1302 | ||
83b8795a | 1303 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1304 | if (rc != X86EMUL_CONTINUE) |
1305 | return rc; | |
0f65dd70 AK |
1306 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1307 | size, &ctxt->exception); | |
3ca3ac4d AK |
1308 | } |
1309 | ||
dde7e6d1 | 1310 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1311 | unsigned int size, unsigned short port, |
1312 | void *dest) | |
1313 | { | |
9dac77fa | 1314 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1315 | |
dde7e6d1 | 1316 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1317 | unsigned int in_page, n; |
9dac77fa | 1318 | unsigned int count = ctxt->rep_prefix ? |
dd856efa | 1319 | address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; |
dde7e6d1 | 1320 | in_page = (ctxt->eflags & EFLG_DF) ? |
dd856efa AK |
1321 | offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : |
1322 | PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); | |
dde7e6d1 AK |
1323 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1324 | count); | |
1325 | if (n == 0) | |
1326 | n = 1; | |
1327 | rc->pos = rc->end = 0; | |
7b105ca2 | 1328 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1329 | return 0; |
1330 | rc->end = n * size; | |
6aa8b732 AK |
1331 | } |
1332 | ||
b3356bf0 GN |
1333 | if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) { |
1334 | ctxt->dst.data = rc->data + rc->pos; | |
1335 | ctxt->dst.type = OP_MEM_STR; | |
1336 | ctxt->dst.count = (rc->end - rc->pos) / size; | |
1337 | rc->pos = rc->end; | |
1338 | } else { | |
1339 | memcpy(dest, rc->data + rc->pos, size); | |
1340 | rc->pos += size; | |
1341 | } | |
dde7e6d1 AK |
1342 | return 1; |
1343 | } | |
6aa8b732 | 1344 | |
7f3d35fd KW |
1345 | static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
1346 | u16 index, struct desc_struct *desc) | |
1347 | { | |
1348 | struct desc_ptr dt; | |
1349 | ulong addr; | |
1350 | ||
1351 | ctxt->ops->get_idt(ctxt, &dt); | |
1352 | ||
1353 | if (dt.size < index * 8 + 7) | |
1354 | return emulate_gp(ctxt, index << 3 | 0x2); | |
1355 | ||
1356 | addr = dt.address + index * 8; | |
1357 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1358 | &ctxt->exception); | |
1359 | } | |
1360 | ||
dde7e6d1 | 1361 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1362 | u16 selector, struct desc_ptr *dt) |
1363 | { | |
0225fb50 | 1364 | const struct x86_emulate_ops *ops = ctxt->ops; |
7b105ca2 | 1365 | |
dde7e6d1 AK |
1366 | if (selector & 1 << 2) { |
1367 | struct desc_struct desc; | |
1aa36616 AK |
1368 | u16 sel; |
1369 | ||
dde7e6d1 | 1370 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1371 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1372 | return; |
e09d082c | 1373 | |
dde7e6d1 AK |
1374 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1375 | dt->address = get_desc_base(&desc); | |
1376 | } else | |
4bff1e86 | 1377 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1378 | } |
120df890 | 1379 | |
dde7e6d1 AK |
1380 | /* allowed just for 8 bytes segments */ |
1381 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
e919464b AK |
1382 | u16 selector, struct desc_struct *desc, |
1383 | ulong *desc_addr_p) | |
dde7e6d1 AK |
1384 | { |
1385 | struct desc_ptr dt; | |
1386 | u16 index = selector >> 3; | |
dde7e6d1 | 1387 | ulong addr; |
120df890 | 1388 | |
7b105ca2 | 1389 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1390 | |
35d3d4a1 AK |
1391 | if (dt.size < index * 8 + 7) |
1392 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1393 | |
e919464b | 1394 | *desc_addr_p = addr = dt.address + index * 8; |
7b105ca2 TY |
1395 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, |
1396 | &ctxt->exception); | |
dde7e6d1 | 1397 | } |
ef65c889 | 1398 | |
dde7e6d1 AK |
1399 | /* allowed just for 8 bytes segments */ |
1400 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1401 | u16 selector, struct desc_struct *desc) |
1402 | { | |
1403 | struct desc_ptr dt; | |
1404 | u16 index = selector >> 3; | |
dde7e6d1 | 1405 | ulong addr; |
6aa8b732 | 1406 | |
7b105ca2 | 1407 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1408 | |
35d3d4a1 AK |
1409 | if (dt.size < index * 8 + 7) |
1410 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1411 | |
dde7e6d1 | 1412 | addr = dt.address + index * 8; |
7b105ca2 TY |
1413 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1414 | &ctxt->exception); | |
dde7e6d1 | 1415 | } |
c7e75a3d | 1416 | |
5601d05b | 1417 | /* Does not support long mode */ |
dde7e6d1 | 1418 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1419 | u16 selector, int seg) |
1420 | { | |
869be99c | 1421 | struct desc_struct seg_desc, old_desc; |
dde7e6d1 AK |
1422 | u8 dpl, rpl, cpl; |
1423 | unsigned err_vec = GP_VECTOR; | |
1424 | u32 err_code = 0; | |
1425 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
e919464b | 1426 | ulong desc_addr; |
dde7e6d1 | 1427 | int ret; |
03ebebeb | 1428 | u16 dummy; |
69f55cb1 | 1429 | |
dde7e6d1 | 1430 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1431 | |
f8da94e9 KW |
1432 | if (ctxt->mode == X86EMUL_MODE_REAL) { |
1433 | /* set real mode segment descriptor (keep limit etc. for | |
1434 | * unreal mode) */ | |
03ebebeb | 1435 | ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); |
dde7e6d1 | 1436 | set_desc_base(&seg_desc, selector << 4); |
dde7e6d1 | 1437 | goto load; |
f8da94e9 KW |
1438 | } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { |
1439 | /* VM86 needs a clean new segment descriptor */ | |
1440 | set_desc_base(&seg_desc, selector << 4); | |
1441 | set_desc_limit(&seg_desc, 0xffff); | |
1442 | seg_desc.type = 3; | |
1443 | seg_desc.p = 1; | |
1444 | seg_desc.s = 1; | |
1445 | seg_desc.dpl = 3; | |
1446 | goto load; | |
dde7e6d1 AK |
1447 | } |
1448 | ||
79d5b4c3 AK |
1449 | rpl = selector & 3; |
1450 | cpl = ctxt->ops->cpl(ctxt); | |
1451 | ||
1452 | /* NULL selector is not valid for TR, CS and SS (except for long mode) */ | |
1453 | if ((seg == VCPU_SREG_CS | |
1454 | || (seg == VCPU_SREG_SS | |
1455 | && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) | |
1456 | || seg == VCPU_SREG_TR) | |
dde7e6d1 AK |
1457 | && null_selector) |
1458 | goto exception; | |
1459 | ||
1460 | /* TR should be in GDT only */ | |
1461 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1462 | goto exception; | |
1463 | ||
1464 | if (null_selector) /* for NULL selector skip all following checks */ | |
1465 | goto load; | |
1466 | ||
e919464b | 1467 | ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); |
dde7e6d1 AK |
1468 | if (ret != X86EMUL_CONTINUE) |
1469 | return ret; | |
1470 | ||
1471 | err_code = selector & 0xfffc; | |
1472 | err_vec = GP_VECTOR; | |
1473 | ||
fc058680 | 1474 | /* can't load system descriptor into segment selector */ |
dde7e6d1 AK |
1475 | if (seg <= VCPU_SREG_GS && !seg_desc.s) |
1476 | goto exception; | |
1477 | ||
1478 | if (!seg_desc.p) { | |
1479 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1480 | goto exception; | |
1481 | } | |
1482 | ||
dde7e6d1 | 1483 | dpl = seg_desc.dpl; |
dde7e6d1 AK |
1484 | |
1485 | switch (seg) { | |
1486 | case VCPU_SREG_SS: | |
1487 | /* | |
1488 | * segment is not a writable data segment or segment | |
1489 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1490 | */ | |
1491 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1492 | goto exception; | |
6aa8b732 | 1493 | break; |
dde7e6d1 AK |
1494 | case VCPU_SREG_CS: |
1495 | if (!(seg_desc.type & 8)) | |
1496 | goto exception; | |
1497 | ||
1498 | if (seg_desc.type & 4) { | |
1499 | /* conforming */ | |
1500 | if (dpl > cpl) | |
1501 | goto exception; | |
1502 | } else { | |
1503 | /* nonconforming */ | |
1504 | if (rpl > cpl || dpl != cpl) | |
1505 | goto exception; | |
1506 | } | |
1507 | /* CS(RPL) <- CPL */ | |
1508 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1509 | break; |
dde7e6d1 AK |
1510 | case VCPU_SREG_TR: |
1511 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1512 | goto exception; | |
869be99c AK |
1513 | old_desc = seg_desc; |
1514 | seg_desc.type |= 2; /* busy */ | |
1515 | ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, | |
1516 | sizeof(seg_desc), &ctxt->exception); | |
1517 | if (ret != X86EMUL_CONTINUE) | |
1518 | return ret; | |
dde7e6d1 AK |
1519 | break; |
1520 | case VCPU_SREG_LDTR: | |
1521 | if (seg_desc.s || seg_desc.type != 2) | |
1522 | goto exception; | |
1523 | break; | |
1524 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1525 | /* |
dde7e6d1 AK |
1526 | * segment is not a data or readable code segment or |
1527 | * ((segment is a data or nonconforming code segment) | |
1528 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1529 | */ |
dde7e6d1 AK |
1530 | if ((seg_desc.type & 0xa) == 0x8 || |
1531 | (((seg_desc.type & 0xc) != 0xc) && | |
1532 | (rpl > dpl && cpl > dpl))) | |
1533 | goto exception; | |
6aa8b732 | 1534 | break; |
dde7e6d1 AK |
1535 | } |
1536 | ||
1537 | if (seg_desc.s) { | |
1538 | /* mark segment as accessed */ | |
1539 | seg_desc.type |= 1; | |
7b105ca2 | 1540 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1541 | if (ret != X86EMUL_CONTINUE) |
1542 | return ret; | |
1543 | } | |
1544 | load: | |
7b105ca2 | 1545 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1546 | return X86EMUL_CONTINUE; |
1547 | exception: | |
1548 | emulate_exception(ctxt, err_vec, err_code, true); | |
1549 | return X86EMUL_PROPAGATE_FAULT; | |
1550 | } | |
1551 | ||
31be40b3 WY |
1552 | static void write_register_operand(struct operand *op) |
1553 | { | |
1554 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1555 | switch (op->bytes) { | |
1556 | case 1: | |
1557 | *(u8 *)op->addr.reg = (u8)op->val; | |
1558 | break; | |
1559 | case 2: | |
1560 | *(u16 *)op->addr.reg = (u16)op->val; | |
1561 | break; | |
1562 | case 4: | |
1563 | *op->addr.reg = (u32)op->val; | |
1564 | break; /* 64b: zero-extend */ | |
1565 | case 8: | |
1566 | *op->addr.reg = op->val; | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | ||
fb32b1ed | 1571 | static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) |
dde7e6d1 AK |
1572 | { |
1573 | int rc; | |
dde7e6d1 | 1574 | |
fb32b1ed | 1575 | switch (op->type) { |
dde7e6d1 | 1576 | case OP_REG: |
fb32b1ed | 1577 | write_register_operand(op); |
6aa8b732 | 1578 | break; |
dde7e6d1 | 1579 | case OP_MEM: |
9dac77fa | 1580 | if (ctxt->lock_prefix) |
3ca3ac4d | 1581 | rc = segmented_cmpxchg(ctxt, |
fb32b1ed AK |
1582 | op->addr.mem, |
1583 | &op->orig_val, | |
1584 | &op->val, | |
1585 | op->bytes); | |
341de7e3 | 1586 | else |
3ca3ac4d | 1587 | rc = segmented_write(ctxt, |
fb32b1ed AK |
1588 | op->addr.mem, |
1589 | &op->val, | |
1590 | op->bytes); | |
dde7e6d1 AK |
1591 | if (rc != X86EMUL_CONTINUE) |
1592 | return rc; | |
a682e354 | 1593 | break; |
b3356bf0 GN |
1594 | case OP_MEM_STR: |
1595 | rc = segmented_write(ctxt, | |
fb32b1ed AK |
1596 | op->addr.mem, |
1597 | op->data, | |
1598 | op->bytes * op->count); | |
b3356bf0 GN |
1599 | if (rc != X86EMUL_CONTINUE) |
1600 | return rc; | |
1601 | break; | |
1253791d | 1602 | case OP_XMM: |
fb32b1ed | 1603 | write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); |
1253791d | 1604 | break; |
cbe2c9d3 | 1605 | case OP_MM: |
fb32b1ed | 1606 | write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); |
cbe2c9d3 | 1607 | break; |
dde7e6d1 AK |
1608 | case OP_NONE: |
1609 | /* no writeback */ | |
414e6277 | 1610 | break; |
dde7e6d1 | 1611 | default: |
414e6277 | 1612 | break; |
6aa8b732 | 1613 | } |
dde7e6d1 AK |
1614 | return X86EMUL_CONTINUE; |
1615 | } | |
6aa8b732 | 1616 | |
51ddff50 | 1617 | static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) |
dde7e6d1 | 1618 | { |
4179bb02 | 1619 | struct segmented_address addr; |
0dc8d10f | 1620 | |
5ad105e5 | 1621 | rsp_increment(ctxt, -bytes); |
dd856efa | 1622 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
4179bb02 TY |
1623 | addr.seg = VCPU_SREG_SS; |
1624 | ||
51ddff50 AK |
1625 | return segmented_write(ctxt, addr, data, bytes); |
1626 | } | |
1627 | ||
1628 | static int em_push(struct x86_emulate_ctxt *ctxt) | |
1629 | { | |
4179bb02 | 1630 | /* Disable writeback. */ |
9dac77fa | 1631 | ctxt->dst.type = OP_NONE; |
51ddff50 | 1632 | return push(ctxt, &ctxt->src.val, ctxt->op_bytes); |
dde7e6d1 | 1633 | } |
69f55cb1 | 1634 | |
dde7e6d1 | 1635 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1636 | void *dest, int len) |
1637 | { | |
dde7e6d1 | 1638 | int rc; |
90de84f5 | 1639 | struct segmented_address addr; |
8b4caf66 | 1640 | |
dd856efa | 1641 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
90de84f5 | 1642 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1643 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1644 | if (rc != X86EMUL_CONTINUE) |
1645 | return rc; | |
1646 | ||
5ad105e5 | 1647 | rsp_increment(ctxt, len); |
dde7e6d1 | 1648 | return rc; |
8b4caf66 LV |
1649 | } |
1650 | ||
c54fe504 TY |
1651 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1652 | { | |
9dac77fa | 1653 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1654 | } |
1655 | ||
dde7e6d1 | 1656 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1657 | void *dest, int len) |
9de41573 GN |
1658 | { |
1659 | int rc; | |
dde7e6d1 AK |
1660 | unsigned long val, change_mask; |
1661 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1662 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1663 | |
3b9be3bf | 1664 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1665 | if (rc != X86EMUL_CONTINUE) |
1666 | return rc; | |
9de41573 | 1667 | |
dde7e6d1 AK |
1668 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1669 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1670 | |
dde7e6d1 AK |
1671 | switch(ctxt->mode) { |
1672 | case X86EMUL_MODE_PROT64: | |
1673 | case X86EMUL_MODE_PROT32: | |
1674 | case X86EMUL_MODE_PROT16: | |
1675 | if (cpl == 0) | |
1676 | change_mask |= EFLG_IOPL; | |
1677 | if (cpl <= iopl) | |
1678 | change_mask |= EFLG_IF; | |
1679 | break; | |
1680 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1681 | if (iopl < 3) |
1682 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1683 | change_mask |= EFLG_IF; |
1684 | break; | |
1685 | default: /* real mode */ | |
1686 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1687 | break; | |
9de41573 | 1688 | } |
dde7e6d1 AK |
1689 | |
1690 | *(unsigned long *)dest = | |
1691 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1692 | ||
1693 | return rc; | |
9de41573 GN |
1694 | } |
1695 | ||
62aaa2f0 TY |
1696 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1697 | { | |
9dac77fa AK |
1698 | ctxt->dst.type = OP_REG; |
1699 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1700 | ctxt->dst.bytes = ctxt->op_bytes; | |
1701 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1702 | } |
1703 | ||
612e89f0 AK |
1704 | static int em_enter(struct x86_emulate_ctxt *ctxt) |
1705 | { | |
1706 | int rc; | |
1707 | unsigned frame_size = ctxt->src.val; | |
1708 | unsigned nesting_level = ctxt->src2.val & 31; | |
dd856efa | 1709 | ulong rbp; |
612e89f0 AK |
1710 | |
1711 | if (nesting_level) | |
1712 | return X86EMUL_UNHANDLEABLE; | |
1713 | ||
dd856efa AK |
1714 | rbp = reg_read(ctxt, VCPU_REGS_RBP); |
1715 | rc = push(ctxt, &rbp, stack_size(ctxt)); | |
612e89f0 AK |
1716 | if (rc != X86EMUL_CONTINUE) |
1717 | return rc; | |
dd856efa | 1718 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), |
612e89f0 | 1719 | stack_mask(ctxt)); |
dd856efa AK |
1720 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), |
1721 | reg_read(ctxt, VCPU_REGS_RSP) - frame_size, | |
612e89f0 AK |
1722 | stack_mask(ctxt)); |
1723 | return X86EMUL_CONTINUE; | |
1724 | } | |
1725 | ||
f47cfa31 AK |
1726 | static int em_leave(struct x86_emulate_ctxt *ctxt) |
1727 | { | |
dd856efa | 1728 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), |
f47cfa31 | 1729 | stack_mask(ctxt)); |
dd856efa | 1730 | return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); |
f47cfa31 AK |
1731 | } |
1732 | ||
1cd196ea | 1733 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1734 | { |
1cd196ea AK |
1735 | int seg = ctxt->src2.val; |
1736 | ||
9dac77fa | 1737 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1738 | |
4487b3b4 | 1739 | return em_push(ctxt); |
7b262e90 GN |
1740 | } |
1741 | ||
1cd196ea | 1742 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1743 | { |
1cd196ea | 1744 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1745 | unsigned long selector; |
1746 | int rc; | |
38ba30ba | 1747 | |
9dac77fa | 1748 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1749 | if (rc != X86EMUL_CONTINUE) |
1750 | return rc; | |
1751 | ||
7b105ca2 | 1752 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1753 | return rc; |
38ba30ba GN |
1754 | } |
1755 | ||
b96a7fad | 1756 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1757 | { |
dd856efa | 1758 | unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); |
dde7e6d1 AK |
1759 | int rc = X86EMUL_CONTINUE; |
1760 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1761 | |
dde7e6d1 AK |
1762 | while (reg <= VCPU_REGS_RDI) { |
1763 | (reg == VCPU_REGS_RSP) ? | |
dd856efa | 1764 | (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); |
38ba30ba | 1765 | |
4487b3b4 | 1766 | rc = em_push(ctxt); |
dde7e6d1 AK |
1767 | if (rc != X86EMUL_CONTINUE) |
1768 | return rc; | |
38ba30ba | 1769 | |
dde7e6d1 | 1770 | ++reg; |
38ba30ba | 1771 | } |
38ba30ba | 1772 | |
dde7e6d1 | 1773 | return rc; |
38ba30ba GN |
1774 | } |
1775 | ||
62aaa2f0 TY |
1776 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1777 | { | |
9dac77fa | 1778 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1779 | return em_push(ctxt); |
1780 | } | |
1781 | ||
b96a7fad | 1782 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1783 | { |
dde7e6d1 AK |
1784 | int rc = X86EMUL_CONTINUE; |
1785 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1786 | |
dde7e6d1 AK |
1787 | while (reg >= VCPU_REGS_RAX) { |
1788 | if (reg == VCPU_REGS_RSP) { | |
5ad105e5 | 1789 | rsp_increment(ctxt, ctxt->op_bytes); |
dde7e6d1 AK |
1790 | --reg; |
1791 | } | |
38ba30ba | 1792 | |
dd856efa | 1793 | rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); |
dde7e6d1 AK |
1794 | if (rc != X86EMUL_CONTINUE) |
1795 | break; | |
1796 | --reg; | |
38ba30ba | 1797 | } |
dde7e6d1 | 1798 | return rc; |
38ba30ba GN |
1799 | } |
1800 | ||
dd856efa | 1801 | static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1802 | { |
0225fb50 | 1803 | const struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1804 | int rc; |
6e154e56 MG |
1805 | struct desc_ptr dt; |
1806 | gva_t cs_addr; | |
1807 | gva_t eip_addr; | |
1808 | u16 cs, eip; | |
6e154e56 MG |
1809 | |
1810 | /* TODO: Add limit checks */ | |
9dac77fa | 1811 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1812 | rc = em_push(ctxt); |
5c56e1cf AK |
1813 | if (rc != X86EMUL_CONTINUE) |
1814 | return rc; | |
6e154e56 MG |
1815 | |
1816 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1817 | ||
9dac77fa | 1818 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1819 | rc = em_push(ctxt); |
5c56e1cf AK |
1820 | if (rc != X86EMUL_CONTINUE) |
1821 | return rc; | |
6e154e56 | 1822 | |
9dac77fa | 1823 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1824 | rc = em_push(ctxt); |
5c56e1cf AK |
1825 | if (rc != X86EMUL_CONTINUE) |
1826 | return rc; | |
1827 | ||
4bff1e86 | 1828 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1829 | |
1830 | eip_addr = dt.address + (irq << 2); | |
1831 | cs_addr = dt.address + (irq << 2) + 2; | |
1832 | ||
0f65dd70 | 1833 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1834 | if (rc != X86EMUL_CONTINUE) |
1835 | return rc; | |
1836 | ||
0f65dd70 | 1837 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1838 | if (rc != X86EMUL_CONTINUE) |
1839 | return rc; | |
1840 | ||
7b105ca2 | 1841 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1842 | if (rc != X86EMUL_CONTINUE) |
1843 | return rc; | |
1844 | ||
9dac77fa | 1845 | ctxt->_eip = eip; |
6e154e56 MG |
1846 | |
1847 | return rc; | |
1848 | } | |
1849 | ||
dd856efa AK |
1850 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
1851 | { | |
1852 | int rc; | |
1853 | ||
1854 | invalidate_registers(ctxt); | |
1855 | rc = __emulate_int_real(ctxt, irq); | |
1856 | if (rc == X86EMUL_CONTINUE) | |
1857 | writeback_registers(ctxt); | |
1858 | return rc; | |
1859 | } | |
1860 | ||
7b105ca2 | 1861 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
1862 | { |
1863 | switch(ctxt->mode) { | |
1864 | case X86EMUL_MODE_REAL: | |
dd856efa | 1865 | return __emulate_int_real(ctxt, irq); |
6e154e56 MG |
1866 | case X86EMUL_MODE_VM86: |
1867 | case X86EMUL_MODE_PROT16: | |
1868 | case X86EMUL_MODE_PROT32: | |
1869 | case X86EMUL_MODE_PROT64: | |
1870 | default: | |
1871 | /* Protected mode interrupts unimplemented yet */ | |
1872 | return X86EMUL_UNHANDLEABLE; | |
1873 | } | |
1874 | } | |
1875 | ||
7b105ca2 | 1876 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1877 | { |
dde7e6d1 AK |
1878 | int rc = X86EMUL_CONTINUE; |
1879 | unsigned long temp_eip = 0; | |
1880 | unsigned long temp_eflags = 0; | |
1881 | unsigned long cs = 0; | |
1882 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1883 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1884 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1885 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1886 | |
dde7e6d1 | 1887 | /* TODO: Add stack limit check */ |
38ba30ba | 1888 | |
9dac77fa | 1889 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 1890 | |
dde7e6d1 AK |
1891 | if (rc != X86EMUL_CONTINUE) |
1892 | return rc; | |
38ba30ba | 1893 | |
35d3d4a1 AK |
1894 | if (temp_eip & ~0xffff) |
1895 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1896 | |
9dac77fa | 1897 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 1898 | |
dde7e6d1 AK |
1899 | if (rc != X86EMUL_CONTINUE) |
1900 | return rc; | |
38ba30ba | 1901 | |
9dac77fa | 1902 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 1903 | |
dde7e6d1 AK |
1904 | if (rc != X86EMUL_CONTINUE) |
1905 | return rc; | |
38ba30ba | 1906 | |
7b105ca2 | 1907 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1908 | |
dde7e6d1 AK |
1909 | if (rc != X86EMUL_CONTINUE) |
1910 | return rc; | |
38ba30ba | 1911 | |
9dac77fa | 1912 | ctxt->_eip = temp_eip; |
38ba30ba | 1913 | |
38ba30ba | 1914 | |
9dac77fa | 1915 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 1916 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 1917 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
1918 | ctxt->eflags &= ~0xffff; |
1919 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1920 | } |
dde7e6d1 AK |
1921 | |
1922 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1923 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1924 | ||
1925 | return rc; | |
38ba30ba GN |
1926 | } |
1927 | ||
e01991e7 | 1928 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 1929 | { |
dde7e6d1 AK |
1930 | switch(ctxt->mode) { |
1931 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1932 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
1933 | case X86EMUL_MODE_VM86: |
1934 | case X86EMUL_MODE_PROT16: | |
1935 | case X86EMUL_MODE_PROT32: | |
1936 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1937 | default: |
dde7e6d1 AK |
1938 | /* iret from protected mode unimplemented yet */ |
1939 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1940 | } |
c37eda13 WY |
1941 | } |
1942 | ||
d2f62766 TY |
1943 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
1944 | { | |
d2f62766 TY |
1945 | int rc; |
1946 | unsigned short sel; | |
1947 | ||
9dac77fa | 1948 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 1949 | |
7b105ca2 | 1950 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
1951 | if (rc != X86EMUL_CONTINUE) |
1952 | return rc; | |
1953 | ||
9dac77fa AK |
1954 | ctxt->_eip = 0; |
1955 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
1956 | return X86EMUL_CONTINUE; |
1957 | } | |
1958 | ||
51187683 | 1959 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1960 | { |
4179bb02 | 1961 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 1962 | |
9dac77fa | 1963 | switch (ctxt->modrm_reg) { |
d19292e4 MG |
1964 | case 2: /* call near abs */ { |
1965 | long int old_eip; | |
9dac77fa AK |
1966 | old_eip = ctxt->_eip; |
1967 | ctxt->_eip = ctxt->src.val; | |
1968 | ctxt->src.val = old_eip; | |
4487b3b4 | 1969 | rc = em_push(ctxt); |
d19292e4 MG |
1970 | break; |
1971 | } | |
8cdbd2c9 | 1972 | case 4: /* jmp abs */ |
9dac77fa | 1973 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 1974 | break; |
d2f62766 TY |
1975 | case 5: /* jmp far */ |
1976 | rc = em_jmp_far(ctxt); | |
1977 | break; | |
8cdbd2c9 | 1978 | case 6: /* push */ |
4487b3b4 | 1979 | rc = em_push(ctxt); |
8cdbd2c9 | 1980 | break; |
8cdbd2c9 | 1981 | } |
4179bb02 | 1982 | return rc; |
8cdbd2c9 LV |
1983 | } |
1984 | ||
e0dac408 | 1985 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1986 | { |
9dac77fa | 1987 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 1988 | |
dd856efa AK |
1989 | if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || |
1990 | ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { | |
1991 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); | |
1992 | *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); | |
05f086f8 | 1993 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 1994 | } else { |
dd856efa AK |
1995 | ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | |
1996 | (u32) reg_read(ctxt, VCPU_REGS_RBX); | |
8cdbd2c9 | 1997 | |
05f086f8 | 1998 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 1999 | } |
1b30eaa8 | 2000 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
2001 | } |
2002 | ||
ebda02c2 TY |
2003 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
2004 | { | |
9dac77fa AK |
2005 | ctxt->dst.type = OP_REG; |
2006 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2007 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
2008 | return em_pop(ctxt); |
2009 | } | |
2010 | ||
e01991e7 | 2011 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 2012 | { |
a77ab5ea AK |
2013 | int rc; |
2014 | unsigned long cs; | |
2015 | ||
9dac77fa | 2016 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 2017 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2018 | return rc; |
9dac77fa AK |
2019 | if (ctxt->op_bytes == 4) |
2020 | ctxt->_eip = (u32)ctxt->_eip; | |
2021 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 2022 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2023 | return rc; |
7b105ca2 | 2024 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
2025 | return rc; |
2026 | } | |
2027 | ||
3261107e BR |
2028 | static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) |
2029 | { | |
2030 | int rc; | |
2031 | ||
2032 | rc = em_ret_far(ctxt); | |
2033 | if (rc != X86EMUL_CONTINUE) | |
2034 | return rc; | |
2035 | rsp_increment(ctxt, ctxt->src.val); | |
2036 | return X86EMUL_CONTINUE; | |
2037 | } | |
2038 | ||
e940b5c2 TY |
2039 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
2040 | { | |
2041 | /* Save real source value, then compare EAX against destination. */ | |
2042 | ctxt->src.orig_val = ctxt->src.val; | |
dd856efa | 2043 | ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX); |
158de57f | 2044 | fastop(ctxt, em_cmp); |
e940b5c2 TY |
2045 | |
2046 | if (ctxt->eflags & EFLG_ZF) { | |
2047 | /* Success: write back to memory. */ | |
2048 | ctxt->dst.val = ctxt->src.orig_val; | |
2049 | } else { | |
2050 | /* Failure: write the value we saw to EAX. */ | |
2051 | ctxt->dst.type = OP_REG; | |
dd856efa | 2052 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
e940b5c2 TY |
2053 | } |
2054 | return X86EMUL_CONTINUE; | |
2055 | } | |
2056 | ||
d4b4325f | 2057 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 2058 | { |
d4b4325f | 2059 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
2060 | unsigned short sel; |
2061 | int rc; | |
2062 | ||
9dac77fa | 2063 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 2064 | |
7b105ca2 | 2065 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
2066 | if (rc != X86EMUL_CONTINUE) |
2067 | return rc; | |
2068 | ||
9dac77fa | 2069 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
2070 | return rc; |
2071 | } | |
2072 | ||
7b105ca2 | 2073 | static void |
e66bb2cc | 2074 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 2075 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 2076 | { |
e66bb2cc | 2077 | cs->l = 0; /* will be adjusted later */ |
79168fd1 | 2078 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 2079 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 2080 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
2081 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
2082 | cs->s = 1; | |
2083 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
2084 | cs->p = 1; |
2085 | cs->d = 1; | |
99245b50 | 2086 | cs->avl = 0; |
e66bb2cc | 2087 | |
79168fd1 GN |
2088 | set_desc_base(ss, 0); /* flat segment */ |
2089 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
2090 | ss->g = 1; /* 4kb granularity */ |
2091 | ss->s = 1; | |
2092 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 2093 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 2094 | ss->dpl = 0; |
79168fd1 | 2095 | ss->p = 1; |
99245b50 GN |
2096 | ss->l = 0; |
2097 | ss->avl = 0; | |
e66bb2cc AP |
2098 | } |
2099 | ||
1a18a69b AK |
2100 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
2101 | { | |
2102 | u32 eax, ebx, ecx, edx; | |
2103 | ||
2104 | eax = ecx = 0; | |
0017f93a AK |
2105 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2106 | return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1a18a69b AK |
2107 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx |
2108 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
2109 | } | |
2110 | ||
c2226fc9 SB |
2111 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
2112 | { | |
0225fb50 | 2113 | const struct x86_emulate_ops *ops = ctxt->ops; |
c2226fc9 SB |
2114 | u32 eax, ebx, ecx, edx; |
2115 | ||
2116 | /* | |
2117 | * syscall should always be enabled in longmode - so only become | |
2118 | * vendor specific (cpuid) if other modes are active... | |
2119 | */ | |
2120 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2121 | return true; | |
2122 | ||
2123 | eax = 0x00000000; | |
2124 | ecx = 0x00000000; | |
0017f93a AK |
2125 | ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2126 | /* | |
2127 | * Intel ("GenuineIntel") | |
2128 | * remark: Intel CPUs only support "syscall" in 64bit | |
2129 | * longmode. Also an 64bit guest with a | |
2130 | * 32bit compat-app running will #UD !! While this | |
2131 | * behaviour can be fixed (by emulating) into AMD | |
2132 | * response - CPUs of AMD can't behave like Intel. | |
2133 | */ | |
2134 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
2135 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
2136 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
2137 | return false; | |
2138 | ||
2139 | /* AMD ("AuthenticAMD") */ | |
2140 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
2141 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
2142 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
2143 | return true; | |
2144 | ||
2145 | /* AMD ("AMDisbetter!") */ | |
2146 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
2147 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
2148 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
2149 | return true; | |
c2226fc9 SB |
2150 | |
2151 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
2152 | return false; | |
2153 | } | |
2154 | ||
e01991e7 | 2155 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 2156 | { |
0225fb50 | 2157 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2158 | struct desc_struct cs, ss; |
e66bb2cc | 2159 | u64 msr_data; |
79168fd1 | 2160 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2161 | u64 efer = 0; |
e66bb2cc AP |
2162 | |
2163 | /* syscall is not available in real mode */ | |
2e901c4c | 2164 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
2165 | ctxt->mode == X86EMUL_MODE_VM86) |
2166 | return emulate_ud(ctxt); | |
e66bb2cc | 2167 | |
c2226fc9 SB |
2168 | if (!(em_syscall_is_enabled(ctxt))) |
2169 | return emulate_ud(ctxt); | |
2170 | ||
c2ad2bb3 | 2171 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 2172 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 2173 | |
c2226fc9 SB |
2174 | if (!(efer & EFER_SCE)) |
2175 | return emulate_ud(ctxt); | |
2176 | ||
717746e3 | 2177 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 2178 | msr_data >>= 32; |
79168fd1 GN |
2179 | cs_sel = (u16)(msr_data & 0xfffc); |
2180 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 2181 | |
c2ad2bb3 | 2182 | if (efer & EFER_LMA) { |
79168fd1 | 2183 | cs.d = 0; |
e66bb2cc AP |
2184 | cs.l = 1; |
2185 | } | |
1aa36616 AK |
2186 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2187 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 2188 | |
dd856efa | 2189 | *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; |
c2ad2bb3 | 2190 | if (efer & EFER_LMA) { |
e66bb2cc | 2191 | #ifdef CONFIG_X86_64 |
dd856efa | 2192 | *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 2193 | |
717746e3 | 2194 | ops->get_msr(ctxt, |
3fb1b5db GN |
2195 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
2196 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 2197 | ctxt->_eip = msr_data; |
e66bb2cc | 2198 | |
717746e3 | 2199 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
2200 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
2201 | #endif | |
2202 | } else { | |
2203 | /* legacy mode */ | |
717746e3 | 2204 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2205 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
2206 | |
2207 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2208 | } | |
2209 | ||
e54cfa97 | 2210 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2211 | } |
2212 | ||
e01991e7 | 2213 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2214 | { |
0225fb50 | 2215 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2216 | struct desc_struct cs, ss; |
8c604352 | 2217 | u64 msr_data; |
79168fd1 | 2218 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2219 | u64 efer = 0; |
8c604352 | 2220 | |
7b105ca2 | 2221 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2222 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2223 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2224 | return emulate_gp(ctxt, 0); | |
8c604352 | 2225 | |
1a18a69b AK |
2226 | /* |
2227 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2228 | * mode). | |
2229 | */ | |
2230 | if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) | |
2231 | && !vendor_intel(ctxt)) | |
2232 | return emulate_ud(ctxt); | |
2233 | ||
8c604352 AP |
2234 | /* XXX sysenter/sysexit have not been tested in 64bit mode. |
2235 | * Therefore, we inject an #UD. | |
2236 | */ | |
35d3d4a1 AK |
2237 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
2238 | return emulate_ud(ctxt); | |
8c604352 | 2239 | |
7b105ca2 | 2240 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2241 | |
717746e3 | 2242 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2243 | switch (ctxt->mode) { |
2244 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
2245 | if ((msr_data & 0xfffc) == 0x0) |
2246 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2247 | break; |
2248 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
2249 | if (msr_data == 0x0) |
2250 | return emulate_gp(ctxt, 0); | |
8c604352 | 2251 | break; |
9d1b39a9 GN |
2252 | default: |
2253 | break; | |
8c604352 AP |
2254 | } |
2255 | ||
2256 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2257 | cs_sel = (u16)msr_data; |
2258 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2259 | ss_sel = cs_sel + 8; | |
2260 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 2261 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 2262 | cs.d = 0; |
8c604352 AP |
2263 | cs.l = 1; |
2264 | } | |
2265 | ||
1aa36616 AK |
2266 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2267 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2268 | |
717746e3 | 2269 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 2270 | ctxt->_eip = msr_data; |
8c604352 | 2271 | |
717746e3 | 2272 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
dd856efa | 2273 | *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; |
8c604352 | 2274 | |
e54cfa97 | 2275 | return X86EMUL_CONTINUE; |
8c604352 AP |
2276 | } |
2277 | ||
e01991e7 | 2278 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2279 | { |
0225fb50 | 2280 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2281 | struct desc_struct cs, ss; |
4668f050 AP |
2282 | u64 msr_data; |
2283 | int usermode; | |
1249b96e | 2284 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2285 | |
a0044755 GN |
2286 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2287 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2288 | ctxt->mode == X86EMUL_MODE_VM86) |
2289 | return emulate_gp(ctxt, 0); | |
4668f050 | 2290 | |
7b105ca2 | 2291 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2292 | |
9dac77fa | 2293 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2294 | usermode = X86EMUL_MODE_PROT64; |
2295 | else | |
2296 | usermode = X86EMUL_MODE_PROT32; | |
2297 | ||
2298 | cs.dpl = 3; | |
2299 | ss.dpl = 3; | |
717746e3 | 2300 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2301 | switch (usermode) { |
2302 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2303 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2304 | if ((msr_data & 0xfffc) == 0x0) |
2305 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2306 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2307 | break; |
2308 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2309 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2310 | if (msr_data == 0x0) |
2311 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2312 | ss_sel = cs_sel + 8; |
2313 | cs.d = 0; | |
4668f050 AP |
2314 | cs.l = 1; |
2315 | break; | |
2316 | } | |
79168fd1 GN |
2317 | cs_sel |= SELECTOR_RPL_MASK; |
2318 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2319 | |
1aa36616 AK |
2320 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2321 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2322 | |
dd856efa AK |
2323 | ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); |
2324 | *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); | |
4668f050 | 2325 | |
e54cfa97 | 2326 | return X86EMUL_CONTINUE; |
4668f050 AP |
2327 | } |
2328 | ||
7b105ca2 | 2329 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2330 | { |
2331 | int iopl; | |
2332 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2333 | return false; | |
2334 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2335 | return true; | |
2336 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2337 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2338 | } |
2339 | ||
2340 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2341 | u16 port, u16 len) |
2342 | { | |
0225fb50 | 2343 | const struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2344 | struct desc_struct tr_seg; |
5601d05b | 2345 | u32 base3; |
f850e2e6 | 2346 | int r; |
1aa36616 | 2347 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2348 | unsigned mask = (1 << len) - 1; |
5601d05b | 2349 | unsigned long base; |
f850e2e6 | 2350 | |
1aa36616 | 2351 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2352 | if (!tr_seg.p) |
f850e2e6 | 2353 | return false; |
79168fd1 | 2354 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2355 | return false; |
5601d05b GN |
2356 | base = get_desc_base(&tr_seg); |
2357 | #ifdef CONFIG_X86_64 | |
2358 | base |= ((u64)base3) << 32; | |
2359 | #endif | |
0f65dd70 | 2360 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2361 | if (r != X86EMUL_CONTINUE) |
2362 | return false; | |
79168fd1 | 2363 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2364 | return false; |
0f65dd70 | 2365 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2366 | if (r != X86EMUL_CONTINUE) |
2367 | return false; | |
2368 | if ((perm >> bit_idx) & mask) | |
2369 | return false; | |
2370 | return true; | |
2371 | } | |
2372 | ||
2373 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2374 | u16 port, u16 len) |
2375 | { | |
4fc40f07 GN |
2376 | if (ctxt->perm_ok) |
2377 | return true; | |
2378 | ||
7b105ca2 TY |
2379 | if (emulator_bad_iopl(ctxt)) |
2380 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2381 | return false; |
4fc40f07 GN |
2382 | |
2383 | ctxt->perm_ok = true; | |
2384 | ||
f850e2e6 GN |
2385 | return true; |
2386 | } | |
2387 | ||
38ba30ba | 2388 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2389 | struct tss_segment_16 *tss) |
2390 | { | |
9dac77fa | 2391 | tss->ip = ctxt->_eip; |
38ba30ba | 2392 | tss->flag = ctxt->eflags; |
dd856efa AK |
2393 | tss->ax = reg_read(ctxt, VCPU_REGS_RAX); |
2394 | tss->cx = reg_read(ctxt, VCPU_REGS_RCX); | |
2395 | tss->dx = reg_read(ctxt, VCPU_REGS_RDX); | |
2396 | tss->bx = reg_read(ctxt, VCPU_REGS_RBX); | |
2397 | tss->sp = reg_read(ctxt, VCPU_REGS_RSP); | |
2398 | tss->bp = reg_read(ctxt, VCPU_REGS_RBP); | |
2399 | tss->si = reg_read(ctxt, VCPU_REGS_RSI); | |
2400 | tss->di = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2401 | |
1aa36616 AK |
2402 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2403 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2404 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2405 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2406 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2407 | } |
2408 | ||
2409 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2410 | struct tss_segment_16 *tss) |
2411 | { | |
38ba30ba GN |
2412 | int ret; |
2413 | ||
9dac77fa | 2414 | ctxt->_eip = tss->ip; |
38ba30ba | 2415 | ctxt->eflags = tss->flag | 2; |
dd856efa AK |
2416 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; |
2417 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; | |
2418 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; | |
2419 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; | |
2420 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; | |
2421 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; | |
2422 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; | |
2423 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; | |
38ba30ba GN |
2424 | |
2425 | /* | |
2426 | * SDM says that segment selectors are loaded before segment | |
2427 | * descriptors | |
2428 | */ | |
1aa36616 AK |
2429 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2430 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2431 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2432 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2433 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2434 | |
2435 | /* | |
fc058680 | 2436 | * Now load segment descriptors. If fault happens at this stage |
38ba30ba GN |
2437 | * it is handled in a context of new task |
2438 | */ | |
7b105ca2 | 2439 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2440 | if (ret != X86EMUL_CONTINUE) |
2441 | return ret; | |
7b105ca2 | 2442 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2443 | if (ret != X86EMUL_CONTINUE) |
2444 | return ret; | |
7b105ca2 | 2445 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2446 | if (ret != X86EMUL_CONTINUE) |
2447 | return ret; | |
7b105ca2 | 2448 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2449 | if (ret != X86EMUL_CONTINUE) |
2450 | return ret; | |
7b105ca2 | 2451 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2452 | if (ret != X86EMUL_CONTINUE) |
2453 | return ret; | |
2454 | ||
2455 | return X86EMUL_CONTINUE; | |
2456 | } | |
2457 | ||
2458 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2459 | u16 tss_selector, u16 old_tss_sel, |
2460 | ulong old_tss_base, struct desc_struct *new_desc) | |
2461 | { | |
0225fb50 | 2462 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2463 | struct tss_segment_16 tss_seg; |
2464 | int ret; | |
bcc55cba | 2465 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2466 | |
0f65dd70 | 2467 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2468 | &ctxt->exception); |
db297e3d | 2469 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2470 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2471 | return ret; |
38ba30ba | 2472 | |
7b105ca2 | 2473 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2474 | |
0f65dd70 | 2475 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2476 | &ctxt->exception); |
db297e3d | 2477 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2478 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2479 | return ret; |
38ba30ba | 2480 | |
0f65dd70 | 2481 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2482 | &ctxt->exception); |
db297e3d | 2483 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2484 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2485 | return ret; |
38ba30ba GN |
2486 | |
2487 | if (old_tss_sel != 0xffff) { | |
2488 | tss_seg.prev_task_link = old_tss_sel; | |
2489 | ||
0f65dd70 | 2490 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2491 | &tss_seg.prev_task_link, |
2492 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2493 | &ctxt->exception); |
db297e3d | 2494 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2495 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2496 | return ret; |
38ba30ba GN |
2497 | } |
2498 | ||
7b105ca2 | 2499 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2500 | } |
2501 | ||
2502 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2503 | struct tss_segment_32 *tss) |
2504 | { | |
7b105ca2 | 2505 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2506 | tss->eip = ctxt->_eip; |
38ba30ba | 2507 | tss->eflags = ctxt->eflags; |
dd856efa AK |
2508 | tss->eax = reg_read(ctxt, VCPU_REGS_RAX); |
2509 | tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
2510 | tss->edx = reg_read(ctxt, VCPU_REGS_RDX); | |
2511 | tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); | |
2512 | tss->esp = reg_read(ctxt, VCPU_REGS_RSP); | |
2513 | tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); | |
2514 | tss->esi = reg_read(ctxt, VCPU_REGS_RSI); | |
2515 | tss->edi = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2516 | |
1aa36616 AK |
2517 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2518 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2519 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2520 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2521 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2522 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2523 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2524 | } |
2525 | ||
2526 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2527 | struct tss_segment_32 *tss) |
2528 | { | |
38ba30ba GN |
2529 | int ret; |
2530 | ||
7b105ca2 | 2531 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2532 | return emulate_gp(ctxt, 0); |
9dac77fa | 2533 | ctxt->_eip = tss->eip; |
38ba30ba | 2534 | ctxt->eflags = tss->eflags | 2; |
4cee4798 KW |
2535 | |
2536 | /* General purpose registers */ | |
dd856efa AK |
2537 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; |
2538 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; | |
2539 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; | |
2540 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; | |
2541 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; | |
2542 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; | |
2543 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; | |
2544 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; | |
38ba30ba GN |
2545 | |
2546 | /* | |
2547 | * SDM says that segment selectors are loaded before segment | |
2548 | * descriptors | |
2549 | */ | |
1aa36616 AK |
2550 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2551 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2552 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2553 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2554 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2555 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2556 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba | 2557 | |
4cee4798 KW |
2558 | /* |
2559 | * If we're switching between Protected Mode and VM86, we need to make | |
2560 | * sure to update the mode before loading the segment descriptors so | |
2561 | * that the selectors are interpreted correctly. | |
2562 | * | |
2563 | * Need to get rflags to the vcpu struct immediately because it | |
2564 | * influences the CPL which is checked at least when loading the segment | |
2565 | * descriptors and when pushing an error code to the new kernel stack. | |
2566 | * | |
2567 | * TODO Introduce a separate ctxt->ops->set_cpl callback | |
2568 | */ | |
2569 | if (ctxt->eflags & X86_EFLAGS_VM) | |
2570 | ctxt->mode = X86EMUL_MODE_VM86; | |
2571 | else | |
2572 | ctxt->mode = X86EMUL_MODE_PROT32; | |
2573 | ||
2574 | ctxt->ops->set_rflags(ctxt, ctxt->eflags); | |
2575 | ||
38ba30ba GN |
2576 | /* |
2577 | * Now load segment descriptors. If fault happenes at this stage | |
2578 | * it is handled in a context of new task | |
2579 | */ | |
7b105ca2 | 2580 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2581 | if (ret != X86EMUL_CONTINUE) |
2582 | return ret; | |
7b105ca2 | 2583 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2584 | if (ret != X86EMUL_CONTINUE) |
2585 | return ret; | |
7b105ca2 | 2586 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2587 | if (ret != X86EMUL_CONTINUE) |
2588 | return ret; | |
7b105ca2 | 2589 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2590 | if (ret != X86EMUL_CONTINUE) |
2591 | return ret; | |
7b105ca2 | 2592 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2593 | if (ret != X86EMUL_CONTINUE) |
2594 | return ret; | |
7b105ca2 | 2595 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2596 | if (ret != X86EMUL_CONTINUE) |
2597 | return ret; | |
7b105ca2 | 2598 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2599 | if (ret != X86EMUL_CONTINUE) |
2600 | return ret; | |
2601 | ||
2602 | return X86EMUL_CONTINUE; | |
2603 | } | |
2604 | ||
2605 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2606 | u16 tss_selector, u16 old_tss_sel, |
2607 | ulong old_tss_base, struct desc_struct *new_desc) | |
2608 | { | |
0225fb50 | 2609 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2610 | struct tss_segment_32 tss_seg; |
2611 | int ret; | |
bcc55cba | 2612 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2613 | |
0f65dd70 | 2614 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2615 | &ctxt->exception); |
db297e3d | 2616 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2617 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2618 | return ret; |
38ba30ba | 2619 | |
7b105ca2 | 2620 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2621 | |
0f65dd70 | 2622 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2623 | &ctxt->exception); |
db297e3d | 2624 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2625 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2626 | return ret; |
38ba30ba | 2627 | |
0f65dd70 | 2628 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2629 | &ctxt->exception); |
db297e3d | 2630 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2631 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2632 | return ret; |
38ba30ba GN |
2633 | |
2634 | if (old_tss_sel != 0xffff) { | |
2635 | tss_seg.prev_task_link = old_tss_sel; | |
2636 | ||
0f65dd70 | 2637 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2638 | &tss_seg.prev_task_link, |
2639 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2640 | &ctxt->exception); |
db297e3d | 2641 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2642 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2643 | return ret; |
38ba30ba GN |
2644 | } |
2645 | ||
7b105ca2 | 2646 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2647 | } |
2648 | ||
2649 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2650 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2651 | bool has_error_code, u32 error_code) |
38ba30ba | 2652 | { |
0225fb50 | 2653 | const struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2654 | struct desc_struct curr_tss_desc, next_tss_desc; |
2655 | int ret; | |
1aa36616 | 2656 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2657 | ulong old_tss_base = |
4bff1e86 | 2658 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2659 | u32 desc_limit; |
e919464b | 2660 | ulong desc_addr; |
38ba30ba GN |
2661 | |
2662 | /* FIXME: old_tss_base == ~0 ? */ | |
2663 | ||
e919464b | 2664 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); |
38ba30ba GN |
2665 | if (ret != X86EMUL_CONTINUE) |
2666 | return ret; | |
e919464b | 2667 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); |
38ba30ba GN |
2668 | if (ret != X86EMUL_CONTINUE) |
2669 | return ret; | |
2670 | ||
2671 | /* FIXME: check that next_tss_desc is tss */ | |
2672 | ||
7f3d35fd KW |
2673 | /* |
2674 | * Check privileges. The three cases are task switch caused by... | |
2675 | * | |
2676 | * 1. jmp/call/int to task gate: Check against DPL of the task gate | |
2677 | * 2. Exception/IRQ/iret: No check is performed | |
fc058680 | 2678 | * 3. jmp/call to TSS: Check against DPL of the TSS |
7f3d35fd KW |
2679 | */ |
2680 | if (reason == TASK_SWITCH_GATE) { | |
2681 | if (idt_index != -1) { | |
2682 | /* Software interrupts */ | |
2683 | struct desc_struct task_gate_desc; | |
2684 | int dpl; | |
2685 | ||
2686 | ret = read_interrupt_descriptor(ctxt, idt_index, | |
2687 | &task_gate_desc); | |
2688 | if (ret != X86EMUL_CONTINUE) | |
2689 | return ret; | |
2690 | ||
2691 | dpl = task_gate_desc.dpl; | |
2692 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2693 | return emulate_gp(ctxt, (idt_index << 3) | 0x2); | |
2694 | } | |
2695 | } else if (reason != TASK_SWITCH_IRET) { | |
2696 | int dpl = next_tss_desc.dpl; | |
2697 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2698 | return emulate_gp(ctxt, tss_selector); | |
38ba30ba GN |
2699 | } |
2700 | ||
7f3d35fd | 2701 | |
ceffb459 GN |
2702 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2703 | if (!next_tss_desc.p || | |
2704 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2705 | desc_limit < 0x2b)) { | |
54b8486f | 2706 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2707 | return X86EMUL_PROPAGATE_FAULT; |
2708 | } | |
2709 | ||
2710 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2711 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2712 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2713 | } |
2714 | ||
2715 | if (reason == TASK_SWITCH_IRET) | |
2716 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2717 | ||
2718 | /* set back link to prev task only if NT bit is set in eflags | |
fc058680 | 2719 | note that old_tss_sel is not used after this point */ |
38ba30ba GN |
2720 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) |
2721 | old_tss_sel = 0xffff; | |
2722 | ||
2723 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2724 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2725 | old_tss_base, &next_tss_desc); |
2726 | else | |
7b105ca2 | 2727 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2728 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2729 | if (ret != X86EMUL_CONTINUE) |
2730 | return ret; | |
38ba30ba GN |
2731 | |
2732 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2733 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2734 | ||
2735 | if (reason != TASK_SWITCH_IRET) { | |
2736 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2737 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2738 | } |
2739 | ||
717746e3 | 2740 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2741 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2742 | |
e269fb21 | 2743 | if (has_error_code) { |
9dac77fa AK |
2744 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2745 | ctxt->lock_prefix = 0; | |
2746 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2747 | ret = em_push(ctxt); |
e269fb21 JK |
2748 | } |
2749 | ||
38ba30ba GN |
2750 | return ret; |
2751 | } | |
2752 | ||
2753 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2754 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2755 | bool has_error_code, u32 error_code) |
38ba30ba | 2756 | { |
38ba30ba GN |
2757 | int rc; |
2758 | ||
dd856efa | 2759 | invalidate_registers(ctxt); |
9dac77fa AK |
2760 | ctxt->_eip = ctxt->eip; |
2761 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2762 | |
7f3d35fd | 2763 | rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
e269fb21 | 2764 | has_error_code, error_code); |
38ba30ba | 2765 | |
dd856efa | 2766 | if (rc == X86EMUL_CONTINUE) { |
9dac77fa | 2767 | ctxt->eip = ctxt->_eip; |
dd856efa AK |
2768 | writeback_registers(ctxt); |
2769 | } | |
38ba30ba | 2770 | |
a0c0ab2f | 2771 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2772 | } |
2773 | ||
f3bd64c6 GN |
2774 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, |
2775 | struct operand *op) | |
a682e354 | 2776 | { |
b3356bf0 | 2777 | int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; |
a682e354 | 2778 | |
dd856efa AK |
2779 | register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes); |
2780 | op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg)); | |
a682e354 GN |
2781 | } |
2782 | ||
7af04fc0 AK |
2783 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2784 | { | |
7af04fc0 AK |
2785 | u8 al, old_al; |
2786 | bool af, cf, old_cf; | |
2787 | ||
2788 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2789 | al = ctxt->dst.val; |
7af04fc0 AK |
2790 | |
2791 | old_al = al; | |
2792 | old_cf = cf; | |
2793 | cf = false; | |
2794 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2795 | if ((al & 0x0f) > 9 || af) { | |
2796 | al -= 6; | |
2797 | cf = old_cf | (al >= 250); | |
2798 | af = true; | |
2799 | } else { | |
2800 | af = false; | |
2801 | } | |
2802 | if (old_al > 0x99 || old_cf) { | |
2803 | al -= 0x60; | |
2804 | cf = true; | |
2805 | } | |
2806 | ||
9dac77fa | 2807 | ctxt->dst.val = al; |
7af04fc0 | 2808 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2809 | ctxt->src.type = OP_IMM; |
2810 | ctxt->src.val = 0; | |
2811 | ctxt->src.bytes = 1; | |
158de57f | 2812 | fastop(ctxt, em_or); |
7af04fc0 AK |
2813 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2814 | if (cf) | |
2815 | ctxt->eflags |= X86_EFLAGS_CF; | |
2816 | if (af) | |
2817 | ctxt->eflags |= X86_EFLAGS_AF; | |
2818 | return X86EMUL_CONTINUE; | |
2819 | } | |
2820 | ||
a035d5c6 PB |
2821 | static int em_aam(struct x86_emulate_ctxt *ctxt) |
2822 | { | |
2823 | u8 al, ah; | |
2824 | ||
2825 | if (ctxt->src.val == 0) | |
2826 | return emulate_de(ctxt); | |
2827 | ||
2828 | al = ctxt->dst.val & 0xff; | |
2829 | ah = al / ctxt->src.val; | |
2830 | al %= ctxt->src.val; | |
2831 | ||
2832 | ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); | |
2833 | ||
2834 | /* Set PF, ZF, SF */ | |
2835 | ctxt->src.type = OP_IMM; | |
2836 | ctxt->src.val = 0; | |
2837 | ctxt->src.bytes = 1; | |
2838 | fastop(ctxt, em_or); | |
2839 | ||
2840 | return X86EMUL_CONTINUE; | |
2841 | } | |
2842 | ||
7f662273 GN |
2843 | static int em_aad(struct x86_emulate_ctxt *ctxt) |
2844 | { | |
2845 | u8 al = ctxt->dst.val & 0xff; | |
2846 | u8 ah = (ctxt->dst.val >> 8) & 0xff; | |
2847 | ||
2848 | al = (al + (ah * ctxt->src.val)) & 0xff; | |
2849 | ||
2850 | ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; | |
2851 | ||
f583c29b GN |
2852 | /* Set PF, ZF, SF */ |
2853 | ctxt->src.type = OP_IMM; | |
2854 | ctxt->src.val = 0; | |
2855 | ctxt->src.bytes = 1; | |
2856 | fastop(ctxt, em_or); | |
7f662273 GN |
2857 | |
2858 | return X86EMUL_CONTINUE; | |
2859 | } | |
2860 | ||
d4ddafcd TY |
2861 | static int em_call(struct x86_emulate_ctxt *ctxt) |
2862 | { | |
2863 | long rel = ctxt->src.val; | |
2864 | ||
2865 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
2866 | jmp_rel(ctxt, rel); | |
2867 | return em_push(ctxt); | |
2868 | } | |
2869 | ||
0ef753b8 AK |
2870 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2871 | { | |
0ef753b8 AK |
2872 | u16 sel, old_cs; |
2873 | ulong old_eip; | |
2874 | int rc; | |
2875 | ||
1aa36616 | 2876 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 2877 | old_eip = ctxt->_eip; |
0ef753b8 | 2878 | |
9dac77fa | 2879 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 2880 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
2881 | return X86EMUL_CONTINUE; |
2882 | ||
9dac77fa AK |
2883 | ctxt->_eip = 0; |
2884 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 2885 | |
9dac77fa | 2886 | ctxt->src.val = old_cs; |
4487b3b4 | 2887 | rc = em_push(ctxt); |
0ef753b8 AK |
2888 | if (rc != X86EMUL_CONTINUE) |
2889 | return rc; | |
2890 | ||
9dac77fa | 2891 | ctxt->src.val = old_eip; |
4487b3b4 | 2892 | return em_push(ctxt); |
0ef753b8 AK |
2893 | } |
2894 | ||
40ece7c7 AK |
2895 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2896 | { | |
40ece7c7 AK |
2897 | int rc; |
2898 | ||
9dac77fa AK |
2899 | ctxt->dst.type = OP_REG; |
2900 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2901 | ctxt->dst.bytes = ctxt->op_bytes; | |
2902 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
2903 | if (rc != X86EMUL_CONTINUE) |
2904 | return rc; | |
5ad105e5 | 2905 | rsp_increment(ctxt, ctxt->src.val); |
40ece7c7 AK |
2906 | return X86EMUL_CONTINUE; |
2907 | } | |
2908 | ||
e4f973ae TY |
2909 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
2910 | { | |
e4f973ae | 2911 | /* Write back the register source. */ |
9dac77fa AK |
2912 | ctxt->src.val = ctxt->dst.val; |
2913 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
2914 | |
2915 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
2916 | ctxt->dst.val = ctxt->src.orig_val; |
2917 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
2918 | return X86EMUL_CONTINUE; |
2919 | } | |
2920 | ||
5c82aa29 AK |
2921 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2922 | { | |
9dac77fa | 2923 | ctxt->dst.val = ctxt->src2.val; |
4d758349 | 2924 | return fastop(ctxt, em_imul); |
5c82aa29 AK |
2925 | } |
2926 | ||
61429142 AK |
2927 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2928 | { | |
9dac77fa AK |
2929 | ctxt->dst.type = OP_REG; |
2930 | ctxt->dst.bytes = ctxt->src.bytes; | |
dd856efa | 2931 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
9dac77fa | 2932 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); |
61429142 AK |
2933 | |
2934 | return X86EMUL_CONTINUE; | |
2935 | } | |
2936 | ||
48bb5d3c AK |
2937 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2938 | { | |
48bb5d3c AK |
2939 | u64 tsc = 0; |
2940 | ||
717746e3 | 2941 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
dd856efa AK |
2942 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; |
2943 | *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; | |
48bb5d3c AK |
2944 | return X86EMUL_CONTINUE; |
2945 | } | |
2946 | ||
222d21aa AK |
2947 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
2948 | { | |
2949 | u64 pmc; | |
2950 | ||
dd856efa | 2951 | if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) |
222d21aa | 2952 | return emulate_gp(ctxt, 0); |
dd856efa AK |
2953 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; |
2954 | *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; | |
222d21aa AK |
2955 | return X86EMUL_CONTINUE; |
2956 | } | |
2957 | ||
b9eac5f4 AK |
2958 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
2959 | { | |
49597d81 | 2960 | memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); |
b9eac5f4 AK |
2961 | return X86EMUL_CONTINUE; |
2962 | } | |
2963 | ||
bc00f8d2 TY |
2964 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
2965 | { | |
2966 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
2967 | return emulate_gp(ctxt, 0); | |
2968 | ||
2969 | /* Disable writeback. */ | |
2970 | ctxt->dst.type = OP_NONE; | |
2971 | return X86EMUL_CONTINUE; | |
2972 | } | |
2973 | ||
2974 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
2975 | { | |
2976 | unsigned long val; | |
2977 | ||
2978 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2979 | val = ctxt->src.val & ~0ULL; | |
2980 | else | |
2981 | val = ctxt->src.val & ~0U; | |
2982 | ||
2983 | /* #UD condition is already handled. */ | |
2984 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
2985 | return emulate_gp(ctxt, 0); | |
2986 | ||
2987 | /* Disable writeback. */ | |
2988 | ctxt->dst.type = OP_NONE; | |
2989 | return X86EMUL_CONTINUE; | |
2990 | } | |
2991 | ||
e1e210b0 TY |
2992 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
2993 | { | |
2994 | u64 msr_data; | |
2995 | ||
dd856efa AK |
2996 | msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) |
2997 | | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); | |
2998 | if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) | |
e1e210b0 TY |
2999 | return emulate_gp(ctxt, 0); |
3000 | ||
3001 | return X86EMUL_CONTINUE; | |
3002 | } | |
3003 | ||
3004 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
3005 | { | |
3006 | u64 msr_data; | |
3007 | ||
dd856efa | 3008 | if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) |
e1e210b0 TY |
3009 | return emulate_gp(ctxt, 0); |
3010 | ||
dd856efa AK |
3011 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; |
3012 | *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; | |
e1e210b0 TY |
3013 | return X86EMUL_CONTINUE; |
3014 | } | |
3015 | ||
1bd5f469 TY |
3016 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
3017 | { | |
9dac77fa | 3018 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3019 | return emulate_ud(ctxt); |
3020 | ||
9dac77fa | 3021 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
3022 | return X86EMUL_CONTINUE; |
3023 | } | |
3024 | ||
3025 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
3026 | { | |
9dac77fa | 3027 | u16 sel = ctxt->src.val; |
1bd5f469 | 3028 | |
9dac77fa | 3029 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3030 | return emulate_ud(ctxt); |
3031 | ||
9dac77fa | 3032 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
3033 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
3034 | ||
3035 | /* Disable writeback. */ | |
9dac77fa AK |
3036 | ctxt->dst.type = OP_NONE; |
3037 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
3038 | } |
3039 | ||
a14e579f AK |
3040 | static int em_lldt(struct x86_emulate_ctxt *ctxt) |
3041 | { | |
3042 | u16 sel = ctxt->src.val; | |
3043 | ||
3044 | /* Disable writeback. */ | |
3045 | ctxt->dst.type = OP_NONE; | |
3046 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); | |
3047 | } | |
3048 | ||
80890006 AK |
3049 | static int em_ltr(struct x86_emulate_ctxt *ctxt) |
3050 | { | |
3051 | u16 sel = ctxt->src.val; | |
3052 | ||
3053 | /* Disable writeback. */ | |
3054 | ctxt->dst.type = OP_NONE; | |
3055 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); | |
3056 | } | |
3057 | ||
38503911 AK |
3058 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
3059 | { | |
9fa088f4 AK |
3060 | int rc; |
3061 | ulong linear; | |
3062 | ||
9dac77fa | 3063 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 3064 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 3065 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 3066 | /* Disable writeback. */ |
9dac77fa | 3067 | ctxt->dst.type = OP_NONE; |
38503911 AK |
3068 | return X86EMUL_CONTINUE; |
3069 | } | |
3070 | ||
2d04a05b AK |
3071 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
3072 | { | |
3073 | ulong cr0; | |
3074 | ||
3075 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
3076 | cr0 &= ~X86_CR0_TS; | |
3077 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
3078 | return X86EMUL_CONTINUE; | |
3079 | } | |
3080 | ||
26d05cc7 AK |
3081 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
3082 | { | |
26d05cc7 AK |
3083 | int rc; |
3084 | ||
9dac77fa | 3085 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
3086 | return X86EMUL_UNHANDLEABLE; |
3087 | ||
3088 | rc = ctxt->ops->fix_hypercall(ctxt); | |
3089 | if (rc != X86EMUL_CONTINUE) | |
3090 | return rc; | |
3091 | ||
3092 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 3093 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 3094 | /* Disable writeback. */ |
9dac77fa | 3095 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3096 | return X86EMUL_CONTINUE; |
3097 | } | |
3098 | ||
96051572 AK |
3099 | static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, |
3100 | void (*get)(struct x86_emulate_ctxt *ctxt, | |
3101 | struct desc_ptr *ptr)) | |
3102 | { | |
3103 | struct desc_ptr desc_ptr; | |
3104 | ||
3105 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3106 | ctxt->op_bytes = 8; | |
3107 | get(ctxt, &desc_ptr); | |
3108 | if (ctxt->op_bytes == 2) { | |
3109 | ctxt->op_bytes = 4; | |
3110 | desc_ptr.address &= 0x00ffffff; | |
3111 | } | |
3112 | /* Disable writeback. */ | |
3113 | ctxt->dst.type = OP_NONE; | |
3114 | return segmented_write(ctxt, ctxt->dst.addr.mem, | |
3115 | &desc_ptr, 2 + ctxt->op_bytes); | |
3116 | } | |
3117 | ||
3118 | static int em_sgdt(struct x86_emulate_ctxt *ctxt) | |
3119 | { | |
3120 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); | |
3121 | } | |
3122 | ||
3123 | static int em_sidt(struct x86_emulate_ctxt *ctxt) | |
3124 | { | |
3125 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); | |
3126 | } | |
3127 | ||
26d05cc7 AK |
3128 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) |
3129 | { | |
26d05cc7 AK |
3130 | struct desc_ptr desc_ptr; |
3131 | int rc; | |
3132 | ||
510425ff AK |
3133 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3134 | ctxt->op_bytes = 8; | |
9dac77fa | 3135 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 3136 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3137 | ctxt->op_bytes); |
26d05cc7 AK |
3138 | if (rc != X86EMUL_CONTINUE) |
3139 | return rc; | |
3140 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
3141 | /* Disable writeback. */ | |
9dac77fa | 3142 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3143 | return X86EMUL_CONTINUE; |
3144 | } | |
3145 | ||
5ef39c71 | 3146 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 3147 | { |
26d05cc7 AK |
3148 | int rc; |
3149 | ||
5ef39c71 AK |
3150 | rc = ctxt->ops->fix_hypercall(ctxt); |
3151 | ||
26d05cc7 | 3152 | /* Disable writeback. */ |
9dac77fa | 3153 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3154 | return rc; |
3155 | } | |
3156 | ||
3157 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
3158 | { | |
26d05cc7 AK |
3159 | struct desc_ptr desc_ptr; |
3160 | int rc; | |
3161 | ||
510425ff AK |
3162 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3163 | ctxt->op_bytes = 8; | |
9dac77fa | 3164 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 3165 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3166 | ctxt->op_bytes); |
26d05cc7 AK |
3167 | if (rc != X86EMUL_CONTINUE) |
3168 | return rc; | |
3169 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
3170 | /* Disable writeback. */ | |
9dac77fa | 3171 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3172 | return X86EMUL_CONTINUE; |
3173 | } | |
3174 | ||
3175 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
3176 | { | |
9dac77fa AK |
3177 | ctxt->dst.bytes = 2; |
3178 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
3179 | return X86EMUL_CONTINUE; |
3180 | } | |
3181 | ||
3182 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
3183 | { | |
26d05cc7 | 3184 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
3185 | | (ctxt->src.val & 0x0f)); |
3186 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
3187 | return X86EMUL_CONTINUE; |
3188 | } | |
3189 | ||
d06e03ad TY |
3190 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
3191 | { | |
dd856efa AK |
3192 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); |
3193 | if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && | |
9dac77fa AK |
3194 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) |
3195 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
3196 | |
3197 | return X86EMUL_CONTINUE; | |
3198 | } | |
3199 | ||
3200 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
3201 | { | |
dd856efa | 3202 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) |
9dac77fa | 3203 | jmp_rel(ctxt, ctxt->src.val); |
d06e03ad TY |
3204 | |
3205 | return X86EMUL_CONTINUE; | |
3206 | } | |
3207 | ||
d7841a4b TY |
3208 | static int em_in(struct x86_emulate_ctxt *ctxt) |
3209 | { | |
3210 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
3211 | &ctxt->dst.val)) | |
3212 | return X86EMUL_IO_NEEDED; | |
3213 | ||
3214 | return X86EMUL_CONTINUE; | |
3215 | } | |
3216 | ||
3217 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
3218 | { | |
3219 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
3220 | &ctxt->src.val, 1); | |
3221 | /* Disable writeback. */ | |
3222 | ctxt->dst.type = OP_NONE; | |
3223 | return X86EMUL_CONTINUE; | |
3224 | } | |
3225 | ||
f411e6cd TY |
3226 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
3227 | { | |
3228 | if (emulator_bad_iopl(ctxt)) | |
3229 | return emulate_gp(ctxt, 0); | |
3230 | ||
3231 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
3232 | return X86EMUL_CONTINUE; | |
3233 | } | |
3234 | ||
3235 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
3236 | { | |
3237 | if (emulator_bad_iopl(ctxt)) | |
3238 | return emulate_gp(ctxt, 0); | |
3239 | ||
3240 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
3241 | ctxt->eflags |= X86_EFLAGS_IF; | |
3242 | return X86EMUL_CONTINUE; | |
3243 | } | |
3244 | ||
6d6eede4 AK |
3245 | static int em_cpuid(struct x86_emulate_ctxt *ctxt) |
3246 | { | |
3247 | u32 eax, ebx, ecx, edx; | |
3248 | ||
dd856efa AK |
3249 | eax = reg_read(ctxt, VCPU_REGS_RAX); |
3250 | ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
6d6eede4 | 3251 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
dd856efa AK |
3252 | *reg_write(ctxt, VCPU_REGS_RAX) = eax; |
3253 | *reg_write(ctxt, VCPU_REGS_RBX) = ebx; | |
3254 | *reg_write(ctxt, VCPU_REGS_RCX) = ecx; | |
3255 | *reg_write(ctxt, VCPU_REGS_RDX) = edx; | |
6d6eede4 AK |
3256 | return X86EMUL_CONTINUE; |
3257 | } | |
3258 | ||
2dd7caa0 AK |
3259 | static int em_lahf(struct x86_emulate_ctxt *ctxt) |
3260 | { | |
dd856efa AK |
3261 | *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; |
3262 | *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; | |
2dd7caa0 AK |
3263 | return X86EMUL_CONTINUE; |
3264 | } | |
3265 | ||
9299836e AK |
3266 | static int em_bswap(struct x86_emulate_ctxt *ctxt) |
3267 | { | |
3268 | switch (ctxt->op_bytes) { | |
3269 | #ifdef CONFIG_X86_64 | |
3270 | case 8: | |
3271 | asm("bswap %0" : "+r"(ctxt->dst.val)); | |
3272 | break; | |
3273 | #endif | |
3274 | default: | |
3275 | asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); | |
3276 | break; | |
3277 | } | |
3278 | return X86EMUL_CONTINUE; | |
3279 | } | |
3280 | ||
cfec82cb JR |
3281 | static bool valid_cr(int nr) |
3282 | { | |
3283 | switch (nr) { | |
3284 | case 0: | |
3285 | case 2 ... 4: | |
3286 | case 8: | |
3287 | return true; | |
3288 | default: | |
3289 | return false; | |
3290 | } | |
3291 | } | |
3292 | ||
3293 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3294 | { | |
9dac77fa | 3295 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3296 | return emulate_ud(ctxt); |
3297 | ||
3298 | return X86EMUL_CONTINUE; | |
3299 | } | |
3300 | ||
3301 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3302 | { | |
9dac77fa AK |
3303 | u64 new_val = ctxt->src.val64; |
3304 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3305 | u64 efer = 0; |
cfec82cb JR |
3306 | |
3307 | static u64 cr_reserved_bits[] = { | |
3308 | 0xffffffff00000000ULL, | |
3309 | 0, 0, 0, /* CR3 checked later */ | |
3310 | CR4_RESERVED_BITS, | |
3311 | 0, 0, 0, | |
3312 | CR8_RESERVED_BITS, | |
3313 | }; | |
3314 | ||
3315 | if (!valid_cr(cr)) | |
3316 | return emulate_ud(ctxt); | |
3317 | ||
3318 | if (new_val & cr_reserved_bits[cr]) | |
3319 | return emulate_gp(ctxt, 0); | |
3320 | ||
3321 | switch (cr) { | |
3322 | case 0: { | |
c2ad2bb3 | 3323 | u64 cr4; |
cfec82cb JR |
3324 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3325 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3326 | return emulate_gp(ctxt, 0); | |
3327 | ||
717746e3 AK |
3328 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3329 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3330 | |
3331 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3332 | !(cr4 & X86_CR4_PAE)) | |
3333 | return emulate_gp(ctxt, 0); | |
3334 | ||
3335 | break; | |
3336 | } | |
3337 | case 3: { | |
3338 | u64 rsvd = 0; | |
3339 | ||
c2ad2bb3 AK |
3340 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3341 | if (efer & EFER_LMA) | |
cfec82cb | 3342 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 3343 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 3344 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 3345 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
3346 | rsvd = CR3_NONPAE_RESERVED_BITS; |
3347 | ||
3348 | if (new_val & rsvd) | |
3349 | return emulate_gp(ctxt, 0); | |
3350 | ||
3351 | break; | |
3352 | } | |
3353 | case 4: { | |
717746e3 | 3354 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3355 | |
3356 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3357 | return emulate_gp(ctxt, 0); | |
3358 | ||
3359 | break; | |
3360 | } | |
3361 | } | |
3362 | ||
3363 | return X86EMUL_CONTINUE; | |
3364 | } | |
3365 | ||
3b88e41a JR |
3366 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3367 | { | |
3368 | unsigned long dr7; | |
3369 | ||
717746e3 | 3370 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3371 | |
3372 | /* Check if DR7.Global_Enable is set */ | |
3373 | return dr7 & (1 << 13); | |
3374 | } | |
3375 | ||
3376 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3377 | { | |
9dac77fa | 3378 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3379 | u64 cr4; |
3380 | ||
3381 | if (dr > 7) | |
3382 | return emulate_ud(ctxt); | |
3383 | ||
717746e3 | 3384 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3385 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3386 | return emulate_ud(ctxt); | |
3387 | ||
3388 | if (check_dr7_gd(ctxt)) | |
3389 | return emulate_db(ctxt); | |
3390 | ||
3391 | return X86EMUL_CONTINUE; | |
3392 | } | |
3393 | ||
3394 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3395 | { | |
9dac77fa AK |
3396 | u64 new_val = ctxt->src.val64; |
3397 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3398 | |
3399 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3400 | return emulate_gp(ctxt, 0); | |
3401 | ||
3402 | return check_dr_read(ctxt); | |
3403 | } | |
3404 | ||
01de8b09 JR |
3405 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3406 | { | |
3407 | u64 efer; | |
3408 | ||
717746e3 | 3409 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3410 | |
3411 | if (!(efer & EFER_SVME)) | |
3412 | return emulate_ud(ctxt); | |
3413 | ||
3414 | return X86EMUL_CONTINUE; | |
3415 | } | |
3416 | ||
3417 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3418 | { | |
dd856efa | 3419 | u64 rax = reg_read(ctxt, VCPU_REGS_RAX); |
01de8b09 JR |
3420 | |
3421 | /* Valid physical address? */ | |
d4224449 | 3422 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3423 | return emulate_gp(ctxt, 0); |
3424 | ||
3425 | return check_svme(ctxt); | |
3426 | } | |
3427 | ||
d7eb8203 JR |
3428 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3429 | { | |
717746e3 | 3430 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3431 | |
717746e3 | 3432 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3433 | return emulate_ud(ctxt); |
3434 | ||
3435 | return X86EMUL_CONTINUE; | |
3436 | } | |
3437 | ||
8061252e JR |
3438 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3439 | { | |
717746e3 | 3440 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
dd856efa | 3441 | u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); |
8061252e | 3442 | |
717746e3 | 3443 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
3444 | (rcx > 3)) |
3445 | return emulate_gp(ctxt, 0); | |
3446 | ||
3447 | return X86EMUL_CONTINUE; | |
3448 | } | |
3449 | ||
f6511935 JR |
3450 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3451 | { | |
9dac77fa AK |
3452 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3453 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3454 | return emulate_gp(ctxt, 0); |
3455 | ||
3456 | return X86EMUL_CONTINUE; | |
3457 | } | |
3458 | ||
3459 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3460 | { | |
9dac77fa AK |
3461 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3462 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3463 | return emulate_gp(ctxt, 0); |
3464 | ||
3465 | return X86EMUL_CONTINUE; | |
3466 | } | |
3467 | ||
73fba5f4 | 3468 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 3469 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
3470 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
3471 | .check_perm = (_p) } | |
0b789eee | 3472 | #define N D(NotImpl) |
01de8b09 | 3473 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
1c2545be TY |
3474 | #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
3475 | #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } | |
045a282c | 3476 | #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } |
73fba5f4 | 3477 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
e28bbd44 | 3478 | #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } |
c4f035c6 AK |
3479 | #define II(_f, _e, _i) \ |
3480 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
3481 | #define IIP(_f, _e, _i, _p) \ |
3482 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
3483 | .check_perm = (_p) } | |
aa97bb48 | 3484 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3485 | |
8d8f4e9f | 3486 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3487 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3488 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
f7857f35 | 3489 | #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) |
d7841a4b TY |
3490 | #define I2bvIP(_f, _e, _i, _p) \ |
3491 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3492 | |
fb864fbc AK |
3493 | #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3494 | F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3495 | F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3496 | |
fd0a0d82 | 3497 | static const struct opcode group7_rm1[] = { |
1c2545be TY |
3498 | DI(SrcNone | Priv, monitor), |
3499 | DI(SrcNone | Priv, mwait), | |
d7eb8203 JR |
3500 | N, N, N, N, N, N, |
3501 | }; | |
3502 | ||
fd0a0d82 | 3503 | static const struct opcode group7_rm3[] = { |
1c2545be TY |
3504 | DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), |
3505 | II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall), | |
3506 | DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), | |
3507 | DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), | |
3508 | DIP(SrcNone | Prot | Priv, stgi, check_svme), | |
3509 | DIP(SrcNone | Prot | Priv, clgi, check_svme), | |
3510 | DIP(SrcNone | Prot | Priv, skinit, check_svme), | |
3511 | DIP(SrcNone | Prot | Priv, invlpga, check_svme), | |
01de8b09 | 3512 | }; |
6230f7fc | 3513 | |
fd0a0d82 | 3514 | static const struct opcode group7_rm7[] = { |
d7eb8203 | 3515 | N, |
1c2545be | 3516 | DIP(SrcNone, rdtscp, check_rdtsc), |
d7eb8203 JR |
3517 | N, N, N, N, N, N, |
3518 | }; | |
d67fc27a | 3519 | |
fd0a0d82 | 3520 | static const struct opcode group1[] = { |
fb864fbc AK |
3521 | F(Lock, em_add), |
3522 | F(Lock | PageTable, em_or), | |
3523 | F(Lock, em_adc), | |
3524 | F(Lock, em_sbb), | |
3525 | F(Lock | PageTable, em_and), | |
3526 | F(Lock, em_sub), | |
3527 | F(Lock, em_xor), | |
3528 | F(NoWrite, em_cmp), | |
73fba5f4 AK |
3529 | }; |
3530 | ||
fd0a0d82 | 3531 | static const struct opcode group1A[] = { |
1c2545be | 3532 | I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3533 | }; |
3534 | ||
007a3b54 AK |
3535 | static const struct opcode group2[] = { |
3536 | F(DstMem | ModRM, em_rol), | |
3537 | F(DstMem | ModRM, em_ror), | |
3538 | F(DstMem | ModRM, em_rcl), | |
3539 | F(DstMem | ModRM, em_rcr), | |
3540 | F(DstMem | ModRM, em_shl), | |
3541 | F(DstMem | ModRM, em_shr), | |
3542 | F(DstMem | ModRM, em_shl), | |
3543 | F(DstMem | ModRM, em_sar), | |
3544 | }; | |
3545 | ||
fd0a0d82 | 3546 | static const struct opcode group3[] = { |
fb864fbc AK |
3547 | F(DstMem | SrcImm | NoWrite, em_test), |
3548 | F(DstMem | SrcImm | NoWrite, em_test), | |
45a1467d AK |
3549 | F(DstMem | SrcNone | Lock, em_not), |
3550 | F(DstMem | SrcNone | Lock, em_neg), | |
b9fa409b AK |
3551 | F(DstXacc | Src2Mem, em_mul_ex), |
3552 | F(DstXacc | Src2Mem, em_imul_ex), | |
b8c0b6ae AK |
3553 | F(DstXacc | Src2Mem, em_div_ex), |
3554 | F(DstXacc | Src2Mem, em_idiv_ex), | |
73fba5f4 AK |
3555 | }; |
3556 | ||
fd0a0d82 | 3557 | static const struct opcode group4[] = { |
95413dc4 AK |
3558 | F(ByteOp | DstMem | SrcNone | Lock, em_inc), |
3559 | F(ByteOp | DstMem | SrcNone | Lock, em_dec), | |
73fba5f4 AK |
3560 | N, N, N, N, N, N, |
3561 | }; | |
3562 | ||
fd0a0d82 | 3563 | static const struct opcode group5[] = { |
95413dc4 AK |
3564 | F(DstMem | SrcNone | Lock, em_inc), |
3565 | F(DstMem | SrcNone | Lock, em_dec), | |
1c2545be TY |
3566 | I(SrcMem | Stack, em_grp45), |
3567 | I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), | |
3568 | I(SrcMem | Stack, em_grp45), | |
3569 | I(SrcMemFAddr | ImplicitOps, em_grp45), | |
188424ba | 3570 | I(SrcMem | Stack, em_grp45), D(Undefined), |
73fba5f4 AK |
3571 | }; |
3572 | ||
fd0a0d82 | 3573 | static const struct opcode group6[] = { |
1c2545be TY |
3574 | DI(Prot, sldt), |
3575 | DI(Prot, str), | |
a14e579f | 3576 | II(Prot | Priv | SrcMem16, em_lldt, lldt), |
80890006 | 3577 | II(Prot | Priv | SrcMem16, em_ltr, ltr), |
dee6bb70 JR |
3578 | N, N, N, N, |
3579 | }; | |
3580 | ||
fd0a0d82 | 3581 | static const struct group_dual group7 = { { |
96051572 AK |
3582 | II(Mov | DstMem | Priv, em_sgdt, sgdt), |
3583 | II(Mov | DstMem | Priv, em_sidt, sidt), | |
1c2545be TY |
3584 | II(SrcMem | Priv, em_lgdt, lgdt), |
3585 | II(SrcMem | Priv, em_lidt, lidt), | |
3586 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, | |
3587 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3588 | II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3589 | }, { |
1c2545be | 3590 | I(SrcNone | Priv | VendorSpecific, em_vmcall), |
5ef39c71 | 3591 | EXT(0, group7_rm1), |
01de8b09 | 3592 | N, EXT(0, group7_rm3), |
1c2545be TY |
3593 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
3594 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3595 | EXT(0, group7_rm7), | |
73fba5f4 AK |
3596 | } }; |
3597 | ||
fd0a0d82 | 3598 | static const struct opcode group8[] = { |
73fba5f4 | 3599 | N, N, N, N, |
11c363ba AK |
3600 | F(DstMem | SrcImmByte | NoWrite, em_bt), |
3601 | F(DstMem | SrcImmByte | Lock | PageTable, em_bts), | |
3602 | F(DstMem | SrcImmByte | Lock, em_btr), | |
3603 | F(DstMem | SrcImmByte | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3604 | }; |
3605 | ||
fd0a0d82 | 3606 | static const struct group_dual group9 = { { |
1c2545be | 3607 | N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3608 | }, { |
3609 | N, N, N, N, N, N, N, N, | |
3610 | } }; | |
3611 | ||
fd0a0d82 | 3612 | static const struct opcode group11[] = { |
1c2545be | 3613 | I(DstMem | SrcImm | Mov | PageTable, em_mov), |
d5ae7ce8 | 3614 | X7(D(Undefined)), |
a4d4a7c1 AK |
3615 | }; |
3616 | ||
fd0a0d82 | 3617 | static const struct gprefix pfx_0f_6f_0f_7f = { |
e5971755 | 3618 | I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
aa97bb48 AK |
3619 | }; |
3620 | ||
fd0a0d82 | 3621 | static const struct gprefix pfx_vmovntpx = { |
3e114eb4 AK |
3622 | I(0, em_mov), N, N, N, |
3623 | }; | |
3624 | ||
045a282c GN |
3625 | static const struct escape escape_d9 = { { |
3626 | N, N, N, N, N, N, N, I(DstMem, em_fnstcw), | |
3627 | }, { | |
3628 | /* 0xC0 - 0xC7 */ | |
3629 | N, N, N, N, N, N, N, N, | |
3630 | /* 0xC8 - 0xCF */ | |
3631 | N, N, N, N, N, N, N, N, | |
3632 | /* 0xD0 - 0xC7 */ | |
3633 | N, N, N, N, N, N, N, N, | |
3634 | /* 0xD8 - 0xDF */ | |
3635 | N, N, N, N, N, N, N, N, | |
3636 | /* 0xE0 - 0xE7 */ | |
3637 | N, N, N, N, N, N, N, N, | |
3638 | /* 0xE8 - 0xEF */ | |
3639 | N, N, N, N, N, N, N, N, | |
3640 | /* 0xF0 - 0xF7 */ | |
3641 | N, N, N, N, N, N, N, N, | |
3642 | /* 0xF8 - 0xFF */ | |
3643 | N, N, N, N, N, N, N, N, | |
3644 | } }; | |
3645 | ||
3646 | static const struct escape escape_db = { { | |
3647 | N, N, N, N, N, N, N, N, | |
3648 | }, { | |
3649 | /* 0xC0 - 0xC7 */ | |
3650 | N, N, N, N, N, N, N, N, | |
3651 | /* 0xC8 - 0xCF */ | |
3652 | N, N, N, N, N, N, N, N, | |
3653 | /* 0xD0 - 0xC7 */ | |
3654 | N, N, N, N, N, N, N, N, | |
3655 | /* 0xD8 - 0xDF */ | |
3656 | N, N, N, N, N, N, N, N, | |
3657 | /* 0xE0 - 0xE7 */ | |
3658 | N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, | |
3659 | /* 0xE8 - 0xEF */ | |
3660 | N, N, N, N, N, N, N, N, | |
3661 | /* 0xF0 - 0xF7 */ | |
3662 | N, N, N, N, N, N, N, N, | |
3663 | /* 0xF8 - 0xFF */ | |
3664 | N, N, N, N, N, N, N, N, | |
3665 | } }; | |
3666 | ||
3667 | static const struct escape escape_dd = { { | |
3668 | N, N, N, N, N, N, N, I(DstMem, em_fnstsw), | |
3669 | }, { | |
3670 | /* 0xC0 - 0xC7 */ | |
3671 | N, N, N, N, N, N, N, N, | |
3672 | /* 0xC8 - 0xCF */ | |
3673 | N, N, N, N, N, N, N, N, | |
3674 | /* 0xD0 - 0xC7 */ | |
3675 | N, N, N, N, N, N, N, N, | |
3676 | /* 0xD8 - 0xDF */ | |
3677 | N, N, N, N, N, N, N, N, | |
3678 | /* 0xE0 - 0xE7 */ | |
3679 | N, N, N, N, N, N, N, N, | |
3680 | /* 0xE8 - 0xEF */ | |
3681 | N, N, N, N, N, N, N, N, | |
3682 | /* 0xF0 - 0xF7 */ | |
3683 | N, N, N, N, N, N, N, N, | |
3684 | /* 0xF8 - 0xFF */ | |
3685 | N, N, N, N, N, N, N, N, | |
3686 | } }; | |
3687 | ||
fd0a0d82 | 3688 | static const struct opcode opcode_table[256] = { |
73fba5f4 | 3689 | /* 0x00 - 0x07 */ |
fb864fbc | 3690 | F6ALU(Lock, em_add), |
1cd196ea AK |
3691 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
3692 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 3693 | /* 0x08 - 0x0F */ |
fb864fbc | 3694 | F6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
3695 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
3696 | N, | |
73fba5f4 | 3697 | /* 0x10 - 0x17 */ |
fb864fbc | 3698 | F6ALU(Lock, em_adc), |
1cd196ea AK |
3699 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
3700 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 3701 | /* 0x18 - 0x1F */ |
fb864fbc | 3702 | F6ALU(Lock, em_sbb), |
1cd196ea AK |
3703 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
3704 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 3705 | /* 0x20 - 0x27 */ |
fb864fbc | 3706 | F6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 3707 | /* 0x28 - 0x2F */ |
fb864fbc | 3708 | F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3709 | /* 0x30 - 0x37 */ |
fb864fbc | 3710 | F6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3711 | /* 0x38 - 0x3F */ |
fb864fbc | 3712 | F6ALU(NoWrite, em_cmp), N, N, |
73fba5f4 | 3713 | /* 0x40 - 0x4F */ |
95413dc4 | 3714 | X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), |
73fba5f4 | 3715 | /* 0x50 - 0x57 */ |
63540382 | 3716 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3717 | /* 0x58 - 0x5F */ |
c54fe504 | 3718 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3719 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3720 | I(ImplicitOps | Stack | No64, em_pusha), |
3721 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3722 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3723 | N, N, N, N, | |
3724 | /* 0x68 - 0x6F */ | |
d46164db AK |
3725 | I(SrcImm | Mov | Stack, em_push), |
3726 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3727 | I(SrcImmByte | Mov | Stack, em_push), |
3728 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
b3356bf0 | 3729 | I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ |
2b5e97e1 | 3730 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ |
73fba5f4 AK |
3731 | /* 0x70 - 0x7F */ |
3732 | X16(D(SrcImmByte)), | |
3733 | /* 0x80 - 0x87 */ | |
1c2545be TY |
3734 | G(ByteOp | DstMem | SrcImm, group1), |
3735 | G(DstMem | SrcImm, group1), | |
3736 | G(ByteOp | DstMem | SrcImm | No64, group1), | |
3737 | G(DstMem | SrcImmByte, group1), | |
fb864fbc | 3738 | F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), |
d5ae7ce8 | 3739 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 3740 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 3741 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 3742 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 3743 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
3744 | D(ModRM | SrcMem | NoAccess | DstReg), |
3745 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3746 | G(0, group1A), | |
73fba5f4 | 3747 | /* 0x90 - 0x97 */ |
bf608f88 | 3748 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3749 | /* 0x98 - 0x9F */ |
61429142 | 3750 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3751 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 | 3752 | II(ImplicitOps | Stack, em_pushf, pushf), |
2dd7caa0 | 3753 | II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf), |
73fba5f4 | 3754 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 3755 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 3756 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 3757 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
fb864fbc | 3758 | F2bv(SrcSI | DstDI | String | NoWrite, em_cmp), |
73fba5f4 | 3759 | /* 0xA8 - 0xAF */ |
fb864fbc | 3760 | F2bv(DstAcc | SrcImm | NoWrite, em_test), |
b9eac5f4 AK |
3761 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3762 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
fb864fbc | 3763 | F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp), |
73fba5f4 | 3764 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3765 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3766 | /* 0xB8 - 0xBF */ |
5e2c6883 | 3767 | X8(I(DstReg | SrcImm64 | Mov, em_mov)), |
73fba5f4 | 3768 | /* 0xC0 - 0xC7 */ |
007a3b54 | 3769 | G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), |
40ece7c7 | 3770 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3771 | I(ImplicitOps | Stack, em_ret), |
d4b4325f AK |
3772 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
3773 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 3774 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3775 | /* 0xC8 - 0xCF */ |
612e89f0 | 3776 | I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), |
3261107e BR |
3777 | I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm), |
3778 | I(ImplicitOps | Stack, em_ret_far), | |
3c6e276f | 3779 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3780 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3781 | /* 0xD0 - 0xD7 */ |
007a3b54 AK |
3782 | G(Src2One | ByteOp, group2), G(Src2One, group2), |
3783 | G(Src2CL | ByteOp, group2), G(Src2CL, group2), | |
a035d5c6 | 3784 | I(DstAcc | SrcImmUByte | No64, em_aam), |
326f578f PB |
3785 | I(DstAcc | SrcImmUByte | No64, em_aad), |
3786 | F(DstAcc | ByteOp | No64, em_salc), | |
7fa57952 | 3787 | I(DstAcc | SrcXLat | ByteOp, em_mov), |
73fba5f4 | 3788 | /* 0xD8 - 0xDF */ |
045a282c | 3789 | N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, |
73fba5f4 | 3790 | /* 0xE0 - 0xE7 */ |
d06e03ad TY |
3791 | X3(I(SrcImmByte, em_loop)), |
3792 | I(SrcImmByte, em_jcxz), | |
d7841a4b TY |
3793 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
3794 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 3795 | /* 0xE8 - 0xEF */ |
d4ddafcd | 3796 | I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), |
db5b0762 | 3797 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
d7841a4b TY |
3798 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
3799 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 3800 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3801 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3802 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3803 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3804 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3805 | D(ImplicitOps), D(ImplicitOps), |
3806 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3807 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3808 | }; | |
3809 | ||
fd0a0d82 | 3810 | static const struct opcode twobyte_table[256] = { |
73fba5f4 | 3811 | /* 0x00 - 0x0F */ |
dee6bb70 | 3812 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3813 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3814 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3815 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3816 | N, D(ImplicitOps | ModRM), N, N, |
3817 | /* 0x10 - 0x1F */ | |
103f98ea PB |
3818 | N, N, N, N, N, N, N, N, |
3819 | D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM), | |
73fba5f4 | 3820 | /* 0x20 - 0x2F */ |
cfec82cb | 3821 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3822 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
bc00f8d2 TY |
3823 | IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), |
3824 | IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), | |
73fba5f4 | 3825 | N, N, N, N, |
3e114eb4 AK |
3826 | N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx), |
3827 | N, N, N, N, | |
73fba5f4 | 3828 | /* 0x30 - 0x3F */ |
e1e210b0 | 3829 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 3830 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 3831 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 3832 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
db5b0762 TY |
3833 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3834 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3835 | N, N, |
73fba5f4 AK |
3836 | N, N, N, N, N, N, N, N, |
3837 | /* 0x40 - 0x4F */ | |
3838 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3839 | /* 0x50 - 0x5F */ | |
3840 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3841 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3842 | N, N, N, N, |
3843 | N, N, N, N, | |
3844 | N, N, N, N, | |
3845 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3846 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3847 | N, N, N, N, |
3848 | N, N, N, N, | |
3849 | N, N, N, N, | |
3850 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
3851 | /* 0x80 - 0x8F */ |
3852 | X16(D(SrcImm)), | |
3853 | /* 0x90 - 0x9F */ | |
ee45b58e | 3854 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 3855 | /* 0xA0 - 0xA7 */ |
1cd196ea | 3856 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
11c363ba AK |
3857 | II(ImplicitOps, em_cpuid, cpuid), |
3858 | F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), | |
0bdea068 AK |
3859 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), |
3860 | F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, | |
73fba5f4 | 3861 | /* 0xA8 - 0xAF */ |
1cd196ea | 3862 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 3863 | DI(ImplicitOps, rsm), |
11c363ba | 3864 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
0bdea068 AK |
3865 | F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), |
3866 | F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), | |
4d758349 | 3867 | D(ModRM), F(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 3868 | /* 0xB0 - 0xB7 */ |
e940b5c2 | 3869 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
d4b4325f | 3870 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
11c363ba | 3871 | F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
3872 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
3873 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 3874 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
3875 | /* 0xB8 - 0xBF */ |
3876 | N, N, | |
ce7faab2 | 3877 | G(BitOp, group8), |
11c363ba AK |
3878 | F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), |
3879 | F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr), | |
2adb5ad9 | 3880 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
9299836e | 3881 | /* 0xC0 - 0xC7 */ |
e47a5f5f | 3882 | F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), |
92f738a5 | 3883 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 | 3884 | N, N, N, GD(0, &group9), |
9299836e AK |
3885 | /* 0xC8 - 0xCF */ |
3886 | X8(I(DstReg, em_bswap)), | |
73fba5f4 AK |
3887 | /* 0xD0 - 0xDF */ |
3888 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3889 | /* 0xE0 - 0xEF */ | |
3890 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3891 | /* 0xF0 - 0xFF */ | |
3892 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
3893 | }; | |
3894 | ||
3895 | #undef D | |
3896 | #undef N | |
3897 | #undef G | |
3898 | #undef GD | |
3899 | #undef I | |
aa97bb48 | 3900 | #undef GP |
01de8b09 | 3901 | #undef EXT |
73fba5f4 | 3902 | |
8d8f4e9f | 3903 | #undef D2bv |
f6511935 | 3904 | #undef D2bvIP |
8d8f4e9f | 3905 | #undef I2bv |
d7841a4b | 3906 | #undef I2bvIP |
d67fc27a | 3907 | #undef I6ALU |
8d8f4e9f | 3908 | |
9dac77fa | 3909 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
3910 | { |
3911 | unsigned size; | |
3912 | ||
9dac77fa | 3913 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
3914 | if (size == 8) |
3915 | size = 4; | |
3916 | return size; | |
3917 | } | |
3918 | ||
3919 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3920 | unsigned size, bool sign_extension) | |
3921 | { | |
39f21ee5 AK |
3922 | int rc = X86EMUL_CONTINUE; |
3923 | ||
3924 | op->type = OP_IMM; | |
3925 | op->bytes = size; | |
9dac77fa | 3926 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
3927 | /* NB. Immediates are sign-extended as necessary. */ |
3928 | switch (op->bytes) { | |
3929 | case 1: | |
e85a1085 | 3930 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
3931 | break; |
3932 | case 2: | |
e85a1085 | 3933 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
3934 | break; |
3935 | case 4: | |
e85a1085 | 3936 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 | 3937 | break; |
5e2c6883 NA |
3938 | case 8: |
3939 | op->val = insn_fetch(s64, ctxt); | |
3940 | break; | |
39f21ee5 AK |
3941 | } |
3942 | if (!sign_extension) { | |
3943 | switch (op->bytes) { | |
3944 | case 1: | |
3945 | op->val &= 0xff; | |
3946 | break; | |
3947 | case 2: | |
3948 | op->val &= 0xffff; | |
3949 | break; | |
3950 | case 4: | |
3951 | op->val &= 0xffffffff; | |
3952 | break; | |
3953 | } | |
3954 | } | |
3955 | done: | |
3956 | return rc; | |
3957 | } | |
3958 | ||
a9945549 AK |
3959 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
3960 | unsigned d) | |
3961 | { | |
3962 | int rc = X86EMUL_CONTINUE; | |
3963 | ||
3964 | switch (d) { | |
3965 | case OpReg: | |
2adb5ad9 | 3966 | decode_register_operand(ctxt, op); |
a9945549 AK |
3967 | break; |
3968 | case OpImmUByte: | |
608aabe3 | 3969 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
3970 | break; |
3971 | case OpMem: | |
41ddf978 | 3972 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
3973 | mem_common: |
3974 | *op = ctxt->memop; | |
3975 | ctxt->memopp = op; | |
3976 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
3977 | fetch_bit_operand(ctxt); |
3978 | op->orig_val = op->val; | |
3979 | break; | |
41ddf978 AK |
3980 | case OpMem64: |
3981 | ctxt->memop.bytes = 8; | |
3982 | goto mem_common; | |
a9945549 AK |
3983 | case OpAcc: |
3984 | op->type = OP_REG; | |
3985 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
dd856efa | 3986 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
a9945549 AK |
3987 | fetch_register_operand(op); |
3988 | op->orig_val = op->val; | |
3989 | break; | |
820207c8 AK |
3990 | case OpAccLo: |
3991 | op->type = OP_REG; | |
3992 | op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; | |
3993 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); | |
3994 | fetch_register_operand(op); | |
3995 | op->orig_val = op->val; | |
3996 | break; | |
3997 | case OpAccHi: | |
3998 | if (ctxt->d & ByteOp) { | |
3999 | op->type = OP_NONE; | |
4000 | break; | |
4001 | } | |
4002 | op->type = OP_REG; | |
4003 | op->bytes = ctxt->op_bytes; | |
4004 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); | |
4005 | fetch_register_operand(op); | |
4006 | op->orig_val = op->val; | |
4007 | break; | |
a9945549 AK |
4008 | case OpDI: |
4009 | op->type = OP_MEM; | |
4010 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4011 | op->addr.mem.ea = | |
dd856efa | 4012 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI)); |
a9945549 AK |
4013 | op->addr.mem.seg = VCPU_SREG_ES; |
4014 | op->val = 0; | |
b3356bf0 | 4015 | op->count = 1; |
a9945549 AK |
4016 | break; |
4017 | case OpDX: | |
4018 | op->type = OP_REG; | |
4019 | op->bytes = 2; | |
dd856efa | 4020 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
a9945549 AK |
4021 | fetch_register_operand(op); |
4022 | break; | |
4dd6a57d AK |
4023 | case OpCL: |
4024 | op->bytes = 1; | |
dd856efa | 4025 | op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; |
4dd6a57d AK |
4026 | break; |
4027 | case OpImmByte: | |
4028 | rc = decode_imm(ctxt, op, 1, true); | |
4029 | break; | |
4030 | case OpOne: | |
4031 | op->bytes = 1; | |
4032 | op->val = 1; | |
4033 | break; | |
4034 | case OpImm: | |
4035 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
4036 | break; | |
5e2c6883 NA |
4037 | case OpImm64: |
4038 | rc = decode_imm(ctxt, op, ctxt->op_bytes, true); | |
4039 | break; | |
28867cee AK |
4040 | case OpMem8: |
4041 | ctxt->memop.bytes = 1; | |
660696d1 GN |
4042 | if (ctxt->memop.type == OP_REG) { |
4043 | ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1); | |
4044 | fetch_register_operand(&ctxt->memop); | |
4045 | } | |
28867cee | 4046 | goto mem_common; |
0fe59128 AK |
4047 | case OpMem16: |
4048 | ctxt->memop.bytes = 2; | |
4049 | goto mem_common; | |
4050 | case OpMem32: | |
4051 | ctxt->memop.bytes = 4; | |
4052 | goto mem_common; | |
4053 | case OpImmU16: | |
4054 | rc = decode_imm(ctxt, op, 2, false); | |
4055 | break; | |
4056 | case OpImmU: | |
4057 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
4058 | break; | |
4059 | case OpSI: | |
4060 | op->type = OP_MEM; | |
4061 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4062 | op->addr.mem.ea = | |
dd856efa | 4063 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI)); |
0fe59128 AK |
4064 | op->addr.mem.seg = seg_override(ctxt); |
4065 | op->val = 0; | |
b3356bf0 | 4066 | op->count = 1; |
0fe59128 | 4067 | break; |
7fa57952 PB |
4068 | case OpXLat: |
4069 | op->type = OP_MEM; | |
4070 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4071 | op->addr.mem.ea = | |
4072 | register_address(ctxt, | |
4073 | reg_read(ctxt, VCPU_REGS_RBX) + | |
4074 | (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); | |
4075 | op->addr.mem.seg = seg_override(ctxt); | |
4076 | op->val = 0; | |
4077 | break; | |
0fe59128 AK |
4078 | case OpImmFAddr: |
4079 | op->type = OP_IMM; | |
4080 | op->addr.mem.ea = ctxt->_eip; | |
4081 | op->bytes = ctxt->op_bytes + 2; | |
4082 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
4083 | break; | |
4084 | case OpMemFAddr: | |
4085 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
4086 | goto mem_common; | |
c191a7a0 AK |
4087 | case OpES: |
4088 | op->val = VCPU_SREG_ES; | |
4089 | break; | |
4090 | case OpCS: | |
4091 | op->val = VCPU_SREG_CS; | |
4092 | break; | |
4093 | case OpSS: | |
4094 | op->val = VCPU_SREG_SS; | |
4095 | break; | |
4096 | case OpDS: | |
4097 | op->val = VCPU_SREG_DS; | |
4098 | break; | |
4099 | case OpFS: | |
4100 | op->val = VCPU_SREG_FS; | |
4101 | break; | |
4102 | case OpGS: | |
4103 | op->val = VCPU_SREG_GS; | |
4104 | break; | |
a9945549 AK |
4105 | case OpImplicit: |
4106 | /* Special instructions do their own operand decoding. */ | |
4107 | default: | |
4108 | op->type = OP_NONE; /* Disable writeback. */ | |
4109 | break; | |
4110 | } | |
4111 | ||
4112 | done: | |
4113 | return rc; | |
4114 | } | |
4115 | ||
ef5d75cc | 4116 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 4117 | { |
dde7e6d1 AK |
4118 | int rc = X86EMUL_CONTINUE; |
4119 | int mode = ctxt->mode; | |
46561646 | 4120 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 4121 | bool op_prefix = false; |
46561646 | 4122 | struct opcode opcode; |
dde7e6d1 | 4123 | |
f09ed83e AK |
4124 | ctxt->memop.type = OP_NONE; |
4125 | ctxt->memopp = NULL; | |
9dac77fa AK |
4126 | ctxt->_eip = ctxt->eip; |
4127 | ctxt->fetch.start = ctxt->_eip; | |
4128 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 4129 | if (insn_len > 0) |
9dac77fa | 4130 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
4131 | |
4132 | switch (mode) { | |
4133 | case X86EMUL_MODE_REAL: | |
4134 | case X86EMUL_MODE_VM86: | |
4135 | case X86EMUL_MODE_PROT16: | |
4136 | def_op_bytes = def_ad_bytes = 2; | |
4137 | break; | |
4138 | case X86EMUL_MODE_PROT32: | |
4139 | def_op_bytes = def_ad_bytes = 4; | |
4140 | break; | |
4141 | #ifdef CONFIG_X86_64 | |
4142 | case X86EMUL_MODE_PROT64: | |
4143 | def_op_bytes = 4; | |
4144 | def_ad_bytes = 8; | |
4145 | break; | |
4146 | #endif | |
4147 | default: | |
1d2887e2 | 4148 | return EMULATION_FAILED; |
dde7e6d1 AK |
4149 | } |
4150 | ||
9dac77fa AK |
4151 | ctxt->op_bytes = def_op_bytes; |
4152 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
4153 | |
4154 | /* Legacy prefixes. */ | |
4155 | for (;;) { | |
e85a1085 | 4156 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 4157 | case 0x66: /* operand-size override */ |
0d7cdee8 | 4158 | op_prefix = true; |
dde7e6d1 | 4159 | /* switch between 2/4 bytes */ |
9dac77fa | 4160 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
4161 | break; |
4162 | case 0x67: /* address-size override */ | |
4163 | if (mode == X86EMUL_MODE_PROT64) | |
4164 | /* switch between 4/8 bytes */ | |
9dac77fa | 4165 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
4166 | else |
4167 | /* switch between 2/4 bytes */ | |
9dac77fa | 4168 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
4169 | break; |
4170 | case 0x26: /* ES override */ | |
4171 | case 0x2e: /* CS override */ | |
4172 | case 0x36: /* SS override */ | |
4173 | case 0x3e: /* DS override */ | |
9dac77fa | 4174 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
4175 | break; |
4176 | case 0x64: /* FS override */ | |
4177 | case 0x65: /* GS override */ | |
9dac77fa | 4178 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
4179 | break; |
4180 | case 0x40 ... 0x4f: /* REX */ | |
4181 | if (mode != X86EMUL_MODE_PROT64) | |
4182 | goto done_prefixes; | |
9dac77fa | 4183 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
4184 | continue; |
4185 | case 0xf0: /* LOCK */ | |
9dac77fa | 4186 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
4187 | break; |
4188 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 4189 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 4190 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
4191 | break; |
4192 | default: | |
4193 | goto done_prefixes; | |
4194 | } | |
4195 | ||
4196 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
4197 | ||
9dac77fa | 4198 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
4199 | } |
4200 | ||
4201 | done_prefixes: | |
4202 | ||
4203 | /* REX prefix. */ | |
9dac77fa AK |
4204 | if (ctxt->rex_prefix & 8) |
4205 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
4206 | |
4207 | /* Opcode byte(s). */ | |
9dac77fa | 4208 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 4209 | /* Two-byte opcode? */ |
9dac77fa AK |
4210 | if (ctxt->b == 0x0f) { |
4211 | ctxt->twobyte = 1; | |
e85a1085 | 4212 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 4213 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 4214 | } |
9dac77fa | 4215 | ctxt->d = opcode.flags; |
dde7e6d1 | 4216 | |
9f4260e7 TY |
4217 | if (ctxt->d & ModRM) |
4218 | ctxt->modrm = insn_fetch(u8, ctxt); | |
4219 | ||
9dac77fa AK |
4220 | while (ctxt->d & GroupMask) { |
4221 | switch (ctxt->d & GroupMask) { | |
46561646 | 4222 | case Group: |
9dac77fa | 4223 | goffset = (ctxt->modrm >> 3) & 7; |
46561646 AK |
4224 | opcode = opcode.u.group[goffset]; |
4225 | break; | |
4226 | case GroupDual: | |
9dac77fa AK |
4227 | goffset = (ctxt->modrm >> 3) & 7; |
4228 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
4229 | opcode = opcode.u.gdual->mod3[goffset]; |
4230 | else | |
4231 | opcode = opcode.u.gdual->mod012[goffset]; | |
4232 | break; | |
4233 | case RMExt: | |
9dac77fa | 4234 | goffset = ctxt->modrm & 7; |
01de8b09 | 4235 | opcode = opcode.u.group[goffset]; |
46561646 AK |
4236 | break; |
4237 | case Prefix: | |
9dac77fa | 4238 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 4239 | return EMULATION_FAILED; |
9dac77fa | 4240 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
4241 | switch (simd_prefix) { |
4242 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
4243 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
4244 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
4245 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
4246 | } | |
4247 | break; | |
045a282c GN |
4248 | case Escape: |
4249 | if (ctxt->modrm > 0xbf) | |
4250 | opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; | |
4251 | else | |
4252 | opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; | |
4253 | break; | |
46561646 | 4254 | default: |
1d2887e2 | 4255 | return EMULATION_FAILED; |
0d7cdee8 | 4256 | } |
46561646 | 4257 | |
b1ea50b2 | 4258 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 4259 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
4260 | } |
4261 | ||
9dac77fa AK |
4262 | ctxt->execute = opcode.u.execute; |
4263 | ctxt->check_perm = opcode.check_perm; | |
4264 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
4265 | |
4266 | /* Unrecognised? */ | |
1146a78b | 4267 | if (ctxt->d == 0 || (ctxt->d & NotImpl)) |
1d2887e2 | 4268 | return EMULATION_FAILED; |
dde7e6d1 | 4269 | |
9dac77fa | 4270 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 4271 | return EMULATION_FAILED; |
d867162c | 4272 | |
9dac77fa AK |
4273 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
4274 | ctxt->op_bytes = 8; | |
dde7e6d1 | 4275 | |
9dac77fa | 4276 | if (ctxt->d & Op3264) { |
7f9b4b75 | 4277 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 4278 | ctxt->op_bytes = 8; |
7f9b4b75 | 4279 | else |
9dac77fa | 4280 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
4281 | } |
4282 | ||
9dac77fa AK |
4283 | if (ctxt->d & Sse) |
4284 | ctxt->op_bytes = 16; | |
cbe2c9d3 AK |
4285 | else if (ctxt->d & Mmx) |
4286 | ctxt->op_bytes = 8; | |
1253791d | 4287 | |
dde7e6d1 | 4288 | /* ModRM and SIB bytes. */ |
9dac77fa | 4289 | if (ctxt->d & ModRM) { |
f09ed83e | 4290 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
4291 | if (!ctxt->has_seg_override) |
4292 | set_seg_override(ctxt, ctxt->modrm_seg); | |
4293 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 4294 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
4295 | if (rc != X86EMUL_CONTINUE) |
4296 | goto done; | |
4297 | ||
9dac77fa AK |
4298 | if (!ctxt->has_seg_override) |
4299 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 4300 | |
f09ed83e | 4301 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 4302 | |
f09ed83e AK |
4303 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
4304 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 4305 | |
dde7e6d1 AK |
4306 | /* |
4307 | * Decode and fetch the source operand: register, memory | |
4308 | * or immediate. | |
4309 | */ | |
0fe59128 | 4310 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
4311 | if (rc != X86EMUL_CONTINUE) |
4312 | goto done; | |
4313 | ||
dde7e6d1 AK |
4314 | /* |
4315 | * Decode and fetch the second source operand: register, memory | |
4316 | * or immediate. | |
4317 | */ | |
4dd6a57d | 4318 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
4319 | if (rc != X86EMUL_CONTINUE) |
4320 | goto done; | |
4321 | ||
dde7e6d1 | 4322 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 4323 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
4324 | |
4325 | done: | |
f09ed83e AK |
4326 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
4327 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 4328 | |
1d2887e2 | 4329 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
4330 | } |
4331 | ||
1cb3f3ae XG |
4332 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
4333 | { | |
4334 | return ctxt->d & PageTable; | |
4335 | } | |
4336 | ||
3e2f65d5 GN |
4337 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
4338 | { | |
3e2f65d5 GN |
4339 | /* The second termination condition only applies for REPE |
4340 | * and REPNE. Test if the repeat string operation prefix is | |
4341 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
4342 | * corresponding termination condition according to: | |
4343 | * - if REPE/REPZ and ZF = 0 then done | |
4344 | * - if REPNE/REPNZ and ZF = 1 then done | |
4345 | */ | |
9dac77fa AK |
4346 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
4347 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
4348 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 4349 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 4350 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
4351 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
4352 | return true; | |
4353 | ||
4354 | return false; | |
4355 | } | |
4356 | ||
cbe2c9d3 AK |
4357 | static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) |
4358 | { | |
4359 | bool fault = false; | |
4360 | ||
4361 | ctxt->ops->get_fpu(ctxt); | |
4362 | asm volatile("1: fwait \n\t" | |
4363 | "2: \n\t" | |
4364 | ".pushsection .fixup,\"ax\" \n\t" | |
4365 | "3: \n\t" | |
4366 | "movb $1, %[fault] \n\t" | |
4367 | "jmp 2b \n\t" | |
4368 | ".popsection \n\t" | |
4369 | _ASM_EXTABLE(1b, 3b) | |
38e8a2dd | 4370 | : [fault]"+qm"(fault)); |
cbe2c9d3 AK |
4371 | ctxt->ops->put_fpu(ctxt); |
4372 | ||
4373 | if (unlikely(fault)) | |
4374 | return emulate_exception(ctxt, MF_VECTOR, 0, false); | |
4375 | ||
4376 | return X86EMUL_CONTINUE; | |
4377 | } | |
4378 | ||
4379 | static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, | |
4380 | struct operand *op) | |
4381 | { | |
4382 | if (op->type == OP_MM) | |
4383 | read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); | |
4384 | } | |
4385 | ||
e28bbd44 AK |
4386 | static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) |
4387 | { | |
4388 | ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; | |
b9fa409b AK |
4389 | if (!(ctxt->d & ByteOp)) |
4390 | fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; | |
e28bbd44 | 4391 | asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" |
b8c0b6ae AK |
4392 | : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), |
4393 | [fastop]"+S"(fop) | |
4394 | : "c"(ctxt->src2.val)); | |
e28bbd44 | 4395 | ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); |
b8c0b6ae AK |
4396 | if (!fop) /* exception is returned in fop variable */ |
4397 | return emulate_de(ctxt); | |
e28bbd44 AK |
4398 | return X86EMUL_CONTINUE; |
4399 | } | |
dd856efa | 4400 | |
7b105ca2 | 4401 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 4402 | { |
0225fb50 | 4403 | const struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 4404 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 4405 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 4406 | |
9dac77fa | 4407 | ctxt->mem_read.pos = 0; |
310b5d30 | 4408 | |
1146a78b GN |
4409 | if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || |
4410 | (ctxt->d & Undefined)) { | |
35d3d4a1 | 4411 | rc = emulate_ud(ctxt); |
1161624f GN |
4412 | goto done; |
4413 | } | |
4414 | ||
d380a5e4 | 4415 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 4416 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 4417 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
4418 | goto done; |
4419 | } | |
4420 | ||
9dac77fa | 4421 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 4422 | rc = emulate_ud(ctxt); |
081bca0e AK |
4423 | goto done; |
4424 | } | |
4425 | ||
cbe2c9d3 AK |
4426 | if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) |
4427 | || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
4428 | rc = emulate_ud(ctxt); |
4429 | goto done; | |
4430 | } | |
4431 | ||
cbe2c9d3 | 4432 | if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
4433 | rc = emulate_nm(ctxt); |
4434 | goto done; | |
4435 | } | |
4436 | ||
cbe2c9d3 AK |
4437 | if (ctxt->d & Mmx) { |
4438 | rc = flush_pending_x87_faults(ctxt); | |
4439 | if (rc != X86EMUL_CONTINUE) | |
4440 | goto done; | |
4441 | /* | |
4442 | * Now that we know the fpu is exception safe, we can fetch | |
4443 | * operands from it. | |
4444 | */ | |
4445 | fetch_possible_mmx_operand(ctxt, &ctxt->src); | |
4446 | fetch_possible_mmx_operand(ctxt, &ctxt->src2); | |
4447 | if (!(ctxt->d & Mov)) | |
4448 | fetch_possible_mmx_operand(ctxt, &ctxt->dst); | |
4449 | } | |
4450 | ||
9dac77fa AK |
4451 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4452 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4453 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
4454 | if (rc != X86EMUL_CONTINUE) |
4455 | goto done; | |
4456 | } | |
4457 | ||
e92805ac | 4458 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 4459 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 4460 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
4461 | goto done; |
4462 | } | |
4463 | ||
8ea7d6ae | 4464 | /* Instruction can only be executed in protected mode */ |
9d1b39a9 | 4465 | if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { |
8ea7d6ae JR |
4466 | rc = emulate_ud(ctxt); |
4467 | goto done; | |
4468 | } | |
4469 | ||
d09beabd | 4470 | /* Do instruction specific permission checks */ |
9dac77fa AK |
4471 | if (ctxt->check_perm) { |
4472 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
4473 | if (rc != X86EMUL_CONTINUE) |
4474 | goto done; | |
4475 | } | |
4476 | ||
9dac77fa AK |
4477 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4478 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4479 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
4480 | if (rc != X86EMUL_CONTINUE) |
4481 | goto done; | |
4482 | } | |
4483 | ||
9dac77fa | 4484 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 4485 | /* All REP prefixes have the same first termination condition */ |
dd856efa | 4486 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { |
9dac77fa | 4487 | ctxt->eip = ctxt->_eip; |
b9fa9d6b AK |
4488 | goto done; |
4489 | } | |
b9fa9d6b AK |
4490 | } |
4491 | ||
9dac77fa AK |
4492 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4493 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4494 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4495 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4496 | goto done; |
9dac77fa | 4497 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4498 | } |
4499 | ||
9dac77fa AK |
4500 | if (ctxt->src2.type == OP_MEM) { |
4501 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4502 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4503 | if (rc != X86EMUL_CONTINUE) |
4504 | goto done; | |
4505 | } | |
4506 | ||
9dac77fa | 4507 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4508 | goto special_insn; |
4509 | ||
4510 | ||
9dac77fa | 4511 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4512 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4513 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4514 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
4515 | if (rc != X86EMUL_CONTINUE) |
4516 | goto done; | |
038e51de | 4517 | } |
9dac77fa | 4518 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 4519 | |
018a98db AK |
4520 | special_insn: |
4521 | ||
9dac77fa AK |
4522 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4523 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4524 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4525 | if (rc != X86EMUL_CONTINUE) |
4526 | goto done; | |
4527 | } | |
4528 | ||
9dac77fa | 4529 | if (ctxt->execute) { |
e28bbd44 AK |
4530 | if (ctxt->d & Fastop) { |
4531 | void (*fop)(struct fastop *) = (void *)ctxt->execute; | |
4532 | rc = fastop(ctxt, fop); | |
4533 | if (rc != X86EMUL_CONTINUE) | |
4534 | goto done; | |
4535 | goto writeback; | |
4536 | } | |
9dac77fa | 4537 | rc = ctxt->execute(ctxt); |
ef65c889 AK |
4538 | if (rc != X86EMUL_CONTINUE) |
4539 | goto done; | |
4540 | goto writeback; | |
4541 | } | |
4542 | ||
9dac77fa | 4543 | if (ctxt->twobyte) |
6aa8b732 AK |
4544 | goto twobyte_insn; |
4545 | ||
9dac77fa | 4546 | switch (ctxt->b) { |
6aa8b732 | 4547 | case 0x63: /* movsxd */ |
8b4caf66 | 4548 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 4549 | goto cannot_emulate; |
9dac77fa | 4550 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 4551 | break; |
b2833e3c | 4552 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
4553 | if (test_cc(ctxt->b, ctxt->eflags)) |
4554 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4555 | break; |
7e0b54b1 | 4556 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 4557 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 4558 | break; |
3d9e77df | 4559 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
dd856efa | 4560 | if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) |
34698d8c | 4561 | break; |
e4f973ae TY |
4562 | rc = em_xchg(ctxt); |
4563 | break; | |
e8b6fa70 | 4564 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
4565 | switch (ctxt->op_bytes) { |
4566 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
4567 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
4568 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
4569 | } |
4570 | break; | |
6e154e56 | 4571 | case 0xcc: /* int3 */ |
5c5df76b TY |
4572 | rc = emulate_int(ctxt, 3); |
4573 | break; | |
6e154e56 | 4574 | case 0xcd: /* int n */ |
9dac77fa | 4575 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
4576 | break; |
4577 | case 0xce: /* into */ | |
5c5df76b TY |
4578 | if (ctxt->eflags & EFLG_OF) |
4579 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 4580 | break; |
1a52e051 | 4581 | case 0xe9: /* jmp rel */ |
db5b0762 | 4582 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
4583 | jmp_rel(ctxt, ctxt->src.val); |
4584 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 4585 | break; |
111de5d6 | 4586 | case 0xf4: /* hlt */ |
6c3287f7 | 4587 | ctxt->ops->halt(ctxt); |
19fdfa0d | 4588 | break; |
111de5d6 AK |
4589 | case 0xf5: /* cmc */ |
4590 | /* complement carry flag from eflags reg */ | |
4591 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
4592 | break; |
4593 | case 0xf8: /* clc */ | |
4594 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 4595 | break; |
8744aa9a MG |
4596 | case 0xf9: /* stc */ |
4597 | ctxt->eflags |= EFLG_CF; | |
4598 | break; | |
fb4616f4 MG |
4599 | case 0xfc: /* cld */ |
4600 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
4601 | break; |
4602 | case 0xfd: /* std */ | |
4603 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 4604 | break; |
91269b8f AK |
4605 | default: |
4606 | goto cannot_emulate; | |
6aa8b732 | 4607 | } |
018a98db | 4608 | |
7d9ddaed AK |
4609 | if (rc != X86EMUL_CONTINUE) |
4610 | goto done; | |
4611 | ||
018a98db | 4612 | writeback: |
fb32b1ed AK |
4613 | if (!(ctxt->d & NoWrite)) { |
4614 | rc = writeback(ctxt, &ctxt->dst); | |
4615 | if (rc != X86EMUL_CONTINUE) | |
4616 | goto done; | |
4617 | } | |
4618 | if (ctxt->d & SrcWrite) { | |
4619 | BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); | |
4620 | rc = writeback(ctxt, &ctxt->src); | |
4621 | if (rc != X86EMUL_CONTINUE) | |
4622 | goto done; | |
4623 | } | |
018a98db | 4624 | |
5cd21917 GN |
4625 | /* |
4626 | * restore dst type in case the decoding will be reused | |
4627 | * (happens for string instruction ) | |
4628 | */ | |
9dac77fa | 4629 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 4630 | |
9dac77fa | 4631 | if ((ctxt->d & SrcMask) == SrcSI) |
f3bd64c6 | 4632 | string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); |
a682e354 | 4633 | |
9dac77fa | 4634 | if ((ctxt->d & DstMask) == DstDI) |
f3bd64c6 | 4635 | string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); |
d9271123 | 4636 | |
9dac77fa | 4637 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b3356bf0 | 4638 | unsigned int count; |
9dac77fa | 4639 | struct read_cache *r = &ctxt->io_read; |
b3356bf0 GN |
4640 | if ((ctxt->d & SrcMask) == SrcSI) |
4641 | count = ctxt->src.count; | |
4642 | else | |
4643 | count = ctxt->dst.count; | |
4644 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), | |
4645 | -count); | |
3e2f65d5 | 4646 | |
d2ddd1c4 GN |
4647 | if (!string_insn_completed(ctxt)) { |
4648 | /* | |
4649 | * Re-enter guest when pio read ahead buffer is empty | |
4650 | * or, if it is not used, after each 1024 iteration. | |
4651 | */ | |
dd856efa | 4652 | if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && |
d2ddd1c4 GN |
4653 | (r->end == 0 || r->end != r->pos)) { |
4654 | /* | |
4655 | * Reset read cache. Usually happens before | |
4656 | * decode, but since instruction is restarted | |
4657 | * we have to do it here. | |
4658 | */ | |
9dac77fa | 4659 | ctxt->mem_read.end = 0; |
dd856efa | 4660 | writeback_registers(ctxt); |
d2ddd1c4 GN |
4661 | return EMULATION_RESTART; |
4662 | } | |
4663 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 4664 | } |
5cd21917 | 4665 | } |
d2ddd1c4 | 4666 | |
9dac77fa | 4667 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4668 | |
4669 | done: | |
da9cb575 AK |
4670 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4671 | ctxt->have_exception = true; | |
775fde86 JR |
4672 | if (rc == X86EMUL_INTERCEPTED) |
4673 | return EMULATION_INTERCEPTED; | |
4674 | ||
dd856efa AK |
4675 | if (rc == X86EMUL_CONTINUE) |
4676 | writeback_registers(ctxt); | |
4677 | ||
d2ddd1c4 | 4678 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4679 | |
4680 | twobyte_insn: | |
9dac77fa | 4681 | switch (ctxt->b) { |
018a98db | 4682 | case 0x09: /* wbinvd */ |
cfb22375 | 4683 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4684 | break; |
4685 | case 0x08: /* invd */ | |
018a98db AK |
4686 | case 0x0d: /* GrpP (prefetch) */ |
4687 | case 0x18: /* Grp16 (prefetch/nop) */ | |
103f98ea | 4688 | case 0x1f: /* nop */ |
018a98db AK |
4689 | break; |
4690 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4691 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4692 | break; |
6aa8b732 | 4693 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4694 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4695 | break; |
6aa8b732 | 4696 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4697 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4698 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4699 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4700 | break; |
b2833e3c | 4701 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4702 | if (test_cc(ctxt->b, ctxt->eflags)) |
4703 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4704 | break; |
ee45b58e | 4705 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4706 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4707 | break; |
2a7c5b8b GC |
4708 | case 0xae: /* clflush */ |
4709 | break; | |
6aa8b732 | 4710 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa | 4711 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4712 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val |
9dac77fa | 4713 | : (u16) ctxt->src.val; |
6aa8b732 | 4714 | break; |
6aa8b732 | 4715 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa | 4716 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4717 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : |
9dac77fa | 4718 | (s16) ctxt->src.val; |
6aa8b732 | 4719 | break; |
a012e65a | 4720 | case 0xc3: /* movnti */ |
9dac77fa AK |
4721 | ctxt->dst.bytes = ctxt->op_bytes; |
4722 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4723 | (u64) ctxt->src.val; | |
a012e65a | 4724 | break; |
91269b8f AK |
4725 | default: |
4726 | goto cannot_emulate; | |
6aa8b732 | 4727 | } |
7d9ddaed AK |
4728 | |
4729 | if (rc != X86EMUL_CONTINUE) | |
4730 | goto done; | |
4731 | ||
6aa8b732 AK |
4732 | goto writeback; |
4733 | ||
4734 | cannot_emulate: | |
a0c0ab2f | 4735 | return EMULATION_FAILED; |
6aa8b732 | 4736 | } |
dd856efa AK |
4737 | |
4738 | void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) | |
4739 | { | |
4740 | invalidate_registers(ctxt); | |
4741 | } | |
4742 | ||
4743 | void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) | |
4744 | { | |
4745 | writeback_registers(ctxt); | |
4746 | } |