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KVM: VMX: Improve error reporting during invalid guest state emulation
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
a9945549
AK		 31/*
32 * Operand types
33 */
b1ea50b2
AK		 34#define OpNone 0ull
35#define OpImplicit 1ull /* No generic decode */
36#define OpReg 2ull /* Register */
37#define OpMem 3ull /* Memory */
38#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
39#define OpDI 5ull /* ES:DI/EDI/RDI */
40#define OpMem64 6ull /* Memory, 64-bit */
41#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
42#define OpDX 8ull /* DX register */
4dd6a57d
AK		 43#define OpCL 9ull /* CL register (for shifts) */
44#define OpImmByte 10ull /* 8-bit sign extended immediate */
45#define OpOne 11ull /* Implied 1 */
46#define OpImm 12ull /* Sign extended immediate */
0fe59128
AK		 47#define OpMem16 13ull /* Memory operand (16-bit). */
48#define OpMem32 14ull /* Memory operand (32-bit). */
49#define OpImmU 15ull /* Immediate operand, zero extended */
50#define OpSI 16ull /* SI/ESI/RSI */
51#define OpImmFAddr 17ull /* Immediate far address */
52#define OpMemFAddr 18ull /* Far address in memory */
53#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 54#define OpES 20ull /* ES */
55#define OpCS 21ull /* CS */
56#define OpSS 22ull /* SS */
57#define OpDS 23ull /* DS */
58#define OpFS 24ull /* FS */
59#define OpGS 25ull /* GS */
28867cee 60#define OpMem8 26ull /* 8-bit zero extended memory operand */
0fe59128
AK		 61
62#define OpBits 5 /* Width of operand field */
b1ea50b2 63#define OpMask ((1ull << OpBits) - 1)
a9945549 64
6aa8b732
AK		 65/*
66 * Opcode effective-address decode tables.
67 * Note that we only emulate instructions that have at least one memory
68 * operand (excluding implicit stack references). We assume that stack
69 * references and instruction fetches will never occur in special memory
70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
71 * not be handled.
72 */
73
74/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 75#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 76/* Destination operand type. */
a9945549
AK		 77#define DstShift 1
78#define ImplicitOps (OpImplicit << DstShift)
79#define DstReg (OpReg << DstShift)
80#define DstMem (OpMem << DstShift)
81#define DstAcc (OpAcc << DstShift)
82#define DstDI (OpDI << DstShift)
83#define DstMem64 (OpMem64 << DstShift)
84#define DstImmUByte (OpImmUByte << DstShift)
85#define DstDX (OpDX << DstShift)
86#define DstMask (OpMask << DstShift)
6aa8b732 87/* Source operand type. */
0fe59128
AK		 88#define SrcShift 6
89#define SrcNone (OpNone << SrcShift)
90#define SrcReg (OpReg << SrcShift)
91#define SrcMem (OpMem << SrcShift)
92#define SrcMem16 (OpMem16 << SrcShift)
93#define SrcMem32 (OpMem32 << SrcShift)
94#define SrcImm (OpImm << SrcShift)
95#define SrcImmByte (OpImmByte << SrcShift)
96#define SrcOne (OpOne << SrcShift)
97#define SrcImmUByte (OpImmUByte << SrcShift)
98#define SrcImmU (OpImmU << SrcShift)
99#define SrcSI (OpSI << SrcShift)
100#define SrcImmFAddr (OpImmFAddr << SrcShift)
101#define SrcMemFAddr (OpMemFAddr << SrcShift)
102#define SrcAcc (OpAcc << SrcShift)
103#define SrcImmU16 (OpImmU16 << SrcShift)
104#define SrcDX (OpDX << SrcShift)
28867cee 105#define SrcMem8 (OpMem8 << SrcShift)
0fe59128 106#define SrcMask (OpMask << SrcShift)
221192bd
MT		 107#define BitOp (1<<11)
108#define MemAbs (1<<12) /* Memory operand is absolute displacement */
109#define String (1<<13) /* String instruction (rep capable) */
110#define Stack (1<<14) /* Stack instruction (push/pop) */
111#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
112#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
113#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
114#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
115#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
116#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 117/* Generic ModRM decode. */
118#define ModRM (1<<19)
119/* Destination is only written; never read. */
120#define Mov (1<<20)
d8769fed 121/* Misc flags */
8ea7d6ae 122#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 123#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 124#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 125#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 126#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 127#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 128#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 129#define No64 (1<<28)
d5ae7ce8 130#define PageTable (1 << 29) /* instruction used to write page table */
0dc8d10f 131/* Source 2 operand type */
d5ae7ce8 132#define Src2Shift (30)
4dd6a57d
AK		 133#define Src2None (OpNone << Src2Shift)
134#define Src2CL (OpCL << Src2Shift)
135#define Src2ImmByte (OpImmByte << Src2Shift)
136#define Src2One (OpOne << Src2Shift)
137#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 138#define Src2ES (OpES << Src2Shift)
139#define Src2CS (OpCS << Src2Shift)
140#define Src2SS (OpSS << Src2Shift)
141#define Src2DS (OpDS << Src2Shift)
142#define Src2FS (OpFS << Src2Shift)
143#define Src2GS (OpGS << Src2Shift)
4dd6a57d 144#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 145#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 146#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
147#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
148#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
6aa8b732 149
d0e53325
AK		 150#define X2(x...) x, x
151#define X3(x...) X2(x), x
152#define X4(x...) X2(x), X2(x)
153#define X5(x...) X4(x), x
154#define X6(x...) X4(x), X2(x)
155#define X7(x...) X4(x), X3(x)
156#define X8(x...) X4(x), X4(x)
157#define X16(x...) X8(x), X8(x)
83babbca 158
d65b1dee 159struct opcode {
b1ea50b2
AK		 160 u64 flags : 56;
161 u64 intercept : 8;
120df890 162 union {
ef65c889 163 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 164 struct opcode *group;
165 struct group_dual *gdual;
0d7cdee8 166 struct gprefix *gprefix;
120df890 167 } u;
d09beabd 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 169};
170
171struct group_dual {
172 struct opcode mod012[8];
173 struct opcode mod3[8];
d65b1dee
AK		 174};
175
0d7cdee8
AK		 176struct gprefix {
177 struct opcode pfx_no;
178 struct opcode pfx_66;
179 struct opcode pfx_f2;
180 struct opcode pfx_f3;
181};
182
6aa8b732 183/* EFLAGS bit definitions. */
d4c6a154
GN		 184#define EFLG_ID (1<<21)
185#define EFLG_VIP (1<<20)
186#define EFLG_VIF (1<<19)
187#define EFLG_AC (1<<18)
b1d86143
AP		 188#define EFLG_VM (1<<17)
189#define EFLG_RF (1<<16)
d4c6a154
GN		 190#define EFLG_IOPL (3<<12)
191#define EFLG_NT (1<<14)
6aa8b732
AK		 192#define EFLG_OF (1<<11)
193#define EFLG_DF (1<<10)
b1d86143 194#define EFLG_IF (1<<9)
d4c6a154 195#define EFLG_TF (1<<8)
6aa8b732
AK		 196#define EFLG_SF (1<<7)
197#define EFLG_ZF (1<<6)
198#define EFLG_AF (1<<4)
199#define EFLG_PF (1<<2)
200#define EFLG_CF (1<<0)
201
62bd430e
MG		 202#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
203#define EFLG_RESERVED_ONE_MASK 2
204
6aa8b732
AK		 205/*
206 * Instruction emulation:
207 * Most instructions are emulated directly via a fragment of inline assembly
208 * code. This allows us to save/restore EFLAGS and thus very easily pick up
209 * any modified flags.
210 */
211
05b3e0c2 212#if defined(CONFIG_X86_64)
6aa8b732
AK		 213#define _LO32 "k" /* force 32-bit operand */
214#define _STK "%%rsp" /* stack pointer */
215#elif defined(__i386__)
216#define _LO32 "" /* force 32-bit operand */
217#define _STK "%%esp" /* stack pointer */
218#endif
219
220/*
221 * These EFLAGS bits are restored from saved value during emulation, and
222 * any changes are written back to the saved value after emulation.
223 */
224#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
225
226/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 227#define _PRE_EFLAGS(_sav, _msk, _tmp) \
228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
229 "movl %"_sav",%"_LO32 _tmp"; " \
230 "push %"_tmp"; " \
231 "push %"_tmp"; " \
232 "movl %"_msk",%"_LO32 _tmp"; " \
233 "andl %"_LO32 _tmp",("_STK"); " \
234 "pushf; " \
235 "notl %"_LO32 _tmp"; " \
236 "andl %"_LO32 _tmp",("_STK"); " \
237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
238 "pop %"_tmp"; " \
239 "orl %"_LO32 _tmp",("_STK"); " \
240 "popf; " \
241 "pop %"_sav"; "
6aa8b732
AK		 242
243/* After executing instruction: write-back necessary bits in EFLAGS. */
244#define _POST_EFLAGS(_sav, _msk, _tmp) \
245 /* _sav |= EFLAGS & _msk; */ \
246 "pushf; " \
247 "pop %"_tmp"; " \
248 "andl %"_msk",%"_LO32 _tmp"; " \
249 "orl %"_LO32 _tmp",%"_sav"; "
250
dda96d8f
AK		 251#ifdef CONFIG_X86_64
252#define ON64(x) x
253#else
254#define ON64(x)
255#endif
256
a31b9cea 257#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 258 do { \
259 __asm__ __volatile__ ( \
260 _PRE_EFLAGS("0", "4", "2") \
261 _op _suffix " %"_x"3,%1; " \
262 _POST_EFLAGS("0", "4", "2") \
a31b9cea
AK		 263 : "=m" ((ctxt)->eflags), \
264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
6b7ad61f 265 "=&r" (_tmp) \
a31b9cea 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
f3fd92fb 267 } while (0)
6b7ad61f
AK		 268
269
6aa8b732 270/* Raw emulation: instruction has two explicit operands. */
a31b9cea 271#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 272 do { \
273 unsigned long _tmp; \
274 \
a31b9cea 275 switch ((ctxt)->dst.bytes) { \
6b7ad61f 276 case 2: \
a31b9cea 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
6b7ad61f
AK		 278 break; \
279 case 4: \
a31b9cea 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
6b7ad61f
AK		 281 break; \
282 case 8: \
a31b9cea 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 284 break; \
285 } \
6aa8b732
AK		 286 } while (0)
287
a31b9cea 288#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
6aa8b732 289 do { \
6b7ad61f 290 unsigned long _tmp; \
a31b9cea 291 switch ((ctxt)->dst.bytes) { \
6aa8b732 292 case 1: \
a31b9cea 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
6aa8b732
AK		 294 break; \
295 default: \
a31b9cea 296 __emulate_2op_nobyte(ctxt, _op, \
6aa8b732
AK		 297 _wx, _wy, _lx, _ly, _qx, _qy); \
298 break; \
299 } \
300 } while (0)
301
302/* Source operand is byte-sized and may be restricted to just %cl. */
a31b9cea
AK		 303#define emulate_2op_SrcB(ctxt, _op) \
304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
6aa8b732
AK		 305
306/* Source operand is byte, word, long or quad sized. */
a31b9cea
AK		 307#define emulate_2op_SrcV(ctxt, _op) \
308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
6aa8b732
AK		 309
310/* Source operand is word, long or quad sized. */
a31b9cea
AK		 311#define emulate_2op_SrcV_nobyte(ctxt, _op) \
312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
6aa8b732 313
d175226a 314/* Instruction has three operands and one operand is stored in ECX register */
29053a60 315#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
7295261c
AK		 316 do { \
317 unsigned long _tmp; \
761441b9
AK		 318 _type _clv = (ctxt)->src2.val; \
319 _type _srcv = (ctxt)->src.val; \
320 _type _dstv = (ctxt)->dst.val; \
7295261c
AK		 321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "5", "2") \
324 _op _suffix " %4,%1 \n" \
325 _POST_EFLAGS("0", "5", "2") \
761441b9 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
7295261c
AK		 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
328 ); \
329 \
761441b9
AK		 330 (ctxt)->src2.val = (unsigned long) _clv; \
331 (ctxt)->src2.val = (unsigned long) _srcv; \
332 (ctxt)->dst.val = (unsigned long) _dstv; \
d175226a
GT		 333 } while (0)
334
761441b9 335#define emulate_2op_cl(ctxt, _op) \
7295261c 336 do { \
761441b9 337 switch ((ctxt)->dst.bytes) { \
7295261c 338 case 2: \
29053a60 339 __emulate_2op_cl(ctxt, _op, "w", u16); \
7295261c
AK		 340 break; \
341 case 4: \
29053a60 342 __emulate_2op_cl(ctxt, _op, "l", u32); \
7295261c
AK		 343 break; \
344 case 8: \
29053a60 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
7295261c
AK		 346 break; \
347 } \
d175226a
GT		 348 } while (0)
349
d1eef45d 350#define __emulate_1op(ctxt, _op, _suffix) \
6aa8b732
AK		 351 do { \
352 unsigned long _tmp; \
353 \
dda96d8f
AK		 354 __asm__ __volatile__ ( \
355 _PRE_EFLAGS("0", "3", "2") \
356 _op _suffix " %1; " \
357 _POST_EFLAGS("0", "3", "2") \
d1eef45d 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
dda96d8f
AK		 359 "=&r" (_tmp) \
360 : "i" (EFLAGS_MASK)); \
361 } while (0)
362
363/* Instruction has only one explicit operand (no source operand). */
d1eef45d 364#define emulate_1op(ctxt, _op) \
dda96d8f 365 do { \
d1eef45d
AK		 366 switch ((ctxt)->dst.bytes) { \
367 case 1: __emulate_1op(ctxt, _op, "b"); break; \
368 case 2: __emulate_1op(ctxt, _op, "w"); break; \
369 case 4: __emulate_1op(ctxt, _op, "l"); break; \
370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
6aa8b732
AK		 371 } \
372 } while (0)
373
e8f2b1d6 374#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
f6b3597b
AK		 375 do { \
376 unsigned long _tmp; \
e8f2b1d6
AK		 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \
378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \
f6b3597b
AK		 379 \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0", "5", "1") \
382 "1: \n\t" \
383 _op _suffix " %6; " \
384 "2: \n\t" \
385 _POST_EFLAGS("0", "5", "1") \
386 ".pushsection .fixup,\"ax\" \n\t" \
387 "3: movb $1, %4 \n\t" \
388 "jmp 2b \n\t" \
389 ".popsection \n\t" \
390 _ASM_EXTABLE(1b, 3b) \
e8f2b1d6
AK		 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \
394 "a" (*rax), "d" (*rdx)); \
f6b3597b
AK		 395 } while (0)
396
3f9f53b0 397/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
e8f2b1d6 398#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
7295261c 399 do { \
e8f2b1d6 400 switch((ctxt)->src.bytes) { \
7295261c 401 case 1: \
e8f2b1d6 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
7295261c
AK		 403 break; \
404 case 2: \
e8f2b1d6 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
7295261c
AK		 406 break; \
407 case 4: \
e8f2b1d6 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
f6b3597b
AK		 409 break; \
410 case 8: ON64( \
e8f2b1d6 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
f6b3597b
AK		 412 break; \
413 } \
414 } while (0)
415
8a76d7f2
JR		 416static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
417 enum x86_intercept intercept,
418 enum x86_intercept_stage stage)
419{
420 struct x86_instruction_info info = {
421 .intercept = intercept,
9dac77fa
AK		 422 .rep_prefix = ctxt->rep_prefix,
423 .modrm_mod = ctxt->modrm_mod,
424 .modrm_reg = ctxt->modrm_reg,
425 .modrm_rm = ctxt->modrm_rm,
426 .src_val = ctxt->src.val64,
427 .src_bytes = ctxt->src.bytes,
428 .dst_bytes = ctxt->dst.bytes,
429 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 430 .next_rip = ctxt->eip,
431 };
432
2953538e 433 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 434}
435
f47cfa31
AK		 436static void assign_masked(ulong *dest, ulong src, ulong mask)
437{
438 *dest = (*dest & ~mask) | (src & mask);
439}
440
9dac77fa 441static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 442{
9dac77fa 443 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 444}
445
f47cfa31
AK		 446static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
447{
448 u16 sel;
449 struct desc_struct ss;
450
451 if (ctxt->mode == X86EMUL_MODE_PROT64)
452 return ~0UL;
453 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
454 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
455}
456
612e89f0
AK		 457static int stack_size(struct x86_emulate_ctxt *ctxt)
458{
459 return (__fls(stack_mask(ctxt)) + 1) >> 3;
460}
461
6aa8b732 462/* Access/update address held in a register, based on addressing mode. */
e4706772 463static inline unsigned long
9dac77fa 464address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 465{
9dac77fa 466 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 467 return reg;
468 else
9dac77fa 469 return reg & ad_mask(ctxt);
e4706772
HH		 470}
471
472static inline unsigned long
9dac77fa 473register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 474{
9dac77fa 475 return address_mask(ctxt, reg);
e4706772
HH		 476}
477
7a957275 478static inline void
9dac77fa 479register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
7a957275 480{
9dac77fa 481 if (ctxt->ad_bytes == sizeof(unsigned long))
7a957275
HH		 482 *reg += inc;
483 else
9dac77fa 484 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
7a957275 485}
6aa8b732 486
9dac77fa 487static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
7a957275 488{
9dac77fa 489 register_address_increment(ctxt, &ctxt->_eip, rel);
7a957275 490}
098c937b 491
56697687
AK		 492static u32 desc_limit_scaled(struct desc_struct *desc)
493{
494 u32 limit = get_desc_limit(desc);
495
496 return desc->g ? (limit << 12) | 0xfff : limit;
497}
498
9dac77fa 499static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df 500{
9dac77fa
AK		 501 ctxt->has_seg_override = true;
502 ctxt->seg_override = seg;
7a5b56df
AK		 503}
504
7b105ca2 505static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 506{
507 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
508 return 0;
509
7b105ca2 510 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 511}
512
9dac77fa 513static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
7a5b56df 514{
9dac77fa 515 if (!ctxt->has_seg_override)
7a5b56df
AK		 516 return 0;
517
9dac77fa 518 return ctxt->seg_override;
7a5b56df
AK		 519}
520
35d3d4a1
AK		 521static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
522 u32 error, bool valid)
54b8486f 523{
da9cb575
AK		 524 ctxt->exception.vector = vec;
525 ctxt->exception.error_code = error;
526 ctxt->exception.error_code_valid = valid;
35d3d4a1 527 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 528}
529
3b88e41a
JR		 530static int emulate_db(struct x86_emulate_ctxt *ctxt)
531{
532 return emulate_exception(ctxt, DB_VECTOR, 0, false);
533}
534
35d3d4a1 535static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 536{
35d3d4a1 537 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 538}
539
618ff15d
AK		 540static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
541{
542 return emulate_exception(ctxt, SS_VECTOR, err, true);
543}
544
35d3d4a1 545static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 546{
35d3d4a1 547 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 548}
549
35d3d4a1 550static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 551{
35d3d4a1 552 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 553}
554
34d1f490
AK		 555static int emulate_de(struct x86_emulate_ctxt *ctxt)
556{
35d3d4a1 557 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 558}
559
1253791d
AK		 560static int emulate_nm(struct x86_emulate_ctxt *ctxt)
561{
562 return emulate_exception(ctxt, NM_VECTOR, 0, false);
563}
564
1aa36616
AK		 565static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
566{
567 u16 selector;
568 struct desc_struct desc;
569
570 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
571 return selector;
572}
573
574static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
575 unsigned seg)
576{
577 u16 dummy;
578 u32 base3;
579 struct desc_struct desc;
580
581 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
582 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
583}
584
1c11b376
AK		 585/*
586 * x86 defines three classes of vector instructions: explicitly
587 * aligned, explicitly unaligned, and the rest, which change behaviour
588 * depending on whether they're AVX encoded or not.
589 *
590 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
591 * subject to the same check.
592 */
593static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
594{
595 if (likely(size < 16))
596 return false;
597
598 if (ctxt->d & Aligned)
599 return true;
600 else if (ctxt->d & Unaligned)
601 return false;
602 else if (ctxt->d & Avx)
603 return false;
604 else
605 return true;
606}
607
3d9b938e 608static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 609 struct segmented_address addr,
3d9b938e 610 unsigned size, bool write, bool fetch,
52fd8b44
AK		 611 ulong *linear)
612{
618ff15d
AK		 613 struct desc_struct desc;
614 bool usable;
52fd8b44 615 ulong la;
618ff15d 616 u32 lim;
1aa36616 617 u16 sel;
618ff15d 618 unsigned cpl, rpl;
52fd8b44 619
7b105ca2 620 la = seg_base(ctxt, addr.seg) + addr.ea;
618ff15d
AK		 621 switch (ctxt->mode) {
622 case X86EMUL_MODE_REAL:
623 break;
624 case X86EMUL_MODE_PROT64:
625 if (((signed long)la << 16) >> 16 != la)
626 return emulate_gp(ctxt, 0);
627 break;
628 default:
1aa36616
AK		 629 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
630 addr.seg);
618ff15d
AK		 631 if (!usable)
632 goto bad;
633 /* code segment or read-only data segment */
634 if (((desc.type & 8) || !(desc.type & 2)) && write)
635 goto bad;
636 /* unreadable code segment */
3d9b938e 637 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 638 goto bad;
639 lim = desc_limit_scaled(&desc);
640 if ((desc.type & 8) || !(desc.type & 4)) {
641 /* expand-up segment */
642 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
643 goto bad;
644 } else {
645 /* exapand-down segment */
646 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
647 goto bad;
648 lim = desc.d ? 0xffffffff : 0xffff;
649 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
650 goto bad;
651 }
717746e3 652 cpl = ctxt->ops->cpl(ctxt);
1aa36616 653 rpl = sel & 3;
618ff15d
AK		 654 cpl = max(cpl, rpl);
655 if (!(desc.type & 8)) {
656 /* data segment */
657 if (cpl > desc.dpl)
658 goto bad;
659 } else if ((desc.type & 8) && !(desc.type & 4)) {
660 /* nonconforming code segment */
661 if (cpl != desc.dpl)
662 goto bad;
663 } else if ((desc.type & 8) && (desc.type & 4)) {
664 /* conforming code segment */
665 if (cpl < desc.dpl)
666 goto bad;
667 }
668 break;
669 }
9dac77fa 670 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
52fd8b44 671 la &= (u32)-1;
1c11b376
AK		 672 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
673 return emulate_gp(ctxt, 0);
52fd8b44
AK		 674 *linear = la;
675 return X86EMUL_CONTINUE;
618ff15d
AK		 676bad:
677 if (addr.seg == VCPU_SREG_SS)
678 return emulate_ss(ctxt, addr.seg);
679 else
680 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 681}
682
3d9b938e
NE		 683static int linearize(struct x86_emulate_ctxt *ctxt,
684 struct segmented_address addr,
685 unsigned size, bool write,
686 ulong *linear)
687{
688 return __linearize(ctxt, addr, size, write, false, linear);
689}
690
691
3ca3ac4d
AK		 692static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
693 struct segmented_address addr,
694 void *data,
695 unsigned size)
696{
9fa088f4
AK		 697 int rc;
698 ulong linear;
699
83b8795a 700 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 701 if (rc != X86EMUL_CONTINUE)
702 return rc;
0f65dd70 703 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 704}
705
807941b1
TY		 706/*
707 * Fetch the next byte of the instruction being emulated which is pointed to
708 * by ctxt->_eip, then increment ctxt->_eip.
709 *
710 * Also prefetch the remaining bytes of the instruction without crossing page
711 * boundary if they are not in fetch_cache yet.
712 */
713static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
62266869 714{
9dac77fa 715 struct fetch_cache *fc = &ctxt->fetch;
62266869 716 int rc;
2fb53ad8 717 int size, cur_size;
62266869 718
807941b1 719 if (ctxt->_eip == fc->end) {
3d9b938e 720 unsigned long linear;
807941b1
TY		 721 struct segmented_address addr = { .seg = VCPU_SREG_CS,
722 .ea = ctxt->_eip };
2fb53ad8 723 cur_size = fc->end - fc->start;
807941b1
TY		 724 size = min(15UL - cur_size,
725 PAGE_SIZE - offset_in_page(ctxt->_eip));
3d9b938e 726 rc = __linearize(ctxt, addr, size, false, true, &linear);
7d88bb48 727 if (unlikely(rc != X86EMUL_CONTINUE))
3d9b938e 728 return rc;
ef5d75cc
TY		 729 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
730 size, &ctxt->exception);
7d88bb48 731 if (unlikely(rc != X86EMUL_CONTINUE))
62266869 732 return rc;
2fb53ad8 733 fc->end += size;
62266869 734 }
807941b1
TY		 735 *dest = fc->data[ctxt->_eip - fc->start];
736 ctxt->_eip++;
3e2815e9 737 return X86EMUL_CONTINUE;
62266869
AK		 738}
739
740static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
807941b1 741 void *dest, unsigned size)
62266869 742{
3e2815e9 743 int rc;
62266869 744
eb3c79e6 745 /* x86 instructions are limited to 15 bytes. */
7d88bb48 746 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
eb3c79e6 747 return X86EMUL_UNHANDLEABLE;
62266869 748 while (size--) {
807941b1 749 rc = do_insn_fetch_byte(ctxt, dest++);
3e2815e9 750 if (rc != X86EMUL_CONTINUE)
62266869
AK		 751 return rc;
752 }
3e2815e9 753 return X86EMUL_CONTINUE;
62266869
AK		 754}
755
67cbc90d 756/* Fetch next part of the instruction being emulated. */
e85a1085 757#define insn_fetch(_type, _ctxt) \
67cbc90d 758({ unsigned long _x; \
e85a1085 759 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
67cbc90d
TY		 760 if (rc != X86EMUL_CONTINUE) \
761 goto done; \
67cbc90d
TY		 762 (_type)_x; \
763})
764
807941b1
TY		 765#define insn_fetch_arr(_arr, _size, _ctxt) \
766({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
67cbc90d
TY		 767 if (rc != X86EMUL_CONTINUE) \
768 goto done; \
67cbc90d
TY		 769})
770
1e3c5cb0
RR		 771/*
772 * Given the 'reg' portion of a ModRM byte, and a register block, return a
773 * pointer into the block that addresses the relevant register.
774 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
775 */
776static void *decode_register(u8 modrm_reg, unsigned long *regs,
777 int highbyte_regs)
6aa8b732
AK		 778{
779 void *p;
780
781 p = &regs[modrm_reg];
782 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
783 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
784 return p;
785}
786
787static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 788 struct segmented_address addr,
6aa8b732
AK		 789 u16 *size, unsigned long *address, int op_bytes)
790{
791 int rc;
792
793 if (op_bytes == 2)
794 op_bytes = 3;
795 *address = 0;
3ca3ac4d 796 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 797 if (rc != X86EMUL_CONTINUE)
6aa8b732 798 return rc;
30b31ab6 799 addr.ea += 2;
3ca3ac4d 800 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 801 return rc;
802}
803
bbe9abbd
NK		 804static int test_cc(unsigned int condition, unsigned int flags)
805{
806 int rc = 0;
807
808 switch ((condition & 15) >> 1) {
809 case 0: /* o */
810 rc |= (flags & EFLG_OF);
811 break;
812 case 1: /* b/c/nae */
813 rc |= (flags & EFLG_CF);
814 break;
815 case 2: /* z/e */
816 rc |= (flags & EFLG_ZF);
817 break;
818 case 3: /* be/na */
819 rc |= (flags & (EFLG_CF|EFLG_ZF));
820 break;
821 case 4: /* s */
822 rc |= (flags & EFLG_SF);
823 break;
824 case 5: /* p/pe */
825 rc |= (flags & EFLG_PF);
826 break;
827 case 7: /* le/ng */
828 rc |= (flags & EFLG_ZF);
829 /* fall through */
830 case 6: /* l/nge */
831 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
832 break;
833 }
834
835 /* Odd condition identifiers (lsb == 1) have inverted sense. */
836 return (!!rc ^ (condition & 1));
837}
838
91ff3cb4
AK		 839static void fetch_register_operand(struct operand *op)
840{
841 switch (op->bytes) {
842 case 1:
843 op->val = *(u8 *)op->addr.reg;
844 break;
845 case 2:
846 op->val = *(u16 *)op->addr.reg;
847 break;
848 case 4:
849 op->val = *(u32 *)op->addr.reg;
850 break;
851 case 8:
852 op->val = *(u64 *)op->addr.reg;
853 break;
854 }
855}
856
1253791d
AK		 857static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
858{
859 ctxt->ops->get_fpu(ctxt);
860 switch (reg) {
861 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
862 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
863 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
864 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
865 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
866 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
867 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
868 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
869#ifdef CONFIG_X86_64
870 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
871 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
872 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
873 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
874 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
875 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
876 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
877 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
878#endif
879 default: BUG();
880 }
881 ctxt->ops->put_fpu(ctxt);
882}
883
884static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
885 int reg)
886{
887 ctxt->ops->get_fpu(ctxt);
888 switch (reg) {
889 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
890 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
891 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
892 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
893 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
894 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
895 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
896 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
897#ifdef CONFIG_X86_64
898 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
899 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
900 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
901 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
902 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
903 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
904 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
905 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
906#endif
907 default: BUG();
908 }
909 ctxt->ops->put_fpu(ctxt);
910}
911
cbe2c9d3
AK		 912static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
913{
914 ctxt->ops->get_fpu(ctxt);
915 switch (reg) {
916 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
917 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
918 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
919 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
920 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
921 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
922 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
923 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
924 default: BUG();
925 }
926 ctxt->ops->put_fpu(ctxt);
927}
928
929static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
930{
931 ctxt->ops->get_fpu(ctxt);
932 switch (reg) {
933 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
934 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
935 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
936 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
937 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
938 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
939 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
940 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
941 default: BUG();
942 }
943 ctxt->ops->put_fpu(ctxt);
944}
945
1253791d 946static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 947 struct operand *op)
3c118e24 948{
9dac77fa
AK		 949 unsigned reg = ctxt->modrm_reg;
950 int highbyte_regs = ctxt->rex_prefix == 0;
33615aa9 951
9dac77fa
AK		 952 if (!(ctxt->d & ModRM))
953 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 954
9dac77fa 955 if (ctxt->d & Sse) {
1253791d
AK		 956 op->type = OP_XMM;
957 op->bytes = 16;
958 op->addr.xmm = reg;
959 read_sse_reg(ctxt, &op->vec_val, reg);
960 return;
961 }
cbe2c9d3
AK		 962 if (ctxt->d & Mmx) {
963 reg &= 7;
964 op->type = OP_MM;
965 op->bytes = 8;
966 op->addr.mm = reg;
967 return;
968 }
1253791d 969
3c118e24 970 op->type = OP_REG;
2adb5ad9 971 if (ctxt->d & ByteOp) {
9dac77fa 972 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
3c118e24
AK		 973 op->bytes = 1;
974 } else {
9dac77fa
AK		 975 op->addr.reg = decode_register(reg, ctxt->regs, 0);
976 op->bytes = ctxt->op_bytes;
3c118e24 977 }
91ff3cb4 978 fetch_register_operand(op);
3c118e24
AK		 979 op->orig_val = op->val;
980}
981
a6e3407b
AK		 982static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
983{
984 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
985 ctxt->modrm_seg = VCPU_SREG_SS;
986}
987
1c73ef66 988static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 989 struct operand *op)
1c73ef66 990{
1c73ef66 991 u8 sib;
f5b4edcd 992 int index_reg = 0, base_reg = 0, scale;
3e2815e9 993 int rc = X86EMUL_CONTINUE;
2dbd0dd7 994 ulong modrm_ea = 0;
1c73ef66 995
9dac77fa
AK		 996 if (ctxt->rex_prefix) {
997 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
998 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
999 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1c73ef66
AK		 1000 }
1001
9dac77fa
AK		 1002 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1003 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1004 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1005 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1006
9dac77fa 1007 if (ctxt->modrm_mod == 3) {
2dbd0dd7 1008 op->type = OP_REG;
9dac77fa
AK		 1009 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1010 op->addr.reg = decode_register(ctxt->modrm_rm,
1011 ctxt->regs, ctxt->d & ByteOp);
1012 if (ctxt->d & Sse) {
1253791d
AK		 1013 op->type = OP_XMM;
1014 op->bytes = 16;
9dac77fa
AK		 1015 op->addr.xmm = ctxt->modrm_rm;
1016 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1017 return rc;
1018 }
cbe2c9d3
AK		 1019 if (ctxt->d & Mmx) {
1020 op->type = OP_MM;
1021 op->bytes = 8;
1022 op->addr.xmm = ctxt->modrm_rm & 7;
1023 return rc;
1024 }
2dbd0dd7 1025 fetch_register_operand(op);
1c73ef66
AK		 1026 return rc;
1027 }
1028
2dbd0dd7
AK		 1029 op->type = OP_MEM;
1030
9dac77fa
AK		 1031 if (ctxt->ad_bytes == 2) {
1032 unsigned bx = ctxt->regs[VCPU_REGS_RBX];
1033 unsigned bp = ctxt->regs[VCPU_REGS_RBP];
1034 unsigned si = ctxt->regs[VCPU_REGS_RSI];
1035 unsigned di = ctxt->regs[VCPU_REGS_RDI];
1c73ef66
AK		 1036
1037 /* 16-bit ModR/M decode. */
9dac77fa 1038 switch (ctxt->modrm_mod) {
1c73ef66 1039 case 0:
9dac77fa 1040 if (ctxt->modrm_rm == 6)
e85a1085 1041 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1042 break;
1043 case 1:
e85a1085 1044 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1045 break;
1046 case 2:
e85a1085 1047 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1048 break;
1049 }
9dac77fa 1050 switch (ctxt->modrm_rm) {
1c73ef66 1051 case 0:
2dbd0dd7 1052 modrm_ea += bx + si;
1c73ef66
AK		 1053 break;
1054 case 1:
2dbd0dd7 1055 modrm_ea += bx + di;
1c73ef66
AK		 1056 break;
1057 case 2:
2dbd0dd7 1058 modrm_ea += bp + si;
1c73ef66
AK		 1059 break;
1060 case 3:
2dbd0dd7 1061 modrm_ea += bp + di;
1c73ef66
AK		 1062 break;
1063 case 4:
2dbd0dd7 1064 modrm_ea += si;
1c73ef66
AK		 1065 break;
1066 case 5:
2dbd0dd7 1067 modrm_ea += di;
1c73ef66
AK		 1068 break;
1069 case 6:
9dac77fa 1070 if (ctxt->modrm_mod != 0)
2dbd0dd7 1071 modrm_ea += bp;
1c73ef66
AK		 1072 break;
1073 case 7:
2dbd0dd7 1074 modrm_ea += bx;
1c73ef66
AK		 1075 break;
1076 }
9dac77fa
AK		 1077 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1078 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1079 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1080 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1081 } else {
1082 /* 32/64-bit ModR/M decode. */
9dac77fa 1083 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1084 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1085 index_reg |= (sib >> 3) & 7;
1086 base_reg |= sib & 7;
1087 scale = sib >> 6;
1088
9dac77fa 1089 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1090 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1091 else {
9dac77fa 1092 modrm_ea += ctxt->regs[base_reg];
a6e3407b
AK		 1093 adjust_modrm_seg(ctxt, base_reg);
1094 }
dc71d0f1 1095 if (index_reg != 4)
9dac77fa
AK		 1096 modrm_ea += ctxt->regs[index_reg] << scale;
1097 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
84411d85 1098 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1099 ctxt->rip_relative = 1;
a6e3407b
AK		 1100 } else {
1101 base_reg = ctxt->modrm_rm;
1102 modrm_ea += ctxt->regs[base_reg];
1103 adjust_modrm_seg(ctxt, base_reg);
1104 }
9dac77fa 1105 switch (ctxt->modrm_mod) {
1c73ef66 1106 case 0:
9dac77fa 1107 if (ctxt->modrm_rm == 5)
e85a1085 1108 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1109 break;
1110 case 1:
e85a1085 1111 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1112 break;
1113 case 2:
e85a1085 1114 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1115 break;
1116 }
1117 }
90de84f5 1118 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1119done:
1120 return rc;
1121}
1122
1123static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1124 struct operand *op)
1c73ef66 1125{
3e2815e9 1126 int rc = X86EMUL_CONTINUE;
1c73ef66 1127
2dbd0dd7 1128 op->type = OP_MEM;
9dac77fa 1129 switch (ctxt->ad_bytes) {
1c73ef66 1130 case 2:
e85a1085 1131 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1132 break;
1133 case 4:
e85a1085 1134 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1135 break;
1136 case 8:
e85a1085 1137 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1138 break;
1139 }
1140done:
1141 return rc;
1142}
1143
9dac77fa 1144static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1145{
7129eeca 1146 long sv = 0, mask;
35c843c4 1147
9dac77fa
AK		 1148 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1149 mask = ~(ctxt->dst.bytes * 8 - 1);
35c843c4 1150
9dac77fa
AK		 1151 if (ctxt->src.bytes == 2)
1152 sv = (s16)ctxt->src.val & (s16)mask;
1153 else if (ctxt->src.bytes == 4)
1154 sv = (s32)ctxt->src.val & (s32)mask;
35c843c4 1155
9dac77fa 1156 ctxt->dst.addr.mem.ea += (sv >> 3);
35c843c4 1157 }
ba7ff2b7
WY		 1158
1159 /* only subword offset */
9dac77fa 1160 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1161}
1162
dde7e6d1 1163static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1164 unsigned long addr, void *dest, unsigned size)
6aa8b732 1165{
dde7e6d1 1166 int rc;
9dac77fa 1167 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1168
dde7e6d1
AK		 1169 while (size) {
1170 int n = min(size, 8u);
1171 size -= n;
1172 if (mc->pos < mc->end)
1173 goto read_cached;
5cd21917 1174
7b105ca2
TY		 1175 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1176 &ctxt->exception);
dde7e6d1
AK		 1177 if (rc != X86EMUL_CONTINUE)
1178 return rc;
1179 mc->end += n;
6aa8b732 1180
dde7e6d1
AK		 1181 read_cached:
1182 memcpy(dest, mc->data + mc->pos, n);
1183 mc->pos += n;
1184 dest += n;
1185 addr += n;
6aa8b732 1186 }
dde7e6d1
AK		 1187 return X86EMUL_CONTINUE;
1188}
6aa8b732 1189
3ca3ac4d
AK		 1190static int segmented_read(struct x86_emulate_ctxt *ctxt,
1191 struct segmented_address addr,
1192 void *data,
1193 unsigned size)
1194{
9fa088f4
AK		 1195 int rc;
1196 ulong linear;
1197
83b8795a 1198 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1199 if (rc != X86EMUL_CONTINUE)
1200 return rc;
7b105ca2 1201 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1202}
1203
1204static int segmented_write(struct x86_emulate_ctxt *ctxt,
1205 struct segmented_address addr,
1206 const void *data,
1207 unsigned size)
1208{
9fa088f4
AK		 1209 int rc;
1210 ulong linear;
1211
83b8795a 1212 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1213 if (rc != X86EMUL_CONTINUE)
1214 return rc;
0f65dd70
AK		 1215 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1216 &ctxt->exception);
3ca3ac4d
AK		 1217}
1218
1219static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1220 struct segmented_address addr,
1221 const void *orig_data, const void *data,
1222 unsigned size)
1223{
9fa088f4
AK		 1224 int rc;
1225 ulong linear;
1226
83b8795a 1227 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1228 if (rc != X86EMUL_CONTINUE)
1229 return rc;
0f65dd70
AK		 1230 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1231 size, &ctxt->exception);
3ca3ac4d
AK		 1232}
1233
dde7e6d1 1234static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1235 unsigned int size, unsigned short port,
1236 void *dest)
1237{
9dac77fa 1238 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1239
dde7e6d1 1240 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1241 unsigned int in_page, n;
9dac77fa
AK		 1242 unsigned int count = ctxt->rep_prefix ?
1243 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
dde7e6d1 1244 in_page = (ctxt->eflags & EFLG_DF) ?
9dac77fa
AK		 1245 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
1246 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
dde7e6d1
AK		 1247 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1248 count);
1249 if (n == 0)
1250 n = 1;
1251 rc->pos = rc->end = 0;
7b105ca2 1252 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1253 return 0;
1254 rc->end = n * size;
6aa8b732
AK		 1255 }
1256
dde7e6d1
AK		 1257 memcpy(dest, rc->data + rc->pos, size);
1258 rc->pos += size;
1259 return 1;
1260}
6aa8b732 1261
7f3d35fd
KW		 1262static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1263 u16 index, struct desc_struct *desc)
1264{
1265 struct desc_ptr dt;
1266 ulong addr;
1267
1268 ctxt->ops->get_idt(ctxt, &dt);
1269
1270 if (dt.size < index * 8 + 7)
1271 return emulate_gp(ctxt, index << 3 | 0x2);
1272
1273 addr = dt.address + index * 8;
1274 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1275 &ctxt->exception);
1276}
1277
dde7e6d1 1278static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1279 u16 selector, struct desc_ptr *dt)
1280{
7b105ca2
TY		 1281 struct x86_emulate_ops *ops = ctxt->ops;
1282
dde7e6d1
AK		 1283 if (selector & 1 << 2) {
1284 struct desc_struct desc;
1aa36616
AK		 1285 u16 sel;
1286
dde7e6d1 1287 memset (dt, 0, sizeof *dt);
1aa36616 1288 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1289 return;
e09d082c 1290
dde7e6d1
AK		 1291 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1292 dt->address = get_desc_base(&desc);
1293 } else
4bff1e86 1294 ops->get_gdt(ctxt, dt);
dde7e6d1 1295}
120df890 1296
dde7e6d1
AK		 1297/* allowed just for 8 bytes segments */
1298static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1299 u16 selector, struct desc_struct *desc)
1300{
1301 struct desc_ptr dt;
1302 u16 index = selector >> 3;
dde7e6d1 1303 ulong addr;
120df890 1304
7b105ca2 1305 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1306
35d3d4a1
AK		 1307 if (dt.size < index * 8 + 7)
1308 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1309
7b105ca2
TY		 1310 addr = dt.address + index * 8;
1311 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1312 &ctxt->exception);
dde7e6d1 1313}
ef65c889 1314
dde7e6d1
AK		 1315/* allowed just for 8 bytes segments */
1316static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1317 u16 selector, struct desc_struct *desc)
1318{
1319 struct desc_ptr dt;
1320 u16 index = selector >> 3;
dde7e6d1 1321 ulong addr;
6aa8b732 1322
7b105ca2 1323 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1324
35d3d4a1
AK		 1325 if (dt.size < index * 8 + 7)
1326 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1327
dde7e6d1 1328 addr = dt.address + index * 8;
7b105ca2
TY		 1329 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1330 &ctxt->exception);
dde7e6d1 1331}
c7e75a3d 1332
5601d05b 1333/* Does not support long mode */
dde7e6d1 1334static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1335 u16 selector, int seg)
1336{
1337 struct desc_struct seg_desc;
1338 u8 dpl, rpl, cpl;
1339 unsigned err_vec = GP_VECTOR;
1340 u32 err_code = 0;
1341 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1342 int ret;
69f55cb1 1343
dde7e6d1 1344 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1345
dde7e6d1
AK		 1346 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1347 || ctxt->mode == X86EMUL_MODE_REAL) {
1348 /* set real mode segment descriptor */
1349 set_desc_base(&seg_desc, selector << 4);
1350 set_desc_limit(&seg_desc, 0xffff);
1351 seg_desc.type = 3;
1352 seg_desc.p = 1;
1353 seg_desc.s = 1;
66b0ab8f
KW		 1354 if (ctxt->mode == X86EMUL_MODE_VM86)
1355 seg_desc.dpl = 3;
dde7e6d1
AK		 1356 goto load;
1357 }
1358
79d5b4c3
AK		 1359 rpl = selector & 3;
1360 cpl = ctxt->ops->cpl(ctxt);
1361
1362 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1363 if ((seg == VCPU_SREG_CS
1364 || (seg == VCPU_SREG_SS
1365 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1366 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1367 && null_selector)
1368 goto exception;
1369
1370 /* TR should be in GDT only */
1371 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1372 goto exception;
1373
1374 if (null_selector) /* for NULL selector skip all following checks */
1375 goto load;
1376
7b105ca2 1377 ret = read_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1378 if (ret != X86EMUL_CONTINUE)
1379 return ret;
1380
1381 err_code = selector & 0xfffc;
1382 err_vec = GP_VECTOR;
1383
1384 /* can't load system descriptor into segment selecor */
1385 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1386 goto exception;
1387
1388 if (!seg_desc.p) {
1389 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1390 goto exception;
1391 }
1392
dde7e6d1 1393 dpl = seg_desc.dpl;
dde7e6d1
AK		 1394
1395 switch (seg) {
1396 case VCPU_SREG_SS:
1397 /*
1398 * segment is not a writable data segment or segment
1399 * selector's RPL != CPL or segment selector's RPL != CPL
1400 */
1401 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1402 goto exception;
6aa8b732 1403 break;
dde7e6d1
AK		 1404 case VCPU_SREG_CS:
1405 if (!(seg_desc.type & 8))
1406 goto exception;
1407
1408 if (seg_desc.type & 4) {
1409 /* conforming */
1410 if (dpl > cpl)
1411 goto exception;
1412 } else {
1413 /* nonconforming */
1414 if (rpl > cpl || dpl != cpl)
1415 goto exception;
1416 }
1417 /* CS(RPL) <- CPL */
1418 selector = (selector & 0xfffc) | cpl;
6aa8b732 1419 break;
dde7e6d1
AK		 1420 case VCPU_SREG_TR:
1421 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1422 goto exception;
1423 break;
1424 case VCPU_SREG_LDTR:
1425 if (seg_desc.s || seg_desc.type != 2)
1426 goto exception;
1427 break;
1428 default: /* DS, ES, FS, or GS */
4e62417b 1429 /*
dde7e6d1
AK		 1430 * segment is not a data or readable code segment or
1431 * ((segment is a data or nonconforming code segment)
1432 * and (both RPL and CPL > DPL))
4e62417b 1433 */
dde7e6d1
AK		 1434 if ((seg_desc.type & 0xa) == 0x8 ||
1435 (((seg_desc.type & 0xc) != 0xc) &&
1436 (rpl > dpl && cpl > dpl)))
1437 goto exception;
6aa8b732 1438 break;
dde7e6d1
AK		 1439 }
1440
1441 if (seg_desc.s) {
1442 /* mark segment as accessed */
1443 seg_desc.type |= 1;
7b105ca2 1444 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
dde7e6d1
AK		 1445 if (ret != X86EMUL_CONTINUE)
1446 return ret;
1447 }
1448load:
7b105ca2 1449 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1450 return X86EMUL_CONTINUE;
1451exception:
1452 emulate_exception(ctxt, err_vec, err_code, true);
1453 return X86EMUL_PROPAGATE_FAULT;
1454}
1455
31be40b3
WY		 1456static void write_register_operand(struct operand *op)
1457{
1458 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1459 switch (op->bytes) {
1460 case 1:
1461 *(u8 *)op->addr.reg = (u8)op->val;
1462 break;
1463 case 2:
1464 *(u16 *)op->addr.reg = (u16)op->val;
1465 break;
1466 case 4:
1467 *op->addr.reg = (u32)op->val;
1468 break; /* 64b: zero-extend */
1469 case 8:
1470 *op->addr.reg = op->val;
1471 break;
1472 }
1473}
1474
adddcecf 1475static int writeback(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1476{
1477 int rc;
dde7e6d1 1478
9dac77fa 1479 switch (ctxt->dst.type) {
dde7e6d1 1480 case OP_REG:
9dac77fa 1481 write_register_operand(&ctxt->dst);
6aa8b732 1482 break;
dde7e6d1 1483 case OP_MEM:
9dac77fa 1484 if (ctxt->lock_prefix)
3ca3ac4d 1485 rc = segmented_cmpxchg(ctxt,
9dac77fa
AK		 1486 ctxt->dst.addr.mem,
1487 &ctxt->dst.orig_val,
1488 &ctxt->dst.val,
1489 ctxt->dst.bytes);
341de7e3 1490 else
3ca3ac4d 1491 rc = segmented_write(ctxt,
9dac77fa
AK		 1492 ctxt->dst.addr.mem,
1493 &ctxt->dst.val,
1494 ctxt->dst.bytes);
dde7e6d1
AK		 1495 if (rc != X86EMUL_CONTINUE)
1496 return rc;
a682e354 1497 break;
1253791d 1498 case OP_XMM:
9dac77fa 1499 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
1253791d 1500 break;
cbe2c9d3
AK		 1501 case OP_MM:
1502 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
1503 break;
dde7e6d1
AK		 1504 case OP_NONE:
1505 /* no writeback */
414e6277 1506 break;
dde7e6d1 1507 default:
414e6277 1508 break;
6aa8b732 1509 }
dde7e6d1
AK		 1510 return X86EMUL_CONTINUE;
1511}
6aa8b732 1512
51ddff50 1513static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1514{
4179bb02 1515 struct segmented_address addr;
0dc8d10f 1516
51ddff50 1517 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -bytes);
9dac77fa 1518 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
4179bb02
TY		 1519 addr.seg = VCPU_SREG_SS;
1520
51ddff50
AK		 1521 return segmented_write(ctxt, addr, data, bytes);
1522}
1523
1524static int em_push(struct x86_emulate_ctxt *ctxt)
1525{
4179bb02 1526 /* Disable writeback. */
9dac77fa 1527 ctxt->dst.type = OP_NONE;
51ddff50 1528 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1529}
69f55cb1 1530
dde7e6d1 1531static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1532 void *dest, int len)
1533{
dde7e6d1 1534 int rc;
90de84f5 1535 struct segmented_address addr;
8b4caf66 1536
9dac77fa 1537 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
90de84f5 1538 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1539 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1540 if (rc != X86EMUL_CONTINUE)
1541 return rc;
1542
9dac77fa 1543 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
dde7e6d1 1544 return rc;
8b4caf66
LV		 1545}
1546
c54fe504
TY		 1547static int em_pop(struct x86_emulate_ctxt *ctxt)
1548{
9dac77fa 1549 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1550}
1551
dde7e6d1 1552static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1553 void *dest, int len)
9de41573
GN		 1554{
1555 int rc;
dde7e6d1
AK		 1556 unsigned long val, change_mask;
1557 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1558 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1559
3b9be3bf 1560 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1561 if (rc != X86EMUL_CONTINUE)
1562 return rc;
9de41573 1563
dde7e6d1
AK		 1564 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1565 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1566
dde7e6d1
AK		 1567 switch(ctxt->mode) {
1568 case X86EMUL_MODE_PROT64:
1569 case X86EMUL_MODE_PROT32:
1570 case X86EMUL_MODE_PROT16:
1571 if (cpl == 0)
1572 change_mask |= EFLG_IOPL;
1573 if (cpl <= iopl)
1574 change_mask |= EFLG_IF;
1575 break;
1576 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1577 if (iopl < 3)
1578 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1579 change_mask |= EFLG_IF;
1580 break;
1581 default: /* real mode */
1582 change_mask |= (EFLG_IOPL | EFLG_IF);
1583 break;
9de41573 1584 }
dde7e6d1
AK		 1585
1586 *(unsigned long *)dest =
1587 (ctxt->eflags & ~change_mask) | (val & change_mask);
1588
1589 return rc;
9de41573
GN		 1590}
1591
62aaa2f0
TY		 1592static int em_popf(struct x86_emulate_ctxt *ctxt)
1593{
9dac77fa
AK		 1594 ctxt->dst.type = OP_REG;
1595 ctxt->dst.addr.reg = &ctxt->eflags;
1596 ctxt->dst.bytes = ctxt->op_bytes;
1597 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1598}
1599
612e89f0
AK		 1600static int em_enter(struct x86_emulate_ctxt *ctxt)
1601{
1602 int rc;
1603 unsigned frame_size = ctxt->src.val;
1604 unsigned nesting_level = ctxt->src2.val & 31;
1605
1606 if (nesting_level)
1607 return X86EMUL_UNHANDLEABLE;
1608
1609 rc = push(ctxt, &ctxt->regs[VCPU_REGS_RBP], stack_size(ctxt));
1610 if (rc != X86EMUL_CONTINUE)
1611 return rc;
1612 assign_masked(&ctxt->regs[VCPU_REGS_RBP], ctxt->regs[VCPU_REGS_RSP],
1613 stack_mask(ctxt));
1614 assign_masked(&ctxt->regs[VCPU_REGS_RSP],
1615 ctxt->regs[VCPU_REGS_RSP] - frame_size,
1616 stack_mask(ctxt));
1617 return X86EMUL_CONTINUE;
1618}
1619
f47cfa31
AK		 1620static int em_leave(struct x86_emulate_ctxt *ctxt)
1621{
1622 assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
1623 stack_mask(ctxt));
1624 return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
1625}
1626
1cd196ea 1627static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1628{
1cd196ea
AK		 1629 int seg = ctxt->src2.val;
1630
9dac77fa 1631 ctxt->src.val = get_segment_selector(ctxt, seg);
7b262e90 1632
4487b3b4 1633 return em_push(ctxt);
7b262e90
GN		 1634}
1635
1cd196ea 1636static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1637{
1cd196ea 1638 int seg = ctxt->src2.val;
dde7e6d1
AK		 1639 unsigned long selector;
1640 int rc;
38ba30ba 1641
9dac77fa 1642 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
dde7e6d1
AK		 1643 if (rc != X86EMUL_CONTINUE)
1644 return rc;
1645
7b105ca2 1646 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1647 return rc;
38ba30ba
GN		 1648}
1649
b96a7fad 1650static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1651{
9dac77fa 1652 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
dde7e6d1
AK		 1653 int rc = X86EMUL_CONTINUE;
1654 int reg = VCPU_REGS_RAX;
38ba30ba 1655
dde7e6d1
AK		 1656 while (reg <= VCPU_REGS_RDI) {
1657 (reg == VCPU_REGS_RSP) ?
9dac77fa 1658 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
38ba30ba 1659
4487b3b4 1660 rc = em_push(ctxt);
dde7e6d1
AK		 1661 if (rc != X86EMUL_CONTINUE)
1662 return rc;
38ba30ba 1663
dde7e6d1 1664 ++reg;
38ba30ba 1665 }
38ba30ba 1666
dde7e6d1 1667 return rc;
38ba30ba
GN		 1668}
1669
62aaa2f0
TY		 1670static int em_pushf(struct x86_emulate_ctxt *ctxt)
1671{
9dac77fa 1672 ctxt->src.val = (unsigned long)ctxt->eflags;
62aaa2f0
TY		 1673 return em_push(ctxt);
1674}
1675
b96a7fad 1676static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1677{
dde7e6d1
AK		 1678 int rc = X86EMUL_CONTINUE;
1679 int reg = VCPU_REGS_RDI;
38ba30ba 1680
dde7e6d1
AK		 1681 while (reg >= VCPU_REGS_RAX) {
1682 if (reg == VCPU_REGS_RSP) {
9dac77fa
AK		 1683 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
1684 ctxt->op_bytes);
dde7e6d1
AK		 1685 --reg;
1686 }
38ba30ba 1687
9dac77fa 1688 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
dde7e6d1
AK		 1689 if (rc != X86EMUL_CONTINUE)
1690 break;
1691 --reg;
38ba30ba 1692 }
dde7e6d1 1693 return rc;
38ba30ba
GN		 1694}
1695
7b105ca2 1696int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1697{
7b105ca2 1698 struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1699 int rc;
6e154e56
MG		 1700 struct desc_ptr dt;
1701 gva_t cs_addr;
1702 gva_t eip_addr;
1703 u16 cs, eip;
6e154e56
MG		 1704
1705 /* TODO: Add limit checks */
9dac77fa 1706 ctxt->src.val = ctxt->eflags;
4487b3b4 1707 rc = em_push(ctxt);
5c56e1cf
AK		 1708 if (rc != X86EMUL_CONTINUE)
1709 return rc;
6e154e56
MG		 1710
1711 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1712
9dac77fa 1713 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1714 rc = em_push(ctxt);
5c56e1cf
AK		 1715 if (rc != X86EMUL_CONTINUE)
1716 return rc;
6e154e56 1717
9dac77fa 1718 ctxt->src.val = ctxt->_eip;
4487b3b4 1719 rc = em_push(ctxt);
5c56e1cf
AK		 1720 if (rc != X86EMUL_CONTINUE)
1721 return rc;
1722
4bff1e86 1723 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1724
1725 eip_addr = dt.address + (irq << 2);
1726 cs_addr = dt.address + (irq << 2) + 2;
1727
0f65dd70 1728 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1729 if (rc != X86EMUL_CONTINUE)
1730 return rc;
1731
0f65dd70 1732 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1733 if (rc != X86EMUL_CONTINUE)
1734 return rc;
1735
7b105ca2 1736 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1737 if (rc != X86EMUL_CONTINUE)
1738 return rc;
1739
9dac77fa 1740 ctxt->_eip = eip;
6e154e56
MG		 1741
1742 return rc;
1743}
1744
7b105ca2 1745static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1746{
1747 switch(ctxt->mode) {
1748 case X86EMUL_MODE_REAL:
7b105ca2 1749 return emulate_int_real(ctxt, irq);
6e154e56
MG		 1750 case X86EMUL_MODE_VM86:
1751 case X86EMUL_MODE_PROT16:
1752 case X86EMUL_MODE_PROT32:
1753 case X86EMUL_MODE_PROT64:
1754 default:
1755 /* Protected mode interrupts unimplemented yet */
1756 return X86EMUL_UNHANDLEABLE;
1757 }
1758}
1759
7b105ca2 1760static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1761{
dde7e6d1
AK		 1762 int rc = X86EMUL_CONTINUE;
1763 unsigned long temp_eip = 0;
1764 unsigned long temp_eflags = 0;
1765 unsigned long cs = 0;
1766 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1767 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1768 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1769 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1770
dde7e6d1 1771 /* TODO: Add stack limit check */
38ba30ba 1772
9dac77fa 1773 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1774
dde7e6d1
AK		 1775 if (rc != X86EMUL_CONTINUE)
1776 return rc;
38ba30ba 1777
35d3d4a1
AK		 1778 if (temp_eip & ~0xffff)
1779 return emulate_gp(ctxt, 0);
38ba30ba 1780
9dac77fa 1781 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 1782
dde7e6d1
AK		 1783 if (rc != X86EMUL_CONTINUE)
1784 return rc;
38ba30ba 1785
9dac77fa 1786 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 1787
dde7e6d1
AK		 1788 if (rc != X86EMUL_CONTINUE)
1789 return rc;
38ba30ba 1790
7b105ca2 1791 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 1792
dde7e6d1
AK		 1793 if (rc != X86EMUL_CONTINUE)
1794 return rc;
38ba30ba 1795
9dac77fa 1796 ctxt->_eip = temp_eip;
38ba30ba 1797
38ba30ba 1798
9dac77fa 1799 if (ctxt->op_bytes == 4)
dde7e6d1 1800 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 1801 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 1802 ctxt->eflags &= ~0xffff;
1803 ctxt->eflags |= temp_eflags;
38ba30ba 1804 }
dde7e6d1
AK		 1805
1806 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1807 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1808
1809 return rc;
38ba30ba
GN		 1810}
1811
e01991e7 1812static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 1813{
dde7e6d1
AK		 1814 switch(ctxt->mode) {
1815 case X86EMUL_MODE_REAL:
7b105ca2 1816 return emulate_iret_real(ctxt);
dde7e6d1
AK		 1817 case X86EMUL_MODE_VM86:
1818 case X86EMUL_MODE_PROT16:
1819 case X86EMUL_MODE_PROT32:
1820 case X86EMUL_MODE_PROT64:
c37eda13 1821 default:
dde7e6d1
AK		 1822 /* iret from protected mode unimplemented yet */
1823 return X86EMUL_UNHANDLEABLE;
c37eda13 1824 }
c37eda13
WY		 1825}
1826
d2f62766
TY		 1827static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1828{
d2f62766
TY		 1829 int rc;
1830 unsigned short sel;
1831
9dac77fa 1832 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 1833
7b105ca2 1834 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
d2f62766
TY		 1835 if (rc != X86EMUL_CONTINUE)
1836 return rc;
1837
9dac77fa
AK		 1838 ctxt->_eip = 0;
1839 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
d2f62766
TY		 1840 return X86EMUL_CONTINUE;
1841}
1842
51187683 1843static int em_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1844{
9dac77fa 1845 switch (ctxt->modrm_reg) {
8cdbd2c9 1846 case 0: /* rol */
a31b9cea 1847 emulate_2op_SrcB(ctxt, "rol");
8cdbd2c9
LV		 1848 break;
1849 case 1: /* ror */
a31b9cea 1850 emulate_2op_SrcB(ctxt, "ror");
8cdbd2c9
LV		 1851 break;
1852 case 2: /* rcl */
a31b9cea 1853 emulate_2op_SrcB(ctxt, "rcl");
8cdbd2c9
LV		 1854 break;
1855 case 3: /* rcr */
a31b9cea 1856 emulate_2op_SrcB(ctxt, "rcr");
8cdbd2c9
LV		 1857 break;
1858 case 4: /* sal/shl */
1859 case 6: /* sal/shl */
a31b9cea 1860 emulate_2op_SrcB(ctxt, "sal");
8cdbd2c9
LV		 1861 break;
1862 case 5: /* shr */
a31b9cea 1863 emulate_2op_SrcB(ctxt, "shr");
8cdbd2c9
LV		 1864 break;
1865 case 7: /* sar */
a31b9cea 1866 emulate_2op_SrcB(ctxt, "sar");
8cdbd2c9
LV		 1867 break;
1868 }
51187683 1869 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1870}
1871
3329ece1
AK		 1872static int em_not(struct x86_emulate_ctxt *ctxt)
1873{
1874 ctxt->dst.val = ~ctxt->dst.val;
1875 return X86EMUL_CONTINUE;
1876}
1877
1878static int em_neg(struct x86_emulate_ctxt *ctxt)
1879{
1880 emulate_1op(ctxt, "neg");
1881 return X86EMUL_CONTINUE;
1882}
1883
1884static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
1885{
1886 u8 ex = 0;
1887
1888 emulate_1op_rax_rdx(ctxt, "mul", ex);
1889 return X86EMUL_CONTINUE;
1890}
1891
1892static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
1893{
1894 u8 ex = 0;
1895
1896 emulate_1op_rax_rdx(ctxt, "imul", ex);
1897 return X86EMUL_CONTINUE;
1898}
1899
1900static int em_div_ex(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1901{
34d1f490 1902 u8 de = 0;
8cdbd2c9 1903
3329ece1
AK		 1904 emulate_1op_rax_rdx(ctxt, "div", de);
1905 if (de)
1906 return emulate_de(ctxt);
1907 return X86EMUL_CONTINUE;
1908}
1909
1910static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
1911{
1912 u8 de = 0;
1913
1914 emulate_1op_rax_rdx(ctxt, "idiv", de);
34d1f490
AK		 1915 if (de)
1916 return emulate_de(ctxt);
8c5eee30 1917 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1918}
1919
51187683 1920static int em_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1921{
4179bb02 1922 int rc = X86EMUL_CONTINUE;
8cdbd2c9 1923
9dac77fa 1924 switch (ctxt->modrm_reg) {
8cdbd2c9 1925 case 0: /* inc */
d1eef45d 1926 emulate_1op(ctxt, "inc");
8cdbd2c9
LV		 1927 break;
1928 case 1: /* dec */
d1eef45d 1929 emulate_1op(ctxt, "dec");
8cdbd2c9 1930 break;
d19292e4
MG		 1931 case 2: /* call near abs */ {
1932 long int old_eip;
9dac77fa
AK		 1933 old_eip = ctxt->_eip;
1934 ctxt->_eip = ctxt->src.val;
1935 ctxt->src.val = old_eip;
4487b3b4 1936 rc = em_push(ctxt);
d19292e4
MG		 1937 break;
1938 }
8cdbd2c9 1939 case 4: /* jmp abs */
9dac77fa 1940 ctxt->_eip = ctxt->src.val;
8cdbd2c9 1941 break;
d2f62766
TY		 1942 case 5: /* jmp far */
1943 rc = em_jmp_far(ctxt);
1944 break;
8cdbd2c9 1945 case 6: /* push */
4487b3b4 1946 rc = em_push(ctxt);
8cdbd2c9 1947 break;
8cdbd2c9 1948 }
4179bb02 1949 return rc;
8cdbd2c9
LV		 1950}
1951
e0dac408 1952static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1953{
9dac77fa 1954 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 1955
9dac77fa
AK		 1956 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
1957 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
1958 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1959 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1960 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1961 } else {
9dac77fa
AK		 1962 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
1963 (u32) ctxt->regs[VCPU_REGS_RBX];
8cdbd2c9 1964
05f086f8 1965 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1966 }
1b30eaa8 1967 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1968}
1969
ebda02c2
TY		 1970static int em_ret(struct x86_emulate_ctxt *ctxt)
1971{
9dac77fa
AK		 1972 ctxt->dst.type = OP_REG;
1973 ctxt->dst.addr.reg = &ctxt->_eip;
1974 ctxt->dst.bytes = ctxt->op_bytes;
ebda02c2
TY		 1975 return em_pop(ctxt);
1976}
1977
e01991e7 1978static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 1979{
a77ab5ea
AK		 1980 int rc;
1981 unsigned long cs;
1982
9dac77fa 1983 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1b30eaa8 1984 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1985 return rc;
9dac77fa
AK		 1986 if (ctxt->op_bytes == 4)
1987 ctxt->_eip = (u32)ctxt->_eip;
1988 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 1989 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1990 return rc;
7b105ca2 1991 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1992 return rc;
1993}
1994
e940b5c2
TY		 1995static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
1996{
1997 /* Save real source value, then compare EAX against destination. */
1998 ctxt->src.orig_val = ctxt->src.val;
1999 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
2000 emulate_2op_SrcV(ctxt, "cmp");
2001
2002 if (ctxt->eflags & EFLG_ZF) {
2003 /* Success: write back to memory. */
2004 ctxt->dst.val = ctxt->src.orig_val;
2005 } else {
2006 /* Failure: write the value we saw to EAX. */
2007 ctxt->dst.type = OP_REG;
2008 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
2009 }
2010 return X86EMUL_CONTINUE;
2011}
2012
d4b4325f 2013static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2014{
d4b4325f 2015 int seg = ctxt->src2.val;
09b5f4d3
WY		 2016 unsigned short sel;
2017 int rc;
2018
9dac77fa 2019 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2020
7b105ca2 2021 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2022 if (rc != X86EMUL_CONTINUE)
2023 return rc;
2024
9dac77fa 2025 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2026 return rc;
2027}
2028
7b105ca2 2029static void
e66bb2cc 2030setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2031 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2032{
1aa36616
AK		 2033 u16 selector;
2034
79168fd1 2035 memset(cs, 0, sizeof(struct desc_struct));
7b105ca2 2036 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 2037 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 2038
2039 cs->l = 0; /* will be adjusted later */
79168fd1 2040 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2041 cs->g = 1; /* 4kb granularity */
79168fd1 2042 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2043 cs->type = 0x0b; /* Read, Execute, Accessed */
2044 cs->s = 1;
2045 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2046 cs->p = 1;
2047 cs->d = 1;
e66bb2cc 2048
79168fd1
GN		 2049 set_desc_base(ss, 0); /* flat segment */
2050 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2051 ss->g = 1; /* 4kb granularity */
2052 ss->s = 1;
2053 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2054 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2055 ss->dpl = 0;
79168fd1 2056 ss->p = 1;
e66bb2cc
AP		 2057}
2058
1a18a69b
AK		 2059static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2060{
2061 u32 eax, ebx, ecx, edx;
2062
2063 eax = ecx = 0;
0017f93a
AK		 2064 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2065 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2066 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2067 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2068}
2069
c2226fc9
SB		 2070static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2071{
2072 struct x86_emulate_ops *ops = ctxt->ops;
2073 u32 eax, ebx, ecx, edx;
2074
2075 /*
2076 * syscall should always be enabled in longmode - so only become
2077 * vendor specific (cpuid) if other modes are active...
2078 */
2079 if (ctxt->mode == X86EMUL_MODE_PROT64)
2080 return true;
2081
2082 eax = 0x00000000;
2083 ecx = 0x00000000;
0017f93a
AK		 2084 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2085 /*
2086 * Intel ("GenuineIntel")
2087 * remark: Intel CPUs only support "syscall" in 64bit
2088 * longmode. Also an 64bit guest with a
2089 * 32bit compat-app running will #UD !! While this
2090 * behaviour can be fixed (by emulating) into AMD
2091 * response - CPUs of AMD can't behave like Intel.
2092 */
2093 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2094 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2095 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2096 return false;
2097
2098 /* AMD ("AuthenticAMD") */
2099 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2100 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2101 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2102 return true;
2103
2104 /* AMD ("AMDisbetter!") */
2105 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2106 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2107 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2108 return true;
c2226fc9
SB		 2109
2110 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2111 return false;
2112}
2113
e01991e7 2114static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2115{
7b105ca2 2116 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2117 struct desc_struct cs, ss;
e66bb2cc 2118 u64 msr_data;
79168fd1 2119 u16 cs_sel, ss_sel;
c2ad2bb3 2120 u64 efer = 0;
e66bb2cc
AP		 2121
2122 /* syscall is not available in real mode */
2e901c4c 2123 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2124 ctxt->mode == X86EMUL_MODE_VM86)
2125 return emulate_ud(ctxt);
e66bb2cc 2126
c2226fc9
SB		 2127 if (!(em_syscall_is_enabled(ctxt)))
2128 return emulate_ud(ctxt);
2129
c2ad2bb3 2130 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2131 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2132
c2226fc9
SB		 2133 if (!(efer & EFER_SCE))
2134 return emulate_ud(ctxt);
2135
717746e3 2136 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2137 msr_data >>= 32;
79168fd1
GN		 2138 cs_sel = (u16)(msr_data & 0xfffc);
2139 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2140
c2ad2bb3 2141 if (efer & EFER_LMA) {
79168fd1 2142 cs.d = 0;
e66bb2cc
AP		 2143 cs.l = 1;
2144 }
1aa36616
AK		 2145 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2146 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2147
9dac77fa 2148 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
c2ad2bb3 2149 if (efer & EFER_LMA) {
e66bb2cc 2150#ifdef CONFIG_X86_64
9dac77fa 2151 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
e66bb2cc 2152
717746e3 2153 ops->get_msr(ctxt,
3fb1b5db
GN		 2154 ctxt->mode == X86EMUL_MODE_PROT64 ?
2155 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2156 ctxt->_eip = msr_data;
e66bb2cc 2157
717746e3 2158 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 2159 ctxt->eflags &= ~(msr_data | EFLG_RF);
2160#endif
2161 } else {
2162 /* legacy mode */
717746e3 2163 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2164 ctxt->_eip = (u32)msr_data;
e66bb2cc
AP		 2165
2166 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2167 }
2168
e54cfa97 2169 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2170}
2171
e01991e7 2172static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2173{
7b105ca2 2174 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2175 struct desc_struct cs, ss;
8c604352 2176 u64 msr_data;
79168fd1 2177 u16 cs_sel, ss_sel;
c2ad2bb3 2178 u64 efer = 0;
8c604352 2179
7b105ca2 2180 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2181 /* inject #GP if in real mode */
35d3d4a1
AK		 2182 if (ctxt->mode == X86EMUL_MODE_REAL)
2183 return emulate_gp(ctxt, 0);
8c604352 2184
1a18a69b
AK		 2185 /*
2186 * Not recognized on AMD in compat mode (but is recognized in legacy
2187 * mode).
2188 */
2189 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2190 && !vendor_intel(ctxt))
2191 return emulate_ud(ctxt);
2192
8c604352
AP		 2193 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2194 * Therefore, we inject an #UD.
2195 */
35d3d4a1
AK		 2196 if (ctxt->mode == X86EMUL_MODE_PROT64)
2197 return emulate_ud(ctxt);
8c604352 2198
7b105ca2 2199 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2200
717746e3 2201 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2202 switch (ctxt->mode) {
2203 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2204 if ((msr_data & 0xfffc) == 0x0)
2205 return emulate_gp(ctxt, 0);
8c604352
AP		 2206 break;
2207 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2208 if (msr_data == 0x0)
2209 return emulate_gp(ctxt, 0);
8c604352
AP		 2210 break;
2211 }
2212
2213 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 2214 cs_sel = (u16)msr_data;
2215 cs_sel &= ~SELECTOR_RPL_MASK;
2216 ss_sel = cs_sel + 8;
2217 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2218 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2219 cs.d = 0;
8c604352
AP		 2220 cs.l = 1;
2221 }
2222
1aa36616
AK		 2223 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2224 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2225
717746e3 2226 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2227 ctxt->_eip = msr_data;
8c604352 2228
717746e3 2229 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
9dac77fa 2230 ctxt->regs[VCPU_REGS_RSP] = msr_data;
8c604352 2231
e54cfa97 2232 return X86EMUL_CONTINUE;
8c604352
AP		 2233}
2234
e01991e7 2235static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2236{
7b105ca2 2237 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2238 struct desc_struct cs, ss;
4668f050
AP		 2239 u64 msr_data;
2240 int usermode;
1249b96e 2241 u16 cs_sel = 0, ss_sel = 0;
4668f050 2242
a0044755
GN		 2243 /* inject #GP if in real mode or Virtual 8086 mode */
2244 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2245 ctxt->mode == X86EMUL_MODE_VM86)
2246 return emulate_gp(ctxt, 0);
4668f050 2247
7b105ca2 2248 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2249
9dac77fa 2250 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2251 usermode = X86EMUL_MODE_PROT64;
2252 else
2253 usermode = X86EMUL_MODE_PROT32;
2254
2255 cs.dpl = 3;
2256 ss.dpl = 3;
717746e3 2257 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2258 switch (usermode) {
2259 case X86EMUL_MODE_PROT32:
79168fd1 2260 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2261 if ((msr_data & 0xfffc) == 0x0)
2262 return emulate_gp(ctxt, 0);
79168fd1 2263 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2264 break;
2265 case X86EMUL_MODE_PROT64:
79168fd1 2266 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2267 if (msr_data == 0x0)
2268 return emulate_gp(ctxt, 0);
79168fd1
GN		 2269 ss_sel = cs_sel + 8;
2270 cs.d = 0;
4668f050
AP		 2271 cs.l = 1;
2272 break;
2273 }
79168fd1
GN		 2274 cs_sel |= SELECTOR_RPL_MASK;
2275 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2276
1aa36616
AK		 2277 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2278 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2279
9dac77fa
AK		 2280 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
2281 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
4668f050 2282
e54cfa97 2283 return X86EMUL_CONTINUE;
4668f050
AP		 2284}
2285
7b105ca2 2286static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2287{
2288 int iopl;
2289 if (ctxt->mode == X86EMUL_MODE_REAL)
2290 return false;
2291 if (ctxt->mode == X86EMUL_MODE_VM86)
2292 return true;
2293 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2294 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2295}
2296
2297static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2298 u16 port, u16 len)
2299{
7b105ca2 2300 struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2301 struct desc_struct tr_seg;
5601d05b 2302 u32 base3;
f850e2e6 2303 int r;
1aa36616 2304 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2305 unsigned mask = (1 << len) - 1;
5601d05b 2306 unsigned long base;
f850e2e6 2307
1aa36616 2308 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2309 if (!tr_seg.p)
f850e2e6 2310 return false;
79168fd1 2311 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2312 return false;
5601d05b
GN		 2313 base = get_desc_base(&tr_seg);
2314#ifdef CONFIG_X86_64
2315 base |= ((u64)base3) << 32;
2316#endif
0f65dd70 2317 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2318 if (r != X86EMUL_CONTINUE)
2319 return false;
79168fd1 2320 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2321 return false;
0f65dd70 2322 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2323 if (r != X86EMUL_CONTINUE)
2324 return false;
2325 if ((perm >> bit_idx) & mask)
2326 return false;
2327 return true;
2328}
2329
2330static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2331 u16 port, u16 len)
2332{
4fc40f07
GN		 2333 if (ctxt->perm_ok)
2334 return true;
2335
7b105ca2
TY		 2336 if (emulator_bad_iopl(ctxt))
2337 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2338 return false;
4fc40f07
GN		 2339
2340 ctxt->perm_ok = true;
2341
f850e2e6
GN		 2342 return true;
2343}
2344
38ba30ba 2345static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2346 struct tss_segment_16 *tss)
2347{
9dac77fa 2348 tss->ip = ctxt->_eip;
38ba30ba 2349 tss->flag = ctxt->eflags;
9dac77fa
AK		 2350 tss->ax = ctxt->regs[VCPU_REGS_RAX];
2351 tss->cx = ctxt->regs[VCPU_REGS_RCX];
2352 tss->dx = ctxt->regs[VCPU_REGS_RDX];
2353 tss->bx = ctxt->regs[VCPU_REGS_RBX];
2354 tss->sp = ctxt->regs[VCPU_REGS_RSP];
2355 tss->bp = ctxt->regs[VCPU_REGS_RBP];
2356 tss->si = ctxt->regs[VCPU_REGS_RSI];
2357 tss->di = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2358
1aa36616
AK		 2359 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2360 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2361 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2362 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2363 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2364}
2365
2366static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2367 struct tss_segment_16 *tss)
2368{
38ba30ba
GN		 2369 int ret;
2370
9dac77fa 2371 ctxt->_eip = tss->ip;
38ba30ba 2372 ctxt->eflags = tss->flag | 2;
9dac77fa
AK		 2373 ctxt->regs[VCPU_REGS_RAX] = tss->ax;
2374 ctxt->regs[VCPU_REGS_RCX] = tss->cx;
2375 ctxt->regs[VCPU_REGS_RDX] = tss->dx;
2376 ctxt->regs[VCPU_REGS_RBX] = tss->bx;
2377 ctxt->regs[VCPU_REGS_RSP] = tss->sp;
2378 ctxt->regs[VCPU_REGS_RBP] = tss->bp;
2379 ctxt->regs[VCPU_REGS_RSI] = tss->si;
2380 ctxt->regs[VCPU_REGS_RDI] = tss->di;
38ba30ba
GN		 2381
2382 /*
2383 * SDM says that segment selectors are loaded before segment
2384 * descriptors
2385 */
1aa36616
AK		 2386 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2387 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2388 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2389 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2390 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2391
2392 /*
2393 * Now load segment descriptors. If fault happenes at this stage
2394 * it is handled in a context of new task
2395 */
7b105ca2 2396 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
38ba30ba
GN		 2397 if (ret != X86EMUL_CONTINUE)
2398 return ret;
7b105ca2 2399 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2400 if (ret != X86EMUL_CONTINUE)
2401 return ret;
7b105ca2 2402 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2403 if (ret != X86EMUL_CONTINUE)
2404 return ret;
7b105ca2 2405 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2406 if (ret != X86EMUL_CONTINUE)
2407 return ret;
7b105ca2 2408 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2409 if (ret != X86EMUL_CONTINUE)
2410 return ret;
2411
2412 return X86EMUL_CONTINUE;
2413}
2414
2415static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2416 u16 tss_selector, u16 old_tss_sel,
2417 ulong old_tss_base, struct desc_struct *new_desc)
2418{
7b105ca2 2419 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2420 struct tss_segment_16 tss_seg;
2421 int ret;
bcc55cba 2422 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2423
0f65dd70 2424 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2425 &ctxt->exception);
db297e3d 2426 if (ret != X86EMUL_CONTINUE)
38ba30ba 2427 /* FIXME: need to provide precise fault address */
38ba30ba 2428 return ret;
38ba30ba 2429
7b105ca2 2430 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2431
0f65dd70 2432 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2433 &ctxt->exception);
db297e3d 2434 if (ret != X86EMUL_CONTINUE)
38ba30ba 2435 /* FIXME: need to provide precise fault address */
38ba30ba 2436 return ret;
38ba30ba 2437
0f65dd70 2438 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2439 &ctxt->exception);
db297e3d 2440 if (ret != X86EMUL_CONTINUE)
38ba30ba 2441 /* FIXME: need to provide precise fault address */
38ba30ba 2442 return ret;
38ba30ba
GN		 2443
2444 if (old_tss_sel != 0xffff) {
2445 tss_seg.prev_task_link = old_tss_sel;
2446
0f65dd70 2447 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2448 &tss_seg.prev_task_link,
2449 sizeof tss_seg.prev_task_link,
0f65dd70 2450 &ctxt->exception);
db297e3d 2451 if (ret != X86EMUL_CONTINUE)
38ba30ba 2452 /* FIXME: need to provide precise fault address */
38ba30ba 2453 return ret;
38ba30ba
GN		 2454 }
2455
7b105ca2 2456 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2457}
2458
2459static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2460 struct tss_segment_32 *tss)
2461{
7b105ca2 2462 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
9dac77fa 2463 tss->eip = ctxt->_eip;
38ba30ba 2464 tss->eflags = ctxt->eflags;
9dac77fa
AK		 2465 tss->eax = ctxt->regs[VCPU_REGS_RAX];
2466 tss->ecx = ctxt->regs[VCPU_REGS_RCX];
2467 tss->edx = ctxt->regs[VCPU_REGS_RDX];
2468 tss->ebx = ctxt->regs[VCPU_REGS_RBX];
2469 tss->esp = ctxt->regs[VCPU_REGS_RSP];
2470 tss->ebp = ctxt->regs[VCPU_REGS_RBP];
2471 tss->esi = ctxt->regs[VCPU_REGS_RSI];
2472 tss->edi = ctxt->regs[VCPU_REGS_RDI];
38ba30ba 2473
1aa36616
AK		 2474 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2475 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2476 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2477 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2478 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2479 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2480 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2481}
2482
2483static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2484 struct tss_segment_32 *tss)
2485{
38ba30ba
GN		 2486 int ret;
2487
7b105ca2 2488 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2489 return emulate_gp(ctxt, 0);
9dac77fa 2490 ctxt->_eip = tss->eip;
38ba30ba 2491 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2492
2493 /* General purpose registers */
9dac77fa
AK		 2494 ctxt->regs[VCPU_REGS_RAX] = tss->eax;
2495 ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
2496 ctxt->regs[VCPU_REGS_RDX] = tss->edx;
2497 ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
2498 ctxt->regs[VCPU_REGS_RSP] = tss->esp;
2499 ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
2500 ctxt->regs[VCPU_REGS_RSI] = tss->esi;
2501 ctxt->regs[VCPU_REGS_RDI] = tss->edi;
38ba30ba
GN		 2502
2503 /*
2504 * SDM says that segment selectors are loaded before segment
2505 * descriptors
2506 */
1aa36616
AK		 2507 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2508 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2509 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2510 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2511 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2512 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2513 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2514
4cee4798
KW		 2515 /*
2516 * If we're switching between Protected Mode and VM86, we need to make
2517 * sure to update the mode before loading the segment descriptors so
2518 * that the selectors are interpreted correctly.
2519 *
2520 * Need to get rflags to the vcpu struct immediately because it
2521 * influences the CPL which is checked at least when loading the segment
2522 * descriptors and when pushing an error code to the new kernel stack.
2523 *
2524 * TODO Introduce a separate ctxt->ops->set_cpl callback
2525 */
2526 if (ctxt->eflags & X86_EFLAGS_VM)
2527 ctxt->mode = X86EMUL_MODE_VM86;
2528 else
2529 ctxt->mode = X86EMUL_MODE_PROT32;
2530
2531 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2532
38ba30ba
GN		 2533 /*
2534 * Now load segment descriptors. If fault happenes at this stage
2535 * it is handled in a context of new task
2536 */
7b105ca2 2537 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
38ba30ba
GN		 2538 if (ret != X86EMUL_CONTINUE)
2539 return ret;
7b105ca2 2540 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
38ba30ba
GN		 2541 if (ret != X86EMUL_CONTINUE)
2542 return ret;
7b105ca2 2543 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
38ba30ba
GN		 2544 if (ret != X86EMUL_CONTINUE)
2545 return ret;
7b105ca2 2546 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
38ba30ba
GN		 2547 if (ret != X86EMUL_CONTINUE)
2548 return ret;
7b105ca2 2549 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2550 if (ret != X86EMUL_CONTINUE)
2551 return ret;
7b105ca2 2552 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
38ba30ba
GN		 2553 if (ret != X86EMUL_CONTINUE)
2554 return ret;
7b105ca2 2555 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2556 if (ret != X86EMUL_CONTINUE)
2557 return ret;
2558
2559 return X86EMUL_CONTINUE;
2560}
2561
2562static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2563 u16 tss_selector, u16 old_tss_sel,
2564 ulong old_tss_base, struct desc_struct *new_desc)
2565{
7b105ca2 2566 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2567 struct tss_segment_32 tss_seg;
2568 int ret;
bcc55cba 2569 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2570
0f65dd70 2571 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2572 &ctxt->exception);
db297e3d 2573 if (ret != X86EMUL_CONTINUE)
38ba30ba 2574 /* FIXME: need to provide precise fault address */
38ba30ba 2575 return ret;
38ba30ba 2576
7b105ca2 2577 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2578
0f65dd70 2579 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2580 &ctxt->exception);
db297e3d 2581 if (ret != X86EMUL_CONTINUE)
38ba30ba 2582 /* FIXME: need to provide precise fault address */
38ba30ba 2583 return ret;
38ba30ba 2584
0f65dd70 2585 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2586 &ctxt->exception);
db297e3d 2587 if (ret != X86EMUL_CONTINUE)
38ba30ba 2588 /* FIXME: need to provide precise fault address */
38ba30ba 2589 return ret;
38ba30ba
GN		 2590
2591 if (old_tss_sel != 0xffff) {
2592 tss_seg.prev_task_link = old_tss_sel;
2593
0f65dd70 2594 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2595 &tss_seg.prev_task_link,
2596 sizeof tss_seg.prev_task_link,
0f65dd70 2597 &ctxt->exception);
db297e3d 2598 if (ret != X86EMUL_CONTINUE)
38ba30ba 2599 /* FIXME: need to provide precise fault address */
38ba30ba 2600 return ret;
38ba30ba
GN		 2601 }
2602
7b105ca2 2603 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2604}
2605
2606static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2607 u16 tss_selector, int idt_index, int reason,
e269fb21 2608 bool has_error_code, u32 error_code)
38ba30ba 2609{
7b105ca2 2610 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2611 struct desc_struct curr_tss_desc, next_tss_desc;
2612 int ret;
1aa36616 2613 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2614 ulong old_tss_base =
4bff1e86 2615 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2616 u32 desc_limit;
38ba30ba
GN		 2617
2618 /* FIXME: old_tss_base == ~0 ? */
2619
7b105ca2 2620 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2621 if (ret != X86EMUL_CONTINUE)
2622 return ret;
7b105ca2 2623 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2624 if (ret != X86EMUL_CONTINUE)
2625 return ret;
2626
2627 /* FIXME: check that next_tss_desc is tss */
2628
7f3d35fd
KW		 2629 /*
2630 * Check privileges. The three cases are task switch caused by...
2631 *
2632 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2633 * 2. Exception/IRQ/iret: No check is performed
2634 * 3. jmp/call to TSS: Check agains DPL of the TSS
2635 */
2636 if (reason == TASK_SWITCH_GATE) {
2637 if (idt_index != -1) {
2638 /* Software interrupts */
2639 struct desc_struct task_gate_desc;
2640 int dpl;
2641
2642 ret = read_interrupt_descriptor(ctxt, idt_index,
2643 &task_gate_desc);
2644 if (ret != X86EMUL_CONTINUE)
2645 return ret;
2646
2647 dpl = task_gate_desc.dpl;
2648 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2649 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2650 }
2651 } else if (reason != TASK_SWITCH_IRET) {
2652 int dpl = next_tss_desc.dpl;
2653 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2654 return emulate_gp(ctxt, tss_selector);
38ba30ba
GN		 2655 }
2656
7f3d35fd 2657
ceffb459
GN		 2658 desc_limit = desc_limit_scaled(&next_tss_desc);
2659 if (!next_tss_desc.p ||
2660 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2661 desc_limit < 0x2b)) {
54b8486f 2662 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2663 return X86EMUL_PROPAGATE_FAULT;
2664 }
2665
2666 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2667 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2668 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2669 }
2670
2671 if (reason == TASK_SWITCH_IRET)
2672 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2673
2674 /* set back link to prev task only if NT bit is set in eflags
2675 note that old_tss_sel is not used afetr this point */
2676 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2677 old_tss_sel = 0xffff;
2678
2679 if (next_tss_desc.type & 8)
7b105ca2 2680 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2681 old_tss_base, &next_tss_desc);
2682 else
7b105ca2 2683 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2684 old_tss_base, &next_tss_desc);
0760d448
JK		 2685 if (ret != X86EMUL_CONTINUE)
2686 return ret;
38ba30ba
GN		 2687
2688 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2689 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2690
2691 if (reason != TASK_SWITCH_IRET) {
2692 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2693 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2694 }
2695
717746e3 2696 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2697 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2698
e269fb21 2699 if (has_error_code) {
9dac77fa
AK		 2700 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2701 ctxt->lock_prefix = 0;
2702 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2703 ret = em_push(ctxt);
e269fb21
JK		 2704 }
2705
38ba30ba
GN		 2706 return ret;
2707}
2708
2709int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2710 u16 tss_selector, int idt_index, int reason,
e269fb21 2711 bool has_error_code, u32 error_code)
38ba30ba 2712{
38ba30ba
GN		 2713 int rc;
2714
9dac77fa
AK		 2715 ctxt->_eip = ctxt->eip;
2716 ctxt->dst.type = OP_NONE;
38ba30ba 2717
7f3d35fd 2718 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2719 has_error_code, error_code);
38ba30ba 2720
4179bb02 2721 if (rc == X86EMUL_CONTINUE)
9dac77fa 2722 ctxt->eip = ctxt->_eip;
38ba30ba 2723
a0c0ab2f 2724 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2725}
2726
90de84f5 2727static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2728 int reg, struct operand *op)
a682e354 2729{
a682e354
GN		 2730 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2731
9dac77fa
AK		 2732 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
2733 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
90de84f5 2734 op->addr.mem.seg = seg;
a682e354
GN		 2735}
2736
7af04fc0
AK		 2737static int em_das(struct x86_emulate_ctxt *ctxt)
2738{
7af04fc0
AK		 2739 u8 al, old_al;
2740 bool af, cf, old_cf;
2741
2742 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2743 al = ctxt->dst.val;
7af04fc0
AK		 2744
2745 old_al = al;
2746 old_cf = cf;
2747 cf = false;
2748 af = ctxt->eflags & X86_EFLAGS_AF;
2749 if ((al & 0x0f) > 9 || af) {
2750 al -= 6;
2751 cf = old_cf | (al >= 250);
2752 af = true;
2753 } else {
2754 af = false;
2755 }
2756 if (old_al > 0x99 || old_cf) {
2757 al -= 0x60;
2758 cf = true;
2759 }
2760
9dac77fa 2761 ctxt->dst.val = al;
7af04fc0 2762 /* Set PF, ZF, SF */
9dac77fa
AK		 2763 ctxt->src.type = OP_IMM;
2764 ctxt->src.val = 0;
2765 ctxt->src.bytes = 1;
a31b9cea 2766 emulate_2op_SrcV(ctxt, "or");
7af04fc0
AK		 2767 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2768 if (cf)
2769 ctxt->eflags |= X86_EFLAGS_CF;
2770 if (af)
2771 ctxt->eflags |= X86_EFLAGS_AF;
2772 return X86EMUL_CONTINUE;
2773}
2774
d4ddafcd
TY		 2775static int em_call(struct x86_emulate_ctxt *ctxt)
2776{
2777 long rel = ctxt->src.val;
2778
2779 ctxt->src.val = (unsigned long)ctxt->_eip;
2780 jmp_rel(ctxt, rel);
2781 return em_push(ctxt);
2782}
2783
0ef753b8
AK		 2784static int em_call_far(struct x86_emulate_ctxt *ctxt)
2785{
0ef753b8
AK		 2786 u16 sel, old_cs;
2787 ulong old_eip;
2788 int rc;
2789
1aa36616 2790 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
9dac77fa 2791 old_eip = ctxt->_eip;
0ef753b8 2792
9dac77fa 2793 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
7b105ca2 2794 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
0ef753b8
AK		 2795 return X86EMUL_CONTINUE;
2796
9dac77fa
AK		 2797 ctxt->_eip = 0;
2798 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
0ef753b8 2799
9dac77fa 2800 ctxt->src.val = old_cs;
4487b3b4 2801 rc = em_push(ctxt);
0ef753b8
AK		 2802 if (rc != X86EMUL_CONTINUE)
2803 return rc;
2804
9dac77fa 2805 ctxt->src.val = old_eip;
4487b3b4 2806 return em_push(ctxt);
0ef753b8
AK		 2807}
2808
40ece7c7
AK		 2809static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2810{
40ece7c7
AK		 2811 int rc;
2812
9dac77fa
AK		 2813 ctxt->dst.type = OP_REG;
2814 ctxt->dst.addr.reg = &ctxt->_eip;
2815 ctxt->dst.bytes = ctxt->op_bytes;
2816 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
40ece7c7
AK		 2817 if (rc != X86EMUL_CONTINUE)
2818 return rc;
9dac77fa 2819 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
40ece7c7
AK		 2820 return X86EMUL_CONTINUE;
2821}
2822
d67fc27a
TY		 2823static int em_add(struct x86_emulate_ctxt *ctxt)
2824{
a31b9cea 2825 emulate_2op_SrcV(ctxt, "add");
d67fc27a
TY		 2826 return X86EMUL_CONTINUE;
2827}
2828
2829static int em_or(struct x86_emulate_ctxt *ctxt)
2830{
a31b9cea 2831 emulate_2op_SrcV(ctxt, "or");
d67fc27a
TY		 2832 return X86EMUL_CONTINUE;
2833}
2834
2835static int em_adc(struct x86_emulate_ctxt *ctxt)
2836{
a31b9cea 2837 emulate_2op_SrcV(ctxt, "adc");
d67fc27a
TY		 2838 return X86EMUL_CONTINUE;
2839}
2840
2841static int em_sbb(struct x86_emulate_ctxt *ctxt)
2842{
a31b9cea 2843 emulate_2op_SrcV(ctxt, "sbb");
d67fc27a
TY		 2844 return X86EMUL_CONTINUE;
2845}
2846
2847static int em_and(struct x86_emulate_ctxt *ctxt)
2848{
a31b9cea 2849 emulate_2op_SrcV(ctxt, "and");
d67fc27a
TY		 2850 return X86EMUL_CONTINUE;
2851}
2852
2853static int em_sub(struct x86_emulate_ctxt *ctxt)
2854{
a31b9cea 2855 emulate_2op_SrcV(ctxt, "sub");
d67fc27a
TY		 2856 return X86EMUL_CONTINUE;
2857}
2858
2859static int em_xor(struct x86_emulate_ctxt *ctxt)
2860{
a31b9cea 2861 emulate_2op_SrcV(ctxt, "xor");
d67fc27a
TY		 2862 return X86EMUL_CONTINUE;
2863}
2864
2865static int em_cmp(struct x86_emulate_ctxt *ctxt)
2866{
a31b9cea 2867 emulate_2op_SrcV(ctxt, "cmp");
d67fc27a 2868 /* Disable writeback. */
9dac77fa 2869 ctxt->dst.type = OP_NONE;
d67fc27a
TY		 2870 return X86EMUL_CONTINUE;
2871}
2872
9f21ca59
TY		 2873static int em_test(struct x86_emulate_ctxt *ctxt)
2874{
a31b9cea 2875 emulate_2op_SrcV(ctxt, "test");
caa8a168
AK		 2876 /* Disable writeback. */
2877 ctxt->dst.type = OP_NONE;
9f21ca59
TY		 2878 return X86EMUL_CONTINUE;
2879}
2880
e4f973ae
TY		 2881static int em_xchg(struct x86_emulate_ctxt *ctxt)
2882{
e4f973ae 2883 /* Write back the register source. */
9dac77fa
AK		 2884 ctxt->src.val = ctxt->dst.val;
2885 write_register_operand(&ctxt->src);
e4f973ae
TY		 2886
2887 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 2888 ctxt->dst.val = ctxt->src.orig_val;
2889 ctxt->lock_prefix = 1;
e4f973ae
TY		 2890 return X86EMUL_CONTINUE;
2891}
2892
5c82aa29 2893static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4 2894{
a31b9cea 2895 emulate_2op_SrcV_nobyte(ctxt, "imul");
f3a1b9f4
AK		 2896 return X86EMUL_CONTINUE;
2897}
2898
5c82aa29
AK		 2899static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2900{
9dac77fa 2901 ctxt->dst.val = ctxt->src2.val;
5c82aa29
AK		 2902 return em_imul(ctxt);
2903}
2904
61429142
AK		 2905static int em_cwd(struct x86_emulate_ctxt *ctxt)
2906{
9dac77fa
AK		 2907 ctxt->dst.type = OP_REG;
2908 ctxt->dst.bytes = ctxt->src.bytes;
2909 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
2910 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 2911
2912 return X86EMUL_CONTINUE;
2913}
2914
48bb5d3c
AK		 2915static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2916{
48bb5d3c
AK		 2917 u64 tsc = 0;
2918
717746e3 2919 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
9dac77fa
AK		 2920 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
2921 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
48bb5d3c
AK		 2922 return X86EMUL_CONTINUE;
2923}
2924
222d21aa
AK		 2925static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
2926{
2927 u64 pmc;
2928
2929 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
2930 return emulate_gp(ctxt, 0);
2931 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
2932 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
2933 return X86EMUL_CONTINUE;
2934}
2935
b9eac5f4
AK		 2936static int em_mov(struct x86_emulate_ctxt *ctxt)
2937{
49597d81 2938 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
b9eac5f4
AK		 2939 return X86EMUL_CONTINUE;
2940}
2941
bc00f8d2
TY		 2942static int em_cr_write(struct x86_emulate_ctxt *ctxt)
2943{
2944 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
2945 return emulate_gp(ctxt, 0);
2946
2947 /* Disable writeback. */
2948 ctxt->dst.type = OP_NONE;
2949 return X86EMUL_CONTINUE;
2950}
2951
2952static int em_dr_write(struct x86_emulate_ctxt *ctxt)
2953{
2954 unsigned long val;
2955
2956 if (ctxt->mode == X86EMUL_MODE_PROT64)
2957 val = ctxt->src.val & ~0ULL;
2958 else
2959 val = ctxt->src.val & ~0U;
2960
2961 /* #UD condition is already handled. */
2962 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
2963 return emulate_gp(ctxt, 0);
2964
2965 /* Disable writeback. */
2966 ctxt->dst.type = OP_NONE;
2967 return X86EMUL_CONTINUE;
2968}
2969
e1e210b0
TY		 2970static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
2971{
2972 u64 msr_data;
2973
2974 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
2975 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
2976 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
2977 return emulate_gp(ctxt, 0);
2978
2979 return X86EMUL_CONTINUE;
2980}
2981
2982static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
2983{
2984 u64 msr_data;
2985
2986 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
2987 return emulate_gp(ctxt, 0);
2988
2989 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
2990 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
2991 return X86EMUL_CONTINUE;
2992}
2993
1bd5f469
TY		 2994static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
2995{
9dac77fa 2996 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 2997 return emulate_ud(ctxt);
2998
9dac77fa 2999 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
1bd5f469
TY		 3000 return X86EMUL_CONTINUE;
3001}
3002
3003static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3004{
9dac77fa 3005 u16 sel = ctxt->src.val;
1bd5f469 3006
9dac77fa 3007 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3008 return emulate_ud(ctxt);
3009
9dac77fa 3010 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3011 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3012
3013 /* Disable writeback. */
9dac77fa
AK		 3014 ctxt->dst.type = OP_NONE;
3015 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3016}
3017
38503911
AK		 3018static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3019{
9fa088f4
AK		 3020 int rc;
3021 ulong linear;
3022
9dac77fa 3023 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3024 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3025 ctxt->ops->invlpg(ctxt, linear);
38503911 3026 /* Disable writeback. */
9dac77fa 3027 ctxt->dst.type = OP_NONE;
38503911
AK		 3028 return X86EMUL_CONTINUE;
3029}
3030
2d04a05b
AK		 3031static int em_clts(struct x86_emulate_ctxt *ctxt)
3032{
3033 ulong cr0;
3034
3035 cr0 = ctxt->ops->get_cr(ctxt, 0);
3036 cr0 &= ~X86_CR0_TS;
3037 ctxt->ops->set_cr(ctxt, 0, cr0);
3038 return X86EMUL_CONTINUE;
3039}
3040
26d05cc7
AK		 3041static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3042{
26d05cc7
AK		 3043 int rc;
3044
9dac77fa 3045 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
26d05cc7
AK		 3046 return X86EMUL_UNHANDLEABLE;
3047
3048 rc = ctxt->ops->fix_hypercall(ctxt);
3049 if (rc != X86EMUL_CONTINUE)
3050 return rc;
3051
3052 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3053 ctxt->_eip = ctxt->eip;
26d05cc7 3054 /* Disable writeback. */
9dac77fa 3055 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3056 return X86EMUL_CONTINUE;
3057}
3058
96051572
AK		 3059static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3060 void (*get)(struct x86_emulate_ctxt *ctxt,
3061 struct desc_ptr *ptr))
3062{
3063 struct desc_ptr desc_ptr;
3064
3065 if (ctxt->mode == X86EMUL_MODE_PROT64)
3066 ctxt->op_bytes = 8;
3067 get(ctxt, &desc_ptr);
3068 if (ctxt->op_bytes == 2) {
3069 ctxt->op_bytes = 4;
3070 desc_ptr.address &= 0x00ffffff;
3071 }
3072 /* Disable writeback. */
3073 ctxt->dst.type = OP_NONE;
3074 return segmented_write(ctxt, ctxt->dst.addr.mem,
3075 &desc_ptr, 2 + ctxt->op_bytes);
3076}
3077
3078static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3079{
3080 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3081}
3082
3083static int em_sidt(struct x86_emulate_ctxt *ctxt)
3084{
3085 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3086}
3087
26d05cc7
AK		 3088static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3089{
26d05cc7
AK		 3090 struct desc_ptr desc_ptr;
3091 int rc;
3092
510425ff
AK		 3093 if (ctxt->mode == X86EMUL_MODE_PROT64)
3094 ctxt->op_bytes = 8;
9dac77fa 3095 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3096 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3097 ctxt->op_bytes);
26d05cc7
AK		 3098 if (rc != X86EMUL_CONTINUE)
3099 return rc;
3100 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3101 /* Disable writeback. */
9dac77fa 3102 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3103 return X86EMUL_CONTINUE;
3104}
3105
5ef39c71 3106static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3107{
26d05cc7
AK		 3108 int rc;
3109
5ef39c71
AK		 3110 rc = ctxt->ops->fix_hypercall(ctxt);
3111
26d05cc7 3112 /* Disable writeback. */
9dac77fa 3113 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3114 return rc;
3115}
3116
3117static int em_lidt(struct x86_emulate_ctxt *ctxt)
3118{
26d05cc7
AK		 3119 struct desc_ptr desc_ptr;
3120 int rc;
3121
510425ff
AK		 3122 if (ctxt->mode == X86EMUL_MODE_PROT64)
3123 ctxt->op_bytes = 8;
9dac77fa 3124 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
509cf9fe 3125 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3126 ctxt->op_bytes);
26d05cc7
AK		 3127 if (rc != X86EMUL_CONTINUE)
3128 return rc;
3129 ctxt->ops->set_idt(ctxt, &desc_ptr);
3130 /* Disable writeback. */
9dac77fa 3131 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3132 return X86EMUL_CONTINUE;
3133}
3134
3135static int em_smsw(struct x86_emulate_ctxt *ctxt)
3136{
9dac77fa
AK		 3137 ctxt->dst.bytes = 2;
3138 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3139 return X86EMUL_CONTINUE;
3140}
3141
3142static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3143{
26d05cc7 3144 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3145 | (ctxt->src.val & 0x0f));
3146 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3147 return X86EMUL_CONTINUE;
3148}
3149
d06e03ad
TY		 3150static int em_loop(struct x86_emulate_ctxt *ctxt)
3151{
9dac77fa
AK		 3152 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3153 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
3154 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3155 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3156
3157 return X86EMUL_CONTINUE;
3158}
3159
3160static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3161{
9dac77fa
AK		 3162 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
3163 jmp_rel(ctxt, ctxt->src.val);
d06e03ad
TY		 3164
3165 return X86EMUL_CONTINUE;
3166}
3167
d7841a4b
TY		 3168static int em_in(struct x86_emulate_ctxt *ctxt)
3169{
3170 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3171 &ctxt->dst.val))
3172 return X86EMUL_IO_NEEDED;
3173
3174 return X86EMUL_CONTINUE;
3175}
3176
3177static int em_out(struct x86_emulate_ctxt *ctxt)
3178{
3179 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3180 &ctxt->src.val, 1);
3181 /* Disable writeback. */
3182 ctxt->dst.type = OP_NONE;
3183 return X86EMUL_CONTINUE;
3184}
3185
f411e6cd
TY		 3186static int em_cli(struct x86_emulate_ctxt *ctxt)
3187{
3188 if (emulator_bad_iopl(ctxt))
3189 return emulate_gp(ctxt, 0);
3190
3191 ctxt->eflags &= ~X86_EFLAGS_IF;
3192 return X86EMUL_CONTINUE;
3193}
3194
3195static int em_sti(struct x86_emulate_ctxt *ctxt)
3196{
3197 if (emulator_bad_iopl(ctxt))
3198 return emulate_gp(ctxt, 0);
3199
3200 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3201 ctxt->eflags |= X86_EFLAGS_IF;
3202 return X86EMUL_CONTINUE;
3203}
3204
ce7faab2
TY		 3205static int em_bt(struct x86_emulate_ctxt *ctxt)
3206{
3207 /* Disable writeback. */
3208 ctxt->dst.type = OP_NONE;
3209 /* only subword offset */
3210 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
3211
3212 emulate_2op_SrcV_nobyte(ctxt, "bt");
3213 return X86EMUL_CONTINUE;
3214}
3215
3216static int em_bts(struct x86_emulate_ctxt *ctxt)
3217{
3218 emulate_2op_SrcV_nobyte(ctxt, "bts");
3219 return X86EMUL_CONTINUE;
3220}
3221
3222static int em_btr(struct x86_emulate_ctxt *ctxt)
3223{
3224 emulate_2op_SrcV_nobyte(ctxt, "btr");
3225 return X86EMUL_CONTINUE;
3226}
3227
3228static int em_btc(struct x86_emulate_ctxt *ctxt)
3229{
3230 emulate_2op_SrcV_nobyte(ctxt, "btc");
3231 return X86EMUL_CONTINUE;
3232}
3233
ff227392
TY		 3234static int em_bsf(struct x86_emulate_ctxt *ctxt)
3235{
d54e4237 3236 emulate_2op_SrcV_nobyte(ctxt, "bsf");
ff227392
TY		 3237 return X86EMUL_CONTINUE;
3238}
3239
3240static int em_bsr(struct x86_emulate_ctxt *ctxt)
3241{
d54e4237 3242 emulate_2op_SrcV_nobyte(ctxt, "bsr");
ff227392
TY		 3243 return X86EMUL_CONTINUE;
3244}
3245
6d6eede4
AK		 3246static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3247{
3248 u32 eax, ebx, ecx, edx;
3249
3250 eax = ctxt->regs[VCPU_REGS_RAX];
3251 ecx = ctxt->regs[VCPU_REGS_RCX];
3252 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3253 ctxt->regs[VCPU_REGS_RAX] = eax;
3254 ctxt->regs[VCPU_REGS_RBX] = ebx;
3255 ctxt->regs[VCPU_REGS_RCX] = ecx;
3256 ctxt->regs[VCPU_REGS_RDX] = edx;
3257 return X86EMUL_CONTINUE;
3258}
3259
2dd7caa0
AK		 3260static int em_lahf(struct x86_emulate_ctxt *ctxt)
3261{
3262 ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
3263 ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
3264 return X86EMUL_CONTINUE;
3265}
3266
cfec82cb
JR		 3267static bool valid_cr(int nr)
3268{
3269 switch (nr) {
3270 case 0:
3271 case 2 ... 4:
3272 case 8:
3273 return true;
3274 default:
3275 return false;
3276 }
3277}
3278
3279static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3280{
9dac77fa 3281 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3282 return emulate_ud(ctxt);
3283
3284 return X86EMUL_CONTINUE;
3285}
3286
3287static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3288{
9dac77fa
AK		 3289 u64 new_val = ctxt->src.val64;
3290 int cr = ctxt->modrm_reg;
c2ad2bb3 3291 u64 efer = 0;
cfec82cb
JR		 3292
3293 static u64 cr_reserved_bits[] = {
3294 0xffffffff00000000ULL,
3295 0, 0, 0, /* CR3 checked later */
3296 CR4_RESERVED_BITS,
3297 0, 0, 0,
3298 CR8_RESERVED_BITS,
3299 };
3300
3301 if (!valid_cr(cr))
3302 return emulate_ud(ctxt);
3303
3304 if (new_val & cr_reserved_bits[cr])
3305 return emulate_gp(ctxt, 0);
3306
3307 switch (cr) {
3308 case 0: {
c2ad2bb3 3309 u64 cr4;
cfec82cb
JR		 3310 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3311 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3312 return emulate_gp(ctxt, 0);
3313
717746e3
AK		 3314 cr4 = ctxt->ops->get_cr(ctxt, 4);
3315 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3316
3317 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3318 !(cr4 & X86_CR4_PAE))
3319 return emulate_gp(ctxt, 0);
3320
3321 break;
3322 }
3323 case 3: {
3324 u64 rsvd = 0;
3325
c2ad2bb3
AK		 3326 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3327 if (efer & EFER_LMA)
cfec82cb 3328 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 3329 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 3330 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 3331 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 3332 rsvd = CR3_NONPAE_RESERVED_BITS;
3333
3334 if (new_val & rsvd)
3335 return emulate_gp(ctxt, 0);
3336
3337 break;
3338 }
3339 case 4: {
717746e3 3340 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3341
3342 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3343 return emulate_gp(ctxt, 0);
3344
3345 break;
3346 }
3347 }
3348
3349 return X86EMUL_CONTINUE;
3350}
3351
3b88e41a
JR		 3352static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3353{
3354 unsigned long dr7;
3355
717746e3 3356 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3357
3358 /* Check if DR7.Global_Enable is set */
3359 return dr7 & (1 << 13);
3360}
3361
3362static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3363{
9dac77fa 3364 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3365 u64 cr4;
3366
3367 if (dr > 7)
3368 return emulate_ud(ctxt);
3369
717746e3 3370 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3371 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3372 return emulate_ud(ctxt);
3373
3374 if (check_dr7_gd(ctxt))
3375 return emulate_db(ctxt);
3376
3377 return X86EMUL_CONTINUE;
3378}
3379
3380static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3381{
9dac77fa
AK		 3382 u64 new_val = ctxt->src.val64;
3383 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3384
3385 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3386 return emulate_gp(ctxt, 0);
3387
3388 return check_dr_read(ctxt);
3389}
3390
01de8b09
JR		 3391static int check_svme(struct x86_emulate_ctxt *ctxt)
3392{
3393 u64 efer;
3394
717746e3 3395 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3396
3397 if (!(efer & EFER_SVME))
3398 return emulate_ud(ctxt);
3399
3400 return X86EMUL_CONTINUE;
3401}
3402
3403static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3404{
9dac77fa 3405 u64 rax = ctxt->regs[VCPU_REGS_RAX];
01de8b09
JR		 3406
3407 /* Valid physical address? */
d4224449 3408 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3409 return emulate_gp(ctxt, 0);
3410
3411 return check_svme(ctxt);
3412}
3413
d7eb8203
JR		 3414static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3415{
717746e3 3416 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3417
717746e3 3418 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3419 return emulate_ud(ctxt);
3420
3421 return X86EMUL_CONTINUE;
3422}
3423
8061252e
JR		 3424static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3425{
717746e3 3426 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
9dac77fa 3427 u64 rcx = ctxt->regs[VCPU_REGS_RCX];
8061252e 3428
717746e3 3429 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 3430 (rcx > 3))
3431 return emulate_gp(ctxt, 0);
3432
3433 return X86EMUL_CONTINUE;
3434}
3435
f6511935
JR		 3436static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3437{
9dac77fa
AK		 3438 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3439 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3440 return emulate_gp(ctxt, 0);
3441
3442 return X86EMUL_CONTINUE;
3443}
3444
3445static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3446{
9dac77fa
AK		 3447 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3448 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3449 return emulate_gp(ctxt, 0);
3450
3451 return X86EMUL_CONTINUE;
3452}
3453
73fba5f4 3454#define D(_y) { .flags = (_y) }
c4f035c6 3455#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 3456#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3457 .check_perm = (_p) }
73fba5f4 3458#define N D(0)
01de8b09 3459#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3460#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3461#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
73fba5f4 3462#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 3463#define II(_f, _e, _i) \
3464 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 3465#define IIP(_f, _e, _i, _p) \
3466 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3467 .check_perm = (_p) }
aa97bb48 3468#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3469
8d8f4e9f 3470#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3471#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3472#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
d7841a4b
TY		 3473#define I2bvIP(_f, _e, _i, _p) \
3474 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3475
d67fc27a
TY		 3476#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3477 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3478 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3479
d7eb8203 3480static struct opcode group7_rm1[] = {
1c2545be
TY		 3481 DI(SrcNone | Priv, monitor),
3482 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3483 N, N, N, N, N, N,
3484};
3485
01de8b09 3486static struct opcode group7_rm3[] = {
1c2545be
TY		 3487 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3488 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3489 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3490 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3491 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3492 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3493 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3494 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3495};
6230f7fc 3496
d7eb8203
JR		 3497static struct opcode group7_rm7[] = {
3498 N,
1c2545be 3499 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3500 N, N, N, N, N, N,
3501};
d67fc27a 3502
73fba5f4 3503static struct opcode group1[] = {
d67fc27a 3504 I(Lock, em_add),
d5ae7ce8 3505 I(Lock | PageTable, em_or),
d67fc27a
TY		 3506 I(Lock, em_adc),
3507 I(Lock, em_sbb),
d5ae7ce8 3508 I(Lock | PageTable, em_and),
d67fc27a
TY		 3509 I(Lock, em_sub),
3510 I(Lock, em_xor),
3511 I(0, em_cmp),
73fba5f4
AK		 3512};
3513
3514static struct opcode group1A[] = {
1c2545be 3515 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3516};
3517
3518static struct opcode group3[] = {
1c2545be
TY		 3519 I(DstMem | SrcImm, em_test),
3520 I(DstMem | SrcImm, em_test),
3521 I(DstMem | SrcNone | Lock, em_not),
3522 I(DstMem | SrcNone | Lock, em_neg),
3523 I(SrcMem, em_mul_ex),
3524 I(SrcMem, em_imul_ex),
3525 I(SrcMem, em_div_ex),
3526 I(SrcMem, em_idiv_ex),
73fba5f4
AK		 3527};
3528
3529static struct opcode group4[] = {
1c2545be
TY		 3530 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3531 I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
73fba5f4
AK		 3532 N, N, N, N, N, N,
3533};
3534
3535static struct opcode group5[] = {
1c2545be
TY		 3536 I(DstMem | SrcNone | Lock, em_grp45),
3537 I(DstMem | SrcNone | Lock, em_grp45),
3538 I(SrcMem | Stack, em_grp45),
3539 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3540 I(SrcMem | Stack, em_grp45),
3541 I(SrcMemFAddr | ImplicitOps, em_grp45),
3542 I(SrcMem | Stack, em_grp45), N,
73fba5f4
AK		 3543};
3544
dee6bb70 3545static struct opcode group6[] = {
1c2545be
TY		 3546 DI(Prot, sldt),
3547 DI(Prot, str),
3548 DI(Prot | Priv, lldt),
3549 DI(Prot | Priv, ltr),
dee6bb70
JR		 3550 N, N, N, N,
3551};
3552
73fba5f4 3553static struct group_dual group7 = { {
96051572
AK		 3554 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3555 II(Mov | DstMem | Priv, em_sidt, sidt),
1c2545be
TY		 3556 II(SrcMem | Priv, em_lgdt, lgdt),
3557 II(SrcMem | Priv, em_lidt, lidt),
3558 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3559 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3560 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3561}, {
1c2545be 3562 I(SrcNone | Priv | VendorSpecific, em_vmcall),
5ef39c71 3563 EXT(0, group7_rm1),
01de8b09 3564 N, EXT(0, group7_rm3),
1c2545be
TY		 3565 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3566 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3567 EXT(0, group7_rm7),
73fba5f4
AK		 3568} };
3569
3570static struct opcode group8[] = {
3571 N, N, N, N,
1c2545be
TY		 3572 I(DstMem | SrcImmByte, em_bt),
3573 I(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3574 I(DstMem | SrcImmByte | Lock, em_btr),
3575 I(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3576};
3577
3578static struct group_dual group9 = { {
1c2545be 3579 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3580}, {
3581 N, N, N, N, N, N, N, N,
3582} };
3583
a4d4a7c1 3584static struct opcode group11[] = {
1c2545be 3585 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3586 X7(D(Undefined)),
a4d4a7c1
AK		 3587};
3588
aa97bb48 3589static struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3590 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3591};
3592
3e114eb4
AK		 3593static struct gprefix pfx_vmovntpx = {
3594 I(0, em_mov), N, N, N,
3595};
3596
73fba5f4
AK		 3597static struct opcode opcode_table[256] = {
3598 /* 0x00 - 0x07 */
d67fc27a 3599 I6ALU(Lock, em_add),
1cd196ea
AK		 3600 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3601 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3602 /* 0x08 - 0x0F */
d5ae7ce8 3603 I6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3604 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3605 N,
73fba5f4 3606 /* 0x10 - 0x17 */
d67fc27a 3607 I6ALU(Lock, em_adc),
1cd196ea
AK		 3608 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3609 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3610 /* 0x18 - 0x1F */
d67fc27a 3611 I6ALU(Lock, em_sbb),
1cd196ea
AK		 3612 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3613 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3614 /* 0x20 - 0x27 */
d5ae7ce8 3615 I6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3616 /* 0x28 - 0x2F */
d67fc27a 3617 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3618 /* 0x30 - 0x37 */
d67fc27a 3619 I6ALU(Lock, em_xor), N, N,
73fba5f4 3620 /* 0x38 - 0x3F */
d67fc27a 3621 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3622 /* 0x40 - 0x4F */
3623 X16(D(DstReg)),
3624 /* 0x50 - 0x57 */
63540382 3625 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3626 /* 0x58 - 0x5F */
c54fe504 3627 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3628 /* 0x60 - 0x67 */
b96a7fad
TY		 3629 I(ImplicitOps | Stack | No64, em_pusha),
3630 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3631 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3632 N, N, N, N,
3633 /* 0x68 - 0x6F */
d46164db
AK		 3634 I(SrcImm | Mov | Stack, em_push),
3635 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3636 I(SrcImmByte | Mov | Stack, em_push),
3637 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2b5e97e1
TY		 3638 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
3639 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3640 /* 0x70 - 0x7F */
3641 X16(D(SrcImmByte)),
3642 /* 0x80 - 0x87 */
1c2545be
TY		 3643 G(ByteOp | DstMem | SrcImm, group1),
3644 G(DstMem | SrcImm, group1),
3645 G(ByteOp | DstMem | SrcImm | No64, group1),
3646 G(DstMem | SrcImmByte, group1),
9f21ca59 3647 I2bv(DstMem | SrcReg | ModRM, em_test),
d5ae7ce8 3648 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 3649 /* 0x88 - 0x8F */
d5ae7ce8 3650 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 3651 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 3652 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 3653 D(ModRM | SrcMem | NoAccess | DstReg),
3654 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3655 G(0, group1A),
73fba5f4 3656 /* 0x90 - 0x97 */
bf608f88 3657 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3658 /* 0x98 - 0x9F */
61429142 3659 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3660 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 3661 II(ImplicitOps | Stack, em_pushf, pushf),
2dd7caa0 3662 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
73fba5f4 3663 /* 0xA0 - 0xA7 */
b9eac5f4 3664 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 3665 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 3666 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3667 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3668 /* 0xA8 - 0xAF */
9f21ca59 3669 I2bv(DstAcc | SrcImm, em_test),
b9eac5f4
AK		 3670 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3671 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3672 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3673 /* 0xB0 - 0xB7 */
b9eac5f4 3674 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3675 /* 0xB8 - 0xBF */
b9eac5f4 3676 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3677 /* 0xC0 - 0xC7 */
d2c6c7ad 3678 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7 3679 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
ebda02c2 3680 I(ImplicitOps | Stack, em_ret),
d4b4325f
AK		 3681 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3682 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 3683 G(ByteOp, group11), G(0, group11),
73fba5f4 3684 /* 0xC8 - 0xCF */
612e89f0
AK		 3685 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3686 N, I(ImplicitOps | Stack, em_ret_far),
3c6e276f 3687 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 3688 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 3689 /* 0xD0 - 0xD7 */
d2c6c7ad 3690 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3691 N, N, N, N,
3692 /* 0xD8 - 0xDF */
3693 N, N, N, N, N, N, N, N,
3694 /* 0xE0 - 0xE7 */
d06e03ad
TY		 3695 X3(I(SrcImmByte, em_loop)),
3696 I(SrcImmByte, em_jcxz),
d7841a4b
TY		 3697 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3698 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 3699 /* 0xE8 - 0xEF */
d4ddafcd 3700 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
db5b0762 3701 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
d7841a4b
TY		 3702 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3703 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 3704 /* 0xF0 - 0xF7 */
bf608f88 3705 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3706 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3707 G(ByteOp, group3), G(0, group3),
73fba5f4 3708 /* 0xF8 - 0xFF */
f411e6cd
TY		 3709 D(ImplicitOps), D(ImplicitOps),
3710 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 3711 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3712};
3713
3714static struct opcode twobyte_table[256] = {
3715 /* 0x00 - 0x0F */
dee6bb70 3716 G(0, group6), GD(0, &group7), N, N,
db5b0762
TY		 3717 N, I(ImplicitOps | VendorSpecific, em_syscall),
3718 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 3719 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3720 N, D(ImplicitOps | ModRM), N, N,
3721 /* 0x10 - 0x1F */
3722 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3723 /* 0x20 - 0x2F */
cfec82cb 3724 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3725 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
bc00f8d2
TY		 3726 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
3727 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
73fba5f4 3728 N, N, N, N,
3e114eb4
AK		 3729 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3730 N, N, N, N,
73fba5f4 3731 /* 0x30 - 0x3F */
e1e210b0 3732 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 3733 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 3734 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 3735 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
db5b0762
TY		 3736 I(ImplicitOps | VendorSpecific, em_sysenter),
3737 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
d867162c 3738 N, N,
73fba5f4
AK		 3739 N, N, N, N, N, N, N, N,
3740 /* 0x40 - 0x4F */
3741 X16(D(DstReg | SrcMem | ModRM | Mov)),
3742 /* 0x50 - 0x5F */
3743 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3744 /* 0x60 - 0x6F */
aa97bb48
AK		 3745 N, N, N, N,
3746 N, N, N, N,
3747 N, N, N, N,
3748 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3749 /* 0x70 - 0x7F */
aa97bb48
AK		 3750 N, N, N, N,
3751 N, N, N, N,
3752 N, N, N, N,
3753 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3754 /* 0x80 - 0x8F */
3755 X16(D(SrcImm)),
3756 /* 0x90 - 0x9F */
ee45b58e 3757 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 3758 /* 0xA0 - 0xA7 */
1cd196ea 3759 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
6d6eede4 3760 II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
73fba5f4
AK		 3761 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3762 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3763 /* 0xA8 - 0xAF */
1cd196ea 3764 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 3765 DI(ImplicitOps, rsm),
ce7faab2 3766 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
73fba5f4
AK		 3767 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3768 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3769 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3770 /* 0xB0 - 0xB7 */
e940b5c2 3771 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 3772 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
ce7faab2 3773 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 3774 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
3775 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 3776 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3777 /* 0xB8 - 0xBF */
3778 N, N,
ce7faab2
TY		 3779 G(BitOp, group8),
3780 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
ff227392 3781 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 3782 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3783 /* 0xC0 - 0xCF */
739ae406 3784 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3785 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3786 N, N, N, GD(0, &group9),
3787 N, N, N, N, N, N, N, N,
3788 /* 0xD0 - 0xDF */
3789 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3790 /* 0xE0 - 0xEF */
3791 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3792 /* 0xF0 - 0xFF */
3793 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3794};
3795
3796#undef D
3797#undef N
3798#undef G
3799#undef GD
3800#undef I
aa97bb48 3801#undef GP
01de8b09 3802#undef EXT
73fba5f4 3803
8d8f4e9f 3804#undef D2bv
f6511935 3805#undef D2bvIP
8d8f4e9f 3806#undef I2bv
d7841a4b 3807#undef I2bvIP
d67fc27a 3808#undef I6ALU
8d8f4e9f 3809
9dac77fa 3810static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 3811{
3812 unsigned size;
3813
9dac77fa 3814 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 3815 if (size == 8)
3816 size = 4;
3817 return size;
3818}
3819
3820static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3821 unsigned size, bool sign_extension)
3822{
39f21ee5
AK		 3823 int rc = X86EMUL_CONTINUE;
3824
3825 op->type = OP_IMM;
3826 op->bytes = size;
9dac77fa 3827 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 3828 /* NB. Immediates are sign-extended as necessary. */
3829 switch (op->bytes) {
3830 case 1:
e85a1085 3831 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 3832 break;
3833 case 2:
e85a1085 3834 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 3835 break;
3836 case 4:
e85a1085 3837 op->val = insn_fetch(s32, ctxt);
39f21ee5
AK		 3838 break;
3839 }
3840 if (!sign_extension) {
3841 switch (op->bytes) {
3842 case 1:
3843 op->val &= 0xff;
3844 break;
3845 case 2:
3846 op->val &= 0xffff;
3847 break;
3848 case 4:
3849 op->val &= 0xffffffff;
3850 break;
3851 }
3852 }
3853done:
3854 return rc;
3855}
3856
a9945549
AK		 3857static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
3858 unsigned d)
3859{
3860 int rc = X86EMUL_CONTINUE;
3861
3862 switch (d) {
3863 case OpReg:
2adb5ad9 3864 decode_register_operand(ctxt, op);
a9945549
AK		 3865 break;
3866 case OpImmUByte:
608aabe3 3867 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 3868 break;
3869 case OpMem:
41ddf978 3870 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 3871 mem_common:
3872 *op = ctxt->memop;
3873 ctxt->memopp = op;
3874 if ((ctxt->d & BitOp) && op == &ctxt->dst)
a9945549
AK		 3875 fetch_bit_operand(ctxt);
3876 op->orig_val = op->val;
3877 break;
41ddf978
AK		 3878 case OpMem64:
3879 ctxt->memop.bytes = 8;
3880 goto mem_common;
a9945549
AK		 3881 case OpAcc:
3882 op->type = OP_REG;
3883 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3884 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
3885 fetch_register_operand(op);
3886 op->orig_val = op->val;
3887 break;
3888 case OpDI:
3889 op->type = OP_MEM;
3890 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3891 op->addr.mem.ea =
3892 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
3893 op->addr.mem.seg = VCPU_SREG_ES;
3894 op->val = 0;
3895 break;
3896 case OpDX:
3897 op->type = OP_REG;
3898 op->bytes = 2;
3899 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
3900 fetch_register_operand(op);
3901 break;
4dd6a57d
AK		 3902 case OpCL:
3903 op->bytes = 1;
3904 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
3905 break;
3906 case OpImmByte:
3907 rc = decode_imm(ctxt, op, 1, true);
3908 break;
3909 case OpOne:
3910 op->bytes = 1;
3911 op->val = 1;
3912 break;
3913 case OpImm:
3914 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
3915 break;
28867cee
AK		 3916 case OpMem8:
3917 ctxt->memop.bytes = 1;
3918 goto mem_common;
0fe59128
AK		 3919 case OpMem16:
3920 ctxt->memop.bytes = 2;
3921 goto mem_common;
3922 case OpMem32:
3923 ctxt->memop.bytes = 4;
3924 goto mem_common;
3925 case OpImmU16:
3926 rc = decode_imm(ctxt, op, 2, false);
3927 break;
3928 case OpImmU:
3929 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
3930 break;
3931 case OpSI:
3932 op->type = OP_MEM;
3933 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3934 op->addr.mem.ea =
3935 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
3936 op->addr.mem.seg = seg_override(ctxt);
3937 op->val = 0;
3938 break;
3939 case OpImmFAddr:
3940 op->type = OP_IMM;
3941 op->addr.mem.ea = ctxt->_eip;
3942 op->bytes = ctxt->op_bytes + 2;
3943 insn_fetch_arr(op->valptr, op->bytes, ctxt);
3944 break;
3945 case OpMemFAddr:
3946 ctxt->memop.bytes = ctxt->op_bytes + 2;
3947 goto mem_common;
c191a7a0
AK		 3948 case OpES:
3949 op->val = VCPU_SREG_ES;
3950 break;
3951 case OpCS:
3952 op->val = VCPU_SREG_CS;
3953 break;
3954 case OpSS:
3955 op->val = VCPU_SREG_SS;
3956 break;
3957 case OpDS:
3958 op->val = VCPU_SREG_DS;
3959 break;
3960 case OpFS:
3961 op->val = VCPU_SREG_FS;
3962 break;
3963 case OpGS:
3964 op->val = VCPU_SREG_GS;
3965 break;
a9945549
AK		 3966 case OpImplicit:
3967 /* Special instructions do their own operand decoding. */
3968 default:
3969 op->type = OP_NONE; /* Disable writeback. */
3970 break;
3971 }
3972
3973done:
3974 return rc;
3975}
3976
ef5d75cc 3977int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 3978{
dde7e6d1
AK		 3979 int rc = X86EMUL_CONTINUE;
3980 int mode = ctxt->mode;
46561646 3981 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3982 bool op_prefix = false;
46561646 3983 struct opcode opcode;
dde7e6d1 3984
f09ed83e
AK		 3985 ctxt->memop.type = OP_NONE;
3986 ctxt->memopp = NULL;
9dac77fa
AK		 3987 ctxt->_eip = ctxt->eip;
3988 ctxt->fetch.start = ctxt->_eip;
3989 ctxt->fetch.end = ctxt->fetch.start + insn_len;
dc25e89e 3990 if (insn_len > 0)
9dac77fa 3991 memcpy(ctxt->fetch.data, insn, insn_len);
dde7e6d1
AK		 3992
3993 switch (mode) {
3994 case X86EMUL_MODE_REAL:
3995 case X86EMUL_MODE_VM86:
3996 case X86EMUL_MODE_PROT16:
3997 def_op_bytes = def_ad_bytes = 2;
3998 break;
3999 case X86EMUL_MODE_PROT32:
4000 def_op_bytes = def_ad_bytes = 4;
4001 break;
4002#ifdef CONFIG_X86_64
4003 case X86EMUL_MODE_PROT64:
4004 def_op_bytes = 4;
4005 def_ad_bytes = 8;
4006 break;
4007#endif
4008 default:
1d2887e2 4009 return EMULATION_FAILED;
dde7e6d1
AK		 4010 }
4011
9dac77fa
AK		 4012 ctxt->op_bytes = def_op_bytes;
4013 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4014
4015 /* Legacy prefixes. */
4016 for (;;) {
e85a1085 4017 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4018 case 0x66: /* operand-size override */
0d7cdee8 4019 op_prefix = true;
dde7e6d1 4020 /* switch between 2/4 bytes */
9dac77fa 4021 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4022 break;
4023 case 0x67: /* address-size override */
4024 if (mode == X86EMUL_MODE_PROT64)
4025 /* switch between 4/8 bytes */
9dac77fa 4026 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4027 else
4028 /* switch between 2/4 bytes */
9dac77fa 4029 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4030 break;
4031 case 0x26: /* ES override */
4032 case 0x2e: /* CS override */
4033 case 0x36: /* SS override */
4034 case 0x3e: /* DS override */
9dac77fa 4035 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
dde7e6d1
AK		 4036 break;
4037 case 0x64: /* FS override */
4038 case 0x65: /* GS override */
9dac77fa 4039 set_seg_override(ctxt, ctxt->b & 7);
dde7e6d1
AK		 4040 break;
4041 case 0x40 ... 0x4f: /* REX */
4042 if (mode != X86EMUL_MODE_PROT64)
4043 goto done_prefixes;
9dac77fa 4044 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4045 continue;
4046 case 0xf0: /* LOCK */
9dac77fa 4047 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4048 break;
4049 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4050 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4051 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4052 break;
4053 default:
4054 goto done_prefixes;
4055 }
4056
4057 /* Any legacy prefix after a REX prefix nullifies its effect. */
4058
9dac77fa 4059 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4060 }
4061
4062done_prefixes:
4063
4064 /* REX prefix. */
9dac77fa
AK		 4065 if (ctxt->rex_prefix & 8)
4066 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4067
4068 /* Opcode byte(s). */
9dac77fa 4069 opcode = opcode_table[ctxt->b];
d3ad6243 4070 /* Two-byte opcode? */
9dac77fa
AK		 4071 if (ctxt->b == 0x0f) {
4072 ctxt->twobyte = 1;
e85a1085 4073 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4074 opcode = twobyte_table[ctxt->b];
dde7e6d1 4075 }
9dac77fa 4076 ctxt->d = opcode.flags;
dde7e6d1 4077
9f4260e7
TY		 4078 if (ctxt->d & ModRM)
4079 ctxt->modrm = insn_fetch(u8, ctxt);
4080
9dac77fa
AK		 4081 while (ctxt->d & GroupMask) {
4082 switch (ctxt->d & GroupMask) {
46561646 4083 case Group:
9dac77fa 4084 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4085 opcode = opcode.u.group[goffset];
4086 break;
4087 case GroupDual:
9dac77fa
AK		 4088 goffset = (ctxt->modrm >> 3) & 7;
4089 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4090 opcode = opcode.u.gdual->mod3[goffset];
4091 else
4092 opcode = opcode.u.gdual->mod012[goffset];
4093 break;
4094 case RMExt:
9dac77fa 4095 goffset = ctxt->modrm & 7;
01de8b09 4096 opcode = opcode.u.group[goffset];
46561646
AK		 4097 break;
4098 case Prefix:
9dac77fa 4099 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4100 return EMULATION_FAILED;
9dac77fa 4101 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4102 switch (simd_prefix) {
4103 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4104 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4105 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4106 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4107 }
4108 break;
4109 default:
1d2887e2 4110 return EMULATION_FAILED;
0d7cdee8 4111 }
46561646 4112
b1ea50b2 4113 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4114 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4115 }
4116
9dac77fa
AK		 4117 ctxt->execute = opcode.u.execute;
4118 ctxt->check_perm = opcode.check_perm;
4119 ctxt->intercept = opcode.intercept;
dde7e6d1
AK		 4120
4121 /* Unrecognised? */
9dac77fa 4122 if (ctxt->d == 0 || (ctxt->d & Undefined))
1d2887e2 4123 return EMULATION_FAILED;
dde7e6d1 4124
9dac77fa 4125 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
1d2887e2 4126 return EMULATION_FAILED;
d867162c 4127
9dac77fa
AK		 4128 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4129 ctxt->op_bytes = 8;
dde7e6d1 4130
9dac77fa 4131 if (ctxt->d & Op3264) {
7f9b4b75 4132 if (mode == X86EMUL_MODE_PROT64)
9dac77fa 4133 ctxt->op_bytes = 8;
7f9b4b75 4134 else
9dac77fa 4135 ctxt->op_bytes = 4;
7f9b4b75
AK		 4136 }
4137
9dac77fa
AK		 4138 if (ctxt->d & Sse)
4139 ctxt->op_bytes = 16;
cbe2c9d3
AK		 4140 else if (ctxt->d & Mmx)
4141 ctxt->op_bytes = 8;
1253791d 4142
dde7e6d1 4143 /* ModRM and SIB bytes. */
9dac77fa 4144 if (ctxt->d & ModRM) {
f09ed83e 4145 rc = decode_modrm(ctxt, &ctxt->memop);
9dac77fa
AK		 4146 if (!ctxt->has_seg_override)
4147 set_seg_override(ctxt, ctxt->modrm_seg);
4148 } else if (ctxt->d & MemAbs)
f09ed83e 4149 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4150 if (rc != X86EMUL_CONTINUE)
4151 goto done;
4152
9dac77fa
AK		 4153 if (!ctxt->has_seg_override)
4154 set_seg_override(ctxt, VCPU_SREG_DS);
dde7e6d1 4155
f09ed83e 4156 ctxt->memop.addr.mem.seg = seg_override(ctxt);
dde7e6d1 4157
f09ed83e
AK		 4158 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4159 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
dde7e6d1 4160
dde7e6d1
AK		 4161 /*
4162 * Decode and fetch the source operand: register, memory
4163 * or immediate.
4164 */
0fe59128 4165 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4166 if (rc != X86EMUL_CONTINUE)
4167 goto done;
4168
dde7e6d1
AK		 4169 /*
4170 * Decode and fetch the second source operand: register, memory
4171 * or immediate.
4172 */
4dd6a57d 4173 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4174 if (rc != X86EMUL_CONTINUE)
4175 goto done;
4176
dde7e6d1 4177 /* Decode and fetch the destination operand: register or memory. */
a9945549 4178 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1
AK		 4179
4180done:
f09ed83e
AK		 4181 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4182 ctxt->memopp->addr.mem.ea += ctxt->_eip;
cb16c348 4183
1d2887e2 4184 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4185}
4186
1cb3f3ae
XG		 4187bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4188{
4189 return ctxt->d & PageTable;
4190}
4191
3e2f65d5
GN		 4192static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4193{
3e2f65d5
GN		 4194 /* The second termination condition only applies for REPE
4195 * and REPNE. Test if the repeat string operation prefix is
4196 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4197 * corresponding termination condition according to:
4198 * - if REPE/REPZ and ZF = 0 then done
4199 * - if REPNE/REPNZ and ZF = 1 then done
4200 */
9dac77fa
AK		 4201 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4202 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4203 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4204 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4205 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4206 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4207 return true;
4208
4209 return false;
4210}
4211
cbe2c9d3
AK		 4212static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4213{
4214 bool fault = false;
4215
4216 ctxt->ops->get_fpu(ctxt);
4217 asm volatile("1: fwait \n\t"
4218 "2: \n\t"
4219 ".pushsection .fixup,\"ax\" \n\t"
4220 "3: \n\t"
4221 "movb $1, %[fault] \n\t"
4222 "jmp 2b \n\t"
4223 ".popsection \n\t"
4224 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4225 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4226 ctxt->ops->put_fpu(ctxt);
4227
4228 if (unlikely(fault))
4229 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4230
4231 return X86EMUL_CONTINUE;
4232}
4233
4234static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4235 struct operand *op)
4236{
4237 if (op->type == OP_MM)
4238 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4239}
4240
7b105ca2 4241int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4242{
9aabc88f 4243 struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4244 int rc = X86EMUL_CONTINUE;
9dac77fa 4245 int saved_dst_type = ctxt->dst.type;
8b4caf66 4246
9dac77fa 4247 ctxt->mem_read.pos = 0;
310b5d30 4248
9dac77fa 4249 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
35d3d4a1 4250 rc = emulate_ud(ctxt);
1161624f
GN		 4251 goto done;
4252 }
4253
d380a5e4 4254 /* LOCK prefix is allowed only with some instructions */
9dac77fa 4255 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4256 rc = emulate_ud(ctxt);
d380a5e4
GN		 4257 goto done;
4258 }
4259
9dac77fa 4260 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4261 rc = emulate_ud(ctxt);
081bca0e
AK		 4262 goto done;
4263 }
4264
cbe2c9d3
AK		 4265 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4266 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 4267 rc = emulate_ud(ctxt);
4268 goto done;
4269 }
4270
cbe2c9d3 4271 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 4272 rc = emulate_nm(ctxt);
4273 goto done;
4274 }
4275
cbe2c9d3
AK		 4276 if (ctxt->d & Mmx) {
4277 rc = flush_pending_x87_faults(ctxt);
4278 if (rc != X86EMUL_CONTINUE)
4279 goto done;
4280 /*
4281 * Now that we know the fpu is exception safe, we can fetch
4282 * operands from it.
4283 */
4284 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4285 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4286 if (!(ctxt->d & Mov))
4287 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4288 }
4289
9dac77fa
AK		 4290 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4291 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4292 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 4293 if (rc != X86EMUL_CONTINUE)
4294 goto done;
4295 }
4296
e92805ac 4297 /* Privileged instruction can be executed only in CPL=0 */
9dac77fa 4298 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 4299 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 4300 goto done;
4301 }
4302
8ea7d6ae 4303 /* Instruction can only be executed in protected mode */
9dac77fa 4304 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
8ea7d6ae
JR		 4305 rc = emulate_ud(ctxt);
4306 goto done;
4307 }
4308
d09beabd 4309 /* Do instruction specific permission checks */
9dac77fa
AK		 4310 if (ctxt->check_perm) {
4311 rc = ctxt->check_perm(ctxt);
d09beabd
JR		 4312 if (rc != X86EMUL_CONTINUE)
4313 goto done;
4314 }
4315
9dac77fa
AK		 4316 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4317 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4318 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 4319 if (rc != X86EMUL_CONTINUE)
4320 goto done;
4321 }
4322
9dac77fa 4323 if (ctxt->rep_prefix && (ctxt->d & String)) {
b9fa9d6b 4324 /* All REP prefixes have the same first termination condition */
9dac77fa
AK		 4325 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
4326 ctxt->eip = ctxt->_eip;
b9fa9d6b
AK		 4327 goto done;
4328 }
b9fa9d6b
AK		 4329 }
4330
9dac77fa
AK		 4331 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4332 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4333 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4334 if (rc != X86EMUL_CONTINUE)
8b4caf66 4335 goto done;
9dac77fa 4336 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4337 }
4338
9dac77fa
AK		 4339 if (ctxt->src2.type == OP_MEM) {
4340 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4341 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4342 if (rc != X86EMUL_CONTINUE)
4343 goto done;
4344 }
4345
9dac77fa 4346 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4347 goto special_insn;
4348
4349
9dac77fa 4350 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4351 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4352 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4353 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4354 if (rc != X86EMUL_CONTINUE)
4355 goto done;
038e51de 4356 }
9dac77fa 4357 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4358
018a98db
AK		 4359special_insn:
4360
9dac77fa
AK		 4361 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4362 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4363 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4364 if (rc != X86EMUL_CONTINUE)
4365 goto done;
4366 }
4367
9dac77fa
AK		 4368 if (ctxt->execute) {
4369 rc = ctxt->execute(ctxt);
ef65c889
AK		 4370 if (rc != X86EMUL_CONTINUE)
4371 goto done;
4372 goto writeback;
4373 }
4374
9dac77fa 4375 if (ctxt->twobyte)
6aa8b732
AK		 4376 goto twobyte_insn;
4377
9dac77fa 4378 switch (ctxt->b) {
33615aa9 4379 case 0x40 ... 0x47: /* inc r16/r32 */
d1eef45d 4380 emulate_1op(ctxt, "inc");
33615aa9
AK		 4381 break;
4382 case 0x48 ... 0x4f: /* dec r16/r32 */
d1eef45d 4383 emulate_1op(ctxt, "dec");
33615aa9 4384 break;
6aa8b732 4385 case 0x63: /* movsxd */
8b4caf66 4386 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4387 goto cannot_emulate;
9dac77fa 4388 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4389 break;
b2833e3c 4390 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa
AK		 4391 if (test_cc(ctxt->b, ctxt->eflags))
4392 jmp_rel(ctxt, ctxt->src.val);
018a98db 4393 break;
7e0b54b1 4394 case 0x8d: /* lea r16/r32, m */
9dac77fa 4395 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4396 break;
3d9e77df 4397 case 0x90 ... 0x97: /* nop / xchg reg, rax */
9dac77fa 4398 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
34698d8c 4399 break;
e4f973ae
TY		 4400 rc = em_xchg(ctxt);
4401 break;
e8b6fa70 4402 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4403 switch (ctxt->op_bytes) {
4404 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4405 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4406 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4407 }
4408 break;
018a98db 4409 case 0xc0 ... 0xc1:
51187683 4410 rc = em_grp2(ctxt);
018a98db 4411 break;
6e154e56 4412 case 0xcc: /* int3 */
5c5df76b
TY		 4413 rc = emulate_int(ctxt, 3);
4414 break;
6e154e56 4415 case 0xcd: /* int n */
9dac77fa 4416 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4417 break;
4418 case 0xce: /* into */
5c5df76b
TY		 4419 if (ctxt->eflags & EFLG_OF)
4420 rc = emulate_int(ctxt, 4);
6e154e56 4421 break;
018a98db 4422 case 0xd0 ... 0xd1: /* Grp2 */
51187683 4423 rc = em_grp2(ctxt);
018a98db
AK		 4424 break;
4425 case 0xd2 ... 0xd3: /* Grp2 */
9dac77fa 4426 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
51187683 4427 rc = em_grp2(ctxt);
018a98db 4428 break;
1a52e051 4429 case 0xe9: /* jmp rel */
db5b0762 4430 case 0xeb: /* jmp rel short */
9dac77fa
AK		 4431 jmp_rel(ctxt, ctxt->src.val);
4432 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4433 break;
111de5d6 4434 case 0xf4: /* hlt */
6c3287f7 4435 ctxt->ops->halt(ctxt);
19fdfa0d 4436 break;
111de5d6
AK		 4437 case 0xf5: /* cmc */
4438 /* complement carry flag from eflags reg */
4439 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4440 break;
4441 case 0xf8: /* clc */
4442 ctxt->eflags &= ~EFLG_CF;
111de5d6 4443 break;
8744aa9a
MG		 4444 case 0xf9: /* stc */
4445 ctxt->eflags |= EFLG_CF;
4446 break;
fb4616f4
MG		 4447 case 0xfc: /* cld */
4448 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4449 break;
4450 case 0xfd: /* std */
4451 ctxt->eflags |= EFLG_DF;
fb4616f4 4452 break;
91269b8f
AK		 4453 default:
4454 goto cannot_emulate;
6aa8b732 4455 }
018a98db 4456
7d9ddaed
AK		 4457 if (rc != X86EMUL_CONTINUE)
4458 goto done;
4459
018a98db 4460writeback:
adddcecf 4461 rc = writeback(ctxt);
1b30eaa8 4462 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4463 goto done;
4464
5cd21917
GN		 4465 /*
4466 * restore dst type in case the decoding will be reused
4467 * (happens for string instruction )
4468 */
9dac77fa 4469 ctxt->dst.type = saved_dst_type;
5cd21917 4470
9dac77fa
AK		 4471 if ((ctxt->d & SrcMask) == SrcSI)
4472 string_addr_inc(ctxt, seg_override(ctxt),
4473 VCPU_REGS_RSI, &ctxt->src);
a682e354 4474
9dac77fa 4475 if ((ctxt->d & DstMask) == DstDI)
90de84f5 4476 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
9dac77fa 4477 &ctxt->dst);
d9271123 4478
9dac77fa
AK		 4479 if (ctxt->rep_prefix && (ctxt->d & String)) {
4480 struct read_cache *r = &ctxt->io_read;
4481 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4482
d2ddd1c4
GN		 4483 if (!string_insn_completed(ctxt)) {
4484 /*
4485 * Re-enter guest when pio read ahead buffer is empty
4486 * or, if it is not used, after each 1024 iteration.
4487 */
9dac77fa 4488 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
d2ddd1c4
GN		 4489 (r->end == 0 || r->end != r->pos)) {
4490 /*
4491 * Reset read cache. Usually happens before
4492 * decode, but since instruction is restarted
4493 * we have to do it here.
4494 */
9dac77fa 4495 ctxt->mem_read.end = 0;
d2ddd1c4
GN		 4496 return EMULATION_RESTART;
4497 }
4498 goto done; /* skip rip writeback */
0fa6ccbd 4499 }
5cd21917 4500 }
d2ddd1c4 4501
9dac77fa 4502 ctxt->eip = ctxt->_eip;
018a98db
AK		 4503
4504done:
da9cb575
AK		 4505 if (rc == X86EMUL_PROPAGATE_FAULT)
4506 ctxt->have_exception = true;
775fde86
JR		 4507 if (rc == X86EMUL_INTERCEPTED)
4508 return EMULATION_INTERCEPTED;
4509
d2ddd1c4 4510 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4511
4512twobyte_insn:
9dac77fa 4513 switch (ctxt->b) {
018a98db 4514 case 0x09: /* wbinvd */
cfb22375 4515 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4516 break;
4517 case 0x08: /* invd */
018a98db
AK		 4518 case 0x0d: /* GrpP (prefetch) */
4519 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4520 break;
4521 case 0x20: /* mov cr, reg */
9dac77fa 4522 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 4523 break;
6aa8b732 4524 case 0x21: /* mov from dr to reg */
9dac77fa 4525 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 4526 break;
6aa8b732 4527 case 0x40 ... 0x4f: /* cmov */
9dac77fa
AK		 4528 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4529 if (!test_cc(ctxt->b, ctxt->eflags))
4530 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 4531 break;
b2833e3c 4532 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa
AK		 4533 if (test_cc(ctxt->b, ctxt->eflags))
4534 jmp_rel(ctxt, ctxt->src.val);
018a98db 4535 break;
ee45b58e 4536 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 4537 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 4538 break;
9bf8ea42
GT		 4539 case 0xa4: /* shld imm8, r, r/m */
4540 case 0xa5: /* shld cl, r, r/m */
761441b9 4541 emulate_2op_cl(ctxt, "shld");
9bf8ea42 4542 break;
9bf8ea42
GT		 4543 case 0xac: /* shrd imm8, r, r/m */
4544 case 0xad: /* shrd cl, r, r/m */
761441b9 4545 emulate_2op_cl(ctxt, "shrd");
9bf8ea42 4546 break;
2a7c5b8b
GC		 4547 case 0xae: /* clflush */
4548 break;
6aa8b732 4549 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 4550 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4551 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 4552 : (u16) ctxt->src.val;
6aa8b732 4553 break;
6aa8b732 4554 case 0xbe ... 0xbf: /* movsx */
9dac77fa 4555 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 4556 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 4557 (s16) ctxt->src.val;
6aa8b732 4558 break;
92f738a5 4559 case 0xc0 ... 0xc1: /* xadd */
a31b9cea 4560 emulate_2op_SrcV(ctxt, "add");
92f738a5 4561 /* Write back the register source. */
9dac77fa
AK		 4562 ctxt->src.val = ctxt->dst.orig_val;
4563 write_register_operand(&ctxt->src);
92f738a5 4564 break;
a012e65a 4565 case 0xc3: /* movnti */
9dac77fa
AK		 4566 ctxt->dst.bytes = ctxt->op_bytes;
4567 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4568 (u64) ctxt->src.val;
a012e65a 4569 break;
91269b8f
AK		 4570 default:
4571 goto cannot_emulate;
6aa8b732 4572 }
7d9ddaed
AK		 4573
4574 if (rc != X86EMUL_CONTINUE)
4575 goto done;
4576
6aa8b732
AK		 4577 goto writeback;
4578
4579cannot_emulate:
a0c0ab2f 4580 return EMULATION_FAILED;
6aa8b732 4581}
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