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6aa8b732 | 1 | /****************************************************************************** |
56e82318 | 2 | * emulate.c |
6aa8b732 AK |
3 | * |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
9611c187 | 12 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
13 | * |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * Yaniv Kamay <yaniv@qumranet.com> | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | * | |
20 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
21 | */ | |
22 | ||
edf88417 | 23 | #include <linux/kvm_host.h> |
5fdbf976 | 24 | #include "kvm_cache_regs.h" |
6aa8b732 | 25 | #include <linux/module.h> |
56e82318 | 26 | #include <asm/kvm_emulate.h> |
6aa8b732 | 27 | |
3eeb3288 | 28 | #include "x86.h" |
38ba30ba | 29 | #include "tss.h" |
e99f0507 | 30 | |
a9945549 AK |
31 | /* |
32 | * Operand types | |
33 | */ | |
b1ea50b2 AK |
34 | #define OpNone 0ull |
35 | #define OpImplicit 1ull /* No generic decode */ | |
36 | #define OpReg 2ull /* Register */ | |
37 | #define OpMem 3ull /* Memory */ | |
38 | #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ | |
39 | #define OpDI 5ull /* ES:DI/EDI/RDI */ | |
40 | #define OpMem64 6ull /* Memory, 64-bit */ | |
41 | #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ | |
42 | #define OpDX 8ull /* DX register */ | |
4dd6a57d AK |
43 | #define OpCL 9ull /* CL register (for shifts) */ |
44 | #define OpImmByte 10ull /* 8-bit sign extended immediate */ | |
45 | #define OpOne 11ull /* Implied 1 */ | |
46 | #define OpImm 12ull /* Sign extended immediate */ | |
0fe59128 AK |
47 | #define OpMem16 13ull /* Memory operand (16-bit). */ |
48 | #define OpMem32 14ull /* Memory operand (32-bit). */ | |
49 | #define OpImmU 15ull /* Immediate operand, zero extended */ | |
50 | #define OpSI 16ull /* SI/ESI/RSI */ | |
51 | #define OpImmFAddr 17ull /* Immediate far address */ | |
52 | #define OpMemFAddr 18ull /* Far address in memory */ | |
53 | #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ | |
c191a7a0 AK |
54 | #define OpES 20ull /* ES */ |
55 | #define OpCS 21ull /* CS */ | |
56 | #define OpSS 22ull /* SS */ | |
57 | #define OpDS 23ull /* DS */ | |
58 | #define OpFS 24ull /* FS */ | |
59 | #define OpGS 25ull /* GS */ | |
28867cee | 60 | #define OpMem8 26ull /* 8-bit zero extended memory operand */ |
0fe59128 AK |
61 | |
62 | #define OpBits 5 /* Width of operand field */ | |
b1ea50b2 | 63 | #define OpMask ((1ull << OpBits) - 1) |
a9945549 | 64 | |
6aa8b732 AK |
65 | /* |
66 | * Opcode effective-address decode tables. | |
67 | * Note that we only emulate instructions that have at least one memory | |
68 | * operand (excluding implicit stack references). We assume that stack | |
69 | * references and instruction fetches will never occur in special memory | |
70 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
71 | * not be handled. | |
72 | */ | |
73 | ||
74 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
ab85b12b | 75 | #define ByteOp (1<<0) /* 8-bit operands. */ |
6aa8b732 | 76 | /* Destination operand type. */ |
a9945549 AK |
77 | #define DstShift 1 |
78 | #define ImplicitOps (OpImplicit << DstShift) | |
79 | #define DstReg (OpReg << DstShift) | |
80 | #define DstMem (OpMem << DstShift) | |
81 | #define DstAcc (OpAcc << DstShift) | |
82 | #define DstDI (OpDI << DstShift) | |
83 | #define DstMem64 (OpMem64 << DstShift) | |
84 | #define DstImmUByte (OpImmUByte << DstShift) | |
85 | #define DstDX (OpDX << DstShift) | |
86 | #define DstMask (OpMask << DstShift) | |
6aa8b732 | 87 | /* Source operand type. */ |
0fe59128 AK |
88 | #define SrcShift 6 |
89 | #define SrcNone (OpNone << SrcShift) | |
90 | #define SrcReg (OpReg << SrcShift) | |
91 | #define SrcMem (OpMem << SrcShift) | |
92 | #define SrcMem16 (OpMem16 << SrcShift) | |
93 | #define SrcMem32 (OpMem32 << SrcShift) | |
94 | #define SrcImm (OpImm << SrcShift) | |
95 | #define SrcImmByte (OpImmByte << SrcShift) | |
96 | #define SrcOne (OpOne << SrcShift) | |
97 | #define SrcImmUByte (OpImmUByte << SrcShift) | |
98 | #define SrcImmU (OpImmU << SrcShift) | |
99 | #define SrcSI (OpSI << SrcShift) | |
100 | #define SrcImmFAddr (OpImmFAddr << SrcShift) | |
101 | #define SrcMemFAddr (OpMemFAddr << SrcShift) | |
102 | #define SrcAcc (OpAcc << SrcShift) | |
103 | #define SrcImmU16 (OpImmU16 << SrcShift) | |
104 | #define SrcDX (OpDX << SrcShift) | |
28867cee | 105 | #define SrcMem8 (OpMem8 << SrcShift) |
0fe59128 | 106 | #define SrcMask (OpMask << SrcShift) |
221192bd MT |
107 | #define BitOp (1<<11) |
108 | #define MemAbs (1<<12) /* Memory operand is absolute displacement */ | |
109 | #define String (1<<13) /* String instruction (rep capable) */ | |
110 | #define Stack (1<<14) /* Stack instruction (push/pop) */ | |
111 | #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ | |
112 | #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ | |
113 | #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ | |
114 | #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ | |
115 | #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ | |
116 | #define Sse (1<<18) /* SSE Vector instruction */ | |
20c29ff2 AK |
117 | /* Generic ModRM decode. */ |
118 | #define ModRM (1<<19) | |
119 | /* Destination is only written; never read. */ | |
120 | #define Mov (1<<20) | |
d8769fed | 121 | /* Misc flags */ |
8ea7d6ae | 122 | #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ |
d867162c | 123 | #define VendorSpecific (1<<22) /* Vendor specific instruction */ |
5a506b12 | 124 | #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ |
7f9b4b75 | 125 | #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ |
047a4818 | 126 | #define Undefined (1<<25) /* No Such Instruction */ |
d380a5e4 | 127 | #define Lock (1<<26) /* lock prefix is allowed for the instruction */ |
e92805ac | 128 | #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ |
d8769fed | 129 | #define No64 (1<<28) |
d5ae7ce8 | 130 | #define PageTable (1 << 29) /* instruction used to write page table */ |
0dc8d10f | 131 | /* Source 2 operand type */ |
d5ae7ce8 | 132 | #define Src2Shift (30) |
4dd6a57d AK |
133 | #define Src2None (OpNone << Src2Shift) |
134 | #define Src2CL (OpCL << Src2Shift) | |
135 | #define Src2ImmByte (OpImmByte << Src2Shift) | |
136 | #define Src2One (OpOne << Src2Shift) | |
137 | #define Src2Imm (OpImm << Src2Shift) | |
c191a7a0 AK |
138 | #define Src2ES (OpES << Src2Shift) |
139 | #define Src2CS (OpCS << Src2Shift) | |
140 | #define Src2SS (OpSS << Src2Shift) | |
141 | #define Src2DS (OpDS << Src2Shift) | |
142 | #define Src2FS (OpFS << Src2Shift) | |
143 | #define Src2GS (OpGS << Src2Shift) | |
4dd6a57d | 144 | #define Src2Mask (OpMask << Src2Shift) |
cbe2c9d3 | 145 | #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ |
1c11b376 AK |
146 | #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ |
147 | #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ | |
148 | #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ | |
6aa8b732 | 149 | |
d0e53325 AK |
150 | #define X2(x...) x, x |
151 | #define X3(x...) X2(x), x | |
152 | #define X4(x...) X2(x), X2(x) | |
153 | #define X5(x...) X4(x), x | |
154 | #define X6(x...) X4(x), X2(x) | |
155 | #define X7(x...) X4(x), X3(x) | |
156 | #define X8(x...) X4(x), X4(x) | |
157 | #define X16(x...) X8(x), X8(x) | |
83babbca | 158 | |
d65b1dee | 159 | struct opcode { |
b1ea50b2 AK |
160 | u64 flags : 56; |
161 | u64 intercept : 8; | |
120df890 | 162 | union { |
ef65c889 | 163 | int (*execute)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
164 | struct opcode *group; |
165 | struct group_dual *gdual; | |
0d7cdee8 | 166 | struct gprefix *gprefix; |
120df890 | 167 | } u; |
d09beabd | 168 | int (*check_perm)(struct x86_emulate_ctxt *ctxt); |
120df890 AK |
169 | }; |
170 | ||
171 | struct group_dual { | |
172 | struct opcode mod012[8]; | |
173 | struct opcode mod3[8]; | |
d65b1dee AK |
174 | }; |
175 | ||
0d7cdee8 AK |
176 | struct gprefix { |
177 | struct opcode pfx_no; | |
178 | struct opcode pfx_66; | |
179 | struct opcode pfx_f2; | |
180 | struct opcode pfx_f3; | |
181 | }; | |
182 | ||
6aa8b732 | 183 | /* EFLAGS bit definitions. */ |
d4c6a154 GN |
184 | #define EFLG_ID (1<<21) |
185 | #define EFLG_VIP (1<<20) | |
186 | #define EFLG_VIF (1<<19) | |
187 | #define EFLG_AC (1<<18) | |
b1d86143 AP |
188 | #define EFLG_VM (1<<17) |
189 | #define EFLG_RF (1<<16) | |
d4c6a154 GN |
190 | #define EFLG_IOPL (3<<12) |
191 | #define EFLG_NT (1<<14) | |
6aa8b732 AK |
192 | #define EFLG_OF (1<<11) |
193 | #define EFLG_DF (1<<10) | |
b1d86143 | 194 | #define EFLG_IF (1<<9) |
d4c6a154 | 195 | #define EFLG_TF (1<<8) |
6aa8b732 AK |
196 | #define EFLG_SF (1<<7) |
197 | #define EFLG_ZF (1<<6) | |
198 | #define EFLG_AF (1<<4) | |
199 | #define EFLG_PF (1<<2) | |
200 | #define EFLG_CF (1<<0) | |
201 | ||
62bd430e MG |
202 | #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a |
203 | #define EFLG_RESERVED_ONE_MASK 2 | |
204 | ||
dd856efa AK |
205 | static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) |
206 | { | |
207 | if (!(ctxt->regs_valid & (1 << nr))) { | |
208 | ctxt->regs_valid |= 1 << nr; | |
209 | ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); | |
210 | } | |
211 | return ctxt->_regs[nr]; | |
212 | } | |
213 | ||
214 | static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
215 | { | |
216 | ctxt->regs_valid |= 1 << nr; | |
217 | ctxt->regs_dirty |= 1 << nr; | |
218 | return &ctxt->_regs[nr]; | |
219 | } | |
220 | ||
221 | static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) | |
222 | { | |
223 | reg_read(ctxt, nr); | |
224 | return reg_write(ctxt, nr); | |
225 | } | |
226 | ||
227 | static void writeback_registers(struct x86_emulate_ctxt *ctxt) | |
228 | { | |
229 | unsigned reg; | |
230 | ||
231 | for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) | |
232 | ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); | |
233 | } | |
234 | ||
235 | static void invalidate_registers(struct x86_emulate_ctxt *ctxt) | |
236 | { | |
237 | ctxt->regs_dirty = 0; | |
238 | ctxt->regs_valid = 0; | |
239 | } | |
240 | ||
6aa8b732 AK |
241 | /* |
242 | * Instruction emulation: | |
243 | * Most instructions are emulated directly via a fragment of inline assembly | |
244 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
245 | * any modified flags. | |
246 | */ | |
247 | ||
05b3e0c2 | 248 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
249 | #define _LO32 "k" /* force 32-bit operand */ |
250 | #define _STK "%%rsp" /* stack pointer */ | |
251 | #elif defined(__i386__) | |
252 | #define _LO32 "" /* force 32-bit operand */ | |
253 | #define _STK "%%esp" /* stack pointer */ | |
254 | #endif | |
255 | ||
256 | /* | |
257 | * These EFLAGS bits are restored from saved value during emulation, and | |
258 | * any changes are written back to the saved value after emulation. | |
259 | */ | |
260 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
261 | ||
262 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
263 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
264 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
265 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
266 | "push %"_tmp"; " \ | |
267 | "push %"_tmp"; " \ | |
268 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
269 | "andl %"_LO32 _tmp",("_STK"); " \ | |
270 | "pushf; " \ | |
271 | "notl %"_LO32 _tmp"; " \ | |
272 | "andl %"_LO32 _tmp",("_STK"); " \ | |
273 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
274 | "pop %"_tmp"; " \ | |
275 | "orl %"_LO32 _tmp",("_STK"); " \ | |
276 | "popf; " \ | |
277 | "pop %"_sav"; " | |
6aa8b732 AK |
278 | |
279 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
280 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
281 | /* _sav |= EFLAGS & _msk; */ \ | |
282 | "pushf; " \ | |
283 | "pop %"_tmp"; " \ | |
284 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
285 | "orl %"_LO32 _tmp",%"_sav"; " | |
286 | ||
dda96d8f AK |
287 | #ifdef CONFIG_X86_64 |
288 | #define ON64(x) x | |
289 | #else | |
290 | #define ON64(x) | |
291 | #endif | |
292 | ||
a31b9cea | 293 | #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ |
6b7ad61f AK |
294 | do { \ |
295 | __asm__ __volatile__ ( \ | |
296 | _PRE_EFLAGS("0", "4", "2") \ | |
297 | _op _suffix " %"_x"3,%1; " \ | |
298 | _POST_EFLAGS("0", "4", "2") \ | |
a31b9cea AK |
299 | : "=m" ((ctxt)->eflags), \ |
300 | "+q" (*(_dsttype*)&(ctxt)->dst.val), \ | |
6b7ad61f | 301 | "=&r" (_tmp) \ |
a31b9cea | 302 | : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ |
f3fd92fb | 303 | } while (0) |
6b7ad61f AK |
304 | |
305 | ||
6aa8b732 | 306 | /* Raw emulation: instruction has two explicit operands. */ |
a31b9cea | 307 | #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6b7ad61f AK |
308 | do { \ |
309 | unsigned long _tmp; \ | |
310 | \ | |
a31b9cea | 311 | switch ((ctxt)->dst.bytes) { \ |
6b7ad61f | 312 | case 2: \ |
a31b9cea | 313 | ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ |
6b7ad61f AK |
314 | break; \ |
315 | case 4: \ | |
a31b9cea | 316 | ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ |
6b7ad61f AK |
317 | break; \ |
318 | case 8: \ | |
a31b9cea | 319 | ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ |
6b7ad61f AK |
320 | break; \ |
321 | } \ | |
6aa8b732 AK |
322 | } while (0) |
323 | ||
a31b9cea | 324 | #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ |
6aa8b732 | 325 | do { \ |
6b7ad61f | 326 | unsigned long _tmp; \ |
a31b9cea | 327 | switch ((ctxt)->dst.bytes) { \ |
6aa8b732 | 328 | case 1: \ |
a31b9cea | 329 | ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ |
6aa8b732 AK |
330 | break; \ |
331 | default: \ | |
a31b9cea | 332 | __emulate_2op_nobyte(ctxt, _op, \ |
6aa8b732 AK |
333 | _wx, _wy, _lx, _ly, _qx, _qy); \ |
334 | break; \ | |
335 | } \ | |
336 | } while (0) | |
337 | ||
338 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
a31b9cea AK |
339 | #define emulate_2op_SrcB(ctxt, _op) \ |
340 | __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") | |
6aa8b732 AK |
341 | |
342 | /* Source operand is byte, word, long or quad sized. */ | |
a31b9cea AK |
343 | #define emulate_2op_SrcV(ctxt, _op) \ |
344 | __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") | |
6aa8b732 AK |
345 | |
346 | /* Source operand is word, long or quad sized. */ | |
a31b9cea AK |
347 | #define emulate_2op_SrcV_nobyte(ctxt, _op) \ |
348 | __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") | |
6aa8b732 | 349 | |
d175226a | 350 | /* Instruction has three operands and one operand is stored in ECX register */ |
29053a60 | 351 | #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ |
7295261c AK |
352 | do { \ |
353 | unsigned long _tmp; \ | |
761441b9 AK |
354 | _type _clv = (ctxt)->src2.val; \ |
355 | _type _srcv = (ctxt)->src.val; \ | |
356 | _type _dstv = (ctxt)->dst.val; \ | |
7295261c AK |
357 | \ |
358 | __asm__ __volatile__ ( \ | |
359 | _PRE_EFLAGS("0", "5", "2") \ | |
360 | _op _suffix " %4,%1 \n" \ | |
361 | _POST_EFLAGS("0", "5", "2") \ | |
761441b9 | 362 | : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ |
7295261c AK |
363 | : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ |
364 | ); \ | |
365 | \ | |
761441b9 AK |
366 | (ctxt)->src2.val = (unsigned long) _clv; \ |
367 | (ctxt)->src2.val = (unsigned long) _srcv; \ | |
368 | (ctxt)->dst.val = (unsigned long) _dstv; \ | |
d175226a GT |
369 | } while (0) |
370 | ||
761441b9 | 371 | #define emulate_2op_cl(ctxt, _op) \ |
7295261c | 372 | do { \ |
761441b9 | 373 | switch ((ctxt)->dst.bytes) { \ |
7295261c | 374 | case 2: \ |
29053a60 | 375 | __emulate_2op_cl(ctxt, _op, "w", u16); \ |
7295261c AK |
376 | break; \ |
377 | case 4: \ | |
29053a60 | 378 | __emulate_2op_cl(ctxt, _op, "l", u32); \ |
7295261c AK |
379 | break; \ |
380 | case 8: \ | |
29053a60 | 381 | ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ |
7295261c AK |
382 | break; \ |
383 | } \ | |
d175226a GT |
384 | } while (0) |
385 | ||
d1eef45d | 386 | #define __emulate_1op(ctxt, _op, _suffix) \ |
6aa8b732 AK |
387 | do { \ |
388 | unsigned long _tmp; \ | |
389 | \ | |
dda96d8f AK |
390 | __asm__ __volatile__ ( \ |
391 | _PRE_EFLAGS("0", "3", "2") \ | |
392 | _op _suffix " %1; " \ | |
393 | _POST_EFLAGS("0", "3", "2") \ | |
d1eef45d | 394 | : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ |
dda96d8f AK |
395 | "=&r" (_tmp) \ |
396 | : "i" (EFLAGS_MASK)); \ | |
397 | } while (0) | |
398 | ||
399 | /* Instruction has only one explicit operand (no source operand). */ | |
d1eef45d | 400 | #define emulate_1op(ctxt, _op) \ |
dda96d8f | 401 | do { \ |
d1eef45d AK |
402 | switch ((ctxt)->dst.bytes) { \ |
403 | case 1: __emulate_1op(ctxt, _op, "b"); break; \ | |
404 | case 2: __emulate_1op(ctxt, _op, "w"); break; \ | |
405 | case 4: __emulate_1op(ctxt, _op, "l"); break; \ | |
406 | case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ | |
6aa8b732 AK |
407 | } \ |
408 | } while (0) | |
409 | ||
e8f2b1d6 | 410 | #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ |
f6b3597b AK |
411 | do { \ |
412 | unsigned long _tmp; \ | |
dd856efa AK |
413 | ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \ |
414 | ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \ | |
f6b3597b AK |
415 | \ |
416 | __asm__ __volatile__ ( \ | |
417 | _PRE_EFLAGS("0", "5", "1") \ | |
418 | "1: \n\t" \ | |
419 | _op _suffix " %6; " \ | |
420 | "2: \n\t" \ | |
421 | _POST_EFLAGS("0", "5", "1") \ | |
422 | ".pushsection .fixup,\"ax\" \n\t" \ | |
423 | "3: movb $1, %4 \n\t" \ | |
424 | "jmp 2b \n\t" \ | |
425 | ".popsection \n\t" \ | |
426 | _ASM_EXTABLE(1b, 3b) \ | |
e8f2b1d6 AK |
427 | : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ |
428 | "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ | |
429 | : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ | |
430 | "a" (*rax), "d" (*rdx)); \ | |
f6b3597b AK |
431 | } while (0) |
432 | ||
3f9f53b0 | 433 | /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ |
e8f2b1d6 | 434 | #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ |
7295261c | 435 | do { \ |
e8f2b1d6 | 436 | switch((ctxt)->src.bytes) { \ |
7295261c | 437 | case 1: \ |
e8f2b1d6 | 438 | __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ |
7295261c AK |
439 | break; \ |
440 | case 2: \ | |
e8f2b1d6 | 441 | __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ |
7295261c AK |
442 | break; \ |
443 | case 4: \ | |
e8f2b1d6 | 444 | __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ |
f6b3597b AK |
445 | break; \ |
446 | case 8: ON64( \ | |
e8f2b1d6 | 447 | __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ |
f6b3597b AK |
448 | break; \ |
449 | } \ | |
450 | } while (0) | |
451 | ||
8a76d7f2 JR |
452 | static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, |
453 | enum x86_intercept intercept, | |
454 | enum x86_intercept_stage stage) | |
455 | { | |
456 | struct x86_instruction_info info = { | |
457 | .intercept = intercept, | |
9dac77fa AK |
458 | .rep_prefix = ctxt->rep_prefix, |
459 | .modrm_mod = ctxt->modrm_mod, | |
460 | .modrm_reg = ctxt->modrm_reg, | |
461 | .modrm_rm = ctxt->modrm_rm, | |
462 | .src_val = ctxt->src.val64, | |
463 | .src_bytes = ctxt->src.bytes, | |
464 | .dst_bytes = ctxt->dst.bytes, | |
465 | .ad_bytes = ctxt->ad_bytes, | |
8a76d7f2 JR |
466 | .next_rip = ctxt->eip, |
467 | }; | |
468 | ||
2953538e | 469 | return ctxt->ops->intercept(ctxt, &info, stage); |
8a76d7f2 JR |
470 | } |
471 | ||
f47cfa31 AK |
472 | static void assign_masked(ulong *dest, ulong src, ulong mask) |
473 | { | |
474 | *dest = (*dest & ~mask) | (src & mask); | |
475 | } | |
476 | ||
9dac77fa | 477 | static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) |
ddcb2885 | 478 | { |
9dac77fa | 479 | return (1UL << (ctxt->ad_bytes << 3)) - 1; |
ddcb2885 HH |
480 | } |
481 | ||
f47cfa31 AK |
482 | static ulong stack_mask(struct x86_emulate_ctxt *ctxt) |
483 | { | |
484 | u16 sel; | |
485 | struct desc_struct ss; | |
486 | ||
487 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
488 | return ~0UL; | |
489 | ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); | |
490 | return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ | |
491 | } | |
492 | ||
612e89f0 AK |
493 | static int stack_size(struct x86_emulate_ctxt *ctxt) |
494 | { | |
495 | return (__fls(stack_mask(ctxt)) + 1) >> 3; | |
496 | } | |
497 | ||
6aa8b732 | 498 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 | 499 | static inline unsigned long |
9dac77fa | 500 | address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 501 | { |
9dac77fa | 502 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
e4706772 HH |
503 | return reg; |
504 | else | |
9dac77fa | 505 | return reg & ad_mask(ctxt); |
e4706772 HH |
506 | } |
507 | ||
508 | static inline unsigned long | |
9dac77fa | 509 | register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) |
e4706772 | 510 | { |
9dac77fa | 511 | return address_mask(ctxt, reg); |
e4706772 HH |
512 | } |
513 | ||
5ad105e5 AK |
514 | static void masked_increment(ulong *reg, ulong mask, int inc) |
515 | { | |
516 | assign_masked(reg, *reg + inc, mask); | |
517 | } | |
518 | ||
7a957275 | 519 | static inline void |
9dac77fa | 520 | register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) |
7a957275 | 521 | { |
5ad105e5 AK |
522 | ulong mask; |
523 | ||
9dac77fa | 524 | if (ctxt->ad_bytes == sizeof(unsigned long)) |
5ad105e5 | 525 | mask = ~0UL; |
7a957275 | 526 | else |
5ad105e5 AK |
527 | mask = ad_mask(ctxt); |
528 | masked_increment(reg, mask, inc); | |
529 | } | |
530 | ||
531 | static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) | |
532 | { | |
dd856efa | 533 | masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); |
7a957275 | 534 | } |
6aa8b732 | 535 | |
9dac77fa | 536 | static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) |
7a957275 | 537 | { |
9dac77fa | 538 | register_address_increment(ctxt, &ctxt->_eip, rel); |
7a957275 | 539 | } |
098c937b | 540 | |
56697687 AK |
541 | static u32 desc_limit_scaled(struct desc_struct *desc) |
542 | { | |
543 | u32 limit = get_desc_limit(desc); | |
544 | ||
545 | return desc->g ? (limit << 12) | 0xfff : limit; | |
546 | } | |
547 | ||
9dac77fa | 548 | static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df | 549 | { |
9dac77fa AK |
550 | ctxt->has_seg_override = true; |
551 | ctxt->seg_override = seg; | |
7a5b56df AK |
552 | } |
553 | ||
7b105ca2 | 554 | static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) |
7a5b56df AK |
555 | { |
556 | if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) | |
557 | return 0; | |
558 | ||
7b105ca2 | 559 | return ctxt->ops->get_cached_segment_base(ctxt, seg); |
7a5b56df AK |
560 | } |
561 | ||
9dac77fa | 562 | static unsigned seg_override(struct x86_emulate_ctxt *ctxt) |
7a5b56df | 563 | { |
9dac77fa | 564 | if (!ctxt->has_seg_override) |
7a5b56df AK |
565 | return 0; |
566 | ||
9dac77fa | 567 | return ctxt->seg_override; |
7a5b56df AK |
568 | } |
569 | ||
35d3d4a1 AK |
570 | static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, |
571 | u32 error, bool valid) | |
54b8486f | 572 | { |
da9cb575 AK |
573 | ctxt->exception.vector = vec; |
574 | ctxt->exception.error_code = error; | |
575 | ctxt->exception.error_code_valid = valid; | |
35d3d4a1 | 576 | return X86EMUL_PROPAGATE_FAULT; |
54b8486f GN |
577 | } |
578 | ||
3b88e41a JR |
579 | static int emulate_db(struct x86_emulate_ctxt *ctxt) |
580 | { | |
581 | return emulate_exception(ctxt, DB_VECTOR, 0, false); | |
582 | } | |
583 | ||
35d3d4a1 | 584 | static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 585 | { |
35d3d4a1 | 586 | return emulate_exception(ctxt, GP_VECTOR, err, true); |
54b8486f GN |
587 | } |
588 | ||
618ff15d AK |
589 | static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) |
590 | { | |
591 | return emulate_exception(ctxt, SS_VECTOR, err, true); | |
592 | } | |
593 | ||
35d3d4a1 | 594 | static int emulate_ud(struct x86_emulate_ctxt *ctxt) |
54b8486f | 595 | { |
35d3d4a1 | 596 | return emulate_exception(ctxt, UD_VECTOR, 0, false); |
54b8486f GN |
597 | } |
598 | ||
35d3d4a1 | 599 | static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) |
54b8486f | 600 | { |
35d3d4a1 | 601 | return emulate_exception(ctxt, TS_VECTOR, err, true); |
54b8486f GN |
602 | } |
603 | ||
34d1f490 AK |
604 | static int emulate_de(struct x86_emulate_ctxt *ctxt) |
605 | { | |
35d3d4a1 | 606 | return emulate_exception(ctxt, DE_VECTOR, 0, false); |
34d1f490 AK |
607 | } |
608 | ||
1253791d AK |
609 | static int emulate_nm(struct x86_emulate_ctxt *ctxt) |
610 | { | |
611 | return emulate_exception(ctxt, NM_VECTOR, 0, false); | |
612 | } | |
613 | ||
1aa36616 AK |
614 | static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) |
615 | { | |
616 | u16 selector; | |
617 | struct desc_struct desc; | |
618 | ||
619 | ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); | |
620 | return selector; | |
621 | } | |
622 | ||
623 | static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, | |
624 | unsigned seg) | |
625 | { | |
626 | u16 dummy; | |
627 | u32 base3; | |
628 | struct desc_struct desc; | |
629 | ||
630 | ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); | |
631 | ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); | |
632 | } | |
633 | ||
1c11b376 AK |
634 | /* |
635 | * x86 defines three classes of vector instructions: explicitly | |
636 | * aligned, explicitly unaligned, and the rest, which change behaviour | |
637 | * depending on whether they're AVX encoded or not. | |
638 | * | |
639 | * Also included is CMPXCHG16B which is not a vector instruction, yet it is | |
640 | * subject to the same check. | |
641 | */ | |
642 | static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) | |
643 | { | |
644 | if (likely(size < 16)) | |
645 | return false; | |
646 | ||
647 | if (ctxt->d & Aligned) | |
648 | return true; | |
649 | else if (ctxt->d & Unaligned) | |
650 | return false; | |
651 | else if (ctxt->d & Avx) | |
652 | return false; | |
653 | else | |
654 | return true; | |
655 | } | |
656 | ||
3d9b938e | 657 | static int __linearize(struct x86_emulate_ctxt *ctxt, |
52fd8b44 | 658 | struct segmented_address addr, |
3d9b938e | 659 | unsigned size, bool write, bool fetch, |
52fd8b44 AK |
660 | ulong *linear) |
661 | { | |
618ff15d AK |
662 | struct desc_struct desc; |
663 | bool usable; | |
52fd8b44 | 664 | ulong la; |
618ff15d | 665 | u32 lim; |
1aa36616 | 666 | u16 sel; |
618ff15d | 667 | unsigned cpl, rpl; |
52fd8b44 | 668 | |
7b105ca2 | 669 | la = seg_base(ctxt, addr.seg) + addr.ea; |
618ff15d AK |
670 | switch (ctxt->mode) { |
671 | case X86EMUL_MODE_REAL: | |
672 | break; | |
673 | case X86EMUL_MODE_PROT64: | |
674 | if (((signed long)la << 16) >> 16 != la) | |
675 | return emulate_gp(ctxt, 0); | |
676 | break; | |
677 | default: | |
1aa36616 AK |
678 | usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, |
679 | addr.seg); | |
618ff15d AK |
680 | if (!usable) |
681 | goto bad; | |
682 | /* code segment or read-only data segment */ | |
683 | if (((desc.type & 8) || !(desc.type & 2)) && write) | |
684 | goto bad; | |
685 | /* unreadable code segment */ | |
3d9b938e | 686 | if (!fetch && (desc.type & 8) && !(desc.type & 2)) |
618ff15d AK |
687 | goto bad; |
688 | lim = desc_limit_scaled(&desc); | |
689 | if ((desc.type & 8) || !(desc.type & 4)) { | |
690 | /* expand-up segment */ | |
691 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
692 | goto bad; | |
693 | } else { | |
fc058680 | 694 | /* expand-down segment */ |
618ff15d AK |
695 | if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) |
696 | goto bad; | |
697 | lim = desc.d ? 0xffffffff : 0xffff; | |
698 | if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) | |
699 | goto bad; | |
700 | } | |
717746e3 | 701 | cpl = ctxt->ops->cpl(ctxt); |
1aa36616 | 702 | rpl = sel & 3; |
618ff15d AK |
703 | cpl = max(cpl, rpl); |
704 | if (!(desc.type & 8)) { | |
705 | /* data segment */ | |
706 | if (cpl > desc.dpl) | |
707 | goto bad; | |
708 | } else if ((desc.type & 8) && !(desc.type & 4)) { | |
709 | /* nonconforming code segment */ | |
710 | if (cpl != desc.dpl) | |
711 | goto bad; | |
712 | } else if ((desc.type & 8) && (desc.type & 4)) { | |
713 | /* conforming code segment */ | |
714 | if (cpl < desc.dpl) | |
715 | goto bad; | |
716 | } | |
717 | break; | |
718 | } | |
9dac77fa | 719 | if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) |
52fd8b44 | 720 | la &= (u32)-1; |
1c11b376 AK |
721 | if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) |
722 | return emulate_gp(ctxt, 0); | |
52fd8b44 AK |
723 | *linear = la; |
724 | return X86EMUL_CONTINUE; | |
618ff15d AK |
725 | bad: |
726 | if (addr.seg == VCPU_SREG_SS) | |
727 | return emulate_ss(ctxt, addr.seg); | |
728 | else | |
729 | return emulate_gp(ctxt, addr.seg); | |
52fd8b44 AK |
730 | } |
731 | ||
3d9b938e NE |
732 | static int linearize(struct x86_emulate_ctxt *ctxt, |
733 | struct segmented_address addr, | |
734 | unsigned size, bool write, | |
735 | ulong *linear) | |
736 | { | |
737 | return __linearize(ctxt, addr, size, write, false, linear); | |
738 | } | |
739 | ||
740 | ||
3ca3ac4d AK |
741 | static int segmented_read_std(struct x86_emulate_ctxt *ctxt, |
742 | struct segmented_address addr, | |
743 | void *data, | |
744 | unsigned size) | |
745 | { | |
9fa088f4 AK |
746 | int rc; |
747 | ulong linear; | |
748 | ||
83b8795a | 749 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
750 | if (rc != X86EMUL_CONTINUE) |
751 | return rc; | |
0f65dd70 | 752 | return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); |
3ca3ac4d AK |
753 | } |
754 | ||
807941b1 TY |
755 | /* |
756 | * Fetch the next byte of the instruction being emulated which is pointed to | |
757 | * by ctxt->_eip, then increment ctxt->_eip. | |
758 | * | |
759 | * Also prefetch the remaining bytes of the instruction without crossing page | |
760 | * boundary if they are not in fetch_cache yet. | |
761 | */ | |
762 | static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) | |
62266869 | 763 | { |
9dac77fa | 764 | struct fetch_cache *fc = &ctxt->fetch; |
62266869 | 765 | int rc; |
2fb53ad8 | 766 | int size, cur_size; |
62266869 | 767 | |
807941b1 | 768 | if (ctxt->_eip == fc->end) { |
3d9b938e | 769 | unsigned long linear; |
807941b1 TY |
770 | struct segmented_address addr = { .seg = VCPU_SREG_CS, |
771 | .ea = ctxt->_eip }; | |
2fb53ad8 | 772 | cur_size = fc->end - fc->start; |
807941b1 TY |
773 | size = min(15UL - cur_size, |
774 | PAGE_SIZE - offset_in_page(ctxt->_eip)); | |
3d9b938e | 775 | rc = __linearize(ctxt, addr, size, false, true, &linear); |
7d88bb48 | 776 | if (unlikely(rc != X86EMUL_CONTINUE)) |
3d9b938e | 777 | return rc; |
ef5d75cc TY |
778 | rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, |
779 | size, &ctxt->exception); | |
7d88bb48 | 780 | if (unlikely(rc != X86EMUL_CONTINUE)) |
62266869 | 781 | return rc; |
2fb53ad8 | 782 | fc->end += size; |
62266869 | 783 | } |
807941b1 TY |
784 | *dest = fc->data[ctxt->_eip - fc->start]; |
785 | ctxt->_eip++; | |
3e2815e9 | 786 | return X86EMUL_CONTINUE; |
62266869 AK |
787 | } |
788 | ||
789 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
807941b1 | 790 | void *dest, unsigned size) |
62266869 | 791 | { |
3e2815e9 | 792 | int rc; |
62266869 | 793 | |
eb3c79e6 | 794 | /* x86 instructions are limited to 15 bytes. */ |
7d88bb48 | 795 | if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) |
eb3c79e6 | 796 | return X86EMUL_UNHANDLEABLE; |
62266869 | 797 | while (size--) { |
807941b1 | 798 | rc = do_insn_fetch_byte(ctxt, dest++); |
3e2815e9 | 799 | if (rc != X86EMUL_CONTINUE) |
62266869 AK |
800 | return rc; |
801 | } | |
3e2815e9 | 802 | return X86EMUL_CONTINUE; |
62266869 AK |
803 | } |
804 | ||
67cbc90d | 805 | /* Fetch next part of the instruction being emulated. */ |
e85a1085 | 806 | #define insn_fetch(_type, _ctxt) \ |
67cbc90d | 807 | ({ unsigned long _x; \ |
e85a1085 | 808 | rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ |
67cbc90d TY |
809 | if (rc != X86EMUL_CONTINUE) \ |
810 | goto done; \ | |
67cbc90d TY |
811 | (_type)_x; \ |
812 | }) | |
813 | ||
807941b1 TY |
814 | #define insn_fetch_arr(_arr, _size, _ctxt) \ |
815 | ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ | |
67cbc90d TY |
816 | if (rc != X86EMUL_CONTINUE) \ |
817 | goto done; \ | |
67cbc90d TY |
818 | }) |
819 | ||
1e3c5cb0 RR |
820 | /* |
821 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
822 | * pointer into the block that addresses the relevant register. | |
823 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
824 | */ | |
dd856efa | 825 | static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, |
1e3c5cb0 | 826 | int highbyte_regs) |
6aa8b732 AK |
827 | { |
828 | void *p; | |
829 | ||
6aa8b732 | 830 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) |
dd856efa AK |
831 | p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; |
832 | else | |
833 | p = reg_rmw(ctxt, modrm_reg); | |
6aa8b732 AK |
834 | return p; |
835 | } | |
836 | ||
837 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
90de84f5 | 838 | struct segmented_address addr, |
6aa8b732 AK |
839 | u16 *size, unsigned long *address, int op_bytes) |
840 | { | |
841 | int rc; | |
842 | ||
843 | if (op_bytes == 2) | |
844 | op_bytes = 3; | |
845 | *address = 0; | |
3ca3ac4d | 846 | rc = segmented_read_std(ctxt, addr, size, 2); |
1b30eaa8 | 847 | if (rc != X86EMUL_CONTINUE) |
6aa8b732 | 848 | return rc; |
30b31ab6 | 849 | addr.ea += 2; |
3ca3ac4d | 850 | rc = segmented_read_std(ctxt, addr, address, op_bytes); |
6aa8b732 AK |
851 | return rc; |
852 | } | |
853 | ||
bbe9abbd NK |
854 | static int test_cc(unsigned int condition, unsigned int flags) |
855 | { | |
856 | int rc = 0; | |
857 | ||
858 | switch ((condition & 15) >> 1) { | |
859 | case 0: /* o */ | |
860 | rc |= (flags & EFLG_OF); | |
861 | break; | |
862 | case 1: /* b/c/nae */ | |
863 | rc |= (flags & EFLG_CF); | |
864 | break; | |
865 | case 2: /* z/e */ | |
866 | rc |= (flags & EFLG_ZF); | |
867 | break; | |
868 | case 3: /* be/na */ | |
869 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
870 | break; | |
871 | case 4: /* s */ | |
872 | rc |= (flags & EFLG_SF); | |
873 | break; | |
874 | case 5: /* p/pe */ | |
875 | rc |= (flags & EFLG_PF); | |
876 | break; | |
877 | case 7: /* le/ng */ | |
878 | rc |= (flags & EFLG_ZF); | |
879 | /* fall through */ | |
880 | case 6: /* l/nge */ | |
881 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
882 | break; | |
883 | } | |
884 | ||
885 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
886 | return (!!rc ^ (condition & 1)); | |
887 | } | |
888 | ||
91ff3cb4 AK |
889 | static void fetch_register_operand(struct operand *op) |
890 | { | |
891 | switch (op->bytes) { | |
892 | case 1: | |
893 | op->val = *(u8 *)op->addr.reg; | |
894 | break; | |
895 | case 2: | |
896 | op->val = *(u16 *)op->addr.reg; | |
897 | break; | |
898 | case 4: | |
899 | op->val = *(u32 *)op->addr.reg; | |
900 | break; | |
901 | case 8: | |
902 | op->val = *(u64 *)op->addr.reg; | |
903 | break; | |
904 | } | |
905 | } | |
906 | ||
1253791d AK |
907 | static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) |
908 | { | |
909 | ctxt->ops->get_fpu(ctxt); | |
910 | switch (reg) { | |
911 | case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; | |
912 | case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; | |
913 | case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; | |
914 | case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; | |
915 | case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; | |
916 | case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; | |
917 | case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; | |
918 | case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; | |
919 | #ifdef CONFIG_X86_64 | |
920 | case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; | |
921 | case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; | |
922 | case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; | |
923 | case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; | |
924 | case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; | |
925 | case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; | |
926 | case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; | |
927 | case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; | |
928 | #endif | |
929 | default: BUG(); | |
930 | } | |
931 | ctxt->ops->put_fpu(ctxt); | |
932 | } | |
933 | ||
934 | static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, | |
935 | int reg) | |
936 | { | |
937 | ctxt->ops->get_fpu(ctxt); | |
938 | switch (reg) { | |
939 | case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; | |
940 | case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; | |
941 | case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; | |
942 | case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; | |
943 | case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; | |
944 | case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; | |
945 | case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; | |
946 | case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; | |
947 | #ifdef CONFIG_X86_64 | |
948 | case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; | |
949 | case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; | |
950 | case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; | |
951 | case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; | |
952 | case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; | |
953 | case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; | |
954 | case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; | |
955 | case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; | |
956 | #endif | |
957 | default: BUG(); | |
958 | } | |
959 | ctxt->ops->put_fpu(ctxt); | |
960 | } | |
961 | ||
cbe2c9d3 AK |
962 | static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) |
963 | { | |
964 | ctxt->ops->get_fpu(ctxt); | |
965 | switch (reg) { | |
966 | case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; | |
967 | case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; | |
968 | case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; | |
969 | case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; | |
970 | case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; | |
971 | case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; | |
972 | case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; | |
973 | case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; | |
974 | default: BUG(); | |
975 | } | |
976 | ctxt->ops->put_fpu(ctxt); | |
977 | } | |
978 | ||
979 | static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) | |
980 | { | |
981 | ctxt->ops->get_fpu(ctxt); | |
982 | switch (reg) { | |
983 | case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; | |
984 | case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; | |
985 | case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; | |
986 | case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; | |
987 | case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; | |
988 | case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; | |
989 | case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; | |
990 | case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; | |
991 | default: BUG(); | |
992 | } | |
993 | ctxt->ops->put_fpu(ctxt); | |
994 | } | |
995 | ||
1253791d | 996 | static void decode_register_operand(struct x86_emulate_ctxt *ctxt, |
2adb5ad9 | 997 | struct operand *op) |
3c118e24 | 998 | { |
9dac77fa AK |
999 | unsigned reg = ctxt->modrm_reg; |
1000 | int highbyte_regs = ctxt->rex_prefix == 0; | |
33615aa9 | 1001 | |
9dac77fa AK |
1002 | if (!(ctxt->d & ModRM)) |
1003 | reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); | |
1253791d | 1004 | |
9dac77fa | 1005 | if (ctxt->d & Sse) { |
1253791d AK |
1006 | op->type = OP_XMM; |
1007 | op->bytes = 16; | |
1008 | op->addr.xmm = reg; | |
1009 | read_sse_reg(ctxt, &op->vec_val, reg); | |
1010 | return; | |
1011 | } | |
cbe2c9d3 AK |
1012 | if (ctxt->d & Mmx) { |
1013 | reg &= 7; | |
1014 | op->type = OP_MM; | |
1015 | op->bytes = 8; | |
1016 | op->addr.mm = reg; | |
1017 | return; | |
1018 | } | |
1253791d | 1019 | |
3c118e24 | 1020 | op->type = OP_REG; |
2adb5ad9 | 1021 | if (ctxt->d & ByteOp) { |
dd856efa | 1022 | op->addr.reg = decode_register(ctxt, reg, highbyte_regs); |
3c118e24 AK |
1023 | op->bytes = 1; |
1024 | } else { | |
dd856efa | 1025 | op->addr.reg = decode_register(ctxt, reg, 0); |
9dac77fa | 1026 | op->bytes = ctxt->op_bytes; |
3c118e24 | 1027 | } |
91ff3cb4 | 1028 | fetch_register_operand(op); |
3c118e24 AK |
1029 | op->orig_val = op->val; |
1030 | } | |
1031 | ||
a6e3407b AK |
1032 | static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) |
1033 | { | |
1034 | if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) | |
1035 | ctxt->modrm_seg = VCPU_SREG_SS; | |
1036 | } | |
1037 | ||
1c73ef66 | 1038 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
2dbd0dd7 | 1039 | struct operand *op) |
1c73ef66 | 1040 | { |
1c73ef66 | 1041 | u8 sib; |
f5b4edcd | 1042 | int index_reg = 0, base_reg = 0, scale; |
3e2815e9 | 1043 | int rc = X86EMUL_CONTINUE; |
2dbd0dd7 | 1044 | ulong modrm_ea = 0; |
1c73ef66 | 1045 | |
9dac77fa AK |
1046 | if (ctxt->rex_prefix) { |
1047 | ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ | |
1048 | index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ | |
1049 | ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ | |
1c73ef66 AK |
1050 | } |
1051 | ||
9dac77fa AK |
1052 | ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; |
1053 | ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; | |
1054 | ctxt->modrm_rm |= (ctxt->modrm & 0x07); | |
1055 | ctxt->modrm_seg = VCPU_SREG_DS; | |
1c73ef66 | 1056 | |
9dac77fa | 1057 | if (ctxt->modrm_mod == 3) { |
2dbd0dd7 | 1058 | op->type = OP_REG; |
9dac77fa | 1059 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
dd856efa | 1060 | op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp); |
9dac77fa | 1061 | if (ctxt->d & Sse) { |
1253791d AK |
1062 | op->type = OP_XMM; |
1063 | op->bytes = 16; | |
9dac77fa AK |
1064 | op->addr.xmm = ctxt->modrm_rm; |
1065 | read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); | |
1253791d AK |
1066 | return rc; |
1067 | } | |
cbe2c9d3 AK |
1068 | if (ctxt->d & Mmx) { |
1069 | op->type = OP_MM; | |
1070 | op->bytes = 8; | |
1071 | op->addr.xmm = ctxt->modrm_rm & 7; | |
1072 | return rc; | |
1073 | } | |
2dbd0dd7 | 1074 | fetch_register_operand(op); |
1c73ef66 AK |
1075 | return rc; |
1076 | } | |
1077 | ||
2dbd0dd7 AK |
1078 | op->type = OP_MEM; |
1079 | ||
9dac77fa | 1080 | if (ctxt->ad_bytes == 2) { |
dd856efa AK |
1081 | unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); |
1082 | unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); | |
1083 | unsigned si = reg_read(ctxt, VCPU_REGS_RSI); | |
1084 | unsigned di = reg_read(ctxt, VCPU_REGS_RDI); | |
1c73ef66 AK |
1085 | |
1086 | /* 16-bit ModR/M decode. */ | |
9dac77fa | 1087 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1088 | case 0: |
9dac77fa | 1089 | if (ctxt->modrm_rm == 6) |
e85a1085 | 1090 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1091 | break; |
1092 | case 1: | |
e85a1085 | 1093 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1094 | break; |
1095 | case 2: | |
e85a1085 | 1096 | modrm_ea += insn_fetch(u16, ctxt); |
1c73ef66 AK |
1097 | break; |
1098 | } | |
9dac77fa | 1099 | switch (ctxt->modrm_rm) { |
1c73ef66 | 1100 | case 0: |
2dbd0dd7 | 1101 | modrm_ea += bx + si; |
1c73ef66 AK |
1102 | break; |
1103 | case 1: | |
2dbd0dd7 | 1104 | modrm_ea += bx + di; |
1c73ef66 AK |
1105 | break; |
1106 | case 2: | |
2dbd0dd7 | 1107 | modrm_ea += bp + si; |
1c73ef66 AK |
1108 | break; |
1109 | case 3: | |
2dbd0dd7 | 1110 | modrm_ea += bp + di; |
1c73ef66 AK |
1111 | break; |
1112 | case 4: | |
2dbd0dd7 | 1113 | modrm_ea += si; |
1c73ef66 AK |
1114 | break; |
1115 | case 5: | |
2dbd0dd7 | 1116 | modrm_ea += di; |
1c73ef66 AK |
1117 | break; |
1118 | case 6: | |
9dac77fa | 1119 | if (ctxt->modrm_mod != 0) |
2dbd0dd7 | 1120 | modrm_ea += bp; |
1c73ef66 AK |
1121 | break; |
1122 | case 7: | |
2dbd0dd7 | 1123 | modrm_ea += bx; |
1c73ef66 AK |
1124 | break; |
1125 | } | |
9dac77fa AK |
1126 | if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || |
1127 | (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) | |
1128 | ctxt->modrm_seg = VCPU_SREG_SS; | |
2dbd0dd7 | 1129 | modrm_ea = (u16)modrm_ea; |
1c73ef66 AK |
1130 | } else { |
1131 | /* 32/64-bit ModR/M decode. */ | |
9dac77fa | 1132 | if ((ctxt->modrm_rm & 7) == 4) { |
e85a1085 | 1133 | sib = insn_fetch(u8, ctxt); |
1c73ef66 AK |
1134 | index_reg |= (sib >> 3) & 7; |
1135 | base_reg |= sib & 7; | |
1136 | scale = sib >> 6; | |
1137 | ||
9dac77fa | 1138 | if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) |
e85a1085 | 1139 | modrm_ea += insn_fetch(s32, ctxt); |
a6e3407b | 1140 | else { |
dd856efa | 1141 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1142 | adjust_modrm_seg(ctxt, base_reg); |
1143 | } | |
dc71d0f1 | 1144 | if (index_reg != 4) |
dd856efa | 1145 | modrm_ea += reg_read(ctxt, index_reg) << scale; |
9dac77fa | 1146 | } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { |
84411d85 | 1147 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
9dac77fa | 1148 | ctxt->rip_relative = 1; |
a6e3407b AK |
1149 | } else { |
1150 | base_reg = ctxt->modrm_rm; | |
dd856efa | 1151 | modrm_ea += reg_read(ctxt, base_reg); |
a6e3407b AK |
1152 | adjust_modrm_seg(ctxt, base_reg); |
1153 | } | |
9dac77fa | 1154 | switch (ctxt->modrm_mod) { |
1c73ef66 | 1155 | case 0: |
9dac77fa | 1156 | if (ctxt->modrm_rm == 5) |
e85a1085 | 1157 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1158 | break; |
1159 | case 1: | |
e85a1085 | 1160 | modrm_ea += insn_fetch(s8, ctxt); |
1c73ef66 AK |
1161 | break; |
1162 | case 2: | |
e85a1085 | 1163 | modrm_ea += insn_fetch(s32, ctxt); |
1c73ef66 AK |
1164 | break; |
1165 | } | |
1166 | } | |
90de84f5 | 1167 | op->addr.mem.ea = modrm_ea; |
1c73ef66 AK |
1168 | done: |
1169 | return rc; | |
1170 | } | |
1171 | ||
1172 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
2dbd0dd7 | 1173 | struct operand *op) |
1c73ef66 | 1174 | { |
3e2815e9 | 1175 | int rc = X86EMUL_CONTINUE; |
1c73ef66 | 1176 | |
2dbd0dd7 | 1177 | op->type = OP_MEM; |
9dac77fa | 1178 | switch (ctxt->ad_bytes) { |
1c73ef66 | 1179 | case 2: |
e85a1085 | 1180 | op->addr.mem.ea = insn_fetch(u16, ctxt); |
1c73ef66 AK |
1181 | break; |
1182 | case 4: | |
e85a1085 | 1183 | op->addr.mem.ea = insn_fetch(u32, ctxt); |
1c73ef66 AK |
1184 | break; |
1185 | case 8: | |
e85a1085 | 1186 | op->addr.mem.ea = insn_fetch(u64, ctxt); |
1c73ef66 AK |
1187 | break; |
1188 | } | |
1189 | done: | |
1190 | return rc; | |
1191 | } | |
1192 | ||
9dac77fa | 1193 | static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) |
35c843c4 | 1194 | { |
7129eeca | 1195 | long sv = 0, mask; |
35c843c4 | 1196 | |
9dac77fa AK |
1197 | if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { |
1198 | mask = ~(ctxt->dst.bytes * 8 - 1); | |
35c843c4 | 1199 | |
9dac77fa AK |
1200 | if (ctxt->src.bytes == 2) |
1201 | sv = (s16)ctxt->src.val & (s16)mask; | |
1202 | else if (ctxt->src.bytes == 4) | |
1203 | sv = (s32)ctxt->src.val & (s32)mask; | |
35c843c4 | 1204 | |
9dac77fa | 1205 | ctxt->dst.addr.mem.ea += (sv >> 3); |
35c843c4 | 1206 | } |
ba7ff2b7 WY |
1207 | |
1208 | /* only subword offset */ | |
9dac77fa | 1209 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; |
35c843c4 WY |
1210 | } |
1211 | ||
dde7e6d1 | 1212 | static int read_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 | 1213 | unsigned long addr, void *dest, unsigned size) |
6aa8b732 | 1214 | { |
dde7e6d1 | 1215 | int rc; |
9dac77fa | 1216 | struct read_cache *mc = &ctxt->mem_read; |
6aa8b732 | 1217 | |
f23b070e XG |
1218 | if (mc->pos < mc->end) |
1219 | goto read_cached; | |
6aa8b732 | 1220 | |
f23b070e XG |
1221 | WARN_ON((mc->end + size) >= sizeof(mc->data)); |
1222 | ||
1223 | rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, | |
1224 | &ctxt->exception); | |
1225 | if (rc != X86EMUL_CONTINUE) | |
1226 | return rc; | |
1227 | ||
1228 | mc->end += size; | |
1229 | ||
1230 | read_cached: | |
1231 | memcpy(dest, mc->data + mc->pos, size); | |
1232 | mc->pos += size; | |
dde7e6d1 AK |
1233 | return X86EMUL_CONTINUE; |
1234 | } | |
6aa8b732 | 1235 | |
3ca3ac4d AK |
1236 | static int segmented_read(struct x86_emulate_ctxt *ctxt, |
1237 | struct segmented_address addr, | |
1238 | void *data, | |
1239 | unsigned size) | |
1240 | { | |
9fa088f4 AK |
1241 | int rc; |
1242 | ulong linear; | |
1243 | ||
83b8795a | 1244 | rc = linearize(ctxt, addr, size, false, &linear); |
9fa088f4 AK |
1245 | if (rc != X86EMUL_CONTINUE) |
1246 | return rc; | |
7b105ca2 | 1247 | return read_emulated(ctxt, linear, data, size); |
3ca3ac4d AK |
1248 | } |
1249 | ||
1250 | static int segmented_write(struct x86_emulate_ctxt *ctxt, | |
1251 | struct segmented_address addr, | |
1252 | const void *data, | |
1253 | unsigned size) | |
1254 | { | |
9fa088f4 AK |
1255 | int rc; |
1256 | ulong linear; | |
1257 | ||
83b8795a | 1258 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1259 | if (rc != X86EMUL_CONTINUE) |
1260 | return rc; | |
0f65dd70 AK |
1261 | return ctxt->ops->write_emulated(ctxt, linear, data, size, |
1262 | &ctxt->exception); | |
3ca3ac4d AK |
1263 | } |
1264 | ||
1265 | static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, | |
1266 | struct segmented_address addr, | |
1267 | const void *orig_data, const void *data, | |
1268 | unsigned size) | |
1269 | { | |
9fa088f4 AK |
1270 | int rc; |
1271 | ulong linear; | |
1272 | ||
83b8795a | 1273 | rc = linearize(ctxt, addr, size, true, &linear); |
9fa088f4 AK |
1274 | if (rc != X86EMUL_CONTINUE) |
1275 | return rc; | |
0f65dd70 AK |
1276 | return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, |
1277 | size, &ctxt->exception); | |
3ca3ac4d AK |
1278 | } |
1279 | ||
dde7e6d1 | 1280 | static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1281 | unsigned int size, unsigned short port, |
1282 | void *dest) | |
1283 | { | |
9dac77fa | 1284 | struct read_cache *rc = &ctxt->io_read; |
b4c6abfe | 1285 | |
dde7e6d1 | 1286 | if (rc->pos == rc->end) { /* refill pio read ahead */ |
dde7e6d1 | 1287 | unsigned int in_page, n; |
9dac77fa | 1288 | unsigned int count = ctxt->rep_prefix ? |
dd856efa | 1289 | address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; |
dde7e6d1 | 1290 | in_page = (ctxt->eflags & EFLG_DF) ? |
dd856efa AK |
1291 | offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : |
1292 | PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); | |
dde7e6d1 AK |
1293 | n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, |
1294 | count); | |
1295 | if (n == 0) | |
1296 | n = 1; | |
1297 | rc->pos = rc->end = 0; | |
7b105ca2 | 1298 | if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) |
dde7e6d1 AK |
1299 | return 0; |
1300 | rc->end = n * size; | |
6aa8b732 AK |
1301 | } |
1302 | ||
dde7e6d1 AK |
1303 | memcpy(dest, rc->data + rc->pos, size); |
1304 | rc->pos += size; | |
1305 | return 1; | |
1306 | } | |
6aa8b732 | 1307 | |
7f3d35fd KW |
1308 | static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, |
1309 | u16 index, struct desc_struct *desc) | |
1310 | { | |
1311 | struct desc_ptr dt; | |
1312 | ulong addr; | |
1313 | ||
1314 | ctxt->ops->get_idt(ctxt, &dt); | |
1315 | ||
1316 | if (dt.size < index * 8 + 7) | |
1317 | return emulate_gp(ctxt, index << 3 | 0x2); | |
1318 | ||
1319 | addr = dt.address + index * 8; | |
1320 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, | |
1321 | &ctxt->exception); | |
1322 | } | |
1323 | ||
dde7e6d1 | 1324 | static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1325 | u16 selector, struct desc_ptr *dt) |
1326 | { | |
7b105ca2 TY |
1327 | struct x86_emulate_ops *ops = ctxt->ops; |
1328 | ||
dde7e6d1 AK |
1329 | if (selector & 1 << 2) { |
1330 | struct desc_struct desc; | |
1aa36616 AK |
1331 | u16 sel; |
1332 | ||
dde7e6d1 | 1333 | memset (dt, 0, sizeof *dt); |
1aa36616 | 1334 | if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) |
dde7e6d1 | 1335 | return; |
e09d082c | 1336 | |
dde7e6d1 AK |
1337 | dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ |
1338 | dt->address = get_desc_base(&desc); | |
1339 | } else | |
4bff1e86 | 1340 | ops->get_gdt(ctxt, dt); |
dde7e6d1 | 1341 | } |
120df890 | 1342 | |
dde7e6d1 AK |
1343 | /* allowed just for 8 bytes segments */ |
1344 | static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
e919464b AK |
1345 | u16 selector, struct desc_struct *desc, |
1346 | ulong *desc_addr_p) | |
dde7e6d1 AK |
1347 | { |
1348 | struct desc_ptr dt; | |
1349 | u16 index = selector >> 3; | |
dde7e6d1 | 1350 | ulong addr; |
120df890 | 1351 | |
7b105ca2 | 1352 | get_descriptor_table_ptr(ctxt, selector, &dt); |
120df890 | 1353 | |
35d3d4a1 AK |
1354 | if (dt.size < index * 8 + 7) |
1355 | return emulate_gp(ctxt, selector & 0xfffc); | |
e09d082c | 1356 | |
e919464b | 1357 | *desc_addr_p = addr = dt.address + index * 8; |
7b105ca2 TY |
1358 | return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, |
1359 | &ctxt->exception); | |
dde7e6d1 | 1360 | } |
ef65c889 | 1361 | |
dde7e6d1 AK |
1362 | /* allowed just for 8 bytes segments */ |
1363 | static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, | |
dde7e6d1 AK |
1364 | u16 selector, struct desc_struct *desc) |
1365 | { | |
1366 | struct desc_ptr dt; | |
1367 | u16 index = selector >> 3; | |
dde7e6d1 | 1368 | ulong addr; |
6aa8b732 | 1369 | |
7b105ca2 | 1370 | get_descriptor_table_ptr(ctxt, selector, &dt); |
6e3d5dfb | 1371 | |
35d3d4a1 AK |
1372 | if (dt.size < index * 8 + 7) |
1373 | return emulate_gp(ctxt, selector & 0xfffc); | |
6aa8b732 | 1374 | |
dde7e6d1 | 1375 | addr = dt.address + index * 8; |
7b105ca2 TY |
1376 | return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, |
1377 | &ctxt->exception); | |
dde7e6d1 | 1378 | } |
c7e75a3d | 1379 | |
5601d05b | 1380 | /* Does not support long mode */ |
dde7e6d1 | 1381 | static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1382 | u16 selector, int seg) |
1383 | { | |
869be99c | 1384 | struct desc_struct seg_desc, old_desc; |
dde7e6d1 AK |
1385 | u8 dpl, rpl, cpl; |
1386 | unsigned err_vec = GP_VECTOR; | |
1387 | u32 err_code = 0; | |
1388 | bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ | |
e919464b | 1389 | ulong desc_addr; |
dde7e6d1 | 1390 | int ret; |
69f55cb1 | 1391 | |
dde7e6d1 | 1392 | memset(&seg_desc, 0, sizeof seg_desc); |
69f55cb1 | 1393 | |
dde7e6d1 AK |
1394 | if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) |
1395 | || ctxt->mode == X86EMUL_MODE_REAL) { | |
1396 | /* set real mode segment descriptor */ | |
1397 | set_desc_base(&seg_desc, selector << 4); | |
1398 | set_desc_limit(&seg_desc, 0xffff); | |
1399 | seg_desc.type = 3; | |
1400 | seg_desc.p = 1; | |
1401 | seg_desc.s = 1; | |
66b0ab8f KW |
1402 | if (ctxt->mode == X86EMUL_MODE_VM86) |
1403 | seg_desc.dpl = 3; | |
dde7e6d1 AK |
1404 | goto load; |
1405 | } | |
1406 | ||
79d5b4c3 AK |
1407 | rpl = selector & 3; |
1408 | cpl = ctxt->ops->cpl(ctxt); | |
1409 | ||
1410 | /* NULL selector is not valid for TR, CS and SS (except for long mode) */ | |
1411 | if ((seg == VCPU_SREG_CS | |
1412 | || (seg == VCPU_SREG_SS | |
1413 | && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) | |
1414 | || seg == VCPU_SREG_TR) | |
dde7e6d1 AK |
1415 | && null_selector) |
1416 | goto exception; | |
1417 | ||
1418 | /* TR should be in GDT only */ | |
1419 | if (seg == VCPU_SREG_TR && (selector & (1 << 2))) | |
1420 | goto exception; | |
1421 | ||
1422 | if (null_selector) /* for NULL selector skip all following checks */ | |
1423 | goto load; | |
1424 | ||
e919464b | 1425 | ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); |
dde7e6d1 AK |
1426 | if (ret != X86EMUL_CONTINUE) |
1427 | return ret; | |
1428 | ||
1429 | err_code = selector & 0xfffc; | |
1430 | err_vec = GP_VECTOR; | |
1431 | ||
fc058680 | 1432 | /* can't load system descriptor into segment selector */ |
dde7e6d1 AK |
1433 | if (seg <= VCPU_SREG_GS && !seg_desc.s) |
1434 | goto exception; | |
1435 | ||
1436 | if (!seg_desc.p) { | |
1437 | err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; | |
1438 | goto exception; | |
1439 | } | |
1440 | ||
dde7e6d1 | 1441 | dpl = seg_desc.dpl; |
dde7e6d1 AK |
1442 | |
1443 | switch (seg) { | |
1444 | case VCPU_SREG_SS: | |
1445 | /* | |
1446 | * segment is not a writable data segment or segment | |
1447 | * selector's RPL != CPL or segment selector's RPL != CPL | |
1448 | */ | |
1449 | if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) | |
1450 | goto exception; | |
6aa8b732 | 1451 | break; |
dde7e6d1 AK |
1452 | case VCPU_SREG_CS: |
1453 | if (!(seg_desc.type & 8)) | |
1454 | goto exception; | |
1455 | ||
1456 | if (seg_desc.type & 4) { | |
1457 | /* conforming */ | |
1458 | if (dpl > cpl) | |
1459 | goto exception; | |
1460 | } else { | |
1461 | /* nonconforming */ | |
1462 | if (rpl > cpl || dpl != cpl) | |
1463 | goto exception; | |
1464 | } | |
1465 | /* CS(RPL) <- CPL */ | |
1466 | selector = (selector & 0xfffc) | cpl; | |
6aa8b732 | 1467 | break; |
dde7e6d1 AK |
1468 | case VCPU_SREG_TR: |
1469 | if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) | |
1470 | goto exception; | |
869be99c AK |
1471 | old_desc = seg_desc; |
1472 | seg_desc.type |= 2; /* busy */ | |
1473 | ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, | |
1474 | sizeof(seg_desc), &ctxt->exception); | |
1475 | if (ret != X86EMUL_CONTINUE) | |
1476 | return ret; | |
dde7e6d1 AK |
1477 | break; |
1478 | case VCPU_SREG_LDTR: | |
1479 | if (seg_desc.s || seg_desc.type != 2) | |
1480 | goto exception; | |
1481 | break; | |
1482 | default: /* DS, ES, FS, or GS */ | |
4e62417b | 1483 | /* |
dde7e6d1 AK |
1484 | * segment is not a data or readable code segment or |
1485 | * ((segment is a data or nonconforming code segment) | |
1486 | * and (both RPL and CPL > DPL)) | |
4e62417b | 1487 | */ |
dde7e6d1 AK |
1488 | if ((seg_desc.type & 0xa) == 0x8 || |
1489 | (((seg_desc.type & 0xc) != 0xc) && | |
1490 | (rpl > dpl && cpl > dpl))) | |
1491 | goto exception; | |
6aa8b732 | 1492 | break; |
dde7e6d1 AK |
1493 | } |
1494 | ||
1495 | if (seg_desc.s) { | |
1496 | /* mark segment as accessed */ | |
1497 | seg_desc.type |= 1; | |
7b105ca2 | 1498 | ret = write_segment_descriptor(ctxt, selector, &seg_desc); |
dde7e6d1 AK |
1499 | if (ret != X86EMUL_CONTINUE) |
1500 | return ret; | |
1501 | } | |
1502 | load: | |
7b105ca2 | 1503 | ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); |
dde7e6d1 AK |
1504 | return X86EMUL_CONTINUE; |
1505 | exception: | |
1506 | emulate_exception(ctxt, err_vec, err_code, true); | |
1507 | return X86EMUL_PROPAGATE_FAULT; | |
1508 | } | |
1509 | ||
31be40b3 WY |
1510 | static void write_register_operand(struct operand *op) |
1511 | { | |
1512 | /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ | |
1513 | switch (op->bytes) { | |
1514 | case 1: | |
1515 | *(u8 *)op->addr.reg = (u8)op->val; | |
1516 | break; | |
1517 | case 2: | |
1518 | *(u16 *)op->addr.reg = (u16)op->val; | |
1519 | break; | |
1520 | case 4: | |
1521 | *op->addr.reg = (u32)op->val; | |
1522 | break; /* 64b: zero-extend */ | |
1523 | case 8: | |
1524 | *op->addr.reg = op->val; | |
1525 | break; | |
1526 | } | |
1527 | } | |
1528 | ||
adddcecf | 1529 | static int writeback(struct x86_emulate_ctxt *ctxt) |
dde7e6d1 AK |
1530 | { |
1531 | int rc; | |
dde7e6d1 | 1532 | |
9dac77fa | 1533 | switch (ctxt->dst.type) { |
dde7e6d1 | 1534 | case OP_REG: |
9dac77fa | 1535 | write_register_operand(&ctxt->dst); |
6aa8b732 | 1536 | break; |
dde7e6d1 | 1537 | case OP_MEM: |
9dac77fa | 1538 | if (ctxt->lock_prefix) |
3ca3ac4d | 1539 | rc = segmented_cmpxchg(ctxt, |
9dac77fa AK |
1540 | ctxt->dst.addr.mem, |
1541 | &ctxt->dst.orig_val, | |
1542 | &ctxt->dst.val, | |
1543 | ctxt->dst.bytes); | |
341de7e3 | 1544 | else |
3ca3ac4d | 1545 | rc = segmented_write(ctxt, |
9dac77fa AK |
1546 | ctxt->dst.addr.mem, |
1547 | &ctxt->dst.val, | |
1548 | ctxt->dst.bytes); | |
dde7e6d1 AK |
1549 | if (rc != X86EMUL_CONTINUE) |
1550 | return rc; | |
a682e354 | 1551 | break; |
1253791d | 1552 | case OP_XMM: |
9dac77fa | 1553 | write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); |
1253791d | 1554 | break; |
cbe2c9d3 AK |
1555 | case OP_MM: |
1556 | write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm); | |
1557 | break; | |
dde7e6d1 AK |
1558 | case OP_NONE: |
1559 | /* no writeback */ | |
414e6277 | 1560 | break; |
dde7e6d1 | 1561 | default: |
414e6277 | 1562 | break; |
6aa8b732 | 1563 | } |
dde7e6d1 AK |
1564 | return X86EMUL_CONTINUE; |
1565 | } | |
6aa8b732 | 1566 | |
51ddff50 | 1567 | static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) |
dde7e6d1 | 1568 | { |
4179bb02 | 1569 | struct segmented_address addr; |
0dc8d10f | 1570 | |
5ad105e5 | 1571 | rsp_increment(ctxt, -bytes); |
dd856efa | 1572 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
4179bb02 TY |
1573 | addr.seg = VCPU_SREG_SS; |
1574 | ||
51ddff50 AK |
1575 | return segmented_write(ctxt, addr, data, bytes); |
1576 | } | |
1577 | ||
1578 | static int em_push(struct x86_emulate_ctxt *ctxt) | |
1579 | { | |
4179bb02 | 1580 | /* Disable writeback. */ |
9dac77fa | 1581 | ctxt->dst.type = OP_NONE; |
51ddff50 | 1582 | return push(ctxt, &ctxt->src.val, ctxt->op_bytes); |
dde7e6d1 | 1583 | } |
69f55cb1 | 1584 | |
dde7e6d1 | 1585 | static int emulate_pop(struct x86_emulate_ctxt *ctxt, |
dde7e6d1 AK |
1586 | void *dest, int len) |
1587 | { | |
dde7e6d1 | 1588 | int rc; |
90de84f5 | 1589 | struct segmented_address addr; |
8b4caf66 | 1590 | |
dd856efa | 1591 | addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); |
90de84f5 | 1592 | addr.seg = VCPU_SREG_SS; |
3ca3ac4d | 1593 | rc = segmented_read(ctxt, addr, dest, len); |
dde7e6d1 AK |
1594 | if (rc != X86EMUL_CONTINUE) |
1595 | return rc; | |
1596 | ||
5ad105e5 | 1597 | rsp_increment(ctxt, len); |
dde7e6d1 | 1598 | return rc; |
8b4caf66 LV |
1599 | } |
1600 | ||
c54fe504 TY |
1601 | static int em_pop(struct x86_emulate_ctxt *ctxt) |
1602 | { | |
9dac77fa | 1603 | return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); |
c54fe504 TY |
1604 | } |
1605 | ||
dde7e6d1 | 1606 | static int emulate_popf(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 1607 | void *dest, int len) |
9de41573 GN |
1608 | { |
1609 | int rc; | |
dde7e6d1 AK |
1610 | unsigned long val, change_mask; |
1611 | int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 1612 | int cpl = ctxt->ops->cpl(ctxt); |
9de41573 | 1613 | |
3b9be3bf | 1614 | rc = emulate_pop(ctxt, &val, len); |
dde7e6d1 AK |
1615 | if (rc != X86EMUL_CONTINUE) |
1616 | return rc; | |
9de41573 | 1617 | |
dde7e6d1 AK |
1618 | change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF |
1619 | | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; | |
9de41573 | 1620 | |
dde7e6d1 AK |
1621 | switch(ctxt->mode) { |
1622 | case X86EMUL_MODE_PROT64: | |
1623 | case X86EMUL_MODE_PROT32: | |
1624 | case X86EMUL_MODE_PROT16: | |
1625 | if (cpl == 0) | |
1626 | change_mask |= EFLG_IOPL; | |
1627 | if (cpl <= iopl) | |
1628 | change_mask |= EFLG_IF; | |
1629 | break; | |
1630 | case X86EMUL_MODE_VM86: | |
35d3d4a1 AK |
1631 | if (iopl < 3) |
1632 | return emulate_gp(ctxt, 0); | |
dde7e6d1 AK |
1633 | change_mask |= EFLG_IF; |
1634 | break; | |
1635 | default: /* real mode */ | |
1636 | change_mask |= (EFLG_IOPL | EFLG_IF); | |
1637 | break; | |
9de41573 | 1638 | } |
dde7e6d1 AK |
1639 | |
1640 | *(unsigned long *)dest = | |
1641 | (ctxt->eflags & ~change_mask) | (val & change_mask); | |
1642 | ||
1643 | return rc; | |
9de41573 GN |
1644 | } |
1645 | ||
62aaa2f0 TY |
1646 | static int em_popf(struct x86_emulate_ctxt *ctxt) |
1647 | { | |
9dac77fa AK |
1648 | ctxt->dst.type = OP_REG; |
1649 | ctxt->dst.addr.reg = &ctxt->eflags; | |
1650 | ctxt->dst.bytes = ctxt->op_bytes; | |
1651 | return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
62aaa2f0 TY |
1652 | } |
1653 | ||
612e89f0 AK |
1654 | static int em_enter(struct x86_emulate_ctxt *ctxt) |
1655 | { | |
1656 | int rc; | |
1657 | unsigned frame_size = ctxt->src.val; | |
1658 | unsigned nesting_level = ctxt->src2.val & 31; | |
dd856efa | 1659 | ulong rbp; |
612e89f0 AK |
1660 | |
1661 | if (nesting_level) | |
1662 | return X86EMUL_UNHANDLEABLE; | |
1663 | ||
dd856efa AK |
1664 | rbp = reg_read(ctxt, VCPU_REGS_RBP); |
1665 | rc = push(ctxt, &rbp, stack_size(ctxt)); | |
612e89f0 AK |
1666 | if (rc != X86EMUL_CONTINUE) |
1667 | return rc; | |
dd856efa | 1668 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), |
612e89f0 | 1669 | stack_mask(ctxt)); |
dd856efa AK |
1670 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), |
1671 | reg_read(ctxt, VCPU_REGS_RSP) - frame_size, | |
612e89f0 AK |
1672 | stack_mask(ctxt)); |
1673 | return X86EMUL_CONTINUE; | |
1674 | } | |
1675 | ||
f47cfa31 AK |
1676 | static int em_leave(struct x86_emulate_ctxt *ctxt) |
1677 | { | |
dd856efa | 1678 | assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), |
f47cfa31 | 1679 | stack_mask(ctxt)); |
dd856efa | 1680 | return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); |
f47cfa31 AK |
1681 | } |
1682 | ||
1cd196ea | 1683 | static int em_push_sreg(struct x86_emulate_ctxt *ctxt) |
7b262e90 | 1684 | { |
1cd196ea AK |
1685 | int seg = ctxt->src2.val; |
1686 | ||
9dac77fa | 1687 | ctxt->src.val = get_segment_selector(ctxt, seg); |
7b262e90 | 1688 | |
4487b3b4 | 1689 | return em_push(ctxt); |
7b262e90 GN |
1690 | } |
1691 | ||
1cd196ea | 1692 | static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1693 | { |
1cd196ea | 1694 | int seg = ctxt->src2.val; |
dde7e6d1 AK |
1695 | unsigned long selector; |
1696 | int rc; | |
38ba30ba | 1697 | |
9dac77fa | 1698 | rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); |
dde7e6d1 AK |
1699 | if (rc != X86EMUL_CONTINUE) |
1700 | return rc; | |
1701 | ||
7b105ca2 | 1702 | rc = load_segment_descriptor(ctxt, (u16)selector, seg); |
dde7e6d1 | 1703 | return rc; |
38ba30ba GN |
1704 | } |
1705 | ||
b96a7fad | 1706 | static int em_pusha(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1707 | { |
dd856efa | 1708 | unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); |
dde7e6d1 AK |
1709 | int rc = X86EMUL_CONTINUE; |
1710 | int reg = VCPU_REGS_RAX; | |
38ba30ba | 1711 | |
dde7e6d1 AK |
1712 | while (reg <= VCPU_REGS_RDI) { |
1713 | (reg == VCPU_REGS_RSP) ? | |
dd856efa | 1714 | (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); |
38ba30ba | 1715 | |
4487b3b4 | 1716 | rc = em_push(ctxt); |
dde7e6d1 AK |
1717 | if (rc != X86EMUL_CONTINUE) |
1718 | return rc; | |
38ba30ba | 1719 | |
dde7e6d1 | 1720 | ++reg; |
38ba30ba | 1721 | } |
38ba30ba | 1722 | |
dde7e6d1 | 1723 | return rc; |
38ba30ba GN |
1724 | } |
1725 | ||
62aaa2f0 TY |
1726 | static int em_pushf(struct x86_emulate_ctxt *ctxt) |
1727 | { | |
9dac77fa | 1728 | ctxt->src.val = (unsigned long)ctxt->eflags; |
62aaa2f0 TY |
1729 | return em_push(ctxt); |
1730 | } | |
1731 | ||
b96a7fad | 1732 | static int em_popa(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1733 | { |
dde7e6d1 AK |
1734 | int rc = X86EMUL_CONTINUE; |
1735 | int reg = VCPU_REGS_RDI; | |
38ba30ba | 1736 | |
dde7e6d1 AK |
1737 | while (reg >= VCPU_REGS_RAX) { |
1738 | if (reg == VCPU_REGS_RSP) { | |
5ad105e5 | 1739 | rsp_increment(ctxt, ctxt->op_bytes); |
dde7e6d1 AK |
1740 | --reg; |
1741 | } | |
38ba30ba | 1742 | |
dd856efa | 1743 | rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); |
dde7e6d1 AK |
1744 | if (rc != X86EMUL_CONTINUE) |
1745 | break; | |
1746 | --reg; | |
38ba30ba | 1747 | } |
dde7e6d1 | 1748 | return rc; |
38ba30ba GN |
1749 | } |
1750 | ||
dd856efa | 1751 | static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 | 1752 | { |
7b105ca2 | 1753 | struct x86_emulate_ops *ops = ctxt->ops; |
5c56e1cf | 1754 | int rc; |
6e154e56 MG |
1755 | struct desc_ptr dt; |
1756 | gva_t cs_addr; | |
1757 | gva_t eip_addr; | |
1758 | u16 cs, eip; | |
6e154e56 MG |
1759 | |
1760 | /* TODO: Add limit checks */ | |
9dac77fa | 1761 | ctxt->src.val = ctxt->eflags; |
4487b3b4 | 1762 | rc = em_push(ctxt); |
5c56e1cf AK |
1763 | if (rc != X86EMUL_CONTINUE) |
1764 | return rc; | |
6e154e56 MG |
1765 | |
1766 | ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); | |
1767 | ||
9dac77fa | 1768 | ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); |
4487b3b4 | 1769 | rc = em_push(ctxt); |
5c56e1cf AK |
1770 | if (rc != X86EMUL_CONTINUE) |
1771 | return rc; | |
6e154e56 | 1772 | |
9dac77fa | 1773 | ctxt->src.val = ctxt->_eip; |
4487b3b4 | 1774 | rc = em_push(ctxt); |
5c56e1cf AK |
1775 | if (rc != X86EMUL_CONTINUE) |
1776 | return rc; | |
1777 | ||
4bff1e86 | 1778 | ops->get_idt(ctxt, &dt); |
6e154e56 MG |
1779 | |
1780 | eip_addr = dt.address + (irq << 2); | |
1781 | cs_addr = dt.address + (irq << 2) + 2; | |
1782 | ||
0f65dd70 | 1783 | rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); |
6e154e56 MG |
1784 | if (rc != X86EMUL_CONTINUE) |
1785 | return rc; | |
1786 | ||
0f65dd70 | 1787 | rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); |
6e154e56 MG |
1788 | if (rc != X86EMUL_CONTINUE) |
1789 | return rc; | |
1790 | ||
7b105ca2 | 1791 | rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); |
6e154e56 MG |
1792 | if (rc != X86EMUL_CONTINUE) |
1793 | return rc; | |
1794 | ||
9dac77fa | 1795 | ctxt->_eip = eip; |
6e154e56 MG |
1796 | |
1797 | return rc; | |
1798 | } | |
1799 | ||
dd856efa AK |
1800 | int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) |
1801 | { | |
1802 | int rc; | |
1803 | ||
1804 | invalidate_registers(ctxt); | |
1805 | rc = __emulate_int_real(ctxt, irq); | |
1806 | if (rc == X86EMUL_CONTINUE) | |
1807 | writeback_registers(ctxt); | |
1808 | return rc; | |
1809 | } | |
1810 | ||
7b105ca2 | 1811 | static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) |
6e154e56 MG |
1812 | { |
1813 | switch(ctxt->mode) { | |
1814 | case X86EMUL_MODE_REAL: | |
dd856efa | 1815 | return __emulate_int_real(ctxt, irq); |
6e154e56 MG |
1816 | case X86EMUL_MODE_VM86: |
1817 | case X86EMUL_MODE_PROT16: | |
1818 | case X86EMUL_MODE_PROT32: | |
1819 | case X86EMUL_MODE_PROT64: | |
1820 | default: | |
1821 | /* Protected mode interrupts unimplemented yet */ | |
1822 | return X86EMUL_UNHANDLEABLE; | |
1823 | } | |
1824 | } | |
1825 | ||
7b105ca2 | 1826 | static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) |
38ba30ba | 1827 | { |
dde7e6d1 AK |
1828 | int rc = X86EMUL_CONTINUE; |
1829 | unsigned long temp_eip = 0; | |
1830 | unsigned long temp_eflags = 0; | |
1831 | unsigned long cs = 0; | |
1832 | unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | | |
1833 | EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | | |
1834 | EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ | |
1835 | unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; | |
38ba30ba | 1836 | |
dde7e6d1 | 1837 | /* TODO: Add stack limit check */ |
38ba30ba | 1838 | |
9dac77fa | 1839 | rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); |
38ba30ba | 1840 | |
dde7e6d1 AK |
1841 | if (rc != X86EMUL_CONTINUE) |
1842 | return rc; | |
38ba30ba | 1843 | |
35d3d4a1 AK |
1844 | if (temp_eip & ~0xffff) |
1845 | return emulate_gp(ctxt, 0); | |
38ba30ba | 1846 | |
9dac77fa | 1847 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); |
38ba30ba | 1848 | |
dde7e6d1 AK |
1849 | if (rc != X86EMUL_CONTINUE) |
1850 | return rc; | |
38ba30ba | 1851 | |
9dac77fa | 1852 | rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); |
38ba30ba | 1853 | |
dde7e6d1 AK |
1854 | if (rc != X86EMUL_CONTINUE) |
1855 | return rc; | |
38ba30ba | 1856 | |
7b105ca2 | 1857 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
38ba30ba | 1858 | |
dde7e6d1 AK |
1859 | if (rc != X86EMUL_CONTINUE) |
1860 | return rc; | |
38ba30ba | 1861 | |
9dac77fa | 1862 | ctxt->_eip = temp_eip; |
38ba30ba | 1863 | |
38ba30ba | 1864 | |
9dac77fa | 1865 | if (ctxt->op_bytes == 4) |
dde7e6d1 | 1866 | ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); |
9dac77fa | 1867 | else if (ctxt->op_bytes == 2) { |
dde7e6d1 AK |
1868 | ctxt->eflags &= ~0xffff; |
1869 | ctxt->eflags |= temp_eflags; | |
38ba30ba | 1870 | } |
dde7e6d1 AK |
1871 | |
1872 | ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ | |
1873 | ctxt->eflags |= EFLG_RESERVED_ONE_MASK; | |
1874 | ||
1875 | return rc; | |
38ba30ba GN |
1876 | } |
1877 | ||
e01991e7 | 1878 | static int em_iret(struct x86_emulate_ctxt *ctxt) |
c37eda13 | 1879 | { |
dde7e6d1 AK |
1880 | switch(ctxt->mode) { |
1881 | case X86EMUL_MODE_REAL: | |
7b105ca2 | 1882 | return emulate_iret_real(ctxt); |
dde7e6d1 AK |
1883 | case X86EMUL_MODE_VM86: |
1884 | case X86EMUL_MODE_PROT16: | |
1885 | case X86EMUL_MODE_PROT32: | |
1886 | case X86EMUL_MODE_PROT64: | |
c37eda13 | 1887 | default: |
dde7e6d1 AK |
1888 | /* iret from protected mode unimplemented yet */ |
1889 | return X86EMUL_UNHANDLEABLE; | |
c37eda13 | 1890 | } |
c37eda13 WY |
1891 | } |
1892 | ||
d2f62766 TY |
1893 | static int em_jmp_far(struct x86_emulate_ctxt *ctxt) |
1894 | { | |
d2f62766 TY |
1895 | int rc; |
1896 | unsigned short sel; | |
1897 | ||
9dac77fa | 1898 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
d2f62766 | 1899 | |
7b105ca2 | 1900 | rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); |
d2f62766 TY |
1901 | if (rc != X86EMUL_CONTINUE) |
1902 | return rc; | |
1903 | ||
9dac77fa AK |
1904 | ctxt->_eip = 0; |
1905 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
d2f62766 TY |
1906 | return X86EMUL_CONTINUE; |
1907 | } | |
1908 | ||
51187683 | 1909 | static int em_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1910 | { |
9dac77fa | 1911 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1912 | case 0: /* rol */ |
a31b9cea | 1913 | emulate_2op_SrcB(ctxt, "rol"); |
8cdbd2c9 LV |
1914 | break; |
1915 | case 1: /* ror */ | |
a31b9cea | 1916 | emulate_2op_SrcB(ctxt, "ror"); |
8cdbd2c9 LV |
1917 | break; |
1918 | case 2: /* rcl */ | |
a31b9cea | 1919 | emulate_2op_SrcB(ctxt, "rcl"); |
8cdbd2c9 LV |
1920 | break; |
1921 | case 3: /* rcr */ | |
a31b9cea | 1922 | emulate_2op_SrcB(ctxt, "rcr"); |
8cdbd2c9 LV |
1923 | break; |
1924 | case 4: /* sal/shl */ | |
1925 | case 6: /* sal/shl */ | |
a31b9cea | 1926 | emulate_2op_SrcB(ctxt, "sal"); |
8cdbd2c9 LV |
1927 | break; |
1928 | case 5: /* shr */ | |
a31b9cea | 1929 | emulate_2op_SrcB(ctxt, "shr"); |
8cdbd2c9 LV |
1930 | break; |
1931 | case 7: /* sar */ | |
a31b9cea | 1932 | emulate_2op_SrcB(ctxt, "sar"); |
8cdbd2c9 LV |
1933 | break; |
1934 | } | |
51187683 | 1935 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1936 | } |
1937 | ||
3329ece1 AK |
1938 | static int em_not(struct x86_emulate_ctxt *ctxt) |
1939 | { | |
1940 | ctxt->dst.val = ~ctxt->dst.val; | |
1941 | return X86EMUL_CONTINUE; | |
1942 | } | |
1943 | ||
1944 | static int em_neg(struct x86_emulate_ctxt *ctxt) | |
1945 | { | |
1946 | emulate_1op(ctxt, "neg"); | |
1947 | return X86EMUL_CONTINUE; | |
1948 | } | |
1949 | ||
1950 | static int em_mul_ex(struct x86_emulate_ctxt *ctxt) | |
1951 | { | |
1952 | u8 ex = 0; | |
1953 | ||
1954 | emulate_1op_rax_rdx(ctxt, "mul", ex); | |
1955 | return X86EMUL_CONTINUE; | |
1956 | } | |
1957 | ||
1958 | static int em_imul_ex(struct x86_emulate_ctxt *ctxt) | |
1959 | { | |
1960 | u8 ex = 0; | |
1961 | ||
1962 | emulate_1op_rax_rdx(ctxt, "imul", ex); | |
1963 | return X86EMUL_CONTINUE; | |
1964 | } | |
1965 | ||
1966 | static int em_div_ex(struct x86_emulate_ctxt *ctxt) | |
8cdbd2c9 | 1967 | { |
34d1f490 | 1968 | u8 de = 0; |
8cdbd2c9 | 1969 | |
3329ece1 AK |
1970 | emulate_1op_rax_rdx(ctxt, "div", de); |
1971 | if (de) | |
1972 | return emulate_de(ctxt); | |
1973 | return X86EMUL_CONTINUE; | |
1974 | } | |
1975 | ||
1976 | static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) | |
1977 | { | |
1978 | u8 de = 0; | |
1979 | ||
1980 | emulate_1op_rax_rdx(ctxt, "idiv", de); | |
34d1f490 AK |
1981 | if (de) |
1982 | return emulate_de(ctxt); | |
8c5eee30 | 1983 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
1984 | } |
1985 | ||
51187683 | 1986 | static int em_grp45(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1987 | { |
4179bb02 | 1988 | int rc = X86EMUL_CONTINUE; |
8cdbd2c9 | 1989 | |
9dac77fa | 1990 | switch (ctxt->modrm_reg) { |
8cdbd2c9 | 1991 | case 0: /* inc */ |
d1eef45d | 1992 | emulate_1op(ctxt, "inc"); |
8cdbd2c9 LV |
1993 | break; |
1994 | case 1: /* dec */ | |
d1eef45d | 1995 | emulate_1op(ctxt, "dec"); |
8cdbd2c9 | 1996 | break; |
d19292e4 MG |
1997 | case 2: /* call near abs */ { |
1998 | long int old_eip; | |
9dac77fa AK |
1999 | old_eip = ctxt->_eip; |
2000 | ctxt->_eip = ctxt->src.val; | |
2001 | ctxt->src.val = old_eip; | |
4487b3b4 | 2002 | rc = em_push(ctxt); |
d19292e4 MG |
2003 | break; |
2004 | } | |
8cdbd2c9 | 2005 | case 4: /* jmp abs */ |
9dac77fa | 2006 | ctxt->_eip = ctxt->src.val; |
8cdbd2c9 | 2007 | break; |
d2f62766 TY |
2008 | case 5: /* jmp far */ |
2009 | rc = em_jmp_far(ctxt); | |
2010 | break; | |
8cdbd2c9 | 2011 | case 6: /* push */ |
4487b3b4 | 2012 | rc = em_push(ctxt); |
8cdbd2c9 | 2013 | break; |
8cdbd2c9 | 2014 | } |
4179bb02 | 2015 | return rc; |
8cdbd2c9 LV |
2016 | } |
2017 | ||
e0dac408 | 2018 | static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 2019 | { |
9dac77fa | 2020 | u64 old = ctxt->dst.orig_val64; |
8cdbd2c9 | 2021 | |
dd856efa AK |
2022 | if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || |
2023 | ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { | |
2024 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); | |
2025 | *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); | |
05f086f8 | 2026 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 | 2027 | } else { |
dd856efa AK |
2028 | ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | |
2029 | (u32) reg_read(ctxt, VCPU_REGS_RBX); | |
8cdbd2c9 | 2030 | |
05f086f8 | 2031 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 | 2032 | } |
1b30eaa8 | 2033 | return X86EMUL_CONTINUE; |
8cdbd2c9 LV |
2034 | } |
2035 | ||
ebda02c2 TY |
2036 | static int em_ret(struct x86_emulate_ctxt *ctxt) |
2037 | { | |
9dac77fa AK |
2038 | ctxt->dst.type = OP_REG; |
2039 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2040 | ctxt->dst.bytes = ctxt->op_bytes; | |
ebda02c2 TY |
2041 | return em_pop(ctxt); |
2042 | } | |
2043 | ||
e01991e7 | 2044 | static int em_ret_far(struct x86_emulate_ctxt *ctxt) |
a77ab5ea | 2045 | { |
a77ab5ea AK |
2046 | int rc; |
2047 | unsigned long cs; | |
2048 | ||
9dac77fa | 2049 | rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); |
1b30eaa8 | 2050 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2051 | return rc; |
9dac77fa AK |
2052 | if (ctxt->op_bytes == 4) |
2053 | ctxt->_eip = (u32)ctxt->_eip; | |
2054 | rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); | |
1b30eaa8 | 2055 | if (rc != X86EMUL_CONTINUE) |
a77ab5ea | 2056 | return rc; |
7b105ca2 | 2057 | rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); |
a77ab5ea AK |
2058 | return rc; |
2059 | } | |
2060 | ||
e940b5c2 TY |
2061 | static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) |
2062 | { | |
2063 | /* Save real source value, then compare EAX against destination. */ | |
2064 | ctxt->src.orig_val = ctxt->src.val; | |
dd856efa | 2065 | ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX); |
e940b5c2 TY |
2066 | emulate_2op_SrcV(ctxt, "cmp"); |
2067 | ||
2068 | if (ctxt->eflags & EFLG_ZF) { | |
2069 | /* Success: write back to memory. */ | |
2070 | ctxt->dst.val = ctxt->src.orig_val; | |
2071 | } else { | |
2072 | /* Failure: write the value we saw to EAX. */ | |
2073 | ctxt->dst.type = OP_REG; | |
dd856efa | 2074 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
e940b5c2 TY |
2075 | } |
2076 | return X86EMUL_CONTINUE; | |
2077 | } | |
2078 | ||
d4b4325f | 2079 | static int em_lseg(struct x86_emulate_ctxt *ctxt) |
09b5f4d3 | 2080 | { |
d4b4325f | 2081 | int seg = ctxt->src2.val; |
09b5f4d3 WY |
2082 | unsigned short sel; |
2083 | int rc; | |
2084 | ||
9dac77fa | 2085 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
09b5f4d3 | 2086 | |
7b105ca2 | 2087 | rc = load_segment_descriptor(ctxt, sel, seg); |
09b5f4d3 WY |
2088 | if (rc != X86EMUL_CONTINUE) |
2089 | return rc; | |
2090 | ||
9dac77fa | 2091 | ctxt->dst.val = ctxt->src.val; |
09b5f4d3 WY |
2092 | return rc; |
2093 | } | |
2094 | ||
7b105ca2 | 2095 | static void |
e66bb2cc | 2096 | setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, |
7b105ca2 | 2097 | struct desc_struct *cs, struct desc_struct *ss) |
e66bb2cc | 2098 | { |
e66bb2cc | 2099 | cs->l = 0; /* will be adjusted later */ |
79168fd1 | 2100 | set_desc_base(cs, 0); /* flat segment */ |
e66bb2cc | 2101 | cs->g = 1; /* 4kb granularity */ |
79168fd1 | 2102 | set_desc_limit(cs, 0xfffff); /* 4GB limit */ |
e66bb2cc AP |
2103 | cs->type = 0x0b; /* Read, Execute, Accessed */ |
2104 | cs->s = 1; | |
2105 | cs->dpl = 0; /* will be adjusted later */ | |
79168fd1 GN |
2106 | cs->p = 1; |
2107 | cs->d = 1; | |
99245b50 | 2108 | cs->avl = 0; |
e66bb2cc | 2109 | |
79168fd1 GN |
2110 | set_desc_base(ss, 0); /* flat segment */ |
2111 | set_desc_limit(ss, 0xfffff); /* 4GB limit */ | |
e66bb2cc AP |
2112 | ss->g = 1; /* 4kb granularity */ |
2113 | ss->s = 1; | |
2114 | ss->type = 0x03; /* Read/Write, Accessed */ | |
79168fd1 | 2115 | ss->d = 1; /* 32bit stack segment */ |
e66bb2cc | 2116 | ss->dpl = 0; |
79168fd1 | 2117 | ss->p = 1; |
99245b50 GN |
2118 | ss->l = 0; |
2119 | ss->avl = 0; | |
e66bb2cc AP |
2120 | } |
2121 | ||
1a18a69b AK |
2122 | static bool vendor_intel(struct x86_emulate_ctxt *ctxt) |
2123 | { | |
2124 | u32 eax, ebx, ecx, edx; | |
2125 | ||
2126 | eax = ecx = 0; | |
0017f93a AK |
2127 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2128 | return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx | |
1a18a69b AK |
2129 | && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx |
2130 | && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; | |
2131 | } | |
2132 | ||
c2226fc9 SB |
2133 | static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) |
2134 | { | |
2135 | struct x86_emulate_ops *ops = ctxt->ops; | |
2136 | u32 eax, ebx, ecx, edx; | |
2137 | ||
2138 | /* | |
2139 | * syscall should always be enabled in longmode - so only become | |
2140 | * vendor specific (cpuid) if other modes are active... | |
2141 | */ | |
2142 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
2143 | return true; | |
2144 | ||
2145 | eax = 0x00000000; | |
2146 | ecx = 0x00000000; | |
0017f93a AK |
2147 | ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
2148 | /* | |
2149 | * Intel ("GenuineIntel") | |
2150 | * remark: Intel CPUs only support "syscall" in 64bit | |
2151 | * longmode. Also an 64bit guest with a | |
2152 | * 32bit compat-app running will #UD !! While this | |
2153 | * behaviour can be fixed (by emulating) into AMD | |
2154 | * response - CPUs of AMD can't behave like Intel. | |
2155 | */ | |
2156 | if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && | |
2157 | ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && | |
2158 | edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) | |
2159 | return false; | |
2160 | ||
2161 | /* AMD ("AuthenticAMD") */ | |
2162 | if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && | |
2163 | ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && | |
2164 | edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) | |
2165 | return true; | |
2166 | ||
2167 | /* AMD ("AMDisbetter!") */ | |
2168 | if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && | |
2169 | ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && | |
2170 | edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) | |
2171 | return true; | |
c2226fc9 SB |
2172 | |
2173 | /* default: (not Intel, not AMD), apply Intel's stricter rules... */ | |
2174 | return false; | |
2175 | } | |
2176 | ||
e01991e7 | 2177 | static int em_syscall(struct x86_emulate_ctxt *ctxt) |
e66bb2cc | 2178 | { |
7b105ca2 | 2179 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2180 | struct desc_struct cs, ss; |
e66bb2cc | 2181 | u64 msr_data; |
79168fd1 | 2182 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2183 | u64 efer = 0; |
e66bb2cc AP |
2184 | |
2185 | /* syscall is not available in real mode */ | |
2e901c4c | 2186 | if (ctxt->mode == X86EMUL_MODE_REAL || |
35d3d4a1 AK |
2187 | ctxt->mode == X86EMUL_MODE_VM86) |
2188 | return emulate_ud(ctxt); | |
e66bb2cc | 2189 | |
c2226fc9 SB |
2190 | if (!(em_syscall_is_enabled(ctxt))) |
2191 | return emulate_ud(ctxt); | |
2192 | ||
c2ad2bb3 | 2193 | ops->get_msr(ctxt, MSR_EFER, &efer); |
7b105ca2 | 2194 | setup_syscalls_segments(ctxt, &cs, &ss); |
e66bb2cc | 2195 | |
c2226fc9 SB |
2196 | if (!(efer & EFER_SCE)) |
2197 | return emulate_ud(ctxt); | |
2198 | ||
717746e3 | 2199 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
e66bb2cc | 2200 | msr_data >>= 32; |
79168fd1 GN |
2201 | cs_sel = (u16)(msr_data & 0xfffc); |
2202 | ss_sel = (u16)(msr_data + 8); | |
e66bb2cc | 2203 | |
c2ad2bb3 | 2204 | if (efer & EFER_LMA) { |
79168fd1 | 2205 | cs.d = 0; |
e66bb2cc AP |
2206 | cs.l = 1; |
2207 | } | |
1aa36616 AK |
2208 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2209 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
e66bb2cc | 2210 | |
dd856efa | 2211 | *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; |
c2ad2bb3 | 2212 | if (efer & EFER_LMA) { |
e66bb2cc | 2213 | #ifdef CONFIG_X86_64 |
dd856efa | 2214 | *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF; |
e66bb2cc | 2215 | |
717746e3 | 2216 | ops->get_msr(ctxt, |
3fb1b5db GN |
2217 | ctxt->mode == X86EMUL_MODE_PROT64 ? |
2218 | MSR_LSTAR : MSR_CSTAR, &msr_data); | |
9dac77fa | 2219 | ctxt->_eip = msr_data; |
e66bb2cc | 2220 | |
717746e3 | 2221 | ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); |
e66bb2cc AP |
2222 | ctxt->eflags &= ~(msr_data | EFLG_RF); |
2223 | #endif | |
2224 | } else { | |
2225 | /* legacy mode */ | |
717746e3 | 2226 | ops->get_msr(ctxt, MSR_STAR, &msr_data); |
9dac77fa | 2227 | ctxt->_eip = (u32)msr_data; |
e66bb2cc AP |
2228 | |
2229 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
2230 | } | |
2231 | ||
e54cfa97 | 2232 | return X86EMUL_CONTINUE; |
e66bb2cc AP |
2233 | } |
2234 | ||
e01991e7 | 2235 | static int em_sysenter(struct x86_emulate_ctxt *ctxt) |
8c604352 | 2236 | { |
7b105ca2 | 2237 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2238 | struct desc_struct cs, ss; |
8c604352 | 2239 | u64 msr_data; |
79168fd1 | 2240 | u16 cs_sel, ss_sel; |
c2ad2bb3 | 2241 | u64 efer = 0; |
8c604352 | 2242 | |
7b105ca2 | 2243 | ops->get_msr(ctxt, MSR_EFER, &efer); |
a0044755 | 2244 | /* inject #GP if in real mode */ |
35d3d4a1 AK |
2245 | if (ctxt->mode == X86EMUL_MODE_REAL) |
2246 | return emulate_gp(ctxt, 0); | |
8c604352 | 2247 | |
1a18a69b AK |
2248 | /* |
2249 | * Not recognized on AMD in compat mode (but is recognized in legacy | |
2250 | * mode). | |
2251 | */ | |
2252 | if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) | |
2253 | && !vendor_intel(ctxt)) | |
2254 | return emulate_ud(ctxt); | |
2255 | ||
8c604352 AP |
2256 | /* XXX sysenter/sysexit have not been tested in 64bit mode. |
2257 | * Therefore, we inject an #UD. | |
2258 | */ | |
35d3d4a1 AK |
2259 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
2260 | return emulate_ud(ctxt); | |
8c604352 | 2261 | |
7b105ca2 | 2262 | setup_syscalls_segments(ctxt, &cs, &ss); |
8c604352 | 2263 | |
717746e3 | 2264 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
8c604352 AP |
2265 | switch (ctxt->mode) { |
2266 | case X86EMUL_MODE_PROT32: | |
35d3d4a1 AK |
2267 | if ((msr_data & 0xfffc) == 0x0) |
2268 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2269 | break; |
2270 | case X86EMUL_MODE_PROT64: | |
35d3d4a1 AK |
2271 | if (msr_data == 0x0) |
2272 | return emulate_gp(ctxt, 0); | |
8c604352 AP |
2273 | break; |
2274 | } | |
2275 | ||
2276 | ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); | |
79168fd1 GN |
2277 | cs_sel = (u16)msr_data; |
2278 | cs_sel &= ~SELECTOR_RPL_MASK; | |
2279 | ss_sel = cs_sel + 8; | |
2280 | ss_sel &= ~SELECTOR_RPL_MASK; | |
c2ad2bb3 | 2281 | if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { |
79168fd1 | 2282 | cs.d = 0; |
8c604352 AP |
2283 | cs.l = 1; |
2284 | } | |
2285 | ||
1aa36616 AK |
2286 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2287 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
8c604352 | 2288 | |
717746e3 | 2289 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); |
9dac77fa | 2290 | ctxt->_eip = msr_data; |
8c604352 | 2291 | |
717746e3 | 2292 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); |
dd856efa | 2293 | *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; |
8c604352 | 2294 | |
e54cfa97 | 2295 | return X86EMUL_CONTINUE; |
8c604352 AP |
2296 | } |
2297 | ||
e01991e7 | 2298 | static int em_sysexit(struct x86_emulate_ctxt *ctxt) |
4668f050 | 2299 | { |
7b105ca2 | 2300 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2301 | struct desc_struct cs, ss; |
4668f050 AP |
2302 | u64 msr_data; |
2303 | int usermode; | |
1249b96e | 2304 | u16 cs_sel = 0, ss_sel = 0; |
4668f050 | 2305 | |
a0044755 GN |
2306 | /* inject #GP if in real mode or Virtual 8086 mode */ |
2307 | if (ctxt->mode == X86EMUL_MODE_REAL || | |
35d3d4a1 AK |
2308 | ctxt->mode == X86EMUL_MODE_VM86) |
2309 | return emulate_gp(ctxt, 0); | |
4668f050 | 2310 | |
7b105ca2 | 2311 | setup_syscalls_segments(ctxt, &cs, &ss); |
4668f050 | 2312 | |
9dac77fa | 2313 | if ((ctxt->rex_prefix & 0x8) != 0x0) |
4668f050 AP |
2314 | usermode = X86EMUL_MODE_PROT64; |
2315 | else | |
2316 | usermode = X86EMUL_MODE_PROT32; | |
2317 | ||
2318 | cs.dpl = 3; | |
2319 | ss.dpl = 3; | |
717746e3 | 2320 | ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); |
4668f050 AP |
2321 | switch (usermode) { |
2322 | case X86EMUL_MODE_PROT32: | |
79168fd1 | 2323 | cs_sel = (u16)(msr_data + 16); |
35d3d4a1 AK |
2324 | if ((msr_data & 0xfffc) == 0x0) |
2325 | return emulate_gp(ctxt, 0); | |
79168fd1 | 2326 | ss_sel = (u16)(msr_data + 24); |
4668f050 AP |
2327 | break; |
2328 | case X86EMUL_MODE_PROT64: | |
79168fd1 | 2329 | cs_sel = (u16)(msr_data + 32); |
35d3d4a1 AK |
2330 | if (msr_data == 0x0) |
2331 | return emulate_gp(ctxt, 0); | |
79168fd1 GN |
2332 | ss_sel = cs_sel + 8; |
2333 | cs.d = 0; | |
4668f050 AP |
2334 | cs.l = 1; |
2335 | break; | |
2336 | } | |
79168fd1 GN |
2337 | cs_sel |= SELECTOR_RPL_MASK; |
2338 | ss_sel |= SELECTOR_RPL_MASK; | |
4668f050 | 2339 | |
1aa36616 AK |
2340 | ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); |
2341 | ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); | |
4668f050 | 2342 | |
dd856efa AK |
2343 | ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); |
2344 | *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); | |
4668f050 | 2345 | |
e54cfa97 | 2346 | return X86EMUL_CONTINUE; |
4668f050 AP |
2347 | } |
2348 | ||
7b105ca2 | 2349 | static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) |
f850e2e6 GN |
2350 | { |
2351 | int iopl; | |
2352 | if (ctxt->mode == X86EMUL_MODE_REAL) | |
2353 | return false; | |
2354 | if (ctxt->mode == X86EMUL_MODE_VM86) | |
2355 | return true; | |
2356 | iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
7b105ca2 | 2357 | return ctxt->ops->cpl(ctxt) > iopl; |
f850e2e6 GN |
2358 | } |
2359 | ||
2360 | static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2361 | u16 port, u16 len) |
2362 | { | |
7b105ca2 | 2363 | struct x86_emulate_ops *ops = ctxt->ops; |
79168fd1 | 2364 | struct desc_struct tr_seg; |
5601d05b | 2365 | u32 base3; |
f850e2e6 | 2366 | int r; |
1aa36616 | 2367 | u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; |
f850e2e6 | 2368 | unsigned mask = (1 << len) - 1; |
5601d05b | 2369 | unsigned long base; |
f850e2e6 | 2370 | |
1aa36616 | 2371 | ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); |
79168fd1 | 2372 | if (!tr_seg.p) |
f850e2e6 | 2373 | return false; |
79168fd1 | 2374 | if (desc_limit_scaled(&tr_seg) < 103) |
f850e2e6 | 2375 | return false; |
5601d05b GN |
2376 | base = get_desc_base(&tr_seg); |
2377 | #ifdef CONFIG_X86_64 | |
2378 | base |= ((u64)base3) << 32; | |
2379 | #endif | |
0f65dd70 | 2380 | r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); |
f850e2e6 GN |
2381 | if (r != X86EMUL_CONTINUE) |
2382 | return false; | |
79168fd1 | 2383 | if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) |
f850e2e6 | 2384 | return false; |
0f65dd70 | 2385 | r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); |
f850e2e6 GN |
2386 | if (r != X86EMUL_CONTINUE) |
2387 | return false; | |
2388 | if ((perm >> bit_idx) & mask) | |
2389 | return false; | |
2390 | return true; | |
2391 | } | |
2392 | ||
2393 | static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, | |
f850e2e6 GN |
2394 | u16 port, u16 len) |
2395 | { | |
4fc40f07 GN |
2396 | if (ctxt->perm_ok) |
2397 | return true; | |
2398 | ||
7b105ca2 TY |
2399 | if (emulator_bad_iopl(ctxt)) |
2400 | if (!emulator_io_port_access_allowed(ctxt, port, len)) | |
f850e2e6 | 2401 | return false; |
4fc40f07 GN |
2402 | |
2403 | ctxt->perm_ok = true; | |
2404 | ||
f850e2e6 GN |
2405 | return true; |
2406 | } | |
2407 | ||
38ba30ba | 2408 | static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, |
38ba30ba GN |
2409 | struct tss_segment_16 *tss) |
2410 | { | |
9dac77fa | 2411 | tss->ip = ctxt->_eip; |
38ba30ba | 2412 | tss->flag = ctxt->eflags; |
dd856efa AK |
2413 | tss->ax = reg_read(ctxt, VCPU_REGS_RAX); |
2414 | tss->cx = reg_read(ctxt, VCPU_REGS_RCX); | |
2415 | tss->dx = reg_read(ctxt, VCPU_REGS_RDX); | |
2416 | tss->bx = reg_read(ctxt, VCPU_REGS_RBX); | |
2417 | tss->sp = reg_read(ctxt, VCPU_REGS_RSP); | |
2418 | tss->bp = reg_read(ctxt, VCPU_REGS_RBP); | |
2419 | tss->si = reg_read(ctxt, VCPU_REGS_RSI); | |
2420 | tss->di = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2421 | |
1aa36616 AK |
2422 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2423 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2424 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2425 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2426 | tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2427 | } |
2428 | ||
2429 | static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2430 | struct tss_segment_16 *tss) |
2431 | { | |
38ba30ba GN |
2432 | int ret; |
2433 | ||
9dac77fa | 2434 | ctxt->_eip = tss->ip; |
38ba30ba | 2435 | ctxt->eflags = tss->flag | 2; |
dd856efa AK |
2436 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; |
2437 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; | |
2438 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; | |
2439 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; | |
2440 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; | |
2441 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; | |
2442 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; | |
2443 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; | |
38ba30ba GN |
2444 | |
2445 | /* | |
2446 | * SDM says that segment selectors are loaded before segment | |
2447 | * descriptors | |
2448 | */ | |
1aa36616 AK |
2449 | set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); |
2450 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2451 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2452 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2453 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
38ba30ba GN |
2454 | |
2455 | /* | |
fc058680 | 2456 | * Now load segment descriptors. If fault happens at this stage |
38ba30ba GN |
2457 | * it is handled in a context of new task |
2458 | */ | |
7b105ca2 | 2459 | ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); |
38ba30ba GN |
2460 | if (ret != X86EMUL_CONTINUE) |
2461 | return ret; | |
7b105ca2 | 2462 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2463 | if (ret != X86EMUL_CONTINUE) |
2464 | return ret; | |
7b105ca2 | 2465 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2466 | if (ret != X86EMUL_CONTINUE) |
2467 | return ret; | |
7b105ca2 | 2468 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2469 | if (ret != X86EMUL_CONTINUE) |
2470 | return ret; | |
7b105ca2 | 2471 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2472 | if (ret != X86EMUL_CONTINUE) |
2473 | return ret; | |
2474 | ||
2475 | return X86EMUL_CONTINUE; | |
2476 | } | |
2477 | ||
2478 | static int task_switch_16(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2479 | u16 tss_selector, u16 old_tss_sel, |
2480 | ulong old_tss_base, struct desc_struct *new_desc) | |
2481 | { | |
7b105ca2 | 2482 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2483 | struct tss_segment_16 tss_seg; |
2484 | int ret; | |
bcc55cba | 2485 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2486 | |
0f65dd70 | 2487 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2488 | &ctxt->exception); |
db297e3d | 2489 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2490 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2491 | return ret; |
38ba30ba | 2492 | |
7b105ca2 | 2493 | save_state_to_tss16(ctxt, &tss_seg); |
38ba30ba | 2494 | |
0f65dd70 | 2495 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2496 | &ctxt->exception); |
db297e3d | 2497 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2498 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2499 | return ret; |
38ba30ba | 2500 | |
0f65dd70 | 2501 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2502 | &ctxt->exception); |
db297e3d | 2503 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2504 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2505 | return ret; |
38ba30ba GN |
2506 | |
2507 | if (old_tss_sel != 0xffff) { | |
2508 | tss_seg.prev_task_link = old_tss_sel; | |
2509 | ||
0f65dd70 | 2510 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2511 | &tss_seg.prev_task_link, |
2512 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2513 | &ctxt->exception); |
db297e3d | 2514 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2515 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2516 | return ret; |
38ba30ba GN |
2517 | } |
2518 | ||
7b105ca2 | 2519 | return load_state_from_tss16(ctxt, &tss_seg); |
38ba30ba GN |
2520 | } |
2521 | ||
2522 | static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2523 | struct tss_segment_32 *tss) |
2524 | { | |
7b105ca2 | 2525 | tss->cr3 = ctxt->ops->get_cr(ctxt, 3); |
9dac77fa | 2526 | tss->eip = ctxt->_eip; |
38ba30ba | 2527 | tss->eflags = ctxt->eflags; |
dd856efa AK |
2528 | tss->eax = reg_read(ctxt, VCPU_REGS_RAX); |
2529 | tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
2530 | tss->edx = reg_read(ctxt, VCPU_REGS_RDX); | |
2531 | tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); | |
2532 | tss->esp = reg_read(ctxt, VCPU_REGS_RSP); | |
2533 | tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); | |
2534 | tss->esi = reg_read(ctxt, VCPU_REGS_RSI); | |
2535 | tss->edi = reg_read(ctxt, VCPU_REGS_RDI); | |
38ba30ba | 2536 | |
1aa36616 AK |
2537 | tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); |
2538 | tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); | |
2539 | tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); | |
2540 | tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); | |
2541 | tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); | |
2542 | tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); | |
2543 | tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); | |
38ba30ba GN |
2544 | } |
2545 | ||
2546 | static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2547 | struct tss_segment_32 *tss) |
2548 | { | |
38ba30ba GN |
2549 | int ret; |
2550 | ||
7b105ca2 | 2551 | if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) |
35d3d4a1 | 2552 | return emulate_gp(ctxt, 0); |
9dac77fa | 2553 | ctxt->_eip = tss->eip; |
38ba30ba | 2554 | ctxt->eflags = tss->eflags | 2; |
4cee4798 KW |
2555 | |
2556 | /* General purpose registers */ | |
dd856efa AK |
2557 | *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; |
2558 | *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; | |
2559 | *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; | |
2560 | *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; | |
2561 | *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; | |
2562 | *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; | |
2563 | *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; | |
2564 | *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; | |
38ba30ba GN |
2565 | |
2566 | /* | |
2567 | * SDM says that segment selectors are loaded before segment | |
2568 | * descriptors | |
2569 | */ | |
1aa36616 AK |
2570 | set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
2571 | set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); | |
2572 | set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); | |
2573 | set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); | |
2574 | set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); | |
2575 | set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); | |
2576 | set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); | |
38ba30ba | 2577 | |
4cee4798 KW |
2578 | /* |
2579 | * If we're switching between Protected Mode and VM86, we need to make | |
2580 | * sure to update the mode before loading the segment descriptors so | |
2581 | * that the selectors are interpreted correctly. | |
2582 | * | |
2583 | * Need to get rflags to the vcpu struct immediately because it | |
2584 | * influences the CPL which is checked at least when loading the segment | |
2585 | * descriptors and when pushing an error code to the new kernel stack. | |
2586 | * | |
2587 | * TODO Introduce a separate ctxt->ops->set_cpl callback | |
2588 | */ | |
2589 | if (ctxt->eflags & X86_EFLAGS_VM) | |
2590 | ctxt->mode = X86EMUL_MODE_VM86; | |
2591 | else | |
2592 | ctxt->mode = X86EMUL_MODE_PROT32; | |
2593 | ||
2594 | ctxt->ops->set_rflags(ctxt, ctxt->eflags); | |
2595 | ||
38ba30ba GN |
2596 | /* |
2597 | * Now load segment descriptors. If fault happenes at this stage | |
2598 | * it is handled in a context of new task | |
2599 | */ | |
7b105ca2 | 2600 | ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); |
38ba30ba GN |
2601 | if (ret != X86EMUL_CONTINUE) |
2602 | return ret; | |
7b105ca2 | 2603 | ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); |
38ba30ba GN |
2604 | if (ret != X86EMUL_CONTINUE) |
2605 | return ret; | |
7b105ca2 | 2606 | ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); |
38ba30ba GN |
2607 | if (ret != X86EMUL_CONTINUE) |
2608 | return ret; | |
7b105ca2 | 2609 | ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); |
38ba30ba GN |
2610 | if (ret != X86EMUL_CONTINUE) |
2611 | return ret; | |
7b105ca2 | 2612 | ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); |
38ba30ba GN |
2613 | if (ret != X86EMUL_CONTINUE) |
2614 | return ret; | |
7b105ca2 | 2615 | ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); |
38ba30ba GN |
2616 | if (ret != X86EMUL_CONTINUE) |
2617 | return ret; | |
7b105ca2 | 2618 | ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); |
38ba30ba GN |
2619 | if (ret != X86EMUL_CONTINUE) |
2620 | return ret; | |
2621 | ||
2622 | return X86EMUL_CONTINUE; | |
2623 | } | |
2624 | ||
2625 | static int task_switch_32(struct x86_emulate_ctxt *ctxt, | |
38ba30ba GN |
2626 | u16 tss_selector, u16 old_tss_sel, |
2627 | ulong old_tss_base, struct desc_struct *new_desc) | |
2628 | { | |
7b105ca2 | 2629 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2630 | struct tss_segment_32 tss_seg; |
2631 | int ret; | |
bcc55cba | 2632 | u32 new_tss_base = get_desc_base(new_desc); |
38ba30ba | 2633 | |
0f65dd70 | 2634 | ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2635 | &ctxt->exception); |
db297e3d | 2636 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2637 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2638 | return ret; |
38ba30ba | 2639 | |
7b105ca2 | 2640 | save_state_to_tss32(ctxt, &tss_seg); |
38ba30ba | 2641 | |
0f65dd70 | 2642 | ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2643 | &ctxt->exception); |
db297e3d | 2644 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2645 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2646 | return ret; |
38ba30ba | 2647 | |
0f65dd70 | 2648 | ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, |
bcc55cba | 2649 | &ctxt->exception); |
db297e3d | 2650 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2651 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2652 | return ret; |
38ba30ba GN |
2653 | |
2654 | if (old_tss_sel != 0xffff) { | |
2655 | tss_seg.prev_task_link = old_tss_sel; | |
2656 | ||
0f65dd70 | 2657 | ret = ops->write_std(ctxt, new_tss_base, |
38ba30ba GN |
2658 | &tss_seg.prev_task_link, |
2659 | sizeof tss_seg.prev_task_link, | |
0f65dd70 | 2660 | &ctxt->exception); |
db297e3d | 2661 | if (ret != X86EMUL_CONTINUE) |
38ba30ba | 2662 | /* FIXME: need to provide precise fault address */ |
38ba30ba | 2663 | return ret; |
38ba30ba GN |
2664 | } |
2665 | ||
7b105ca2 | 2666 | return load_state_from_tss32(ctxt, &tss_seg); |
38ba30ba GN |
2667 | } |
2668 | ||
2669 | static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2670 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2671 | bool has_error_code, u32 error_code) |
38ba30ba | 2672 | { |
7b105ca2 | 2673 | struct x86_emulate_ops *ops = ctxt->ops; |
38ba30ba GN |
2674 | struct desc_struct curr_tss_desc, next_tss_desc; |
2675 | int ret; | |
1aa36616 | 2676 | u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); |
38ba30ba | 2677 | ulong old_tss_base = |
4bff1e86 | 2678 | ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); |
ceffb459 | 2679 | u32 desc_limit; |
e919464b | 2680 | ulong desc_addr; |
38ba30ba GN |
2681 | |
2682 | /* FIXME: old_tss_base == ~0 ? */ | |
2683 | ||
e919464b | 2684 | ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); |
38ba30ba GN |
2685 | if (ret != X86EMUL_CONTINUE) |
2686 | return ret; | |
e919464b | 2687 | ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); |
38ba30ba GN |
2688 | if (ret != X86EMUL_CONTINUE) |
2689 | return ret; | |
2690 | ||
2691 | /* FIXME: check that next_tss_desc is tss */ | |
2692 | ||
7f3d35fd KW |
2693 | /* |
2694 | * Check privileges. The three cases are task switch caused by... | |
2695 | * | |
2696 | * 1. jmp/call/int to task gate: Check against DPL of the task gate | |
2697 | * 2. Exception/IRQ/iret: No check is performed | |
fc058680 | 2698 | * 3. jmp/call to TSS: Check against DPL of the TSS |
7f3d35fd KW |
2699 | */ |
2700 | if (reason == TASK_SWITCH_GATE) { | |
2701 | if (idt_index != -1) { | |
2702 | /* Software interrupts */ | |
2703 | struct desc_struct task_gate_desc; | |
2704 | int dpl; | |
2705 | ||
2706 | ret = read_interrupt_descriptor(ctxt, idt_index, | |
2707 | &task_gate_desc); | |
2708 | if (ret != X86EMUL_CONTINUE) | |
2709 | return ret; | |
2710 | ||
2711 | dpl = task_gate_desc.dpl; | |
2712 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2713 | return emulate_gp(ctxt, (idt_index << 3) | 0x2); | |
2714 | } | |
2715 | } else if (reason != TASK_SWITCH_IRET) { | |
2716 | int dpl = next_tss_desc.dpl; | |
2717 | if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) | |
2718 | return emulate_gp(ctxt, tss_selector); | |
38ba30ba GN |
2719 | } |
2720 | ||
7f3d35fd | 2721 | |
ceffb459 GN |
2722 | desc_limit = desc_limit_scaled(&next_tss_desc); |
2723 | if (!next_tss_desc.p || | |
2724 | ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || | |
2725 | desc_limit < 0x2b)) { | |
54b8486f | 2726 | emulate_ts(ctxt, tss_selector & 0xfffc); |
38ba30ba GN |
2727 | return X86EMUL_PROPAGATE_FAULT; |
2728 | } | |
2729 | ||
2730 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
2731 | curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ | |
7b105ca2 | 2732 | write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); |
38ba30ba GN |
2733 | } |
2734 | ||
2735 | if (reason == TASK_SWITCH_IRET) | |
2736 | ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; | |
2737 | ||
2738 | /* set back link to prev task only if NT bit is set in eflags | |
fc058680 | 2739 | note that old_tss_sel is not used after this point */ |
38ba30ba GN |
2740 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) |
2741 | old_tss_sel = 0xffff; | |
2742 | ||
2743 | if (next_tss_desc.type & 8) | |
7b105ca2 | 2744 | ret = task_switch_32(ctxt, tss_selector, old_tss_sel, |
38ba30ba GN |
2745 | old_tss_base, &next_tss_desc); |
2746 | else | |
7b105ca2 | 2747 | ret = task_switch_16(ctxt, tss_selector, old_tss_sel, |
38ba30ba | 2748 | old_tss_base, &next_tss_desc); |
0760d448 JK |
2749 | if (ret != X86EMUL_CONTINUE) |
2750 | return ret; | |
38ba30ba GN |
2751 | |
2752 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) | |
2753 | ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; | |
2754 | ||
2755 | if (reason != TASK_SWITCH_IRET) { | |
2756 | next_tss_desc.type |= (1 << 1); /* set busy flag */ | |
7b105ca2 | 2757 | write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); |
38ba30ba GN |
2758 | } |
2759 | ||
717746e3 | 2760 | ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); |
1aa36616 | 2761 | ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); |
38ba30ba | 2762 | |
e269fb21 | 2763 | if (has_error_code) { |
9dac77fa AK |
2764 | ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; |
2765 | ctxt->lock_prefix = 0; | |
2766 | ctxt->src.val = (unsigned long) error_code; | |
4487b3b4 | 2767 | ret = em_push(ctxt); |
e269fb21 JK |
2768 | } |
2769 | ||
38ba30ba GN |
2770 | return ret; |
2771 | } | |
2772 | ||
2773 | int emulator_task_switch(struct x86_emulate_ctxt *ctxt, | |
7f3d35fd | 2774 | u16 tss_selector, int idt_index, int reason, |
e269fb21 | 2775 | bool has_error_code, u32 error_code) |
38ba30ba | 2776 | { |
38ba30ba GN |
2777 | int rc; |
2778 | ||
dd856efa | 2779 | invalidate_registers(ctxt); |
9dac77fa AK |
2780 | ctxt->_eip = ctxt->eip; |
2781 | ctxt->dst.type = OP_NONE; | |
38ba30ba | 2782 | |
7f3d35fd | 2783 | rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, |
e269fb21 | 2784 | has_error_code, error_code); |
38ba30ba | 2785 | |
dd856efa | 2786 | if (rc == X86EMUL_CONTINUE) { |
9dac77fa | 2787 | ctxt->eip = ctxt->_eip; |
dd856efa AK |
2788 | writeback_registers(ctxt); |
2789 | } | |
38ba30ba | 2790 | |
a0c0ab2f | 2791 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
38ba30ba GN |
2792 | } |
2793 | ||
90de84f5 | 2794 | static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, |
d9271123 | 2795 | int reg, struct operand *op) |
a682e354 | 2796 | { |
a682e354 GN |
2797 | int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; |
2798 | ||
dd856efa AK |
2799 | register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes); |
2800 | op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg)); | |
90de84f5 | 2801 | op->addr.mem.seg = seg; |
a682e354 GN |
2802 | } |
2803 | ||
7af04fc0 AK |
2804 | static int em_das(struct x86_emulate_ctxt *ctxt) |
2805 | { | |
7af04fc0 AK |
2806 | u8 al, old_al; |
2807 | bool af, cf, old_cf; | |
2808 | ||
2809 | cf = ctxt->eflags & X86_EFLAGS_CF; | |
9dac77fa | 2810 | al = ctxt->dst.val; |
7af04fc0 AK |
2811 | |
2812 | old_al = al; | |
2813 | old_cf = cf; | |
2814 | cf = false; | |
2815 | af = ctxt->eflags & X86_EFLAGS_AF; | |
2816 | if ((al & 0x0f) > 9 || af) { | |
2817 | al -= 6; | |
2818 | cf = old_cf | (al >= 250); | |
2819 | af = true; | |
2820 | } else { | |
2821 | af = false; | |
2822 | } | |
2823 | if (old_al > 0x99 || old_cf) { | |
2824 | al -= 0x60; | |
2825 | cf = true; | |
2826 | } | |
2827 | ||
9dac77fa | 2828 | ctxt->dst.val = al; |
7af04fc0 | 2829 | /* Set PF, ZF, SF */ |
9dac77fa AK |
2830 | ctxt->src.type = OP_IMM; |
2831 | ctxt->src.val = 0; | |
2832 | ctxt->src.bytes = 1; | |
a31b9cea | 2833 | emulate_2op_SrcV(ctxt, "or"); |
7af04fc0 AK |
2834 | ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); |
2835 | if (cf) | |
2836 | ctxt->eflags |= X86_EFLAGS_CF; | |
2837 | if (af) | |
2838 | ctxt->eflags |= X86_EFLAGS_AF; | |
2839 | return X86EMUL_CONTINUE; | |
2840 | } | |
2841 | ||
d4ddafcd TY |
2842 | static int em_call(struct x86_emulate_ctxt *ctxt) |
2843 | { | |
2844 | long rel = ctxt->src.val; | |
2845 | ||
2846 | ctxt->src.val = (unsigned long)ctxt->_eip; | |
2847 | jmp_rel(ctxt, rel); | |
2848 | return em_push(ctxt); | |
2849 | } | |
2850 | ||
0ef753b8 AK |
2851 | static int em_call_far(struct x86_emulate_ctxt *ctxt) |
2852 | { | |
0ef753b8 AK |
2853 | u16 sel, old_cs; |
2854 | ulong old_eip; | |
2855 | int rc; | |
2856 | ||
1aa36616 | 2857 | old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); |
9dac77fa | 2858 | old_eip = ctxt->_eip; |
0ef753b8 | 2859 | |
9dac77fa | 2860 | memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); |
7b105ca2 | 2861 | if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) |
0ef753b8 AK |
2862 | return X86EMUL_CONTINUE; |
2863 | ||
9dac77fa AK |
2864 | ctxt->_eip = 0; |
2865 | memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); | |
0ef753b8 | 2866 | |
9dac77fa | 2867 | ctxt->src.val = old_cs; |
4487b3b4 | 2868 | rc = em_push(ctxt); |
0ef753b8 AK |
2869 | if (rc != X86EMUL_CONTINUE) |
2870 | return rc; | |
2871 | ||
9dac77fa | 2872 | ctxt->src.val = old_eip; |
4487b3b4 | 2873 | return em_push(ctxt); |
0ef753b8 AK |
2874 | } |
2875 | ||
40ece7c7 AK |
2876 | static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) |
2877 | { | |
40ece7c7 AK |
2878 | int rc; |
2879 | ||
9dac77fa AK |
2880 | ctxt->dst.type = OP_REG; |
2881 | ctxt->dst.addr.reg = &ctxt->_eip; | |
2882 | ctxt->dst.bytes = ctxt->op_bytes; | |
2883 | rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); | |
40ece7c7 AK |
2884 | if (rc != X86EMUL_CONTINUE) |
2885 | return rc; | |
5ad105e5 | 2886 | rsp_increment(ctxt, ctxt->src.val); |
40ece7c7 AK |
2887 | return X86EMUL_CONTINUE; |
2888 | } | |
2889 | ||
d67fc27a TY |
2890 | static int em_add(struct x86_emulate_ctxt *ctxt) |
2891 | { | |
a31b9cea | 2892 | emulate_2op_SrcV(ctxt, "add"); |
d67fc27a TY |
2893 | return X86EMUL_CONTINUE; |
2894 | } | |
2895 | ||
2896 | static int em_or(struct x86_emulate_ctxt *ctxt) | |
2897 | { | |
a31b9cea | 2898 | emulate_2op_SrcV(ctxt, "or"); |
d67fc27a TY |
2899 | return X86EMUL_CONTINUE; |
2900 | } | |
2901 | ||
2902 | static int em_adc(struct x86_emulate_ctxt *ctxt) | |
2903 | { | |
a31b9cea | 2904 | emulate_2op_SrcV(ctxt, "adc"); |
d67fc27a TY |
2905 | return X86EMUL_CONTINUE; |
2906 | } | |
2907 | ||
2908 | static int em_sbb(struct x86_emulate_ctxt *ctxt) | |
2909 | { | |
a31b9cea | 2910 | emulate_2op_SrcV(ctxt, "sbb"); |
d67fc27a TY |
2911 | return X86EMUL_CONTINUE; |
2912 | } | |
2913 | ||
2914 | static int em_and(struct x86_emulate_ctxt *ctxt) | |
2915 | { | |
a31b9cea | 2916 | emulate_2op_SrcV(ctxt, "and"); |
d67fc27a TY |
2917 | return X86EMUL_CONTINUE; |
2918 | } | |
2919 | ||
2920 | static int em_sub(struct x86_emulate_ctxt *ctxt) | |
2921 | { | |
a31b9cea | 2922 | emulate_2op_SrcV(ctxt, "sub"); |
d67fc27a TY |
2923 | return X86EMUL_CONTINUE; |
2924 | } | |
2925 | ||
2926 | static int em_xor(struct x86_emulate_ctxt *ctxt) | |
2927 | { | |
a31b9cea | 2928 | emulate_2op_SrcV(ctxt, "xor"); |
d67fc27a TY |
2929 | return X86EMUL_CONTINUE; |
2930 | } | |
2931 | ||
2932 | static int em_cmp(struct x86_emulate_ctxt *ctxt) | |
2933 | { | |
a31b9cea | 2934 | emulate_2op_SrcV(ctxt, "cmp"); |
d67fc27a | 2935 | /* Disable writeback. */ |
9dac77fa | 2936 | ctxt->dst.type = OP_NONE; |
d67fc27a TY |
2937 | return X86EMUL_CONTINUE; |
2938 | } | |
2939 | ||
9f21ca59 TY |
2940 | static int em_test(struct x86_emulate_ctxt *ctxt) |
2941 | { | |
a31b9cea | 2942 | emulate_2op_SrcV(ctxt, "test"); |
caa8a168 AK |
2943 | /* Disable writeback. */ |
2944 | ctxt->dst.type = OP_NONE; | |
9f21ca59 TY |
2945 | return X86EMUL_CONTINUE; |
2946 | } | |
2947 | ||
e4f973ae TY |
2948 | static int em_xchg(struct x86_emulate_ctxt *ctxt) |
2949 | { | |
e4f973ae | 2950 | /* Write back the register source. */ |
9dac77fa AK |
2951 | ctxt->src.val = ctxt->dst.val; |
2952 | write_register_operand(&ctxt->src); | |
e4f973ae TY |
2953 | |
2954 | /* Write back the memory destination with implicit LOCK prefix. */ | |
9dac77fa AK |
2955 | ctxt->dst.val = ctxt->src.orig_val; |
2956 | ctxt->lock_prefix = 1; | |
e4f973ae TY |
2957 | return X86EMUL_CONTINUE; |
2958 | } | |
2959 | ||
5c82aa29 | 2960 | static int em_imul(struct x86_emulate_ctxt *ctxt) |
f3a1b9f4 | 2961 | { |
a31b9cea | 2962 | emulate_2op_SrcV_nobyte(ctxt, "imul"); |
f3a1b9f4 AK |
2963 | return X86EMUL_CONTINUE; |
2964 | } | |
2965 | ||
5c82aa29 AK |
2966 | static int em_imul_3op(struct x86_emulate_ctxt *ctxt) |
2967 | { | |
9dac77fa | 2968 | ctxt->dst.val = ctxt->src2.val; |
5c82aa29 AK |
2969 | return em_imul(ctxt); |
2970 | } | |
2971 | ||
61429142 AK |
2972 | static int em_cwd(struct x86_emulate_ctxt *ctxt) |
2973 | { | |
9dac77fa AK |
2974 | ctxt->dst.type = OP_REG; |
2975 | ctxt->dst.bytes = ctxt->src.bytes; | |
dd856efa | 2976 | ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
9dac77fa | 2977 | ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); |
61429142 AK |
2978 | |
2979 | return X86EMUL_CONTINUE; | |
2980 | } | |
2981 | ||
48bb5d3c AK |
2982 | static int em_rdtsc(struct x86_emulate_ctxt *ctxt) |
2983 | { | |
48bb5d3c AK |
2984 | u64 tsc = 0; |
2985 | ||
717746e3 | 2986 | ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); |
dd856efa AK |
2987 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; |
2988 | *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; | |
48bb5d3c AK |
2989 | return X86EMUL_CONTINUE; |
2990 | } | |
2991 | ||
222d21aa AK |
2992 | static int em_rdpmc(struct x86_emulate_ctxt *ctxt) |
2993 | { | |
2994 | u64 pmc; | |
2995 | ||
dd856efa | 2996 | if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) |
222d21aa | 2997 | return emulate_gp(ctxt, 0); |
dd856efa AK |
2998 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; |
2999 | *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; | |
222d21aa AK |
3000 | return X86EMUL_CONTINUE; |
3001 | } | |
3002 | ||
b9eac5f4 AK |
3003 | static int em_mov(struct x86_emulate_ctxt *ctxt) |
3004 | { | |
49597d81 | 3005 | memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); |
b9eac5f4 AK |
3006 | return X86EMUL_CONTINUE; |
3007 | } | |
3008 | ||
bc00f8d2 TY |
3009 | static int em_cr_write(struct x86_emulate_ctxt *ctxt) |
3010 | { | |
3011 | if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) | |
3012 | return emulate_gp(ctxt, 0); | |
3013 | ||
3014 | /* Disable writeback. */ | |
3015 | ctxt->dst.type = OP_NONE; | |
3016 | return X86EMUL_CONTINUE; | |
3017 | } | |
3018 | ||
3019 | static int em_dr_write(struct x86_emulate_ctxt *ctxt) | |
3020 | { | |
3021 | unsigned long val; | |
3022 | ||
3023 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3024 | val = ctxt->src.val & ~0ULL; | |
3025 | else | |
3026 | val = ctxt->src.val & ~0U; | |
3027 | ||
3028 | /* #UD condition is already handled. */ | |
3029 | if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) | |
3030 | return emulate_gp(ctxt, 0); | |
3031 | ||
3032 | /* Disable writeback. */ | |
3033 | ctxt->dst.type = OP_NONE; | |
3034 | return X86EMUL_CONTINUE; | |
3035 | } | |
3036 | ||
e1e210b0 TY |
3037 | static int em_wrmsr(struct x86_emulate_ctxt *ctxt) |
3038 | { | |
3039 | u64 msr_data; | |
3040 | ||
dd856efa AK |
3041 | msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) |
3042 | | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); | |
3043 | if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) | |
e1e210b0 TY |
3044 | return emulate_gp(ctxt, 0); |
3045 | ||
3046 | return X86EMUL_CONTINUE; | |
3047 | } | |
3048 | ||
3049 | static int em_rdmsr(struct x86_emulate_ctxt *ctxt) | |
3050 | { | |
3051 | u64 msr_data; | |
3052 | ||
dd856efa | 3053 | if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) |
e1e210b0 TY |
3054 | return emulate_gp(ctxt, 0); |
3055 | ||
dd856efa AK |
3056 | *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; |
3057 | *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; | |
e1e210b0 TY |
3058 | return X86EMUL_CONTINUE; |
3059 | } | |
3060 | ||
1bd5f469 TY |
3061 | static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) |
3062 | { | |
9dac77fa | 3063 | if (ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3064 | return emulate_ud(ctxt); |
3065 | ||
9dac77fa | 3066 | ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); |
1bd5f469 TY |
3067 | return X86EMUL_CONTINUE; |
3068 | } | |
3069 | ||
3070 | static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) | |
3071 | { | |
9dac77fa | 3072 | u16 sel = ctxt->src.val; |
1bd5f469 | 3073 | |
9dac77fa | 3074 | if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) |
1bd5f469 TY |
3075 | return emulate_ud(ctxt); |
3076 | ||
9dac77fa | 3077 | if (ctxt->modrm_reg == VCPU_SREG_SS) |
1bd5f469 TY |
3078 | ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; |
3079 | ||
3080 | /* Disable writeback. */ | |
9dac77fa AK |
3081 | ctxt->dst.type = OP_NONE; |
3082 | return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); | |
1bd5f469 TY |
3083 | } |
3084 | ||
a14e579f AK |
3085 | static int em_lldt(struct x86_emulate_ctxt *ctxt) |
3086 | { | |
3087 | u16 sel = ctxt->src.val; | |
3088 | ||
3089 | /* Disable writeback. */ | |
3090 | ctxt->dst.type = OP_NONE; | |
3091 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); | |
3092 | } | |
3093 | ||
80890006 AK |
3094 | static int em_ltr(struct x86_emulate_ctxt *ctxt) |
3095 | { | |
3096 | u16 sel = ctxt->src.val; | |
3097 | ||
3098 | /* Disable writeback. */ | |
3099 | ctxt->dst.type = OP_NONE; | |
3100 | return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); | |
3101 | } | |
3102 | ||
38503911 AK |
3103 | static int em_invlpg(struct x86_emulate_ctxt *ctxt) |
3104 | { | |
9fa088f4 AK |
3105 | int rc; |
3106 | ulong linear; | |
3107 | ||
9dac77fa | 3108 | rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); |
9fa088f4 | 3109 | if (rc == X86EMUL_CONTINUE) |
3cb16fe7 | 3110 | ctxt->ops->invlpg(ctxt, linear); |
38503911 | 3111 | /* Disable writeback. */ |
9dac77fa | 3112 | ctxt->dst.type = OP_NONE; |
38503911 AK |
3113 | return X86EMUL_CONTINUE; |
3114 | } | |
3115 | ||
2d04a05b AK |
3116 | static int em_clts(struct x86_emulate_ctxt *ctxt) |
3117 | { | |
3118 | ulong cr0; | |
3119 | ||
3120 | cr0 = ctxt->ops->get_cr(ctxt, 0); | |
3121 | cr0 &= ~X86_CR0_TS; | |
3122 | ctxt->ops->set_cr(ctxt, 0, cr0); | |
3123 | return X86EMUL_CONTINUE; | |
3124 | } | |
3125 | ||
26d05cc7 AK |
3126 | static int em_vmcall(struct x86_emulate_ctxt *ctxt) |
3127 | { | |
26d05cc7 AK |
3128 | int rc; |
3129 | ||
9dac77fa | 3130 | if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) |
26d05cc7 AK |
3131 | return X86EMUL_UNHANDLEABLE; |
3132 | ||
3133 | rc = ctxt->ops->fix_hypercall(ctxt); | |
3134 | if (rc != X86EMUL_CONTINUE) | |
3135 | return rc; | |
3136 | ||
3137 | /* Let the processor re-execute the fixed hypercall */ | |
9dac77fa | 3138 | ctxt->_eip = ctxt->eip; |
26d05cc7 | 3139 | /* Disable writeback. */ |
9dac77fa | 3140 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3141 | return X86EMUL_CONTINUE; |
3142 | } | |
3143 | ||
96051572 AK |
3144 | static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, |
3145 | void (*get)(struct x86_emulate_ctxt *ctxt, | |
3146 | struct desc_ptr *ptr)) | |
3147 | { | |
3148 | struct desc_ptr desc_ptr; | |
3149 | ||
3150 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
3151 | ctxt->op_bytes = 8; | |
3152 | get(ctxt, &desc_ptr); | |
3153 | if (ctxt->op_bytes == 2) { | |
3154 | ctxt->op_bytes = 4; | |
3155 | desc_ptr.address &= 0x00ffffff; | |
3156 | } | |
3157 | /* Disable writeback. */ | |
3158 | ctxt->dst.type = OP_NONE; | |
3159 | return segmented_write(ctxt, ctxt->dst.addr.mem, | |
3160 | &desc_ptr, 2 + ctxt->op_bytes); | |
3161 | } | |
3162 | ||
3163 | static int em_sgdt(struct x86_emulate_ctxt *ctxt) | |
3164 | { | |
3165 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); | |
3166 | } | |
3167 | ||
3168 | static int em_sidt(struct x86_emulate_ctxt *ctxt) | |
3169 | { | |
3170 | return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); | |
3171 | } | |
3172 | ||
26d05cc7 AK |
3173 | static int em_lgdt(struct x86_emulate_ctxt *ctxt) |
3174 | { | |
26d05cc7 AK |
3175 | struct desc_ptr desc_ptr; |
3176 | int rc; | |
3177 | ||
510425ff AK |
3178 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3179 | ctxt->op_bytes = 8; | |
9dac77fa | 3180 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
26d05cc7 | 3181 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3182 | ctxt->op_bytes); |
26d05cc7 AK |
3183 | if (rc != X86EMUL_CONTINUE) |
3184 | return rc; | |
3185 | ctxt->ops->set_gdt(ctxt, &desc_ptr); | |
3186 | /* Disable writeback. */ | |
9dac77fa | 3187 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3188 | return X86EMUL_CONTINUE; |
3189 | } | |
3190 | ||
5ef39c71 | 3191 | static int em_vmmcall(struct x86_emulate_ctxt *ctxt) |
26d05cc7 | 3192 | { |
26d05cc7 AK |
3193 | int rc; |
3194 | ||
5ef39c71 AK |
3195 | rc = ctxt->ops->fix_hypercall(ctxt); |
3196 | ||
26d05cc7 | 3197 | /* Disable writeback. */ |
9dac77fa | 3198 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3199 | return rc; |
3200 | } | |
3201 | ||
3202 | static int em_lidt(struct x86_emulate_ctxt *ctxt) | |
3203 | { | |
26d05cc7 AK |
3204 | struct desc_ptr desc_ptr; |
3205 | int rc; | |
3206 | ||
510425ff AK |
3207 | if (ctxt->mode == X86EMUL_MODE_PROT64) |
3208 | ctxt->op_bytes = 8; | |
9dac77fa | 3209 | rc = read_descriptor(ctxt, ctxt->src.addr.mem, |
509cf9fe | 3210 | &desc_ptr.size, &desc_ptr.address, |
9dac77fa | 3211 | ctxt->op_bytes); |
26d05cc7 AK |
3212 | if (rc != X86EMUL_CONTINUE) |
3213 | return rc; | |
3214 | ctxt->ops->set_idt(ctxt, &desc_ptr); | |
3215 | /* Disable writeback. */ | |
9dac77fa | 3216 | ctxt->dst.type = OP_NONE; |
26d05cc7 AK |
3217 | return X86EMUL_CONTINUE; |
3218 | } | |
3219 | ||
3220 | static int em_smsw(struct x86_emulate_ctxt *ctxt) | |
3221 | { | |
9dac77fa AK |
3222 | ctxt->dst.bytes = 2; |
3223 | ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); | |
26d05cc7 AK |
3224 | return X86EMUL_CONTINUE; |
3225 | } | |
3226 | ||
3227 | static int em_lmsw(struct x86_emulate_ctxt *ctxt) | |
3228 | { | |
26d05cc7 | 3229 | ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) |
9dac77fa AK |
3230 | | (ctxt->src.val & 0x0f)); |
3231 | ctxt->dst.type = OP_NONE; | |
26d05cc7 AK |
3232 | return X86EMUL_CONTINUE; |
3233 | } | |
3234 | ||
d06e03ad TY |
3235 | static int em_loop(struct x86_emulate_ctxt *ctxt) |
3236 | { | |
dd856efa AK |
3237 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); |
3238 | if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && | |
9dac77fa AK |
3239 | (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) |
3240 | jmp_rel(ctxt, ctxt->src.val); | |
d06e03ad TY |
3241 | |
3242 | return X86EMUL_CONTINUE; | |
3243 | } | |
3244 | ||
3245 | static int em_jcxz(struct x86_emulate_ctxt *ctxt) | |
3246 | { | |
dd856efa | 3247 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) |
9dac77fa | 3248 | jmp_rel(ctxt, ctxt->src.val); |
d06e03ad TY |
3249 | |
3250 | return X86EMUL_CONTINUE; | |
3251 | } | |
3252 | ||
d7841a4b TY |
3253 | static int em_in(struct x86_emulate_ctxt *ctxt) |
3254 | { | |
3255 | if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, | |
3256 | &ctxt->dst.val)) | |
3257 | return X86EMUL_IO_NEEDED; | |
3258 | ||
3259 | return X86EMUL_CONTINUE; | |
3260 | } | |
3261 | ||
3262 | static int em_out(struct x86_emulate_ctxt *ctxt) | |
3263 | { | |
3264 | ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, | |
3265 | &ctxt->src.val, 1); | |
3266 | /* Disable writeback. */ | |
3267 | ctxt->dst.type = OP_NONE; | |
3268 | return X86EMUL_CONTINUE; | |
3269 | } | |
3270 | ||
f411e6cd TY |
3271 | static int em_cli(struct x86_emulate_ctxt *ctxt) |
3272 | { | |
3273 | if (emulator_bad_iopl(ctxt)) | |
3274 | return emulate_gp(ctxt, 0); | |
3275 | ||
3276 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
3277 | return X86EMUL_CONTINUE; | |
3278 | } | |
3279 | ||
3280 | static int em_sti(struct x86_emulate_ctxt *ctxt) | |
3281 | { | |
3282 | if (emulator_bad_iopl(ctxt)) | |
3283 | return emulate_gp(ctxt, 0); | |
3284 | ||
3285 | ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; | |
3286 | ctxt->eflags |= X86_EFLAGS_IF; | |
3287 | return X86EMUL_CONTINUE; | |
3288 | } | |
3289 | ||
ce7faab2 TY |
3290 | static int em_bt(struct x86_emulate_ctxt *ctxt) |
3291 | { | |
3292 | /* Disable writeback. */ | |
3293 | ctxt->dst.type = OP_NONE; | |
3294 | /* only subword offset */ | |
3295 | ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; | |
3296 | ||
3297 | emulate_2op_SrcV_nobyte(ctxt, "bt"); | |
3298 | return X86EMUL_CONTINUE; | |
3299 | } | |
3300 | ||
3301 | static int em_bts(struct x86_emulate_ctxt *ctxt) | |
3302 | { | |
3303 | emulate_2op_SrcV_nobyte(ctxt, "bts"); | |
3304 | return X86EMUL_CONTINUE; | |
3305 | } | |
3306 | ||
3307 | static int em_btr(struct x86_emulate_ctxt *ctxt) | |
3308 | { | |
3309 | emulate_2op_SrcV_nobyte(ctxt, "btr"); | |
3310 | return X86EMUL_CONTINUE; | |
3311 | } | |
3312 | ||
3313 | static int em_btc(struct x86_emulate_ctxt *ctxt) | |
3314 | { | |
3315 | emulate_2op_SrcV_nobyte(ctxt, "btc"); | |
3316 | return X86EMUL_CONTINUE; | |
3317 | } | |
3318 | ||
ff227392 TY |
3319 | static int em_bsf(struct x86_emulate_ctxt *ctxt) |
3320 | { | |
d54e4237 | 3321 | emulate_2op_SrcV_nobyte(ctxt, "bsf"); |
ff227392 TY |
3322 | return X86EMUL_CONTINUE; |
3323 | } | |
3324 | ||
3325 | static int em_bsr(struct x86_emulate_ctxt *ctxt) | |
3326 | { | |
d54e4237 | 3327 | emulate_2op_SrcV_nobyte(ctxt, "bsr"); |
ff227392 TY |
3328 | return X86EMUL_CONTINUE; |
3329 | } | |
3330 | ||
6d6eede4 AK |
3331 | static int em_cpuid(struct x86_emulate_ctxt *ctxt) |
3332 | { | |
3333 | u32 eax, ebx, ecx, edx; | |
3334 | ||
dd856efa AK |
3335 | eax = reg_read(ctxt, VCPU_REGS_RAX); |
3336 | ecx = reg_read(ctxt, VCPU_REGS_RCX); | |
6d6eede4 | 3337 | ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); |
dd856efa AK |
3338 | *reg_write(ctxt, VCPU_REGS_RAX) = eax; |
3339 | *reg_write(ctxt, VCPU_REGS_RBX) = ebx; | |
3340 | *reg_write(ctxt, VCPU_REGS_RCX) = ecx; | |
3341 | *reg_write(ctxt, VCPU_REGS_RDX) = edx; | |
6d6eede4 AK |
3342 | return X86EMUL_CONTINUE; |
3343 | } | |
3344 | ||
2dd7caa0 AK |
3345 | static int em_lahf(struct x86_emulate_ctxt *ctxt) |
3346 | { | |
dd856efa AK |
3347 | *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; |
3348 | *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; | |
2dd7caa0 AK |
3349 | return X86EMUL_CONTINUE; |
3350 | } | |
3351 | ||
9299836e AK |
3352 | static int em_bswap(struct x86_emulate_ctxt *ctxt) |
3353 | { | |
3354 | switch (ctxt->op_bytes) { | |
3355 | #ifdef CONFIG_X86_64 | |
3356 | case 8: | |
3357 | asm("bswap %0" : "+r"(ctxt->dst.val)); | |
3358 | break; | |
3359 | #endif | |
3360 | default: | |
3361 | asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); | |
3362 | break; | |
3363 | } | |
3364 | return X86EMUL_CONTINUE; | |
3365 | } | |
3366 | ||
cfec82cb JR |
3367 | static bool valid_cr(int nr) |
3368 | { | |
3369 | switch (nr) { | |
3370 | case 0: | |
3371 | case 2 ... 4: | |
3372 | case 8: | |
3373 | return true; | |
3374 | default: | |
3375 | return false; | |
3376 | } | |
3377 | } | |
3378 | ||
3379 | static int check_cr_read(struct x86_emulate_ctxt *ctxt) | |
3380 | { | |
9dac77fa | 3381 | if (!valid_cr(ctxt->modrm_reg)) |
cfec82cb JR |
3382 | return emulate_ud(ctxt); |
3383 | ||
3384 | return X86EMUL_CONTINUE; | |
3385 | } | |
3386 | ||
3387 | static int check_cr_write(struct x86_emulate_ctxt *ctxt) | |
3388 | { | |
9dac77fa AK |
3389 | u64 new_val = ctxt->src.val64; |
3390 | int cr = ctxt->modrm_reg; | |
c2ad2bb3 | 3391 | u64 efer = 0; |
cfec82cb JR |
3392 | |
3393 | static u64 cr_reserved_bits[] = { | |
3394 | 0xffffffff00000000ULL, | |
3395 | 0, 0, 0, /* CR3 checked later */ | |
3396 | CR4_RESERVED_BITS, | |
3397 | 0, 0, 0, | |
3398 | CR8_RESERVED_BITS, | |
3399 | }; | |
3400 | ||
3401 | if (!valid_cr(cr)) | |
3402 | return emulate_ud(ctxt); | |
3403 | ||
3404 | if (new_val & cr_reserved_bits[cr]) | |
3405 | return emulate_gp(ctxt, 0); | |
3406 | ||
3407 | switch (cr) { | |
3408 | case 0: { | |
c2ad2bb3 | 3409 | u64 cr4; |
cfec82cb JR |
3410 | if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || |
3411 | ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) | |
3412 | return emulate_gp(ctxt, 0); | |
3413 | ||
717746e3 AK |
3414 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3415 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); | |
cfec82cb JR |
3416 | |
3417 | if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && | |
3418 | !(cr4 & X86_CR4_PAE)) | |
3419 | return emulate_gp(ctxt, 0); | |
3420 | ||
3421 | break; | |
3422 | } | |
3423 | case 3: { | |
3424 | u64 rsvd = 0; | |
3425 | ||
c2ad2bb3 AK |
3426 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
3427 | if (efer & EFER_LMA) | |
cfec82cb | 3428 | rsvd = CR3_L_MODE_RESERVED_BITS; |
fd72c419 | 3429 | else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) |
cfec82cb | 3430 | rsvd = CR3_PAE_RESERVED_BITS; |
fd72c419 | 3431 | else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) |
cfec82cb JR |
3432 | rsvd = CR3_NONPAE_RESERVED_BITS; |
3433 | ||
3434 | if (new_val & rsvd) | |
3435 | return emulate_gp(ctxt, 0); | |
3436 | ||
3437 | break; | |
3438 | } | |
3439 | case 4: { | |
717746e3 | 3440 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
cfec82cb JR |
3441 | |
3442 | if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) | |
3443 | return emulate_gp(ctxt, 0); | |
3444 | ||
3445 | break; | |
3446 | } | |
3447 | } | |
3448 | ||
3449 | return X86EMUL_CONTINUE; | |
3450 | } | |
3451 | ||
3b88e41a JR |
3452 | static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) |
3453 | { | |
3454 | unsigned long dr7; | |
3455 | ||
717746e3 | 3456 | ctxt->ops->get_dr(ctxt, 7, &dr7); |
3b88e41a JR |
3457 | |
3458 | /* Check if DR7.Global_Enable is set */ | |
3459 | return dr7 & (1 << 13); | |
3460 | } | |
3461 | ||
3462 | static int check_dr_read(struct x86_emulate_ctxt *ctxt) | |
3463 | { | |
9dac77fa | 3464 | int dr = ctxt->modrm_reg; |
3b88e41a JR |
3465 | u64 cr4; |
3466 | ||
3467 | if (dr > 7) | |
3468 | return emulate_ud(ctxt); | |
3469 | ||
717746e3 | 3470 | cr4 = ctxt->ops->get_cr(ctxt, 4); |
3b88e41a JR |
3471 | if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) |
3472 | return emulate_ud(ctxt); | |
3473 | ||
3474 | if (check_dr7_gd(ctxt)) | |
3475 | return emulate_db(ctxt); | |
3476 | ||
3477 | return X86EMUL_CONTINUE; | |
3478 | } | |
3479 | ||
3480 | static int check_dr_write(struct x86_emulate_ctxt *ctxt) | |
3481 | { | |
9dac77fa AK |
3482 | u64 new_val = ctxt->src.val64; |
3483 | int dr = ctxt->modrm_reg; | |
3b88e41a JR |
3484 | |
3485 | if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) | |
3486 | return emulate_gp(ctxt, 0); | |
3487 | ||
3488 | return check_dr_read(ctxt); | |
3489 | } | |
3490 | ||
01de8b09 JR |
3491 | static int check_svme(struct x86_emulate_ctxt *ctxt) |
3492 | { | |
3493 | u64 efer; | |
3494 | ||
717746e3 | 3495 | ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); |
01de8b09 JR |
3496 | |
3497 | if (!(efer & EFER_SVME)) | |
3498 | return emulate_ud(ctxt); | |
3499 | ||
3500 | return X86EMUL_CONTINUE; | |
3501 | } | |
3502 | ||
3503 | static int check_svme_pa(struct x86_emulate_ctxt *ctxt) | |
3504 | { | |
dd856efa | 3505 | u64 rax = reg_read(ctxt, VCPU_REGS_RAX); |
01de8b09 JR |
3506 | |
3507 | /* Valid physical address? */ | |
d4224449 | 3508 | if (rax & 0xffff000000000000ULL) |
01de8b09 JR |
3509 | return emulate_gp(ctxt, 0); |
3510 | ||
3511 | return check_svme(ctxt); | |
3512 | } | |
3513 | ||
d7eb8203 JR |
3514 | static int check_rdtsc(struct x86_emulate_ctxt *ctxt) |
3515 | { | |
717746e3 | 3516 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
d7eb8203 | 3517 | |
717746e3 | 3518 | if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) |
d7eb8203 JR |
3519 | return emulate_ud(ctxt); |
3520 | ||
3521 | return X86EMUL_CONTINUE; | |
3522 | } | |
3523 | ||
8061252e JR |
3524 | static int check_rdpmc(struct x86_emulate_ctxt *ctxt) |
3525 | { | |
717746e3 | 3526 | u64 cr4 = ctxt->ops->get_cr(ctxt, 4); |
dd856efa | 3527 | u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); |
8061252e | 3528 | |
717746e3 | 3529 | if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || |
8061252e JR |
3530 | (rcx > 3)) |
3531 | return emulate_gp(ctxt, 0); | |
3532 | ||
3533 | return X86EMUL_CONTINUE; | |
3534 | } | |
3535 | ||
f6511935 JR |
3536 | static int check_perm_in(struct x86_emulate_ctxt *ctxt) |
3537 | { | |
9dac77fa AK |
3538 | ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); |
3539 | if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) | |
f6511935 JR |
3540 | return emulate_gp(ctxt, 0); |
3541 | ||
3542 | return X86EMUL_CONTINUE; | |
3543 | } | |
3544 | ||
3545 | static int check_perm_out(struct x86_emulate_ctxt *ctxt) | |
3546 | { | |
9dac77fa AK |
3547 | ctxt->src.bytes = min(ctxt->src.bytes, 4u); |
3548 | if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) | |
f6511935 JR |
3549 | return emulate_gp(ctxt, 0); |
3550 | ||
3551 | return X86EMUL_CONTINUE; | |
3552 | } | |
3553 | ||
73fba5f4 | 3554 | #define D(_y) { .flags = (_y) } |
c4f035c6 | 3555 | #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } |
d09beabd JR |
3556 | #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ |
3557 | .check_perm = (_p) } | |
73fba5f4 | 3558 | #define N D(0) |
01de8b09 | 3559 | #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } |
1c2545be TY |
3560 | #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } |
3561 | #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } | |
73fba5f4 | 3562 | #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } |
c4f035c6 AK |
3563 | #define II(_f, _e, _i) \ |
3564 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } | |
d09beabd JR |
3565 | #define IIP(_f, _e, _i, _p) \ |
3566 | { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ | |
3567 | .check_perm = (_p) } | |
aa97bb48 | 3568 | #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } |
73fba5f4 | 3569 | |
8d8f4e9f | 3570 | #define D2bv(_f) D((_f) | ByteOp), D(_f) |
f6511935 | 3571 | #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) |
8d8f4e9f | 3572 | #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) |
d7841a4b TY |
3573 | #define I2bvIP(_f, _e, _i, _p) \ |
3574 | IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) | |
8d8f4e9f | 3575 | |
d67fc27a TY |
3576 | #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ |
3577 | I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ | |
3578 | I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) | |
6230f7fc | 3579 | |
d7eb8203 | 3580 | static struct opcode group7_rm1[] = { |
1c2545be TY |
3581 | DI(SrcNone | Priv, monitor), |
3582 | DI(SrcNone | Priv, mwait), | |
d7eb8203 JR |
3583 | N, N, N, N, N, N, |
3584 | }; | |
3585 | ||
01de8b09 | 3586 | static struct opcode group7_rm3[] = { |
1c2545be TY |
3587 | DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), |
3588 | II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall), | |
3589 | DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), | |
3590 | DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), | |
3591 | DIP(SrcNone | Prot | Priv, stgi, check_svme), | |
3592 | DIP(SrcNone | Prot | Priv, clgi, check_svme), | |
3593 | DIP(SrcNone | Prot | Priv, skinit, check_svme), | |
3594 | DIP(SrcNone | Prot | Priv, invlpga, check_svme), | |
01de8b09 | 3595 | }; |
6230f7fc | 3596 | |
d7eb8203 JR |
3597 | static struct opcode group7_rm7[] = { |
3598 | N, | |
1c2545be | 3599 | DIP(SrcNone, rdtscp, check_rdtsc), |
d7eb8203 JR |
3600 | N, N, N, N, N, N, |
3601 | }; | |
d67fc27a | 3602 | |
73fba5f4 | 3603 | static struct opcode group1[] = { |
d67fc27a | 3604 | I(Lock, em_add), |
d5ae7ce8 | 3605 | I(Lock | PageTable, em_or), |
d67fc27a TY |
3606 | I(Lock, em_adc), |
3607 | I(Lock, em_sbb), | |
d5ae7ce8 | 3608 | I(Lock | PageTable, em_and), |
d67fc27a TY |
3609 | I(Lock, em_sub), |
3610 | I(Lock, em_xor), | |
3611 | I(0, em_cmp), | |
73fba5f4 AK |
3612 | }; |
3613 | ||
3614 | static struct opcode group1A[] = { | |
1c2545be | 3615 | I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, |
73fba5f4 AK |
3616 | }; |
3617 | ||
3618 | static struct opcode group3[] = { | |
1c2545be TY |
3619 | I(DstMem | SrcImm, em_test), |
3620 | I(DstMem | SrcImm, em_test), | |
3621 | I(DstMem | SrcNone | Lock, em_not), | |
3622 | I(DstMem | SrcNone | Lock, em_neg), | |
3623 | I(SrcMem, em_mul_ex), | |
3624 | I(SrcMem, em_imul_ex), | |
3625 | I(SrcMem, em_div_ex), | |
3626 | I(SrcMem, em_idiv_ex), | |
73fba5f4 AK |
3627 | }; |
3628 | ||
3629 | static struct opcode group4[] = { | |
1c2545be TY |
3630 | I(ByteOp | DstMem | SrcNone | Lock, em_grp45), |
3631 | I(ByteOp | DstMem | SrcNone | Lock, em_grp45), | |
73fba5f4 AK |
3632 | N, N, N, N, N, N, |
3633 | }; | |
3634 | ||
3635 | static struct opcode group5[] = { | |
1c2545be TY |
3636 | I(DstMem | SrcNone | Lock, em_grp45), |
3637 | I(DstMem | SrcNone | Lock, em_grp45), | |
3638 | I(SrcMem | Stack, em_grp45), | |
3639 | I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), | |
3640 | I(SrcMem | Stack, em_grp45), | |
3641 | I(SrcMemFAddr | ImplicitOps, em_grp45), | |
3642 | I(SrcMem | Stack, em_grp45), N, | |
73fba5f4 AK |
3643 | }; |
3644 | ||
dee6bb70 | 3645 | static struct opcode group6[] = { |
1c2545be TY |
3646 | DI(Prot, sldt), |
3647 | DI(Prot, str), | |
a14e579f | 3648 | II(Prot | Priv | SrcMem16, em_lldt, lldt), |
80890006 | 3649 | II(Prot | Priv | SrcMem16, em_ltr, ltr), |
dee6bb70 JR |
3650 | N, N, N, N, |
3651 | }; | |
3652 | ||
73fba5f4 | 3653 | static struct group_dual group7 = { { |
96051572 AK |
3654 | II(Mov | DstMem | Priv, em_sgdt, sgdt), |
3655 | II(Mov | DstMem | Priv, em_sidt, sidt), | |
1c2545be TY |
3656 | II(SrcMem | Priv, em_lgdt, lgdt), |
3657 | II(SrcMem | Priv, em_lidt, lidt), | |
3658 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, | |
3659 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3660 | II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), | |
73fba5f4 | 3661 | }, { |
1c2545be | 3662 | I(SrcNone | Priv | VendorSpecific, em_vmcall), |
5ef39c71 | 3663 | EXT(0, group7_rm1), |
01de8b09 | 3664 | N, EXT(0, group7_rm3), |
1c2545be TY |
3665 | II(SrcNone | DstMem | Mov, em_smsw, smsw), N, |
3666 | II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), | |
3667 | EXT(0, group7_rm7), | |
73fba5f4 AK |
3668 | } }; |
3669 | ||
3670 | static struct opcode group8[] = { | |
3671 | N, N, N, N, | |
1c2545be TY |
3672 | I(DstMem | SrcImmByte, em_bt), |
3673 | I(DstMem | SrcImmByte | Lock | PageTable, em_bts), | |
3674 | I(DstMem | SrcImmByte | Lock, em_btr), | |
3675 | I(DstMem | SrcImmByte | Lock | PageTable, em_btc), | |
73fba5f4 AK |
3676 | }; |
3677 | ||
3678 | static struct group_dual group9 = { { | |
1c2545be | 3679 | N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, |
73fba5f4 AK |
3680 | }, { |
3681 | N, N, N, N, N, N, N, N, | |
3682 | } }; | |
3683 | ||
a4d4a7c1 | 3684 | static struct opcode group11[] = { |
1c2545be | 3685 | I(DstMem | SrcImm | Mov | PageTable, em_mov), |
d5ae7ce8 | 3686 | X7(D(Undefined)), |
a4d4a7c1 AK |
3687 | }; |
3688 | ||
aa97bb48 | 3689 | static struct gprefix pfx_0f_6f_0f_7f = { |
e5971755 | 3690 | I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), |
aa97bb48 AK |
3691 | }; |
3692 | ||
3e114eb4 AK |
3693 | static struct gprefix pfx_vmovntpx = { |
3694 | I(0, em_mov), N, N, N, | |
3695 | }; | |
3696 | ||
73fba5f4 AK |
3697 | static struct opcode opcode_table[256] = { |
3698 | /* 0x00 - 0x07 */ | |
d67fc27a | 3699 | I6ALU(Lock, em_add), |
1cd196ea AK |
3700 | I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), |
3701 | I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), | |
73fba5f4 | 3702 | /* 0x08 - 0x0F */ |
d5ae7ce8 | 3703 | I6ALU(Lock | PageTable, em_or), |
1cd196ea AK |
3704 | I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), |
3705 | N, | |
73fba5f4 | 3706 | /* 0x10 - 0x17 */ |
d67fc27a | 3707 | I6ALU(Lock, em_adc), |
1cd196ea AK |
3708 | I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), |
3709 | I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), | |
73fba5f4 | 3710 | /* 0x18 - 0x1F */ |
d67fc27a | 3711 | I6ALU(Lock, em_sbb), |
1cd196ea AK |
3712 | I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), |
3713 | I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), | |
73fba5f4 | 3714 | /* 0x20 - 0x27 */ |
d5ae7ce8 | 3715 | I6ALU(Lock | PageTable, em_and), N, N, |
73fba5f4 | 3716 | /* 0x28 - 0x2F */ |
d67fc27a | 3717 | I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), |
73fba5f4 | 3718 | /* 0x30 - 0x37 */ |
d67fc27a | 3719 | I6ALU(Lock, em_xor), N, N, |
73fba5f4 | 3720 | /* 0x38 - 0x3F */ |
d67fc27a | 3721 | I6ALU(0, em_cmp), N, N, |
73fba5f4 AK |
3722 | /* 0x40 - 0x4F */ |
3723 | X16(D(DstReg)), | |
3724 | /* 0x50 - 0x57 */ | |
63540382 | 3725 | X8(I(SrcReg | Stack, em_push)), |
73fba5f4 | 3726 | /* 0x58 - 0x5F */ |
c54fe504 | 3727 | X8(I(DstReg | Stack, em_pop)), |
73fba5f4 | 3728 | /* 0x60 - 0x67 */ |
b96a7fad TY |
3729 | I(ImplicitOps | Stack | No64, em_pusha), |
3730 | I(ImplicitOps | Stack | No64, em_popa), | |
73fba5f4 AK |
3731 | N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , |
3732 | N, N, N, N, | |
3733 | /* 0x68 - 0x6F */ | |
d46164db AK |
3734 | I(SrcImm | Mov | Stack, em_push), |
3735 | I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), | |
f3a1b9f4 AK |
3736 | I(SrcImmByte | Mov | Stack, em_push), |
3737 | I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), | |
2b5e97e1 TY |
3738 | I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */ |
3739 | I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ | |
73fba5f4 AK |
3740 | /* 0x70 - 0x7F */ |
3741 | X16(D(SrcImmByte)), | |
3742 | /* 0x80 - 0x87 */ | |
1c2545be TY |
3743 | G(ByteOp | DstMem | SrcImm, group1), |
3744 | G(DstMem | SrcImm, group1), | |
3745 | G(ByteOp | DstMem | SrcImm | No64, group1), | |
3746 | G(DstMem | SrcImmByte, group1), | |
9f21ca59 | 3747 | I2bv(DstMem | SrcReg | ModRM, em_test), |
d5ae7ce8 | 3748 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), |
73fba5f4 | 3749 | /* 0x88 - 0x8F */ |
d5ae7ce8 | 3750 | I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), |
b9eac5f4 | 3751 | I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), |
d5ae7ce8 | 3752 | I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), |
1bd5f469 TY |
3753 | D(ModRM | SrcMem | NoAccess | DstReg), |
3754 | I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), | |
3755 | G(0, group1A), | |
73fba5f4 | 3756 | /* 0x90 - 0x97 */ |
bf608f88 | 3757 | DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), |
73fba5f4 | 3758 | /* 0x98 - 0x9F */ |
61429142 | 3759 | D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), |
cc4feed5 | 3760 | I(SrcImmFAddr | No64, em_call_far), N, |
62aaa2f0 | 3761 | II(ImplicitOps | Stack, em_pushf, pushf), |
2dd7caa0 | 3762 | II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf), |
73fba5f4 | 3763 | /* 0xA0 - 0xA7 */ |
b9eac5f4 | 3764 | I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), |
d5ae7ce8 | 3765 | I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), |
b9eac5f4 | 3766 | I2bv(SrcSI | DstDI | Mov | String, em_mov), |
d67fc27a | 3767 | I2bv(SrcSI | DstDI | String, em_cmp), |
73fba5f4 | 3768 | /* 0xA8 - 0xAF */ |
9f21ca59 | 3769 | I2bv(DstAcc | SrcImm, em_test), |
b9eac5f4 AK |
3770 | I2bv(SrcAcc | DstDI | Mov | String, em_mov), |
3771 | I2bv(SrcSI | DstAcc | Mov | String, em_mov), | |
d67fc27a | 3772 | I2bv(SrcAcc | DstDI | String, em_cmp), |
73fba5f4 | 3773 | /* 0xB0 - 0xB7 */ |
b9eac5f4 | 3774 | X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3775 | /* 0xB8 - 0xBF */ |
b9eac5f4 | 3776 | X8(I(DstReg | SrcImm | Mov, em_mov)), |
73fba5f4 | 3777 | /* 0xC0 - 0xC7 */ |
d2c6c7ad | 3778 | D2bv(DstMem | SrcImmByte | ModRM), |
40ece7c7 | 3779 | I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), |
ebda02c2 | 3780 | I(ImplicitOps | Stack, em_ret), |
d4b4325f AK |
3781 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), |
3782 | I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), | |
a4d4a7c1 | 3783 | G(ByteOp, group11), G(0, group11), |
73fba5f4 | 3784 | /* 0xC8 - 0xCF */ |
612e89f0 AK |
3785 | I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), |
3786 | N, I(ImplicitOps | Stack, em_ret_far), | |
3c6e276f | 3787 | D(ImplicitOps), DI(SrcImmByte, intn), |
db5b0762 | 3788 | D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), |
73fba5f4 | 3789 | /* 0xD0 - 0xD7 */ |
d2c6c7ad | 3790 | D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), |
73fba5f4 AK |
3791 | N, N, N, N, |
3792 | /* 0xD8 - 0xDF */ | |
3793 | N, N, N, N, N, N, N, N, | |
3794 | /* 0xE0 - 0xE7 */ | |
d06e03ad TY |
3795 | X3(I(SrcImmByte, em_loop)), |
3796 | I(SrcImmByte, em_jcxz), | |
d7841a4b TY |
3797 | I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), |
3798 | I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), | |
73fba5f4 | 3799 | /* 0xE8 - 0xEF */ |
d4ddafcd | 3800 | I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), |
db5b0762 | 3801 | I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), |
d7841a4b TY |
3802 | I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), |
3803 | I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), | |
73fba5f4 | 3804 | /* 0xF0 - 0xF7 */ |
bf608f88 | 3805 | N, DI(ImplicitOps, icebp), N, N, |
3c6e276f AK |
3806 | DI(ImplicitOps | Priv, hlt), D(ImplicitOps), |
3807 | G(ByteOp, group3), G(0, group3), | |
73fba5f4 | 3808 | /* 0xF8 - 0xFF */ |
f411e6cd TY |
3809 | D(ImplicitOps), D(ImplicitOps), |
3810 | I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), | |
73fba5f4 AK |
3811 | D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), |
3812 | }; | |
3813 | ||
3814 | static struct opcode twobyte_table[256] = { | |
3815 | /* 0x00 - 0x0F */ | |
dee6bb70 | 3816 | G(0, group6), GD(0, &group7), N, N, |
db5b0762 TY |
3817 | N, I(ImplicitOps | VendorSpecific, em_syscall), |
3818 | II(ImplicitOps | Priv, em_clts, clts), N, | |
3c6e276f | 3819 | DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, |
73fba5f4 AK |
3820 | N, D(ImplicitOps | ModRM), N, N, |
3821 | /* 0x10 - 0x1F */ | |
3822 | N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, | |
3823 | /* 0x20 - 0x2F */ | |
cfec82cb | 3824 | DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), |
3b88e41a | 3825 | DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), |
bc00f8d2 TY |
3826 | IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), |
3827 | IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), | |
73fba5f4 | 3828 | N, N, N, N, |
3e114eb4 AK |
3829 | N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx), |
3830 | N, N, N, N, | |
73fba5f4 | 3831 | /* 0x30 - 0x3F */ |
e1e210b0 | 3832 | II(ImplicitOps | Priv, em_wrmsr, wrmsr), |
8061252e | 3833 | IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), |
e1e210b0 | 3834 | II(ImplicitOps | Priv, em_rdmsr, rdmsr), |
222d21aa | 3835 | IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), |
db5b0762 TY |
3836 | I(ImplicitOps | VendorSpecific, em_sysenter), |
3837 | I(ImplicitOps | Priv | VendorSpecific, em_sysexit), | |
d867162c | 3838 | N, N, |
73fba5f4 AK |
3839 | N, N, N, N, N, N, N, N, |
3840 | /* 0x40 - 0x4F */ | |
3841 | X16(D(DstReg | SrcMem | ModRM | Mov)), | |
3842 | /* 0x50 - 0x5F */ | |
3843 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3844 | /* 0x60 - 0x6F */ | |
aa97bb48 AK |
3845 | N, N, N, N, |
3846 | N, N, N, N, | |
3847 | N, N, N, N, | |
3848 | N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 | 3849 | /* 0x70 - 0x7F */ |
aa97bb48 AK |
3850 | N, N, N, N, |
3851 | N, N, N, N, | |
3852 | N, N, N, N, | |
3853 | N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), | |
73fba5f4 AK |
3854 | /* 0x80 - 0x8F */ |
3855 | X16(D(SrcImm)), | |
3856 | /* 0x90 - 0x9F */ | |
ee45b58e | 3857 | X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), |
73fba5f4 | 3858 | /* 0xA0 - 0xA7 */ |
1cd196ea | 3859 | I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), |
6d6eede4 | 3860 | II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt), |
73fba5f4 AK |
3861 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3862 | D(DstMem | SrcReg | Src2CL | ModRM), N, N, | |
3863 | /* 0xA8 - 0xAF */ | |
1cd196ea | 3864 | I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), |
d5ae7ce8 | 3865 | DI(ImplicitOps, rsm), |
ce7faab2 | 3866 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), |
73fba5f4 AK |
3867 | D(DstMem | SrcReg | Src2ImmByte | ModRM), |
3868 | D(DstMem | SrcReg | Src2CL | ModRM), | |
5c82aa29 | 3869 | D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), |
73fba5f4 | 3870 | /* 0xB0 - 0xB7 */ |
e940b5c2 | 3871 | I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), |
d4b4325f | 3872 | I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), |
ce7faab2 | 3873 | I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), |
d4b4325f AK |
3874 | I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), |
3875 | I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), | |
2adb5ad9 | 3876 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
73fba5f4 AK |
3877 | /* 0xB8 - 0xBF */ |
3878 | N, N, | |
ce7faab2 TY |
3879 | G(BitOp, group8), |
3880 | I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), | |
ff227392 | 3881 | I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr), |
2adb5ad9 | 3882 | D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), |
9299836e | 3883 | /* 0xC0 - 0xC7 */ |
739ae406 | 3884 | D2bv(DstMem | SrcReg | ModRM | Lock), |
92f738a5 | 3885 | N, D(DstMem | SrcReg | ModRM | Mov), |
73fba5f4 | 3886 | N, N, N, GD(0, &group9), |
9299836e AK |
3887 | /* 0xC8 - 0xCF */ |
3888 | X8(I(DstReg, em_bswap)), | |
73fba5f4 AK |
3889 | /* 0xD0 - 0xDF */ |
3890 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3891 | /* 0xE0 - 0xEF */ | |
3892 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, | |
3893 | /* 0xF0 - 0xFF */ | |
3894 | N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N | |
3895 | }; | |
3896 | ||
3897 | #undef D | |
3898 | #undef N | |
3899 | #undef G | |
3900 | #undef GD | |
3901 | #undef I | |
aa97bb48 | 3902 | #undef GP |
01de8b09 | 3903 | #undef EXT |
73fba5f4 | 3904 | |
8d8f4e9f | 3905 | #undef D2bv |
f6511935 | 3906 | #undef D2bvIP |
8d8f4e9f | 3907 | #undef I2bv |
d7841a4b | 3908 | #undef I2bvIP |
d67fc27a | 3909 | #undef I6ALU |
8d8f4e9f | 3910 | |
9dac77fa | 3911 | static unsigned imm_size(struct x86_emulate_ctxt *ctxt) |
39f21ee5 AK |
3912 | { |
3913 | unsigned size; | |
3914 | ||
9dac77fa | 3915 | size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
39f21ee5 AK |
3916 | if (size == 8) |
3917 | size = 4; | |
3918 | return size; | |
3919 | } | |
3920 | ||
3921 | static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, | |
3922 | unsigned size, bool sign_extension) | |
3923 | { | |
39f21ee5 AK |
3924 | int rc = X86EMUL_CONTINUE; |
3925 | ||
3926 | op->type = OP_IMM; | |
3927 | op->bytes = size; | |
9dac77fa | 3928 | op->addr.mem.ea = ctxt->_eip; |
39f21ee5 AK |
3929 | /* NB. Immediates are sign-extended as necessary. */ |
3930 | switch (op->bytes) { | |
3931 | case 1: | |
e85a1085 | 3932 | op->val = insn_fetch(s8, ctxt); |
39f21ee5 AK |
3933 | break; |
3934 | case 2: | |
e85a1085 | 3935 | op->val = insn_fetch(s16, ctxt); |
39f21ee5 AK |
3936 | break; |
3937 | case 4: | |
e85a1085 | 3938 | op->val = insn_fetch(s32, ctxt); |
39f21ee5 AK |
3939 | break; |
3940 | } | |
3941 | if (!sign_extension) { | |
3942 | switch (op->bytes) { | |
3943 | case 1: | |
3944 | op->val &= 0xff; | |
3945 | break; | |
3946 | case 2: | |
3947 | op->val &= 0xffff; | |
3948 | break; | |
3949 | case 4: | |
3950 | op->val &= 0xffffffff; | |
3951 | break; | |
3952 | } | |
3953 | } | |
3954 | done: | |
3955 | return rc; | |
3956 | } | |
3957 | ||
a9945549 AK |
3958 | static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, |
3959 | unsigned d) | |
3960 | { | |
3961 | int rc = X86EMUL_CONTINUE; | |
3962 | ||
3963 | switch (d) { | |
3964 | case OpReg: | |
2adb5ad9 | 3965 | decode_register_operand(ctxt, op); |
a9945549 AK |
3966 | break; |
3967 | case OpImmUByte: | |
608aabe3 | 3968 | rc = decode_imm(ctxt, op, 1, false); |
a9945549 AK |
3969 | break; |
3970 | case OpMem: | |
41ddf978 | 3971 | ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; |
0fe59128 AK |
3972 | mem_common: |
3973 | *op = ctxt->memop; | |
3974 | ctxt->memopp = op; | |
3975 | if ((ctxt->d & BitOp) && op == &ctxt->dst) | |
a9945549 AK |
3976 | fetch_bit_operand(ctxt); |
3977 | op->orig_val = op->val; | |
3978 | break; | |
41ddf978 AK |
3979 | case OpMem64: |
3980 | ctxt->memop.bytes = 8; | |
3981 | goto mem_common; | |
a9945549 AK |
3982 | case OpAcc: |
3983 | op->type = OP_REG; | |
3984 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
dd856efa | 3985 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); |
a9945549 AK |
3986 | fetch_register_operand(op); |
3987 | op->orig_val = op->val; | |
3988 | break; | |
3989 | case OpDI: | |
3990 | op->type = OP_MEM; | |
3991 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
3992 | op->addr.mem.ea = | |
dd856efa | 3993 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI)); |
a9945549 AK |
3994 | op->addr.mem.seg = VCPU_SREG_ES; |
3995 | op->val = 0; | |
3996 | break; | |
3997 | case OpDX: | |
3998 | op->type = OP_REG; | |
3999 | op->bytes = 2; | |
dd856efa | 4000 | op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); |
a9945549 AK |
4001 | fetch_register_operand(op); |
4002 | break; | |
4dd6a57d AK |
4003 | case OpCL: |
4004 | op->bytes = 1; | |
dd856efa | 4005 | op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; |
4dd6a57d AK |
4006 | break; |
4007 | case OpImmByte: | |
4008 | rc = decode_imm(ctxt, op, 1, true); | |
4009 | break; | |
4010 | case OpOne: | |
4011 | op->bytes = 1; | |
4012 | op->val = 1; | |
4013 | break; | |
4014 | case OpImm: | |
4015 | rc = decode_imm(ctxt, op, imm_size(ctxt), true); | |
4016 | break; | |
28867cee AK |
4017 | case OpMem8: |
4018 | ctxt->memop.bytes = 1; | |
4019 | goto mem_common; | |
0fe59128 AK |
4020 | case OpMem16: |
4021 | ctxt->memop.bytes = 2; | |
4022 | goto mem_common; | |
4023 | case OpMem32: | |
4024 | ctxt->memop.bytes = 4; | |
4025 | goto mem_common; | |
4026 | case OpImmU16: | |
4027 | rc = decode_imm(ctxt, op, 2, false); | |
4028 | break; | |
4029 | case OpImmU: | |
4030 | rc = decode_imm(ctxt, op, imm_size(ctxt), false); | |
4031 | break; | |
4032 | case OpSI: | |
4033 | op->type = OP_MEM; | |
4034 | op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; | |
4035 | op->addr.mem.ea = | |
dd856efa | 4036 | register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI)); |
0fe59128 AK |
4037 | op->addr.mem.seg = seg_override(ctxt); |
4038 | op->val = 0; | |
4039 | break; | |
4040 | case OpImmFAddr: | |
4041 | op->type = OP_IMM; | |
4042 | op->addr.mem.ea = ctxt->_eip; | |
4043 | op->bytes = ctxt->op_bytes + 2; | |
4044 | insn_fetch_arr(op->valptr, op->bytes, ctxt); | |
4045 | break; | |
4046 | case OpMemFAddr: | |
4047 | ctxt->memop.bytes = ctxt->op_bytes + 2; | |
4048 | goto mem_common; | |
c191a7a0 AK |
4049 | case OpES: |
4050 | op->val = VCPU_SREG_ES; | |
4051 | break; | |
4052 | case OpCS: | |
4053 | op->val = VCPU_SREG_CS; | |
4054 | break; | |
4055 | case OpSS: | |
4056 | op->val = VCPU_SREG_SS; | |
4057 | break; | |
4058 | case OpDS: | |
4059 | op->val = VCPU_SREG_DS; | |
4060 | break; | |
4061 | case OpFS: | |
4062 | op->val = VCPU_SREG_FS; | |
4063 | break; | |
4064 | case OpGS: | |
4065 | op->val = VCPU_SREG_GS; | |
4066 | break; | |
a9945549 AK |
4067 | case OpImplicit: |
4068 | /* Special instructions do their own operand decoding. */ | |
4069 | default: | |
4070 | op->type = OP_NONE; /* Disable writeback. */ | |
4071 | break; | |
4072 | } | |
4073 | ||
4074 | done: | |
4075 | return rc; | |
4076 | } | |
4077 | ||
ef5d75cc | 4078 | int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) |
dde7e6d1 | 4079 | { |
dde7e6d1 AK |
4080 | int rc = X86EMUL_CONTINUE; |
4081 | int mode = ctxt->mode; | |
46561646 | 4082 | int def_op_bytes, def_ad_bytes, goffset, simd_prefix; |
0d7cdee8 | 4083 | bool op_prefix = false; |
46561646 | 4084 | struct opcode opcode; |
dde7e6d1 | 4085 | |
f09ed83e AK |
4086 | ctxt->memop.type = OP_NONE; |
4087 | ctxt->memopp = NULL; | |
9dac77fa AK |
4088 | ctxt->_eip = ctxt->eip; |
4089 | ctxt->fetch.start = ctxt->_eip; | |
4090 | ctxt->fetch.end = ctxt->fetch.start + insn_len; | |
dc25e89e | 4091 | if (insn_len > 0) |
9dac77fa | 4092 | memcpy(ctxt->fetch.data, insn, insn_len); |
dde7e6d1 AK |
4093 | |
4094 | switch (mode) { | |
4095 | case X86EMUL_MODE_REAL: | |
4096 | case X86EMUL_MODE_VM86: | |
4097 | case X86EMUL_MODE_PROT16: | |
4098 | def_op_bytes = def_ad_bytes = 2; | |
4099 | break; | |
4100 | case X86EMUL_MODE_PROT32: | |
4101 | def_op_bytes = def_ad_bytes = 4; | |
4102 | break; | |
4103 | #ifdef CONFIG_X86_64 | |
4104 | case X86EMUL_MODE_PROT64: | |
4105 | def_op_bytes = 4; | |
4106 | def_ad_bytes = 8; | |
4107 | break; | |
4108 | #endif | |
4109 | default: | |
1d2887e2 | 4110 | return EMULATION_FAILED; |
dde7e6d1 AK |
4111 | } |
4112 | ||
9dac77fa AK |
4113 | ctxt->op_bytes = def_op_bytes; |
4114 | ctxt->ad_bytes = def_ad_bytes; | |
dde7e6d1 AK |
4115 | |
4116 | /* Legacy prefixes. */ | |
4117 | for (;;) { | |
e85a1085 | 4118 | switch (ctxt->b = insn_fetch(u8, ctxt)) { |
dde7e6d1 | 4119 | case 0x66: /* operand-size override */ |
0d7cdee8 | 4120 | op_prefix = true; |
dde7e6d1 | 4121 | /* switch between 2/4 bytes */ |
9dac77fa | 4122 | ctxt->op_bytes = def_op_bytes ^ 6; |
dde7e6d1 AK |
4123 | break; |
4124 | case 0x67: /* address-size override */ | |
4125 | if (mode == X86EMUL_MODE_PROT64) | |
4126 | /* switch between 4/8 bytes */ | |
9dac77fa | 4127 | ctxt->ad_bytes = def_ad_bytes ^ 12; |
dde7e6d1 AK |
4128 | else |
4129 | /* switch between 2/4 bytes */ | |
9dac77fa | 4130 | ctxt->ad_bytes = def_ad_bytes ^ 6; |
dde7e6d1 AK |
4131 | break; |
4132 | case 0x26: /* ES override */ | |
4133 | case 0x2e: /* CS override */ | |
4134 | case 0x36: /* SS override */ | |
4135 | case 0x3e: /* DS override */ | |
9dac77fa | 4136 | set_seg_override(ctxt, (ctxt->b >> 3) & 3); |
dde7e6d1 AK |
4137 | break; |
4138 | case 0x64: /* FS override */ | |
4139 | case 0x65: /* GS override */ | |
9dac77fa | 4140 | set_seg_override(ctxt, ctxt->b & 7); |
dde7e6d1 AK |
4141 | break; |
4142 | case 0x40 ... 0x4f: /* REX */ | |
4143 | if (mode != X86EMUL_MODE_PROT64) | |
4144 | goto done_prefixes; | |
9dac77fa | 4145 | ctxt->rex_prefix = ctxt->b; |
dde7e6d1 AK |
4146 | continue; |
4147 | case 0xf0: /* LOCK */ | |
9dac77fa | 4148 | ctxt->lock_prefix = 1; |
dde7e6d1 AK |
4149 | break; |
4150 | case 0xf2: /* REPNE/REPNZ */ | |
dde7e6d1 | 4151 | case 0xf3: /* REP/REPE/REPZ */ |
9dac77fa | 4152 | ctxt->rep_prefix = ctxt->b; |
dde7e6d1 AK |
4153 | break; |
4154 | default: | |
4155 | goto done_prefixes; | |
4156 | } | |
4157 | ||
4158 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
4159 | ||
9dac77fa | 4160 | ctxt->rex_prefix = 0; |
dde7e6d1 AK |
4161 | } |
4162 | ||
4163 | done_prefixes: | |
4164 | ||
4165 | /* REX prefix. */ | |
9dac77fa AK |
4166 | if (ctxt->rex_prefix & 8) |
4167 | ctxt->op_bytes = 8; /* REX.W */ | |
dde7e6d1 AK |
4168 | |
4169 | /* Opcode byte(s). */ | |
9dac77fa | 4170 | opcode = opcode_table[ctxt->b]; |
d3ad6243 | 4171 | /* Two-byte opcode? */ |
9dac77fa AK |
4172 | if (ctxt->b == 0x0f) { |
4173 | ctxt->twobyte = 1; | |
e85a1085 | 4174 | ctxt->b = insn_fetch(u8, ctxt); |
9dac77fa | 4175 | opcode = twobyte_table[ctxt->b]; |
dde7e6d1 | 4176 | } |
9dac77fa | 4177 | ctxt->d = opcode.flags; |
dde7e6d1 | 4178 | |
9f4260e7 TY |
4179 | if (ctxt->d & ModRM) |
4180 | ctxt->modrm = insn_fetch(u8, ctxt); | |
4181 | ||
9dac77fa AK |
4182 | while (ctxt->d & GroupMask) { |
4183 | switch (ctxt->d & GroupMask) { | |
46561646 | 4184 | case Group: |
9dac77fa | 4185 | goffset = (ctxt->modrm >> 3) & 7; |
46561646 AK |
4186 | opcode = opcode.u.group[goffset]; |
4187 | break; | |
4188 | case GroupDual: | |
9dac77fa AK |
4189 | goffset = (ctxt->modrm >> 3) & 7; |
4190 | if ((ctxt->modrm >> 6) == 3) | |
46561646 AK |
4191 | opcode = opcode.u.gdual->mod3[goffset]; |
4192 | else | |
4193 | opcode = opcode.u.gdual->mod012[goffset]; | |
4194 | break; | |
4195 | case RMExt: | |
9dac77fa | 4196 | goffset = ctxt->modrm & 7; |
01de8b09 | 4197 | opcode = opcode.u.group[goffset]; |
46561646 AK |
4198 | break; |
4199 | case Prefix: | |
9dac77fa | 4200 | if (ctxt->rep_prefix && op_prefix) |
1d2887e2 | 4201 | return EMULATION_FAILED; |
9dac77fa | 4202 | simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; |
46561646 AK |
4203 | switch (simd_prefix) { |
4204 | case 0x00: opcode = opcode.u.gprefix->pfx_no; break; | |
4205 | case 0x66: opcode = opcode.u.gprefix->pfx_66; break; | |
4206 | case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; | |
4207 | case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; | |
4208 | } | |
4209 | break; | |
4210 | default: | |
1d2887e2 | 4211 | return EMULATION_FAILED; |
0d7cdee8 | 4212 | } |
46561646 | 4213 | |
b1ea50b2 | 4214 | ctxt->d &= ~(u64)GroupMask; |
9dac77fa | 4215 | ctxt->d |= opcode.flags; |
0d7cdee8 AK |
4216 | } |
4217 | ||
9dac77fa AK |
4218 | ctxt->execute = opcode.u.execute; |
4219 | ctxt->check_perm = opcode.check_perm; | |
4220 | ctxt->intercept = opcode.intercept; | |
dde7e6d1 AK |
4221 | |
4222 | /* Unrecognised? */ | |
9dac77fa | 4223 | if (ctxt->d == 0 || (ctxt->d & Undefined)) |
1d2887e2 | 4224 | return EMULATION_FAILED; |
dde7e6d1 | 4225 | |
9dac77fa | 4226 | if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) |
1d2887e2 | 4227 | return EMULATION_FAILED; |
d867162c | 4228 | |
9dac77fa AK |
4229 | if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) |
4230 | ctxt->op_bytes = 8; | |
dde7e6d1 | 4231 | |
9dac77fa | 4232 | if (ctxt->d & Op3264) { |
7f9b4b75 | 4233 | if (mode == X86EMUL_MODE_PROT64) |
9dac77fa | 4234 | ctxt->op_bytes = 8; |
7f9b4b75 | 4235 | else |
9dac77fa | 4236 | ctxt->op_bytes = 4; |
7f9b4b75 AK |
4237 | } |
4238 | ||
9dac77fa AK |
4239 | if (ctxt->d & Sse) |
4240 | ctxt->op_bytes = 16; | |
cbe2c9d3 AK |
4241 | else if (ctxt->d & Mmx) |
4242 | ctxt->op_bytes = 8; | |
1253791d | 4243 | |
dde7e6d1 | 4244 | /* ModRM and SIB bytes. */ |
9dac77fa | 4245 | if (ctxt->d & ModRM) { |
f09ed83e | 4246 | rc = decode_modrm(ctxt, &ctxt->memop); |
9dac77fa AK |
4247 | if (!ctxt->has_seg_override) |
4248 | set_seg_override(ctxt, ctxt->modrm_seg); | |
4249 | } else if (ctxt->d & MemAbs) | |
f09ed83e | 4250 | rc = decode_abs(ctxt, &ctxt->memop); |
dde7e6d1 AK |
4251 | if (rc != X86EMUL_CONTINUE) |
4252 | goto done; | |
4253 | ||
9dac77fa AK |
4254 | if (!ctxt->has_seg_override) |
4255 | set_seg_override(ctxt, VCPU_SREG_DS); | |
dde7e6d1 | 4256 | |
f09ed83e | 4257 | ctxt->memop.addr.mem.seg = seg_override(ctxt); |
dde7e6d1 | 4258 | |
f09ed83e AK |
4259 | if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) |
4260 | ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; | |
dde7e6d1 | 4261 | |
dde7e6d1 AK |
4262 | /* |
4263 | * Decode and fetch the source operand: register, memory | |
4264 | * or immediate. | |
4265 | */ | |
0fe59128 | 4266 | rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); |
39f21ee5 AK |
4267 | if (rc != X86EMUL_CONTINUE) |
4268 | goto done; | |
4269 | ||
dde7e6d1 AK |
4270 | /* |
4271 | * Decode and fetch the second source operand: register, memory | |
4272 | * or immediate. | |
4273 | */ | |
4dd6a57d | 4274 | rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); |
39f21ee5 AK |
4275 | if (rc != X86EMUL_CONTINUE) |
4276 | goto done; | |
4277 | ||
dde7e6d1 | 4278 | /* Decode and fetch the destination operand: register or memory. */ |
a9945549 | 4279 | rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); |
dde7e6d1 AK |
4280 | |
4281 | done: | |
f09ed83e AK |
4282 | if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) |
4283 | ctxt->memopp->addr.mem.ea += ctxt->_eip; | |
cb16c348 | 4284 | |
1d2887e2 | 4285 | return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; |
dde7e6d1 AK |
4286 | } |
4287 | ||
1cb3f3ae XG |
4288 | bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) |
4289 | { | |
4290 | return ctxt->d & PageTable; | |
4291 | } | |
4292 | ||
3e2f65d5 GN |
4293 | static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) |
4294 | { | |
3e2f65d5 GN |
4295 | /* The second termination condition only applies for REPE |
4296 | * and REPNE. Test if the repeat string operation prefix is | |
4297 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
4298 | * corresponding termination condition according to: | |
4299 | * - if REPE/REPZ and ZF = 0 then done | |
4300 | * - if REPNE/REPNZ and ZF = 1 then done | |
4301 | */ | |
9dac77fa AK |
4302 | if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || |
4303 | (ctxt->b == 0xae) || (ctxt->b == 0xaf)) | |
4304 | && (((ctxt->rep_prefix == REPE_PREFIX) && | |
3e2f65d5 | 4305 | ((ctxt->eflags & EFLG_ZF) == 0)) |
9dac77fa | 4306 | || ((ctxt->rep_prefix == REPNE_PREFIX) && |
3e2f65d5 GN |
4307 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) |
4308 | return true; | |
4309 | ||
4310 | return false; | |
4311 | } | |
4312 | ||
cbe2c9d3 AK |
4313 | static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) |
4314 | { | |
4315 | bool fault = false; | |
4316 | ||
4317 | ctxt->ops->get_fpu(ctxt); | |
4318 | asm volatile("1: fwait \n\t" | |
4319 | "2: \n\t" | |
4320 | ".pushsection .fixup,\"ax\" \n\t" | |
4321 | "3: \n\t" | |
4322 | "movb $1, %[fault] \n\t" | |
4323 | "jmp 2b \n\t" | |
4324 | ".popsection \n\t" | |
4325 | _ASM_EXTABLE(1b, 3b) | |
38e8a2dd | 4326 | : [fault]"+qm"(fault)); |
cbe2c9d3 AK |
4327 | ctxt->ops->put_fpu(ctxt); |
4328 | ||
4329 | if (unlikely(fault)) | |
4330 | return emulate_exception(ctxt, MF_VECTOR, 0, false); | |
4331 | ||
4332 | return X86EMUL_CONTINUE; | |
4333 | } | |
4334 | ||
4335 | static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, | |
4336 | struct operand *op) | |
4337 | { | |
4338 | if (op->type == OP_MM) | |
4339 | read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); | |
4340 | } | |
4341 | ||
dd856efa | 4342 | |
7b105ca2 | 4343 | int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) |
8b4caf66 | 4344 | { |
9aabc88f | 4345 | struct x86_emulate_ops *ops = ctxt->ops; |
1b30eaa8 | 4346 | int rc = X86EMUL_CONTINUE; |
9dac77fa | 4347 | int saved_dst_type = ctxt->dst.type; |
8b4caf66 | 4348 | |
9dac77fa | 4349 | ctxt->mem_read.pos = 0; |
310b5d30 | 4350 | |
9dac77fa | 4351 | if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { |
35d3d4a1 | 4352 | rc = emulate_ud(ctxt); |
1161624f GN |
4353 | goto done; |
4354 | } | |
4355 | ||
d380a5e4 | 4356 | /* LOCK prefix is allowed only with some instructions */ |
9dac77fa | 4357 | if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { |
35d3d4a1 | 4358 | rc = emulate_ud(ctxt); |
d380a5e4 GN |
4359 | goto done; |
4360 | } | |
4361 | ||
9dac77fa | 4362 | if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { |
35d3d4a1 | 4363 | rc = emulate_ud(ctxt); |
081bca0e AK |
4364 | goto done; |
4365 | } | |
4366 | ||
cbe2c9d3 AK |
4367 | if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) |
4368 | || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { | |
1253791d AK |
4369 | rc = emulate_ud(ctxt); |
4370 | goto done; | |
4371 | } | |
4372 | ||
cbe2c9d3 | 4373 | if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { |
1253791d AK |
4374 | rc = emulate_nm(ctxt); |
4375 | goto done; | |
4376 | } | |
4377 | ||
cbe2c9d3 AK |
4378 | if (ctxt->d & Mmx) { |
4379 | rc = flush_pending_x87_faults(ctxt); | |
4380 | if (rc != X86EMUL_CONTINUE) | |
4381 | goto done; | |
4382 | /* | |
4383 | * Now that we know the fpu is exception safe, we can fetch | |
4384 | * operands from it. | |
4385 | */ | |
4386 | fetch_possible_mmx_operand(ctxt, &ctxt->src); | |
4387 | fetch_possible_mmx_operand(ctxt, &ctxt->src2); | |
4388 | if (!(ctxt->d & Mov)) | |
4389 | fetch_possible_mmx_operand(ctxt, &ctxt->dst); | |
4390 | } | |
4391 | ||
9dac77fa AK |
4392 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4393 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4394 | X86_ICPT_PRE_EXCEPT); |
c4f035c6 AK |
4395 | if (rc != X86EMUL_CONTINUE) |
4396 | goto done; | |
4397 | } | |
4398 | ||
e92805ac | 4399 | /* Privileged instruction can be executed only in CPL=0 */ |
9dac77fa | 4400 | if ((ctxt->d & Priv) && ops->cpl(ctxt)) { |
35d3d4a1 | 4401 | rc = emulate_gp(ctxt, 0); |
e92805ac GN |
4402 | goto done; |
4403 | } | |
4404 | ||
8ea7d6ae | 4405 | /* Instruction can only be executed in protected mode */ |
9dac77fa | 4406 | if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { |
8ea7d6ae JR |
4407 | rc = emulate_ud(ctxt); |
4408 | goto done; | |
4409 | } | |
4410 | ||
d09beabd | 4411 | /* Do instruction specific permission checks */ |
9dac77fa AK |
4412 | if (ctxt->check_perm) { |
4413 | rc = ctxt->check_perm(ctxt); | |
d09beabd JR |
4414 | if (rc != X86EMUL_CONTINUE) |
4415 | goto done; | |
4416 | } | |
4417 | ||
9dac77fa AK |
4418 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4419 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4420 | X86_ICPT_POST_EXCEPT); |
c4f035c6 AK |
4421 | if (rc != X86EMUL_CONTINUE) |
4422 | goto done; | |
4423 | } | |
4424 | ||
9dac77fa | 4425 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
b9fa9d6b | 4426 | /* All REP prefixes have the same first termination condition */ |
dd856efa | 4427 | if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { |
9dac77fa | 4428 | ctxt->eip = ctxt->_eip; |
b9fa9d6b AK |
4429 | goto done; |
4430 | } | |
b9fa9d6b AK |
4431 | } |
4432 | ||
9dac77fa AK |
4433 | if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { |
4434 | rc = segmented_read(ctxt, ctxt->src.addr.mem, | |
4435 | ctxt->src.valptr, ctxt->src.bytes); | |
b60d513c | 4436 | if (rc != X86EMUL_CONTINUE) |
8b4caf66 | 4437 | goto done; |
9dac77fa | 4438 | ctxt->src.orig_val64 = ctxt->src.val64; |
8b4caf66 LV |
4439 | } |
4440 | ||
9dac77fa AK |
4441 | if (ctxt->src2.type == OP_MEM) { |
4442 | rc = segmented_read(ctxt, ctxt->src2.addr.mem, | |
4443 | &ctxt->src2.val, ctxt->src2.bytes); | |
e35b7b9c GN |
4444 | if (rc != X86EMUL_CONTINUE) |
4445 | goto done; | |
4446 | } | |
4447 | ||
9dac77fa | 4448 | if ((ctxt->d & DstMask) == ImplicitOps) |
8b4caf66 LV |
4449 | goto special_insn; |
4450 | ||
4451 | ||
9dac77fa | 4452 | if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { |
69f55cb1 | 4453 | /* optimisation - avoid slow emulated read if Mov */ |
9dac77fa AK |
4454 | rc = segmented_read(ctxt, ctxt->dst.addr.mem, |
4455 | &ctxt->dst.val, ctxt->dst.bytes); | |
69f55cb1 GN |
4456 | if (rc != X86EMUL_CONTINUE) |
4457 | goto done; | |
038e51de | 4458 | } |
9dac77fa | 4459 | ctxt->dst.orig_val = ctxt->dst.val; |
038e51de | 4460 | |
018a98db AK |
4461 | special_insn: |
4462 | ||
9dac77fa AK |
4463 | if (unlikely(ctxt->guest_mode) && ctxt->intercept) { |
4464 | rc = emulator_check_intercept(ctxt, ctxt->intercept, | |
8a76d7f2 | 4465 | X86_ICPT_POST_MEMACCESS); |
c4f035c6 AK |
4466 | if (rc != X86EMUL_CONTINUE) |
4467 | goto done; | |
4468 | } | |
4469 | ||
9dac77fa AK |
4470 | if (ctxt->execute) { |
4471 | rc = ctxt->execute(ctxt); | |
ef65c889 AK |
4472 | if (rc != X86EMUL_CONTINUE) |
4473 | goto done; | |
4474 | goto writeback; | |
4475 | } | |
4476 | ||
9dac77fa | 4477 | if (ctxt->twobyte) |
6aa8b732 AK |
4478 | goto twobyte_insn; |
4479 | ||
9dac77fa | 4480 | switch (ctxt->b) { |
33615aa9 | 4481 | case 0x40 ... 0x47: /* inc r16/r32 */ |
d1eef45d | 4482 | emulate_1op(ctxt, "inc"); |
33615aa9 AK |
4483 | break; |
4484 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
d1eef45d | 4485 | emulate_1op(ctxt, "dec"); |
33615aa9 | 4486 | break; |
6aa8b732 | 4487 | case 0x63: /* movsxd */ |
8b4caf66 | 4488 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 4489 | goto cannot_emulate; |
9dac77fa | 4490 | ctxt->dst.val = (s32) ctxt->src.val; |
6aa8b732 | 4491 | break; |
b2833e3c | 4492 | case 0x70 ... 0x7f: /* jcc (short) */ |
9dac77fa AK |
4493 | if (test_cc(ctxt->b, ctxt->eflags)) |
4494 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4495 | break; |
7e0b54b1 | 4496 | case 0x8d: /* lea r16/r32, m */ |
9dac77fa | 4497 | ctxt->dst.val = ctxt->src.addr.mem.ea; |
7e0b54b1 | 4498 | break; |
3d9e77df | 4499 | case 0x90 ... 0x97: /* nop / xchg reg, rax */ |
dd856efa | 4500 | if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) |
34698d8c | 4501 | break; |
e4f973ae TY |
4502 | rc = em_xchg(ctxt); |
4503 | break; | |
e8b6fa70 | 4504 | case 0x98: /* cbw/cwde/cdqe */ |
9dac77fa AK |
4505 | switch (ctxt->op_bytes) { |
4506 | case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; | |
4507 | case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; | |
4508 | case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; | |
e8b6fa70 WY |
4509 | } |
4510 | break; | |
018a98db | 4511 | case 0xc0 ... 0xc1: |
51187683 | 4512 | rc = em_grp2(ctxt); |
018a98db | 4513 | break; |
6e154e56 | 4514 | case 0xcc: /* int3 */ |
5c5df76b TY |
4515 | rc = emulate_int(ctxt, 3); |
4516 | break; | |
6e154e56 | 4517 | case 0xcd: /* int n */ |
9dac77fa | 4518 | rc = emulate_int(ctxt, ctxt->src.val); |
6e154e56 MG |
4519 | break; |
4520 | case 0xce: /* into */ | |
5c5df76b TY |
4521 | if (ctxt->eflags & EFLG_OF) |
4522 | rc = emulate_int(ctxt, 4); | |
6e154e56 | 4523 | break; |
018a98db | 4524 | case 0xd0 ... 0xd1: /* Grp2 */ |
51187683 | 4525 | rc = em_grp2(ctxt); |
018a98db AK |
4526 | break; |
4527 | case 0xd2 ... 0xd3: /* Grp2 */ | |
dd856efa | 4528 | ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX); |
51187683 | 4529 | rc = em_grp2(ctxt); |
018a98db | 4530 | break; |
1a52e051 | 4531 | case 0xe9: /* jmp rel */ |
db5b0762 | 4532 | case 0xeb: /* jmp rel short */ |
9dac77fa AK |
4533 | jmp_rel(ctxt, ctxt->src.val); |
4534 | ctxt->dst.type = OP_NONE; /* Disable writeback. */ | |
1a52e051 | 4535 | break; |
111de5d6 | 4536 | case 0xf4: /* hlt */ |
6c3287f7 | 4537 | ctxt->ops->halt(ctxt); |
19fdfa0d | 4538 | break; |
111de5d6 AK |
4539 | case 0xf5: /* cmc */ |
4540 | /* complement carry flag from eflags reg */ | |
4541 | ctxt->eflags ^= EFLG_CF; | |
111de5d6 AK |
4542 | break; |
4543 | case 0xf8: /* clc */ | |
4544 | ctxt->eflags &= ~EFLG_CF; | |
111de5d6 | 4545 | break; |
8744aa9a MG |
4546 | case 0xf9: /* stc */ |
4547 | ctxt->eflags |= EFLG_CF; | |
4548 | break; | |
fb4616f4 MG |
4549 | case 0xfc: /* cld */ |
4550 | ctxt->eflags &= ~EFLG_DF; | |
fb4616f4 MG |
4551 | break; |
4552 | case 0xfd: /* std */ | |
4553 | ctxt->eflags |= EFLG_DF; | |
fb4616f4 | 4554 | break; |
91269b8f AK |
4555 | default: |
4556 | goto cannot_emulate; | |
6aa8b732 | 4557 | } |
018a98db | 4558 | |
7d9ddaed AK |
4559 | if (rc != X86EMUL_CONTINUE) |
4560 | goto done; | |
4561 | ||
018a98db | 4562 | writeback: |
adddcecf | 4563 | rc = writeback(ctxt); |
1b30eaa8 | 4564 | if (rc != X86EMUL_CONTINUE) |
018a98db AK |
4565 | goto done; |
4566 | ||
5cd21917 GN |
4567 | /* |
4568 | * restore dst type in case the decoding will be reused | |
4569 | * (happens for string instruction ) | |
4570 | */ | |
9dac77fa | 4571 | ctxt->dst.type = saved_dst_type; |
5cd21917 | 4572 | |
9dac77fa AK |
4573 | if ((ctxt->d & SrcMask) == SrcSI) |
4574 | string_addr_inc(ctxt, seg_override(ctxt), | |
4575 | VCPU_REGS_RSI, &ctxt->src); | |
a682e354 | 4576 | |
9dac77fa | 4577 | if ((ctxt->d & DstMask) == DstDI) |
90de84f5 | 4578 | string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, |
9dac77fa | 4579 | &ctxt->dst); |
d9271123 | 4580 | |
9dac77fa AK |
4581 | if (ctxt->rep_prefix && (ctxt->d & String)) { |
4582 | struct read_cache *r = &ctxt->io_read; | |
dd856efa | 4583 | register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); |
3e2f65d5 | 4584 | |
d2ddd1c4 GN |
4585 | if (!string_insn_completed(ctxt)) { |
4586 | /* | |
4587 | * Re-enter guest when pio read ahead buffer is empty | |
4588 | * or, if it is not used, after each 1024 iteration. | |
4589 | */ | |
dd856efa | 4590 | if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && |
d2ddd1c4 GN |
4591 | (r->end == 0 || r->end != r->pos)) { |
4592 | /* | |
4593 | * Reset read cache. Usually happens before | |
4594 | * decode, but since instruction is restarted | |
4595 | * we have to do it here. | |
4596 | */ | |
9dac77fa | 4597 | ctxt->mem_read.end = 0; |
dd856efa | 4598 | writeback_registers(ctxt); |
d2ddd1c4 GN |
4599 | return EMULATION_RESTART; |
4600 | } | |
4601 | goto done; /* skip rip writeback */ | |
0fa6ccbd | 4602 | } |
5cd21917 | 4603 | } |
d2ddd1c4 | 4604 | |
9dac77fa | 4605 | ctxt->eip = ctxt->_eip; |
018a98db AK |
4606 | |
4607 | done: | |
da9cb575 AK |
4608 | if (rc == X86EMUL_PROPAGATE_FAULT) |
4609 | ctxt->have_exception = true; | |
775fde86 JR |
4610 | if (rc == X86EMUL_INTERCEPTED) |
4611 | return EMULATION_INTERCEPTED; | |
4612 | ||
dd856efa AK |
4613 | if (rc == X86EMUL_CONTINUE) |
4614 | writeback_registers(ctxt); | |
4615 | ||
d2ddd1c4 | 4616 | return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; |
6aa8b732 AK |
4617 | |
4618 | twobyte_insn: | |
9dac77fa | 4619 | switch (ctxt->b) { |
018a98db | 4620 | case 0x09: /* wbinvd */ |
cfb22375 | 4621 | (ctxt->ops->wbinvd)(ctxt); |
f5f48ee1 SY |
4622 | break; |
4623 | case 0x08: /* invd */ | |
018a98db AK |
4624 | case 0x0d: /* GrpP (prefetch) */ |
4625 | case 0x18: /* Grp16 (prefetch/nop) */ | |
018a98db AK |
4626 | break; |
4627 | case 0x20: /* mov cr, reg */ | |
9dac77fa | 4628 | ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); |
018a98db | 4629 | break; |
6aa8b732 | 4630 | case 0x21: /* mov from dr to reg */ |
9dac77fa | 4631 | ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); |
6aa8b732 | 4632 | break; |
6aa8b732 | 4633 | case 0x40 ... 0x4f: /* cmov */ |
9dac77fa AK |
4634 | ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; |
4635 | if (!test_cc(ctxt->b, ctxt->eflags)) | |
4636 | ctxt->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 4637 | break; |
b2833e3c | 4638 | case 0x80 ... 0x8f: /* jnz rel, etc*/ |
9dac77fa AK |
4639 | if (test_cc(ctxt->b, ctxt->eflags)) |
4640 | jmp_rel(ctxt, ctxt->src.val); | |
018a98db | 4641 | break; |
ee45b58e | 4642 | case 0x90 ... 0x9f: /* setcc r/m8 */ |
9dac77fa | 4643 | ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); |
ee45b58e | 4644 | break; |
9bf8ea42 GT |
4645 | case 0xa4: /* shld imm8, r, r/m */ |
4646 | case 0xa5: /* shld cl, r, r/m */ | |
761441b9 | 4647 | emulate_2op_cl(ctxt, "shld"); |
9bf8ea42 | 4648 | break; |
9bf8ea42 GT |
4649 | case 0xac: /* shrd imm8, r, r/m */ |
4650 | case 0xad: /* shrd cl, r, r/m */ | |
761441b9 | 4651 | emulate_2op_cl(ctxt, "shrd"); |
9bf8ea42 | 4652 | break; |
2a7c5b8b GC |
4653 | case 0xae: /* clflush */ |
4654 | break; | |
6aa8b732 | 4655 | case 0xb6 ... 0xb7: /* movzx */ |
9dac77fa | 4656 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4657 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val |
9dac77fa | 4658 | : (u16) ctxt->src.val; |
6aa8b732 | 4659 | break; |
6aa8b732 | 4660 | case 0xbe ... 0xbf: /* movsx */ |
9dac77fa | 4661 | ctxt->dst.bytes = ctxt->op_bytes; |
361cad2b | 4662 | ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : |
9dac77fa | 4663 | (s16) ctxt->src.val; |
6aa8b732 | 4664 | break; |
92f738a5 | 4665 | case 0xc0 ... 0xc1: /* xadd */ |
a31b9cea | 4666 | emulate_2op_SrcV(ctxt, "add"); |
92f738a5 | 4667 | /* Write back the register source. */ |
9dac77fa AK |
4668 | ctxt->src.val = ctxt->dst.orig_val; |
4669 | write_register_operand(&ctxt->src); | |
92f738a5 | 4670 | break; |
a012e65a | 4671 | case 0xc3: /* movnti */ |
9dac77fa AK |
4672 | ctxt->dst.bytes = ctxt->op_bytes; |
4673 | ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : | |
4674 | (u64) ctxt->src.val; | |
a012e65a | 4675 | break; |
91269b8f AK |
4676 | default: |
4677 | goto cannot_emulate; | |
6aa8b732 | 4678 | } |
7d9ddaed AK |
4679 | |
4680 | if (rc != X86EMUL_CONTINUE) | |
4681 | goto done; | |
4682 | ||
6aa8b732 AK |
4683 | goto writeback; |
4684 | ||
4685 | cannot_emulate: | |
a0c0ab2f | 4686 | return EMULATION_FAILED; |
6aa8b732 | 4687 | } |
dd856efa AK |
4688 | |
4689 | void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) | |
4690 | { | |
4691 | invalidate_registers(ctxt); | |
4692 | } | |
4693 | ||
4694 | void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) | |
4695 | { | |
4696 | writeback_registers(ctxt); | |
4697 | } |