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KVM: x86: Do not set access bit on accessed segments
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
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6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
b7d491e7 27#include <linux/stringify.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
221192bd 128#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 129/* Generic ModRM decode. */
130#define ModRM (1<<19)
131/* Destination is only written; never read. */
132#define Mov (1<<20)
d8769fed 133/* Misc flags */
8ea7d6ae 134#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 135#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 136#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 137#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 138#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 139#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 140#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 141#define No64 (1<<28)
d5ae7ce8 142#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 143#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 144/* Source 2 operand type */
0b789eee 145#define Src2Shift (31)
4dd6a57d 146#define Src2None (OpNone << Src2Shift)
ab2c5ce6 147#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 148#define Src2CL (OpCL << Src2Shift)
149#define Src2ImmByte (OpImmByte << Src2Shift)
150#define Src2One (OpOne << Src2Shift)
151#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 152#define Src2ES (OpES << Src2Shift)
153#define Src2CS (OpCS << Src2Shift)
154#define Src2SS (OpSS << Src2Shift)
155#define Src2DS (OpDS << Src2Shift)
156#define Src2FS (OpFS << Src2Shift)
157#define Src2GS (OpGS << Src2Shift)
4dd6a57d 158#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 159#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
1c11b376
AK		 160#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
161#define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
162#define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
e28bbd44 163#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 164#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 165#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 166#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 167#define Intercept ((u64)1 << 48) /* Has valid intercept field */
168#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
10e38fc7 169#define NoBigReal ((u64)1 << 50) /* No big real mode */
68efa764 170#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 171#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 172#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 173#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
6aa8b732 174
820207c8 175#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 176
d0e53325
AK		 177#define X2(x...) x, x
178#define X3(x...) X2(x), x
179#define X4(x...) X2(x), X2(x)
180#define X5(x...) X4(x), x
181#define X6(x...) X4(x), X2(x)
182#define X7(x...) X4(x), X3(x)
183#define X8(x...) X4(x), X4(x)
184#define X16(x...) X8(x), X8(x)
83babbca 185
e28bbd44
AK		 186#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
187#define FASTOP_SIZE 8
188
189/*
190 * fastop functions have a special calling convention:
191 *
017da7b6
AK		 192 * dst: rax (in/out)
193 * src: rdx (in/out)
e28bbd44
AK		 194 * src2: rcx (in)
195 * flags: rflags (in/out)
b8c0b6ae 196 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 197 *
198 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
199 * different operand sizes can be reached by calculation, rather than a jump
200 * table (which would be bigger than the code).
201 *
202 * fastop functions are declared as taking a never-defined fastop parameter,
203 * so they can't be called from C directly.
204 */
205
206struct fastop;
207
d65b1dee 208struct opcode {
b1ea50b2
AK		 209 u64 flags : 56;
210 u64 intercept : 8;
120df890 211 union {
ef65c889 212 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 213 const struct opcode *group;
214 const struct group_dual *gdual;
215 const struct gprefix *gprefix;
045a282c 216 const struct escape *esc;
39f062ff 217 const struct instr_dual *idual;
e28bbd44 218 void (*fastop)(struct fastop *fake);
120df890 219 } u;
d09beabd 220 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 221};
222
223struct group_dual {
224 struct opcode mod012[8];
225 struct opcode mod3[8];
d65b1dee
AK		 226};
227
0d7cdee8
AK		 228struct gprefix {
229 struct opcode pfx_no;
230 struct opcode pfx_66;
231 struct opcode pfx_f2;
232 struct opcode pfx_f3;
233};
234
045a282c
GN		 235struct escape {
236 struct opcode op[8];
237 struct opcode high[64];
238};
239
39f062ff
NA		 240struct instr_dual {
241 struct opcode mod012;
242 struct opcode mod3;
243};
244
6aa8b732 245/* EFLAGS bit definitions. */
d4c6a154
GN		 246#define EFLG_ID (1<<21)
247#define EFLG_VIP (1<<20)
248#define EFLG_VIF (1<<19)
249#define EFLG_AC (1<<18)
b1d86143
AP		 250#define EFLG_VM (1<<17)
251#define EFLG_RF (1<<16)
d4c6a154
GN		 252#define EFLG_IOPL (3<<12)
253#define EFLG_NT (1<<14)
6aa8b732
AK		 254#define EFLG_OF (1<<11)
255#define EFLG_DF (1<<10)
b1d86143 256#define EFLG_IF (1<<9)
d4c6a154 257#define EFLG_TF (1<<8)
6aa8b732
AK		 258#define EFLG_SF (1<<7)
259#define EFLG_ZF (1<<6)
260#define EFLG_AF (1<<4)
261#define EFLG_PF (1<<2)
262#define EFLG_CF (1<<0)
263
62bd430e
MG		 264#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
265#define EFLG_RESERVED_ONE_MASK 2
266
3dc4bc4f
NA		 267enum x86_transfer_type {
268 X86_TRANSFER_NONE,
269 X86_TRANSFER_CALL_JMP,
270 X86_TRANSFER_RET,
271 X86_TRANSFER_TASK_SWITCH,
272};
273
dd856efa
AK		 274static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
275{
276 if (!(ctxt->regs_valid & (1 << nr))) {
277 ctxt->regs_valid |= 1 << nr;
278 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
279 }
280 return ctxt->_regs[nr];
281}
282
283static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
284{
285 ctxt->regs_valid |= 1 << nr;
286 ctxt->regs_dirty |= 1 << nr;
287 return &ctxt->_regs[nr];
288}
289
290static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
291{
292 reg_read(ctxt, nr);
293 return reg_write(ctxt, nr);
294}
295
296static void writeback_registers(struct x86_emulate_ctxt *ctxt)
297{
298 unsigned reg;
299
300 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
301 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
302}
303
304static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
305{
306 ctxt->regs_dirty = 0;
307 ctxt->regs_valid = 0;
308}
309
6aa8b732
AK		 310/*
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
313 */
314#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
315
dda96d8f
AK		 316#ifdef CONFIG_X86_64
317#define ON64(x) x
318#else
319#define ON64(x)
320#endif
321
4d758349
AK		 322static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
323
b7d491e7
AK		 324#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
325#define FOP_RET "ret \n\t"
326
327#define FOP_START(op) \
328 extern void em_##op(struct fastop *fake); \
329 asm(".pushsection .text, \"ax\" \n\t" \
330 ".global em_" #op " \n\t" \
331 FOP_ALIGN \
332 "em_" #op ": \n\t"
333
334#define FOP_END \
335 ".popsection")
336
0bdea068
AK		 337#define FOPNOP() FOP_ALIGN FOP_RET
338
b7d491e7 339#define FOP1E(op, dst) \
b8c0b6ae
AK		 340 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
341
342#define FOP1EEX(op, dst) \
343 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 344
345#define FASTOP1(op) \
346 FOP_START(op) \
347 FOP1E(op##b, al) \
348 FOP1E(op##w, ax) \
349 FOP1E(op##l, eax) \
350 ON64(FOP1E(op##q, rax)) \
351 FOP_END
352
b9fa409b
AK		 353/* 1-operand, using src2 (for MUL/DIV r/m) */
354#define FASTOP1SRC2(op, name) \
355 FOP_START(name) \
356 FOP1E(op, cl) \
357 FOP1E(op, cx) \
358 FOP1E(op, ecx) \
359 ON64(FOP1E(op, rcx)) \
360 FOP_END
361
b8c0b6ae
AK		 362/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
363#define FASTOP1SRC2EX(op, name) \
364 FOP_START(name) \
365 FOP1EEX(op, cl) \
366 FOP1EEX(op, cx) \
367 FOP1EEX(op, ecx) \
368 ON64(FOP1EEX(op, rcx)) \
369 FOP_END
370
f7857f35
AK		 371#define FOP2E(op, dst, src) \
372 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
373
374#define FASTOP2(op) \
375 FOP_START(op) \
017da7b6
AK		 376 FOP2E(op##b, al, dl) \
377 FOP2E(op##w, ax, dx) \
378 FOP2E(op##l, eax, edx) \
379 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 380 FOP_END
381
11c363ba
AK		 382/* 2 operand, word only */
383#define FASTOP2W(op) \
384 FOP_START(op) \
385 FOPNOP() \
017da7b6
AK		 386 FOP2E(op##w, ax, dx) \
387 FOP2E(op##l, eax, edx) \
388 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 389 FOP_END
390
007a3b54
AK		 391/* 2 operand, src is CL */
392#define FASTOP2CL(op) \
393 FOP_START(op) \
394 FOP2E(op##b, al, cl) \
395 FOP2E(op##w, ax, cl) \
396 FOP2E(op##l, eax, cl) \
397 ON64(FOP2E(op##q, rax, cl)) \
398 FOP_END
399
5aca3722
NA		 400/* 2 operand, src and dest are reversed */
401#define FASTOP2R(op, name) \
402 FOP_START(name) \
403 FOP2E(op##b, dl, al) \
404 FOP2E(op##w, dx, ax) \
405 FOP2E(op##l, edx, eax) \
406 ON64(FOP2E(op##q, rdx, rax)) \
407 FOP_END
408
0bdea068
AK		 409#define FOP3E(op, dst, src, src2) \
410 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
411
412/* 3-operand, word-only, src2=cl */
413#define FASTOP3WCL(op) \
414 FOP_START(op) \
415 FOPNOP() \
017da7b6
AK		 416 FOP3E(op##w, ax, dx, cl) \
417 FOP3E(op##l, eax, edx, cl) \
418 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 419 FOP_END
420
9ae9feba
AK		 421/* Special case for SETcc - 1 instruction per cc */
422#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
423
b8c0b6ae
AK		 424asm(".global kvm_fastop_exception \n"
425 "kvm_fastop_exception: xor %esi, %esi; ret");
426
9ae9feba
AK		 427FOP_START(setcc)
428FOP_SETCC(seto)
429FOP_SETCC(setno)
430FOP_SETCC(setc)
431FOP_SETCC(setnc)
432FOP_SETCC(setz)
433FOP_SETCC(setnz)
434FOP_SETCC(setbe)
435FOP_SETCC(setnbe)
436FOP_SETCC(sets)
437FOP_SETCC(setns)
438FOP_SETCC(setp)
439FOP_SETCC(setnp)
440FOP_SETCC(setl)
441FOP_SETCC(setnl)
442FOP_SETCC(setle)
443FOP_SETCC(setnle)
444FOP_END;
445
326f578f
PB		 446FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
447FOP_END;
448
8a76d7f2
JR		 449static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
450 enum x86_intercept intercept,
451 enum x86_intercept_stage stage)
452{
453 struct x86_instruction_info info = {
454 .intercept = intercept,
9dac77fa
AK		 455 .rep_prefix = ctxt->rep_prefix,
456 .modrm_mod = ctxt->modrm_mod,
457 .modrm_reg = ctxt->modrm_reg,
458 .modrm_rm = ctxt->modrm_rm,
459 .src_val = ctxt->src.val64,
6cbc5f5a 460 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 461 .src_bytes = ctxt->src.bytes,
462 .dst_bytes = ctxt->dst.bytes,
463 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 464 .next_rip = ctxt->eip,
465 };
466
2953538e 467 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 468}
469
f47cfa31
AK		 470static void assign_masked(ulong *dest, ulong src, ulong mask)
471{
472 *dest = (*dest & ~mask) | (src & mask);
473}
474
9dac77fa 475static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 476{
9dac77fa 477 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 478}
479
f47cfa31
AK		 480static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
481{
482 u16 sel;
483 struct desc_struct ss;
484
485 if (ctxt->mode == X86EMUL_MODE_PROT64)
486 return ~0UL;
487 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
488 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
489}
490
612e89f0
AK		 491static int stack_size(struct x86_emulate_ctxt *ctxt)
492{
493 return (__fls(stack_mask(ctxt)) + 1) >> 3;
494}
495
6aa8b732 496/* Access/update address held in a register, based on addressing mode. */
e4706772 497static inline unsigned long
9dac77fa 498address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 499{
9dac77fa 500 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 501 return reg;
502 else
9dac77fa 503 return reg & ad_mask(ctxt);
e4706772
HH		 504}
505
506static inline unsigned long
01485a22 507register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 508{
01485a22 509 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 510}
511
5ad105e5
AK		 512static void masked_increment(ulong *reg, ulong mask, int inc)
513{
514 assign_masked(reg, *reg + inc, mask);
515}
516
7a957275 517static inline void
01485a22 518register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 519{
5ad105e5
AK		 520 ulong mask;
521
9dac77fa 522 if (ctxt->ad_bytes == sizeof(unsigned long))
5ad105e5 523 mask = ~0UL;
7a957275 524 else
5ad105e5 525 mask = ad_mask(ctxt);
01485a22 526 masked_increment(reg_rmw(ctxt, reg), mask, inc);
5ad105e5
AK		 527}
528
529static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
530{
dd856efa 531 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 532}
6aa8b732 533
56697687
AK		 534static u32 desc_limit_scaled(struct desc_struct *desc)
535{
536 u32 limit = get_desc_limit(desc);
537
538 return desc->g ? (limit << 12) | 0xfff : limit;
539}
540
7b105ca2 541static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 542{
543 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
544 return 0;
545
7b105ca2 546 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 547}
548
35d3d4a1
AK		 549static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
550 u32 error, bool valid)
54b8486f 551{
e0ad0b47 552 WARN_ON(vec > 0x1f);
da9cb575
AK		 553 ctxt->exception.vector = vec;
554 ctxt->exception.error_code = error;
555 ctxt->exception.error_code_valid = valid;
35d3d4a1 556 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 557}
558
3b88e41a
JR		 559static int emulate_db(struct x86_emulate_ctxt *ctxt)
560{
561 return emulate_exception(ctxt, DB_VECTOR, 0, false);
562}
563
35d3d4a1 564static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 565{
35d3d4a1 566 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 567}
568
618ff15d
AK		 569static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
570{
571 return emulate_exception(ctxt, SS_VECTOR, err, true);
572}
573
35d3d4a1 574static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 575{
35d3d4a1 576 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 577}
578
35d3d4a1 579static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 580{
35d3d4a1 581 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 582}
583
34d1f490
AK		 584static int emulate_de(struct x86_emulate_ctxt *ctxt)
585{
35d3d4a1 586 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 587}
588
1253791d
AK		 589static int emulate_nm(struct x86_emulate_ctxt *ctxt)
590{
591 return emulate_exception(ctxt, NM_VECTOR, 0, false);
592}
593
1aa36616
AK		 594static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
595{
596 u16 selector;
597 struct desc_struct desc;
598
599 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
600 return selector;
601}
602
603static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
604 unsigned seg)
605{
606 u16 dummy;
607 u32 base3;
608 struct desc_struct desc;
609
610 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
611 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
612}
613
1c11b376
AK		 614/*
615 * x86 defines three classes of vector instructions: explicitly
616 * aligned, explicitly unaligned, and the rest, which change behaviour
617 * depending on whether they're AVX encoded or not.
618 *
619 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
620 * subject to the same check.
621 */
622static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
623{
624 if (likely(size < 16))
625 return false;
626
627 if (ctxt->d & Aligned)
628 return true;
629 else if (ctxt->d & Unaligned)
630 return false;
631 else if (ctxt->d & Avx)
632 return false;
633 else
634 return true;
635}
636
d09155d2
PB		 637static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 unsigned *max_size, unsigned size,
640 bool write, bool fetch,
d50eaa18 641 enum x86emul_mode mode, ulong *linear)
52fd8b44 642{
618ff15d
AK		 643 struct desc_struct desc;
644 bool usable;
52fd8b44 645 ulong la;
618ff15d 646 u32 lim;
1aa36616 647 u16 sel;
52fd8b44 648
7b105ca2 649 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 650 *max_size = 0;
d50eaa18 651 switch (mode) {
618ff15d 652 case X86EMUL_MODE_PROT64:
4be4de7e 653 if (is_noncanonical_address(la))
abc7d8a4 654 goto bad;
fd56e154
PB		 655
656 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
657 if (size > *max_size)
658 goto bad;
618ff15d
AK		 659 break;
660 default:
1aa36616
AK		 661 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
662 addr.seg);
618ff15d
AK		 663 if (!usable)
664 goto bad;
58b7825b
GN		 665 /* code segment in protected mode or read-only data segment */
666 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
667 || !(desc.type & 2)) && write)
618ff15d
AK		 668 goto bad;
669 /* unreadable code segment */
3d9b938e 670 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 671 goto bad;
672 lim = desc_limit_scaled(&desc);
997b0412 673 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 674 /* expand-down segment */
fd56e154 675 if (addr.ea <= lim)
618ff15d
AK		 676 goto bad;
677 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 678 }
997b0412
PB		 679 if (addr.ea > lim)
680 goto bad;
681 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
fd56e154
PB		 682 if (size > *max_size)
683 goto bad;
31ff6488 684 la &= (u32)-1;
618ff15d
AK		 685 break;
686 }
1c11b376
AK		 687 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
688 return emulate_gp(ctxt, 0);
52fd8b44
AK		 689 *linear = la;
690 return X86EMUL_CONTINUE;
618ff15d
AK		 691bad:
692 if (addr.seg == VCPU_SREG_SS)
3606189f 693 return emulate_ss(ctxt, 0);
618ff15d 694 else
3606189f 695 return emulate_gp(ctxt, 0);
52fd8b44
AK		 696}
697
3d9b938e
NE		 698static int linearize(struct x86_emulate_ctxt *ctxt,
699 struct segmented_address addr,
700 unsigned size, bool write,
701 ulong *linear)
702{
fd56e154 703 unsigned max_size;
d50eaa18
NA		 704 return __linearize(ctxt, addr, &max_size, size, write, false,
705 ctxt->mode, linear);
3d9b938e
NE		 706}
707
d50eaa18
NA		 708static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
709 enum x86emul_mode mode)
710{
711 ulong linear;
712 int rc;
713 unsigned max_size;
714 struct segmented_address addr = { .seg = VCPU_SREG_CS,
715 .ea = dst };
716
717 if (ctxt->op_bytes != sizeof(unsigned long))
718 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
719 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
720 if (rc == X86EMUL_CONTINUE)
721 ctxt->_eip = addr.ea;
722 return rc;
723}
724
725static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
726{
727 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 728}
729
d50eaa18
NA		 730static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
731 const struct desc_struct *cs_desc)
732{
733 enum x86emul_mode mode = ctxt->mode;
734
735#ifdef CONFIG_X86_64
736 if (ctxt->mode >= X86EMUL_MODE_PROT32 && cs_desc->l) {
737 u64 efer = 0;
738
739 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
740 if (efer & EFER_LMA)
741 mode = X86EMUL_MODE_PROT64;
742 }
743#endif
744 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
745 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
746 return assign_eip(ctxt, dst, mode);
747}
748
749static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
750{
751 return assign_eip_near(ctxt, ctxt->_eip + rel);
752}
3d9b938e 753
3ca3ac4d
AK		 754static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
755 struct segmented_address addr,
756 void *data,
757 unsigned size)
758{
9fa088f4
AK		 759 int rc;
760 ulong linear;
761
83b8795a 762 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 763 if (rc != X86EMUL_CONTINUE)
764 return rc;
0f65dd70 765 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 766}
767
807941b1 768/*
285ca9e9 769 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 770 * boundary if they are not in fetch_cache yet.
771 */
9506d57d 772static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 773{
62266869 774 int rc;
fd56e154 775 unsigned size, max_size;
285ca9e9 776 unsigned long linear;
17052f16 777 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 778 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 779 .ea = ctxt->eip + cur_size };
780
fd56e154
PB		 781 /*
782 * We do not know exactly how many bytes will be needed, and
783 * __linearize is expensive, so fetch as much as possible. We
784 * just have to avoid going beyond the 15 byte limit, the end
785 * of the segment, or the end of the page.
786 *
787 * __linearize is called with size 0 so that it does not do any
788 * boundary check itself. Instead, we use max_size to check
789 * against op_size.
790 */
d50eaa18
NA		 791 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
792 &linear);
719d5a9b
PB		 793 if (unlikely(rc != X86EMUL_CONTINUE))
794 return rc;
795
fd56e154 796 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 797 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 798
799 /*
800 * One instruction can only straddle two pages,
801 * and one has been loaded at the beginning of
802 * x86_decode_insn. So, if not enough bytes
803 * still, we must have hit the 15-byte boundary.
804 */
805 if (unlikely(size < op_size))
fd56e154
PB		 806 return emulate_gp(ctxt, 0);
807
17052f16 808 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 809 size, &ctxt->exception);
810 if (unlikely(rc != X86EMUL_CONTINUE))
811 return rc;
17052f16 812 ctxt->fetch.end += size;
3e2815e9 813 return X86EMUL_CONTINUE;
62266869
AK		 814}
815
9506d57d
PB		 816static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
817 unsigned size)
62266869 818{
08da44ae
NA		 819 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
820
821 if (unlikely(done_size < size))
822 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 823 else
824 return X86EMUL_CONTINUE;
62266869
AK		 825}
826
67cbc90d 827/* Fetch next part of the instruction being emulated. */
e85a1085 828#define insn_fetch(_type, _ctxt) \
9506d57d 829({ _type _x; \
9506d57d
PB		 830 \
831 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 832 if (rc != X86EMUL_CONTINUE) \
833 goto done; \
9506d57d 834 ctxt->_eip += sizeof(_type); \
17052f16
PB		 835 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
836 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 837 _x; \
67cbc90d
TY		 838})
839
807941b1 840#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 841({ \
9506d57d 842 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 843 if (rc != X86EMUL_CONTINUE) \
844 goto done; \
9506d57d 845 ctxt->_eip += (_size); \
17052f16
PB		 846 memcpy(_arr, ctxt->fetch.ptr, _size); \
847 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 848})
849
1e3c5cb0
RR		 850/*
851 * Given the 'reg' portion of a ModRM byte, and a register block, return a
852 * pointer into the block that addresses the relevant register.
853 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
854 */
dd856efa 855static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 856 int byteop)
6aa8b732
AK		 857{
858 void *p;
aa9ac1a6 859 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 860
6aa8b732 861 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 862 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
863 else
864 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 865 return p;
866}
867
868static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 869 struct segmented_address addr,
6aa8b732
AK		 870 u16 *size, unsigned long *address, int op_bytes)
871{
872 int rc;
873
874 if (op_bytes == 2)
875 op_bytes = 3;
876 *address = 0;
3ca3ac4d 877 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 878 if (rc != X86EMUL_CONTINUE)
6aa8b732 879 return rc;
30b31ab6 880 addr.ea += 2;
3ca3ac4d 881 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 882 return rc;
883}
884
34b77652
AK		 885FASTOP2(add);
886FASTOP2(or);
887FASTOP2(adc);
888FASTOP2(sbb);
889FASTOP2(and);
890FASTOP2(sub);
891FASTOP2(xor);
892FASTOP2(cmp);
893FASTOP2(test);
894
b9fa409b
AK		 895FASTOP1SRC2(mul, mul_ex);
896FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 897FASTOP1SRC2EX(div, div_ex);
898FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 899
34b77652
AK		 900FASTOP3WCL(shld);
901FASTOP3WCL(shrd);
902
903FASTOP2W(imul);
904
905FASTOP1(not);
906FASTOP1(neg);
907FASTOP1(inc);
908FASTOP1(dec);
909
910FASTOP2CL(rol);
911FASTOP2CL(ror);
912FASTOP2CL(rcl);
913FASTOP2CL(rcr);
914FASTOP2CL(shl);
915FASTOP2CL(shr);
916FASTOP2CL(sar);
917
918FASTOP2W(bsf);
919FASTOP2W(bsr);
920FASTOP2W(bt);
921FASTOP2W(bts);
922FASTOP2W(btr);
923FASTOP2W(btc);
924
e47a5f5f
AK		 925FASTOP2(xadd);
926
5aca3722
NA		 927FASTOP2R(cmp, cmp_r);
928
9ae9feba 929static u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 930{
9ae9feba
AK		 931 u8 rc;
932 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 933
9ae9feba 934 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 935 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 936 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
937 return rc;
bbe9abbd
NK		 938}
939
91ff3cb4
AK		 940static void fetch_register_operand(struct operand *op)
941{
942 switch (op->bytes) {
943 case 1:
944 op->val = *(u8 *)op->addr.reg;
945 break;
946 case 2:
947 op->val = *(u16 *)op->addr.reg;
948 break;
949 case 4:
950 op->val = *(u32 *)op->addr.reg;
951 break;
952 case 8:
953 op->val = *(u64 *)op->addr.reg;
954 break;
955 }
956}
957
1253791d
AK		 958static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
959{
960 ctxt->ops->get_fpu(ctxt);
961 switch (reg) {
89a87c67
MK		 962 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
963 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
964 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
965 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
966 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
967 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
968 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
969 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 970#ifdef CONFIG_X86_64
89a87c67
MK		 971 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
972 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
973 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
974 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
975 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
976 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
977 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
978 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 979#endif
980 default: BUG();
981 }
982 ctxt->ops->put_fpu(ctxt);
983}
984
985static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
986 int reg)
987{
988 ctxt->ops->get_fpu(ctxt);
989 switch (reg) {
89a87c67
MK		 990 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
991 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
992 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
993 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
994 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
995 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
996 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
997 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 998#ifdef CONFIG_X86_64
89a87c67
MK		 999 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1000 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1001 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1002 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1003 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1004 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1005 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1006 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1007#endif
1008 default: BUG();
1009 }
1010 ctxt->ops->put_fpu(ctxt);
1011}
1012
cbe2c9d3
AK		 1013static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1014{
1015 ctxt->ops->get_fpu(ctxt);
1016 switch (reg) {
1017 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1018 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1019 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1020 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1021 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1022 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1023 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1024 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1025 default: BUG();
1026 }
1027 ctxt->ops->put_fpu(ctxt);
1028}
1029
1030static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1031{
1032 ctxt->ops->get_fpu(ctxt);
1033 switch (reg) {
1034 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1035 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1036 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1037 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1038 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1039 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1040 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1041 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1042 default: BUG();
1043 }
1044 ctxt->ops->put_fpu(ctxt);
1045}
1046
045a282c
GN		 1047static int em_fninit(struct x86_emulate_ctxt *ctxt)
1048{
1049 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1050 return emulate_nm(ctxt);
1051
1052 ctxt->ops->get_fpu(ctxt);
1053 asm volatile("fninit");
1054 ctxt->ops->put_fpu(ctxt);
1055 return X86EMUL_CONTINUE;
1056}
1057
1058static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1059{
1060 u16 fcw;
1061
1062 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1063 return emulate_nm(ctxt);
1064
1065 ctxt->ops->get_fpu(ctxt);
1066 asm volatile("fnstcw %0": "+m"(fcw));
1067 ctxt->ops->put_fpu(ctxt);
1068
045a282c
GN		 1069 ctxt->dst.val = fcw;
1070
1071 return X86EMUL_CONTINUE;
1072}
1073
1074static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1075{
1076 u16 fsw;
1077
1078 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1079 return emulate_nm(ctxt);
1080
1081 ctxt->ops->get_fpu(ctxt);
1082 asm volatile("fnstsw %0": "+m"(fsw));
1083 ctxt->ops->put_fpu(ctxt);
1084
045a282c
GN		 1085 ctxt->dst.val = fsw;
1086
1087 return X86EMUL_CONTINUE;
1088}
1089
1253791d 1090static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1091 struct operand *op)
3c118e24 1092{
9dac77fa 1093 unsigned reg = ctxt->modrm_reg;
33615aa9 1094
9dac77fa
AK		 1095 if (!(ctxt->d & ModRM))
1096 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1097
9dac77fa 1098 if (ctxt->d & Sse) {
1253791d
AK		 1099 op->type = OP_XMM;
1100 op->bytes = 16;
1101 op->addr.xmm = reg;
1102 read_sse_reg(ctxt, &op->vec_val, reg);
1103 return;
1104 }
cbe2c9d3
AK		 1105 if (ctxt->d & Mmx) {
1106 reg &= 7;
1107 op->type = OP_MM;
1108 op->bytes = 8;
1109 op->addr.mm = reg;
1110 return;
1111 }
1253791d 1112
3c118e24 1113 op->type = OP_REG;
6d4d85ec
GN		 1114 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1115 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1116
91ff3cb4 1117 fetch_register_operand(op);
3c118e24
AK		 1118 op->orig_val = op->val;
1119}
1120
a6e3407b
AK		 1121static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1122{
1123 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1124 ctxt->modrm_seg = VCPU_SREG_SS;
1125}
1126
1c73ef66 1127static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1128 struct operand *op)
1c73ef66 1129{
1c73ef66 1130 u8 sib;
02357bdc 1131 int index_reg, base_reg, scale;
3e2815e9 1132 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1133 ulong modrm_ea = 0;
1c73ef66 1134
02357bdc
BD		 1135 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1136 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1137 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1138
02357bdc 1139 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1140 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1141 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1142 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1143
9b88ae99 1144 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1145 op->type = OP_REG;
9dac77fa 1146 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1147 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1148 ctxt->d & ByteOp);
9dac77fa 1149 if (ctxt->d & Sse) {
1253791d
AK		 1150 op->type = OP_XMM;
1151 op->bytes = 16;
9dac77fa
AK		 1152 op->addr.xmm = ctxt->modrm_rm;
1153 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1154 return rc;
1155 }
cbe2c9d3
AK		 1156 if (ctxt->d & Mmx) {
1157 op->type = OP_MM;
1158 op->bytes = 8;
bdc90722 1159 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1160 return rc;
1161 }
2dbd0dd7 1162 fetch_register_operand(op);
1c73ef66
AK		 1163 return rc;
1164 }
1165
2dbd0dd7
AK		 1166 op->type = OP_MEM;
1167
9dac77fa 1168 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1169 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1170 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1171 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1172 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1173
1174 /* 16-bit ModR/M decode. */
9dac77fa 1175 switch (ctxt->modrm_mod) {
1c73ef66 1176 case 0:
9dac77fa 1177 if (ctxt->modrm_rm == 6)
e85a1085 1178 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1179 break;
1180 case 1:
e85a1085 1181 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1182 break;
1183 case 2:
e85a1085 1184 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1185 break;
1186 }
9dac77fa 1187 switch (ctxt->modrm_rm) {
1c73ef66 1188 case 0:
2dbd0dd7 1189 modrm_ea += bx + si;
1c73ef66
AK		 1190 break;
1191 case 1:
2dbd0dd7 1192 modrm_ea += bx + di;
1c73ef66
AK		 1193 break;
1194 case 2:
2dbd0dd7 1195 modrm_ea += bp + si;
1c73ef66
AK		 1196 break;
1197 case 3:
2dbd0dd7 1198 modrm_ea += bp + di;
1c73ef66
AK		 1199 break;
1200 case 4:
2dbd0dd7 1201 modrm_ea += si;
1c73ef66
AK		 1202 break;
1203 case 5:
2dbd0dd7 1204 modrm_ea += di;
1c73ef66
AK		 1205 break;
1206 case 6:
9dac77fa 1207 if (ctxt->modrm_mod != 0)
2dbd0dd7 1208 modrm_ea += bp;
1c73ef66
AK		 1209 break;
1210 case 7:
2dbd0dd7 1211 modrm_ea += bx;
1c73ef66
AK		 1212 break;
1213 }
9dac77fa
AK		 1214 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1215 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1216 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1217 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1218 } else {
1219 /* 32/64-bit ModR/M decode. */
9dac77fa 1220 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1221 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1222 index_reg |= (sib >> 3) & 7;
1223 base_reg |= sib & 7;
1224 scale = sib >> 6;
1225
9dac77fa 1226 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1227 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1228 else {
dd856efa 1229 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1230 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1231 /* Increment ESP on POP [ESP] */
1232 if ((ctxt->d & IncSP) &&
1233 base_reg == VCPU_REGS_RSP)
1234 modrm_ea += ctxt->op_bytes;
a6e3407b 1235 }
dc71d0f1 1236 if (index_reg != 4)
dd856efa 1237 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1238 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1239 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1240 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1241 ctxt->rip_relative = 1;
a6e3407b
AK		 1242 } else {
1243 base_reg = ctxt->modrm_rm;
dd856efa 1244 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1245 adjust_modrm_seg(ctxt, base_reg);
1246 }
9dac77fa 1247 switch (ctxt->modrm_mod) {
1c73ef66 1248 case 1:
e85a1085 1249 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1250 break;
1251 case 2:
e85a1085 1252 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1253 break;
1254 }
1255 }
90de84f5 1256 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1257 if (ctxt->ad_bytes != 8)
1258 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1259
1c73ef66
AK		 1260done:
1261 return rc;
1262}
1263
1264static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1265 struct operand *op)
1c73ef66 1266{
3e2815e9 1267 int rc = X86EMUL_CONTINUE;
1c73ef66 1268
2dbd0dd7 1269 op->type = OP_MEM;
9dac77fa 1270 switch (ctxt->ad_bytes) {
1c73ef66 1271 case 2:
e85a1085 1272 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1273 break;
1274 case 4:
e85a1085 1275 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1276 break;
1277 case 8:
e85a1085 1278 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1279 break;
1280 }
1281done:
1282 return rc;
1283}
1284
9dac77fa 1285static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1286{
7129eeca 1287 long sv = 0, mask;
35c843c4 1288
9dac77fa 1289 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1290 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1291
9dac77fa
AK		 1292 if (ctxt->src.bytes == 2)
1293 sv = (s16)ctxt->src.val & (s16)mask;
1294 else if (ctxt->src.bytes == 4)
1295 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1296 else
1297 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1298
1c1c35ae
NA		 1299 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1300 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1301 }
ba7ff2b7
WY		 1302
1303 /* only subword offset */
9dac77fa 1304 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1305}
1306
dde7e6d1 1307static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1308 unsigned long addr, void *dest, unsigned size)
6aa8b732 1309{
dde7e6d1 1310 int rc;
9dac77fa 1311 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1312
f23b070e
XG		 1313 if (mc->pos < mc->end)
1314 goto read_cached;
6aa8b732 1315
f23b070e
XG		 1316 WARN_ON((mc->end + size) >= sizeof(mc->data));
1317
1318 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1319 &ctxt->exception);
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 mc->end += size;
1324
1325read_cached:
1326 memcpy(dest, mc->data + mc->pos, size);
1327 mc->pos += size;
dde7e6d1
AK		 1328 return X86EMUL_CONTINUE;
1329}
6aa8b732 1330
3ca3ac4d
AK		 1331static int segmented_read(struct x86_emulate_ctxt *ctxt,
1332 struct segmented_address addr,
1333 void *data,
1334 unsigned size)
1335{
9fa088f4
AK		 1336 int rc;
1337 ulong linear;
1338
83b8795a 1339 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
7b105ca2 1342 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1343}
1344
1345static int segmented_write(struct x86_emulate_ctxt *ctxt,
1346 struct segmented_address addr,
1347 const void *data,
1348 unsigned size)
1349{
9fa088f4
AK		 1350 int rc;
1351 ulong linear;
1352
83b8795a 1353 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1354 if (rc != X86EMUL_CONTINUE)
1355 return rc;
0f65dd70
AK		 1356 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1357 &ctxt->exception);
3ca3ac4d
AK		 1358}
1359
1360static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1361 struct segmented_address addr,
1362 const void *orig_data, const void *data,
1363 unsigned size)
1364{
9fa088f4
AK		 1365 int rc;
1366 ulong linear;
1367
83b8795a 1368 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1369 if (rc != X86EMUL_CONTINUE)
1370 return rc;
0f65dd70
AK		 1371 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1372 size, &ctxt->exception);
3ca3ac4d
AK		 1373}
1374
dde7e6d1 1375static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1376 unsigned int size, unsigned short port,
1377 void *dest)
1378{
9dac77fa 1379 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1380
dde7e6d1 1381 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1382 unsigned int in_page, n;
9dac77fa 1383 unsigned int count = ctxt->rep_prefix ?
dd856efa 1384 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
dde7e6d1 1385 in_page = (ctxt->eflags & EFLG_DF) ?
dd856efa
AK		 1386 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1387 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1388 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1389 if (n == 0)
1390 n = 1;
1391 rc->pos = rc->end = 0;
7b105ca2 1392 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1393 return 0;
1394 rc->end = n * size;
6aa8b732
AK		 1395 }
1396
e6e39f04
NA		 1397 if (ctxt->rep_prefix && (ctxt->d & String) &&
1398 !(ctxt->eflags & EFLG_DF)) {
b3356bf0
GN		 1399 ctxt->dst.data = rc->data + rc->pos;
1400 ctxt->dst.type = OP_MEM_STR;
1401 ctxt->dst.count = (rc->end - rc->pos) / size;
1402 rc->pos = rc->end;
1403 } else {
1404 memcpy(dest, rc->data + rc->pos, size);
1405 rc->pos += size;
1406 }
dde7e6d1
AK		 1407 return 1;
1408}
6aa8b732 1409
7f3d35fd
KW		 1410static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1411 u16 index, struct desc_struct *desc)
1412{
1413 struct desc_ptr dt;
1414 ulong addr;
1415
1416 ctxt->ops->get_idt(ctxt, &dt);
1417
1418 if (dt.size < index * 8 + 7)
1419 return emulate_gp(ctxt, index << 3 | 0x2);
1420
1421 addr = dt.address + index * 8;
1422 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1423 &ctxt->exception);
1424}
1425
dde7e6d1 1426static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1427 u16 selector, struct desc_ptr *dt)
1428{
0225fb50 1429 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1430 u32 base3 = 0;
7b105ca2 1431
dde7e6d1
AK		 1432 if (selector & 1 << 2) {
1433 struct desc_struct desc;
1aa36616
AK		 1434 u16 sel;
1435
dde7e6d1 1436 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1437 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1438 VCPU_SREG_LDTR))
dde7e6d1 1439 return;
e09d082c 1440
dde7e6d1 1441 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1442 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1443 } else
4bff1e86 1444 ops->get_gdt(ctxt, dt);
dde7e6d1 1445}
120df890 1446
dde7e6d1
AK		 1447/* allowed just for 8 bytes segments */
1448static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
e919464b
AK		 1449 u16 selector, struct desc_struct *desc,
1450 ulong *desc_addr_p)
dde7e6d1
AK		 1451{
1452 struct desc_ptr dt;
1453 u16 index = selector >> 3;
dde7e6d1 1454 ulong addr;
120df890 1455
7b105ca2 1456 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1457
35d3d4a1
AK		 1458 if (dt.size < index * 8 + 7)
1459 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1460
e919464b 1461 *desc_addr_p = addr = dt.address + index * 8;
7b105ca2
TY		 1462 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1463 &ctxt->exception);
dde7e6d1 1464}
ef65c889 1465
dde7e6d1
AK		 1466/* allowed just for 8 bytes segments */
1467static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1468 u16 selector, struct desc_struct *desc)
1469{
1470 struct desc_ptr dt;
1471 u16 index = selector >> 3;
dde7e6d1 1472 ulong addr;
6aa8b732 1473
7b105ca2 1474 get_descriptor_table_ptr(ctxt, selector, &dt);
6e3d5dfb 1475
35d3d4a1
AK		 1476 if (dt.size < index * 8 + 7)
1477 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1478
dde7e6d1 1479 addr = dt.address + index * 8;
7b105ca2
TY		 1480 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1481 &ctxt->exception);
dde7e6d1 1482}
c7e75a3d 1483
5601d05b 1484/* Does not support long mode */
2356aaeb 1485static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1486 u16 selector, int seg, u8 cpl,
3dc4bc4f 1487 enum x86_transfer_type transfer,
d1442d85 1488 struct desc_struct *desc)
dde7e6d1 1489{
869be99c 1490 struct desc_struct seg_desc, old_desc;
2356aaeb 1491 u8 dpl, rpl;
dde7e6d1
AK		 1492 unsigned err_vec = GP_VECTOR;
1493 u32 err_code = 0;
1494 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1495 ulong desc_addr;
dde7e6d1 1496 int ret;
03ebebeb 1497 u16 dummy;
e37a75a1 1498 u32 base3 = 0;
69f55cb1 1499
dde7e6d1 1500 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1501
f8da94e9
KW		 1502 if (ctxt->mode == X86EMUL_MODE_REAL) {
1503 /* set real mode segment descriptor (keep limit etc. for
1504 * unreal mode) */
03ebebeb 1505 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1506 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1507 goto load;
f8da94e9
KW		 1508 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1509 /* VM86 needs a clean new segment descriptor */
1510 set_desc_base(&seg_desc, selector << 4);
1511 set_desc_limit(&seg_desc, 0xffff);
1512 seg_desc.type = 3;
1513 seg_desc.p = 1;
1514 seg_desc.s = 1;
1515 seg_desc.dpl = 3;
1516 goto load;
dde7e6d1
AK		 1517 }
1518
79d5b4c3 1519 rpl = selector & 3;
79d5b4c3
AK		 1520
1521 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1522 if ((seg == VCPU_SREG_CS
1523 || (seg == VCPU_SREG_SS
1524 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1525 || seg == VCPU_SREG_TR)
dde7e6d1
AK		 1526 && null_selector)
1527 goto exception;
1528
1529 /* TR should be in GDT only */
1530 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1531 goto exception;
1532
1533 if (null_selector) /* for NULL selector skip all following checks */
1534 goto load;
1535
e919464b 1536 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1537 if (ret != X86EMUL_CONTINUE)
1538 return ret;
1539
1540 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1541 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1542 GP_VECTOR;
dde7e6d1 1543
fc058680 1544 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1545 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1546 if (transfer == X86_TRANSFER_CALL_JMP)
1547 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1548 goto exception;
3dc4bc4f 1549 }
dde7e6d1
AK		 1550
1551 if (!seg_desc.p) {
1552 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1553 goto exception;
1554 }
1555
dde7e6d1 1556 dpl = seg_desc.dpl;
dde7e6d1
AK		 1557
1558 switch (seg) {
1559 case VCPU_SREG_SS:
1560 /*
1561 * segment is not a writable data segment or segment
1562 * selector's RPL != CPL or segment selector's RPL != CPL
1563 */
1564 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1565 goto exception;
6aa8b732 1566 break;
dde7e6d1
AK		 1567 case VCPU_SREG_CS:
1568 if (!(seg_desc.type & 8))
1569 goto exception;
1570
1571 if (seg_desc.type & 4) {
1572 /* conforming */
1573 if (dpl > cpl)
1574 goto exception;
1575 } else {
1576 /* nonconforming */
1577 if (rpl > cpl || dpl != cpl)
1578 goto exception;
1579 }
040c8dc8
NA		 1580 /* in long-mode d/b must be clear if l is set */
1581 if (seg_desc.d && seg_desc.l) {
1582 u64 efer = 0;
1583
1584 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1585 if (efer & EFER_LMA)
1586 goto exception;
1587 }
1588
dde7e6d1
AK		 1589 /* CS(RPL) <- CPL */
1590 selector = (selector & 0xfffc) | cpl;
6aa8b732 1591 break;
dde7e6d1
AK		 1592 case VCPU_SREG_TR:
1593 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1594 goto exception;
869be99c
AK		 1595 old_desc = seg_desc;
1596 seg_desc.type |= 2; /* busy */
1597 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1598 sizeof(seg_desc), &ctxt->exception);
1599 if (ret != X86EMUL_CONTINUE)
1600 return ret;
dde7e6d1
AK		 1601 break;
1602 case VCPU_SREG_LDTR:
1603 if (seg_desc.s || seg_desc.type != 2)
1604 goto exception;
1605 break;
1606 default: /* DS, ES, FS, or GS */
4e62417b 1607 /*
dde7e6d1
AK		 1608 * segment is not a data or readable code segment or
1609 * ((segment is a data or nonconforming code segment)
1610 * and (both RPL and CPL > DPL))
4e62417b 1611 */
dde7e6d1
AK		 1612 if ((seg_desc.type & 0xa) == 0x8 ||
1613 (((seg_desc.type & 0xc) != 0xc) &&
1614 (rpl > dpl && cpl > dpl)))
1615 goto exception;
6aa8b732 1616 break;
dde7e6d1
AK		 1617 }
1618
1619 if (seg_desc.s) {
1620 /* mark segment as accessed */
e2cefa74
NA		 1621 if (!(seg_desc.type & 1)) {
1622 seg_desc.type |= 1;
1623 ret = write_segment_descriptor(ctxt, selector,
1624 &seg_desc);
1625 if (ret != X86EMUL_CONTINUE)
1626 return ret;
1627 }
e37a75a1
NA		 1628 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1629 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1630 sizeof(base3), &ctxt->exception);
1631 if (ret != X86EMUL_CONTINUE)
1632 return ret;
9a9abf6b
NA		 1633 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1634 ((u64)base3 << 32)))
1635 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1636 }
1637load:
e37a75a1 1638 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1639 if (desc)
1640 *desc = seg_desc;
dde7e6d1
AK		 1641 return X86EMUL_CONTINUE;
1642exception:
592f0858 1643 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1644}
1645
2356aaeb
PB		 1646static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1647 u16 selector, int seg)
1648{
1649 u8 cpl = ctxt->ops->cpl(ctxt);
3dc4bc4f
NA		 1650 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1651 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1652}
1653
31be40b3
WY		 1654static void write_register_operand(struct operand *op)
1655{
1656 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1657 switch (op->bytes) {
1658 case 1:
1659 *(u8 *)op->addr.reg = (u8)op->val;
1660 break;
1661 case 2:
1662 *(u16 *)op->addr.reg = (u16)op->val;
1663 break;
1664 case 4:
1665 *op->addr.reg = (u32)op->val;
1666 break; /* 64b: zero-extend */
1667 case 8:
1668 *op->addr.reg = op->val;
1669 break;
1670 }
1671}
1672
fb32b1ed 1673static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1674{
fb32b1ed 1675 switch (op->type) {
dde7e6d1 1676 case OP_REG:
fb32b1ed 1677 write_register_operand(op);
6aa8b732 1678 break;
dde7e6d1 1679 case OP_MEM:
9dac77fa 1680 if (ctxt->lock_prefix)
f5f87dfb
PB		 1681 return segmented_cmpxchg(ctxt,
1682 op->addr.mem,
1683 &op->orig_val,
1684 &op->val,
1685 op->bytes);
1686 else
1687 return segmented_write(ctxt,
fb32b1ed 1688 op->addr.mem,
fb32b1ed
AK		 1689 &op->val,
1690 op->bytes);
a682e354 1691 break;
b3356bf0 1692 case OP_MEM_STR:
f5f87dfb
PB		 1693 return segmented_write(ctxt,
1694 op->addr.mem,
1695 op->data,
1696 op->bytes * op->count);
b3356bf0 1697 break;
1253791d 1698 case OP_XMM:
fb32b1ed 1699 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1700 break;
cbe2c9d3 1701 case OP_MM:
fb32b1ed 1702 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1703 break;
dde7e6d1
AK		 1704 case OP_NONE:
1705 /* no writeback */
414e6277 1706 break;
dde7e6d1 1707 default:
414e6277 1708 break;
6aa8b732 1709 }
dde7e6d1
AK		 1710 return X86EMUL_CONTINUE;
1711}
6aa8b732 1712
51ddff50 1713static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1714{
4179bb02 1715 struct segmented_address addr;
0dc8d10f 1716
5ad105e5 1717 rsp_increment(ctxt, -bytes);
dd856efa 1718 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1719 addr.seg = VCPU_SREG_SS;
1720
51ddff50
AK		 1721 return segmented_write(ctxt, addr, data, bytes);
1722}
1723
1724static int em_push(struct x86_emulate_ctxt *ctxt)
1725{
4179bb02 1726 /* Disable writeback. */
9dac77fa 1727 ctxt->dst.type = OP_NONE;
51ddff50 1728 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1729}
69f55cb1 1730
dde7e6d1 1731static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1732 void *dest, int len)
1733{
dde7e6d1 1734 int rc;
90de84f5 1735 struct segmented_address addr;
8b4caf66 1736
dd856efa 1737 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1738 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1739 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1740 if (rc != X86EMUL_CONTINUE)
1741 return rc;
1742
5ad105e5 1743 rsp_increment(ctxt, len);
dde7e6d1 1744 return rc;
8b4caf66
LV		 1745}
1746
c54fe504
TY		 1747static int em_pop(struct x86_emulate_ctxt *ctxt)
1748{
9dac77fa 1749 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1750}
1751
dde7e6d1 1752static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1753 void *dest, int len)
9de41573
GN		 1754{
1755 int rc;
dde7e6d1
AK		 1756 unsigned long val, change_mask;
1757 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 1758 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1759
3b9be3bf 1760 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1761 if (rc != X86EMUL_CONTINUE)
1762 return rc;
9de41573 1763
dde7e6d1 1764 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
163b135e 1765 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
9de41573 1766
dde7e6d1
AK		 1767 switch(ctxt->mode) {
1768 case X86EMUL_MODE_PROT64:
1769 case X86EMUL_MODE_PROT32:
1770 case X86EMUL_MODE_PROT16:
1771 if (cpl == 0)
1772 change_mask |= EFLG_IOPL;
1773 if (cpl <= iopl)
1774 change_mask |= EFLG_IF;
1775 break;
1776 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1777 if (iopl < 3)
1778 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1779 change_mask |= EFLG_IF;
1780 break;
1781 default: /* real mode */
1782 change_mask |= (EFLG_IOPL | EFLG_IF);
1783 break;
9de41573 1784 }
dde7e6d1
AK		 1785
1786 *(unsigned long *)dest =
1787 (ctxt->eflags & ~change_mask) | (val & change_mask);
1788
1789 return rc;
9de41573
GN		 1790}
1791
62aaa2f0
TY		 1792static int em_popf(struct x86_emulate_ctxt *ctxt)
1793{
9dac77fa
AK		 1794 ctxt->dst.type = OP_REG;
1795 ctxt->dst.addr.reg = &ctxt->eflags;
1796 ctxt->dst.bytes = ctxt->op_bytes;
1797 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1798}
1799
612e89f0
AK		 1800static int em_enter(struct x86_emulate_ctxt *ctxt)
1801{
1802 int rc;
1803 unsigned frame_size = ctxt->src.val;
1804 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1805 ulong rbp;
612e89f0
AK		 1806
1807 if (nesting_level)
1808 return X86EMUL_UNHANDLEABLE;
1809
dd856efa
AK		 1810 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1811 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1812 if (rc != X86EMUL_CONTINUE)
1813 return rc;
dd856efa 1814 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1815 stack_mask(ctxt));
dd856efa
AK		 1816 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1817 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1818 stack_mask(ctxt));
1819 return X86EMUL_CONTINUE;
1820}
1821
f47cfa31
AK		 1822static int em_leave(struct x86_emulate_ctxt *ctxt)
1823{
dd856efa 1824 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1825 stack_mask(ctxt));
dd856efa 1826 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1827}
1828
1cd196ea 1829static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1830{
1cd196ea
AK		 1831 int seg = ctxt->src2.val;
1832
9dac77fa 1833 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1834 if (ctxt->op_bytes == 4) {
1835 rsp_increment(ctxt, -2);
1836 ctxt->op_bytes = 2;
1837 }
7b262e90 1838
4487b3b4 1839 return em_push(ctxt);
7b262e90
GN		 1840}
1841
1cd196ea 1842static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1843{
1cd196ea 1844 int seg = ctxt->src2.val;
dde7e6d1
AK		 1845 unsigned long selector;
1846 int rc;
38ba30ba 1847
3313bc4e 1848 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1849 if (rc != X86EMUL_CONTINUE)
1850 return rc;
1851
a5457e7b
PB		 1852 if (ctxt->modrm_reg == VCPU_SREG_SS)
1853 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1854 if (ctxt->op_bytes > 2)
1855 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1856
7b105ca2 1857 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1858 return rc;
38ba30ba
GN		 1859}
1860
b96a7fad 1861static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1862{
dd856efa 1863 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1864 int rc = X86EMUL_CONTINUE;
1865 int reg = VCPU_REGS_RAX;
38ba30ba 1866
dde7e6d1
AK		 1867 while (reg <= VCPU_REGS_RDI) {
1868 (reg == VCPU_REGS_RSP) ?
dd856efa 1869 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1870
4487b3b4 1871 rc = em_push(ctxt);
dde7e6d1
AK		 1872 if (rc != X86EMUL_CONTINUE)
1873 return rc;
38ba30ba 1874
dde7e6d1 1875 ++reg;
38ba30ba 1876 }
38ba30ba 1877
dde7e6d1 1878 return rc;
38ba30ba
GN		 1879}
1880
62aaa2f0
TY		 1881static int em_pushf(struct x86_emulate_ctxt *ctxt)
1882{
bc397a6c 1883 ctxt->src.val = (unsigned long)ctxt->eflags & ~EFLG_VM;
62aaa2f0
TY		 1884 return em_push(ctxt);
1885}
1886
b96a7fad 1887static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1888{
dde7e6d1
AK		 1889 int rc = X86EMUL_CONTINUE;
1890 int reg = VCPU_REGS_RDI;
38ba30ba 1891
dde7e6d1
AK		 1892 while (reg >= VCPU_REGS_RAX) {
1893 if (reg == VCPU_REGS_RSP) {
5ad105e5 1894 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 1895 --reg;
1896 }
38ba30ba 1897
dd856efa 1898 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
dde7e6d1
AK		 1899 if (rc != X86EMUL_CONTINUE)
1900 break;
1901 --reg;
38ba30ba 1902 }
dde7e6d1 1903 return rc;
38ba30ba
GN		 1904}
1905
dd856efa 1906static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 1907{
0225fb50 1908 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 1909 int rc;
6e154e56
MG		 1910 struct desc_ptr dt;
1911 gva_t cs_addr;
1912 gva_t eip_addr;
1913 u16 cs, eip;
6e154e56
MG		 1914
1915 /* TODO: Add limit checks */
9dac77fa 1916 ctxt->src.val = ctxt->eflags;
4487b3b4 1917 rc = em_push(ctxt);
5c56e1cf
AK		 1918 if (rc != X86EMUL_CONTINUE)
1919 return rc;
6e154e56
MG		 1920
1921 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1922
9dac77fa 1923 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1924 rc = em_push(ctxt);
5c56e1cf
AK		 1925 if (rc != X86EMUL_CONTINUE)
1926 return rc;
6e154e56 1927
9dac77fa 1928 ctxt->src.val = ctxt->_eip;
4487b3b4 1929 rc = em_push(ctxt);
5c56e1cf
AK		 1930 if (rc != X86EMUL_CONTINUE)
1931 return rc;
1932
4bff1e86 1933 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1934
1935 eip_addr = dt.address + (irq << 2);
1936 cs_addr = dt.address + (irq << 2) + 2;
1937
0f65dd70 1938 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1939 if (rc != X86EMUL_CONTINUE)
1940 return rc;
1941
0f65dd70 1942 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1943 if (rc != X86EMUL_CONTINUE)
1944 return rc;
1945
7b105ca2 1946 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 1947 if (rc != X86EMUL_CONTINUE)
1948 return rc;
1949
9dac77fa 1950 ctxt->_eip = eip;
6e154e56
MG		 1951
1952 return rc;
1953}
1954
dd856efa
AK		 1955int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1956{
1957 int rc;
1958
1959 invalidate_registers(ctxt);
1960 rc = __emulate_int_real(ctxt, irq);
1961 if (rc == X86EMUL_CONTINUE)
1962 writeback_registers(ctxt);
1963 return rc;
1964}
1965
7b105ca2 1966static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 1967{
1968 switch(ctxt->mode) {
1969 case X86EMUL_MODE_REAL:
dd856efa 1970 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 1971 case X86EMUL_MODE_VM86:
1972 case X86EMUL_MODE_PROT16:
1973 case X86EMUL_MODE_PROT32:
1974 case X86EMUL_MODE_PROT64:
1975 default:
1976 /* Protected mode interrupts unimplemented yet */
1977 return X86EMUL_UNHANDLEABLE;
1978 }
1979}
1980
7b105ca2 1981static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 1982{
dde7e6d1
AK		 1983 int rc = X86EMUL_CONTINUE;
1984 unsigned long temp_eip = 0;
1985 unsigned long temp_eflags = 0;
1986 unsigned long cs = 0;
1987 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1988 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1989 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1990 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1991
dde7e6d1 1992 /* TODO: Add stack limit check */
38ba30ba 1993
9dac77fa 1994 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 1995
dde7e6d1
AK		 1996 if (rc != X86EMUL_CONTINUE)
1997 return rc;
38ba30ba 1998
35d3d4a1
AK		 1999 if (temp_eip & ~0xffff)
2000 return emulate_gp(ctxt, 0);
38ba30ba 2001
9dac77fa 2002 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2003
dde7e6d1
AK		 2004 if (rc != X86EMUL_CONTINUE)
2005 return rc;
38ba30ba 2006
9dac77fa 2007 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2008
dde7e6d1
AK		 2009 if (rc != X86EMUL_CONTINUE)
2010 return rc;
38ba30ba 2011
7b105ca2 2012 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2013
dde7e6d1
AK		 2014 if (rc != X86EMUL_CONTINUE)
2015 return rc;
38ba30ba 2016
9dac77fa 2017 ctxt->_eip = temp_eip;
38ba30ba 2018
38ba30ba 2019
9dac77fa 2020 if (ctxt->op_bytes == 4)
dde7e6d1 2021 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2022 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2023 ctxt->eflags &= ~0xffff;
2024 ctxt->eflags |= temp_eflags;
38ba30ba 2025 }
dde7e6d1
AK		 2026
2027 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2028 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2029
2030 return rc;
38ba30ba
GN		 2031}
2032
e01991e7 2033static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2034{
dde7e6d1
AK		 2035 switch(ctxt->mode) {
2036 case X86EMUL_MODE_REAL:
7b105ca2 2037 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2038 case X86EMUL_MODE_VM86:
2039 case X86EMUL_MODE_PROT16:
2040 case X86EMUL_MODE_PROT32:
2041 case X86EMUL_MODE_PROT64:
c37eda13 2042 default:
dde7e6d1
AK		 2043 /* iret from protected mode unimplemented yet */
2044 return X86EMUL_UNHANDLEABLE;
c37eda13 2045 }
c37eda13
WY		 2046}
2047
d2f62766
TY		 2048static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2049{
d2f62766 2050 int rc;
d1442d85
NA		 2051 unsigned short sel, old_sel;
2052 struct desc_struct old_desc, new_desc;
2053 const struct x86_emulate_ops *ops = ctxt->ops;
2054 u8 cpl = ctxt->ops->cpl(ctxt);
2055
2056 /* Assignment of RIP may only fail in 64-bit mode */
2057 if (ctxt->mode == X86EMUL_MODE_PROT64)
2058 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2059 VCPU_SREG_CS);
d2f62766 2060
9dac77fa 2061 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2062
3dc4bc4f
NA		 2063 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2064 X86_TRANSFER_CALL_JMP,
d1442d85 2065 &new_desc);
d2f62766
TY		 2066 if (rc != X86EMUL_CONTINUE)
2067 return rc;
2068
d50eaa18 2069 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85 2070 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2071 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2072 /* assigning eip failed; restore the old cs */
2073 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2074 return rc;
2075 }
2076 return rc;
d2f62766
TY		 2077}
2078
f7784046 2079static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2080{
f7784046
NA		 2081 return assign_eip_near(ctxt, ctxt->src.val);
2082}
8cdbd2c9 2083
f7784046
NA		 2084static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2085{
2086 int rc;
2087 long int old_eip;
2088
2089 old_eip = ctxt->_eip;
2090 rc = assign_eip_near(ctxt, ctxt->src.val);
2091 if (rc != X86EMUL_CONTINUE)
2092 return rc;
2093 ctxt->src.val = old_eip;
2094 rc = em_push(ctxt);
4179bb02 2095 return rc;
8cdbd2c9
LV		 2096}
2097
e0dac408 2098static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2099{
9dac77fa 2100 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2101
aaa05f24
NA		 2102 if (ctxt->dst.bytes == 16)
2103 return X86EMUL_UNHANDLEABLE;
2104
dd856efa
AK		 2105 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2106 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2107 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2108 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
05f086f8 2109 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 2110 } else {
dd856efa
AK		 2111 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2112 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2113
05f086f8 2114 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 2115 }
1b30eaa8 2116 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2117}
2118
ebda02c2
TY		 2119static int em_ret(struct x86_emulate_ctxt *ctxt)
2120{
234f3ce4
NA		 2121 int rc;
2122 unsigned long eip;
2123
2124 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2125 if (rc != X86EMUL_CONTINUE)
2126 return rc;
2127
2128 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2129}
2130
e01991e7 2131static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2132{
a77ab5ea 2133 int rc;
d1442d85
NA		 2134 unsigned long eip, cs;
2135 u16 old_cs;
9e8919ae 2136 int cpl = ctxt->ops->cpl(ctxt);
d1442d85
NA		 2137 struct desc_struct old_desc, new_desc;
2138 const struct x86_emulate_ops *ops = ctxt->ops;
2139
2140 if (ctxt->mode == X86EMUL_MODE_PROT64)
2141 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2142 VCPU_SREG_CS);
a77ab5ea 2143
d1442d85 2144 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2145 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2146 return rc;
9dac77fa 2147 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2148 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2149 return rc;
9e8919ae
NA		 2150 /* Outer-privilege level return is not implemented */
2151 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2152 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2153 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2154 X86_TRANSFER_RET,
d1442d85
NA		 2155 &new_desc);
2156 if (rc != X86EMUL_CONTINUE)
2157 return rc;
d50eaa18 2158 rc = assign_eip_far(ctxt, eip, &new_desc);
d1442d85 2159 if (rc != X86EMUL_CONTINUE) {
7e46dddd 2160 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
d1442d85
NA		 2161 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2162 }
a77ab5ea
AK		 2163 return rc;
2164}
2165
3261107e
BR		 2166static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2167{
2168 int rc;
2169
2170 rc = em_ret_far(ctxt);
2171 if (rc != X86EMUL_CONTINUE)
2172 return rc;
2173 rsp_increment(ctxt, ctxt->src.val);
2174 return X86EMUL_CONTINUE;
2175}
2176
e940b5c2
TY		 2177static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2178{
2179 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2180 ctxt->dst.orig_val = ctxt->dst.val;
2181 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2182 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2183 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2184 fastop(ctxt, em_cmp);
e940b5c2
TY		 2185
2186 if (ctxt->eflags & EFLG_ZF) {
2187 /* Success: write back to memory. */
2188 ctxt->dst.val = ctxt->src.orig_val;
2189 } else {
2190 /* Failure: write the value we saw to EAX. */
2191 ctxt->dst.type = OP_REG;
dd856efa 2192 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
37c564f2 2193 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2194 }
2195 return X86EMUL_CONTINUE;
2196}
2197
d4b4325f 2198static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2199{
d4b4325f 2200 int seg = ctxt->src2.val;
09b5f4d3
WY		 2201 unsigned short sel;
2202 int rc;
2203
9dac77fa 2204 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2205
7b105ca2 2206 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2207 if (rc != X86EMUL_CONTINUE)
2208 return rc;
2209
9dac77fa 2210 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2211 return rc;
2212}
2213
7b105ca2 2214static void
e66bb2cc 2215setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2216 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2217{
e66bb2cc 2218 cs->l = 0; /* will be adjusted later */
79168fd1 2219 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2220 cs->g = 1; /* 4kb granularity */
79168fd1 2221 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2222 cs->type = 0x0b; /* Read, Execute, Accessed */
2223 cs->s = 1;
2224 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2225 cs->p = 1;
2226 cs->d = 1;
99245b50 2227 cs->avl = 0;
e66bb2cc 2228
79168fd1
GN		 2229 set_desc_base(ss, 0); /* flat segment */
2230 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2231 ss->g = 1; /* 4kb granularity */
2232 ss->s = 1;
2233 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2234 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2235 ss->dpl = 0;
79168fd1 2236 ss->p = 1;
99245b50
GN		 2237 ss->l = 0;
2238 ss->avl = 0;
e66bb2cc
AP		 2239}
2240
1a18a69b
AK		 2241static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2242{
2243 u32 eax, ebx, ecx, edx;
2244
2245 eax = ecx = 0;
0017f93a
AK		 2246 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2247 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2248 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2249 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2250}
2251
c2226fc9
SB		 2252static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2253{
0225fb50 2254 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2255 u32 eax, ebx, ecx, edx;
2256
2257 /*
2258 * syscall should always be enabled in longmode - so only become
2259 * vendor specific (cpuid) if other modes are active...
2260 */
2261 if (ctxt->mode == X86EMUL_MODE_PROT64)
2262 return true;
2263
2264 eax = 0x00000000;
2265 ecx = 0x00000000;
0017f93a
AK		 2266 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2267 /*
2268 * Intel ("GenuineIntel")
2269 * remark: Intel CPUs only support "syscall" in 64bit
2270 * longmode. Also an 64bit guest with a
2271 * 32bit compat-app running will #UD !! While this
2272 * behaviour can be fixed (by emulating) into AMD
2273 * response - CPUs of AMD can't behave like Intel.
2274 */
2275 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2276 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2277 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2278 return false;
2279
2280 /* AMD ("AuthenticAMD") */
2281 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2282 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2283 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2284 return true;
2285
2286 /* AMD ("AMDisbetter!") */
2287 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2288 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2289 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2290 return true;
c2226fc9
SB		 2291
2292 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2293 return false;
2294}
2295
e01991e7 2296static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2297{
0225fb50 2298 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2299 struct desc_struct cs, ss;
e66bb2cc 2300 u64 msr_data;
79168fd1 2301 u16 cs_sel, ss_sel;
c2ad2bb3 2302 u64 efer = 0;
e66bb2cc
AP		 2303
2304 /* syscall is not available in real mode */
2e901c4c 2305 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2306 ctxt->mode == X86EMUL_MODE_VM86)
2307 return emulate_ud(ctxt);
e66bb2cc 2308
c2226fc9
SB		 2309 if (!(em_syscall_is_enabled(ctxt)))
2310 return emulate_ud(ctxt);
2311
c2ad2bb3 2312 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2313 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2314
c2226fc9
SB		 2315 if (!(efer & EFER_SCE))
2316 return emulate_ud(ctxt);
2317
717746e3 2318 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2319 msr_data >>= 32;
79168fd1
GN		 2320 cs_sel = (u16)(msr_data & 0xfffc);
2321 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2322
c2ad2bb3 2323 if (efer & EFER_LMA) {
79168fd1 2324 cs.d = 0;
e66bb2cc
AP		 2325 cs.l = 1;
2326 }
1aa36616
AK		 2327 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2328 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2329
dd856efa 2330 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2331 if (efer & EFER_LMA) {
e66bb2cc 2332#ifdef CONFIG_X86_64
6c6cb69b 2333 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2334
717746e3 2335 ops->get_msr(ctxt,
3fb1b5db
GN		 2336 ctxt->mode == X86EMUL_MODE_PROT64 ?
2337 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2338 ctxt->_eip = msr_data;
e66bb2cc 2339
717746e3 2340 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2341 ctxt->eflags &= ~msr_data;
807c1425 2342 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
e66bb2cc
AP		 2343#endif
2344 } else {
2345 /* legacy mode */
717746e3 2346 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2347 ctxt->_eip = (u32)msr_data;
e66bb2cc 2348
6c6cb69b 2349 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
e66bb2cc
AP		 2350 }
2351
e54cfa97 2352 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2353}
2354
e01991e7 2355static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2356{
0225fb50 2357 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2358 struct desc_struct cs, ss;
8c604352 2359 u64 msr_data;
79168fd1 2360 u16 cs_sel, ss_sel;
c2ad2bb3 2361 u64 efer = 0;
8c604352 2362
7b105ca2 2363 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2364 /* inject #GP if in real mode */
35d3d4a1
AK		 2365 if (ctxt->mode == X86EMUL_MODE_REAL)
2366 return emulate_gp(ctxt, 0);
8c604352 2367
1a18a69b
AK		 2368 /*
2369 * Not recognized on AMD in compat mode (but is recognized in legacy
2370 * mode).
2371 */
2372 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2373 && !vendor_intel(ctxt))
2374 return emulate_ud(ctxt);
2375
b2c9d43e 2376 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2377 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2378 return X86EMUL_UNHANDLEABLE;
8c604352 2379
7b105ca2 2380 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2381
717746e3 2382 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 2383 switch (ctxt->mode) {
2384 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 2385 if ((msr_data & 0xfffc) == 0x0)
2386 return emulate_gp(ctxt, 0);
8c604352
AP		 2387 break;
2388 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 2389 if (msr_data == 0x0)
2390 return emulate_gp(ctxt, 0);
8c604352 2391 break;
9d1b39a9
GN		 2392 default:
2393 break;
8c604352
AP		 2394 }
2395
6c6cb69b 2396 ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
79168fd1
GN		 2397 cs_sel = (u16)msr_data;
2398 cs_sel &= ~SELECTOR_RPL_MASK;
2399 ss_sel = cs_sel + 8;
2400 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 2401 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 2402 cs.d = 0;
8c604352
AP		 2403 cs.l = 1;
2404 }
2405
1aa36616
AK		 2406 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2407 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2408
717746e3 2409 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
9dac77fa 2410 ctxt->_eip = msr_data;
8c604352 2411
717746e3 2412 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
dd856efa 2413 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
8c604352 2414
e54cfa97 2415 return X86EMUL_CONTINUE;
8c604352
AP		 2416}
2417
e01991e7 2418static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2419{
0225fb50 2420 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2421 struct desc_struct cs, ss;
234f3ce4 2422 u64 msr_data, rcx, rdx;
4668f050 2423 int usermode;
1249b96e 2424 u16 cs_sel = 0, ss_sel = 0;
4668f050 2425
a0044755
GN		 2426 /* inject #GP if in real mode or Virtual 8086 mode */
2427 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2428 ctxt->mode == X86EMUL_MODE_VM86)
2429 return emulate_gp(ctxt, 0);
4668f050 2430
7b105ca2 2431 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2432
9dac77fa 2433 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2434 usermode = X86EMUL_MODE_PROT64;
2435 else
2436 usermode = X86EMUL_MODE_PROT32;
2437
234f3ce4
NA		 2438 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2439 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2440
4668f050
AP		 2441 cs.dpl = 3;
2442 ss.dpl = 3;
717746e3 2443 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2444 switch (usermode) {
2445 case X86EMUL_MODE_PROT32:
79168fd1 2446 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2447 if ((msr_data & 0xfffc) == 0x0)
2448 return emulate_gp(ctxt, 0);
79168fd1 2449 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2450 rcx = (u32)rcx;
2451 rdx = (u32)rdx;
4668f050
AP		 2452 break;
2453 case X86EMUL_MODE_PROT64:
79168fd1 2454 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2455 if (msr_data == 0x0)
2456 return emulate_gp(ctxt, 0);
79168fd1
GN		 2457 ss_sel = cs_sel + 8;
2458 cs.d = 0;
4668f050 2459 cs.l = 1;
234f3ce4
NA		 2460 if (is_noncanonical_address(rcx) ||
2461 is_noncanonical_address(rdx))
2462 return emulate_gp(ctxt, 0);
4668f050
AP		 2463 break;
2464 }
79168fd1
GN		 2465 cs_sel |= SELECTOR_RPL_MASK;
2466 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2467
1aa36616
AK		 2468 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2469 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2470
234f3ce4
NA		 2471 ctxt->_eip = rdx;
2472 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2473
e54cfa97 2474 return X86EMUL_CONTINUE;
4668f050
AP		 2475}
2476
7b105ca2 2477static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2478{
2479 int iopl;
2480 if (ctxt->mode == X86EMUL_MODE_REAL)
2481 return false;
2482 if (ctxt->mode == X86EMUL_MODE_VM86)
2483 return true;
2484 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
7b105ca2 2485 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2486}
2487
2488static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2489 u16 port, u16 len)
2490{
0225fb50 2491 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2492 struct desc_struct tr_seg;
5601d05b 2493 u32 base3;
f850e2e6 2494 int r;
1aa36616 2495 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2496 unsigned mask = (1 << len) - 1;
5601d05b 2497 unsigned long base;
f850e2e6 2498
1aa36616 2499 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2500 if (!tr_seg.p)
f850e2e6 2501 return false;
79168fd1 2502 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2503 return false;
5601d05b
GN		 2504 base = get_desc_base(&tr_seg);
2505#ifdef CONFIG_X86_64
2506 base |= ((u64)base3) << 32;
2507#endif
0f65dd70 2508 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2509 if (r != X86EMUL_CONTINUE)
2510 return false;
79168fd1 2511 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2512 return false;
0f65dd70 2513 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2514 if (r != X86EMUL_CONTINUE)
2515 return false;
2516 if ((perm >> bit_idx) & mask)
2517 return false;
2518 return true;
2519}
2520
2521static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2522 u16 port, u16 len)
2523{
4fc40f07
GN		 2524 if (ctxt->perm_ok)
2525 return true;
2526
7b105ca2
TY		 2527 if (emulator_bad_iopl(ctxt))
2528 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2529 return false;
4fc40f07
GN		 2530
2531 ctxt->perm_ok = true;
2532
f850e2e6
GN		 2533 return true;
2534}
2535
38ba30ba 2536static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2537 struct tss_segment_16 *tss)
2538{
9dac77fa 2539 tss->ip = ctxt->_eip;
38ba30ba 2540 tss->flag = ctxt->eflags;
dd856efa
AK		 2541 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2542 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2543 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2544 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2545 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2546 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2547 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2548 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2549
1aa36616
AK		 2550 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2551 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2552 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2553 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2554 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2555}
2556
2557static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2558 struct tss_segment_16 *tss)
2559{
38ba30ba 2560 int ret;
2356aaeb 2561 u8 cpl;
38ba30ba 2562
9dac77fa 2563 ctxt->_eip = tss->ip;
38ba30ba 2564 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2565 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2566 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2567 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2568 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2569 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2570 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2571 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2572 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2573
2574 /*
2575 * SDM says that segment selectors are loaded before segment
2576 * descriptors
2577 */
1aa36616
AK		 2578 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2579 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2580 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2581 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2582 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2583
2356aaeb
PB		 2584 cpl = tss->cs & 3;
2585
38ba30ba 2586 /*
fc058680 2587 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2588 * it is handled in a context of new task
2589 */
d1442d85 2590 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2591 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2592 if (ret != X86EMUL_CONTINUE)
2593 return ret;
d1442d85 2594 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2595 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2596 if (ret != X86EMUL_CONTINUE)
2597 return ret;
d1442d85 2598 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2599 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2600 if (ret != X86EMUL_CONTINUE)
2601 return ret;
d1442d85 2602 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2603 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2604 if (ret != X86EMUL_CONTINUE)
2605 return ret;
d1442d85 2606 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2607 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2608 if (ret != X86EMUL_CONTINUE)
2609 return ret;
2610
2611 return X86EMUL_CONTINUE;
2612}
2613
2614static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2615 u16 tss_selector, u16 old_tss_sel,
2616 ulong old_tss_base, struct desc_struct *new_desc)
2617{
0225fb50 2618 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2619 struct tss_segment_16 tss_seg;
2620 int ret;
bcc55cba 2621 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2622
0f65dd70 2623 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2624 &ctxt->exception);
db297e3d 2625 if (ret != X86EMUL_CONTINUE)
38ba30ba 2626 return ret;
38ba30ba 2627
7b105ca2 2628 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 2629
0f65dd70 2630 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2631 &ctxt->exception);
db297e3d 2632 if (ret != X86EMUL_CONTINUE)
38ba30ba 2633 return ret;
38ba30ba 2634
0f65dd70 2635 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2636 &ctxt->exception);
db297e3d 2637 if (ret != X86EMUL_CONTINUE)
38ba30ba 2638 return ret;
38ba30ba
GN		 2639
2640 if (old_tss_sel != 0xffff) {
2641 tss_seg.prev_task_link = old_tss_sel;
2642
0f65dd70 2643 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2644 &tss_seg.prev_task_link,
2645 sizeof tss_seg.prev_task_link,
0f65dd70 2646 &ctxt->exception);
db297e3d 2647 if (ret != X86EMUL_CONTINUE)
38ba30ba 2648 return ret;
38ba30ba
GN		 2649 }
2650
7b105ca2 2651 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 2652}
2653
2654static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2655 struct tss_segment_32 *tss)
2656{
5c7411e2 2657 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 2658 tss->eip = ctxt->_eip;
38ba30ba 2659 tss->eflags = ctxt->eflags;
dd856efa
AK		 2660 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2661 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2662 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2663 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2664 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2665 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2666 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2667 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2668
1aa36616
AK		 2669 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2670 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2671 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2672 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2673 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2674 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 2675}
2676
2677static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2678 struct tss_segment_32 *tss)
2679{
38ba30ba 2680 int ret;
2356aaeb 2681 u8 cpl;
38ba30ba 2682
7b105ca2 2683 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2684 return emulate_gp(ctxt, 0);
9dac77fa 2685 ctxt->_eip = tss->eip;
38ba30ba 2686 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 2687
2688 /* General purpose registers */
dd856efa
AK		 2689 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2690 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2691 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2692 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2693 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2694 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2695 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2696 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 2697
2698 /*
2699 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 2700 * descriptors. This is important because CPL checks will
2701 * use CS.RPL.
38ba30ba 2702 */
1aa36616
AK		 2703 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2704 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2705 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2706 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2707 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2708 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2709 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 2710
4cee4798
KW		 2711 /*
2712 * If we're switching between Protected Mode and VM86, we need to make
2713 * sure to update the mode before loading the segment descriptors so
2714 * that the selectors are interpreted correctly.
4cee4798 2715 */
2356aaeb 2716 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 2717 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 2718 cpl = 3;
2719 } else {
4cee4798 2720 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 2721 cpl = tss->cs & 3;
2722 }
4cee4798 2723
38ba30ba
GN		 2724 /*
2725 * Now load segment descriptors. If fault happenes at this stage
2726 * it is handled in a context of new task
2727 */
d1442d85 2728 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 2729 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2730 if (ret != X86EMUL_CONTINUE)
2731 return ret;
d1442d85 2732 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 2733 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2734 if (ret != X86EMUL_CONTINUE)
2735 return ret;
d1442d85 2736 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 2737 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2738 if (ret != X86EMUL_CONTINUE)
2739 return ret;
d1442d85 2740 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 2741 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2742 if (ret != X86EMUL_CONTINUE)
2743 return ret;
d1442d85 2744 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 2745 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2746 if (ret != X86EMUL_CONTINUE)
2747 return ret;
d1442d85 2748 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 2749 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2750 if (ret != X86EMUL_CONTINUE)
2751 return ret;
d1442d85 2752 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 2753 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2754 if (ret != X86EMUL_CONTINUE)
2755 return ret;
2756
2757 return X86EMUL_CONTINUE;
2758}
2759
2760static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2761 u16 tss_selector, u16 old_tss_sel,
2762 ulong old_tss_base, struct desc_struct *new_desc)
2763{
0225fb50 2764 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2765 struct tss_segment_32 tss_seg;
2766 int ret;
bcc55cba 2767 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 2768 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2769 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 2770
0f65dd70 2771 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2772 &ctxt->exception);
db297e3d 2773 if (ret != X86EMUL_CONTINUE)
38ba30ba 2774 return ret;
38ba30ba 2775
7b105ca2 2776 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 2777
5c7411e2
NA		 2778 /* Only GP registers and segment selectors are saved */
2779 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2780 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 2781 if (ret != X86EMUL_CONTINUE)
38ba30ba 2782 return ret;
38ba30ba 2783
0f65dd70 2784 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2785 &ctxt->exception);
db297e3d 2786 if (ret != X86EMUL_CONTINUE)
38ba30ba 2787 return ret;
38ba30ba
GN		 2788
2789 if (old_tss_sel != 0xffff) {
2790 tss_seg.prev_task_link = old_tss_sel;
2791
0f65dd70 2792 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2793 &tss_seg.prev_task_link,
2794 sizeof tss_seg.prev_task_link,
0f65dd70 2795 &ctxt->exception);
db297e3d 2796 if (ret != X86EMUL_CONTINUE)
38ba30ba 2797 return ret;
38ba30ba
GN		 2798 }
2799
7b105ca2 2800 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 2801}
2802
2803static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2804 u16 tss_selector, int idt_index, int reason,
e269fb21 2805 bool has_error_code, u32 error_code)
38ba30ba 2806{
0225fb50 2807 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2808 struct desc_struct curr_tss_desc, next_tss_desc;
2809 int ret;
1aa36616 2810 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2811 ulong old_tss_base =
4bff1e86 2812 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2813 u32 desc_limit;
e919464b 2814 ulong desc_addr;
38ba30ba
GN		 2815
2816 /* FIXME: old_tss_base == ~0 ? */
2817
e919464b 2818 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 2819 if (ret != X86EMUL_CONTINUE)
2820 return ret;
e919464b 2821 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 2822 if (ret != X86EMUL_CONTINUE)
2823 return ret;
2824
2825 /* FIXME: check that next_tss_desc is tss */
2826
7f3d35fd
KW		 2827 /*
2828 * Check privileges. The three cases are task switch caused by...
2829 *
2830 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2831 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 2832 * 3. jmp/call to TSS/task-gate: No check is performed since the
2833 * hardware checks it before exiting.
7f3d35fd
KW		 2834 */
2835 if (reason == TASK_SWITCH_GATE) {
2836 if (idt_index != -1) {
2837 /* Software interrupts */
2838 struct desc_struct task_gate_desc;
2839 int dpl;
2840
2841 ret = read_interrupt_descriptor(ctxt, idt_index,
2842 &task_gate_desc);
2843 if (ret != X86EMUL_CONTINUE)
2844 return ret;
2845
2846 dpl = task_gate_desc.dpl;
2847 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2848 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2849 }
38ba30ba
GN		 2850 }
2851
ceffb459
GN		 2852 desc_limit = desc_limit_scaled(&next_tss_desc);
2853 if (!next_tss_desc.p ||
2854 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2855 desc_limit < 0x2b)) {
592f0858 2856 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2857 }
2858
2859 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2860 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 2861 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 2862 }
2863
2864 if (reason == TASK_SWITCH_IRET)
2865 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2866
2867 /* set back link to prev task only if NT bit is set in eflags
fc058680 2868 note that old_tss_sel is not used after this point */
38ba30ba
GN		 2869 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2870 old_tss_sel = 0xffff;
2871
2872 if (next_tss_desc.type & 8)
7b105ca2 2873 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 2874 old_tss_base, &next_tss_desc);
2875 else
7b105ca2 2876 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 2877 old_tss_base, &next_tss_desc);
0760d448
JK		 2878 if (ret != X86EMUL_CONTINUE)
2879 return ret;
38ba30ba
GN		 2880
2881 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2882 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2883
2884 if (reason != TASK_SWITCH_IRET) {
2885 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 2886 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 2887 }
2888
717746e3 2889 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2890 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2891
e269fb21 2892 if (has_error_code) {
9dac77fa
AK		 2893 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2894 ctxt->lock_prefix = 0;
2895 ctxt->src.val = (unsigned long) error_code;
4487b3b4 2896 ret = em_push(ctxt);
e269fb21
JK		 2897 }
2898
38ba30ba
GN		 2899 return ret;
2900}
2901
2902int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 2903 u16 tss_selector, int idt_index, int reason,
e269fb21 2904 bool has_error_code, u32 error_code)
38ba30ba 2905{
38ba30ba
GN		 2906 int rc;
2907
dd856efa 2908 invalidate_registers(ctxt);
9dac77fa
AK		 2909 ctxt->_eip = ctxt->eip;
2910 ctxt->dst.type = OP_NONE;
38ba30ba 2911
7f3d35fd 2912 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 2913 has_error_code, error_code);
38ba30ba 2914
dd856efa 2915 if (rc == X86EMUL_CONTINUE) {
9dac77fa 2916 ctxt->eip = ctxt->_eip;
dd856efa
AK		 2917 writeback_registers(ctxt);
2918 }
38ba30ba 2919
a0c0ab2f 2920 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2921}
2922
f3bd64c6
GN		 2923static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2924 struct operand *op)
a682e354 2925{
b3356bf0 2926 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
a682e354 2927
01485a22
PB		 2928 register_address_increment(ctxt, reg, df * op->bytes);
2929 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 2930}
2931
7af04fc0
AK		 2932static int em_das(struct x86_emulate_ctxt *ctxt)
2933{
7af04fc0
AK		 2934 u8 al, old_al;
2935 bool af, cf, old_cf;
2936
2937 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 2938 al = ctxt->dst.val;
7af04fc0
AK		 2939
2940 old_al = al;
2941 old_cf = cf;
2942 cf = false;
2943 af = ctxt->eflags & X86_EFLAGS_AF;
2944 if ((al & 0x0f) > 9 || af) {
2945 al -= 6;
2946 cf = old_cf | (al >= 250);
2947 af = true;
2948 } else {
2949 af = false;
2950 }
2951 if (old_al > 0x99 || old_cf) {
2952 al -= 0x60;
2953 cf = true;
2954 }
2955
9dac77fa 2956 ctxt->dst.val = al;
7af04fc0 2957 /* Set PF, ZF, SF */
9dac77fa
AK		 2958 ctxt->src.type = OP_IMM;
2959 ctxt->src.val = 0;
2960 ctxt->src.bytes = 1;
158de57f 2961 fastop(ctxt, em_or);
7af04fc0
AK		 2962 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2963 if (cf)
2964 ctxt->eflags |= X86_EFLAGS_CF;
2965 if (af)
2966 ctxt->eflags |= X86_EFLAGS_AF;
2967 return X86EMUL_CONTINUE;
2968}
2969
a035d5c6
PB		 2970static int em_aam(struct x86_emulate_ctxt *ctxt)
2971{
2972 u8 al, ah;
2973
2974 if (ctxt->src.val == 0)
2975 return emulate_de(ctxt);
2976
2977 al = ctxt->dst.val & 0xff;
2978 ah = al / ctxt->src.val;
2979 al %= ctxt->src.val;
2980
2981 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
2982
2983 /* Set PF, ZF, SF */
2984 ctxt->src.type = OP_IMM;
2985 ctxt->src.val = 0;
2986 ctxt->src.bytes = 1;
2987 fastop(ctxt, em_or);
2988
2989 return X86EMUL_CONTINUE;
2990}
2991
7f662273
GN		 2992static int em_aad(struct x86_emulate_ctxt *ctxt)
2993{
2994 u8 al = ctxt->dst.val & 0xff;
2995 u8 ah = (ctxt->dst.val >> 8) & 0xff;
2996
2997 al = (al + (ah * ctxt->src.val)) & 0xff;
2998
2999 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3000
f583c29b
GN		 3001 /* Set PF, ZF, SF */
3002 ctxt->src.type = OP_IMM;
3003 ctxt->src.val = 0;
3004 ctxt->src.bytes = 1;
3005 fastop(ctxt, em_or);
7f662273
GN		 3006
3007 return X86EMUL_CONTINUE;
3008}
3009
d4ddafcd
TY		 3010static int em_call(struct x86_emulate_ctxt *ctxt)
3011{
234f3ce4 3012 int rc;
d4ddafcd
TY		 3013 long rel = ctxt->src.val;
3014
3015 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3016 rc = jmp_rel(ctxt, rel);
3017 if (rc != X86EMUL_CONTINUE)
3018 return rc;
d4ddafcd
TY		 3019 return em_push(ctxt);
3020}
3021
0ef753b8
AK		 3022static int em_call_far(struct x86_emulate_ctxt *ctxt)
3023{
0ef753b8
AK		 3024 u16 sel, old_cs;
3025 ulong old_eip;
3026 int rc;
d1442d85
NA		 3027 struct desc_struct old_desc, new_desc;
3028 const struct x86_emulate_ops *ops = ctxt->ops;
3029 int cpl = ctxt->ops->cpl(ctxt);
0ef753b8 3030
9dac77fa 3031 old_eip = ctxt->_eip;
d1442d85 3032 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3033
9dac77fa 3034 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3035 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3036 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3037 if (rc != X86EMUL_CONTINUE)
80976dbb 3038 return rc;
0ef753b8 3039
d50eaa18 3040 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3041 if (rc != X86EMUL_CONTINUE)
3042 goto fail;
0ef753b8 3043
9dac77fa 3044 ctxt->src.val = old_cs;
4487b3b4 3045 rc = em_push(ctxt);
0ef753b8 3046 if (rc != X86EMUL_CONTINUE)
d1442d85 3047 goto fail;
0ef753b8 3048
9dac77fa 3049 ctxt->src.val = old_eip;
d1442d85
NA		 3050 rc = em_push(ctxt);
3051 /* If we failed, we tainted the memory, but the very least we should
3052 restore cs */
3053 if (rc != X86EMUL_CONTINUE)
3054 goto fail;
3055 return rc;
3056fail:
3057 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3058 return rc;
3059
0ef753b8
AK		 3060}
3061
40ece7c7
AK		 3062static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3063{
40ece7c7 3064 int rc;
234f3ce4 3065 unsigned long eip;
40ece7c7 3066
234f3ce4
NA		 3067 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3068 if (rc != X86EMUL_CONTINUE)
3069 return rc;
3070 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3071 if (rc != X86EMUL_CONTINUE)
3072 return rc;
5ad105e5 3073 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3074 return X86EMUL_CONTINUE;
3075}
3076
e4f973ae
TY		 3077static int em_xchg(struct x86_emulate_ctxt *ctxt)
3078{
e4f973ae 3079 /* Write back the register source. */
9dac77fa
AK		 3080 ctxt->src.val = ctxt->dst.val;
3081 write_register_operand(&ctxt->src);
e4f973ae
TY		 3082
3083 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3084 ctxt->dst.val = ctxt->src.orig_val;
3085 ctxt->lock_prefix = 1;
e4f973ae
TY		 3086 return X86EMUL_CONTINUE;
3087}
3088
5c82aa29
AK		 3089static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3090{
9dac77fa 3091 ctxt->dst.val = ctxt->src2.val;
4d758349 3092 return fastop(ctxt, em_imul);
5c82aa29
AK		 3093}
3094
61429142
AK		 3095static int em_cwd(struct x86_emulate_ctxt *ctxt)
3096{
9dac77fa
AK		 3097 ctxt->dst.type = OP_REG;
3098 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3099 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3100 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3101
3102 return X86EMUL_CONTINUE;
3103}
3104
48bb5d3c
AK		 3105static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3106{
48bb5d3c
AK		 3107 u64 tsc = 0;
3108
717746e3 3109 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3110 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3111 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3112 return X86EMUL_CONTINUE;
3113}
3114
222d21aa
AK		 3115static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3116{
3117 u64 pmc;
3118
dd856efa 3119 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3120 return emulate_gp(ctxt, 0);
dd856efa
AK		 3121 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3122 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3123 return X86EMUL_CONTINUE;
3124}
3125
b9eac5f4
AK		 3126static int em_mov(struct x86_emulate_ctxt *ctxt)
3127{
54cfdb3e 3128 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3129 return X86EMUL_CONTINUE;
3130}
3131
84cffe49
BP		 3132#define FFL(x) bit(X86_FEATURE_##x)
3133
3134static int em_movbe(struct x86_emulate_ctxt *ctxt)
3135{
3136 u32 ebx, ecx, edx, eax = 1;
3137 u16 tmp;
3138
3139 /*
3140 * Check MOVBE is set in the guest-visible CPUID leaf.
3141 */
3142 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3143 if (!(ecx & FFL(MOVBE)))
3144 return emulate_ud(ctxt);
3145
3146 switch (ctxt->op_bytes) {
3147 case 2:
3148 /*
3149 * From MOVBE definition: "...When the operand size is 16 bits,
3150 * the upper word of the destination register remains unchanged
3151 * ..."
3152 *
3153 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3154 * rules so we have to do the operation almost per hand.
3155 */
3156 tmp = (u16)ctxt->src.val;
3157 ctxt->dst.val &= ~0xffffUL;
3158 ctxt->dst.val |= (unsigned long)swab16(tmp);
3159 break;
3160 case 4:
3161 ctxt->dst.val = swab32((u32)ctxt->src.val);
3162 break;
3163 case 8:
3164 ctxt->dst.val = swab64(ctxt->src.val);
3165 break;
3166 default:
592f0858 3167 BUG();
84cffe49
BP		 3168 }
3169 return X86EMUL_CONTINUE;
3170}
3171
bc00f8d2
TY		 3172static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3173{
3174 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3175 return emulate_gp(ctxt, 0);
3176
3177 /* Disable writeback. */
3178 ctxt->dst.type = OP_NONE;
3179 return X86EMUL_CONTINUE;
3180}
3181
3182static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3183{
3184 unsigned long val;
3185
3186 if (ctxt->mode == X86EMUL_MODE_PROT64)
3187 val = ctxt->src.val & ~0ULL;
3188 else
3189 val = ctxt->src.val & ~0U;
3190
3191 /* #UD condition is already handled. */
3192 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3193 return emulate_gp(ctxt, 0);
3194
3195 /* Disable writeback. */
3196 ctxt->dst.type = OP_NONE;
3197 return X86EMUL_CONTINUE;
3198}
3199
e1e210b0
TY		 3200static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3201{
3202 u64 msr_data;
3203
dd856efa
AK		 3204 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3205 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3206 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3207 return emulate_gp(ctxt, 0);
3208
3209 return X86EMUL_CONTINUE;
3210}
3211
3212static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3213{
3214 u64 msr_data;
3215
dd856efa 3216 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3217 return emulate_gp(ctxt, 0);
3218
dd856efa
AK		 3219 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3220 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3221 return X86EMUL_CONTINUE;
3222}
3223
1bd5f469
TY		 3224static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3225{
9dac77fa 3226 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3227 return emulate_ud(ctxt);
3228
9dac77fa 3229 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3230 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3231 ctxt->dst.bytes = 2;
1bd5f469
TY		 3232 return X86EMUL_CONTINUE;
3233}
3234
3235static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3236{
9dac77fa 3237 u16 sel = ctxt->src.val;
1bd5f469 3238
9dac77fa 3239 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3240 return emulate_ud(ctxt);
3241
9dac77fa 3242 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3243 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3244
3245 /* Disable writeback. */
9dac77fa
AK		 3246 ctxt->dst.type = OP_NONE;
3247 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3248}
3249
a14e579f
AK		 3250static int em_lldt(struct x86_emulate_ctxt *ctxt)
3251{
3252 u16 sel = ctxt->src.val;
3253
3254 /* Disable writeback. */
3255 ctxt->dst.type = OP_NONE;
3256 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3257}
3258
80890006
AK		 3259static int em_ltr(struct x86_emulate_ctxt *ctxt)
3260{
3261 u16 sel = ctxt->src.val;
3262
3263 /* Disable writeback. */
3264 ctxt->dst.type = OP_NONE;
3265 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3266}
3267
38503911
AK		 3268static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3269{
9fa088f4
AK		 3270 int rc;
3271 ulong linear;
3272
9dac77fa 3273 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3274 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3275 ctxt->ops->invlpg(ctxt, linear);
38503911 3276 /* Disable writeback. */
9dac77fa 3277 ctxt->dst.type = OP_NONE;
38503911
AK		 3278 return X86EMUL_CONTINUE;
3279}
3280
2d04a05b
AK		 3281static int em_clts(struct x86_emulate_ctxt *ctxt)
3282{
3283 ulong cr0;
3284
3285 cr0 = ctxt->ops->get_cr(ctxt, 0);
3286 cr0 &= ~X86_CR0_TS;
3287 ctxt->ops->set_cr(ctxt, 0, cr0);
3288 return X86EMUL_CONTINUE;
3289}
3290
26d05cc7
AK		 3291static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3292{
0f54a321 3293 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3294
26d05cc7
AK		 3295 if (rc != X86EMUL_CONTINUE)
3296 return rc;
3297
3298 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3299 ctxt->_eip = ctxt->eip;
26d05cc7 3300 /* Disable writeback. */
9dac77fa 3301 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3302 return X86EMUL_CONTINUE;
3303}
3304
96051572
AK		 3305static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3306 void (*get)(struct x86_emulate_ctxt *ctxt,
3307 struct desc_ptr *ptr))
3308{
3309 struct desc_ptr desc_ptr;
3310
3311 if (ctxt->mode == X86EMUL_MODE_PROT64)
3312 ctxt->op_bytes = 8;
3313 get(ctxt, &desc_ptr);
3314 if (ctxt->op_bytes == 2) {
3315 ctxt->op_bytes = 4;
3316 desc_ptr.address &= 0x00ffffff;
3317 }
3318 /* Disable writeback. */
3319 ctxt->dst.type = OP_NONE;
3320 return segmented_write(ctxt, ctxt->dst.addr.mem,
3321 &desc_ptr, 2 + ctxt->op_bytes);
3322}
3323
3324static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3325{
3326 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3327}
3328
3329static int em_sidt(struct x86_emulate_ctxt *ctxt)
3330{
3331 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3332}
3333
5b7f6a1e 3334static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3335{
26d05cc7
AK		 3336 struct desc_ptr desc_ptr;
3337 int rc;
3338
510425ff
AK		 3339 if (ctxt->mode == X86EMUL_MODE_PROT64)
3340 ctxt->op_bytes = 8;
9dac77fa 3341 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3342 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3343 ctxt->op_bytes);
26d05cc7
AK		 3344 if (rc != X86EMUL_CONTINUE)
3345 return rc;
9a9abf6b
NA		 3346 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3347 is_noncanonical_address(desc_ptr.address))
3348 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3349 if (lgdt)
3350 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3351 else
3352 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3353 /* Disable writeback. */
9dac77fa 3354 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3355 return X86EMUL_CONTINUE;
3356}
3357
5b7f6a1e
NA		 3358static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3359{
3360 return em_lgdt_lidt(ctxt, true);
3361}
3362
5ef39c71 3363static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3364{
26d05cc7
AK		 3365 int rc;
3366
5ef39c71
AK		 3367 rc = ctxt->ops->fix_hypercall(ctxt);
3368
26d05cc7 3369 /* Disable writeback. */
9dac77fa 3370 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3371 return rc;
3372}
3373
3374static int em_lidt(struct x86_emulate_ctxt *ctxt)
3375{
5b7f6a1e 3376 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3377}
3378
3379static int em_smsw(struct x86_emulate_ctxt *ctxt)
3380{
32e94d06
NA		 3381 if (ctxt->dst.type == OP_MEM)
3382 ctxt->dst.bytes = 2;
9dac77fa 3383 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3384 return X86EMUL_CONTINUE;
3385}
3386
3387static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3388{
26d05cc7 3389 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3390 | (ctxt->src.val & 0x0f));
3391 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3392 return X86EMUL_CONTINUE;
3393}
3394
d06e03ad
TY		 3395static int em_loop(struct x86_emulate_ctxt *ctxt)
3396{
234f3ce4
NA		 3397 int rc = X86EMUL_CONTINUE;
3398
01485a22 3399 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3400 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3401 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3402 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3403
234f3ce4 3404 return rc;
d06e03ad
TY		 3405}
3406
3407static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3408{
234f3ce4
NA		 3409 int rc = X86EMUL_CONTINUE;
3410
dd856efa 3411 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3412 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3413
234f3ce4 3414 return rc;
d06e03ad
TY		 3415}
3416
d7841a4b
TY		 3417static int em_in(struct x86_emulate_ctxt *ctxt)
3418{
3419 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3420 &ctxt->dst.val))
3421 return X86EMUL_IO_NEEDED;
3422
3423 return X86EMUL_CONTINUE;
3424}
3425
3426static int em_out(struct x86_emulate_ctxt *ctxt)
3427{
3428 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3429 &ctxt->src.val, 1);
3430 /* Disable writeback. */
3431 ctxt->dst.type = OP_NONE;
3432 return X86EMUL_CONTINUE;
3433}
3434
f411e6cd
TY		 3435static int em_cli(struct x86_emulate_ctxt *ctxt)
3436{
3437 if (emulator_bad_iopl(ctxt))
3438 return emulate_gp(ctxt, 0);
3439
3440 ctxt->eflags &= ~X86_EFLAGS_IF;
3441 return X86EMUL_CONTINUE;
3442}
3443
3444static int em_sti(struct x86_emulate_ctxt *ctxt)
3445{
3446 if (emulator_bad_iopl(ctxt))
3447 return emulate_gp(ctxt, 0);
3448
3449 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3450 ctxt->eflags |= X86_EFLAGS_IF;
3451 return X86EMUL_CONTINUE;
3452}
3453
6d6eede4
AK		 3454static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3455{
3456 u32 eax, ebx, ecx, edx;
3457
dd856efa
AK		 3458 eax = reg_read(ctxt, VCPU_REGS_RAX);
3459 ecx = reg_read(ctxt, VCPU_REGS_RCX);
6d6eede4 3460 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
dd856efa
AK		 3461 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3462 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3463 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3464 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3465 return X86EMUL_CONTINUE;
3466}
3467
98f73630
PB		 3468static int em_sahf(struct x86_emulate_ctxt *ctxt)
3469{
3470 u32 flags;
3471
3472 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
3473 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3474
3475 ctxt->eflags &= ~0xffUL;
3476 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3477 return X86EMUL_CONTINUE;
3478}
3479
2dd7caa0
AK		 3480static int em_lahf(struct x86_emulate_ctxt *ctxt)
3481{
dd856efa
AK		 3482 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3483 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3484 return X86EMUL_CONTINUE;
3485}
3486
9299836e
AK		 3487static int em_bswap(struct x86_emulate_ctxt *ctxt)
3488{
3489 switch (ctxt->op_bytes) {
3490#ifdef CONFIG_X86_64
3491 case 8:
3492 asm("bswap %0" : "+r"(ctxt->dst.val));
3493 break;
3494#endif
3495 default:
3496 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3497 break;
3498 }
3499 return X86EMUL_CONTINUE;
3500}
3501
13e457e0
NA		 3502static int em_clflush(struct x86_emulate_ctxt *ctxt)
3503{
3504 /* emulating clflush regardless of cpuid */
3505 return X86EMUL_CONTINUE;
3506}
3507
cfec82cb
JR		 3508static bool valid_cr(int nr)
3509{
3510 switch (nr) {
3511 case 0:
3512 case 2 ... 4:
3513 case 8:
3514 return true;
3515 default:
3516 return false;
3517 }
3518}
3519
3520static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3521{
9dac77fa 3522 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 3523 return emulate_ud(ctxt);
3524
3525 return X86EMUL_CONTINUE;
3526}
3527
3528static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3529{
9dac77fa
AK		 3530 u64 new_val = ctxt->src.val64;
3531 int cr = ctxt->modrm_reg;
c2ad2bb3 3532 u64 efer = 0;
cfec82cb
JR		 3533
3534 static u64 cr_reserved_bits[] = {
3535 0xffffffff00000000ULL,
3536 0, 0, 0, /* CR3 checked later */
3537 CR4_RESERVED_BITS,
3538 0, 0, 0,
3539 CR8_RESERVED_BITS,
3540 };
3541
3542 if (!valid_cr(cr))
3543 return emulate_ud(ctxt);
3544
3545 if (new_val & cr_reserved_bits[cr])
3546 return emulate_gp(ctxt, 0);
3547
3548 switch (cr) {
3549 case 0: {
c2ad2bb3 3550 u64 cr4;
cfec82cb
JR		 3551 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3552 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3553 return emulate_gp(ctxt, 0);
3554
717746e3
AK		 3555 cr4 = ctxt->ops->get_cr(ctxt, 4);
3556 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3557
3558 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3559 !(cr4 & X86_CR4_PAE))
3560 return emulate_gp(ctxt, 0);
3561
3562 break;
3563 }
3564 case 3: {
3565 u64 rsvd = 0;
3566
c2ad2bb3
AK		 3567 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3568 if (efer & EFER_LMA)
9d88fca7 3569 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 3570
3571 if (new_val & rsvd)
3572 return emulate_gp(ctxt, 0);
3573
3574 break;
3575 }
3576 case 4: {
717746e3 3577 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 3578
3579 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3580 return emulate_gp(ctxt, 0);
3581
3582 break;
3583 }
3584 }
3585
3586 return X86EMUL_CONTINUE;
3587}
3588
3b88e41a
JR		 3589static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3590{
3591 unsigned long dr7;
3592
717746e3 3593 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 3594
3595 /* Check if DR7.Global_Enable is set */
3596 return dr7 & (1 << 13);
3597}
3598
3599static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3600{
9dac77fa 3601 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3602 u64 cr4;
3603
3604 if (dr > 7)
3605 return emulate_ud(ctxt);
3606
717746e3 3607 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 3608 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3609 return emulate_ud(ctxt);
3610
6d2a0526
NA		 3611 if (check_dr7_gd(ctxt)) {
3612 ulong dr6;
3613
3614 ctxt->ops->get_dr(ctxt, 6, &dr6);
3615 dr6 &= ~15;
3616 dr6 |= DR6_BD | DR6_RTM;
3617 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 3618 return emulate_db(ctxt);
6d2a0526 3619 }
3b88e41a
JR		 3620
3621 return X86EMUL_CONTINUE;
3622}
3623
3624static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3625{
9dac77fa
AK		 3626 u64 new_val = ctxt->src.val64;
3627 int dr = ctxt->modrm_reg;
3b88e41a
JR		 3628
3629 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3630 return emulate_gp(ctxt, 0);
3631
3632 return check_dr_read(ctxt);
3633}
3634
01de8b09
JR		 3635static int check_svme(struct x86_emulate_ctxt *ctxt)
3636{
3637 u64 efer;
3638
717746e3 3639 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 3640
3641 if (!(efer & EFER_SVME))
3642 return emulate_ud(ctxt);
3643
3644 return X86EMUL_CONTINUE;
3645}
3646
3647static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3648{
dd856efa 3649 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 3650
3651 /* Valid physical address? */
d4224449 3652 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 3653 return emulate_gp(ctxt, 0);
3654
3655 return check_svme(ctxt);
3656}
3657
d7eb8203
JR		 3658static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3659{
717746e3 3660 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 3661
717746e3 3662 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 3663 return emulate_ud(ctxt);
3664
3665 return X86EMUL_CONTINUE;
3666}
3667
8061252e
JR		 3668static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3669{
717746e3 3670 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 3671 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 3672
717746e3 3673 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 3674 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 3675 return emulate_gp(ctxt, 0);
3676
3677 return X86EMUL_CONTINUE;
3678}
3679
f6511935
JR		 3680static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3681{
9dac77fa
AK		 3682 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3683 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 3684 return emulate_gp(ctxt, 0);
3685
3686 return X86EMUL_CONTINUE;
3687}
3688
3689static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3690{
9dac77fa
AK		 3691 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3692 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 3693 return emulate_gp(ctxt, 0);
3694
3695 return X86EMUL_CONTINUE;
3696}
3697
73fba5f4 3698#define D(_y) { .flags = (_y) }
d40a6898
PB		 3699#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3700#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3701 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 3702#define N D(NotImpl)
01de8b09 3703#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 3704#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3705#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 3706#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
045a282c 3707#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 3708#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 3709#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 3710#define II(_f, _e, _i) \
d40a6898 3711 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 3712#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 3713 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3714 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 3715#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 3716
8d8f4e9f 3717#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 3718#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 3719#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 3720#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 3721#define I2bvIP(_f, _e, _i, _p) \
3722 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 3723
fb864fbc
AK		 3724#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3725 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3726 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3727
0f54a321
NA		 3728static const struct opcode group7_rm0[] = {
3729 N,
3730 I(SrcNone | Priv | EmulateOnUD, em_vmcall),
3731 N, N, N, N, N, N,
3732};
3733
fd0a0d82 3734static const struct opcode group7_rm1[] = {
1c2545be
TY		 3735 DI(SrcNone | Priv, monitor),
3736 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 3737 N, N, N, N, N, N,
3738};
3739
fd0a0d82 3740static const struct opcode group7_rm3[] = {
1c2545be 3741 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b51e974f 3742 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall),
1c2545be
TY		 3743 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3744 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3745 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3746 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3747 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3748 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 3749};
6230f7fc 3750
fd0a0d82 3751static const struct opcode group7_rm7[] = {
d7eb8203 3752 N,
1c2545be 3753 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 3754 N, N, N, N, N, N,
3755};
d67fc27a 3756
fd0a0d82 3757static const struct opcode group1[] = {
fb864fbc
AK		 3758 F(Lock, em_add),
3759 F(Lock | PageTable, em_or),
3760 F(Lock, em_adc),
3761 F(Lock, em_sbb),
3762 F(Lock | PageTable, em_and),
3763 F(Lock, em_sub),
3764 F(Lock, em_xor),
3765 F(NoWrite, em_cmp),
73fba5f4
AK		 3766};
3767
fd0a0d82 3768static const struct opcode group1A[] = {
ab708099 3769 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 3770};
3771
007a3b54
AK		 3772static const struct opcode group2[] = {
3773 F(DstMem | ModRM, em_rol),
3774 F(DstMem | ModRM, em_ror),
3775 F(DstMem | ModRM, em_rcl),
3776 F(DstMem | ModRM, em_rcr),
3777 F(DstMem | ModRM, em_shl),
3778 F(DstMem | ModRM, em_shr),
3779 F(DstMem | ModRM, em_shl),
3780 F(DstMem | ModRM, em_sar),
3781};
3782
fd0a0d82 3783static const struct opcode group3[] = {
fb864fbc
AK		 3784 F(DstMem | SrcImm | NoWrite, em_test),
3785 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 3786 F(DstMem | SrcNone | Lock, em_not),
3787 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 3788 F(DstXacc | Src2Mem, em_mul_ex),
3789 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 3790 F(DstXacc | Src2Mem, em_div_ex),
3791 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 3792};
3793
fd0a0d82 3794static const struct opcode group4[] = {
95413dc4
AK		 3795 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3796 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 3797 N, N, N, N, N, N,
3798};
3799
fd0a0d82 3800static const struct opcode group5[] = {
95413dc4
AK		 3801 F(DstMem | SrcNone | Lock, em_inc),
3802 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 3803 I(SrcMem | NearBranch, em_call_near_abs),
1c2545be 3804 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
58b7075d 3805 I(SrcMem | NearBranch, em_jmp_abs),
f7784046
NA		 3806 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3807 I(SrcMem | Stack, em_push), D(Undefined),
73fba5f4
AK		 3808};
3809
fd0a0d82 3810static const struct opcode group6[] = {
1c2545be
TY		 3811 DI(Prot, sldt),
3812 DI(Prot, str),
a14e579f 3813 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 3814 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 3815 N, N, N, N,
3816};
3817
fd0a0d82 3818static const struct group_dual group7 = { {
606b1c3e
NA		 3819 II(Mov | DstMem, em_sgdt, sgdt),
3820 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 3821 II(SrcMem | Priv, em_lgdt, lgdt),
3822 II(SrcMem | Priv, em_lidt, lidt),
3823 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3824 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3825 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3826}, {
0f54a321 3827 EXT(0, group7_rm0),
5ef39c71 3828 EXT(0, group7_rm1),
01de8b09 3829 N, EXT(0, group7_rm3),
1c2545be
TY		 3830 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3831 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3832 EXT(0, group7_rm7),
73fba5f4
AK		 3833} };
3834
fd0a0d82 3835static const struct opcode group8[] = {
73fba5f4 3836 N, N, N, N,
11c363ba
AK		 3837 F(DstMem | SrcImmByte | NoWrite, em_bt),
3838 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3839 F(DstMem | SrcImmByte | Lock, em_btr),
3840 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 3841};
3842
fd0a0d82 3843static const struct group_dual group9 = { {
1c2545be 3844 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 3845}, {
3846 N, N, N, N, N, N, N, N,
3847} };
3848
fd0a0d82 3849static const struct opcode group11[] = {
1c2545be 3850 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 3851 X7(D(Undefined)),
a4d4a7c1
AK		 3852};
3853
13e457e0 3854static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 3855 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 3856};
3857
3858static const struct group_dual group15 = { {
3859 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3860}, {
3861 N, N, N, N, N, N, N, N,
3862} };
3863
fd0a0d82 3864static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 3865 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 3866};
3867
39f062ff
NA		 3868static const struct instr_dual instr_dual_0f_2b = {
3869 I(0, em_mov), N
3870};
3871
d5b77069 3872static const struct gprefix pfx_0f_2b = {
39f062ff 3873 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 3874};
3875
27ce8258 3876static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 3877 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 3878};
3879
0a37027e
AW		 3880static const struct gprefix pfx_0f_e7 = {
3881 N, I(Sse, em_mov), N, N,
3882};
3883
045a282c 3884static const struct escape escape_d9 = { {
16bebefe 3885 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 3886}, {
3887 /* 0xC0 - 0xC7 */
3888 N, N, N, N, N, N, N, N,
3889 /* 0xC8 - 0xCF */
3890 N, N, N, N, N, N, N, N,
3891 /* 0xD0 - 0xC7 */
3892 N, N, N, N, N, N, N, N,
3893 /* 0xD8 - 0xDF */
3894 N, N, N, N, N, N, N, N,
3895 /* 0xE0 - 0xE7 */
3896 N, N, N, N, N, N, N, N,
3897 /* 0xE8 - 0xEF */
3898 N, N, N, N, N, N, N, N,
3899 /* 0xF0 - 0xF7 */
3900 N, N, N, N, N, N, N, N,
3901 /* 0xF8 - 0xFF */
3902 N, N, N, N, N, N, N, N,
3903} };
3904
3905static const struct escape escape_db = { {
3906 N, N, N, N, N, N, N, N,
3907}, {
3908 /* 0xC0 - 0xC7 */
3909 N, N, N, N, N, N, N, N,
3910 /* 0xC8 - 0xCF */
3911 N, N, N, N, N, N, N, N,
3912 /* 0xD0 - 0xC7 */
3913 N, N, N, N, N, N, N, N,
3914 /* 0xD8 - 0xDF */
3915 N, N, N, N, N, N, N, N,
3916 /* 0xE0 - 0xE7 */
3917 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3918 /* 0xE8 - 0xEF */
3919 N, N, N, N, N, N, N, N,
3920 /* 0xF0 - 0xF7 */
3921 N, N, N, N, N, N, N, N,
3922 /* 0xF8 - 0xFF */
3923 N, N, N, N, N, N, N, N,
3924} };
3925
3926static const struct escape escape_dd = { {
16bebefe 3927 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 3928}, {
3929 /* 0xC0 - 0xC7 */
3930 N, N, N, N, N, N, N, N,
3931 /* 0xC8 - 0xCF */
3932 N, N, N, N, N, N, N, N,
3933 /* 0xD0 - 0xC7 */
3934 N, N, N, N, N, N, N, N,
3935 /* 0xD8 - 0xDF */
3936 N, N, N, N, N, N, N, N,
3937 /* 0xE0 - 0xE7 */
3938 N, N, N, N, N, N, N, N,
3939 /* 0xE8 - 0xEF */
3940 N, N, N, N, N, N, N, N,
3941 /* 0xF0 - 0xF7 */
3942 N, N, N, N, N, N, N, N,
3943 /* 0xF8 - 0xFF */
3944 N, N, N, N, N, N, N, N,
3945} };
3946
39f062ff
NA		 3947static const struct instr_dual instr_dual_0f_c3 = {
3948 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
3949};
3950
fd0a0d82 3951static const struct opcode opcode_table[256] = {
73fba5f4 3952 /* 0x00 - 0x07 */
fb864fbc 3953 F6ALU(Lock, em_add),
1cd196ea
AK		 3954 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3955 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 3956 /* 0x08 - 0x0F */
fb864fbc 3957 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 3958 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3959 N,
73fba5f4 3960 /* 0x10 - 0x17 */
fb864fbc 3961 F6ALU(Lock, em_adc),
1cd196ea
AK		 3962 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3963 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 3964 /* 0x18 - 0x1F */
fb864fbc 3965 F6ALU(Lock, em_sbb),
1cd196ea
AK		 3966 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3967 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 3968 /* 0x20 - 0x27 */
fb864fbc 3969 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 3970 /* 0x28 - 0x2F */
fb864fbc 3971 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3972 /* 0x30 - 0x37 */
fb864fbc 3973 F6ALU(Lock, em_xor), N, N,
73fba5f4 3974 /* 0x38 - 0x3F */
fb864fbc 3975 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 3976 /* 0x40 - 0x4F */
95413dc4 3977 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 3978 /* 0x50 - 0x57 */
63540382 3979 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3980 /* 0x58 - 0x5F */
c54fe504 3981 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3982 /* 0x60 - 0x67 */
b96a7fad
TY		 3983 I(ImplicitOps | Stack | No64, em_pusha),
3984 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3985 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3986 N, N, N, N,
3987 /* 0x68 - 0x6F */
d46164db
AK		 3988 I(SrcImm | Mov | Stack, em_push),
3989 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3990 I(SrcImmByte | Mov | Stack, em_push),
3991 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 3992 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 3993 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 3994 /* 0x70 - 0x7F */
58b7075d 3995 X16(D(SrcImmByte | NearBranch)),
73fba5f4 3996 /* 0x80 - 0x87 */
1c2545be
TY		 3997 G(ByteOp | DstMem | SrcImm, group1),
3998 G(DstMem | SrcImm, group1),
3999 G(ByteOp | DstMem | SrcImm | No64, group1),
4000 G(DstMem | SrcImmByte, group1),
fb864fbc 4001 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4002 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4003 /* 0x88 - 0x8F */
d5ae7ce8 4004 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4005 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4006 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4007 D(ModRM | SrcMem | NoAccess | DstReg),
4008 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4009 G(0, group1A),
73fba5f4 4010 /* 0x90 - 0x97 */
bf608f88 4011 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4012 /* 0x98 - 0x9F */
61429142 4013 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4014 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4015 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4016 II(ImplicitOps | Stack, em_popf, popf),
4017 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4018 /* 0xA0 - 0xA7 */
b9eac5f4 4019 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4020 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
b9eac5f4 4021 I2bv(SrcSI | DstDI | Mov | String, em_mov),
5aca3722 4022 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4023 /* 0xA8 - 0xAF */
fb864fbc 4024 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4025 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4026 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4027 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4028 /* 0xB0 - 0xB7 */
b9eac5f4 4029 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4030 /* 0xB8 - 0xBF */
5e2c6883 4031 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4032 /* 0xC0 - 0xC7 */
007a3b54 4033 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4034 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4035 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4036 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4037 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4038 G(ByteOp, group11), G(0, group11),
73fba5f4 4039 /* 0xC8 - 0xCF */
612e89f0 4040 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3261107e
BR		 4041 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
4042 I(ImplicitOps | Stack, em_ret_far),
3c6e276f 4043 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4044 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4045 /* 0xD0 - 0xD7 */
007a3b54
AK		 4046 G(Src2One | ByteOp, group2), G(Src2One, group2),
4047 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4048 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4049 I(DstAcc | SrcImmUByte | No64, em_aad),
4050 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4051 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4052 /* 0xD8 - 0xDF */
045a282c 4053 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4054 /* 0xE0 - 0xE7 */
58b7075d
NA		 4055 X3(I(SrcImmByte | NearBranch, em_loop)),
4056 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4057 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4058 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4059 /* 0xE8 - 0xEF */
58b7075d
NA		 4060 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4061 I(SrcImmFAddr | No64, em_jmp_far),
4062 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4063 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4064 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4065 /* 0xF0 - 0xF7 */
bf608f88 4066 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4067 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4068 G(ByteOp, group3), G(0, group3),
73fba5f4 4069 /* 0xF8 - 0xFF */
f411e6cd
TY		 4070 D(ImplicitOps), D(ImplicitOps),
4071 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4072 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4073};
4074
fd0a0d82 4075static const struct opcode twobyte_table[256] = {
73fba5f4 4076 /* 0x00 - 0x0F */
dee6bb70 4077 G(0, group6), GD(0, &group7), N, N,
b51e974f 4078 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4079 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4080 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4081 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4082 /* 0x10 - 0x1F */
103f98ea 4083 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4084 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4085 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4086 /* 0x20 - 0x2F */
9b88ae99
NA		 4087 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4088 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4089 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4090 check_cr_write),
4091 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4092 check_dr_write),
73fba5f4 4093 N, N, N, N,
27ce8258
IM		 4094 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4095 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4096 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4097 N, N, N, N,
73fba5f4 4098 /* 0x30 - 0x3F */
e1e210b0 4099 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4100 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4101 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4102 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4103 I(ImplicitOps | EmulateOnUD, em_sysenter),
4104 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4105 N, N,
73fba5f4
AK		 4106 N, N, N, N, N, N, N, N,
4107 /* 0x40 - 0x4F */
140bad89 4108 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4109 /* 0x50 - 0x5F */
4110 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4111 /* 0x60 - 0x6F */
aa97bb48
AK		 4112 N, N, N, N,
4113 N, N, N, N,
4114 N, N, N, N,
4115 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4116 /* 0x70 - 0x7F */
aa97bb48
AK		 4117 N, N, N, N,
4118 N, N, N, N,
4119 N, N, N, N,
4120 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4121 /* 0x80 - 0x8F */
58b7075d 4122 X16(D(SrcImm | NearBranch)),
73fba5f4 4123 /* 0x90 - 0x9F */
ee45b58e 4124 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4125 /* 0xA0 - 0xA7 */
1cd196ea 4126 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4127 II(ImplicitOps, em_cpuid, cpuid),
4128 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4129 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4130 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4131 /* 0xA8 - 0xAF */
1cd196ea 4132 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
d5ae7ce8 4133 DI(ImplicitOps, rsm),
11c363ba 4134 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4135 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4136 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4137 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4138 /* 0xB0 - 0xB7 */
e940b5c2 4139 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
d4b4325f 4140 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4141 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4142 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4143 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4144 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4145 /* 0xB8 - 0xBF */
4146 N, N,
ce7faab2 4147 G(BitOp, group8),
11c363ba
AK		 4148 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4149 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
2adb5ad9 4150 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4151 /* 0xC0 - 0xC7 */
e47a5f5f 4152 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4153 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4154 N, N, N, GD(0, &group9),
9299836e
AK		 4155 /* 0xC8 - 0xCF */
4156 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4157 /* 0xD0 - 0xDF */
4158 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4159 /* 0xE0 - 0xEF */
0a37027e
AW		 4160 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4161 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4162 /* 0xF0 - 0xFF */
4163 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4164};
4165
39f062ff
NA		 4166static const struct instr_dual instr_dual_0f_38_f0 = {
4167 I(DstReg | SrcMem | Mov, em_movbe), N
4168};
4169
4170static const struct instr_dual instr_dual_0f_38_f1 = {
4171 I(DstMem | SrcReg | Mov, em_movbe), N
4172};
4173
0bc5eedb 4174static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4175 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4176};
4177
4178static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4179 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4180};
4181
4182/*
4183 * Insns below are selected by the prefix which indexed by the third opcode
4184 * byte.
4185 */
4186static const struct opcode opcode_map_0f_38[256] = {
4187 /* 0x00 - 0x7f */
4188 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4189 /* 0x80 - 0xef */
4190 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4191 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4192 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4193 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4194 /* 0xf2 - 0xff */
4195 N, N, X4(N), X8(N)
0bc5eedb
BP		 4196};
4197
73fba5f4
AK		 4198#undef D
4199#undef N
4200#undef G
4201#undef GD
4202#undef I
aa97bb48 4203#undef GP
01de8b09 4204#undef EXT
73fba5f4 4205
8d8f4e9f 4206#undef D2bv
f6511935 4207#undef D2bvIP
8d8f4e9f 4208#undef I2bv
d7841a4b 4209#undef I2bvIP
d67fc27a 4210#undef I6ALU
8d8f4e9f 4211
9dac77fa 4212static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4213{
4214 unsigned size;
4215
9dac77fa 4216 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4217 if (size == 8)
4218 size = 4;
4219 return size;
4220}
4221
4222static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4223 unsigned size, bool sign_extension)
4224{
39f21ee5
AK		 4225 int rc = X86EMUL_CONTINUE;
4226
4227 op->type = OP_IMM;
4228 op->bytes = size;
9dac77fa 4229 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4230 /* NB. Immediates are sign-extended as necessary. */
4231 switch (op->bytes) {
4232 case 1:
e85a1085 4233 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4234 break;
4235 case 2:
e85a1085 4236 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4237 break;
4238 case 4:
e85a1085 4239 op->val = insn_fetch(s32, ctxt);
39f21ee5 4240 break;
5e2c6883
NA		 4241 case 8:
4242 op->val = insn_fetch(s64, ctxt);
4243 break;
39f21ee5
AK		 4244 }
4245 if (!sign_extension) {
4246 switch (op->bytes) {
4247 case 1:
4248 op->val &= 0xff;
4249 break;
4250 case 2:
4251 op->val &= 0xffff;
4252 break;
4253 case 4:
4254 op->val &= 0xffffffff;
4255 break;
4256 }
4257 }
4258done:
4259 return rc;
4260}
4261
a9945549
AK		 4262static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4263 unsigned d)
4264{
4265 int rc = X86EMUL_CONTINUE;
4266
4267 switch (d) {
4268 case OpReg:
2adb5ad9 4269 decode_register_operand(ctxt, op);
a9945549
AK		 4270 break;
4271 case OpImmUByte:
608aabe3 4272 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4273 break;
4274 case OpMem:
41ddf978 4275 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4276 mem_common:
4277 *op = ctxt->memop;
4278 ctxt->memopp = op;
96888977 4279 if (ctxt->d & BitOp)
a9945549
AK		 4280 fetch_bit_operand(ctxt);
4281 op->orig_val = op->val;
4282 break;
41ddf978 4283 case OpMem64:
aaa05f24 4284 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4285 goto mem_common;
a9945549
AK		 4286 case OpAcc:
4287 op->type = OP_REG;
4288 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4289 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4290 fetch_register_operand(op);
4291 op->orig_val = op->val;
4292 break;
820207c8
AK		 4293 case OpAccLo:
4294 op->type = OP_REG;
4295 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4296 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4297 fetch_register_operand(op);
4298 op->orig_val = op->val;
4299 break;
4300 case OpAccHi:
4301 if (ctxt->d & ByteOp) {
4302 op->type = OP_NONE;
4303 break;
4304 }
4305 op->type = OP_REG;
4306 op->bytes = ctxt->op_bytes;
4307 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4308 fetch_register_operand(op);
4309 op->orig_val = op->val;
4310 break;
a9945549
AK		 4311 case OpDI:
4312 op->type = OP_MEM;
4313 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4314 op->addr.mem.ea =
01485a22 4315 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4316 op->addr.mem.seg = VCPU_SREG_ES;
4317 op->val = 0;
b3356bf0 4318 op->count = 1;
a9945549
AK		 4319 break;
4320 case OpDX:
4321 op->type = OP_REG;
4322 op->bytes = 2;
dd856efa 4323 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4324 fetch_register_operand(op);
4325 break;
4dd6a57d 4326 case OpCL:
d29b9d7e 4327 op->type = OP_IMM;
4dd6a57d 4328 op->bytes = 1;
dd856efa 4329 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4330 break;
4331 case OpImmByte:
4332 rc = decode_imm(ctxt, op, 1, true);
4333 break;
4334 case OpOne:
d29b9d7e 4335 op->type = OP_IMM;
4dd6a57d
AK		 4336 op->bytes = 1;
4337 op->val = 1;
4338 break;
4339 case OpImm:
4340 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4341 break;
5e2c6883
NA		 4342 case OpImm64:
4343 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4344 break;
28867cee
AK		 4345 case OpMem8:
4346 ctxt->memop.bytes = 1;
660696d1 4347 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4348 ctxt->memop.addr.reg = decode_register(ctxt,
4349 ctxt->modrm_rm, true);
660696d1
GN		 4350 fetch_register_operand(&ctxt->memop);
4351 }
28867cee 4352 goto mem_common;
0fe59128
AK		 4353 case OpMem16:
4354 ctxt->memop.bytes = 2;
4355 goto mem_common;
4356 case OpMem32:
4357 ctxt->memop.bytes = 4;
4358 goto mem_common;
4359 case OpImmU16:
4360 rc = decode_imm(ctxt, op, 2, false);
4361 break;
4362 case OpImmU:
4363 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4364 break;
4365 case OpSI:
4366 op->type = OP_MEM;
4367 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4368 op->addr.mem.ea =
01485a22 4369 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4370 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4371 op->val = 0;
b3356bf0 4372 op->count = 1;
0fe59128 4373 break;
7fa57952
PB		 4374 case OpXLat:
4375 op->type = OP_MEM;
4376 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4377 op->addr.mem.ea =
01485a22 4378 address_mask(ctxt,
7fa57952
PB		 4379 reg_read(ctxt, VCPU_REGS_RBX) +
4380 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4381 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4382 op->val = 0;
4383 break;
0fe59128
AK		 4384 case OpImmFAddr:
4385 op->type = OP_IMM;
4386 op->addr.mem.ea = ctxt->_eip;
4387 op->bytes = ctxt->op_bytes + 2;
4388 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4389 break;
4390 case OpMemFAddr:
4391 ctxt->memop.bytes = ctxt->op_bytes + 2;
4392 goto mem_common;
c191a7a0 4393 case OpES:
d29b9d7e 4394 op->type = OP_IMM;
c191a7a0
AK		 4395 op->val = VCPU_SREG_ES;
4396 break;
4397 case OpCS:
d29b9d7e 4398 op->type = OP_IMM;
c191a7a0
AK		 4399 op->val = VCPU_SREG_CS;
4400 break;
4401 case OpSS:
d29b9d7e 4402 op->type = OP_IMM;
c191a7a0
AK		 4403 op->val = VCPU_SREG_SS;
4404 break;
4405 case OpDS:
d29b9d7e 4406 op->type = OP_IMM;
c191a7a0
AK		 4407 op->val = VCPU_SREG_DS;
4408 break;
4409 case OpFS:
d29b9d7e 4410 op->type = OP_IMM;
c191a7a0
AK		 4411 op->val = VCPU_SREG_FS;
4412 break;
4413 case OpGS:
d29b9d7e 4414 op->type = OP_IMM;
c191a7a0
AK		 4415 op->val = VCPU_SREG_GS;
4416 break;
a9945549
AK		 4417 case OpImplicit:
4418 /* Special instructions do their own operand decoding. */
4419 default:
4420 op->type = OP_NONE; /* Disable writeback. */
4421 break;
4422 }
4423
4424done:
4425 return rc;
4426}
4427
ef5d75cc 4428int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4429{
dde7e6d1
AK		 4430 int rc = X86EMUL_CONTINUE;
4431 int mode = ctxt->mode;
46561646 4432 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4433 bool op_prefix = false;
573e80fe 4434 bool has_seg_override = false;
46561646 4435 struct opcode opcode;
dde7e6d1 4436
f09ed83e
AK		 4437 ctxt->memop.type = OP_NONE;
4438 ctxt->memopp = NULL;
9dac77fa 4439 ctxt->_eip = ctxt->eip;
17052f16
PB		 4440 ctxt->fetch.ptr = ctxt->fetch.data;
4441 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4442 ctxt->opcode_len = 1;
dc25e89e 4443 if (insn_len > 0)
9dac77fa 4444 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4445 else {
9506d57d 4446 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4447 if (rc != X86EMUL_CONTINUE)
4448 return rc;
4449 }
dde7e6d1
AK		 4450
4451 switch (mode) {
4452 case X86EMUL_MODE_REAL:
4453 case X86EMUL_MODE_VM86:
4454 case X86EMUL_MODE_PROT16:
4455 def_op_bytes = def_ad_bytes = 2;
4456 break;
4457 case X86EMUL_MODE_PROT32:
4458 def_op_bytes = def_ad_bytes = 4;
4459 break;
4460#ifdef CONFIG_X86_64
4461 case X86EMUL_MODE_PROT64:
4462 def_op_bytes = 4;
4463 def_ad_bytes = 8;
4464 break;
4465#endif
4466 default:
1d2887e2 4467 return EMULATION_FAILED;
dde7e6d1
AK		 4468 }
4469
9dac77fa
AK		 4470 ctxt->op_bytes = def_op_bytes;
4471 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 4472
4473 /* Legacy prefixes. */
4474 for (;;) {
e85a1085 4475 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 4476 case 0x66: /* operand-size override */
0d7cdee8 4477 op_prefix = true;
dde7e6d1 4478 /* switch between 2/4 bytes */
9dac77fa 4479 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 4480 break;
4481 case 0x67: /* address-size override */
4482 if (mode == X86EMUL_MODE_PROT64)
4483 /* switch between 4/8 bytes */
9dac77fa 4484 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 4485 else
4486 /* switch between 2/4 bytes */
9dac77fa 4487 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 4488 break;
4489 case 0x26: /* ES override */
4490 case 0x2e: /* CS override */
4491 case 0x36: /* SS override */
4492 case 0x3e: /* DS override */
573e80fe
BD		 4493 has_seg_override = true;
4494 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 4495 break;
4496 case 0x64: /* FS override */
4497 case 0x65: /* GS override */
573e80fe
BD		 4498 has_seg_override = true;
4499 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 4500 break;
4501 case 0x40 ... 0x4f: /* REX */
4502 if (mode != X86EMUL_MODE_PROT64)
4503 goto done_prefixes;
9dac77fa 4504 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 4505 continue;
4506 case 0xf0: /* LOCK */
9dac77fa 4507 ctxt->lock_prefix = 1;
dde7e6d1
AK		 4508 break;
4509 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 4510 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 4511 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 4512 break;
4513 default:
4514 goto done_prefixes;
4515 }
4516
4517 /* Any legacy prefix after a REX prefix nullifies its effect. */
4518
9dac77fa 4519 ctxt->rex_prefix = 0;
dde7e6d1
AK		 4520 }
4521
4522done_prefixes:
4523
4524 /* REX prefix. */
9dac77fa
AK		 4525 if (ctxt->rex_prefix & 8)
4526 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 4527
4528 /* Opcode byte(s). */
9dac77fa 4529 opcode = opcode_table[ctxt->b];
d3ad6243 4530 /* Two-byte opcode? */
9dac77fa 4531 if (ctxt->b == 0x0f) {
1ce19dc1 4532 ctxt->opcode_len = 2;
e85a1085 4533 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 4534 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 4535
4536 /* 0F_38 opcode map */
4537 if (ctxt->b == 0x38) {
4538 ctxt->opcode_len = 3;
4539 ctxt->b = insn_fetch(u8, ctxt);
4540 opcode = opcode_map_0f_38[ctxt->b];
4541 }
dde7e6d1 4542 }
9dac77fa 4543 ctxt->d = opcode.flags;
dde7e6d1 4544
9f4260e7
TY		 4545 if (ctxt->d & ModRM)
4546 ctxt->modrm = insn_fetch(u8, ctxt);
4547
7fe864dc
NA		 4548 /* vex-prefix instructions are not implemented */
4549 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 4550 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 4551 ctxt->d = NotImpl;
4552 }
4553
9dac77fa
AK		 4554 while (ctxt->d & GroupMask) {
4555 switch (ctxt->d & GroupMask) {
46561646 4556 case Group:
9dac77fa 4557 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 4558 opcode = opcode.u.group[goffset];
4559 break;
4560 case GroupDual:
9dac77fa
AK		 4561 goffset = (ctxt->modrm >> 3) & 7;
4562 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 4563 opcode = opcode.u.gdual->mod3[goffset];
4564 else
4565 opcode = opcode.u.gdual->mod012[goffset];
4566 break;
4567 case RMExt:
9dac77fa 4568 goffset = ctxt->modrm & 7;
01de8b09 4569 opcode = opcode.u.group[goffset];
46561646
AK		 4570 break;
4571 case Prefix:
9dac77fa 4572 if (ctxt->rep_prefix && op_prefix)
1d2887e2 4573 return EMULATION_FAILED;
9dac77fa 4574 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 4575 switch (simd_prefix) {
4576 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4577 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4578 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4579 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4580 }
4581 break;
045a282c
GN		 4582 case Escape:
4583 if (ctxt->modrm > 0xbf)
4584 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4585 else
4586 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4587 break;
39f062ff
NA		 4588 case InstrDual:
4589 if ((ctxt->modrm >> 6) == 3)
4590 opcode = opcode.u.idual->mod3;
4591 else
4592 opcode = opcode.u.idual->mod012;
4593 break;
46561646 4594 default:
1d2887e2 4595 return EMULATION_FAILED;
0d7cdee8 4596 }
46561646 4597
b1ea50b2 4598 ctxt->d &= ~(u64)GroupMask;
9dac77fa 4599 ctxt->d |= opcode.flags;
0d7cdee8
AK		 4600 }
4601
e24186e0
PB		 4602 /* Unrecognised? */
4603 if (ctxt->d == 0)
4604 return EMULATION_FAILED;
4605
9dac77fa 4606 ctxt->execute = opcode.u.execute;
dde7e6d1 4607
3a6095a0
NA		 4608 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4609 return EMULATION_FAILED;
4610
d40a6898 4611 if (unlikely(ctxt->d &
ed9aad21
NA		 4612 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4613 No16))) {
d40a6898
PB		 4614 /*
4615 * These are copied unconditionally here, and checked unconditionally
4616 * in x86_emulate_insn.
4617 */
4618 ctxt->check_perm = opcode.check_perm;
4619 ctxt->intercept = opcode.intercept;
dde7e6d1 4620
d40a6898
PB		 4621 if (ctxt->d & NotImpl)
4622 return EMULATION_FAILED;
d867162c 4623
58b7075d
NA		 4624 if (mode == X86EMUL_MODE_PROT64) {
4625 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4626 ctxt->op_bytes = 8;
4627 else if (ctxt->d & NearBranch)
4628 ctxt->op_bytes = 8;
4629 }
7f9b4b75 4630
d40a6898
PB		 4631 if (ctxt->d & Op3264) {
4632 if (mode == X86EMUL_MODE_PROT64)
4633 ctxt->op_bytes = 8;
4634 else
4635 ctxt->op_bytes = 4;
4636 }
4637
ed9aad21
NA		 4638 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4639 ctxt->op_bytes = 4;
4640
d40a6898
PB		 4641 if (ctxt->d & Sse)
4642 ctxt->op_bytes = 16;
4643 else if (ctxt->d & Mmx)
4644 ctxt->op_bytes = 8;
4645 }
1253791d 4646
dde7e6d1 4647 /* ModRM and SIB bytes. */
9dac77fa 4648 if (ctxt->d & ModRM) {
f09ed83e 4649 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 4650 if (!has_seg_override) {
4651 has_seg_override = true;
4652 ctxt->seg_override = ctxt->modrm_seg;
4653 }
9dac77fa 4654 } else if (ctxt->d & MemAbs)
f09ed83e 4655 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 4656 if (rc != X86EMUL_CONTINUE)
4657 goto done;
4658
573e80fe
BD		 4659 if (!has_seg_override)
4660 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 4661
573e80fe 4662 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 4663
dde7e6d1
AK		 4664 /*
4665 * Decode and fetch the source operand: register, memory
4666 * or immediate.
4667 */
0fe59128 4668 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 4669 if (rc != X86EMUL_CONTINUE)
4670 goto done;
4671
dde7e6d1
AK		 4672 /*
4673 * Decode and fetch the second source operand: register, memory
4674 * or immediate.
4675 */
4dd6a57d 4676 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 4677 if (rc != X86EMUL_CONTINUE)
4678 goto done;
4679
dde7e6d1 4680 /* Decode and fetch the destination operand: register or memory. */
a9945549 4681 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 4682
41061cdb 4683 if (ctxt->rip_relative)
1c1c35ae
NA		 4684 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4685 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 4686
a430c916 4687done:
1d2887e2 4688 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 4689}
4690
1cb3f3ae
XG		 4691bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4692{
4693 return ctxt->d & PageTable;
4694}
4695
3e2f65d5
GN		 4696static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4697{
3e2f65d5
GN		 4698 /* The second termination condition only applies for REPE
4699 * and REPNE. Test if the repeat string operation prefix is
4700 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4701 * corresponding termination condition according to:
4702 * - if REPE/REPZ and ZF = 0 then done
4703 * - if REPNE/REPNZ and ZF = 1 then done
4704 */
9dac77fa
AK		 4705 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4706 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4707 && (((ctxt->rep_prefix == REPE_PREFIX) &&
3e2f65d5 4708 ((ctxt->eflags & EFLG_ZF) == 0))
9dac77fa 4709 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
3e2f65d5
GN		 4710 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4711 return true;
4712
4713 return false;
4714}
4715
cbe2c9d3
AK		 4716static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4717{
4718 bool fault = false;
4719
4720 ctxt->ops->get_fpu(ctxt);
4721 asm volatile("1: fwait \n\t"
4722 "2: \n\t"
4723 ".pushsection .fixup,\"ax\" \n\t"
4724 "3: \n\t"
4725 "movb $1, %[fault] \n\t"
4726 "jmp 2b \n\t"
4727 ".popsection \n\t"
4728 _ASM_EXTABLE(1b, 3b)
38e8a2dd 4729 : [fault]"+qm"(fault));
cbe2c9d3
AK		 4730 ctxt->ops->put_fpu(ctxt);
4731
4732 if (unlikely(fault))
4733 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4734
4735 return X86EMUL_CONTINUE;
4736}
4737
4738static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4739 struct operand *op)
4740{
4741 if (op->type == OP_MM)
4742 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4743}
4744
e28bbd44
AK		 4745static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4746{
4747 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
b9fa409b
AK		 4748 if (!(ctxt->d & ByteOp))
4749 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
e28bbd44 4750 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae
AK		 4751 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4752 [fastop]"+S"(fop)
4753 : "c"(ctxt->src2.val));
e28bbd44 4754 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 4755 if (!fop) /* exception is returned in fop variable */
4756 return emulate_de(ctxt);
e28bbd44
AK		 4757 return X86EMUL_CONTINUE;
4758}
dd856efa 4759
1498507a
BD		 4760void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4761{
573e80fe
BD		 4762 memset(&ctxt->rip_relative, 0,
4763 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 4764
1498507a
BD		 4765 ctxt->io_read.pos = 0;
4766 ctxt->io_read.end = 0;
1498507a
BD		 4767 ctxt->mem_read.end = 0;
4768}
4769
7b105ca2 4770int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 4771{
0225fb50 4772 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 4773 int rc = X86EMUL_CONTINUE;
9dac77fa 4774 int saved_dst_type = ctxt->dst.type;
8b4caf66 4775
9dac77fa 4776 ctxt->mem_read.pos = 0;
310b5d30 4777
e24186e0
PB		 4778 /* LOCK prefix is allowed only with some instructions */
4779 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 4780 rc = emulate_ud(ctxt);
1161624f
GN		 4781 goto done;
4782 }
4783
e24186e0 4784 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 4785 rc = emulate_ud(ctxt);
d380a5e4
GN		 4786 goto done;
4787 }
4788
d40a6898
PB		 4789 if (unlikely(ctxt->d &
4790 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4791 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4792 (ctxt->d & Undefined)) {
4793 rc = emulate_ud(ctxt);
4794 goto done;
4795 }
1253791d 4796
d40a6898
PB		 4797 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4798 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4799 rc = emulate_ud(ctxt);
cbe2c9d3 4800 goto done;
d40a6898 4801 }
cbe2c9d3 4802
d40a6898
PB		 4803 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4804 rc = emulate_nm(ctxt);
c4f035c6 4805 goto done;
d40a6898 4806 }
c4f035c6 4807
d40a6898
PB		 4808 if (ctxt->d & Mmx) {
4809 rc = flush_pending_x87_faults(ctxt);
4810 if (rc != X86EMUL_CONTINUE)
4811 goto done;
4812 /*
4813 * Now that we know the fpu is exception safe, we can fetch
4814 * operands from it.
4815 */
4816 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4817 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4818 if (!(ctxt->d & Mov))
4819 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4820 }
e92805ac 4821
685bbf4a 4822 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4823 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4824 X86_ICPT_PRE_EXCEPT);
4825 if (rc != X86EMUL_CONTINUE)
4826 goto done;
4827 }
8ea7d6ae 4828
64a38292
NA		 4829 /* Instruction can only be executed in protected mode */
4830 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4831 rc = emulate_ud(ctxt);
4832 goto done;
4833 }
4834
d40a6898
PB		 4835 /* Privileged instruction can be executed only in CPL=0 */
4836 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 4837 if (ctxt->d & PrivUD)
4838 rc = emulate_ud(ctxt);
4839 else
4840 rc = emulate_gp(ctxt, 0);
d09beabd 4841 goto done;
d40a6898 4842 }
d09beabd 4843
d40a6898 4844 /* Do instruction specific permission checks */
685bbf4a 4845 if (ctxt->d & CheckPerm) {
d40a6898
PB		 4846 rc = ctxt->check_perm(ctxt);
4847 if (rc != X86EMUL_CONTINUE)
4848 goto done;
4849 }
4850
685bbf4a 4851 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
d40a6898
PB		 4852 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4853 X86_ICPT_POST_EXCEPT);
4854 if (rc != X86EMUL_CONTINUE)
4855 goto done;
4856 }
4857
4858 if (ctxt->rep_prefix && (ctxt->d & String)) {
4859 /* All REP prefixes have the same first termination condition */
4860 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4861 ctxt->eip = ctxt->_eip;
4467c3f1 4862 ctxt->eflags &= ~EFLG_RF;
d40a6898
PB		 4863 goto done;
4864 }
b9fa9d6b 4865 }
b9fa9d6b
AK		 4866 }
4867
9dac77fa
AK		 4868 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4869 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4870 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 4871 if (rc != X86EMUL_CONTINUE)
8b4caf66 4872 goto done;
9dac77fa 4873 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 4874 }
4875
9dac77fa
AK		 4876 if (ctxt->src2.type == OP_MEM) {
4877 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4878 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 4879 if (rc != X86EMUL_CONTINUE)
4880 goto done;
4881 }
4882
9dac77fa 4883 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 4884 goto special_insn;
4885
4886
9dac77fa 4887 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 4888 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 4889 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4890 &ctxt->dst.val, ctxt->dst.bytes);
69f55cb1
GN		 4891 if (rc != X86EMUL_CONTINUE)
4892 goto done;
038e51de 4893 }
9dac77fa 4894 ctxt->dst.orig_val = ctxt->dst.val;
038e51de 4895
018a98db
AK		 4896special_insn:
4897
685bbf4a 4898 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
9dac77fa 4899 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 4900 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 4901 if (rc != X86EMUL_CONTINUE)
4902 goto done;
4903 }
4904
b9a1ecb9
NA		 4905 if (ctxt->rep_prefix && (ctxt->d & String))
4906 ctxt->eflags |= EFLG_RF;
4907 else
4908 ctxt->eflags &= ~EFLG_RF;
4467c3f1 4909
9dac77fa 4910 if (ctxt->execute) {
e28bbd44
AK		 4911 if (ctxt->d & Fastop) {
4912 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4913 rc = fastop(ctxt, fop);
4914 if (rc != X86EMUL_CONTINUE)
4915 goto done;
4916 goto writeback;
4917 }
9dac77fa 4918 rc = ctxt->execute(ctxt);
ef65c889
AK		 4919 if (rc != X86EMUL_CONTINUE)
4920 goto done;
4921 goto writeback;
4922 }
4923
1ce19dc1 4924 if (ctxt->opcode_len == 2)
6aa8b732 4925 goto twobyte_insn;
0bc5eedb
BP		 4926 else if (ctxt->opcode_len == 3)
4927 goto threebyte_insn;
6aa8b732 4928
9dac77fa 4929 switch (ctxt->b) {
6aa8b732 4930 case 0x63: /* movsxd */
8b4caf66 4931 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 4932 goto cannot_emulate;
9dac77fa 4933 ctxt->dst.val = (s32) ctxt->src.val;
6aa8b732 4934 break;
b2833e3c 4935 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 4936 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 4937 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 4938 break;
7e0b54b1 4939 case 0x8d: /* lea r16/r32, m */
9dac77fa 4940 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 4941 break;
3d9e77df 4942 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 4943 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 4944 ctxt->dst.type = OP_NONE;
4945 else
4946 rc = em_xchg(ctxt);
e4f973ae 4947 break;
e8b6fa70 4948 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 4949 switch (ctxt->op_bytes) {
4950 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4951 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4952 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 4953 }
4954 break;
6e154e56 4955 case 0xcc: /* int3 */
5c5df76b
TY		 4956 rc = emulate_int(ctxt, 3);
4957 break;
6e154e56 4958 case 0xcd: /* int n */
9dac77fa 4959 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 4960 break;
4961 case 0xce: /* into */
5c5df76b
TY		 4962 if (ctxt->eflags & EFLG_OF)
4963 rc = emulate_int(ctxt, 4);
6e154e56 4964 break;
1a52e051 4965 case 0xe9: /* jmp rel */
db5b0762 4966 case 0xeb: /* jmp rel short */
234f3ce4 4967 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 4968 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4969 break;
111de5d6 4970 case 0xf4: /* hlt */
6c3287f7 4971 ctxt->ops->halt(ctxt);
19fdfa0d 4972 break;
111de5d6
AK		 4973 case 0xf5: /* cmc */
4974 /* complement carry flag from eflags reg */
4975 ctxt->eflags ^= EFLG_CF;
111de5d6
AK		 4976 break;
4977 case 0xf8: /* clc */
4978 ctxt->eflags &= ~EFLG_CF;
111de5d6 4979 break;
8744aa9a
MG		 4980 case 0xf9: /* stc */
4981 ctxt->eflags |= EFLG_CF;
4982 break;
fb4616f4
MG		 4983 case 0xfc: /* cld */
4984 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4985 break;
4986 case 0xfd: /* std */
4987 ctxt->eflags |= EFLG_DF;
fb4616f4 4988 break;
91269b8f
AK		 4989 default:
4990 goto cannot_emulate;
6aa8b732 4991 }
018a98db 4992
7d9ddaed
AK		 4993 if (rc != X86EMUL_CONTINUE)
4994 goto done;
4995
018a98db 4996writeback:
fb32b1ed
AK		 4997 if (ctxt->d & SrcWrite) {
4998 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4999 rc = writeback(ctxt, &ctxt->src);
5000 if (rc != X86EMUL_CONTINUE)
5001 goto done;
5002 }
ee212297
NA		 5003 if (!(ctxt->d & NoWrite)) {
5004 rc = writeback(ctxt, &ctxt->dst);
5005 if (rc != X86EMUL_CONTINUE)
5006 goto done;
5007 }
018a98db 5008
5cd21917
GN		 5009 /*
5010 * restore dst type in case the decoding will be reused
5011 * (happens for string instruction )
5012 */
9dac77fa 5013 ctxt->dst.type = saved_dst_type;
5cd21917 5014
9dac77fa 5015 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5016 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5017
9dac77fa 5018 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5019 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5020
9dac77fa 5021 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5022 unsigned int count;
9dac77fa 5023 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5024 if ((ctxt->d & SrcMask) == SrcSI)
5025 count = ctxt->src.count;
5026 else
5027 count = ctxt->dst.count;
01485a22 5028 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5029
d2ddd1c4
GN		 5030 if (!string_insn_completed(ctxt)) {
5031 /*
5032 * Re-enter guest when pio read ahead buffer is empty
5033 * or, if it is not used, after each 1024 iteration.
5034 */
dd856efa 5035 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5036 (r->end == 0 || r->end != r->pos)) {
5037 /*
5038 * Reset read cache. Usually happens before
5039 * decode, but since instruction is restarted
5040 * we have to do it here.
5041 */
9dac77fa 5042 ctxt->mem_read.end = 0;
dd856efa 5043 writeback_registers(ctxt);
d2ddd1c4
GN		 5044 return EMULATION_RESTART;
5045 }
5046 goto done; /* skip rip writeback */
0fa6ccbd 5047 }
b9a1ecb9 5048 ctxt->eflags &= ~EFLG_RF;
5cd21917 5049 }
d2ddd1c4 5050
9dac77fa 5051 ctxt->eip = ctxt->_eip;
018a98db
AK		 5052
5053done:
e0ad0b47
PB		 5054 if (rc == X86EMUL_PROPAGATE_FAULT) {
5055 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5056 ctxt->have_exception = true;
e0ad0b47 5057 }
775fde86
JR		 5058 if (rc == X86EMUL_INTERCEPTED)
5059 return EMULATION_INTERCEPTED;
5060
dd856efa
AK		 5061 if (rc == X86EMUL_CONTINUE)
5062 writeback_registers(ctxt);
5063
d2ddd1c4 5064 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5065
5066twobyte_insn:
9dac77fa 5067 switch (ctxt->b) {
018a98db 5068 case 0x09: /* wbinvd */
cfb22375 5069 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5070 break;
5071 case 0x08: /* invd */
018a98db
AK		 5072 case 0x0d: /* GrpP (prefetch) */
5073 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5074 case 0x1f: /* nop */
018a98db
AK		 5075 break;
5076 case 0x20: /* mov cr, reg */
9dac77fa 5077 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5078 break;
6aa8b732 5079 case 0x21: /* mov from dr to reg */
9dac77fa 5080 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5081 break;
6aa8b732 5082 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5083 if (test_cc(ctxt->b, ctxt->eflags))
5084 ctxt->dst.val = ctxt->src.val;
5085 else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
5086 ctxt->op_bytes != 4)
9dac77fa 5087 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5088 break;
b2833e3c 5089 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5090 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5091 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5092 break;
ee45b58e 5093 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5094 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5095 break;
6aa8b732 5096 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5097 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5098 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5099 : (u16) ctxt->src.val;
6aa8b732 5100 break;
6aa8b732 5101 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5102 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5103 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5104 (s16) ctxt->src.val;
6aa8b732 5105 break;
91269b8f
AK		 5106 default:
5107 goto cannot_emulate;
6aa8b732 5108 }
7d9ddaed 5109
0bc5eedb
BP		 5110threebyte_insn:
5111
7d9ddaed
AK		 5112 if (rc != X86EMUL_CONTINUE)
5113 goto done;
5114
6aa8b732
AK		 5115 goto writeback;
5116
5117cannot_emulate:
a0c0ab2f 5118 return EMULATION_FAILED;
6aa8b732 5119}
dd856efa
AK		 5120
5121void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5122{
5123 invalidate_registers(ctxt);
5124}
5125
5126void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5127{
5128 writeback_registers(ctxt);
5129}
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