]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/emulate.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: Add return value to kvm_cpuid().
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
56e82318 25#include <asm/kvm_emulate.h>
b7d491e7 26#include <linux/stringify.h>
3db176d5 27#include <asm/debugreg.h>
6aa8b732 28
3eeb3288 29#include "x86.h"
38ba30ba 30#include "tss.h"
e99f0507 31
a9945549
AK		 32/*
33 * Operand types
34 */
b1ea50b2
AK		 35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
4dd6a57d
AK		 44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
5e2c6883 47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
0fe59128
AK		 48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
c191a7a0
AK		 55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
28867cee 61#define OpMem8 26ull /* 8-bit zero extended memory operand */
5e2c6883 62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
7fa57952 63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
820207c8
AK		 64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
0fe59128
AK		 66
67#define OpBits 5 /* Width of operand field */
b1ea50b2 68#define OpMask ((1ull << OpBits) - 1)
a9945549 69
6aa8b732
AK		 70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 80#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 81/* Destination operand type. */
a9945549
AK		 82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
16bebefe 89#define DstMem16 (OpMem16 << DstShift)
a9945549
AK		 90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
820207c8 92#define DstAccLo (OpAccLo << DstShift)
a9945549 93#define DstMask (OpMask << DstShift)
6aa8b732 94/* Source operand type. */
0fe59128
AK		 95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
7fa57952 107#define SrcXLat (OpXLat << SrcShift)
0fe59128
AK		 108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
5e2c6883 112#define SrcImm64 (OpImm64 << SrcShift)
0fe59128 113#define SrcDX (OpDX << SrcShift)
28867cee 114#define SrcMem8 (OpMem8 << SrcShift)
820207c8 115#define SrcAccHi (OpAccHi << SrcShift)
0fe59128 116#define SrcMask (OpMask << SrcShift)
221192bd
MT		 117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
045a282c 126#define Escape (5<<15) /* Escape to coprocessor instruction */
39f062ff 127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
2276b511 128#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
221192bd 129#define Sse (1<<18) /* SSE Vector instruction */
20c29ff2
AK		 130/* Generic ModRM decode. */
131#define ModRM (1<<19)
132/* Destination is only written; never read. */
133#define Mov (1<<20)
d8769fed 134/* Misc flags */
8ea7d6ae 135#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
b51e974f 136#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
5a506b12 137#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 138#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 139#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 140#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 141#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 142#define No64 (1<<28)
d5ae7ce8 143#define PageTable (1 << 29) /* instruction used to write page table */
0b789eee 144#define NotImpl (1 << 30) /* instruction is not implemented */
0dc8d10f 145/* Source 2 operand type */
0b789eee 146#define Src2Shift (31)
4dd6a57d 147#define Src2None (OpNone << Src2Shift)
ab2c5ce6 148#define Src2Mem (OpMem << Src2Shift)
4dd6a57d
AK		 149#define Src2CL (OpCL << Src2Shift)
150#define Src2ImmByte (OpImmByte << Src2Shift)
151#define Src2One (OpOne << Src2Shift)
152#define Src2Imm (OpImm << Src2Shift)
c191a7a0
AK		 153#define Src2ES (OpES << Src2Shift)
154#define Src2CS (OpCS << Src2Shift)
155#define Src2SS (OpSS << Src2Shift)
156#define Src2DS (OpDS << Src2Shift)
157#define Src2FS (OpFS << Src2Shift)
158#define Src2GS (OpGS << Src2Shift)
4dd6a57d 159#define Src2Mask (OpMask << Src2Shift)
cbe2c9d3 160#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
48520187 161#define AlignMask ((u64)7 << 41)
1c11b376 162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
48520187
RK		 163#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
165#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
e28bbd44 166#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
b6744dc3 167#define NoWrite ((u64)1 << 45) /* No writeback */
fb32b1ed 168#define SrcWrite ((u64)1 << 46) /* Write back src operand */
9b88ae99 169#define NoMod ((u64)1 << 47) /* Mod field is ignored */
d40a6898
PB		 170#define Intercept ((u64)1 << 48) /* Has valid intercept field */
171#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
68efa764 172#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
58b7075d 173#define NearBranch ((u64)1 << 52) /* Near branches */
ed9aad21 174#define No16 ((u64)1 << 53) /* No 16 bit operand */
ab708099 175#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
0f89b207 176#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
6aa8b732 177
820207c8 178#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
6aa8b732 179
d0e53325
AK		 180#define X2(x...) x, x
181#define X3(x...) X2(x), x
182#define X4(x...) X2(x), X2(x)
183#define X5(x...) X4(x), x
184#define X6(x...) X4(x), X2(x)
185#define X7(x...) X4(x), X3(x)
186#define X8(x...) X4(x), X4(x)
187#define X16(x...) X8(x), X8(x)
83babbca 188
e28bbd44
AK		 189#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
190#define FASTOP_SIZE 8
191
192/*
193 * fastop functions have a special calling convention:
194 *
017da7b6
AK		 195 * dst: rax (in/out)
196 * src: rdx (in/out)
e28bbd44
AK		 197 * src2: rcx (in)
198 * flags: rflags (in/out)
b8c0b6ae 199 * ex: rsi (in:fastop pointer, out:zero if exception)
e28bbd44
AK		 200 *
201 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
202 * different operand sizes can be reached by calculation, rather than a jump
203 * table (which would be bigger than the code).
204 *
205 * fastop functions are declared as taking a never-defined fastop parameter,
206 * so they can't be called from C directly.
207 */
208
209struct fastop;
210
d65b1dee 211struct opcode {
b1ea50b2
AK		 212 u64 flags : 56;
213 u64 intercept : 8;
120df890 214 union {
ef65c889 215 int (*execute)(struct x86_emulate_ctxt *ctxt);
fd0a0d82
MK		 216 const struct opcode *group;
217 const struct group_dual *gdual;
218 const struct gprefix *gprefix;
045a282c 219 const struct escape *esc;
39f062ff 220 const struct instr_dual *idual;
2276b511 221 const struct mode_dual *mdual;
e28bbd44 222 void (*fastop)(struct fastop *fake);
120df890 223 } u;
d09beabd 224 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 225};
226
227struct group_dual {
228 struct opcode mod012[8];
229 struct opcode mod3[8];
d65b1dee
AK		 230};
231
0d7cdee8
AK		 232struct gprefix {
233 struct opcode pfx_no;
234 struct opcode pfx_66;
235 struct opcode pfx_f2;
236 struct opcode pfx_f3;
237};
238
045a282c
GN		 239struct escape {
240 struct opcode op[8];
241 struct opcode high[64];
242};
243
39f062ff
NA		 244struct instr_dual {
245 struct opcode mod012;
246 struct opcode mod3;
247};
248
2276b511
NA		 249struct mode_dual {
250 struct opcode mode32;
251 struct opcode mode64;
252};
253
62bd430e 254#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
62bd430e 255
3dc4bc4f
NA		 256enum x86_transfer_type {
257 X86_TRANSFER_NONE,
258 X86_TRANSFER_CALL_JMP,
259 X86_TRANSFER_RET,
260 X86_TRANSFER_TASK_SWITCH,
261};
262
dd856efa
AK		 263static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
264{
265 if (!(ctxt->regs_valid & (1 << nr))) {
266 ctxt->regs_valid |= 1 << nr;
267 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
268 }
269 return ctxt->_regs[nr];
270}
271
272static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
273{
274 ctxt->regs_valid |= 1 << nr;
275 ctxt->regs_dirty |= 1 << nr;
276 return &ctxt->_regs[nr];
277}
278
279static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
280{
281 reg_read(ctxt, nr);
282 return reg_write(ctxt, nr);
283}
284
285static void writeback_registers(struct x86_emulate_ctxt *ctxt)
286{
287 unsigned reg;
288
289 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
290 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
291}
292
293static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
294{
295 ctxt->regs_dirty = 0;
296 ctxt->regs_valid = 0;
297}
298
6aa8b732
AK		 299/*
300 * These EFLAGS bits are restored from saved value during emulation, and
301 * any changes are written back to the saved value after emulation.
302 */
0efb0440
NA		 303#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
304 X86_EFLAGS_PF|X86_EFLAGS_CF)
6aa8b732 305
dda96d8f
AK		 306#ifdef CONFIG_X86_64
307#define ON64(x) x
308#else
309#define ON64(x)
310#endif
311
4d758349
AK		 312static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
313
1482a082
JP		 314#define FOP_FUNC(name) \
315 ".align " __stringify(FASTOP_SIZE) " \n\t" \
316 ".type " name ", @function \n\t" \
317 name ":\n\t"
318
b7d491e7
AK		 319#define FOP_RET "ret \n\t"
320
321#define FOP_START(op) \
322 extern void em_##op(struct fastop *fake); \
323 asm(".pushsection .text, \"ax\" \n\t" \
324 ".global em_" #op " \n\t" \
1482a082 325 FOP_FUNC("em_" #op)
b7d491e7
AK		 326
327#define FOP_END \
328 ".popsection")
329
1482a082
JP		 330#define FOPNOP() \
331 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
332 FOP_RET
0bdea068 333
b7d491e7 334#define FOP1E(op, dst) \
1482a082
JP		 335 FOP_FUNC(#op "_" #dst) \
336 "10: " #op " %" #dst " \n\t" FOP_RET
b8c0b6ae
AK		 337
338#define FOP1EEX(op, dst) \
339 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
b7d491e7
AK		 340
341#define FASTOP1(op) \
342 FOP_START(op) \
343 FOP1E(op##b, al) \
344 FOP1E(op##w, ax) \
345 FOP1E(op##l, eax) \
346 ON64(FOP1E(op##q, rax)) \
347 FOP_END
348
b9fa409b
AK		 349/* 1-operand, using src2 (for MUL/DIV r/m) */
350#define FASTOP1SRC2(op, name) \
351 FOP_START(name) \
352 FOP1E(op, cl) \
353 FOP1E(op, cx) \
354 FOP1E(op, ecx) \
355 ON64(FOP1E(op, rcx)) \
356 FOP_END
357
b8c0b6ae
AK		 358/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
359#define FASTOP1SRC2EX(op, name) \
360 FOP_START(name) \
361 FOP1EEX(op, cl) \
362 FOP1EEX(op, cx) \
363 FOP1EEX(op, ecx) \
364 ON64(FOP1EEX(op, rcx)) \
365 FOP_END
366
f7857f35 367#define FOP2E(op, dst, src) \
1482a082
JP		 368 FOP_FUNC(#op "_" #dst "_" #src) \
369 #op " %" #src ", %" #dst " \n\t" FOP_RET
f7857f35
AK		 370
371#define FASTOP2(op) \
372 FOP_START(op) \
017da7b6
AK		 373 FOP2E(op##b, al, dl) \
374 FOP2E(op##w, ax, dx) \
375 FOP2E(op##l, eax, edx) \
376 ON64(FOP2E(op##q, rax, rdx)) \
f7857f35
AK		 377 FOP_END
378
11c363ba
AK		 379/* 2 operand, word only */
380#define FASTOP2W(op) \
381 FOP_START(op) \
382 FOPNOP() \
017da7b6
AK		 383 FOP2E(op##w, ax, dx) \
384 FOP2E(op##l, eax, edx) \
385 ON64(FOP2E(op##q, rax, rdx)) \
11c363ba
AK		 386 FOP_END
387
007a3b54
AK		 388/* 2 operand, src is CL */
389#define FASTOP2CL(op) \
390 FOP_START(op) \
391 FOP2E(op##b, al, cl) \
392 FOP2E(op##w, ax, cl) \
393 FOP2E(op##l, eax, cl) \
394 ON64(FOP2E(op##q, rax, cl)) \
395 FOP_END
396
5aca3722
NA		 397/* 2 operand, src and dest are reversed */
398#define FASTOP2R(op, name) \
399 FOP_START(name) \
400 FOP2E(op##b, dl, al) \
401 FOP2E(op##w, dx, ax) \
402 FOP2E(op##l, edx, eax) \
403 ON64(FOP2E(op##q, rdx, rax)) \
404 FOP_END
405
0bdea068 406#define FOP3E(op, dst, src, src2) \
1482a082
JP		 407 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
408 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
0bdea068
AK		 409
410/* 3-operand, word-only, src2=cl */
411#define FASTOP3WCL(op) \
412 FOP_START(op) \
413 FOPNOP() \
017da7b6
AK		 414 FOP3E(op##w, ax, dx, cl) \
415 FOP3E(op##l, eax, edx, cl) \
416 ON64(FOP3E(op##q, rax, rdx, cl)) \
0bdea068
AK		 417 FOP_END
418
9ae9feba 419/* Special case for SETcc - 1 instruction per cc */
1482a082
JP		 420#define FOP_SETCC(op) \
421 ".align 4 \n\t" \
422 ".type " #op ", @function \n\t" \
423 #op ": \n\t" \
424 #op " %al \n\t" \
425 FOP_RET
9ae9feba 426
b8c0b6ae
AK		 427asm(".global kvm_fastop_exception \n"
428 "kvm_fastop_exception: xor %esi, %esi; ret");
429
9ae9feba
AK		 430FOP_START(setcc)
431FOP_SETCC(seto)
432FOP_SETCC(setno)
433FOP_SETCC(setc)
434FOP_SETCC(setnc)
435FOP_SETCC(setz)
436FOP_SETCC(setnz)
437FOP_SETCC(setbe)
438FOP_SETCC(setnbe)
439FOP_SETCC(sets)
440FOP_SETCC(setns)
441FOP_SETCC(setp)
442FOP_SETCC(setnp)
443FOP_SETCC(setl)
444FOP_SETCC(setnl)
445FOP_SETCC(setle)
446FOP_SETCC(setnle)
447FOP_END;
448
326f578f
PB		 449FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
450FOP_END;
451
aabba3c6
RK		 452/*
453 * XXX: inoutclob user must know where the argument is being expanded.
454 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
455 */
456#define asm_safe(insn, inoutclob...) \
457({ \
458 int _fault = 0; \
459 \
460 asm volatile("1:" insn "\n" \
461 "2:\n" \
462 ".pushsection .fixup, \"ax\"\n" \
463 "3: movl $1, %[_fault]\n" \
464 " jmp 2b\n" \
465 ".popsection\n" \
466 _ASM_EXTABLE(1b, 3b) \
467 : [_fault] "+qm"(_fault) inoutclob ); \
468 \
469 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
470})
471
8a76d7f2
JR		 472static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
473 enum x86_intercept intercept,
474 enum x86_intercept_stage stage)
475{
476 struct x86_instruction_info info = {
477 .intercept = intercept,
9dac77fa
AK		 478 .rep_prefix = ctxt->rep_prefix,
479 .modrm_mod = ctxt->modrm_mod,
480 .modrm_reg = ctxt->modrm_reg,
481 .modrm_rm = ctxt->modrm_rm,
482 .src_val = ctxt->src.val64,
6cbc5f5a 483 .dst_val = ctxt->dst.val64,
9dac77fa
AK		 484 .src_bytes = ctxt->src.bytes,
485 .dst_bytes = ctxt->dst.bytes,
486 .ad_bytes = ctxt->ad_bytes,
8a76d7f2
JR		 487 .next_rip = ctxt->eip,
488 };
489
2953538e 490 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 491}
492
f47cfa31
AK		 493static void assign_masked(ulong *dest, ulong src, ulong mask)
494{
495 *dest = (*dest & ~mask) | (src & mask);
496}
497
6fd8e127
NA		 498static void assign_register(unsigned long *reg, u64 val, int bytes)
499{
500 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
501 switch (bytes) {
502 case 1:
503 *(u8 *)reg = (u8)val;
504 break;
505 case 2:
506 *(u16 *)reg = (u16)val;
507 break;
508 case 4:
509 *reg = (u32)val;
510 break; /* 64b: zero-extend */
511 case 8:
512 *reg = val;
513 break;
514 }
515}
516
9dac77fa 517static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
ddcb2885 518{
9dac77fa 519 return (1UL << (ctxt->ad_bytes << 3)) - 1;
ddcb2885
HH		 520}
521
f47cfa31
AK		 522static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
523{
524 u16 sel;
525 struct desc_struct ss;
526
527 if (ctxt->mode == X86EMUL_MODE_PROT64)
528 return ~0UL;
529 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
530 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
531}
532
612e89f0
AK		 533static int stack_size(struct x86_emulate_ctxt *ctxt)
534{
535 return (__fls(stack_mask(ctxt)) + 1) >> 3;
536}
537
6aa8b732 538/* Access/update address held in a register, based on addressing mode. */
e4706772 539static inline unsigned long
9dac77fa 540address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
e4706772 541{
9dac77fa 542 if (ctxt->ad_bytes == sizeof(unsigned long))
e4706772
HH		 543 return reg;
544 else
9dac77fa 545 return reg & ad_mask(ctxt);
e4706772
HH		 546}
547
548static inline unsigned long
01485a22 549register_address(struct x86_emulate_ctxt *ctxt, int reg)
e4706772 550{
01485a22 551 return address_mask(ctxt, reg_read(ctxt, reg));
e4706772
HH		 552}
553
5ad105e5
AK		 554static void masked_increment(ulong *reg, ulong mask, int inc)
555{
556 assign_masked(reg, *reg + inc, mask);
557}
558
7a957275 559static inline void
01485a22 560register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
7a957275 561{
ee122a71 562 ulong *preg = reg_rmw(ctxt, reg);
5ad105e5 563
ee122a71 564 assign_register(preg, *preg + inc, ctxt->ad_bytes);
5ad105e5
AK		 565}
566
567static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
568{
dd856efa 569 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
7a957275 570}
6aa8b732 571
56697687
AK		 572static u32 desc_limit_scaled(struct desc_struct *desc)
573{
574 u32 limit = get_desc_limit(desc);
575
576 return desc->g ? (limit << 12) | 0xfff : limit;
577}
578
7b105ca2 579static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
7a5b56df
AK		 580{
581 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
582 return 0;
583
7b105ca2 584 return ctxt->ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 585}
586
35d3d4a1
AK		 587static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
588 u32 error, bool valid)
54b8486f 589{
e0ad0b47 590 WARN_ON(vec > 0x1f);
da9cb575
AK		 591 ctxt->exception.vector = vec;
592 ctxt->exception.error_code = error;
593 ctxt->exception.error_code_valid = valid;
35d3d4a1 594 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 595}
596
3b88e41a
JR		 597static int emulate_db(struct x86_emulate_ctxt *ctxt)
598{
599 return emulate_exception(ctxt, DB_VECTOR, 0, false);
600}
601
35d3d4a1 602static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 603{
35d3d4a1 604 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 605}
606
618ff15d
AK		 607static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
608{
609 return emulate_exception(ctxt, SS_VECTOR, err, true);
610}
611
35d3d4a1 612static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 613{
35d3d4a1 614 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 615}
616
35d3d4a1 617static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 618{
35d3d4a1 619 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 620}
621
34d1f490
AK		 622static int emulate_de(struct x86_emulate_ctxt *ctxt)
623{
35d3d4a1 624 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 625}
626
1253791d
AK		 627static int emulate_nm(struct x86_emulate_ctxt *ctxt)
628{
629 return emulate_exception(ctxt, NM_VECTOR, 0, false);
630}
631
1aa36616
AK		 632static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
633{
634 u16 selector;
635 struct desc_struct desc;
636
637 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
638 return selector;
639}
640
641static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
642 unsigned seg)
643{
644 u16 dummy;
645 u32 base3;
646 struct desc_struct desc;
647
648 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
649 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
650}
651
1c11b376
AK		 652/*
653 * x86 defines three classes of vector instructions: explicitly
654 * aligned, explicitly unaligned, and the rest, which change behaviour
655 * depending on whether they're AVX encoded or not.
656 *
657 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
d3fe959f
RK		 658 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
659 * 512 bytes of data must be aligned to a 16 byte boundary.
1c11b376 660 */
d3fe959f 661static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
1c11b376 662{
48520187 663 u64 alignment = ctxt->d & AlignMask;
1c11b376 664
1c11b376 665 if (likely(size < 16))
d3fe959f 666 return 1;
1c11b376 667
48520187
RK		 668 switch (alignment) {
669 case Unaligned:
670 case Avx:
d3fe959f 671 return 1;
48520187 672 case Aligned16:
d3fe959f 673 return 16;
48520187
RK		 674 case Aligned:
675 default:
d3fe959f 676 return size;
48520187 677 }
1c11b376
AK		 678}
679
d09155d2
PB		 680static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
681 struct segmented_address addr,
682 unsigned *max_size, unsigned size,
683 bool write, bool fetch,
d50eaa18 684 enum x86emul_mode mode, ulong *linear)
52fd8b44 685{
618ff15d
AK		 686 struct desc_struct desc;
687 bool usable;
52fd8b44 688 ulong la;
618ff15d 689 u32 lim;
1aa36616 690 u16 sel;
52fd8b44 691
7b105ca2 692 la = seg_base(ctxt, addr.seg) + addr.ea;
fd56e154 693 *max_size = 0;
d50eaa18 694 switch (mode) {
618ff15d 695 case X86EMUL_MODE_PROT64:
0c1d77f4 696 *linear = la;
4be4de7e 697 if (is_noncanonical_address(la))
abc7d8a4 698 goto bad;
fd56e154
PB		 699
700 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
701 if (size > *max_size)
702 goto bad;
618ff15d
AK		 703 break;
704 default:
0c1d77f4 705 *linear = la = (u32)la;
1aa36616
AK		 706 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
707 addr.seg);
618ff15d
AK		 708 if (!usable)
709 goto bad;
58b7825b
GN		 710 /* code segment in protected mode or read-only data segment */
711 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
712 || !(desc.type & 2)) && write)
618ff15d
AK		 713 goto bad;
714 /* unreadable code segment */
3d9b938e 715 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 716 goto bad;
717 lim = desc_limit_scaled(&desc);
997b0412 718 if (!(desc.type & 8) && (desc.type & 4)) {
fc058680 719 /* expand-down segment */
fd56e154 720 if (addr.ea <= lim)
618ff15d
AK		 721 goto bad;
722 lim = desc.d ? 0xffffffff : 0xffff;
618ff15d 723 }
997b0412
PB		 724 if (addr.ea > lim)
725 goto bad;
bac15531
NA		 726 if (lim == 0xffffffff)
727 *max_size = ~0u;
728 else {
729 *max_size = (u64)lim + 1 - addr.ea;
730 if (size > *max_size)
731 goto bad;
732 }
618ff15d
AK		 733 break;
734 }
d3fe959f 735 if (la & (insn_alignment(ctxt, size) - 1))
1c11b376 736 return emulate_gp(ctxt, 0);
52fd8b44 737 return X86EMUL_CONTINUE;
618ff15d
AK		 738bad:
739 if (addr.seg == VCPU_SREG_SS)
3606189f 740 return emulate_ss(ctxt, 0);
618ff15d 741 else
3606189f 742 return emulate_gp(ctxt, 0);
52fd8b44
AK		 743}
744
3d9b938e
NE		 745static int linearize(struct x86_emulate_ctxt *ctxt,
746 struct segmented_address addr,
747 unsigned size, bool write,
748 ulong *linear)
749{
fd56e154 750 unsigned max_size;
d50eaa18
NA		 751 return __linearize(ctxt, addr, &max_size, size, write, false,
752 ctxt->mode, linear);
3d9b938e
NE		 753}
754
d50eaa18
NA		 755static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
756 enum x86emul_mode mode)
757{
758 ulong linear;
759 int rc;
760 unsigned max_size;
761 struct segmented_address addr = { .seg = VCPU_SREG_CS,
762 .ea = dst };
763
764 if (ctxt->op_bytes != sizeof(unsigned long))
765 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
766 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
767 if (rc == X86EMUL_CONTINUE)
768 ctxt->_eip = addr.ea;
769 return rc;
770}
771
772static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
773{
774 return assign_eip(ctxt, dst, ctxt->mode);
3d9b938e
NE		 775}
776
d50eaa18
NA		 777static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
778 const struct desc_struct *cs_desc)
779{
780 enum x86emul_mode mode = ctxt->mode;
82268083 781 int rc;
d50eaa18
NA		 782
783#ifdef CONFIG_X86_64
82268083
NA		 784 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
785 if (cs_desc->l) {
786 u64 efer = 0;
d50eaa18 787
82268083
NA		 788 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
789 if (efer & EFER_LMA)
790 mode = X86EMUL_MODE_PROT64;
791 } else
792 mode = X86EMUL_MODE_PROT32; /* temporary value */
d50eaa18
NA		 793 }
794#endif
795 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
796 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
82268083
NA		 797 rc = assign_eip(ctxt, dst, mode);
798 if (rc == X86EMUL_CONTINUE)
799 ctxt->mode = mode;
800 return rc;
d50eaa18
NA		 801}
802
803static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
804{
805 return assign_eip_near(ctxt, ctxt->_eip + rel);
806}
3d9b938e 807
3ca3ac4d
AK		 808static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
809 struct segmented_address addr,
810 void *data,
811 unsigned size)
812{
9fa088f4
AK		 813 int rc;
814 ulong linear;
815
83b8795a 816 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 817 if (rc != X86EMUL_CONTINUE)
818 return rc;
0f65dd70 819 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 820}
821
129a72a0
SR		 822static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
823 struct segmented_address addr,
824 void *data,
825 unsigned int size)
826{
827 int rc;
828 ulong linear;
829
830 rc = linearize(ctxt, addr, size, true, &linear);
831 if (rc != X86EMUL_CONTINUE)
832 return rc;
833 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
834}
835
807941b1 836/*
285ca9e9 837 * Prefetch the remaining bytes of the instruction without crossing page
807941b1
TY		 838 * boundary if they are not in fetch_cache yet.
839 */
9506d57d 840static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
62266869 841{
62266869 842 int rc;
fd56e154 843 unsigned size, max_size;
285ca9e9 844 unsigned long linear;
17052f16 845 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
285ca9e9 846 struct segmented_address addr = { .seg = VCPU_SREG_CS,
17052f16
PB		 847 .ea = ctxt->eip + cur_size };
848
fd56e154
PB		 849 /*
850 * We do not know exactly how many bytes will be needed, and
851 * __linearize is expensive, so fetch as much as possible. We
852 * just have to avoid going beyond the 15 byte limit, the end
853 * of the segment, or the end of the page.
854 *
855 * __linearize is called with size 0 so that it does not do any
856 * boundary check itself. Instead, we use max_size to check
857 * against op_size.
858 */
d50eaa18
NA		 859 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
860 &linear);
719d5a9b
PB		 861 if (unlikely(rc != X86EMUL_CONTINUE))
862 return rc;
863
fd56e154 864 size = min_t(unsigned, 15UL ^ cur_size, max_size);
719d5a9b 865 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
5cfc7e0f
PB		 866
867 /*
868 * One instruction can only straddle two pages,
869 * and one has been loaded at the beginning of
870 * x86_decode_insn. So, if not enough bytes
871 * still, we must have hit the 15-byte boundary.
872 */
873 if (unlikely(size < op_size))
fd56e154
PB		 874 return emulate_gp(ctxt, 0);
875
17052f16 876 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
285ca9e9
PB		 877 size, &ctxt->exception);
878 if (unlikely(rc != X86EMUL_CONTINUE))
879 return rc;
17052f16 880 ctxt->fetch.end += size;
3e2815e9 881 return X86EMUL_CONTINUE;
62266869
AK		 882}
883
9506d57d
PB		 884static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
885 unsigned size)
62266869 886{
08da44ae
NA		 887 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
888
889 if (unlikely(done_size < size))
890 return __do_insn_fetch_bytes(ctxt, size - done_size);
9506d57d
PB		 891 else
892 return X86EMUL_CONTINUE;
62266869
AK		 893}
894
67cbc90d 895/* Fetch next part of the instruction being emulated. */
e85a1085 896#define insn_fetch(_type, _ctxt) \
9506d57d 897({ _type _x; \
9506d57d
PB		 898 \
899 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
67cbc90d
TY		 900 if (rc != X86EMUL_CONTINUE) \
901 goto done; \
9506d57d 902 ctxt->_eip += sizeof(_type); \
8616abc2 903 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
17052f16 904 ctxt->fetch.ptr += sizeof(_type); \
9506d57d 905 _x; \
67cbc90d
TY		 906})
907
807941b1 908#define insn_fetch_arr(_arr, _size, _ctxt) \
9506d57d 909({ \
9506d57d 910 rc = do_insn_fetch_bytes(_ctxt, _size); \
67cbc90d
TY		 911 if (rc != X86EMUL_CONTINUE) \
912 goto done; \
9506d57d 913 ctxt->_eip += (_size); \
17052f16
PB		 914 memcpy(_arr, ctxt->fetch.ptr, _size); \
915 ctxt->fetch.ptr += (_size); \
67cbc90d
TY		 916})
917
1e3c5cb0
RR		 918/*
919 * Given the 'reg' portion of a ModRM byte, and a register block, return a
920 * pointer into the block that addresses the relevant register.
921 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
922 */
dd856efa 923static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
aa9ac1a6 924 int byteop)
6aa8b732
AK		 925{
926 void *p;
aa9ac1a6 927 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
6aa8b732 928
6aa8b732 929 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
dd856efa
AK		 930 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
931 else
932 p = reg_rmw(ctxt, modrm_reg);
6aa8b732
AK		 933 return p;
934}
935
936static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 937 struct segmented_address addr,
6aa8b732
AK		 938 u16 *size, unsigned long *address, int op_bytes)
939{
940 int rc;
941
942 if (op_bytes == 2)
943 op_bytes = 3;
944 *address = 0;
3ca3ac4d 945 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 946 if (rc != X86EMUL_CONTINUE)
6aa8b732 947 return rc;
30b31ab6 948 addr.ea += 2;
3ca3ac4d 949 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 950 return rc;
951}
952
34b77652
AK		 953FASTOP2(add);
954FASTOP2(or);
955FASTOP2(adc);
956FASTOP2(sbb);
957FASTOP2(and);
958FASTOP2(sub);
959FASTOP2(xor);
960FASTOP2(cmp);
961FASTOP2(test);
962
b9fa409b
AK		 963FASTOP1SRC2(mul, mul_ex);
964FASTOP1SRC2(imul, imul_ex);
b8c0b6ae
AK		 965FASTOP1SRC2EX(div, div_ex);
966FASTOP1SRC2EX(idiv, idiv_ex);
b9fa409b 967
34b77652
AK		 968FASTOP3WCL(shld);
969FASTOP3WCL(shrd);
970
971FASTOP2W(imul);
972
973FASTOP1(not);
974FASTOP1(neg);
975FASTOP1(inc);
976FASTOP1(dec);
977
978FASTOP2CL(rol);
979FASTOP2CL(ror);
980FASTOP2CL(rcl);
981FASTOP2CL(rcr);
982FASTOP2CL(shl);
983FASTOP2CL(shr);
984FASTOP2CL(sar);
985
986FASTOP2W(bsf);
987FASTOP2W(bsr);
988FASTOP2W(bt);
989FASTOP2W(bts);
990FASTOP2W(btr);
991FASTOP2W(btc);
992
e47a5f5f
AK		 993FASTOP2(xadd);
994
5aca3722
NA		 995FASTOP2R(cmp, cmp_r);
996
900efe20
NA		 997static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
998{
999 /* If src is zero, do not writeback, but update flags */
1000 if (ctxt->src.val == 0)
1001 ctxt->dst.type = OP_NONE;
1002 return fastop(ctxt, em_bsf);
1003}
1004
1005static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1006{
1007 /* If src is zero, do not writeback, but update flags */
1008 if (ctxt->src.val == 0)
1009 ctxt->dst.type = OP_NONE;
1010 return fastop(ctxt, em_bsr);
1011}
1012
cb7390fe 1013static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
bbe9abbd 1014{
9ae9feba
AK		 1015 u8 rc;
1016 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
bbe9abbd 1017
9ae9feba 1018 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
3f0c3d0b 1019 asm("push %[flags]; popf; call *%[fastop]"
9ae9feba
AK		 1020 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1021 return rc;
bbe9abbd
NK		 1022}
1023
91ff3cb4
AK		 1024static void fetch_register_operand(struct operand *op)
1025{
1026 switch (op->bytes) {
1027 case 1:
1028 op->val = *(u8 *)op->addr.reg;
1029 break;
1030 case 2:
1031 op->val = *(u16 *)op->addr.reg;
1032 break;
1033 case 4:
1034 op->val = *(u32 *)op->addr.reg;
1035 break;
1036 case 8:
1037 op->val = *(u64 *)op->addr.reg;
1038 break;
1039 }
1040}
1041
1253791d
AK		 1042static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1043{
1044 ctxt->ops->get_fpu(ctxt);
1045 switch (reg) {
89a87c67
MK		 1046 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1047 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1048 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1049 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1050 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1051 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1052 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1053 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1253791d 1054#ifdef CONFIG_X86_64
89a87c67
MK		 1055 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1056 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1057 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1058 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1059 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1060 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1061 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1062 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1253791d
AK		 1063#endif
1064 default: BUG();
1065 }
1066 ctxt->ops->put_fpu(ctxt);
1067}
1068
1069static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1070 int reg)
1071{
1072 ctxt->ops->get_fpu(ctxt);
1073 switch (reg) {
89a87c67
MK		 1074 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1075 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1076 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1077 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1078 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1079 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1080 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1081 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1253791d 1082#ifdef CONFIG_X86_64
89a87c67
MK		 1083 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1084 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1085 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1086 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1087 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1088 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1089 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1090 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1253791d
AK		 1091#endif
1092 default: BUG();
1093 }
1094 ctxt->ops->put_fpu(ctxt);
1095}
1096
cbe2c9d3
AK		 1097static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1098{
1099 ctxt->ops->get_fpu(ctxt);
1100 switch (reg) {
1101 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1102 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1103 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1104 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1105 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1106 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1107 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1108 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1109 default: BUG();
1110 }
1111 ctxt->ops->put_fpu(ctxt);
1112}
1113
1114static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1115{
1116 ctxt->ops->get_fpu(ctxt);
1117 switch (reg) {
1118 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1119 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1120 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1121 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1122 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1123 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1124 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1125 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1126 default: BUG();
1127 }
1128 ctxt->ops->put_fpu(ctxt);
1129}
1130
045a282c
GN		 1131static int em_fninit(struct x86_emulate_ctxt *ctxt)
1132{
1133 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1134 return emulate_nm(ctxt);
1135
1136 ctxt->ops->get_fpu(ctxt);
1137 asm volatile("fninit");
1138 ctxt->ops->put_fpu(ctxt);
1139 return X86EMUL_CONTINUE;
1140}
1141
1142static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1143{
1144 u16 fcw;
1145
1146 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1147 return emulate_nm(ctxt);
1148
1149 ctxt->ops->get_fpu(ctxt);
1150 asm volatile("fnstcw %0": "+m"(fcw));
1151 ctxt->ops->put_fpu(ctxt);
1152
045a282c
GN		 1153 ctxt->dst.val = fcw;
1154
1155 return X86EMUL_CONTINUE;
1156}
1157
1158static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1159{
1160 u16 fsw;
1161
1162 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1163 return emulate_nm(ctxt);
1164
1165 ctxt->ops->get_fpu(ctxt);
1166 asm volatile("fnstsw %0": "+m"(fsw));
1167 ctxt->ops->put_fpu(ctxt);
1168
045a282c
GN		 1169 ctxt->dst.val = fsw;
1170
1171 return X86EMUL_CONTINUE;
1172}
1173
1253791d 1174static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
2adb5ad9 1175 struct operand *op)
3c118e24 1176{
9dac77fa 1177 unsigned reg = ctxt->modrm_reg;
33615aa9 1178
9dac77fa
AK		 1179 if (!(ctxt->d & ModRM))
1180 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1253791d 1181
9dac77fa 1182 if (ctxt->d & Sse) {
1253791d
AK		 1183 op->type = OP_XMM;
1184 op->bytes = 16;
1185 op->addr.xmm = reg;
1186 read_sse_reg(ctxt, &op->vec_val, reg);
1187 return;
1188 }
cbe2c9d3
AK		 1189 if (ctxt->d & Mmx) {
1190 reg &= 7;
1191 op->type = OP_MM;
1192 op->bytes = 8;
1193 op->addr.mm = reg;
1194 return;
1195 }
1253791d 1196
3c118e24 1197 op->type = OP_REG;
6d4d85ec
GN		 1198 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1199 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1200
91ff3cb4 1201 fetch_register_operand(op);
3c118e24
AK		 1202 op->orig_val = op->val;
1203}
1204
a6e3407b
AK		 1205static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1206{
1207 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1208 ctxt->modrm_seg = VCPU_SREG_SS;
1209}
1210
1c73ef66 1211static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1212 struct operand *op)
1c73ef66 1213{
1c73ef66 1214 u8 sib;
02357bdc 1215 int index_reg, base_reg, scale;
3e2815e9 1216 int rc = X86EMUL_CONTINUE;
2dbd0dd7 1217 ulong modrm_ea = 0;
1c73ef66 1218
02357bdc
BD		 1219 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1220 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1221 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1c73ef66 1222
02357bdc 1223 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
9dac77fa 1224 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
02357bdc 1225 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
9dac77fa 1226 ctxt->modrm_seg = VCPU_SREG_DS;
1c73ef66 1227
9b88ae99 1228 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
2dbd0dd7 1229 op->type = OP_REG;
9dac77fa 1230 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
8acb4207 1231 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
aa9ac1a6 1232 ctxt->d & ByteOp);
9dac77fa 1233 if (ctxt->d & Sse) {
1253791d
AK		 1234 op->type = OP_XMM;
1235 op->bytes = 16;
9dac77fa
AK		 1236 op->addr.xmm = ctxt->modrm_rm;
1237 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1253791d
AK		 1238 return rc;
1239 }
cbe2c9d3
AK		 1240 if (ctxt->d & Mmx) {
1241 op->type = OP_MM;
1242 op->bytes = 8;
bdc90722 1243 op->addr.mm = ctxt->modrm_rm & 7;
cbe2c9d3
AK		 1244 return rc;
1245 }
2dbd0dd7 1246 fetch_register_operand(op);
1c73ef66
AK		 1247 return rc;
1248 }
1249
2dbd0dd7
AK		 1250 op->type = OP_MEM;
1251
9dac77fa 1252 if (ctxt->ad_bytes == 2) {
dd856efa
AK		 1253 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1254 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1255 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1256 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1c73ef66
AK		 1257
1258 /* 16-bit ModR/M decode. */
9dac77fa 1259 switch (ctxt->modrm_mod) {
1c73ef66 1260 case 0:
9dac77fa 1261 if (ctxt->modrm_rm == 6)
e85a1085 1262 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1263 break;
1264 case 1:
e85a1085 1265 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1266 break;
1267 case 2:
e85a1085 1268 modrm_ea += insn_fetch(u16, ctxt);
1c73ef66
AK		 1269 break;
1270 }
9dac77fa 1271 switch (ctxt->modrm_rm) {
1c73ef66 1272 case 0:
2dbd0dd7 1273 modrm_ea += bx + si;
1c73ef66
AK		 1274 break;
1275 case 1:
2dbd0dd7 1276 modrm_ea += bx + di;
1c73ef66
AK		 1277 break;
1278 case 2:
2dbd0dd7 1279 modrm_ea += bp + si;
1c73ef66
AK		 1280 break;
1281 case 3:
2dbd0dd7 1282 modrm_ea += bp + di;
1c73ef66
AK		 1283 break;
1284 case 4:
2dbd0dd7 1285 modrm_ea += si;
1c73ef66
AK		 1286 break;
1287 case 5:
2dbd0dd7 1288 modrm_ea += di;
1c73ef66
AK		 1289 break;
1290 case 6:
9dac77fa 1291 if (ctxt->modrm_mod != 0)
2dbd0dd7 1292 modrm_ea += bp;
1c73ef66
AK		 1293 break;
1294 case 7:
2dbd0dd7 1295 modrm_ea += bx;
1c73ef66
AK		 1296 break;
1297 }
9dac77fa
AK		 1298 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1299 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1300 ctxt->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 1301 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 1302 } else {
1303 /* 32/64-bit ModR/M decode. */
9dac77fa 1304 if ((ctxt->modrm_rm & 7) == 4) {
e85a1085 1305 sib = insn_fetch(u8, ctxt);
1c73ef66
AK		 1306 index_reg |= (sib >> 3) & 7;
1307 base_reg |= sib & 7;
1308 scale = sib >> 6;
1309
9dac77fa 1310 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
e85a1085 1311 modrm_ea += insn_fetch(s32, ctxt);
a6e3407b 1312 else {
dd856efa 1313 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b 1314 adjust_modrm_seg(ctxt, base_reg);
ab708099
NA		 1315 /* Increment ESP on POP [ESP] */
1316 if ((ctxt->d & IncSP) &&
1317 base_reg == VCPU_REGS_RSP)
1318 modrm_ea += ctxt->op_bytes;
a6e3407b 1319 }
dc71d0f1 1320 if (index_reg != 4)
dd856efa 1321 modrm_ea += reg_read(ctxt, index_reg) << scale;
9dac77fa 1322 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
5b38ab87 1323 modrm_ea += insn_fetch(s32, ctxt);
84411d85 1324 if (ctxt->mode == X86EMUL_MODE_PROT64)
9dac77fa 1325 ctxt->rip_relative = 1;
a6e3407b
AK		 1326 } else {
1327 base_reg = ctxt->modrm_rm;
dd856efa 1328 modrm_ea += reg_read(ctxt, base_reg);
a6e3407b
AK		 1329 adjust_modrm_seg(ctxt, base_reg);
1330 }
9dac77fa 1331 switch (ctxt->modrm_mod) {
1c73ef66 1332 case 1:
e85a1085 1333 modrm_ea += insn_fetch(s8, ctxt);
1c73ef66
AK		 1334 break;
1335 case 2:
e85a1085 1336 modrm_ea += insn_fetch(s32, ctxt);
1c73ef66
AK		 1337 break;
1338 }
1339 }
90de84f5 1340 op->addr.mem.ea = modrm_ea;
41061cdb
BD		 1341 if (ctxt->ad_bytes != 8)
1342 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1343
1c73ef66
AK		 1344done:
1345 return rc;
1346}
1347
1348static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7 1349 struct operand *op)
1c73ef66 1350{
3e2815e9 1351 int rc = X86EMUL_CONTINUE;
1c73ef66 1352
2dbd0dd7 1353 op->type = OP_MEM;
9dac77fa 1354 switch (ctxt->ad_bytes) {
1c73ef66 1355 case 2:
e85a1085 1356 op->addr.mem.ea = insn_fetch(u16, ctxt);
1c73ef66
AK		 1357 break;
1358 case 4:
e85a1085 1359 op->addr.mem.ea = insn_fetch(u32, ctxt);
1c73ef66
AK		 1360 break;
1361 case 8:
e85a1085 1362 op->addr.mem.ea = insn_fetch(u64, ctxt);
1c73ef66
AK		 1363 break;
1364 }
1365done:
1366 return rc;
1367}
1368
9dac77fa 1369static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
35c843c4 1370{
7129eeca 1371 long sv = 0, mask;
35c843c4 1372
9dac77fa 1373 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
7dec5603 1374 mask = ~((long)ctxt->dst.bytes * 8 - 1);
35c843c4 1375
9dac77fa
AK		 1376 if (ctxt->src.bytes == 2)
1377 sv = (s16)ctxt->src.val & (s16)mask;
1378 else if (ctxt->src.bytes == 4)
1379 sv = (s32)ctxt->src.val & (s32)mask;
7dec5603
NA		 1380 else
1381 sv = (s64)ctxt->src.val & (s64)mask;
35c843c4 1382
1c1c35ae
NA		 1383 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1384 ctxt->dst.addr.mem.ea + (sv >> 3));
35c843c4 1385 }
ba7ff2b7
WY		 1386
1387 /* only subword offset */
9dac77fa 1388 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
35c843c4
WY		 1389}
1390
dde7e6d1 1391static int read_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1 1392 unsigned long addr, void *dest, unsigned size)
6aa8b732 1393{
dde7e6d1 1394 int rc;
9dac77fa 1395 struct read_cache *mc = &ctxt->mem_read;
6aa8b732 1396
f23b070e
XG		 1397 if (mc->pos < mc->end)
1398 goto read_cached;
6aa8b732 1399
f23b070e
XG		 1400 WARN_ON((mc->end + size) >= sizeof(mc->data));
1401
1402 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1403 &ctxt->exception);
1404 if (rc != X86EMUL_CONTINUE)
1405 return rc;
1406
1407 mc->end += size;
1408
1409read_cached:
1410 memcpy(dest, mc->data + mc->pos, size);
1411 mc->pos += size;
dde7e6d1
AK		 1412 return X86EMUL_CONTINUE;
1413}
6aa8b732 1414
3ca3ac4d
AK		 1415static int segmented_read(struct x86_emulate_ctxt *ctxt,
1416 struct segmented_address addr,
1417 void *data,
1418 unsigned size)
1419{
9fa088f4
AK		 1420 int rc;
1421 ulong linear;
1422
83b8795a 1423 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1424 if (rc != X86EMUL_CONTINUE)
1425 return rc;
7b105ca2 1426 return read_emulated(ctxt, linear, data, size);
3ca3ac4d
AK		 1427}
1428
1429static int segmented_write(struct x86_emulate_ctxt *ctxt,
1430 struct segmented_address addr,
1431 const void *data,
1432 unsigned size)
1433{
9fa088f4
AK		 1434 int rc;
1435 ulong linear;
1436
83b8795a 1437 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1438 if (rc != X86EMUL_CONTINUE)
1439 return rc;
0f65dd70
AK		 1440 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1441 &ctxt->exception);
3ca3ac4d
AK		 1442}
1443
1444static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1445 struct segmented_address addr,
1446 const void *orig_data, const void *data,
1447 unsigned size)
1448{
9fa088f4
AK		 1449 int rc;
1450 ulong linear;
1451
83b8795a 1452 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1453 if (rc != X86EMUL_CONTINUE)
1454 return rc;
0f65dd70
AK		 1455 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1456 size, &ctxt->exception);
3ca3ac4d
AK		 1457}
1458
dde7e6d1 1459static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1460 unsigned int size, unsigned short port,
1461 void *dest)
1462{
9dac77fa 1463 struct read_cache *rc = &ctxt->io_read;
b4c6abfe 1464
dde7e6d1 1465 if (rc->pos == rc->end) { /* refill pio read ahead */
dde7e6d1 1466 unsigned int in_page, n;
9dac77fa 1467 unsigned int count = ctxt->rep_prefix ?
dd856efa 1468 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
0efb0440 1469 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
dd856efa
AK		 1470 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1471 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
b55a8144 1472 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
dde7e6d1
AK		 1473 if (n == 0)
1474 n = 1;
1475 rc->pos = rc->end = 0;
7b105ca2 1476 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1477 return 0;
1478 rc->end = n * size;
6aa8b732
AK		 1479 }
1480
e6e39f04 1481 if (ctxt->rep_prefix && (ctxt->d & String) &&
0efb0440 1482 !(ctxt->eflags & X86_EFLAGS_DF)) {
b3356bf0
GN		 1483 ctxt->dst.data = rc->data + rc->pos;
1484 ctxt->dst.type = OP_MEM_STR;
1485 ctxt->dst.count = (rc->end - rc->pos) / size;
1486 rc->pos = rc->end;
1487 } else {
1488 memcpy(dest, rc->data + rc->pos, size);
1489 rc->pos += size;
1490 }
dde7e6d1
AK		 1491 return 1;
1492}
6aa8b732 1493
7f3d35fd
KW		 1494static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1495 u16 index, struct desc_struct *desc)
1496{
1497 struct desc_ptr dt;
1498 ulong addr;
1499
1500 ctxt->ops->get_idt(ctxt, &dt);
1501
1502 if (dt.size < index * 8 + 7)
1503 return emulate_gp(ctxt, index << 3 | 0x2);
1504
1505 addr = dt.address + index * 8;
1506 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1507 &ctxt->exception);
1508}
1509
dde7e6d1 1510static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1511 u16 selector, struct desc_ptr *dt)
1512{
0225fb50 1513 const struct x86_emulate_ops *ops = ctxt->ops;
2eedcac8 1514 u32 base3 = 0;
7b105ca2 1515
dde7e6d1
AK		 1516 if (selector & 1 << 2) {
1517 struct desc_struct desc;
1aa36616
AK		 1518 u16 sel;
1519
dde7e6d1 1520 memset (dt, 0, sizeof *dt);
2eedcac8
NA		 1521 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1522 VCPU_SREG_LDTR))
dde7e6d1 1523 return;
e09d082c 1524
dde7e6d1 1525 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
2eedcac8 1526 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
dde7e6d1 1527 } else
4bff1e86 1528 ops->get_gdt(ctxt, dt);
dde7e6d1 1529}
120df890 1530
edccda7c
NA		 1531static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1532 u16 selector, ulong *desc_addr_p)
dde7e6d1
AK		 1533{
1534 struct desc_ptr dt;
1535 u16 index = selector >> 3;
dde7e6d1 1536 ulong addr;
120df890 1537
7b105ca2 1538 get_descriptor_table_ptr(ctxt, selector, &dt);
120df890 1539
35d3d4a1
AK		 1540 if (dt.size < index * 8 + 7)
1541 return emulate_gp(ctxt, selector & 0xfffc);
e09d082c 1542
edccda7c
NA		 1543 addr = dt.address + index * 8;
1544
1545#ifdef CONFIG_X86_64
1546 if (addr >> 32 != 0) {
1547 u64 efer = 0;
1548
1549 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1550 if (!(efer & EFER_LMA))
1551 addr &= (u32)-1;
1552 }
1553#endif
1554
1555 *desc_addr_p = addr;
1556 return X86EMUL_CONTINUE;
1557}
1558
1559/* allowed just for 8 bytes segments */
1560static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1561 u16 selector, struct desc_struct *desc,
1562 ulong *desc_addr_p)
1563{
1564 int rc;
1565
1566 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1567 if (rc != X86EMUL_CONTINUE)
1568 return rc;
1569
1570 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
7b105ca2 1571 &ctxt->exception);
dde7e6d1 1572}
ef65c889 1573
dde7e6d1
AK		 1574/* allowed just for 8 bytes segments */
1575static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1576 u16 selector, struct desc_struct *desc)
1577{
edccda7c 1578 int rc;
dde7e6d1 1579 ulong addr;
6aa8b732 1580
edccda7c
NA		 1581 rc = get_descriptor_ptr(ctxt, selector, &addr);
1582 if (rc != X86EMUL_CONTINUE)
1583 return rc;
6aa8b732 1584
7b105ca2
TY		 1585 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1586 &ctxt->exception);
dde7e6d1 1587}
c7e75a3d 1588
2356aaeb 1589static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
d1442d85 1590 u16 selector, int seg, u8 cpl,
3dc4bc4f 1591 enum x86_transfer_type transfer,
d1442d85 1592 struct desc_struct *desc)
dde7e6d1 1593{
869be99c 1594 struct desc_struct seg_desc, old_desc;
2356aaeb 1595 u8 dpl, rpl;
dde7e6d1
AK		 1596 unsigned err_vec = GP_VECTOR;
1597 u32 err_code = 0;
1598 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
e919464b 1599 ulong desc_addr;
dde7e6d1 1600 int ret;
03ebebeb 1601 u16 dummy;
e37a75a1 1602 u32 base3 = 0;
69f55cb1 1603
dde7e6d1 1604 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1605
f8da94e9
KW		 1606 if (ctxt->mode == X86EMUL_MODE_REAL) {
1607 /* set real mode segment descriptor (keep limit etc. for
1608 * unreal mode) */
03ebebeb 1609 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
dde7e6d1 1610 set_desc_base(&seg_desc, selector << 4);
dde7e6d1 1611 goto load;
f8da94e9
KW		 1612 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1613 /* VM86 needs a clean new segment descriptor */
1614 set_desc_base(&seg_desc, selector << 4);
1615 set_desc_limit(&seg_desc, 0xffff);
1616 seg_desc.type = 3;
1617 seg_desc.p = 1;
1618 seg_desc.s = 1;
1619 seg_desc.dpl = 3;
1620 goto load;
dde7e6d1
AK		 1621 }
1622
79d5b4c3 1623 rpl = selector & 3;
79d5b4c3 1624
dde7e6d1
AK		 1625 /* TR should be in GDT only */
1626 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1627 goto exception;
1628
33ab9110
PB		 1629 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1630 if (null_selector) {
1631 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1632 goto exception;
1633
1634 if (seg == VCPU_SREG_SS) {
1635 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1636 goto exception;
1637
1638 /*
1639 * ctxt->ops->set_segment expects the CPL to be in
1640 * SS.DPL, so fake an expand-up 32-bit data segment.
1641 */
1642 seg_desc.type = 3;
1643 seg_desc.p = 1;
1644 seg_desc.s = 1;
1645 seg_desc.dpl = cpl;
1646 seg_desc.d = 1;
1647 seg_desc.g = 1;
1648 }
1649
1650 /* Skip all following checks */
dde7e6d1 1651 goto load;
33ab9110 1652 }
dde7e6d1 1653
e919464b 1654 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
dde7e6d1
AK		 1655 if (ret != X86EMUL_CONTINUE)
1656 return ret;
1657
1658 err_code = selector & 0xfffc;
3dc4bc4f
NA		 1659 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1660 GP_VECTOR;
dde7e6d1 1661
fc058680 1662 /* can't load system descriptor into segment selector */
3dc4bc4f
NA		 1663 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1664 if (transfer == X86_TRANSFER_CALL_JMP)
1665 return X86EMUL_UNHANDLEABLE;
dde7e6d1 1666 goto exception;
3dc4bc4f 1667 }
dde7e6d1
AK		 1668
1669 if (!seg_desc.p) {
1670 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1671 goto exception;
1672 }
1673
dde7e6d1 1674 dpl = seg_desc.dpl;
dde7e6d1
AK		 1675
1676 switch (seg) {
1677 case VCPU_SREG_SS:
1678 /*
1679 * segment is not a writable data segment or segment
1680 * selector's RPL != CPL or segment selector's RPL != CPL
1681 */
1682 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1683 goto exception;
6aa8b732 1684 break;
dde7e6d1
AK		 1685 case VCPU_SREG_CS:
1686 if (!(seg_desc.type & 8))
1687 goto exception;
1688
1689 if (seg_desc.type & 4) {
1690 /* conforming */
1691 if (dpl > cpl)
1692 goto exception;
1693 } else {
1694 /* nonconforming */
1695 if (rpl > cpl || dpl != cpl)
1696 goto exception;
1697 }
040c8dc8
NA		 1698 /* in long-mode d/b must be clear if l is set */
1699 if (seg_desc.d && seg_desc.l) {
1700 u64 efer = 0;
1701
1702 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1703 if (efer & EFER_LMA)
1704 goto exception;
1705 }
1706
dde7e6d1
AK		 1707 /* CS(RPL) <- CPL */
1708 selector = (selector & 0xfffc) | cpl;
6aa8b732 1709 break;
dde7e6d1
AK		 1710 case VCPU_SREG_TR:
1711 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1712 goto exception;
869be99c
AK		 1713 old_desc = seg_desc;
1714 seg_desc.type |= 2; /* busy */
1715 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1716 sizeof(seg_desc), &ctxt->exception);
1717 if (ret != X86EMUL_CONTINUE)
1718 return ret;
dde7e6d1
AK		 1719 break;
1720 case VCPU_SREG_LDTR:
1721 if (seg_desc.s || seg_desc.type != 2)
1722 goto exception;
1723 break;
1724 default: /* DS, ES, FS, or GS */
4e62417b 1725 /*
dde7e6d1
AK		 1726 * segment is not a data or readable code segment or
1727 * ((segment is a data or nonconforming code segment)
1728 * and (both RPL and CPL > DPL))
4e62417b 1729 */
dde7e6d1
AK		 1730 if ((seg_desc.type & 0xa) == 0x8 ||
1731 (((seg_desc.type & 0xc) != 0xc) &&
1732 (rpl > dpl && cpl > dpl)))
1733 goto exception;
6aa8b732 1734 break;
dde7e6d1
AK		 1735 }
1736
1737 if (seg_desc.s) {
1738 /* mark segment as accessed */
e2cefa74
NA		 1739 if (!(seg_desc.type & 1)) {
1740 seg_desc.type |= 1;
1741 ret = write_segment_descriptor(ctxt, selector,
1742 &seg_desc);
1743 if (ret != X86EMUL_CONTINUE)
1744 return ret;
1745 }
e37a75a1
NA		 1746 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1747 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1748 sizeof(base3), &ctxt->exception);
1749 if (ret != X86EMUL_CONTINUE)
1750 return ret;
9a9abf6b
NA		 1751 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1752 ((u64)base3 << 32)))
1753 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1754 }
1755load:
e37a75a1 1756 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
d1442d85
NA		 1757 if (desc)
1758 *desc = seg_desc;
dde7e6d1
AK		 1759 return X86EMUL_CONTINUE;
1760exception:
592f0858 1761 return emulate_exception(ctxt, err_vec, err_code, true);
dde7e6d1
AK		 1762}
1763
2356aaeb
PB		 1764static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1765 u16 selector, int seg)
1766{
1767 u8 cpl = ctxt->ops->cpl(ctxt);
33ab9110
PB		 1768
1769 /*
1770 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1771 * they can load it at CPL<3 (Intel's manual says only LSS can,
1772 * but it's wrong).
1773 *
1774 * However, the Intel manual says that putting IST=1/DPL=3 in
1775 * an interrupt gate will result in SS=3 (the AMD manual instead
1776 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1777 * and only forbid it here.
1778 */
1779 if (seg == VCPU_SREG_SS && selector == 3 &&
1780 ctxt->mode == X86EMUL_MODE_PROT64)
1781 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1782
3dc4bc4f
NA		 1783 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1784 X86_TRANSFER_NONE, NULL);
2356aaeb
PB		 1785}
1786
31be40b3
WY		 1787static void write_register_operand(struct operand *op)
1788{
6fd8e127 1789 return assign_register(op->addr.reg, op->val, op->bytes);
31be40b3
WY		 1790}
1791
fb32b1ed 1792static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
dde7e6d1 1793{
fb32b1ed 1794 switch (op->type) {
dde7e6d1 1795 case OP_REG:
fb32b1ed 1796 write_register_operand(op);
6aa8b732 1797 break;
dde7e6d1 1798 case OP_MEM:
9dac77fa 1799 if (ctxt->lock_prefix)
f5f87dfb
PB		 1800 return segmented_cmpxchg(ctxt,
1801 op->addr.mem,
1802 &op->orig_val,
1803 &op->val,
1804 op->bytes);
1805 else
1806 return segmented_write(ctxt,
fb32b1ed 1807 op->addr.mem,
fb32b1ed
AK		 1808 &op->val,
1809 op->bytes);
a682e354 1810 break;
b3356bf0 1811 case OP_MEM_STR:
f5f87dfb
PB		 1812 return segmented_write(ctxt,
1813 op->addr.mem,
1814 op->data,
1815 op->bytes * op->count);
b3356bf0 1816 break;
1253791d 1817 case OP_XMM:
fb32b1ed 1818 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1253791d 1819 break;
cbe2c9d3 1820 case OP_MM:
fb32b1ed 1821 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
cbe2c9d3 1822 break;
dde7e6d1
AK		 1823 case OP_NONE:
1824 /* no writeback */
414e6277 1825 break;
dde7e6d1 1826 default:
414e6277 1827 break;
6aa8b732 1828 }
dde7e6d1
AK		 1829 return X86EMUL_CONTINUE;
1830}
6aa8b732 1831
51ddff50 1832static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
dde7e6d1 1833{
4179bb02 1834 struct segmented_address addr;
0dc8d10f 1835
5ad105e5 1836 rsp_increment(ctxt, -bytes);
dd856efa 1837 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
4179bb02
TY		 1838 addr.seg = VCPU_SREG_SS;
1839
51ddff50
AK		 1840 return segmented_write(ctxt, addr, data, bytes);
1841}
1842
1843static int em_push(struct x86_emulate_ctxt *ctxt)
1844{
4179bb02 1845 /* Disable writeback. */
9dac77fa 1846 ctxt->dst.type = OP_NONE;
51ddff50 1847 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
dde7e6d1 1848}
69f55cb1 1849
dde7e6d1 1850static int emulate_pop(struct x86_emulate_ctxt *ctxt,
dde7e6d1
AK		 1851 void *dest, int len)
1852{
dde7e6d1 1853 int rc;
90de84f5 1854 struct segmented_address addr;
8b4caf66 1855
dd856efa 1856 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
90de84f5 1857 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1858 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1859 if (rc != X86EMUL_CONTINUE)
1860 return rc;
1861
5ad105e5 1862 rsp_increment(ctxt, len);
dde7e6d1 1863 return rc;
8b4caf66
LV		 1864}
1865
c54fe504
TY		 1866static int em_pop(struct x86_emulate_ctxt *ctxt)
1867{
9dac77fa 1868 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
c54fe504
TY		 1869}
1870
dde7e6d1 1871static int emulate_popf(struct x86_emulate_ctxt *ctxt,
7b105ca2 1872 void *dest, int len)
9de41573
GN		 1873{
1874 int rc;
dde7e6d1 1875 unsigned long val, change_mask;
0efb0440 1876 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 1877 int cpl = ctxt->ops->cpl(ctxt);
9de41573 1878
3b9be3bf 1879 rc = emulate_pop(ctxt, &val, len);
dde7e6d1
AK		 1880 if (rc != X86EMUL_CONTINUE)
1881 return rc;
9de41573 1882
0efb0440
NA		 1883 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1884 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1885 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1886 X86_EFLAGS_AC | X86_EFLAGS_ID;
9de41573 1887
dde7e6d1
AK		 1888 switch(ctxt->mode) {
1889 case X86EMUL_MODE_PROT64:
1890 case X86EMUL_MODE_PROT32:
1891 case X86EMUL_MODE_PROT16:
1892 if (cpl == 0)
0efb0440 1893 change_mask |= X86_EFLAGS_IOPL;
dde7e6d1 1894 if (cpl <= iopl)
0efb0440 1895 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1896 break;
1897 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1898 if (iopl < 3)
1899 return emulate_gp(ctxt, 0);
0efb0440 1900 change_mask |= X86_EFLAGS_IF;
dde7e6d1
AK		 1901 break;
1902 default: /* real mode */
0efb0440 1903 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
dde7e6d1 1904 break;
9de41573 1905 }
dde7e6d1
AK		 1906
1907 *(unsigned long *)dest =
1908 (ctxt->eflags & ~change_mask) | (val & change_mask);
1909
1910 return rc;
9de41573
GN		 1911}
1912
62aaa2f0
TY		 1913static int em_popf(struct x86_emulate_ctxt *ctxt)
1914{
9dac77fa
AK		 1915 ctxt->dst.type = OP_REG;
1916 ctxt->dst.addr.reg = &ctxt->eflags;
1917 ctxt->dst.bytes = ctxt->op_bytes;
1918 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
62aaa2f0
TY		 1919}
1920
612e89f0
AK		 1921static int em_enter(struct x86_emulate_ctxt *ctxt)
1922{
1923 int rc;
1924 unsigned frame_size = ctxt->src.val;
1925 unsigned nesting_level = ctxt->src2.val & 31;
dd856efa 1926 ulong rbp;
612e89f0
AK		 1927
1928 if (nesting_level)
1929 return X86EMUL_UNHANDLEABLE;
1930
dd856efa
AK		 1931 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1932 rc = push(ctxt, &rbp, stack_size(ctxt));
612e89f0
AK		 1933 if (rc != X86EMUL_CONTINUE)
1934 return rc;
dd856efa 1935 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
612e89f0 1936 stack_mask(ctxt));
dd856efa
AK		 1937 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1938 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
612e89f0
AK		 1939 stack_mask(ctxt));
1940 return X86EMUL_CONTINUE;
1941}
1942
f47cfa31
AK		 1943static int em_leave(struct x86_emulate_ctxt *ctxt)
1944{
dd856efa 1945 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
f47cfa31 1946 stack_mask(ctxt));
dd856efa 1947 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
f47cfa31
AK		 1948}
1949
1cd196ea 1950static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
7b262e90 1951{
1cd196ea
AK		 1952 int seg = ctxt->src2.val;
1953
9dac77fa 1954 ctxt->src.val = get_segment_selector(ctxt, seg);
0fcc207c
NA		 1955 if (ctxt->op_bytes == 4) {
1956 rsp_increment(ctxt, -2);
1957 ctxt->op_bytes = 2;
1958 }
7b262e90 1959
4487b3b4 1960 return em_push(ctxt);
7b262e90
GN		 1961}
1962
1cd196ea 1963static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
38ba30ba 1964{
1cd196ea 1965 int seg = ctxt->src2.val;
dde7e6d1
AK		 1966 unsigned long selector;
1967 int rc;
38ba30ba 1968
3313bc4e 1969 rc = emulate_pop(ctxt, &selector, 2);
dde7e6d1
AK		 1970 if (rc != X86EMUL_CONTINUE)
1971 return rc;
1972
a5457e7b
PB		 1973 if (ctxt->modrm_reg == VCPU_SREG_SS)
1974 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3313bc4e
NA		 1975 if (ctxt->op_bytes > 2)
1976 rsp_increment(ctxt, ctxt->op_bytes - 2);
a5457e7b 1977
7b105ca2 1978 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
dde7e6d1 1979 return rc;
38ba30ba
GN		 1980}
1981
b96a7fad 1982static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1983{
dd856efa 1984 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
dde7e6d1
AK		 1985 int rc = X86EMUL_CONTINUE;
1986 int reg = VCPU_REGS_RAX;
38ba30ba 1987
dde7e6d1
AK		 1988 while (reg <= VCPU_REGS_RDI) {
1989 (reg == VCPU_REGS_RSP) ?
dd856efa 1990 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
38ba30ba 1991
4487b3b4 1992 rc = em_push(ctxt);
dde7e6d1
AK		 1993 if (rc != X86EMUL_CONTINUE)
1994 return rc;
38ba30ba 1995
dde7e6d1 1996 ++reg;
38ba30ba 1997 }
38ba30ba 1998
dde7e6d1 1999 return rc;
38ba30ba
GN		 2000}
2001
62aaa2f0
TY		 2002static int em_pushf(struct x86_emulate_ctxt *ctxt)
2003{
0efb0440 2004 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
62aaa2f0
TY		 2005 return em_push(ctxt);
2006}
2007
b96a7fad 2008static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 2009{
dde7e6d1
AK		 2010 int rc = X86EMUL_CONTINUE;
2011 int reg = VCPU_REGS_RDI;
6fd8e127 2012 u32 val;
38ba30ba 2013
dde7e6d1
AK		 2014 while (reg >= VCPU_REGS_RAX) {
2015 if (reg == VCPU_REGS_RSP) {
5ad105e5 2016 rsp_increment(ctxt, ctxt->op_bytes);
dde7e6d1
AK		 2017 --reg;
2018 }
38ba30ba 2019
6fd8e127 2020 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
dde7e6d1
AK		 2021 if (rc != X86EMUL_CONTINUE)
2022 break;
6fd8e127 2023 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
dde7e6d1 2024 --reg;
38ba30ba 2025 }
dde7e6d1 2026 return rc;
38ba30ba
GN		 2027}
2028
dd856efa 2029static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56 2030{
0225fb50 2031 const struct x86_emulate_ops *ops = ctxt->ops;
5c56e1cf 2032 int rc;
6e154e56
MG		 2033 struct desc_ptr dt;
2034 gva_t cs_addr;
2035 gva_t eip_addr;
2036 u16 cs, eip;
6e154e56
MG		 2037
2038 /* TODO: Add limit checks */
9dac77fa 2039 ctxt->src.val = ctxt->eflags;
4487b3b4 2040 rc = em_push(ctxt);
5c56e1cf
AK		 2041 if (rc != X86EMUL_CONTINUE)
2042 return rc;
6e154e56 2043
0efb0440 2044 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
6e154e56 2045
9dac77fa 2046 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 2047 rc = em_push(ctxt);
5c56e1cf
AK		 2048 if (rc != X86EMUL_CONTINUE)
2049 return rc;
6e154e56 2050
9dac77fa 2051 ctxt->src.val = ctxt->_eip;
4487b3b4 2052 rc = em_push(ctxt);
5c56e1cf
AK		 2053 if (rc != X86EMUL_CONTINUE)
2054 return rc;
2055
4bff1e86 2056 ops->get_idt(ctxt, &dt);
6e154e56
MG		 2057
2058 eip_addr = dt.address + (irq << 2);
2059 cs_addr = dt.address + (irq << 2) + 2;
2060
0f65dd70 2061 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 2062 if (rc != X86EMUL_CONTINUE)
2063 return rc;
2064
0f65dd70 2065 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 2066 if (rc != X86EMUL_CONTINUE)
2067 return rc;
2068
7b105ca2 2069 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
6e154e56
MG		 2070 if (rc != X86EMUL_CONTINUE)
2071 return rc;
2072
9dac77fa 2073 ctxt->_eip = eip;
6e154e56
MG		 2074
2075 return rc;
2076}
2077
dd856efa
AK		 2078int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2079{
2080 int rc;
2081
2082 invalidate_registers(ctxt);
2083 rc = __emulate_int_real(ctxt, irq);
2084 if (rc == X86EMUL_CONTINUE)
2085 writeback_registers(ctxt);
2086 return rc;
2087}
2088
7b105ca2 2089static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
6e154e56
MG		 2090{
2091 switch(ctxt->mode) {
2092 case X86EMUL_MODE_REAL:
dd856efa 2093 return __emulate_int_real(ctxt, irq);
6e154e56
MG		 2094 case X86EMUL_MODE_VM86:
2095 case X86EMUL_MODE_PROT16:
2096 case X86EMUL_MODE_PROT32:
2097 case X86EMUL_MODE_PROT64:
2098 default:
2099 /* Protected mode interrupts unimplemented yet */
2100 return X86EMUL_UNHANDLEABLE;
2101 }
2102}
2103
7b105ca2 2104static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
38ba30ba 2105{
dde7e6d1
AK		 2106 int rc = X86EMUL_CONTINUE;
2107 unsigned long temp_eip = 0;
2108 unsigned long temp_eflags = 0;
2109 unsigned long cs = 0;
0efb0440
NA		 2110 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2111 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2112 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2113 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2114 X86_EFLAGS_AC | X86_EFLAGS_ID |
35fd68a3 2115 X86_EFLAGS_FIXED;
0efb0440
NA		 2116 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2117 X86_EFLAGS_VIP;
38ba30ba 2118
dde7e6d1 2119 /* TODO: Add stack limit check */
38ba30ba 2120
9dac77fa 2121 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
38ba30ba 2122
dde7e6d1
AK		 2123 if (rc != X86EMUL_CONTINUE)
2124 return rc;
38ba30ba 2125
35d3d4a1
AK		 2126 if (temp_eip & ~0xffff)
2127 return emulate_gp(ctxt, 0);
38ba30ba 2128
9dac77fa 2129 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
38ba30ba 2130
dde7e6d1
AK		 2131 if (rc != X86EMUL_CONTINUE)
2132 return rc;
38ba30ba 2133
9dac77fa 2134 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
38ba30ba 2135
dde7e6d1
AK		 2136 if (rc != X86EMUL_CONTINUE)
2137 return rc;
38ba30ba 2138
7b105ca2 2139 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
38ba30ba 2140
dde7e6d1
AK		 2141 if (rc != X86EMUL_CONTINUE)
2142 return rc;
38ba30ba 2143
9dac77fa 2144 ctxt->_eip = temp_eip;
38ba30ba 2145
9dac77fa 2146 if (ctxt->op_bytes == 4)
dde7e6d1 2147 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
9dac77fa 2148 else if (ctxt->op_bytes == 2) {
dde7e6d1
AK		 2149 ctxt->eflags &= ~0xffff;
2150 ctxt->eflags |= temp_eflags;
38ba30ba 2151 }
dde7e6d1
AK		 2152
2153 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
35fd68a3 2154 ctxt->eflags |= X86_EFLAGS_FIXED;
801806d9 2155 ctxt->ops->set_nmi_mask(ctxt, false);
dde7e6d1
AK		 2156
2157 return rc;
38ba30ba
GN		 2158}
2159
e01991e7 2160static int em_iret(struct x86_emulate_ctxt *ctxt)
c37eda13 2161{
dde7e6d1
AK		 2162 switch(ctxt->mode) {
2163 case X86EMUL_MODE_REAL:
7b105ca2 2164 return emulate_iret_real(ctxt);
dde7e6d1
AK		 2165 case X86EMUL_MODE_VM86:
2166 case X86EMUL_MODE_PROT16:
2167 case X86EMUL_MODE_PROT32:
2168 case X86EMUL_MODE_PROT64:
c37eda13 2169 default:
dde7e6d1
AK		 2170 /* iret from protected mode unimplemented yet */
2171 return X86EMUL_UNHANDLEABLE;
c37eda13 2172 }
c37eda13
WY		 2173}
2174
d2f62766
TY		 2175static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2176{
d2f62766 2177 int rc;
2117d539
RK		 2178 unsigned short sel;
2179 struct desc_struct new_desc;
d1442d85
NA		 2180 u8 cpl = ctxt->ops->cpl(ctxt);
2181
9dac77fa 2182 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
d2f62766 2183
3dc4bc4f
NA		 2184 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2185 X86_TRANSFER_CALL_JMP,
d1442d85 2186 &new_desc);
d2f62766
TY		 2187 if (rc != X86EMUL_CONTINUE)
2188 return rc;
2189
d50eaa18 2190 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2117d539
RK		 2191 /* Error handling is not implemented. */
2192 if (rc != X86EMUL_CONTINUE)
2193 return X86EMUL_UNHANDLEABLE;
2194
d1442d85 2195 return rc;
d2f62766
TY		 2196}
2197
f7784046 2198static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2199{
f7784046
NA		 2200 return assign_eip_near(ctxt, ctxt->src.val);
2201}
8cdbd2c9 2202
f7784046
NA		 2203static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2204{
2205 int rc;
2206 long int old_eip;
2207
2208 old_eip = ctxt->_eip;
2209 rc = assign_eip_near(ctxt, ctxt->src.val);
2210 if (rc != X86EMUL_CONTINUE)
2211 return rc;
2212 ctxt->src.val = old_eip;
2213 rc = em_push(ctxt);
4179bb02 2214 return rc;
8cdbd2c9
LV		 2215}
2216
e0dac408 2217static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 2218{
9dac77fa 2219 u64 old = ctxt->dst.orig_val64;
8cdbd2c9 2220
aaa05f24
NA		 2221 if (ctxt->dst.bytes == 16)
2222 return X86EMUL_UNHANDLEABLE;
2223
dd856efa
AK		 2224 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2225 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2226 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2227 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
0efb0440 2228 ctxt->eflags &= ~X86_EFLAGS_ZF;
8cdbd2c9 2229 } else {
dd856efa
AK		 2230 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2231 (u32) reg_read(ctxt, VCPU_REGS_RBX);
8cdbd2c9 2232
0efb0440 2233 ctxt->eflags |= X86_EFLAGS_ZF;
8cdbd2c9 2234 }
1b30eaa8 2235 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 2236}
2237
ebda02c2
TY		 2238static int em_ret(struct x86_emulate_ctxt *ctxt)
2239{
234f3ce4
NA		 2240 int rc;
2241 unsigned long eip;
2242
2243 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2244 if (rc != X86EMUL_CONTINUE)
2245 return rc;
2246
2247 return assign_eip_near(ctxt, eip);
ebda02c2
TY		 2248}
2249
e01991e7 2250static int em_ret_far(struct x86_emulate_ctxt *ctxt)
a77ab5ea 2251{
a77ab5ea 2252 int rc;
d1442d85 2253 unsigned long eip, cs;
9e8919ae 2254 int cpl = ctxt->ops->cpl(ctxt);
2117d539 2255 struct desc_struct new_desc;
a77ab5ea 2256
d1442d85 2257 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
1b30eaa8 2258 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2259 return rc;
9dac77fa 2260 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1b30eaa8 2261 if (rc != X86EMUL_CONTINUE)
a77ab5ea 2262 return rc;
9e8919ae
NA		 2263 /* Outer-privilege level return is not implemented */
2264 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2265 return X86EMUL_UNHANDLEABLE;
3dc4bc4f
NA		 2266 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2267 X86_TRANSFER_RET,
d1442d85
NA		 2268 &new_desc);
2269 if (rc != X86EMUL_CONTINUE)
2270 return rc;
d50eaa18 2271 rc = assign_eip_far(ctxt, eip, &new_desc);
2117d539
RK		 2272 /* Error handling is not implemented. */
2273 if (rc != X86EMUL_CONTINUE)
2274 return X86EMUL_UNHANDLEABLE;
2275
a77ab5ea
AK		 2276 return rc;
2277}
2278
3261107e
BR		 2279static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2280{
2281 int rc;
2282
2283 rc = em_ret_far(ctxt);
2284 if (rc != X86EMUL_CONTINUE)
2285 return rc;
2286 rsp_increment(ctxt, ctxt->src.val);
2287 return X86EMUL_CONTINUE;
2288}
2289
e940b5c2
TY		 2290static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2291{
2292 /* Save real source value, then compare EAX against destination. */
37c564f2
NA		 2293 ctxt->dst.orig_val = ctxt->dst.val;
2294 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
e940b5c2 2295 ctxt->src.orig_val = ctxt->src.val;
37c564f2 2296 ctxt->src.val = ctxt->dst.orig_val;
158de57f 2297 fastop(ctxt, em_cmp);
e940b5c2 2298
0efb0440 2299 if (ctxt->eflags & X86_EFLAGS_ZF) {
2fcf5c8a
NA		 2300 /* Success: write back to memory; no update of EAX */
2301 ctxt->src.type = OP_NONE;
e940b5c2
TY		 2302 ctxt->dst.val = ctxt->src.orig_val;
2303 } else {
2304 /* Failure: write the value we saw to EAX. */
2fcf5c8a
NA		 2305 ctxt->src.type = OP_REG;
2306 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2307 ctxt->src.val = ctxt->dst.orig_val;
2308 /* Create write-cycle to dest by writing the same value */
37c564f2 2309 ctxt->dst.val = ctxt->dst.orig_val;
e940b5c2
TY		 2310 }
2311 return X86EMUL_CONTINUE;
2312}
2313
d4b4325f 2314static int em_lseg(struct x86_emulate_ctxt *ctxt)
09b5f4d3 2315{
d4b4325f 2316 int seg = ctxt->src2.val;
09b5f4d3
WY		 2317 unsigned short sel;
2318 int rc;
2319
9dac77fa 2320 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
09b5f4d3 2321
7b105ca2 2322 rc = load_segment_descriptor(ctxt, sel, seg);
09b5f4d3
WY		 2323 if (rc != X86EMUL_CONTINUE)
2324 return rc;
2325
9dac77fa 2326 ctxt->dst.val = ctxt->src.val;
09b5f4d3
WY		 2327 return rc;
2328}
2329
660a5d51
PB		 2330static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2331{
2332 u32 eax, ebx, ecx, edx;
2333
2334 eax = 0x80000001;
2335 ecx = 0;
e911eb3b 2336 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
660a5d51
PB		 2337 return edx & bit(X86_FEATURE_LM);
2338}
2339
2340#define GET_SMSTATE(type, smbase, offset) \
2341 ({ \
2342 type __val; \
f40606b1
RK		 2343 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \
2344 sizeof(__val)); \
660a5d51
PB		 2345 if (r != X86EMUL_CONTINUE) \
2346 return X86EMUL_UNHANDLEABLE; \
2347 __val; \
2348 })
2349
2350static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2351{
2352 desc->g = (flags >> 23) & 1;
2353 desc->d = (flags >> 22) & 1;
2354 desc->l = (flags >> 21) & 1;
2355 desc->avl = (flags >> 20) & 1;
2356 desc->p = (flags >> 15) & 1;
2357 desc->dpl = (flags >> 13) & 3;
2358 desc->s = (flags >> 12) & 1;
2359 desc->type = (flags >> 8) & 15;
2360}
2361
2362static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2363{
2364 struct desc_struct desc;
2365 int offset;
2366 u16 selector;
2367
2368 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2369
2370 if (n < 3)
2371 offset = 0x7f84 + n * 12;
2372 else
2373 offset = 0x7f2c + (n - 3) * 12;
2374
2375 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2376 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2377 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2378 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2379 return X86EMUL_CONTINUE;
2380}
2381
2382static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2383{
2384 struct desc_struct desc;
2385 int offset;
2386 u16 selector;
2387 u32 base3;
2388
2389 offset = 0x7e00 + n * 16;
2390
2391 selector = GET_SMSTATE(u16, smbase, offset);
2392 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2393 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2394 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2395 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2396
2397 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2398 return X86EMUL_CONTINUE;
2399}
2400
2401static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2402 u64 cr0, u64 cr4)
2403{
2404 int bad;
2405
2406 /*
2407 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2408 * Then enable protected mode. However, PCID cannot be enabled
2409 * if EFER.LMA=0, so set it separately.
2410 */
2411 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2412 if (bad)
2413 return X86EMUL_UNHANDLEABLE;
2414
2415 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2416 if (bad)
2417 return X86EMUL_UNHANDLEABLE;
2418
2419 if (cr4 & X86_CR4_PCIDE) {
2420 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2421 if (bad)
2422 return X86EMUL_UNHANDLEABLE;
2423 }
2424
2425 return X86EMUL_CONTINUE;
2426}
2427
2428static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2429{
2430 struct desc_struct desc;
2431 struct desc_ptr dt;
2432 u16 selector;
2433 u32 val, cr0, cr4;
2434 int i;
2435
2436 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
2437 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8));
2438 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2439 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2440
2441 for (i = 0; i < 8; i++)
2442 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2443
2444 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2445 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2446 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2447 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2448
2449 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2450 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2451 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2452 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2453 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2454
2455 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2456 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2457 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2458 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2459 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2460
2461 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2462 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2463 ctxt->ops->set_gdt(ctxt, &dt);
2464
2465 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2466 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2467 ctxt->ops->set_idt(ctxt, &dt);
2468
2469 for (i = 0; i < 6; i++) {
2470 int r = rsm_load_seg_32(ctxt, smbase, i);
2471 if (r != X86EMUL_CONTINUE)
2472 return r;
2473 }
2474
2475 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2476
2477 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2478
2479 return rsm_enter_protected_mode(ctxt, cr0, cr4);
2480}
2481
2482static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2483{
2484 struct desc_struct desc;
2485 struct desc_ptr dt;
2486 u64 val, cr0, cr4;
2487 u32 base3;
2488 u16 selector;
b10d92a5 2489 int i, r;
660a5d51
PB		 2490
2491 for (i = 0; i < 16; i++)
2492 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2493
2494 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2495 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2496
2497 val = GET_SMSTATE(u32, smbase, 0x7f68);
2498 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2499 val = GET_SMSTATE(u32, smbase, 0x7f60);
2500 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2501
2502 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
2503 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50));
2504 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2505 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2506 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2507 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2508
2509 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2510 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2511 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2512 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2513 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2514 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2515
2516 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2517 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2518 ctxt->ops->set_idt(ctxt, &dt);
2519
2520 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2521 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2522 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2523 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2524 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2525 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2526
2527 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2528 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2529 ctxt->ops->set_gdt(ctxt, &dt);
2530
b10d92a5
PB		 2531 r = rsm_enter_protected_mode(ctxt, cr0, cr4);
2532 if (r != X86EMUL_CONTINUE)
2533 return r;
2534
660a5d51 2535 for (i = 0; i < 6; i++) {
b10d92a5 2536 r = rsm_load_seg_64(ctxt, smbase, i);
660a5d51
PB		 2537 if (r != X86EMUL_CONTINUE)
2538 return r;
2539 }
2540
b10d92a5 2541 return X86EMUL_CONTINUE;
660a5d51
PB		 2542}
2543
64d60670
PB		 2544static int em_rsm(struct x86_emulate_ctxt *ctxt)
2545{
660a5d51
PB		 2546 unsigned long cr0, cr4, efer;
2547 u64 smbase;
2548 int ret;
2549
6ed071f0 2550 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
64d60670
PB		 2551 return emulate_ud(ctxt);
2552
660a5d51
PB		 2553 /*
2554 * Get back to real mode, to prepare a safe state in which to load
89651a3d
PB		 2555 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2556 * supports long mode.
660a5d51 2557 */
89651a3d
PB		 2558 cr4 = ctxt->ops->get_cr(ctxt, 4);
2559 if (emulator_has_longmode(ctxt)) {
2560 struct desc_struct cs_desc;
2561
2562 /* Zero CR4.PCIDE before CR0.PG. */
2563 if (cr4 & X86_CR4_PCIDE) {
2564 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2565 cr4 &= ~X86_CR4_PCIDE;
2566 }
2567
2568 /* A 32-bit code segment is required to clear EFER.LMA. */
2569 memset(&cs_desc, 0, sizeof(cs_desc));
2570 cs_desc.type = 0xb;
2571 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2572 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2573 }
2574
2575 /* For the 64-bit case, this will clear EFER.LMA. */
660a5d51
PB		 2576 cr0 = ctxt->ops->get_cr(ctxt, 0);
2577 if (cr0 & X86_CR0_PE)
2578 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
89651a3d
PB		 2579
2580 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
660a5d51
PB		 2581 if (cr4 & X86_CR4_PAE)
2582 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
89651a3d
PB		 2583
2584 /* And finally go back to 32-bit mode. */
660a5d51
PB		 2585 efer = 0;
2586 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2587
2588 smbase = ctxt->ops->get_smbase(ctxt);
2589 if (emulator_has_longmode(ctxt))
2590 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2591 else
2592 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2593
2594 if (ret != X86EMUL_CONTINUE) {
2595 /* FIXME: should triple fault */
2596 return X86EMUL_UNHANDLEABLE;
2597 }
2598
6ed071f0 2599 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
660a5d51
PB		 2600 ctxt->ops->set_nmi_mask(ctxt, false);
2601
6ed071f0
LP		 2602 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2603 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
660a5d51 2604 return X86EMUL_CONTINUE;
64d60670
PB		 2605}
2606
7b105ca2 2607static void
e66bb2cc 2608setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
7b105ca2 2609 struct desc_struct *cs, struct desc_struct *ss)
e66bb2cc 2610{
e66bb2cc 2611 cs->l = 0; /* will be adjusted later */
79168fd1 2612 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 2613 cs->g = 1; /* 4kb granularity */
79168fd1 2614 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2615 cs->type = 0x0b; /* Read, Execute, Accessed */
2616 cs->s = 1;
2617 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 2618 cs->p = 1;
2619 cs->d = 1;
99245b50 2620 cs->avl = 0;
e66bb2cc 2621
79168fd1
GN		 2622 set_desc_base(ss, 0); /* flat segment */
2623 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 2624 ss->g = 1; /* 4kb granularity */
2625 ss->s = 1;
2626 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 2627 ss->d = 1; /* 32bit stack segment */
e66bb2cc 2628 ss->dpl = 0;
79168fd1 2629 ss->p = 1;
99245b50
GN		 2630 ss->l = 0;
2631 ss->avl = 0;
e66bb2cc
AP		 2632}
2633
1a18a69b
AK		 2634static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2635{
2636 u32 eax, ebx, ecx, edx;
2637
2638 eax = ecx = 0;
e911eb3b 2639 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a 2640 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
1a18a69b
AK		 2641 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2642 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2643}
2644
c2226fc9
SB		 2645static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2646{
0225fb50 2647 const struct x86_emulate_ops *ops = ctxt->ops;
c2226fc9
SB		 2648 u32 eax, ebx, ecx, edx;
2649
2650 /*
2651 * syscall should always be enabled in longmode - so only become
2652 * vendor specific (cpuid) if other modes are active...
2653 */
2654 if (ctxt->mode == X86EMUL_MODE_PROT64)
2655 return true;
2656
2657 eax = 0x00000000;
2658 ecx = 0x00000000;
e911eb3b 2659 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
0017f93a
AK		 2660 /*
2661 * Intel ("GenuineIntel")
2662 * remark: Intel CPUs only support "syscall" in 64bit
2663 * longmode. Also an 64bit guest with a
2664 * 32bit compat-app running will #UD !! While this
2665 * behaviour can be fixed (by emulating) into AMD
2666 * response - CPUs of AMD can't behave like Intel.
2667 */
2668 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2669 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2670 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2671 return false;
2672
2673 /* AMD ("AuthenticAMD") */
2674 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2675 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2676 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2677 return true;
2678
2679 /* AMD ("AMDisbetter!") */
2680 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2681 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2682 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2683 return true;
c2226fc9
SB		 2684
2685 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2686 return false;
2687}
2688
e01991e7 2689static int em_syscall(struct x86_emulate_ctxt *ctxt)
e66bb2cc 2690{
0225fb50 2691 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2692 struct desc_struct cs, ss;
e66bb2cc 2693 u64 msr_data;
79168fd1 2694 u16 cs_sel, ss_sel;
c2ad2bb3 2695 u64 efer = 0;
e66bb2cc
AP		 2696
2697 /* syscall is not available in real mode */
2e901c4c 2698 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2699 ctxt->mode == X86EMUL_MODE_VM86)
2700 return emulate_ud(ctxt);
e66bb2cc 2701
c2226fc9
SB		 2702 if (!(em_syscall_is_enabled(ctxt)))
2703 return emulate_ud(ctxt);
2704
c2ad2bb3 2705 ops->get_msr(ctxt, MSR_EFER, &efer);
7b105ca2 2706 setup_syscalls_segments(ctxt, &cs, &ss);
e66bb2cc 2707
c2226fc9
SB		 2708 if (!(efer & EFER_SCE))
2709 return emulate_ud(ctxt);
2710
717746e3 2711 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 2712 msr_data >>= 32;
79168fd1
GN		 2713 cs_sel = (u16)(msr_data & 0xfffc);
2714 ss_sel = (u16)(msr_data + 8);
e66bb2cc 2715
c2ad2bb3 2716 if (efer & EFER_LMA) {
79168fd1 2717 cs.d = 0;
e66bb2cc
AP		 2718 cs.l = 1;
2719 }
1aa36616
AK		 2720 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2721 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc 2722
dd856efa 2723 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
c2ad2bb3 2724 if (efer & EFER_LMA) {
e66bb2cc 2725#ifdef CONFIG_X86_64
6c6cb69b 2726 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
e66bb2cc 2727
717746e3 2728 ops->get_msr(ctxt,
3fb1b5db
GN		 2729 ctxt->mode == X86EMUL_MODE_PROT64 ?
2730 MSR_LSTAR : MSR_CSTAR, &msr_data);
9dac77fa 2731 ctxt->_eip = msr_data;
e66bb2cc 2732
717746e3 2733 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
6c6cb69b 2734 ctxt->eflags &= ~msr_data;
35fd68a3 2735 ctxt->eflags |= X86_EFLAGS_FIXED;
e66bb2cc
AP		 2736#endif
2737 } else {
2738 /* legacy mode */
717746e3 2739 ops->get_msr(ctxt, MSR_STAR, &msr_data);
9dac77fa 2740 ctxt->_eip = (u32)msr_data;
e66bb2cc 2741
0efb0440 2742 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
e66bb2cc
AP		 2743 }
2744
c8401dda 2745 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
e54cfa97 2746 return X86EMUL_CONTINUE;
e66bb2cc
AP		 2747}
2748
e01991e7 2749static int em_sysenter(struct x86_emulate_ctxt *ctxt)
8c604352 2750{
0225fb50 2751 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2752 struct desc_struct cs, ss;
8c604352 2753 u64 msr_data;
79168fd1 2754 u16 cs_sel, ss_sel;
c2ad2bb3 2755 u64 efer = 0;
8c604352 2756
7b105ca2 2757 ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 2758 /* inject #GP if in real mode */
35d3d4a1
AK		 2759 if (ctxt->mode == X86EMUL_MODE_REAL)
2760 return emulate_gp(ctxt, 0);
8c604352 2761
1a18a69b
AK		 2762 /*
2763 * Not recognized on AMD in compat mode (but is recognized in legacy
2764 * mode).
2765 */
f3747379 2766 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
1a18a69b
AK		 2767 && !vendor_intel(ctxt))
2768 return emulate_ud(ctxt);
2769
b2c9d43e 2770 /* sysenter/sysexit have not been tested in 64bit mode. */
35d3d4a1 2771 if (ctxt->mode == X86EMUL_MODE_PROT64)
b2c9d43e 2772 return X86EMUL_UNHANDLEABLE;
8c604352 2773
7b105ca2 2774 setup_syscalls_segments(ctxt, &cs, &ss);
8c604352 2775
717746e3 2776 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
f3747379
NA		 2777 if ((msr_data & 0xfffc) == 0x0)
2778 return emulate_gp(ctxt, 0);
8c604352 2779
0efb0440 2780 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
b32a9918 2781 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
79168fd1 2782 ss_sel = cs_sel + 8;
f3747379 2783 if (efer & EFER_LMA) {
79168fd1 2784 cs.d = 0;
8c604352
AP		 2785 cs.l = 1;
2786 }
2787
1aa36616
AK		 2788 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2789 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 2790
717746e3 2791 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
f3747379 2792 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
8c604352 2793
717746e3 2794 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
f3747379
NA		 2795 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2796 (u32)msr_data;
8c604352 2797
e54cfa97 2798 return X86EMUL_CONTINUE;
8c604352
AP		 2799}
2800
e01991e7 2801static int em_sysexit(struct x86_emulate_ctxt *ctxt)
4668f050 2802{
0225fb50 2803 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2804 struct desc_struct cs, ss;
234f3ce4 2805 u64 msr_data, rcx, rdx;
4668f050 2806 int usermode;
1249b96e 2807 u16 cs_sel = 0, ss_sel = 0;
4668f050 2808
a0044755
GN		 2809 /* inject #GP if in real mode or Virtual 8086 mode */
2810 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2811 ctxt->mode == X86EMUL_MODE_VM86)
2812 return emulate_gp(ctxt, 0);
4668f050 2813
7b105ca2 2814 setup_syscalls_segments(ctxt, &cs, &ss);
4668f050 2815
9dac77fa 2816 if ((ctxt->rex_prefix & 0x8) != 0x0)
4668f050
AP		 2817 usermode = X86EMUL_MODE_PROT64;
2818 else
2819 usermode = X86EMUL_MODE_PROT32;
2820
234f3ce4
NA		 2821 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2822 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2823
4668f050
AP		 2824 cs.dpl = 3;
2825 ss.dpl = 3;
717746e3 2826 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2827 switch (usermode) {
2828 case X86EMUL_MODE_PROT32:
79168fd1 2829 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2830 if ((msr_data & 0xfffc) == 0x0)
2831 return emulate_gp(ctxt, 0);
79168fd1 2832 ss_sel = (u16)(msr_data + 24);
bf0b682c
NA		 2833 rcx = (u32)rcx;
2834 rdx = (u32)rdx;
4668f050
AP		 2835 break;
2836 case X86EMUL_MODE_PROT64:
79168fd1 2837 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2838 if (msr_data == 0x0)
2839 return emulate_gp(ctxt, 0);
79168fd1
GN		 2840 ss_sel = cs_sel + 8;
2841 cs.d = 0;
4668f050 2842 cs.l = 1;
234f3ce4
NA		 2843 if (is_noncanonical_address(rcx) ||
2844 is_noncanonical_address(rdx))
2845 return emulate_gp(ctxt, 0);
4668f050
AP		 2846 break;
2847 }
b32a9918
NA		 2848 cs_sel |= SEGMENT_RPL_MASK;
2849 ss_sel |= SEGMENT_RPL_MASK;
4668f050 2850
1aa36616
AK		 2851 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2852 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2853
234f3ce4
NA		 2854 ctxt->_eip = rdx;
2855 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
4668f050 2856
e54cfa97 2857 return X86EMUL_CONTINUE;
4668f050
AP		 2858}
2859
7b105ca2 2860static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
f850e2e6
GN		 2861{
2862 int iopl;
2863 if (ctxt->mode == X86EMUL_MODE_REAL)
2864 return false;
2865 if (ctxt->mode == X86EMUL_MODE_VM86)
2866 return true;
0efb0440 2867 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
7b105ca2 2868 return ctxt->ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2869}
2870
2871static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2872 u16 port, u16 len)
2873{
0225fb50 2874 const struct x86_emulate_ops *ops = ctxt->ops;
79168fd1 2875 struct desc_struct tr_seg;
5601d05b 2876 u32 base3;
f850e2e6 2877 int r;
1aa36616 2878 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2879 unsigned mask = (1 << len) - 1;
5601d05b 2880 unsigned long base;
f850e2e6 2881
1aa36616 2882 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2883 if (!tr_seg.p)
f850e2e6 2884 return false;
79168fd1 2885 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2886 return false;
5601d05b
GN		 2887 base = get_desc_base(&tr_seg);
2888#ifdef CONFIG_X86_64
2889 base |= ((u64)base3) << 32;
2890#endif
0f65dd70 2891 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2892 if (r != X86EMUL_CONTINUE)
2893 return false;
79168fd1 2894 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2895 return false;
0f65dd70 2896 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2897 if (r != X86EMUL_CONTINUE)
2898 return false;
2899 if ((perm >> bit_idx) & mask)
2900 return false;
2901 return true;
2902}
2903
2904static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
f850e2e6
GN		 2905 u16 port, u16 len)
2906{
4fc40f07
GN		 2907 if (ctxt->perm_ok)
2908 return true;
2909
7b105ca2
TY		 2910 if (emulator_bad_iopl(ctxt))
2911 if (!emulator_io_port_access_allowed(ctxt, port, len))
f850e2e6 2912 return false;
4fc40f07
GN		 2913
2914 ctxt->perm_ok = true;
2915
f850e2e6
GN		 2916 return true;
2917}
2918
428e3d08
NA		 2919static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2920{
2921 /*
2922 * Intel CPUs mask the counter and pointers in quite strange
2923 * manner when ECX is zero due to REP-string optimizations.
2924 */
2925#ifdef CONFIG_X86_64
2926 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2927 return;
2928
2929 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2930
2931 switch (ctxt->b) {
2932 case 0xa4: /* movsb */
2933 case 0xa5: /* movsd/w */
2934 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2935 /* fall through */
2936 case 0xaa: /* stosb */
2937 case 0xab: /* stosd/w */
2938 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2939 }
2940#endif
2941}
2942
38ba30ba 2943static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2944 struct tss_segment_16 *tss)
2945{
9dac77fa 2946 tss->ip = ctxt->_eip;
38ba30ba 2947 tss->flag = ctxt->eflags;
dd856efa
AK		 2948 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2949 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2950 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2951 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2952 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2953 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2954 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2955 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 2956
1aa36616
AK		 2957 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2958 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2959 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2960 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2961 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2962}
2963
2964static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 2965 struct tss_segment_16 *tss)
2966{
38ba30ba 2967 int ret;
2356aaeb 2968 u8 cpl;
38ba30ba 2969
9dac77fa 2970 ctxt->_eip = tss->ip;
38ba30ba 2971 ctxt->eflags = tss->flag | 2;
dd856efa
AK		 2972 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2973 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2974 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2975 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2976 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2977 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2978 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2979 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
38ba30ba
GN		 2980
2981 /*
2982 * SDM says that segment selectors are loaded before segment
2983 * descriptors
2984 */
1aa36616
AK		 2985 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2986 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2987 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2988 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2989 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba 2990
2356aaeb
PB		 2991 cpl = tss->cs & 3;
2992
38ba30ba 2993 /*
fc058680 2994 * Now load segment descriptors. If fault happens at this stage
38ba30ba
GN		 2995 * it is handled in a context of new task
2996 */
d1442d85 2997 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3dc4bc4f 2998 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 2999 if (ret != X86EMUL_CONTINUE)
3000 return ret;
d1442d85 3001 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3002 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3003 if (ret != X86EMUL_CONTINUE)
3004 return ret;
d1442d85 3005 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3006 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3007 if (ret != X86EMUL_CONTINUE)
3008 return ret;
d1442d85 3009 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3010 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3011 if (ret != X86EMUL_CONTINUE)
3012 return ret;
d1442d85 3013 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3014 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3015 if (ret != X86EMUL_CONTINUE)
3016 return ret;
3017
3018 return X86EMUL_CONTINUE;
3019}
3020
3021static int task_switch_16(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3022 u16 tss_selector, u16 old_tss_sel,
3023 ulong old_tss_base, struct desc_struct *new_desc)
3024{
0225fb50 3025 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3026 struct tss_segment_16 tss_seg;
3027 int ret;
bcc55cba 3028 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 3029
0f65dd70 3030 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3031 &ctxt->exception);
db297e3d 3032 if (ret != X86EMUL_CONTINUE)
38ba30ba 3033 return ret;
38ba30ba 3034
7b105ca2 3035 save_state_to_tss16(ctxt, &tss_seg);
38ba30ba 3036
0f65dd70 3037 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3038 &ctxt->exception);
db297e3d 3039 if (ret != X86EMUL_CONTINUE)
38ba30ba 3040 return ret;
38ba30ba 3041
0f65dd70 3042 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3043 &ctxt->exception);
db297e3d 3044 if (ret != X86EMUL_CONTINUE)
38ba30ba 3045 return ret;
38ba30ba
GN		 3046
3047 if (old_tss_sel != 0xffff) {
3048 tss_seg.prev_task_link = old_tss_sel;
3049
0f65dd70 3050 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3051 &tss_seg.prev_task_link,
3052 sizeof tss_seg.prev_task_link,
0f65dd70 3053 &ctxt->exception);
db297e3d 3054 if (ret != X86EMUL_CONTINUE)
38ba30ba 3055 return ret;
38ba30ba
GN		 3056 }
3057
7b105ca2 3058 return load_state_from_tss16(ctxt, &tss_seg);
38ba30ba
GN		 3059}
3060
3061static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3062 struct tss_segment_32 *tss)
3063{
5c7411e2 3064 /* CR3 and ldt selector are not saved intentionally */
9dac77fa 3065 tss->eip = ctxt->_eip;
38ba30ba 3066 tss->eflags = ctxt->eflags;
dd856efa
AK		 3067 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3068 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3069 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3070 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3071 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3072 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3073 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3074 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
38ba30ba 3075
1aa36616
AK		 3076 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3077 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3078 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3079 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3080 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3081 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
38ba30ba
GN		 3082}
3083
3084static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3085 struct tss_segment_32 *tss)
3086{
38ba30ba 3087 int ret;
2356aaeb 3088 u8 cpl;
38ba30ba 3089
7b105ca2 3090 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 3091 return emulate_gp(ctxt, 0);
9dac77fa 3092 ctxt->_eip = tss->eip;
38ba30ba 3093 ctxt->eflags = tss->eflags | 2;
4cee4798
KW		 3094
3095 /* General purpose registers */
dd856efa
AK		 3096 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3097 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3098 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3099 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3100 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3101 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3102 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3103 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
38ba30ba
GN		 3104
3105 /*
3106 * SDM says that segment selectors are loaded before segment
2356aaeb
PB		 3107 * descriptors. This is important because CPL checks will
3108 * use CS.RPL.
38ba30ba 3109 */
1aa36616
AK		 3110 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3111 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3112 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3113 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3114 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3115 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3116 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba 3117
4cee4798
KW		 3118 /*
3119 * If we're switching between Protected Mode and VM86, we need to make
3120 * sure to update the mode before loading the segment descriptors so
3121 * that the selectors are interpreted correctly.
4cee4798 3122 */
2356aaeb 3123 if (ctxt->eflags & X86_EFLAGS_VM) {
4cee4798 3124 ctxt->mode = X86EMUL_MODE_VM86;
2356aaeb
PB		 3125 cpl = 3;
3126 } else {
4cee4798 3127 ctxt->mode = X86EMUL_MODE_PROT32;
2356aaeb
PB		 3128 cpl = tss->cs & 3;
3129 }
4cee4798 3130
38ba30ba
GN		 3131 /*
3132 * Now load segment descriptors. If fault happenes at this stage
3133 * it is handled in a context of new task
3134 */
d1442d85 3135 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3dc4bc4f 3136 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3137 if (ret != X86EMUL_CONTINUE)
3138 return ret;
d1442d85 3139 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3dc4bc4f 3140 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3141 if (ret != X86EMUL_CONTINUE)
3142 return ret;
d1442d85 3143 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3dc4bc4f 3144 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3145 if (ret != X86EMUL_CONTINUE)
3146 return ret;
d1442d85 3147 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3dc4bc4f 3148 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3149 if (ret != X86EMUL_CONTINUE)
3150 return ret;
d1442d85 3151 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3dc4bc4f 3152 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3153 if (ret != X86EMUL_CONTINUE)
3154 return ret;
d1442d85 3155 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3dc4bc4f 3156 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba
GN		 3157 if (ret != X86EMUL_CONTINUE)
3158 return ret;
d1442d85 3159 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3dc4bc4f 3160 X86_TRANSFER_TASK_SWITCH, NULL);
38ba30ba 3161
2f729b10 3162 return ret;
38ba30ba
GN		 3163}
3164
3165static int task_switch_32(struct x86_emulate_ctxt *ctxt,
38ba30ba
GN		 3166 u16 tss_selector, u16 old_tss_sel,
3167 ulong old_tss_base, struct desc_struct *new_desc)
3168{
0225fb50 3169 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3170 struct tss_segment_32 tss_seg;
3171 int ret;
bcc55cba 3172 u32 new_tss_base = get_desc_base(new_desc);
5c7411e2
NA		 3173 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3174 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
38ba30ba 3175
0f65dd70 3176 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3177 &ctxt->exception);
db297e3d 3178 if (ret != X86EMUL_CONTINUE)
38ba30ba 3179 return ret;
38ba30ba 3180
7b105ca2 3181 save_state_to_tss32(ctxt, &tss_seg);
38ba30ba 3182
5c7411e2
NA		 3183 /* Only GP registers and segment selectors are saved */
3184 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3185 ldt_sel_offset - eip_offset, &ctxt->exception);
db297e3d 3186 if (ret != X86EMUL_CONTINUE)
38ba30ba 3187 return ret;
38ba30ba 3188
0f65dd70 3189 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 3190 &ctxt->exception);
db297e3d 3191 if (ret != X86EMUL_CONTINUE)
38ba30ba 3192 return ret;
38ba30ba
GN		 3193
3194 if (old_tss_sel != 0xffff) {
3195 tss_seg.prev_task_link = old_tss_sel;
3196
0f65dd70 3197 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 3198 &tss_seg.prev_task_link,
3199 sizeof tss_seg.prev_task_link,
0f65dd70 3200 &ctxt->exception);
db297e3d 3201 if (ret != X86EMUL_CONTINUE)
38ba30ba 3202 return ret;
38ba30ba
GN		 3203 }
3204
7b105ca2 3205 return load_state_from_tss32(ctxt, &tss_seg);
38ba30ba
GN		 3206}
3207
3208static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3209 u16 tss_selector, int idt_index, int reason,
e269fb21 3210 bool has_error_code, u32 error_code)
38ba30ba 3211{
0225fb50 3212 const struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 3213 struct desc_struct curr_tss_desc, next_tss_desc;
3214 int ret;
1aa36616 3215 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 3216 ulong old_tss_base =
4bff1e86 3217 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 3218 u32 desc_limit;
3db176d5 3219 ulong desc_addr, dr7;
38ba30ba
GN		 3220
3221 /* FIXME: old_tss_base == ~0 ? */
3222
e919464b 3223 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
38ba30ba
GN		 3224 if (ret != X86EMUL_CONTINUE)
3225 return ret;
e919464b 3226 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
38ba30ba
GN		 3227 if (ret != X86EMUL_CONTINUE)
3228 return ret;
3229
3230 /* FIXME: check that next_tss_desc is tss */
3231
7f3d35fd
KW		 3232 /*
3233 * Check privileges. The three cases are task switch caused by...
3234 *
3235 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3236 * 2. Exception/IRQ/iret: No check is performed
2c2ca2d1
NA		 3237 * 3. jmp/call to TSS/task-gate: No check is performed since the
3238 * hardware checks it before exiting.
7f3d35fd
KW		 3239 */
3240 if (reason == TASK_SWITCH_GATE) {
3241 if (idt_index != -1) {
3242 /* Software interrupts */
3243 struct desc_struct task_gate_desc;
3244 int dpl;
3245
3246 ret = read_interrupt_descriptor(ctxt, idt_index,
3247 &task_gate_desc);
3248 if (ret != X86EMUL_CONTINUE)
3249 return ret;
3250
3251 dpl = task_gate_desc.dpl;
3252 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3253 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3254 }
38ba30ba
GN		 3255 }
3256
ceffb459
GN		 3257 desc_limit = desc_limit_scaled(&next_tss_desc);
3258 if (!next_tss_desc.p ||
3259 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3260 desc_limit < 0x2b)) {
592f0858 3261 return emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 3262 }
3263
3264 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3265 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
7b105ca2 3266 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
38ba30ba
GN		 3267 }
3268
3269 if (reason == TASK_SWITCH_IRET)
3270 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3271
3272 /* set back link to prev task only if NT bit is set in eflags
fc058680 3273 note that old_tss_sel is not used after this point */
38ba30ba
GN		 3274 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3275 old_tss_sel = 0xffff;
3276
3277 if (next_tss_desc.type & 8)
7b105ca2 3278 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
38ba30ba
GN		 3279 old_tss_base, &next_tss_desc);
3280 else
7b105ca2 3281 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
38ba30ba 3282 old_tss_base, &next_tss_desc);
0760d448
JK		 3283 if (ret != X86EMUL_CONTINUE)
3284 return ret;
38ba30ba
GN		 3285
3286 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3287 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3288
3289 if (reason != TASK_SWITCH_IRET) {
3290 next_tss_desc.type |= (1 << 1); /* set busy flag */
7b105ca2 3291 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
38ba30ba
GN		 3292 }
3293
717746e3 3294 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 3295 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 3296
e269fb21 3297 if (has_error_code) {
9dac77fa
AK		 3298 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3299 ctxt->lock_prefix = 0;
3300 ctxt->src.val = (unsigned long) error_code;
4487b3b4 3301 ret = em_push(ctxt);
e269fb21
JK		 3302 }
3303
3db176d5
NA		 3304 ops->get_dr(ctxt, 7, &dr7);
3305 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3306
38ba30ba
GN		 3307 return ret;
3308}
3309
3310int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
7f3d35fd 3311 u16 tss_selector, int idt_index, int reason,
e269fb21 3312 bool has_error_code, u32 error_code)
38ba30ba 3313{
38ba30ba
GN		 3314 int rc;
3315
dd856efa 3316 invalidate_registers(ctxt);
9dac77fa
AK		 3317 ctxt->_eip = ctxt->eip;
3318 ctxt->dst.type = OP_NONE;
38ba30ba 3319
7f3d35fd 3320 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
e269fb21 3321 has_error_code, error_code);
38ba30ba 3322
dd856efa 3323 if (rc == X86EMUL_CONTINUE) {
9dac77fa 3324 ctxt->eip = ctxt->_eip;
dd856efa
AK		 3325 writeback_registers(ctxt);
3326 }
38ba30ba 3327
a0c0ab2f 3328 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 3329}
3330
f3bd64c6
GN		 3331static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3332 struct operand *op)
a682e354 3333{
0efb0440 3334 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
a682e354 3335
01485a22
PB		 3336 register_address_increment(ctxt, reg, df * op->bytes);
3337 op->addr.mem.ea = register_address(ctxt, reg);
a682e354
GN		 3338}
3339
7af04fc0
AK		 3340static int em_das(struct x86_emulate_ctxt *ctxt)
3341{
7af04fc0
AK		 3342 u8 al, old_al;
3343 bool af, cf, old_cf;
3344
3345 cf = ctxt->eflags & X86_EFLAGS_CF;
9dac77fa 3346 al = ctxt->dst.val;
7af04fc0
AK		 3347
3348 old_al = al;
3349 old_cf = cf;
3350 cf = false;
3351 af = ctxt->eflags & X86_EFLAGS_AF;
3352 if ((al & 0x0f) > 9 || af) {
3353 al -= 6;
3354 cf = old_cf | (al >= 250);
3355 af = true;
3356 } else {
3357 af = false;
3358 }
3359 if (old_al > 0x99 || old_cf) {
3360 al -= 0x60;
3361 cf = true;
3362 }
3363
9dac77fa 3364 ctxt->dst.val = al;
7af04fc0 3365 /* Set PF, ZF, SF */
9dac77fa
AK		 3366 ctxt->src.type = OP_IMM;
3367 ctxt->src.val = 0;
3368 ctxt->src.bytes = 1;
158de57f 3369 fastop(ctxt, em_or);
7af04fc0
AK		 3370 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3371 if (cf)
3372 ctxt->eflags |= X86_EFLAGS_CF;
3373 if (af)
3374 ctxt->eflags |= X86_EFLAGS_AF;
3375 return X86EMUL_CONTINUE;
3376}
3377
a035d5c6
PB		 3378static int em_aam(struct x86_emulate_ctxt *ctxt)
3379{
3380 u8 al, ah;
3381
3382 if (ctxt->src.val == 0)
3383 return emulate_de(ctxt);
3384
3385 al = ctxt->dst.val & 0xff;
3386 ah = al / ctxt->src.val;
3387 al %= ctxt->src.val;
3388
3389 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3390
3391 /* Set PF, ZF, SF */
3392 ctxt->src.type = OP_IMM;
3393 ctxt->src.val = 0;
3394 ctxt->src.bytes = 1;
3395 fastop(ctxt, em_or);
3396
3397 return X86EMUL_CONTINUE;
3398}
3399
7f662273
GN		 3400static int em_aad(struct x86_emulate_ctxt *ctxt)
3401{
3402 u8 al = ctxt->dst.val & 0xff;
3403 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3404
3405 al = (al + (ah * ctxt->src.val)) & 0xff;
3406
3407 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3408
f583c29b
GN		 3409 /* Set PF, ZF, SF */
3410 ctxt->src.type = OP_IMM;
3411 ctxt->src.val = 0;
3412 ctxt->src.bytes = 1;
3413 fastop(ctxt, em_or);
7f662273
GN		 3414
3415 return X86EMUL_CONTINUE;
3416}
3417
d4ddafcd
TY		 3418static int em_call(struct x86_emulate_ctxt *ctxt)
3419{
234f3ce4 3420 int rc;
d4ddafcd
TY		 3421 long rel = ctxt->src.val;
3422
3423 ctxt->src.val = (unsigned long)ctxt->_eip;
234f3ce4
NA		 3424 rc = jmp_rel(ctxt, rel);
3425 if (rc != X86EMUL_CONTINUE)
3426 return rc;
d4ddafcd
TY		 3427 return em_push(ctxt);
3428}
3429
0ef753b8
AK		 3430static int em_call_far(struct x86_emulate_ctxt *ctxt)
3431{
0ef753b8
AK		 3432 u16 sel, old_cs;
3433 ulong old_eip;
3434 int rc;
d1442d85
NA		 3435 struct desc_struct old_desc, new_desc;
3436 const struct x86_emulate_ops *ops = ctxt->ops;
3437 int cpl = ctxt->ops->cpl(ctxt);
82268083 3438 enum x86emul_mode prev_mode = ctxt->mode;
0ef753b8 3439
9dac77fa 3440 old_eip = ctxt->_eip;
d1442d85 3441 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
0ef753b8 3442
9dac77fa 3443 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3dc4bc4f
NA		 3444 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3445 X86_TRANSFER_CALL_JMP, &new_desc);
d1442d85 3446 if (rc != X86EMUL_CONTINUE)
80976dbb 3447 return rc;
0ef753b8 3448
d50eaa18 3449 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
d1442d85
NA		 3450 if (rc != X86EMUL_CONTINUE)
3451 goto fail;
0ef753b8 3452
9dac77fa 3453 ctxt->src.val = old_cs;
4487b3b4 3454 rc = em_push(ctxt);
0ef753b8 3455 if (rc != X86EMUL_CONTINUE)
d1442d85 3456 goto fail;
0ef753b8 3457
9dac77fa 3458 ctxt->src.val = old_eip;
d1442d85
NA		 3459 rc = em_push(ctxt);
3460 /* If we failed, we tainted the memory, but the very least we should
3461 restore cs */
82268083
NA		 3462 if (rc != X86EMUL_CONTINUE) {
3463 pr_warn_once("faulting far call emulation tainted memory\n");
d1442d85 3464 goto fail;
82268083 3465 }
d1442d85
NA		 3466 return rc;
3467fail:
3468 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
82268083 3469 ctxt->mode = prev_mode;
d1442d85
NA		 3470 return rc;
3471
0ef753b8
AK		 3472}
3473
40ece7c7
AK		 3474static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3475{
40ece7c7 3476 int rc;
234f3ce4 3477 unsigned long eip;
40ece7c7 3478
234f3ce4
NA		 3479 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3480 if (rc != X86EMUL_CONTINUE)
3481 return rc;
3482 rc = assign_eip_near(ctxt, eip);
40ece7c7
AK		 3483 if (rc != X86EMUL_CONTINUE)
3484 return rc;
5ad105e5 3485 rsp_increment(ctxt, ctxt->src.val);
40ece7c7
AK		 3486 return X86EMUL_CONTINUE;
3487}
3488
e4f973ae
TY		 3489static int em_xchg(struct x86_emulate_ctxt *ctxt)
3490{
e4f973ae 3491 /* Write back the register source. */
9dac77fa
AK		 3492 ctxt->src.val = ctxt->dst.val;
3493 write_register_operand(&ctxt->src);
e4f973ae
TY		 3494
3495 /* Write back the memory destination with implicit LOCK prefix. */
9dac77fa
AK		 3496 ctxt->dst.val = ctxt->src.orig_val;
3497 ctxt->lock_prefix = 1;
e4f973ae
TY		 3498 return X86EMUL_CONTINUE;
3499}
3500
5c82aa29
AK		 3501static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3502{
9dac77fa 3503 ctxt->dst.val = ctxt->src2.val;
4d758349 3504 return fastop(ctxt, em_imul);
5c82aa29
AK		 3505}
3506
61429142
AK		 3507static int em_cwd(struct x86_emulate_ctxt *ctxt)
3508{
9dac77fa
AK		 3509 ctxt->dst.type = OP_REG;
3510 ctxt->dst.bytes = ctxt->src.bytes;
dd856efa 3511 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
9dac77fa 3512 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
61429142
AK		 3513
3514 return X86EMUL_CONTINUE;
3515}
3516
48bb5d3c
AK		 3517static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3518{
48bb5d3c
AK		 3519 u64 tsc = 0;
3520
717746e3 3521 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
dd856efa
AK		 3522 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3523 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
48bb5d3c
AK		 3524 return X86EMUL_CONTINUE;
3525}
3526
222d21aa
AK		 3527static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3528{
3529 u64 pmc;
3530
dd856efa 3531 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
222d21aa 3532 return emulate_gp(ctxt, 0);
dd856efa
AK		 3533 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3534 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
222d21aa
AK		 3535 return X86EMUL_CONTINUE;
3536}
3537
b9eac5f4
AK		 3538static int em_mov(struct x86_emulate_ctxt *ctxt)
3539{
54cfdb3e 3540 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
b9eac5f4
AK		 3541 return X86EMUL_CONTINUE;
3542}
3543
84cffe49
BP		 3544#define FFL(x) bit(X86_FEATURE_##x)
3545
3546static int em_movbe(struct x86_emulate_ctxt *ctxt)
3547{
3548 u32 ebx, ecx, edx, eax = 1;
3549 u16 tmp;
3550
3551 /*
3552 * Check MOVBE is set in the guest-visible CPUID leaf.
3553 */
e911eb3b 3554 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
84cffe49
BP		 3555 if (!(ecx & FFL(MOVBE)))
3556 return emulate_ud(ctxt);
3557
3558 switch (ctxt->op_bytes) {
3559 case 2:
3560 /*
3561 * From MOVBE definition: "...When the operand size is 16 bits,
3562 * the upper word of the destination register remains unchanged
3563 * ..."
3564 *
3565 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3566 * rules so we have to do the operation almost per hand.
3567 */
3568 tmp = (u16)ctxt->src.val;
3569 ctxt->dst.val &= ~0xffffUL;
3570 ctxt->dst.val |= (unsigned long)swab16(tmp);
3571 break;
3572 case 4:
3573 ctxt->dst.val = swab32((u32)ctxt->src.val);
3574 break;
3575 case 8:
3576 ctxt->dst.val = swab64(ctxt->src.val);
3577 break;
3578 default:
592f0858 3579 BUG();
84cffe49
BP		 3580 }
3581 return X86EMUL_CONTINUE;
3582}
3583
bc00f8d2
TY		 3584static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3585{
3586 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3587 return emulate_gp(ctxt, 0);
3588
3589 /* Disable writeback. */
3590 ctxt->dst.type = OP_NONE;
3591 return X86EMUL_CONTINUE;
3592}
3593
3594static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3595{
3596 unsigned long val;
3597
3598 if (ctxt->mode == X86EMUL_MODE_PROT64)
3599 val = ctxt->src.val & ~0ULL;
3600 else
3601 val = ctxt->src.val & ~0U;
3602
3603 /* #UD condition is already handled. */
3604 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3605 return emulate_gp(ctxt, 0);
3606
3607 /* Disable writeback. */
3608 ctxt->dst.type = OP_NONE;
3609 return X86EMUL_CONTINUE;
3610}
3611
e1e210b0
TY		 3612static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3613{
3614 u64 msr_data;
3615
dd856efa
AK		 3616 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3617 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3618 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
e1e210b0
TY		 3619 return emulate_gp(ctxt, 0);
3620
3621 return X86EMUL_CONTINUE;
3622}
3623
3624static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3625{
3626 u64 msr_data;
3627
dd856efa 3628 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
e1e210b0
TY		 3629 return emulate_gp(ctxt, 0);
3630
dd856efa
AK		 3631 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3632 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
e1e210b0
TY		 3633 return X86EMUL_CONTINUE;
3634}
3635
1bd5f469
TY		 3636static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3637{
9dac77fa 3638 if (ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3639 return emulate_ud(ctxt);
3640
9dac77fa 3641 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
b5bbf10e
NA		 3642 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3643 ctxt->dst.bytes = 2;
1bd5f469
TY		 3644 return X86EMUL_CONTINUE;
3645}
3646
3647static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3648{
9dac77fa 3649 u16 sel = ctxt->src.val;
1bd5f469 3650
9dac77fa 3651 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
1bd5f469
TY		 3652 return emulate_ud(ctxt);
3653
9dac77fa 3654 if (ctxt->modrm_reg == VCPU_SREG_SS)
1bd5f469
TY		 3655 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3656
3657 /* Disable writeback. */
9dac77fa
AK		 3658 ctxt->dst.type = OP_NONE;
3659 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
1bd5f469
TY		 3660}
3661
a14e579f
AK		 3662static int em_lldt(struct x86_emulate_ctxt *ctxt)
3663{
3664 u16 sel = ctxt->src.val;
3665
3666 /* Disable writeback. */
3667 ctxt->dst.type = OP_NONE;
3668 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3669}
3670
80890006
AK		 3671static int em_ltr(struct x86_emulate_ctxt *ctxt)
3672{
3673 u16 sel = ctxt->src.val;
3674
3675 /* Disable writeback. */
3676 ctxt->dst.type = OP_NONE;
3677 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3678}
3679
38503911
AK		 3680static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3681{
9fa088f4
AK		 3682 int rc;
3683 ulong linear;
3684
9dac77fa 3685 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
9fa088f4 3686 if (rc == X86EMUL_CONTINUE)
3cb16fe7 3687 ctxt->ops->invlpg(ctxt, linear);
38503911 3688 /* Disable writeback. */
9dac77fa 3689 ctxt->dst.type = OP_NONE;
38503911
AK		 3690 return X86EMUL_CONTINUE;
3691}
3692
2d04a05b
AK		 3693static int em_clts(struct x86_emulate_ctxt *ctxt)
3694{
3695 ulong cr0;
3696
3697 cr0 = ctxt->ops->get_cr(ctxt, 0);
3698 cr0 &= ~X86_CR0_TS;
3699 ctxt->ops->set_cr(ctxt, 0, cr0);
3700 return X86EMUL_CONTINUE;
3701}
3702
b34a8051 3703static int em_hypercall(struct x86_emulate_ctxt *ctxt)
26d05cc7 3704{
0f54a321 3705 int rc = ctxt->ops->fix_hypercall(ctxt);
26d05cc7 3706
26d05cc7
AK		 3707 if (rc != X86EMUL_CONTINUE)
3708 return rc;
3709
3710 /* Let the processor re-execute the fixed hypercall */
9dac77fa 3711 ctxt->_eip = ctxt->eip;
26d05cc7 3712 /* Disable writeback. */
9dac77fa 3713 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3714 return X86EMUL_CONTINUE;
3715}
3716
96051572
AK		 3717static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3718 void (*get)(struct x86_emulate_ctxt *ctxt,
3719 struct desc_ptr *ptr))
3720{
3721 struct desc_ptr desc_ptr;
3722
3723 if (ctxt->mode == X86EMUL_MODE_PROT64)
3724 ctxt->op_bytes = 8;
3725 get(ctxt, &desc_ptr);
3726 if (ctxt->op_bytes == 2) {
3727 ctxt->op_bytes = 4;
3728 desc_ptr.address &= 0x00ffffff;
3729 }
3730 /* Disable writeback. */
3731 ctxt->dst.type = OP_NONE;
129a72a0
SR		 3732 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3733 &desc_ptr, 2 + ctxt->op_bytes);
96051572
AK		 3734}
3735
3736static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3737{
3738 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3739}
3740
3741static int em_sidt(struct x86_emulate_ctxt *ctxt)
3742{
3743 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3744}
3745
5b7f6a1e 3746static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
26d05cc7 3747{
26d05cc7
AK		 3748 struct desc_ptr desc_ptr;
3749 int rc;
3750
510425ff
AK		 3751 if (ctxt->mode == X86EMUL_MODE_PROT64)
3752 ctxt->op_bytes = 8;
9dac77fa 3753 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
26d05cc7 3754 &desc_ptr.size, &desc_ptr.address,
9dac77fa 3755 ctxt->op_bytes);
26d05cc7
AK		 3756 if (rc != X86EMUL_CONTINUE)
3757 return rc;
9a9abf6b
NA		 3758 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3759 is_noncanonical_address(desc_ptr.address))
3760 return emulate_gp(ctxt, 0);
5b7f6a1e
NA		 3761 if (lgdt)
3762 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3763 else
3764 ctxt->ops->set_idt(ctxt, &desc_ptr);
26d05cc7 3765 /* Disable writeback. */
9dac77fa 3766 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3767 return X86EMUL_CONTINUE;
3768}
3769
5b7f6a1e
NA		 3770static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3771{
3772 return em_lgdt_lidt(ctxt, true);
3773}
3774
26d05cc7
AK		 3775static int em_lidt(struct x86_emulate_ctxt *ctxt)
3776{
5b7f6a1e 3777 return em_lgdt_lidt(ctxt, false);
26d05cc7
AK		 3778}
3779
3780static int em_smsw(struct x86_emulate_ctxt *ctxt)
3781{
32e94d06
NA		 3782 if (ctxt->dst.type == OP_MEM)
3783 ctxt->dst.bytes = 2;
9dac77fa 3784 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
26d05cc7
AK		 3785 return X86EMUL_CONTINUE;
3786}
3787
3788static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3789{
26d05cc7 3790 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
9dac77fa
AK		 3791 | (ctxt->src.val & 0x0f));
3792 ctxt->dst.type = OP_NONE;
26d05cc7
AK		 3793 return X86EMUL_CONTINUE;
3794}
3795
d06e03ad
TY		 3796static int em_loop(struct x86_emulate_ctxt *ctxt)
3797{
234f3ce4
NA		 3798 int rc = X86EMUL_CONTINUE;
3799
01485a22 3800 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
dd856efa 3801 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
9dac77fa 3802 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
234f3ce4 3803 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3804
234f3ce4 3805 return rc;
d06e03ad
TY		 3806}
3807
3808static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3809{
234f3ce4
NA		 3810 int rc = X86EMUL_CONTINUE;
3811
dd856efa 3812 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
234f3ce4 3813 rc = jmp_rel(ctxt, ctxt->src.val);
d06e03ad 3814
234f3ce4 3815 return rc;
d06e03ad
TY		 3816}
3817
d7841a4b
TY		 3818static int em_in(struct x86_emulate_ctxt *ctxt)
3819{
3820 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3821 &ctxt->dst.val))
3822 return X86EMUL_IO_NEEDED;
3823
3824 return X86EMUL_CONTINUE;
3825}
3826
3827static int em_out(struct x86_emulate_ctxt *ctxt)
3828{
3829 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3830 &ctxt->src.val, 1);
3831 /* Disable writeback. */
3832 ctxt->dst.type = OP_NONE;
3833 return X86EMUL_CONTINUE;
3834}
3835
f411e6cd
TY		 3836static int em_cli(struct x86_emulate_ctxt *ctxt)
3837{
3838 if (emulator_bad_iopl(ctxt))
3839 return emulate_gp(ctxt, 0);
3840
3841 ctxt->eflags &= ~X86_EFLAGS_IF;
3842 return X86EMUL_CONTINUE;
3843}
3844
3845static int em_sti(struct x86_emulate_ctxt *ctxt)
3846{
3847 if (emulator_bad_iopl(ctxt))
3848 return emulate_gp(ctxt, 0);
3849
3850 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3851 ctxt->eflags |= X86_EFLAGS_IF;
3852 return X86EMUL_CONTINUE;
3853}
3854
6d6eede4
AK		 3855static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3856{
3857 u32 eax, ebx, ecx, edx;
db2336a8
KH		 3858 u64 msr = 0;
3859
3860 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3861 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3862 ctxt->ops->cpl(ctxt)) {
3863 return emulate_gp(ctxt, 0);
3864 }
6d6eede4 3865
dd856efa
AK		 3866 eax = reg_read(ctxt, VCPU_REGS_RAX);
3867 ecx = reg_read(ctxt, VCPU_REGS_RCX);
e911eb3b 3868 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
dd856efa
AK		 3869 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3870 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3871 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3872 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
6d6eede4
AK		 3873 return X86EMUL_CONTINUE;
3874}
3875
98f73630
PB		 3876static int em_sahf(struct x86_emulate_ctxt *ctxt)
3877{
3878 u32 flags;
3879
0efb0440
NA		 3880 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3881 X86_EFLAGS_SF;
98f73630
PB		 3882 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3883
3884 ctxt->eflags &= ~0xffUL;
3885 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3886 return X86EMUL_CONTINUE;
3887}
3888
2dd7caa0
AK		 3889static int em_lahf(struct x86_emulate_ctxt *ctxt)
3890{
dd856efa
AK		 3891 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3892 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
2dd7caa0
AK		 3893 return X86EMUL_CONTINUE;
3894}
3895
9299836e
AK		 3896static int em_bswap(struct x86_emulate_ctxt *ctxt)
3897{
3898 switch (ctxt->op_bytes) {
3899#ifdef CONFIG_X86_64
3900 case 8:
3901 asm("bswap %0" : "+r"(ctxt->dst.val));
3902 break;
3903#endif
3904 default:
3905 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3906 break;
3907 }
3908 return X86EMUL_CONTINUE;
3909}
3910
13e457e0
NA		 3911static int em_clflush(struct x86_emulate_ctxt *ctxt)
3912{
3913 /* emulating clflush regardless of cpuid */
3914 return X86EMUL_CONTINUE;
3915}
3916
2276b511
NA		 3917static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3918{
3919 ctxt->dst.val = (s32) ctxt->src.val;
3920 return X86EMUL_CONTINUE;
3921}
3922
283c95d0
RK		 3923static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3924{
3925 u32 eax = 1, ebx, ecx = 0, edx;
3926
e911eb3b 3927 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
283c95d0
RK		 3928 if (!(edx & FFL(FXSR)))
3929 return emulate_ud(ctxt);
3930
3931 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3932 return emulate_nm(ctxt);
3933
3934 /*
3935 * Don't emulate a case that should never be hit, instead of working
3936 * around a lack of fxsave64/fxrstor64 on old compilers.
3937 */
3938 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3939 return X86EMUL_UNHANDLEABLE;
3940
3941 return X86EMUL_CONTINUE;
3942}
3943
9d643f63
ND		 3944/*
3945 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
3946 * and restore MXCSR.
3947 */
3948static size_t __fxstate_size(int nregs)
3949{
3950 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
3951}
3952
3953static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
3954{
3955 bool cr4_osfxsr;
3956 if (ctxt->mode == X86EMUL_MODE_PROT64)
3957 return __fxstate_size(16);
3958
3959 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
3960 return __fxstate_size(cr4_osfxsr ? 8 : 0);
3961}
3962
283c95d0
RK		 3963/*
3964 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3965 * 1) 16 bit mode
3966 * 2) 32 bit mode
3967 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3968 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3969 * save and restore
3970 * 3) 64-bit mode with REX.W prefix
3971 * - like (2), but XMM 8-15 are being saved and restored
3972 * 4) 64-bit mode without REX.W prefix
3973 * - like (3), but FIP and FDP are 64 bit
3974 *
3975 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3976 * desired result. (4) is not emulated.
3977 *
3978 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3979 * and FPU DS) should match.
3980 */
3981static int em_fxsave(struct x86_emulate_ctxt *ctxt)
3982{
3983 struct fxregs_state fx_state;
283c95d0
RK		 3984 int rc;
3985
3986 rc = check_fxsr(ctxt);
3987 if (rc != X86EMUL_CONTINUE)
3988 return rc;
3989
3990 ctxt->ops->get_fpu(ctxt);
3991
3992 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
3993
3994 ctxt->ops->put_fpu(ctxt);
3995
3996 if (rc != X86EMUL_CONTINUE)
3997 return rc;
3998
9d643f63
ND		 3999 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4000 fxstate_size(ctxt));
283c95d0
RK		 4001}
4002
4003static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4004{
4005 struct fxregs_state fx_state;
4006 int rc;
9d643f63 4007 size_t size;
283c95d0
RK		 4008
4009 rc = check_fxsr(ctxt);
4010 if (rc != X86EMUL_CONTINUE)
4011 return rc;
4012
9d643f63 4013 ctxt->ops->get_fpu(ctxt);
283c95d0 4014
9d643f63
ND		 4015 size = fxstate_size(ctxt);
4016 if (size < __fxstate_size(16)) {
4017 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4018 if (rc != X86EMUL_CONTINUE)
4019 goto out;
4020 }
283c95d0 4021
9d643f63
ND		 4022 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4023 if (rc != X86EMUL_CONTINUE)
4024 goto out;
283c95d0 4025
9d643f63
ND		 4026 if (fx_state.mxcsr >> 16) {
4027 rc = emulate_gp(ctxt, 0);
4028 goto out;
4029 }
283c95d0
RK		 4030
4031 if (rc == X86EMUL_CONTINUE)
4032 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4033
9d643f63 4034out:
283c95d0
RK		 4035 ctxt->ops->put_fpu(ctxt);
4036
4037 return rc;
4038}
4039
cfec82cb
JR		 4040static bool valid_cr(int nr)
4041{
4042 switch (nr) {
4043 case 0:
4044 case 2 ... 4:
4045 case 8:
4046 return true;
4047 default:
4048 return false;
4049 }
4050}
4051
4052static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4053{
9dac77fa 4054 if (!valid_cr(ctxt->modrm_reg))
cfec82cb
JR		 4055 return emulate_ud(ctxt);
4056
4057 return X86EMUL_CONTINUE;
4058}
4059
4060static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4061{
9dac77fa
AK		 4062 u64 new_val = ctxt->src.val64;
4063 int cr = ctxt->modrm_reg;
c2ad2bb3 4064 u64 efer = 0;
cfec82cb
JR		 4065
4066 static u64 cr_reserved_bits[] = {
4067 0xffffffff00000000ULL,
4068 0, 0, 0, /* CR3 checked later */
4069 CR4_RESERVED_BITS,
4070 0, 0, 0,
4071 CR8_RESERVED_BITS,
4072 };
4073
4074 if (!valid_cr(cr))
4075 return emulate_ud(ctxt);
4076
4077 if (new_val & cr_reserved_bits[cr])
4078 return emulate_gp(ctxt, 0);
4079
4080 switch (cr) {
4081 case 0: {
c2ad2bb3 4082 u64 cr4;
cfec82cb
JR		 4083 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4084 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4085 return emulate_gp(ctxt, 0);
4086
717746e3
AK		 4087 cr4 = ctxt->ops->get_cr(ctxt, 4);
4088 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4089
4090 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4091 !(cr4 & X86_CR4_PAE))
4092 return emulate_gp(ctxt, 0);
4093
4094 break;
4095 }
4096 case 3: {
4097 u64 rsvd = 0;
4098
c2ad2bb3
AK		 4099 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4100 if (efer & EFER_LMA)
9d88fca7 4101 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
cfec82cb
JR		 4102
4103 if (new_val & rsvd)
4104 return emulate_gp(ctxt, 0);
4105
4106 break;
4107 }
4108 case 4: {
717746e3 4109 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 4110
4111 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4112 return emulate_gp(ctxt, 0);
4113
4114 break;
4115 }
4116 }
4117
4118 return X86EMUL_CONTINUE;
4119}
4120
3b88e41a
JR		 4121static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4122{
4123 unsigned long dr7;
4124
717746e3 4125 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 4126
4127 /* Check if DR7.Global_Enable is set */
4128 return dr7 & (1 << 13);
4129}
4130
4131static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4132{
9dac77fa 4133 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4134 u64 cr4;
4135
4136 if (dr > 7)
4137 return emulate_ud(ctxt);
4138
717746e3 4139 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 4140 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4141 return emulate_ud(ctxt);
4142
6d2a0526
NA		 4143 if (check_dr7_gd(ctxt)) {
4144 ulong dr6;
4145
4146 ctxt->ops->get_dr(ctxt, 6, &dr6);
4147 dr6 &= ~15;
4148 dr6 |= DR6_BD | DR6_RTM;
4149 ctxt->ops->set_dr(ctxt, 6, dr6);
3b88e41a 4150 return emulate_db(ctxt);
6d2a0526 4151 }
3b88e41a
JR		 4152
4153 return X86EMUL_CONTINUE;
4154}
4155
4156static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4157{
9dac77fa
AK		 4158 u64 new_val = ctxt->src.val64;
4159 int dr = ctxt->modrm_reg;
3b88e41a
JR		 4160
4161 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4162 return emulate_gp(ctxt, 0);
4163
4164 return check_dr_read(ctxt);
4165}
4166
01de8b09
JR		 4167static int check_svme(struct x86_emulate_ctxt *ctxt)
4168{
92ceb767 4169 u64 efer = 0;
01de8b09 4170
717746e3 4171 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 4172
4173 if (!(efer & EFER_SVME))
4174 return emulate_ud(ctxt);
4175
4176 return X86EMUL_CONTINUE;
4177}
4178
4179static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4180{
dd856efa 4181 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
01de8b09
JR		 4182
4183 /* Valid physical address? */
d4224449 4184 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 4185 return emulate_gp(ctxt, 0);
4186
4187 return check_svme(ctxt);
4188}
4189
d7eb8203
JR		 4190static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4191{
717746e3 4192 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 4193
717746e3 4194 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 4195 return emulate_ud(ctxt);
4196
4197 return X86EMUL_CONTINUE;
4198}
4199
8061252e
JR		 4200static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4201{
717746e3 4202 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
dd856efa 4203 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
8061252e 4204
717746e3 4205 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
67f4d428 4206 ctxt->ops->check_pmc(ctxt, rcx))
8061252e
JR		 4207 return emulate_gp(ctxt, 0);
4208
4209 return X86EMUL_CONTINUE;
4210}
4211
f6511935
JR		 4212static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4213{
9dac77fa
AK		 4214 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4215 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
f6511935
JR		 4216 return emulate_gp(ctxt, 0);
4217
4218 return X86EMUL_CONTINUE;
4219}
4220
4221static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4222{
9dac77fa
AK		 4223 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4224 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
f6511935
JR		 4225 return emulate_gp(ctxt, 0);
4226
4227 return X86EMUL_CONTINUE;
4228}
4229
73fba5f4 4230#define D(_y) { .flags = (_y) }
d40a6898
PB		 4231#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4232#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4233 .intercept = x86_intercept_##_i, .check_perm = (_p) }
0b789eee 4234#define N D(NotImpl)
01de8b09 4235#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
1c2545be
TY		 4236#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4237#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
39f062ff 4238#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
2276b511 4239#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
045a282c 4240#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
73fba5f4 4241#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
e28bbd44 4242#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
c4f035c6 4243#define II(_f, _e, _i) \
d40a6898 4244 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd 4245#define IIP(_f, _e, _i, _p) \
d40a6898
PB		 4246 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4247 .intercept = x86_intercept_##_i, .check_perm = (_p) }
aa97bb48 4248#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 4249
8d8f4e9f 4250#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 4251#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f 4252#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
f7857f35 4253#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
d7841a4b
TY		 4254#define I2bvIP(_f, _e, _i, _p) \
4255 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
8d8f4e9f 4256
fb864fbc
AK		 4257#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4258 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4259 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 4260
0f54a321
NA		 4261static const struct opcode group7_rm0[] = {
4262 N,
b34a8051 4263 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
0f54a321
NA		 4264 N, N, N, N, N, N,
4265};
4266
fd0a0d82 4267static const struct opcode group7_rm1[] = {
1c2545be
TY		 4268 DI(SrcNone | Priv, monitor),
4269 DI(SrcNone | Priv, mwait),
d7eb8203
JR		 4270 N, N, N, N, N, N,
4271};
4272
fd0a0d82 4273static const struct opcode group7_rm3[] = {
1c2545be 4274 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
b34a8051 4275 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
1c2545be
TY		 4276 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4277 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4278 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4279 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4280 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4281 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
01de8b09 4282};
6230f7fc 4283
fd0a0d82 4284static const struct opcode group7_rm7[] = {
d7eb8203 4285 N,
1c2545be 4286 DIP(SrcNone, rdtscp, check_rdtsc),
d7eb8203
JR		 4287 N, N, N, N, N, N,
4288};
d67fc27a 4289
fd0a0d82 4290static const struct opcode group1[] = {
fb864fbc
AK		 4291 F(Lock, em_add),
4292 F(Lock | PageTable, em_or),
4293 F(Lock, em_adc),
4294 F(Lock, em_sbb),
4295 F(Lock | PageTable, em_and),
4296 F(Lock, em_sub),
4297 F(Lock, em_xor),
4298 F(NoWrite, em_cmp),
73fba5f4
AK		 4299};
4300
fd0a0d82 4301static const struct opcode group1A[] = {
0f89b207 4302 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
73fba5f4
AK		 4303};
4304
007a3b54
AK		 4305static const struct opcode group2[] = {
4306 F(DstMem | ModRM, em_rol),
4307 F(DstMem | ModRM, em_ror),
4308 F(DstMem | ModRM, em_rcl),
4309 F(DstMem | ModRM, em_rcr),
4310 F(DstMem | ModRM, em_shl),
4311 F(DstMem | ModRM, em_shr),
4312 F(DstMem | ModRM, em_shl),
4313 F(DstMem | ModRM, em_sar),
4314};
4315
fd0a0d82 4316static const struct opcode group3[] = {
fb864fbc
AK		 4317 F(DstMem | SrcImm | NoWrite, em_test),
4318 F(DstMem | SrcImm | NoWrite, em_test),
45a1467d
AK		 4319 F(DstMem | SrcNone | Lock, em_not),
4320 F(DstMem | SrcNone | Lock, em_neg),
b9fa409b
AK		 4321 F(DstXacc | Src2Mem, em_mul_ex),
4322 F(DstXacc | Src2Mem, em_imul_ex),
b8c0b6ae
AK		 4323 F(DstXacc | Src2Mem, em_div_ex),
4324 F(DstXacc | Src2Mem, em_idiv_ex),
73fba5f4
AK		 4325};
4326
fd0a0d82 4327static const struct opcode group4[] = {
95413dc4
AK		 4328 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4329 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
73fba5f4
AK		 4330 N, N, N, N, N, N,
4331};
4332
fd0a0d82 4333static const struct opcode group5[] = {
95413dc4
AK		 4334 F(DstMem | SrcNone | Lock, em_inc),
4335 F(DstMem | SrcNone | Lock, em_dec),
58b7075d 4336 I(SrcMem | NearBranch, em_call_near_abs),
acac6f89 4337 I(SrcMemFAddr | ImplicitOps, em_call_far),
58b7075d 4338 I(SrcMem | NearBranch, em_jmp_abs),
f7784046 4339 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
0f89b207 4340 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
73fba5f4
AK		 4341};
4342
fd0a0d82 4343static const struct opcode group6[] = {
63ea0a49
NA		 4344 DI(Prot | DstMem, sldt),
4345 DI(Prot | DstMem, str),
a14e579f 4346 II(Prot | Priv | SrcMem16, em_lldt, lldt),
80890006 4347 II(Prot | Priv | SrcMem16, em_ltr, ltr),
dee6bb70
JR		 4348 N, N, N, N,
4349};
4350
fd0a0d82 4351static const struct group_dual group7 = { {
606b1c3e
NA		 4352 II(Mov | DstMem, em_sgdt, sgdt),
4353 II(Mov | DstMem, em_sidt, sidt),
1c2545be
TY		 4354 II(SrcMem | Priv, em_lgdt, lgdt),
4355 II(SrcMem | Priv, em_lidt, lidt),
4356 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4357 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4358 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 4359}, {
0f54a321 4360 EXT(0, group7_rm0),
5ef39c71 4361 EXT(0, group7_rm1),
01de8b09 4362 N, EXT(0, group7_rm3),
1c2545be
TY		 4363 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4364 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4365 EXT(0, group7_rm7),
73fba5f4
AK		 4366} };
4367
fd0a0d82 4368static const struct opcode group8[] = {
73fba5f4 4369 N, N, N, N,
11c363ba
AK		 4370 F(DstMem | SrcImmByte | NoWrite, em_bt),
4371 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4372 F(DstMem | SrcImmByte | Lock, em_btr),
4373 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
73fba5f4
AK		 4374};
4375
fd0a0d82 4376static const struct group_dual group9 = { {
1c2545be 4377 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
73fba5f4
AK		 4378}, {
4379 N, N, N, N, N, N, N, N,
4380} };
4381
fd0a0d82 4382static const struct opcode group11[] = {
1c2545be 4383 I(DstMem | SrcImm | Mov | PageTable, em_mov),
d5ae7ce8 4384 X7(D(Undefined)),
a4d4a7c1
AK		 4385};
4386
13e457e0 4387static const struct gprefix pfx_0f_ae_7 = {
3f6f1480 4388 I(SrcMem | ByteOp, em_clflush), N, N, N,
13e457e0
NA		 4389};
4390
4391static const struct group_dual group15 = { {
283c95d0
RK		 4392 I(ModRM | Aligned16, em_fxsave),
4393 I(ModRM | Aligned16, em_fxrstor),
4394 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
13e457e0
NA		 4395}, {
4396 N, N, N, N, N, N, N, N,
4397} };
4398
fd0a0d82 4399static const struct gprefix pfx_0f_6f_0f_7f = {
e5971755 4400 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
aa97bb48
AK		 4401};
4402
39f062ff
NA		 4403static const struct instr_dual instr_dual_0f_2b = {
4404 I(0, em_mov), N
4405};
4406
d5b77069 4407static const struct gprefix pfx_0f_2b = {
39f062ff 4408 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3e114eb4
AK		 4409};
4410
27ce8258 4411static const struct gprefix pfx_0f_28_0f_29 = {
6fec27d8 4412 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
27ce8258
IM		 4413};
4414
0a37027e
AW		 4415static const struct gprefix pfx_0f_e7 = {
4416 N, I(Sse, em_mov), N, N,
4417};
4418
045a282c 4419static const struct escape escape_d9 = { {
16bebefe 4420 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
045a282c
GN		 4421}, {
4422 /* 0xC0 - 0xC7 */
4423 N, N, N, N, N, N, N, N,
4424 /* 0xC8 - 0xCF */
4425 N, N, N, N, N, N, N, N,
4426 /* 0xD0 - 0xC7 */
4427 N, N, N, N, N, N, N, N,
4428 /* 0xD8 - 0xDF */
4429 N, N, N, N, N, N, N, N,
4430 /* 0xE0 - 0xE7 */
4431 N, N, N, N, N, N, N, N,
4432 /* 0xE8 - 0xEF */
4433 N, N, N, N, N, N, N, N,
4434 /* 0xF0 - 0xF7 */
4435 N, N, N, N, N, N, N, N,
4436 /* 0xF8 - 0xFF */
4437 N, N, N, N, N, N, N, N,
4438} };
4439
4440static const struct escape escape_db = { {
4441 N, N, N, N, N, N, N, N,
4442}, {
4443 /* 0xC0 - 0xC7 */
4444 N, N, N, N, N, N, N, N,
4445 /* 0xC8 - 0xCF */
4446 N, N, N, N, N, N, N, N,
4447 /* 0xD0 - 0xC7 */
4448 N, N, N, N, N, N, N, N,
4449 /* 0xD8 - 0xDF */
4450 N, N, N, N, N, N, N, N,
4451 /* 0xE0 - 0xE7 */
4452 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4453 /* 0xE8 - 0xEF */
4454 N, N, N, N, N, N, N, N,
4455 /* 0xF0 - 0xF7 */
4456 N, N, N, N, N, N, N, N,
4457 /* 0xF8 - 0xFF */
4458 N, N, N, N, N, N, N, N,
4459} };
4460
4461static const struct escape escape_dd = { {
16bebefe 4462 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
045a282c
GN		 4463}, {
4464 /* 0xC0 - 0xC7 */
4465 N, N, N, N, N, N, N, N,
4466 /* 0xC8 - 0xCF */
4467 N, N, N, N, N, N, N, N,
4468 /* 0xD0 - 0xC7 */
4469 N, N, N, N, N, N, N, N,
4470 /* 0xD8 - 0xDF */
4471 N, N, N, N, N, N, N, N,
4472 /* 0xE0 - 0xE7 */
4473 N, N, N, N, N, N, N, N,
4474 /* 0xE8 - 0xEF */
4475 N, N, N, N, N, N, N, N,
4476 /* 0xF0 - 0xF7 */
4477 N, N, N, N, N, N, N, N,
4478 /* 0xF8 - 0xFF */
4479 N, N, N, N, N, N, N, N,
4480} };
4481
39f062ff
NA		 4482static const struct instr_dual instr_dual_0f_c3 = {
4483 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4484};
4485
2276b511
NA		 4486static const struct mode_dual mode_dual_63 = {
4487 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4488};
4489
fd0a0d82 4490static const struct opcode opcode_table[256] = {
73fba5f4 4491 /* 0x00 - 0x07 */
fb864fbc 4492 F6ALU(Lock, em_add),
1cd196ea
AK		 4493 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4494 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
73fba5f4 4495 /* 0x08 - 0x0F */
fb864fbc 4496 F6ALU(Lock | PageTable, em_or),
1cd196ea
AK		 4497 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4498 N,
73fba5f4 4499 /* 0x10 - 0x17 */
fb864fbc 4500 F6ALU(Lock, em_adc),
1cd196ea
AK		 4501 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4502 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
73fba5f4 4503 /* 0x18 - 0x1F */
fb864fbc 4504 F6ALU(Lock, em_sbb),
1cd196ea
AK		 4505 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4506 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
73fba5f4 4507 /* 0x20 - 0x27 */
fb864fbc 4508 F6ALU(Lock | PageTable, em_and), N, N,
73fba5f4 4509 /* 0x28 - 0x2F */
fb864fbc 4510 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 4511 /* 0x30 - 0x37 */
fb864fbc 4512 F6ALU(Lock, em_xor), N, N,
73fba5f4 4513 /* 0x38 - 0x3F */
fb864fbc 4514 F6ALU(NoWrite, em_cmp), N, N,
73fba5f4 4515 /* 0x40 - 0x4F */
95413dc4 4516 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
73fba5f4 4517 /* 0x50 - 0x57 */
63540382 4518 X8(I(SrcReg | Stack, em_push)),
73fba5f4 4519 /* 0x58 - 0x5F */
c54fe504 4520 X8(I(DstReg | Stack, em_pop)),
73fba5f4 4521 /* 0x60 - 0x67 */
b96a7fad
TY		 4522 I(ImplicitOps | Stack | No64, em_pusha),
4523 I(ImplicitOps | Stack | No64, em_popa),
2276b511 4524 N, MD(ModRM, &mode_dual_63),
73fba5f4
AK		 4525 N, N, N, N,
4526 /* 0x68 - 0x6F */
d46164db
AK		 4527 I(SrcImm | Mov | Stack, em_push),
4528 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 4529 I(SrcImmByte | Mov | Stack, em_push),
4530 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
b3356bf0 4531 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
2b5e97e1 4532 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4 4533 /* 0x70 - 0x7F */
58b7075d 4534 X16(D(SrcImmByte | NearBranch)),
73fba5f4 4535 /* 0x80 - 0x87 */
1c2545be
TY		 4536 G(ByteOp | DstMem | SrcImm, group1),
4537 G(DstMem | SrcImm, group1),
4538 G(ByteOp | DstMem | SrcImm | No64, group1),
4539 G(DstMem | SrcImmByte, group1),
fb864fbc 4540 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
d5ae7ce8 4541 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
73fba5f4 4542 /* 0x88 - 0x8F */
d5ae7ce8 4543 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
b9eac5f4 4544 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
d5ae7ce8 4545 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
1bd5f469
TY		 4546 D(ModRM | SrcMem | NoAccess | DstReg),
4547 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4548 G(0, group1A),
73fba5f4 4549 /* 0x90 - 0x97 */
bf608f88 4550 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 4551 /* 0x98 - 0x9F */
61429142 4552 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 4553 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0 4554 II(ImplicitOps | Stack, em_pushf, pushf),
98f73630
PB		 4555 II(ImplicitOps | Stack, em_popf, popf),
4556 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
73fba5f4 4557 /* 0xA0 - 0xA7 */
b9eac5f4 4558 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
d5ae7ce8 4559 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
0f89b207
TL		 4560 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4561 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
73fba5f4 4562 /* 0xA8 - 0xAF */
fb864fbc 4563 F2bv(DstAcc | SrcImm | NoWrite, em_test),
b9eac5f4
AK		 4564 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4565 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
5aca3722 4566 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
73fba5f4 4567 /* 0xB0 - 0xB7 */
b9eac5f4 4568 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 4569 /* 0xB8 - 0xBF */
5e2c6883 4570 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
73fba5f4 4571 /* 0xC0 - 0xC7 */
007a3b54 4572 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
58b7075d
NA		 4573 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4574 I(ImplicitOps | NearBranch, em_ret),
d4b4325f
AK		 4575 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4576 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
a4d4a7c1 4577 G(ByteOp, group11), G(0, group11),
73fba5f4 4578 /* 0xC8 - 0xCF */
612e89f0 4579 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
16794aaa
NA		 4580 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4581 I(ImplicitOps, em_ret_far),
3c6e276f 4582 D(ImplicitOps), DI(SrcImmByte, intn),
db5b0762 4583 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
73fba5f4 4584 /* 0xD0 - 0xD7 */
007a3b54
AK		 4585 G(Src2One | ByteOp, group2), G(Src2One, group2),
4586 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
a035d5c6 4587 I(DstAcc | SrcImmUByte | No64, em_aam),
326f578f
PB		 4588 I(DstAcc | SrcImmUByte | No64, em_aad),
4589 F(DstAcc | ByteOp | No64, em_salc),
7fa57952 4590 I(DstAcc | SrcXLat | ByteOp, em_mov),
73fba5f4 4591 /* 0xD8 - 0xDF */
045a282c 4592 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
73fba5f4 4593 /* 0xE0 - 0xE7 */
58b7075d
NA		 4594 X3(I(SrcImmByte | NearBranch, em_loop)),
4595 I(SrcImmByte | NearBranch, em_jcxz),
d7841a4b
TY		 4596 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4597 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
73fba5f4 4598 /* 0xE8 - 0xEF */
58b7075d
NA		 4599 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4600 I(SrcImmFAddr | No64, em_jmp_far),
4601 D(SrcImmByte | ImplicitOps | NearBranch),
d7841a4b
TY		 4602 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4603 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
73fba5f4 4604 /* 0xF0 - 0xF7 */
bf608f88 4605 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 4606 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4607 G(ByteOp, group3), G(0, group3),
73fba5f4 4608 /* 0xF8 - 0xFF */
f411e6cd
TY		 4609 D(ImplicitOps), D(ImplicitOps),
4610 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
73fba5f4
AK		 4611 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4612};
4613
fd0a0d82 4614static const struct opcode twobyte_table[256] = {
73fba5f4 4615 /* 0x00 - 0x0F */
dee6bb70 4616 G(0, group6), GD(0, &group7), N, N,
b51e974f 4617 N, I(ImplicitOps | EmulateOnUD, em_syscall),
db5b0762 4618 II(ImplicitOps | Priv, em_clts, clts), N,
3c6e276f 4619 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3f6f1480 4620 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
73fba5f4 4621 /* 0x10 - 0x1F */
103f98ea 4622 N, N, N, N, N, N, N, N,
3f6f1480
NA		 4623 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4624 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
73fba5f4 4625 /* 0x20 - 0x2F */
9b88ae99
NA		 4626 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4627 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4628 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4629 check_cr_write),
4630 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4631 check_dr_write),
73fba5f4 4632 N, N, N, N,
27ce8258
IM		 4633 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4634 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
d5b77069 4635 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
3e114eb4 4636 N, N, N, N,
73fba5f4 4637 /* 0x30 - 0x3F */
e1e210b0 4638 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
8061252e 4639 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
e1e210b0 4640 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
222d21aa 4641 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
b51e974f
BP		 4642 I(ImplicitOps | EmulateOnUD, em_sysenter),
4643 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
d867162c 4644 N, N,
73fba5f4
AK		 4645 N, N, N, N, N, N, N, N,
4646 /* 0x40 - 0x4F */
140bad89 4647 X16(D(DstReg | SrcMem | ModRM)),
73fba5f4
AK		 4648 /* 0x50 - 0x5F */
4649 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4650 /* 0x60 - 0x6F */
aa97bb48
AK		 4651 N, N, N, N,
4652 N, N, N, N,
4653 N, N, N, N,
4654 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4655 /* 0x70 - 0x7F */
aa97bb48
AK		 4656 N, N, N, N,
4657 N, N, N, N,
4658 N, N, N, N,
4659 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 4660 /* 0x80 - 0x8F */
58b7075d 4661 X16(D(SrcImm | NearBranch)),
73fba5f4 4662 /* 0x90 - 0x9F */
ee45b58e 4663 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4 4664 /* 0xA0 - 0xA7 */
1cd196ea 4665 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
11c363ba
AK		 4666 II(ImplicitOps, em_cpuid, cpuid),
4667 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
0bdea068
AK		 4668 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4669 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
73fba5f4 4670 /* 0xA8 - 0xAF */
1cd196ea 4671 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
89651a3d 4672 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
11c363ba 4673 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
0bdea068
AK		 4674 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4675 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
13e457e0 4676 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 4677 /* 0xB0 - 0xB7 */
2fcf5c8a 4678 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
d4b4325f 4679 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
11c363ba 4680 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
d4b4325f
AK		 4681 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4682 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
2adb5ad9 4683 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 4684 /* 0xB8 - 0xBF */
4685 N, N,
ce7faab2 4686 G(BitOp, group8),
11c363ba 4687 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
900efe20
NA		 4688 I(DstReg | SrcMem | ModRM, em_bsf_c),
4689 I(DstReg | SrcMem | ModRM, em_bsr_c),
2adb5ad9 4690 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
9299836e 4691 /* 0xC0 - 0xC7 */
e47a5f5f 4692 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
39f062ff 4693 N, ID(0, &instr_dual_0f_c3),
73fba5f4 4694 N, N, N, GD(0, &group9),
9299836e
AK		 4695 /* 0xC8 - 0xCF */
4696 X8(I(DstReg, em_bswap)),
73fba5f4
AK		 4697 /* 0xD0 - 0xDF */
4698 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4699 /* 0xE0 - 0xEF */
0a37027e
AW		 4700 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4701 N, N, N, N, N, N, N, N,
73fba5f4
AK		 4702 /* 0xF0 - 0xFF */
4703 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4704};
4705
39f062ff
NA		 4706static const struct instr_dual instr_dual_0f_38_f0 = {
4707 I(DstReg | SrcMem | Mov, em_movbe), N
4708};
4709
4710static const struct instr_dual instr_dual_0f_38_f1 = {
4711 I(DstMem | SrcReg | Mov, em_movbe), N
4712};
4713
0bc5eedb 4714static const struct gprefix three_byte_0f_38_f0 = {
39f062ff 4715 ID(0, &instr_dual_0f_38_f0), N, N, N
0bc5eedb
BP		 4716};
4717
4718static const struct gprefix three_byte_0f_38_f1 = {
39f062ff 4719 ID(0, &instr_dual_0f_38_f1), N, N, N
0bc5eedb
BP		 4720};
4721
4722/*
4723 * Insns below are selected by the prefix which indexed by the third opcode
4724 * byte.
4725 */
4726static const struct opcode opcode_map_0f_38[256] = {
4727 /* 0x00 - 0x7f */
4728 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
84cffe49
BP		 4729 /* 0x80 - 0xef */
4730 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4731 /* 0xf0 - 0xf1 */
53bb4f78
NA		 4732 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4733 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
84cffe49
BP		 4734 /* 0xf2 - 0xff */
4735 N, N, X4(N), X8(N)
0bc5eedb
BP		 4736};
4737
73fba5f4
AK		 4738#undef D
4739#undef N
4740#undef G
4741#undef GD
4742#undef I
aa97bb48 4743#undef GP
01de8b09 4744#undef EXT
2276b511 4745#undef MD
2b42fce6 4746#undef ID
73fba5f4 4747
8d8f4e9f 4748#undef D2bv
f6511935 4749#undef D2bvIP
8d8f4e9f 4750#undef I2bv
d7841a4b 4751#undef I2bvIP
d67fc27a 4752#undef I6ALU
8d8f4e9f 4753
9dac77fa 4754static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
39f21ee5
AK		 4755{
4756 unsigned size;
4757
9dac77fa 4758 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
39f21ee5
AK		 4759 if (size == 8)
4760 size = 4;
4761 return size;
4762}
4763
4764static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4765 unsigned size, bool sign_extension)
4766{
39f21ee5
AK		 4767 int rc = X86EMUL_CONTINUE;
4768
4769 op->type = OP_IMM;
4770 op->bytes = size;
9dac77fa 4771 op->addr.mem.ea = ctxt->_eip;
39f21ee5
AK		 4772 /* NB. Immediates are sign-extended as necessary. */
4773 switch (op->bytes) {
4774 case 1:
e85a1085 4775 op->val = insn_fetch(s8, ctxt);
39f21ee5
AK		 4776 break;
4777 case 2:
e85a1085 4778 op->val = insn_fetch(s16, ctxt);
39f21ee5
AK		 4779 break;
4780 case 4:
e85a1085 4781 op->val = insn_fetch(s32, ctxt);
39f21ee5 4782 break;
5e2c6883
NA		 4783 case 8:
4784 op->val = insn_fetch(s64, ctxt);
4785 break;
39f21ee5
AK		 4786 }
4787 if (!sign_extension) {
4788 switch (op->bytes) {
4789 case 1:
4790 op->val &= 0xff;
4791 break;
4792 case 2:
4793 op->val &= 0xffff;
4794 break;
4795 case 4:
4796 op->val &= 0xffffffff;
4797 break;
4798 }
4799 }
4800done:
4801 return rc;
4802}
4803
a9945549
AK		 4804static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4805 unsigned d)
4806{
4807 int rc = X86EMUL_CONTINUE;
4808
4809 switch (d) {
4810 case OpReg:
2adb5ad9 4811 decode_register_operand(ctxt, op);
a9945549
AK		 4812 break;
4813 case OpImmUByte:
608aabe3 4814 rc = decode_imm(ctxt, op, 1, false);
a9945549
AK		 4815 break;
4816 case OpMem:
41ddf978 4817 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
0fe59128
AK		 4818 mem_common:
4819 *op = ctxt->memop;
4820 ctxt->memopp = op;
96888977 4821 if (ctxt->d & BitOp)
a9945549
AK		 4822 fetch_bit_operand(ctxt);
4823 op->orig_val = op->val;
4824 break;
41ddf978 4825 case OpMem64:
aaa05f24 4826 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
41ddf978 4827 goto mem_common;
a9945549
AK		 4828 case OpAcc:
4829 op->type = OP_REG;
4830 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
dd856efa 4831 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
a9945549
AK		 4832 fetch_register_operand(op);
4833 op->orig_val = op->val;
4834 break;
820207c8
AK		 4835 case OpAccLo:
4836 op->type = OP_REG;
4837 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4838 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4839 fetch_register_operand(op);
4840 op->orig_val = op->val;
4841 break;
4842 case OpAccHi:
4843 if (ctxt->d & ByteOp) {
4844 op->type = OP_NONE;
4845 break;
4846 }
4847 op->type = OP_REG;
4848 op->bytes = ctxt->op_bytes;
4849 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4850 fetch_register_operand(op);
4851 op->orig_val = op->val;
4852 break;
a9945549
AK		 4853 case OpDI:
4854 op->type = OP_MEM;
4855 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4856 op->addr.mem.ea =
01485a22 4857 register_address(ctxt, VCPU_REGS_RDI);
a9945549
AK		 4858 op->addr.mem.seg = VCPU_SREG_ES;
4859 op->val = 0;
b3356bf0 4860 op->count = 1;
a9945549
AK		 4861 break;
4862 case OpDX:
4863 op->type = OP_REG;
4864 op->bytes = 2;
dd856efa 4865 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
a9945549
AK		 4866 fetch_register_operand(op);
4867 break;
4dd6a57d 4868 case OpCL:
d29b9d7e 4869 op->type = OP_IMM;
4dd6a57d 4870 op->bytes = 1;
dd856efa 4871 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4dd6a57d
AK		 4872 break;
4873 case OpImmByte:
4874 rc = decode_imm(ctxt, op, 1, true);
4875 break;
4876 case OpOne:
d29b9d7e 4877 op->type = OP_IMM;
4dd6a57d
AK		 4878 op->bytes = 1;
4879 op->val = 1;
4880 break;
4881 case OpImm:
4882 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4883 break;
5e2c6883
NA		 4884 case OpImm64:
4885 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4886 break;
28867cee
AK		 4887 case OpMem8:
4888 ctxt->memop.bytes = 1;
660696d1 4889 if (ctxt->memop.type == OP_REG) {
aa9ac1a6
GN		 4890 ctxt->memop.addr.reg = decode_register(ctxt,
4891 ctxt->modrm_rm, true);
660696d1
GN		 4892 fetch_register_operand(&ctxt->memop);
4893 }
28867cee 4894 goto mem_common;
0fe59128
AK		 4895 case OpMem16:
4896 ctxt->memop.bytes = 2;
4897 goto mem_common;
4898 case OpMem32:
4899 ctxt->memop.bytes = 4;
4900 goto mem_common;
4901 case OpImmU16:
4902 rc = decode_imm(ctxt, op, 2, false);
4903 break;
4904 case OpImmU:
4905 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4906 break;
4907 case OpSI:
4908 op->type = OP_MEM;
4909 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4910 op->addr.mem.ea =
01485a22 4911 register_address(ctxt, VCPU_REGS_RSI);
573e80fe 4912 op->addr.mem.seg = ctxt->seg_override;
0fe59128 4913 op->val = 0;
b3356bf0 4914 op->count = 1;
0fe59128 4915 break;
7fa57952
PB		 4916 case OpXLat:
4917 op->type = OP_MEM;
4918 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4919 op->addr.mem.ea =
01485a22 4920 address_mask(ctxt,
7fa57952
PB		 4921 reg_read(ctxt, VCPU_REGS_RBX) +
4922 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
573e80fe 4923 op->addr.mem.seg = ctxt->seg_override;
7fa57952
PB		 4924 op->val = 0;
4925 break;
0fe59128
AK		 4926 case OpImmFAddr:
4927 op->type = OP_IMM;
4928 op->addr.mem.ea = ctxt->_eip;
4929 op->bytes = ctxt->op_bytes + 2;
4930 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4931 break;
4932 case OpMemFAddr:
4933 ctxt->memop.bytes = ctxt->op_bytes + 2;
4934 goto mem_common;
c191a7a0 4935 case OpES:
d29b9d7e 4936 op->type = OP_IMM;
c191a7a0
AK		 4937 op->val = VCPU_SREG_ES;
4938 break;
4939 case OpCS:
d29b9d7e 4940 op->type = OP_IMM;
c191a7a0
AK		 4941 op->val = VCPU_SREG_CS;
4942 break;
4943 case OpSS:
d29b9d7e 4944 op->type = OP_IMM;
c191a7a0
AK		 4945 op->val = VCPU_SREG_SS;
4946 break;
4947 case OpDS:
d29b9d7e 4948 op->type = OP_IMM;
c191a7a0
AK		 4949 op->val = VCPU_SREG_DS;
4950 break;
4951 case OpFS:
d29b9d7e 4952 op->type = OP_IMM;
c191a7a0
AK		 4953 op->val = VCPU_SREG_FS;
4954 break;
4955 case OpGS:
d29b9d7e 4956 op->type = OP_IMM;
c191a7a0
AK		 4957 op->val = VCPU_SREG_GS;
4958 break;
a9945549
AK		 4959 case OpImplicit:
4960 /* Special instructions do their own operand decoding. */
4961 default:
4962 op->type = OP_NONE; /* Disable writeback. */
4963 break;
4964 }
4965
4966done:
4967 return rc;
4968}
4969
ef5d75cc 4970int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1 4971{
dde7e6d1
AK		 4972 int rc = X86EMUL_CONTINUE;
4973 int mode = ctxt->mode;
46561646 4974 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 4975 bool op_prefix = false;
573e80fe 4976 bool has_seg_override = false;
46561646 4977 struct opcode opcode;
dde7e6d1 4978
f09ed83e
AK		 4979 ctxt->memop.type = OP_NONE;
4980 ctxt->memopp = NULL;
9dac77fa 4981 ctxt->_eip = ctxt->eip;
17052f16
PB		 4982 ctxt->fetch.ptr = ctxt->fetch.data;
4983 ctxt->fetch.end = ctxt->fetch.data + insn_len;
1ce19dc1 4984 ctxt->opcode_len = 1;
dc25e89e 4985 if (insn_len > 0)
9dac77fa 4986 memcpy(ctxt->fetch.data, insn, insn_len);
285ca9e9 4987 else {
9506d57d 4988 rc = __do_insn_fetch_bytes(ctxt, 1);
285ca9e9
PB		 4989 if (rc != X86EMUL_CONTINUE)
4990 return rc;
4991 }
dde7e6d1
AK		 4992
4993 switch (mode) {
4994 case X86EMUL_MODE_REAL:
4995 case X86EMUL_MODE_VM86:
4996 case X86EMUL_MODE_PROT16:
4997 def_op_bytes = def_ad_bytes = 2;
4998 break;
4999 case X86EMUL_MODE_PROT32:
5000 def_op_bytes = def_ad_bytes = 4;
5001 break;
5002#ifdef CONFIG_X86_64
5003 case X86EMUL_MODE_PROT64:
5004 def_op_bytes = 4;
5005 def_ad_bytes = 8;
5006 break;
5007#endif
5008 default:
1d2887e2 5009 return EMULATION_FAILED;
dde7e6d1
AK		 5010 }
5011
9dac77fa
AK		 5012 ctxt->op_bytes = def_op_bytes;
5013 ctxt->ad_bytes = def_ad_bytes;
dde7e6d1
AK		 5014
5015 /* Legacy prefixes. */
5016 for (;;) {
e85a1085 5017 switch (ctxt->b = insn_fetch(u8, ctxt)) {
dde7e6d1 5018 case 0x66: /* operand-size override */
0d7cdee8 5019 op_prefix = true;
dde7e6d1 5020 /* switch between 2/4 bytes */
9dac77fa 5021 ctxt->op_bytes = def_op_bytes ^ 6;
dde7e6d1
AK		 5022 break;
5023 case 0x67: /* address-size override */
5024 if (mode == X86EMUL_MODE_PROT64)
5025 /* switch between 4/8 bytes */
9dac77fa 5026 ctxt->ad_bytes = def_ad_bytes ^ 12;
dde7e6d1
AK		 5027 else
5028 /* switch between 2/4 bytes */
9dac77fa 5029 ctxt->ad_bytes = def_ad_bytes ^ 6;
dde7e6d1
AK		 5030 break;
5031 case 0x26: /* ES override */
5032 case 0x2e: /* CS override */
5033 case 0x36: /* SS override */
5034 case 0x3e: /* DS override */
573e80fe
BD		 5035 has_seg_override = true;
5036 ctxt->seg_override = (ctxt->b >> 3) & 3;
dde7e6d1
AK		 5037 break;
5038 case 0x64: /* FS override */
5039 case 0x65: /* GS override */
573e80fe
BD		 5040 has_seg_override = true;
5041 ctxt->seg_override = ctxt->b & 7;
dde7e6d1
AK		 5042 break;
5043 case 0x40 ... 0x4f: /* REX */
5044 if (mode != X86EMUL_MODE_PROT64)
5045 goto done_prefixes;
9dac77fa 5046 ctxt->rex_prefix = ctxt->b;
dde7e6d1
AK		 5047 continue;
5048 case 0xf0: /* LOCK */
9dac77fa 5049 ctxt->lock_prefix = 1;
dde7e6d1
AK		 5050 break;
5051 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 5052 case 0xf3: /* REP/REPE/REPZ */
9dac77fa 5053 ctxt->rep_prefix = ctxt->b;
dde7e6d1
AK		 5054 break;
5055 default:
5056 goto done_prefixes;
5057 }
5058
5059 /* Any legacy prefix after a REX prefix nullifies its effect. */
5060
9dac77fa 5061 ctxt->rex_prefix = 0;
dde7e6d1
AK		 5062 }
5063
5064done_prefixes:
5065
5066 /* REX prefix. */
9dac77fa
AK		 5067 if (ctxt->rex_prefix & 8)
5068 ctxt->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 5069
5070 /* Opcode byte(s). */
9dac77fa 5071 opcode = opcode_table[ctxt->b];
d3ad6243 5072 /* Two-byte opcode? */
9dac77fa 5073 if (ctxt->b == 0x0f) {
1ce19dc1 5074 ctxt->opcode_len = 2;
e85a1085 5075 ctxt->b = insn_fetch(u8, ctxt);
9dac77fa 5076 opcode = twobyte_table[ctxt->b];
0bc5eedb
BP		 5077
5078 /* 0F_38 opcode map */
5079 if (ctxt->b == 0x38) {
5080 ctxt->opcode_len = 3;
5081 ctxt->b = insn_fetch(u8, ctxt);
5082 opcode = opcode_map_0f_38[ctxt->b];
5083 }
dde7e6d1 5084 }
9dac77fa 5085 ctxt->d = opcode.flags;
dde7e6d1 5086
9f4260e7
TY		 5087 if (ctxt->d & ModRM)
5088 ctxt->modrm = insn_fetch(u8, ctxt);
5089
7fe864dc
NA		 5090 /* vex-prefix instructions are not implemented */
5091 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
d14cb5df 5092 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
7fe864dc
NA		 5093 ctxt->d = NotImpl;
5094 }
5095
9dac77fa
AK		 5096 while (ctxt->d & GroupMask) {
5097 switch (ctxt->d & GroupMask) {
46561646 5098 case Group:
9dac77fa 5099 goffset = (ctxt->modrm >> 3) & 7;
46561646
AK		 5100 opcode = opcode.u.group[goffset];
5101 break;
5102 case GroupDual:
9dac77fa
AK		 5103 goffset = (ctxt->modrm >> 3) & 7;
5104 if ((ctxt->modrm >> 6) == 3)
46561646
AK		 5105 opcode = opcode.u.gdual->mod3[goffset];
5106 else
5107 opcode = opcode.u.gdual->mod012[goffset];
5108 break;
5109 case RMExt:
9dac77fa 5110 goffset = ctxt->modrm & 7;
01de8b09 5111 opcode = opcode.u.group[goffset];
46561646
AK		 5112 break;
5113 case Prefix:
9dac77fa 5114 if (ctxt->rep_prefix && op_prefix)
1d2887e2 5115 return EMULATION_FAILED;
9dac77fa 5116 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
46561646
AK		 5117 switch (simd_prefix) {
5118 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5119 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5120 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5121 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5122 }
5123 break;
045a282c
GN		 5124 case Escape:
5125 if (ctxt->modrm > 0xbf)
5126 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5127 else
5128 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5129 break;
39f062ff
NA		 5130 case InstrDual:
5131 if ((ctxt->modrm >> 6) == 3)
5132 opcode = opcode.u.idual->mod3;
5133 else
5134 opcode = opcode.u.idual->mod012;
5135 break;
2276b511
NA		 5136 case ModeDual:
5137 if (ctxt->mode == X86EMUL_MODE_PROT64)
5138 opcode = opcode.u.mdual->mode64;
5139 else
5140 opcode = opcode.u.mdual->mode32;
5141 break;
46561646 5142 default:
1d2887e2 5143 return EMULATION_FAILED;
0d7cdee8 5144 }
46561646 5145
b1ea50b2 5146 ctxt->d &= ~(u64)GroupMask;
9dac77fa 5147 ctxt->d |= opcode.flags;
0d7cdee8
AK		 5148 }
5149
e24186e0
PB		 5150 /* Unrecognised? */
5151 if (ctxt->d == 0)
5152 return EMULATION_FAILED;
5153
9dac77fa 5154 ctxt->execute = opcode.u.execute;
dde7e6d1 5155
3a6095a0
NA		 5156 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5157 return EMULATION_FAILED;
5158
d40a6898 5159 if (unlikely(ctxt->d &
ed9aad21
NA		 5160 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5161 No16))) {
d40a6898
PB		 5162 /*
5163 * These are copied unconditionally here, and checked unconditionally
5164 * in x86_emulate_insn.
5165 */
5166 ctxt->check_perm = opcode.check_perm;
5167 ctxt->intercept = opcode.intercept;
dde7e6d1 5168
d40a6898
PB		 5169 if (ctxt->d & NotImpl)
5170 return EMULATION_FAILED;
d867162c 5171
58b7075d
NA		 5172 if (mode == X86EMUL_MODE_PROT64) {
5173 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5174 ctxt->op_bytes = 8;
5175 else if (ctxt->d & NearBranch)
5176 ctxt->op_bytes = 8;
5177 }
7f9b4b75 5178
d40a6898
PB		 5179 if (ctxt->d & Op3264) {
5180 if (mode == X86EMUL_MODE_PROT64)
5181 ctxt->op_bytes = 8;
5182 else
5183 ctxt->op_bytes = 4;
5184 }
5185
ed9aad21
NA		 5186 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5187 ctxt->op_bytes = 4;
5188
d40a6898
PB		 5189 if (ctxt->d & Sse)
5190 ctxt->op_bytes = 16;
5191 else if (ctxt->d & Mmx)
5192 ctxt->op_bytes = 8;
5193 }
1253791d 5194
dde7e6d1 5195 /* ModRM and SIB bytes. */
9dac77fa 5196 if (ctxt->d & ModRM) {
f09ed83e 5197 rc = decode_modrm(ctxt, &ctxt->memop);
573e80fe
BD		 5198 if (!has_seg_override) {
5199 has_seg_override = true;
5200 ctxt->seg_override = ctxt->modrm_seg;
5201 }
9dac77fa 5202 } else if (ctxt->d & MemAbs)
f09ed83e 5203 rc = decode_abs(ctxt, &ctxt->memop);
dde7e6d1
AK		 5204 if (rc != X86EMUL_CONTINUE)
5205 goto done;
5206
573e80fe
BD		 5207 if (!has_seg_override)
5208 ctxt->seg_override = VCPU_SREG_DS;
dde7e6d1 5209
573e80fe 5210 ctxt->memop.addr.mem.seg = ctxt->seg_override;
dde7e6d1 5211
dde7e6d1
AK		 5212 /*
5213 * Decode and fetch the source operand: register, memory
5214 * or immediate.
5215 */
0fe59128 5216 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
39f21ee5
AK		 5217 if (rc != X86EMUL_CONTINUE)
5218 goto done;
5219
dde7e6d1
AK		 5220 /*
5221 * Decode and fetch the second source operand: register, memory
5222 * or immediate.
5223 */
4dd6a57d 5224 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
39f21ee5
AK		 5225 if (rc != X86EMUL_CONTINUE)
5226 goto done;
5227
dde7e6d1 5228 /* Decode and fetch the destination operand: register or memory. */
a9945549 5229 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
dde7e6d1 5230
d9092f52 5231 if (ctxt->rip_relative && likely(ctxt->memopp))
1c1c35ae
NA		 5232 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5233 ctxt->memopp->addr.mem.ea + ctxt->_eip);
cb16c348 5234
a430c916 5235done:
1d2887e2 5236 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 5237}
5238
1cb3f3ae
XG		 5239bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5240{
5241 return ctxt->d & PageTable;
5242}
5243
3e2f65d5
GN		 5244static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5245{
3e2f65d5
GN		 5246 /* The second termination condition only applies for REPE
5247 * and REPNE. Test if the repeat string operation prefix is
5248 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5249 * corresponding termination condition according to:
5250 * - if REPE/REPZ and ZF = 0 then done
5251 * - if REPNE/REPNZ and ZF = 1 then done
5252 */
9dac77fa
AK		 5253 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5254 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5255 && (((ctxt->rep_prefix == REPE_PREFIX) &&
0efb0440 5256 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
9dac77fa 5257 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
0efb0440 5258 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
3e2f65d5
GN		 5259 return true;
5260
5261 return false;
5262}
5263
cbe2c9d3
AK		 5264static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5265{
aabba3c6 5266 int rc;
cbe2c9d3
AK		 5267
5268 ctxt->ops->get_fpu(ctxt);
aabba3c6 5269 rc = asm_safe("fwait");
cbe2c9d3
AK		 5270 ctxt->ops->put_fpu(ctxt);
5271
aabba3c6 5272 if (unlikely(rc != X86EMUL_CONTINUE))
cbe2c9d3
AK		 5273 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5274
5275 return X86EMUL_CONTINUE;
5276}
5277
5278static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5279 struct operand *op)
5280{
5281 if (op->type == OP_MM)
5282 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5283}
5284
e28bbd44
AK		 5285static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5286{
4548f63e 5287 register void *__sp asm(_ASM_SP);
e28bbd44 5288 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4548f63e 5289
b9fa409b
AK		 5290 if (!(ctxt->d & ByteOp))
5291 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4548f63e 5292
e28bbd44 5293 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
b8c0b6ae 5294 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4548f63e 5295 [fastop]"+S"(fop), "+r"(__sp)
b8c0b6ae 5296 : "c"(ctxt->src2.val));
4548f63e 5297
e28bbd44 5298 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
b8c0b6ae
AK		 5299 if (!fop) /* exception is returned in fop variable */
5300 return emulate_de(ctxt);
e28bbd44
AK		 5301 return X86EMUL_CONTINUE;
5302}
dd856efa 5303
1498507a
BD		 5304void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5305{
573e80fe
BD		 5306 memset(&ctxt->rip_relative, 0,
5307 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
1498507a 5308
1498507a
BD		 5309 ctxt->io_read.pos = 0;
5310 ctxt->io_read.end = 0;
1498507a
BD		 5311 ctxt->mem_read.end = 0;
5312}
5313
7b105ca2 5314int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 5315{
0225fb50 5316 const struct x86_emulate_ops *ops = ctxt->ops;
1b30eaa8 5317 int rc = X86EMUL_CONTINUE;
9dac77fa 5318 int saved_dst_type = ctxt->dst.type;
6ed071f0 5319 unsigned emul_flags;
8b4caf66 5320
9dac77fa 5321 ctxt->mem_read.pos = 0;
310b5d30 5322
e24186e0
PB		 5323 /* LOCK prefix is allowed only with some instructions */
5324 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
35d3d4a1 5325 rc = emulate_ud(ctxt);
1161624f
GN		 5326 goto done;
5327 }
5328
e24186e0 5329 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
35d3d4a1 5330 rc = emulate_ud(ctxt);
d380a5e4
GN		 5331 goto done;
5332 }
5333
6ed071f0 5334 emul_flags = ctxt->ops->get_hflags(ctxt);
d40a6898
PB		 5335 if (unlikely(ctxt->d &
5336 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5337 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5338 (ctxt->d & Undefined)) {
5339 rc = emulate_ud(ctxt);
5340 goto done;
5341 }
1253791d 5342
d40a6898
PB		 5343 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5344 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5345 rc = emulate_ud(ctxt);
cbe2c9d3 5346 goto done;
d40a6898 5347 }
cbe2c9d3 5348
d40a6898
PB		 5349 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5350 rc = emulate_nm(ctxt);
c4f035c6 5351 goto done;
d40a6898 5352 }
c4f035c6 5353
d40a6898
PB		 5354 if (ctxt->d & Mmx) {
5355 rc = flush_pending_x87_faults(ctxt);
5356 if (rc != X86EMUL_CONTINUE)
5357 goto done;
5358 /*
5359 * Now that we know the fpu is exception safe, we can fetch
5360 * operands from it.
5361 */
5362 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5363 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5364 if (!(ctxt->d & Mov))
5365 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5366 }
e92805ac 5367
6ed071f0 5368 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
d40a6898
PB		 5369 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5370 X86_ICPT_PRE_EXCEPT);
5371 if (rc != X86EMUL_CONTINUE)
5372 goto done;
5373 }
8ea7d6ae 5374
64a38292
NA		 5375 /* Instruction can only be executed in protected mode */
5376 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5377 rc = emulate_ud(ctxt);
5378 goto done;
5379 }
5380
d40a6898
PB		 5381 /* Privileged instruction can be executed only in CPL=0 */
5382 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
68efa764
NA		 5383 if (ctxt->d & PrivUD)
5384 rc = emulate_ud(ctxt);
5385 else
5386 rc = emulate_gp(ctxt, 0);
d09beabd 5387 goto done;
d40a6898 5388 }
d09beabd 5389
d40a6898 5390 /* Do instruction specific permission checks */
685bbf4a 5391 if (ctxt->d & CheckPerm) {
d40a6898
PB		 5392 rc = ctxt->check_perm(ctxt);
5393 if (rc != X86EMUL_CONTINUE)
5394 goto done;
5395 }
5396
6ed071f0 5397 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
d40a6898
PB		 5398 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5399 X86_ICPT_POST_EXCEPT);
5400 if (rc != X86EMUL_CONTINUE)
5401 goto done;
5402 }
5403
5404 if (ctxt->rep_prefix && (ctxt->d & String)) {
5405 /* All REP prefixes have the same first termination condition */
5406 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
428e3d08 5407 string_registers_quirk(ctxt);
d40a6898 5408 ctxt->eip = ctxt->_eip;
0efb0440 5409 ctxt->eflags &= ~X86_EFLAGS_RF;
d40a6898
PB		 5410 goto done;
5411 }
b9fa9d6b 5412 }
b9fa9d6b
AK		 5413 }
5414
9dac77fa
AK		 5415 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5416 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5417 ctxt->src.valptr, ctxt->src.bytes);
b60d513c 5418 if (rc != X86EMUL_CONTINUE)
8b4caf66 5419 goto done;
9dac77fa 5420 ctxt->src.orig_val64 = ctxt->src.val64;
8b4caf66
LV		 5421 }
5422
9dac77fa
AK		 5423 if (ctxt->src2.type == OP_MEM) {
5424 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5425 &ctxt->src2.val, ctxt->src2.bytes);
e35b7b9c
GN		 5426 if (rc != X86EMUL_CONTINUE)
5427 goto done;
5428 }
5429
9dac77fa 5430 if ((ctxt->d & DstMask) == ImplicitOps)
8b4caf66
LV		 5431 goto special_insn;
5432
5433
9dac77fa 5434 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
69f55cb1 5435 /* optimisation - avoid slow emulated read if Mov */
9dac77fa
AK		 5436 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5437 &ctxt->dst.val, ctxt->dst.bytes);
c205fb7d 5438 if (rc != X86EMUL_CONTINUE) {
d44e1212
PB		 5439 if (!(ctxt->d & NoWrite) &&
5440 rc == X86EMUL_PROPAGATE_FAULT &&
c205fb7d
NA		 5441 ctxt->exception.vector == PF_VECTOR)
5442 ctxt->exception.error_code |= PFERR_WRITE_MASK;
69f55cb1 5443 goto done;
c205fb7d 5444 }
038e51de 5445 }
4ff6f8e6
PB		 5446 /* Copy full 64-bit value for CMPXCHG8B. */
5447 ctxt->dst.orig_val64 = ctxt->dst.val64;
038e51de 5448
018a98db
AK		 5449special_insn:
5450
6ed071f0 5451 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
9dac77fa 5452 rc = emulator_check_intercept(ctxt, ctxt->intercept,
8a76d7f2 5453 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 5454 if (rc != X86EMUL_CONTINUE)
5455 goto done;
5456 }
5457
b9a1ecb9 5458 if (ctxt->rep_prefix && (ctxt->d & String))
0efb0440 5459 ctxt->eflags |= X86_EFLAGS_RF;
b9a1ecb9 5460 else
0efb0440 5461 ctxt->eflags &= ~X86_EFLAGS_RF;
4467c3f1 5462
9dac77fa 5463 if (ctxt->execute) {
e28bbd44
AK		 5464 if (ctxt->d & Fastop) {
5465 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5466 rc = fastop(ctxt, fop);
5467 if (rc != X86EMUL_CONTINUE)
5468 goto done;
5469 goto writeback;
5470 }
9dac77fa 5471 rc = ctxt->execute(ctxt);
ef65c889
AK		 5472 if (rc != X86EMUL_CONTINUE)
5473 goto done;
5474 goto writeback;
5475 }
5476
1ce19dc1 5477 if (ctxt->opcode_len == 2)
6aa8b732 5478 goto twobyte_insn;
0bc5eedb
BP		 5479 else if (ctxt->opcode_len == 3)
5480 goto threebyte_insn;
6aa8b732 5481
9dac77fa 5482 switch (ctxt->b) {
b2833e3c 5483 case 0x70 ... 0x7f: /* jcc (short) */
9dac77fa 5484 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5485 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5486 break;
7e0b54b1 5487 case 0x8d: /* lea r16/r32, m */
9dac77fa 5488 ctxt->dst.val = ctxt->src.addr.mem.ea;
7e0b54b1 5489 break;
3d9e77df 5490 case 0x90 ... 0x97: /* nop / xchg reg, rax */
dd856efa 5491 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
a825f5cc
NA		 5492 ctxt->dst.type = OP_NONE;
5493 else
5494 rc = em_xchg(ctxt);
e4f973ae 5495 break;
e8b6fa70 5496 case 0x98: /* cbw/cwde/cdqe */
9dac77fa
AK		 5497 switch (ctxt->op_bytes) {
5498 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5499 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5500 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
e8b6fa70
WY		 5501 }
5502 break;
6e154e56 5503 case 0xcc: /* int3 */
5c5df76b
TY		 5504 rc = emulate_int(ctxt, 3);
5505 break;
6e154e56 5506 case 0xcd: /* int n */
9dac77fa 5507 rc = emulate_int(ctxt, ctxt->src.val);
6e154e56
MG		 5508 break;
5509 case 0xce: /* into */
0efb0440 5510 if (ctxt->eflags & X86_EFLAGS_OF)
5c5df76b 5511 rc = emulate_int(ctxt, 4);
6e154e56 5512 break;
1a52e051 5513 case 0xe9: /* jmp rel */
db5b0762 5514 case 0xeb: /* jmp rel short */
234f3ce4 5515 rc = jmp_rel(ctxt, ctxt->src.val);
9dac77fa 5516 ctxt->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 5517 break;
111de5d6 5518 case 0xf4: /* hlt */
6c3287f7 5519 ctxt->ops->halt(ctxt);
19fdfa0d 5520 break;
111de5d6
AK		 5521 case 0xf5: /* cmc */
5522 /* complement carry flag from eflags reg */
0efb0440 5523 ctxt->eflags ^= X86_EFLAGS_CF;
111de5d6
AK		 5524 break;
5525 case 0xf8: /* clc */
0efb0440 5526 ctxt->eflags &= ~X86_EFLAGS_CF;
111de5d6 5527 break;
8744aa9a 5528 case 0xf9: /* stc */
0efb0440 5529 ctxt->eflags |= X86_EFLAGS_CF;
8744aa9a 5530 break;
fb4616f4 5531 case 0xfc: /* cld */
0efb0440 5532 ctxt->eflags &= ~X86_EFLAGS_DF;
fb4616f4
MG		 5533 break;
5534 case 0xfd: /* std */
0efb0440 5535 ctxt->eflags |= X86_EFLAGS_DF;
fb4616f4 5536 break;
91269b8f
AK		 5537 default:
5538 goto cannot_emulate;
6aa8b732 5539 }
018a98db 5540
7d9ddaed
AK		 5541 if (rc != X86EMUL_CONTINUE)
5542 goto done;
5543
018a98db 5544writeback:
fb32b1ed
AK		 5545 if (ctxt->d & SrcWrite) {
5546 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5547 rc = writeback(ctxt, &ctxt->src);
5548 if (rc != X86EMUL_CONTINUE)
5549 goto done;
5550 }
ee212297
NA		 5551 if (!(ctxt->d & NoWrite)) {
5552 rc = writeback(ctxt, &ctxt->dst);
5553 if (rc != X86EMUL_CONTINUE)
5554 goto done;
5555 }
018a98db 5556
5cd21917
GN		 5557 /*
5558 * restore dst type in case the decoding will be reused
5559 * (happens for string instruction )
5560 */
9dac77fa 5561 ctxt->dst.type = saved_dst_type;
5cd21917 5562
9dac77fa 5563 if ((ctxt->d & SrcMask) == SrcSI)
f3bd64c6 5564 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
a682e354 5565
9dac77fa 5566 if ((ctxt->d & DstMask) == DstDI)
f3bd64c6 5567 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
d9271123 5568
9dac77fa 5569 if (ctxt->rep_prefix && (ctxt->d & String)) {
b3356bf0 5570 unsigned int count;
9dac77fa 5571 struct read_cache *r = &ctxt->io_read;
b3356bf0
GN		 5572 if ((ctxt->d & SrcMask) == SrcSI)
5573 count = ctxt->src.count;
5574 else
5575 count = ctxt->dst.count;
01485a22 5576 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
3e2f65d5 5577
d2ddd1c4
GN		 5578 if (!string_insn_completed(ctxt)) {
5579 /*
5580 * Re-enter guest when pio read ahead buffer is empty
5581 * or, if it is not used, after each 1024 iteration.
5582 */
dd856efa 5583 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
d2ddd1c4
GN		 5584 (r->end == 0 || r->end != r->pos)) {
5585 /*
5586 * Reset read cache. Usually happens before
5587 * decode, but since instruction is restarted
5588 * we have to do it here.
5589 */
9dac77fa 5590 ctxt->mem_read.end = 0;
dd856efa 5591 writeback_registers(ctxt);
d2ddd1c4
GN		 5592 return EMULATION_RESTART;
5593 }
5594 goto done; /* skip rip writeback */
0fa6ccbd 5595 }
0efb0440 5596 ctxt->eflags &= ~X86_EFLAGS_RF;
5cd21917 5597 }
d2ddd1c4 5598
9dac77fa 5599 ctxt->eip = ctxt->_eip;
018a98db
AK		 5600
5601done:
e0ad0b47
PB		 5602 if (rc == X86EMUL_PROPAGATE_FAULT) {
5603 WARN_ON(ctxt->exception.vector > 0x1f);
da9cb575 5604 ctxt->have_exception = true;
e0ad0b47 5605 }
775fde86
JR		 5606 if (rc == X86EMUL_INTERCEPTED)
5607 return EMULATION_INTERCEPTED;
5608
dd856efa
AK		 5609 if (rc == X86EMUL_CONTINUE)
5610 writeback_registers(ctxt);
5611
d2ddd1c4 5612 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 5613
5614twobyte_insn:
9dac77fa 5615 switch (ctxt->b) {
018a98db 5616 case 0x09: /* wbinvd */
cfb22375 5617 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 5618 break;
5619 case 0x08: /* invd */
018a98db
AK		 5620 case 0x0d: /* GrpP (prefetch) */
5621 case 0x18: /* Grp16 (prefetch/nop) */
103f98ea 5622 case 0x1f: /* nop */
018a98db
AK		 5623 break;
5624 case 0x20: /* mov cr, reg */
9dac77fa 5625 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
018a98db 5626 break;
6aa8b732 5627 case 0x21: /* mov from dr to reg */
9dac77fa 5628 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
6aa8b732 5629 break;
6aa8b732 5630 case 0x40 ... 0x4f: /* cmov */
140bad89
NA		 5631 if (test_cc(ctxt->b, ctxt->eflags))
5632 ctxt->dst.val = ctxt->src.val;
b91aa14d 5633 else if (ctxt->op_bytes != 4)
9dac77fa 5634 ctxt->dst.type = OP_NONE; /* no writeback */
6aa8b732 5635 break;
b2833e3c 5636 case 0x80 ... 0x8f: /* jnz rel, etc*/
9dac77fa 5637 if (test_cc(ctxt->b, ctxt->eflags))
234f3ce4 5638 rc = jmp_rel(ctxt, ctxt->src.val);
018a98db 5639 break;
ee45b58e 5640 case 0x90 ... 0x9f: /* setcc r/m8 */
9dac77fa 5641 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
ee45b58e 5642 break;
6aa8b732 5643 case 0xb6 ... 0xb7: /* movzx */
9dac77fa 5644 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5645 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
9dac77fa 5646 : (u16) ctxt->src.val;
6aa8b732 5647 break;
6aa8b732 5648 case 0xbe ... 0xbf: /* movsx */
9dac77fa 5649 ctxt->dst.bytes = ctxt->op_bytes;
361cad2b 5650 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
9dac77fa 5651 (s16) ctxt->src.val;
6aa8b732 5652 break;
91269b8f
AK		 5653 default:
5654 goto cannot_emulate;
6aa8b732 5655 }
7d9ddaed 5656
0bc5eedb
BP		 5657threebyte_insn:
5658
7d9ddaed
AK		 5659 if (rc != X86EMUL_CONTINUE)
5660 goto done;
5661
6aa8b732
AK		 5662 goto writeback;
5663
5664cannot_emulate:
a0c0ab2f 5665 return EMULATION_FAILED;
6aa8b732 5666}
dd856efa
AK		 5667
5668void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5669{
5670 invalidate_registers(ctxt);
5671}
5672
5673void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5674{
5675 writeback_registers(ctxt);
5676}
0f89b207
TL		 5677
5678bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5679{
5680 if (ctxt->rep_prefix && (ctxt->d & String))
5681 return false;
5682
5683 if (ctxt->d & TwoMemOp)
5684 return false;
5685
5686 return true;
5687}
ubuntu-bionic-kernel mirror