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KVM: x86 emulator: Check CPL level during privilege instruction emulation
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
56e82318 33#include <asm/kvm_emulate.h>
6aa8b732 34
3eeb3288 35#include "x86.h"
e99f0507 36
6aa8b732
AK		 37/*
38 * Opcode effective-address decode tables.
39 * Note that we only emulate instructions that have at least one memory
40 * operand (excluding implicit stack references). We assume that stack
41 * references and instruction fetches will never occur in special memory
42 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
43 * not be handled.
44 */
45
46/* Operand sizes: 8-bit operands or specified/overridden size. */
47#define ByteOp (1<<0) /* 8-bit operands. */
48/* Destination operand type. */
49#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
50#define DstReg (2<<1) /* Register operand. */
51#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 52#define DstAcc (4<<1) /* Destination Accumulator */
53#define DstMask (7<<1)
6aa8b732 54/* Source operand type. */
9c9fddd0
GT		 55#define SrcNone (0<<4) /* No source operand. */
56#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
57#define SrcReg (1<<4) /* Register operand. */
58#define SrcMem (2<<4) /* Memory operand. */
59#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
60#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
61#define SrcImm (5<<4) /* Immediate operand. */
62#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 63#define SrcOne (7<<4) /* Implied '1' */
341de7e3 64#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 65#define SrcImmU (9<<4) /* Immediate operand, unsigned */
341de7e3 66#define SrcMask (0xf<<4)
6aa8b732 67/* Generic ModRM decode. */
341de7e3 68#define ModRM (1<<8)
6aa8b732 69/* Destination is only written; never read. */
341de7e3
GN		 70#define Mov (1<<9)
71#define BitOp (1<<10)
72#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 73#define String (1<<12) /* String instruction (rep capable) */
74#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 75#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
76#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
77#define GroupMask 0xff /* Group number stored in bits 0:7 */
d8769fed 78/* Misc flags */
e92805ac 79#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 80#define No64 (1<<28)
0dc8d10f
GT		 81/* Source 2 operand type */
82#define Src2None (0<<29)
83#define Src2CL (1<<29)
84#define Src2ImmByte (2<<29)
85#define Src2One (3<<29)
a5f868bd 86#define Src2Imm16 (4<<29)
0dc8d10f 87#define Src2Mask (7<<29)
6aa8b732 88
43bb19cd 89enum {
1d6ad207 90 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 91 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
60a29d4e 92 Group8, Group9,
43bb19cd
AK		 93};
94
45ed60b3 95static u32 opcode_table[256] = {
6aa8b732
AK		 96 /* 0x00 - 0x07 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 99 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 100 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 101 /* 0x08 - 0x0F */
102 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
103 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94677e61
MG		 104 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
105 ImplicitOps | Stack | No64, 0,
6aa8b732
AK		 106 /* 0x10 - 0x17 */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 109 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 110 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 111 /* 0x18 - 0x1F */
112 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
113 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
0934ac9d 114 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
d8769fed 115 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
6aa8b732
AK		 116 /* 0x20 - 0x27 */
117 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
118 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 119 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 120 /* 0x28 - 0x2F */
121 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
122 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
123 0, 0, 0, 0,
124 /* 0x30 - 0x37 */
125 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
127 0, 0, 0, 0,
128 /* 0x38 - 0x3F */
129 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 131 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
132 0, 0,
d77a2507 133 /* 0x40 - 0x47 */
33615aa9 134 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 135 /* 0x48 - 0x4F */
33615aa9 136 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 137 /* 0x50 - 0x57 */
6e3d5dfb
AK		 138 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
139 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 140 /* 0x58 - 0x5F */
6e3d5dfb
AK		 141 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
142 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 143 /* 0x60 - 0x67 */
abcf14b5
MG		 144 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64,
145 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 146 0, 0, 0, 0,
147 /* 0x68 - 0x6F */
91ed7a0e 148 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 149 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
150 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 151 /* 0x70 - 0x77 */
b2833e3c
GN		 152 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
153 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 154 /* 0x78 - 0x7F */
b2833e3c
GN		 155 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
156 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 157 /* 0x80 - 0x87 */
1d6ad207
AK		 158 Group | Group1_80, Group | Group1_81,
159 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 160 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
161 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
162 /* 0x88 - 0x8F */
163 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
164 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 165 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 166 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 167 /* 0x90 - 0x97 */
168 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
169 /* 0x98 - 0x9F */
d8769fed 170 0, 0, SrcImm | Src2Imm16 | No64, 0,
0654169e 171 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 172 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 173 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
174 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 175 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
176 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 177 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 178 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
179 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
180 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 181 /* 0xB0 - 0xB7 */
182 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
183 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
184 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
185 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
186 /* 0xB8 - 0xBF */
187 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
188 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
189 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
190 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 191 /* 0xC0 - 0xC7 */
d9413cd7 192 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 193 0, ImplicitOps | Stack, 0, 0,
d9413cd7 194 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 195 /* 0xC8 - 0xCF */
e637b823 196 0, 0, 0, ImplicitOps | Stack,
d8769fed 197 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps,
6aa8b732
AK		 198 /* 0xD0 - 0xD7 */
199 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
200 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
201 0, 0, 0, 0,
202 /* 0xD8 - 0xDF */
203 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 204 /* 0xE0 - 0xE7 */
a6a3034c 205 0, 0, 0, 0,
84ce66a6
GN		 206 ByteOp | SrcImmUByte, SrcImmUByte,
207 ByteOp | SrcImmUByte, SrcImmUByte,
098c937b 208 /* 0xE8 - 0xEF */
d53c4777 209 SrcImm | Stack, SrcImm | ImplicitOps,
d8769fed 210 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps,
a6a3034c
MG		 211 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
212 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 213 /* 0xF0 - 0xF7 */
214 0, 0, 0, 0,
e92805ac 215 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 216 /* 0xF8 - 0xFF */
b284be57 217 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 218 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 219};
220
45ed60b3 221static u32 twobyte_table[256] = {
6aa8b732 222 /* 0x00 - 0x0F */
e92805ac
GN		 223 0, Group | GroupDual | Group7, 0, 0,
224 0, ImplicitOps, ImplicitOps | Priv, 0,
225 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0,
226 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 227 /* 0x10 - 0x1F */
228 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
229 /* 0x20 - 0x2F */
e92805ac
GN		 230 ModRM | ImplicitOps | Priv, ModRM | Priv,
231 ModRM | ImplicitOps | Priv, ModRM | Priv,
232 0, 0, 0, 0,
6aa8b732
AK		 233 0, 0, 0, 0, 0, 0, 0, 0,
234 /* 0x30 - 0x3F */
e92805ac
GN		 235 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0,
236 ImplicitOps, ImplicitOps | Priv, 0, 0,
e99f0507 237 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 238 /* 0x40 - 0x47 */
239 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
241 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
243 /* 0x48 - 0x4F */
244 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
245 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
246 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
248 /* 0x50 - 0x5F */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0x60 - 0x6F */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0x70 - 0x7F */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0x80 - 0x8F */
b2833e3c
GN		 255 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
256 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 257 /* 0x90 - 0x9F */
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
259 /* 0xA0 - 0xA7 */
0934ac9d
MG		 260 ImplicitOps | Stack, ImplicitOps | Stack,
261 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 262 DstMem | SrcReg | Src2ImmByte | ModRM,
263 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 264 /* 0xA8 - 0xAF */
0934ac9d
MG		 265 ImplicitOps | Stack, ImplicitOps | Stack,
266 0, DstMem | SrcReg | ModRM | BitOp,
9bf8ea42
GT		 267 DstMem | SrcReg | Src2ImmByte | ModRM,
268 DstMem | SrcReg | Src2CL | ModRM,
269 ModRM, 0,
6aa8b732
AK		 270 /* 0xB0 - 0xB7 */
271 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 272 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 273 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
274 DstReg | SrcMem16 | ModRM | Mov,
275 /* 0xB8 - 0xBF */
2db2c2eb 276 0, 0, Group | Group8, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 277 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
278 DstReg | SrcMem16 | ModRM | Mov,
279 /* 0xC0 - 0xCF */
60a29d4e
GN		 280 0, 0, 0, DstMem | SrcReg | ModRM | Mov,
281 0, 0, 0, Group | GroupDual | Group9,
a012e65a 282 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 283 /* 0xD0 - 0xDF */
284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
285 /* 0xE0 - 0xEF */
286 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
287 /* 0xF0 - 0xFF */
288 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
289};
290
45ed60b3 291static u32 group_table[] = {
1d6ad207
AK		 292 [Group1_80*8] =
293 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
294 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
295 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
296 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
297 [Group1_81*8] =
298 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
299 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
300 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
301 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
302 [Group1_82*8] =
303 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
304 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
305 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
306 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
307 [Group1_83*8] =
308 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
309 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
310 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
311 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 312 [Group1A*8] =
313 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 314 [Group3_Byte*8] =
315 ByteOp | SrcImm | DstMem | ModRM, 0,
316 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
317 0, 0, 0, 0,
318 [Group3*8] =
41afa025 319 DstMem | SrcImm | ModRM, 0,
6eb06cb2 320 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 321 0, 0, 0, 0,
fd60754e
AK		 322 [Group4*8] =
323 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
324 0, 0, 0, 0, 0, 0,
325 [Group5*8] =
d19292e4
MG		 326 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
327 SrcMem | ModRM | Stack, 0,
ef46f18e 328 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1 329 [Group7*8] =
e92805ac 330 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv,
16286d08 331 SrcNone | ModRM | DstMem | Mov, 0,
e92805ac 332 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv,
2db2c2eb
GN		 333 [Group8*8] =
334 0, 0, 0, 0,
335 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
336 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
60a29d4e
GN		 337 [Group9*8] =
338 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 339};
340
45ed60b3 341static u32 group2_table[] = {
d95058a1 342 [Group7*8] =
e92805ac 343 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM,
16286d08
AK		 344 SrcNone | ModRM | DstMem | Mov, 0,
345 SrcMem16 | ModRM | Mov, 0,
60a29d4e
GN		 346 [Group9*8] =
347 0, 0, 0, 0, 0, 0, 0, 0,
e09d082c
AK		 348};
349
6aa8b732 350/* EFLAGS bit definitions. */
d4c6a154
GN		 351#define EFLG_ID (1<<21)
352#define EFLG_VIP (1<<20)
353#define EFLG_VIF (1<<19)
354#define EFLG_AC (1<<18)
b1d86143
AP		 355#define EFLG_VM (1<<17)
356#define EFLG_RF (1<<16)
d4c6a154
GN		 357#define EFLG_IOPL (3<<12)
358#define EFLG_NT (1<<14)
6aa8b732
AK		 359#define EFLG_OF (1<<11)
360#define EFLG_DF (1<<10)
b1d86143 361#define EFLG_IF (1<<9)
d4c6a154 362#define EFLG_TF (1<<8)
6aa8b732
AK		 363#define EFLG_SF (1<<7)
364#define EFLG_ZF (1<<6)
365#define EFLG_AF (1<<4)
366#define EFLG_PF (1<<2)
367#define EFLG_CF (1<<0)
368
369/*
370 * Instruction emulation:
371 * Most instructions are emulated directly via a fragment of inline assembly
372 * code. This allows us to save/restore EFLAGS and thus very easily pick up
373 * any modified flags.
374 */
375
05b3e0c2 376#if defined(CONFIG_X86_64)
6aa8b732
AK		 377#define _LO32 "k" /* force 32-bit operand */
378#define _STK "%%rsp" /* stack pointer */
379#elif defined(__i386__)
380#define _LO32 "" /* force 32-bit operand */
381#define _STK "%%esp" /* stack pointer */
382#endif
383
384/*
385 * These EFLAGS bits are restored from saved value during emulation, and
386 * any changes are written back to the saved value after emulation.
387 */
388#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
389
390/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 391#define _PRE_EFLAGS(_sav, _msk, _tmp) \
392 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
393 "movl %"_sav",%"_LO32 _tmp"; " \
394 "push %"_tmp"; " \
395 "push %"_tmp"; " \
396 "movl %"_msk",%"_LO32 _tmp"; " \
397 "andl %"_LO32 _tmp",("_STK"); " \
398 "pushf; " \
399 "notl %"_LO32 _tmp"; " \
400 "andl %"_LO32 _tmp",("_STK"); " \
401 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
402 "pop %"_tmp"; " \
403 "orl %"_LO32 _tmp",("_STK"); " \
404 "popf; " \
405 "pop %"_sav"; "
6aa8b732
AK		 406
407/* After executing instruction: write-back necessary bits in EFLAGS. */
408#define _POST_EFLAGS(_sav, _msk, _tmp) \
409 /* _sav |= EFLAGS & _msk; */ \
410 "pushf; " \
411 "pop %"_tmp"; " \
412 "andl %"_msk",%"_LO32 _tmp"; " \
413 "orl %"_LO32 _tmp",%"_sav"; "
414
dda96d8f
AK		 415#ifdef CONFIG_X86_64
416#define ON64(x) x
417#else
418#define ON64(x)
419#endif
420
6b7ad61f
AK		 421#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
422 do { \
423 __asm__ __volatile__ ( \
424 _PRE_EFLAGS("0", "4", "2") \
425 _op _suffix " %"_x"3,%1; " \
426 _POST_EFLAGS("0", "4", "2") \
427 : "=m" (_eflags), "=m" ((_dst).val), \
428 "=&r" (_tmp) \
429 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 430 } while (0)
6b7ad61f
AK		 431
432
6aa8b732
AK		 433/* Raw emulation: instruction has two explicit operands. */
434#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 435 do { \
436 unsigned long _tmp; \
437 \
438 switch ((_dst).bytes) { \
439 case 2: \
440 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
441 break; \
442 case 4: \
443 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
444 break; \
445 case 8: \
446 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
447 break; \
448 } \
6aa8b732
AK		 449 } while (0)
450
451#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
452 do { \
6b7ad61f 453 unsigned long _tmp; \
d77c26fc 454 switch ((_dst).bytes) { \
6aa8b732 455 case 1: \
6b7ad61f 456 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 457 break; \
458 default: \
459 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
460 _wx, _wy, _lx, _ly, _qx, _qy); \
461 break; \
462 } \
463 } while (0)
464
465/* Source operand is byte-sized and may be restricted to just %cl. */
466#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
467 __emulate_2op(_op, _src, _dst, _eflags, \
468 "b", "c", "b", "c", "b", "c", "b", "c")
469
470/* Source operand is byte, word, long or quad sized. */
471#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
472 __emulate_2op(_op, _src, _dst, _eflags, \
473 "b", "q", "w", "r", _LO32, "r", "", "r")
474
475/* Source operand is word, long or quad sized. */
476#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
477 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
478 "w", "r", _LO32, "r", "", "r")
479
d175226a
GT		 480/* Instruction has three operands and one operand is stored in ECX register */
481#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
482 do { \
483 unsigned long _tmp; \
484 _type _clv = (_cl).val; \
485 _type _srcv = (_src).val; \
486 _type _dstv = (_dst).val; \
487 \
488 __asm__ __volatile__ ( \
489 _PRE_EFLAGS("0", "5", "2") \
490 _op _suffix " %4,%1 \n" \
491 _POST_EFLAGS("0", "5", "2") \
492 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
493 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
494 ); \
495 \
496 (_cl).val = (unsigned long) _clv; \
497 (_src).val = (unsigned long) _srcv; \
498 (_dst).val = (unsigned long) _dstv; \
499 } while (0)
500
501#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
502 do { \
503 switch ((_dst).bytes) { \
504 case 2: \
505 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
506 "w", unsigned short); \
507 break; \
508 case 4: \
509 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
510 "l", unsigned int); \
511 break; \
512 case 8: \
513 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
514 "q", unsigned long)); \
515 break; \
516 } \
517 } while (0)
518
dda96d8f 519#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 520 do { \
521 unsigned long _tmp; \
522 \
dda96d8f
AK		 523 __asm__ __volatile__ ( \
524 _PRE_EFLAGS("0", "3", "2") \
525 _op _suffix " %1; " \
526 _POST_EFLAGS("0", "3", "2") \
527 : "=m" (_eflags), "+m" ((_dst).val), \
528 "=&r" (_tmp) \
529 : "i" (EFLAGS_MASK)); \
530 } while (0)
531
532/* Instruction has only one explicit operand (no source operand). */
533#define emulate_1op(_op, _dst, _eflags) \
534 do { \
d77c26fc 535 switch ((_dst).bytes) { \
dda96d8f
AK		 536 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
537 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
538 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
539 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 540 } \
541 } while (0)
542
6aa8b732
AK		 543/* Fetch next part of the instruction being emulated. */
544#define insn_fetch(_type, _size, _eip) \
545({ unsigned long _x; \
62266869 546 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 547 if (rc != 0) \
6aa8b732
AK		 548 goto done; \
549 (_eip) += (_size); \
550 (_type)_x; \
551})
552
ddcb2885
HH		 553static inline unsigned long ad_mask(struct decode_cache *c)
554{
555 return (1UL << (c->ad_bytes << 3)) - 1;
556}
557
6aa8b732 558/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 559static inline unsigned long
560address_mask(struct decode_cache *c, unsigned long reg)
561{
562 if (c->ad_bytes == sizeof(unsigned long))
563 return reg;
564 else
565 return reg & ad_mask(c);
566}
567
568static inline unsigned long
569register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
570{
571 return base + address_mask(c, reg);
572}
573
7a957275
HH		 574static inline void
575register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
576{
577 if (c->ad_bytes == sizeof(unsigned long))
578 *reg += inc;
579 else
580 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
581}
6aa8b732 582
7a957275
HH		 583static inline void jmp_rel(struct decode_cache *c, int rel)
584{
585 register_address_increment(c, &c->eip, rel);
586}
098c937b 587
7a5b56df
AK		 588static void set_seg_override(struct decode_cache *c, int seg)
589{
590 c->has_seg_override = true;
591 c->seg_override = seg;
592}
593
594static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
595{
596 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
597 return 0;
598
599 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
600}
601
602static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
603 struct decode_cache *c)
604{
605 if (!c->has_seg_override)
606 return 0;
607
608 return seg_base(ctxt, c->seg_override);
609}
610
611static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
612{
613 return seg_base(ctxt, VCPU_SREG_ES);
614}
615
616static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
617{
618 return seg_base(ctxt, VCPU_SREG_SS);
619}
620
62266869
AK		 621static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
622 struct x86_emulate_ops *ops,
623 unsigned long linear, u8 *dest)
624{
625 struct fetch_cache *fc = &ctxt->decode.fetch;
626 int rc;
627 int size;
628
629 if (linear < fc->start || linear >= fc->end) {
630 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
1871c602 631 rc = ops->fetch(linear, fc->data, size, ctxt->vcpu, NULL);
62266869
AK		 632 if (rc)
633 return rc;
634 fc->start = linear;
635 fc->end = linear + size;
636 }
637 *dest = fc->data[linear - fc->start];
638 return 0;
639}
640
641static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
642 struct x86_emulate_ops *ops,
643 unsigned long eip, void *dest, unsigned size)
644{
645 int rc = 0;
646
eb3c79e6
AK		 647 /* x86 instructions are limited to 15 bytes. */
648 if (eip + size - ctxt->decode.eip_orig > 15)
649 return X86EMUL_UNHANDLEABLE;
62266869
AK		 650 eip += ctxt->cs_base;
651 while (size--) {
652 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
653 if (rc)
654 return rc;
655 }
656 return 0;
657}
658
1e3c5cb0
RR		 659/*
660 * Given the 'reg' portion of a ModRM byte, and a register block, return a
661 * pointer into the block that addresses the relevant register.
662 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
663 */
664static void *decode_register(u8 modrm_reg, unsigned long *regs,
665 int highbyte_regs)
6aa8b732
AK		 666{
667 void *p;
668
669 p = &regs[modrm_reg];
670 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
671 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
672 return p;
673}
674
675static int read_descriptor(struct x86_emulate_ctxt *ctxt,
676 struct x86_emulate_ops *ops,
677 void *ptr,
678 u16 *size, unsigned long *address, int op_bytes)
679{
680 int rc;
681
682 if (op_bytes == 2)
683 op_bytes = 3;
684 *address = 0;
cebff02b 685 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 686 ctxt->vcpu, NULL);
6aa8b732
AK		 687 if (rc)
688 return rc;
cebff02b 689 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 690 ctxt->vcpu, NULL);
6aa8b732
AK		 691 return rc;
692}
693
bbe9abbd
NK		 694static int test_cc(unsigned int condition, unsigned int flags)
695{
696 int rc = 0;
697
698 switch ((condition & 15) >> 1) {
699 case 0: /* o */
700 rc |= (flags & EFLG_OF);
701 break;
702 case 1: /* b/c/nae */
703 rc |= (flags & EFLG_CF);
704 break;
705 case 2: /* z/e */
706 rc |= (flags & EFLG_ZF);
707 break;
708 case 3: /* be/na */
709 rc |= (flags & (EFLG_CF|EFLG_ZF));
710 break;
711 case 4: /* s */
712 rc |= (flags & EFLG_SF);
713 break;
714 case 5: /* p/pe */
715 rc |= (flags & EFLG_PF);
716 break;
717 case 7: /* le/ng */
718 rc |= (flags & EFLG_ZF);
719 /* fall through */
720 case 6: /* l/nge */
721 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
722 break;
723 }
724
725 /* Odd condition identifiers (lsb == 1) have inverted sense. */
726 return (!!rc ^ (condition & 1));
727}
728
3c118e24
AK		 729static void decode_register_operand(struct operand *op,
730 struct decode_cache *c,
3c118e24
AK		 731 int inhibit_bytereg)
732{
33615aa9 733 unsigned reg = c->modrm_reg;
9f1ef3f8 734 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 735
736 if (!(c->d & ModRM))
737 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 738 op->type = OP_REG;
739 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 740 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 741 op->val = *(u8 *)op->ptr;
742 op->bytes = 1;
743 } else {
33615aa9 744 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 745 op->bytes = c->op_bytes;
746 switch (op->bytes) {
747 case 2:
748 op->val = *(u16 *)op->ptr;
749 break;
750 case 4:
751 op->val = *(u32 *)op->ptr;
752 break;
753 case 8:
754 op->val = *(u64 *) op->ptr;
755 break;
756 }
757 }
758 op->orig_val = op->val;
759}
760
1c73ef66
AK		 761static int decode_modrm(struct x86_emulate_ctxt *ctxt,
762 struct x86_emulate_ops *ops)
763{
764 struct decode_cache *c = &ctxt->decode;
765 u8 sib;
f5b4edcd 766 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 767 int rc = 0;
768
769 if (c->rex_prefix) {
770 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
771 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
772 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
773 }
774
775 c->modrm = insn_fetch(u8, 1, c->eip);
776 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
777 c->modrm_reg |= (c->modrm & 0x38) >> 3;
778 c->modrm_rm |= (c->modrm & 0x07);
779 c->modrm_ea = 0;
780 c->use_modrm_ea = 1;
781
782 if (c->modrm_mod == 3) {
107d6d2e
AK		 783 c->modrm_ptr = decode_register(c->modrm_rm,
784 c->regs, c->d & ByteOp);
785 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 786 return rc;
787 }
788
789 if (c->ad_bytes == 2) {
790 unsigned bx = c->regs[VCPU_REGS_RBX];
791 unsigned bp = c->regs[VCPU_REGS_RBP];
792 unsigned si = c->regs[VCPU_REGS_RSI];
793 unsigned di = c->regs[VCPU_REGS_RDI];
794
795 /* 16-bit ModR/M decode. */
796 switch (c->modrm_mod) {
797 case 0:
798 if (c->modrm_rm == 6)
799 c->modrm_ea += insn_fetch(u16, 2, c->eip);
800 break;
801 case 1:
802 c->modrm_ea += insn_fetch(s8, 1, c->eip);
803 break;
804 case 2:
805 c->modrm_ea += insn_fetch(u16, 2, c->eip);
806 break;
807 }
808 switch (c->modrm_rm) {
809 case 0:
810 c->modrm_ea += bx + si;
811 break;
812 case 1:
813 c->modrm_ea += bx + di;
814 break;
815 case 2:
816 c->modrm_ea += bp + si;
817 break;
818 case 3:
819 c->modrm_ea += bp + di;
820 break;
821 case 4:
822 c->modrm_ea += si;
823 break;
824 case 5:
825 c->modrm_ea += di;
826 break;
827 case 6:
828 if (c->modrm_mod != 0)
829 c->modrm_ea += bp;
830 break;
831 case 7:
832 c->modrm_ea += bx;
833 break;
834 }
835 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
836 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 837 if (!c->has_seg_override)
838 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 839 c->modrm_ea = (u16)c->modrm_ea;
840 } else {
841 /* 32/64-bit ModR/M decode. */
84411d85 842 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 843 sib = insn_fetch(u8, 1, c->eip);
844 index_reg |= (sib >> 3) & 7;
845 base_reg |= sib & 7;
846 scale = sib >> 6;
847
dc71d0f1
AK		 848 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
849 c->modrm_ea += insn_fetch(s32, 4, c->eip);
850 else
1c73ef66 851 c->modrm_ea += c->regs[base_reg];
dc71d0f1 852 if (index_reg != 4)
1c73ef66 853 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 854 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
855 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 856 c->rip_relative = 1;
84411d85 857 } else
1c73ef66 858 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 859 switch (c->modrm_mod) {
860 case 0:
861 if (c->modrm_rm == 5)
862 c->modrm_ea += insn_fetch(s32, 4, c->eip);
863 break;
864 case 1:
865 c->modrm_ea += insn_fetch(s8, 1, c->eip);
866 break;
867 case 2:
868 c->modrm_ea += insn_fetch(s32, 4, c->eip);
869 break;
870 }
871 }
1c73ef66
AK		 872done:
873 return rc;
874}
875
876static int decode_abs(struct x86_emulate_ctxt *ctxt,
877 struct x86_emulate_ops *ops)
878{
879 struct decode_cache *c = &ctxt->decode;
880 int rc = 0;
881
882 switch (c->ad_bytes) {
883 case 2:
884 c->modrm_ea = insn_fetch(u16, 2, c->eip);
885 break;
886 case 4:
887 c->modrm_ea = insn_fetch(u32, 4, c->eip);
888 break;
889 case 8:
890 c->modrm_ea = insn_fetch(u64, 8, c->eip);
891 break;
892 }
893done:
894 return rc;
895}
896
6aa8b732 897int
8b4caf66 898x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 899{
e4e03ded 900 struct decode_cache *c = &ctxt->decode;
6aa8b732 901 int rc = 0;
6aa8b732 902 int mode = ctxt->mode;
e09d082c 903 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 904
905 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 906
e4e03ded 907 memset(c, 0, sizeof(struct decode_cache));
eb3c79e6 908 c->eip = c->eip_orig = kvm_rip_read(ctxt->vcpu);
7a5b56df 909 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 910 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 911
912 switch (mode) {
913 case X86EMUL_MODE_REAL:
a0044755 914 case X86EMUL_MODE_VM86:
6aa8b732 915 case X86EMUL_MODE_PROT16:
f21b8bf4 916 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 917 break;
918 case X86EMUL_MODE_PROT32:
f21b8bf4 919 def_op_bytes = def_ad_bytes = 4;
6aa8b732 920 break;
05b3e0c2 921#ifdef CONFIG_X86_64
6aa8b732 922 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 923 def_op_bytes = 4;
924 def_ad_bytes = 8;
6aa8b732
AK		 925 break;
926#endif
927 default:
928 return -1;
929 }
930
f21b8bf4
AK		 931 c->op_bytes = def_op_bytes;
932 c->ad_bytes = def_ad_bytes;
933
6aa8b732 934 /* Legacy prefixes. */
b4c6abfe 935 for (;;) {
e4e03ded 936 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 937 case 0x66: /* operand-size override */
f21b8bf4
AK		 938 /* switch between 2/4 bytes */
939 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 940 break;
941 case 0x67: /* address-size override */
942 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 943 /* switch between 4/8 bytes */
f21b8bf4 944 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 945 else
e4e03ded 946 /* switch between 2/4 bytes */
f21b8bf4 947 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 948 break;
7a5b56df 949 case 0x26: /* ES override */
6aa8b732 950 case 0x2e: /* CS override */
7a5b56df 951 case 0x36: /* SS override */
6aa8b732 952 case 0x3e: /* DS override */
7a5b56df 953 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 954 break;
955 case 0x64: /* FS override */
6aa8b732 956 case 0x65: /* GS override */
7a5b56df 957 set_seg_override(c, c->b & 7);
6aa8b732 958 break;
b4c6abfe
LV		 959 case 0x40 ... 0x4f: /* REX */
960 if (mode != X86EMUL_MODE_PROT64)
961 goto done_prefixes;
33615aa9 962 c->rex_prefix = c->b;
b4c6abfe 963 continue;
6aa8b732 964 case 0xf0: /* LOCK */
e4e03ded 965 c->lock_prefix = 1;
6aa8b732 966 break;
ae6200ba 967 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 968 c->rep_prefix = REPNE_PREFIX;
969 break;
6aa8b732 970 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 971 c->rep_prefix = REPE_PREFIX;
6aa8b732 972 break;
6aa8b732
AK		 973 default:
974 goto done_prefixes;
975 }
b4c6abfe
LV		 976
977 /* Any legacy prefix after a REX prefix nullifies its effect. */
978
33615aa9 979 c->rex_prefix = 0;
6aa8b732
AK		 980 }
981
982done_prefixes:
983
984 /* REX prefix. */
1c73ef66 985 if (c->rex_prefix)
33615aa9 986 if (c->rex_prefix & 8)
e4e03ded 987 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 988
989 /* Opcode byte(s). */
e4e03ded
LV		 990 c->d = opcode_table[c->b];
991 if (c->d == 0) {
6aa8b732 992 /* Two-byte opcode? */
e4e03ded
LV		 993 if (c->b == 0x0f) {
994 c->twobyte = 1;
995 c->b = insn_fetch(u8, 1, c->eip);
996 c->d = twobyte_table[c->b];
6aa8b732 997 }
e09d082c 998 }
6aa8b732 999
d8769fed
MG		 1000 if (mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
1001 kvm_report_emulation_failure(ctxt->vcpu, "invalid x86/64 instruction");;
1002 return -1;
1003 }
1004
e09d082c
AK		 1005 if (c->d & Group) {
1006 group = c->d & GroupMask;
1007 c->modrm = insn_fetch(u8, 1, c->eip);
1008 --c->eip;
1009
1010 group = (group << 3) + ((c->modrm >> 3) & 7);
1011 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
1012 c->d = group2_table[group];
1013 else
1014 c->d = group_table[group];
1015 }
1016
1017 /* Unrecognised? */
1018 if (c->d == 0) {
1019 DPRINTF("Cannot emulate %02x\n", c->b);
1020 return -1;
6aa8b732
AK		 1021 }
1022
6e3d5dfb
AK		 1023 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1024 c->op_bytes = 8;
1025
6aa8b732 1026 /* ModRM and SIB bytes. */
1c73ef66
AK		 1027 if (c->d & ModRM)
1028 rc = decode_modrm(ctxt, ops);
1029 else if (c->d & MemAbs)
1030 rc = decode_abs(ctxt, ops);
1031 if (rc)
1032 goto done;
6aa8b732 1033
7a5b56df
AK		 1034 if (!c->has_seg_override)
1035 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 1036
7a5b56df
AK		 1037 if (!(!c->twobyte && c->b == 0x8d))
1038 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 1039
1040 if (c->ad_bytes != 8)
1041 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 1042 /*
1043 * Decode and fetch the source operand: register, memory
1044 * or immediate.
1045 */
e4e03ded 1046 switch (c->d & SrcMask) {
6aa8b732
AK		 1047 case SrcNone:
1048 break;
1049 case SrcReg:
9f1ef3f8 1050 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1051 break;
1052 case SrcMem16:
e4e03ded 1053 c->src.bytes = 2;
6aa8b732
AK		 1054 goto srcmem_common;
1055 case SrcMem32:
e4e03ded 1056 c->src.bytes = 4;
6aa8b732
AK		 1057 goto srcmem_common;
1058 case SrcMem:
e4e03ded
LV		 1059 c->src.bytes = (c->d & ByteOp) ? 1 :
1060 c->op_bytes;
b85b9ee9 1061 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1062 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1063 break;
d77c26fc 1064 srcmem_common:
4e62417b
AJ		 1065 /*
1066 * For instructions with a ModR/M byte, switch to register
1067 * access if Mod = 3.
1068 */
e4e03ded
LV		 1069 if ((c->d & ModRM) && c->modrm_mod == 3) {
1070 c->src.type = OP_REG;
66b85505 1071 c->src.val = c->modrm_val;
107d6d2e 1072 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1073 break;
1074 }
e4e03ded 1075 c->src.type = OP_MEM;
6aa8b732
AK		 1076 break;
1077 case SrcImm:
c9eaf20f 1078 case SrcImmU:
e4e03ded
LV		 1079 c->src.type = OP_IMM;
1080 c->src.ptr = (unsigned long *)c->eip;
1081 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1082 if (c->src.bytes == 8)
1083 c->src.bytes = 4;
6aa8b732 1084 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1085 switch (c->src.bytes) {
6aa8b732 1086 case 1:
e4e03ded 1087 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1088 break;
1089 case 2:
e4e03ded 1090 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1091 break;
1092 case 4:
e4e03ded 1093 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1094 break;
1095 }
c9eaf20f
AK		 1096 if ((c->d & SrcMask) == SrcImmU) {
1097 switch (c->src.bytes) {
1098 case 1:
1099 c->src.val &= 0xff;
1100 break;
1101 case 2:
1102 c->src.val &= 0xffff;
1103 break;
1104 case 4:
1105 c->src.val &= 0xffffffff;
1106 break;
1107 }
1108 }
6aa8b732
AK		 1109 break;
1110 case SrcImmByte:
341de7e3 1111 case SrcImmUByte:
e4e03ded
LV		 1112 c->src.type = OP_IMM;
1113 c->src.ptr = (unsigned long *)c->eip;
1114 c->src.bytes = 1;
341de7e3
GN		 1115 if ((c->d & SrcMask) == SrcImmByte)
1116 c->src.val = insn_fetch(s8, 1, c->eip);
1117 else
1118 c->src.val = insn_fetch(u8, 1, c->eip);
6aa8b732 1119 break;
bfcadf83
GT		 1120 case SrcOne:
1121 c->src.bytes = 1;
1122 c->src.val = 1;
1123 break;
6aa8b732
AK		 1124 }
1125
0dc8d10f
GT		 1126 /*
1127 * Decode and fetch the second source operand: register, memory
1128 * or immediate.
1129 */
1130 switch (c->d & Src2Mask) {
1131 case Src2None:
1132 break;
1133 case Src2CL:
1134 c->src2.bytes = 1;
1135 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1136 break;
1137 case Src2ImmByte:
1138 c->src2.type = OP_IMM;
1139 c->src2.ptr = (unsigned long *)c->eip;
1140 c->src2.bytes = 1;
1141 c->src2.val = insn_fetch(u8, 1, c->eip);
1142 break;
a5f868bd
GN		 1143 case Src2Imm16:
1144 c->src2.type = OP_IMM;
1145 c->src2.ptr = (unsigned long *)c->eip;
1146 c->src2.bytes = 2;
1147 c->src2.val = insn_fetch(u16, 2, c->eip);
1148 break;
0dc8d10f
GT		 1149 case Src2One:
1150 c->src2.bytes = 1;
1151 c->src2.val = 1;
1152 break;
1153 }
1154
038e51de 1155 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1156 switch (c->d & DstMask) {
038e51de
AK		 1157 case ImplicitOps:
1158 /* Special instructions do their own operand decoding. */
8b4caf66 1159 return 0;
038e51de 1160 case DstReg:
9f1ef3f8 1161 decode_register_operand(&c->dst, c,
3c118e24 1162 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1163 break;
1164 case DstMem:
e4e03ded 1165 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1166 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1167 c->dst.type = OP_REG;
66b85505 1168 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1169 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1170 break;
1171 }
8b4caf66
LV		 1172 c->dst.type = OP_MEM;
1173 break;
9c9fddd0
GT		 1174 case DstAcc:
1175 c->dst.type = OP_REG;
1176 c->dst.bytes = c->op_bytes;
1177 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1178 switch (c->op_bytes) {
1179 case 1:
1180 c->dst.val = *(u8 *)c->dst.ptr;
1181 break;
1182 case 2:
1183 c->dst.val = *(u16 *)c->dst.ptr;
1184 break;
1185 case 4:
1186 c->dst.val = *(u32 *)c->dst.ptr;
1187 break;
1188 }
1189 c->dst.orig_val = c->dst.val;
1190 break;
8b4caf66
LV		 1191 }
1192
f5b4edcd
AK		 1193 if (c->rip_relative)
1194 c->modrm_ea += c->eip;
1195
8b4caf66
LV		 1196done:
1197 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1198}
1199
8cdbd2c9
LV		 1200static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1201{
1202 struct decode_cache *c = &ctxt->decode;
1203
1204 c->dst.type = OP_MEM;
1205 c->dst.bytes = c->op_bytes;
1206 c->dst.val = c->src.val;
7a957275 1207 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1208 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1209 c->regs[VCPU_REGS_RSP]);
1210}
1211
faa5a3ae 1212static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1213 struct x86_emulate_ops *ops,
1214 void *dest, int len)
8cdbd2c9
LV		 1215{
1216 struct decode_cache *c = &ctxt->decode;
1217 int rc;
1218
781d0edc
AK		 1219 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1220 c->regs[VCPU_REGS_RSP]),
350f69dc 1221 dest, len, ctxt->vcpu);
b60d513c 1222 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1223 return rc;
1224
350f69dc 1225 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1226 return rc;
1227}
8cdbd2c9 1228
d4c6a154
GN		 1229static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1230 struct x86_emulate_ops *ops,
1231 void *dest, int len)
1232{
1233 int rc;
1234 unsigned long val, change_mask;
1235 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1236 int cpl = kvm_x86_ops->get_cpl(ctxt->vcpu);
1237
1238 rc = emulate_pop(ctxt, ops, &val, len);
1239 if (rc != X86EMUL_CONTINUE)
1240 return rc;
1241
1242 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1243 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1244
1245 switch(ctxt->mode) {
1246 case X86EMUL_MODE_PROT64:
1247 case X86EMUL_MODE_PROT32:
1248 case X86EMUL_MODE_PROT16:
1249 if (cpl == 0)
1250 change_mask |= EFLG_IOPL;
1251 if (cpl <= iopl)
1252 change_mask |= EFLG_IF;
1253 break;
1254 case X86EMUL_MODE_VM86:
1255 if (iopl < 3) {
1256 kvm_inject_gp(ctxt->vcpu, 0);
1257 return X86EMUL_PROPAGATE_FAULT;
1258 }
1259 change_mask |= EFLG_IF;
1260 break;
1261 default: /* real mode */
1262 change_mask |= (EFLG_IOPL | EFLG_IF);
1263 break;
1264 }
1265
1266 *(unsigned long *)dest =
1267 (ctxt->eflags & ~change_mask) | (val & change_mask);
1268
1269 return rc;
1270}
1271
0934ac9d
MG		 1272static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1273{
1274 struct decode_cache *c = &ctxt->decode;
1275 struct kvm_segment segment;
1276
1277 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg);
1278
1279 c->src.val = segment.selector;
1280 emulate_push(ctxt);
1281}
1282
1283static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1284 struct x86_emulate_ops *ops, int seg)
1285{
1286 struct decode_cache *c = &ctxt->decode;
1287 unsigned long selector;
1288 int rc;
1289
1290 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1291 if (rc != 0)
1292 return rc;
1293
1294 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)selector, 1, seg);
1295 return rc;
1296}
1297
abcf14b5
MG		 1298static void emulate_pusha(struct x86_emulate_ctxt *ctxt)
1299{
1300 struct decode_cache *c = &ctxt->decode;
1301 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1302 int reg = VCPU_REGS_RAX;
1303
1304 while (reg <= VCPU_REGS_RDI) {
1305 (reg == VCPU_REGS_RSP) ?
1306 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1307
1308 emulate_push(ctxt);
1309 ++reg;
1310 }
1311}
1312
1313static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1314 struct x86_emulate_ops *ops)
1315{
1316 struct decode_cache *c = &ctxt->decode;
1317 int rc = 0;
1318 int reg = VCPU_REGS_RDI;
1319
1320 while (reg >= VCPU_REGS_RAX) {
1321 if (reg == VCPU_REGS_RSP) {
1322 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1323 c->op_bytes);
1324 --reg;
1325 }
1326
1327 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1328 if (rc != 0)
1329 break;
1330 --reg;
1331 }
1332 return rc;
1333}
1334
faa5a3ae
AK		 1335static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1336 struct x86_emulate_ops *ops)
1337{
1338 struct decode_cache *c = &ctxt->decode;
1339 int rc;
1340
350f69dc 1341 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1342 if (rc != 0)
1343 return rc;
8cdbd2c9
LV		 1344 return 0;
1345}
1346
05f086f8 1347static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1348{
05f086f8 1349 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1350 switch (c->modrm_reg) {
1351 case 0: /* rol */
05f086f8 1352 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1353 break;
1354 case 1: /* ror */
05f086f8 1355 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1356 break;
1357 case 2: /* rcl */
05f086f8 1358 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1359 break;
1360 case 3: /* rcr */
05f086f8 1361 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1362 break;
1363 case 4: /* sal/shl */
1364 case 6: /* sal/shl */
05f086f8 1365 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1366 break;
1367 case 5: /* shr */
05f086f8 1368 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1369 break;
1370 case 7: /* sar */
05f086f8 1371 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1372 break;
1373 }
1374}
1375
1376static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1377 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1378{
1379 struct decode_cache *c = &ctxt->decode;
1380 int rc = 0;
1381
1382 switch (c->modrm_reg) {
1383 case 0 ... 1: /* test */
05f086f8 1384 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1385 break;
1386 case 2: /* not */
1387 c->dst.val = ~c->dst.val;
1388 break;
1389 case 3: /* neg */
05f086f8 1390 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1391 break;
1392 default:
1393 DPRINTF("Cannot emulate %02x\n", c->b);
1394 rc = X86EMUL_UNHANDLEABLE;
1395 break;
1396 }
8cdbd2c9
LV		 1397 return rc;
1398}
1399
1400static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1401 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1402{
1403 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1404
1405 switch (c->modrm_reg) {
1406 case 0: /* inc */
05f086f8 1407 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1408 break;
1409 case 1: /* dec */
05f086f8 1410 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1411 break;
d19292e4
MG		 1412 case 2: /* call near abs */ {
1413 long int old_eip;
1414 old_eip = c->eip;
1415 c->eip = c->src.val;
1416 c->src.val = old_eip;
1417 emulate_push(ctxt);
1418 break;
1419 }
8cdbd2c9 1420 case 4: /* jmp abs */
fd60754e 1421 c->eip = c->src.val;
8cdbd2c9
LV		 1422 break;
1423 case 6: /* push */
fd60754e 1424 emulate_push(ctxt);
8cdbd2c9 1425 break;
8cdbd2c9
LV		 1426 }
1427 return 0;
1428}
1429
1430static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1431 struct x86_emulate_ops *ops,
e8d8d7fe 1432 unsigned long memop)
8cdbd2c9
LV		 1433{
1434 struct decode_cache *c = &ctxt->decode;
1435 u64 old, new;
1436 int rc;
1437
e8d8d7fe 1438 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
b60d513c 1439 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 1440 return rc;
1441
1442 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1443 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1444
1445 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1446 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1447 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1448
1449 } else {
1450 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1451 (u32) c->regs[VCPU_REGS_RBX];
1452
e8d8d7fe 1453 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
b60d513c 1454 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1455 return rc;
05f086f8 1456 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1457 }
1458 return 0;
1459}
1460
a77ab5ea
AK		 1461static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1462 struct x86_emulate_ops *ops)
1463{
1464 struct decode_cache *c = &ctxt->decode;
1465 int rc;
1466 unsigned long cs;
1467
1468 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1469 if (rc)
1470 return rc;
1471 if (c->op_bytes == 4)
1472 c->eip = (u32)c->eip;
1473 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1474 if (rc)
1475 return rc;
1476 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1477 return rc;
1478}
1479
8cdbd2c9
LV		 1480static inline int writeback(struct x86_emulate_ctxt *ctxt,
1481 struct x86_emulate_ops *ops)
1482{
1483 int rc;
1484 struct decode_cache *c = &ctxt->decode;
1485
1486 switch (c->dst.type) {
1487 case OP_REG:
1488 /* The 4-byte case *is* correct:
1489 * in 64-bit mode we zero-extend.
1490 */
1491 switch (c->dst.bytes) {
1492 case 1:
1493 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1494 break;
1495 case 2:
1496 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1497 break;
1498 case 4:
1499 *c->dst.ptr = (u32)c->dst.val;
1500 break; /* 64b: zero-ext */
1501 case 8:
1502 *c->dst.ptr = c->dst.val;
1503 break;
1504 }
1505 break;
1506 case OP_MEM:
1507 if (c->lock_prefix)
1508 rc = ops->cmpxchg_emulated(
1509 (unsigned long)c->dst.ptr,
1510 &c->dst.orig_val,
1511 &c->dst.val,
1512 c->dst.bytes,
1513 ctxt->vcpu);
1514 else
1515 rc = ops->write_emulated(
1516 (unsigned long)c->dst.ptr,
1517 &c->dst.val,
1518 c->dst.bytes,
1519 ctxt->vcpu);
b60d513c 1520 if (rc != X86EMUL_CONTINUE)
8cdbd2c9 1521 return rc;
a01af5ec
LV		 1522 break;
1523 case OP_NONE:
1524 /* no writeback */
1525 break;
8cdbd2c9
LV		 1526 default:
1527 break;
1528 }
1529 return 0;
1530}
1531
a3f9d398 1532static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
310b5d30
GC		 1533{
1534 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask);
1535 /*
1536 * an sti; sti; sequence only disable interrupts for the first
1537 * instruction. So, if the last instruction, be it emulated or
1538 * not, left the system with the INT_STI flag enabled, it
1539 * means that the last instruction is an sti. We should not
1540 * leave the flag on in this case. The same goes for mov ss
1541 */
1542 if (!(int_shadow & mask))
1543 ctxt->interruptibility = mask;
1544}
1545
e66bb2cc
AP		 1546static inline void
1547setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1548 struct kvm_segment *cs, struct kvm_segment *ss)
1549{
1550 memset(cs, 0, sizeof(struct kvm_segment));
1551 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
1552 memset(ss, 0, sizeof(struct kvm_segment));
1553
1554 cs->l = 0; /* will be adjusted later */
1555 cs->base = 0; /* flat segment */
1556 cs->g = 1; /* 4kb granularity */
1557 cs->limit = 0xffffffff; /* 4GB limit */
1558 cs->type = 0x0b; /* Read, Execute, Accessed */
1559 cs->s = 1;
1560 cs->dpl = 0; /* will be adjusted later */
1561 cs->present = 1;
1562 cs->db = 1;
1563
1564 ss->unusable = 0;
1565 ss->base = 0; /* flat segment */
1566 ss->limit = 0xffffffff; /* 4GB limit */
1567 ss->g = 1; /* 4kb granularity */
1568 ss->s = 1;
1569 ss->type = 0x03; /* Read/Write, Accessed */
1570 ss->db = 1; /* 32bit stack segment */
1571 ss->dpl = 0;
1572 ss->present = 1;
1573}
1574
1575static int
1576emulate_syscall(struct x86_emulate_ctxt *ctxt)
1577{
1578 struct decode_cache *c = &ctxt->decode;
1579 struct kvm_segment cs, ss;
1580 u64 msr_data;
1581
1582 /* syscall is not available in real mode */
1583 if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
a0044755 1584 || ctxt->mode == X86EMUL_MODE_VM86)
e66bb2cc
AP		 1585 return -1;
1586
1587 setup_syscalls_segments(ctxt, &cs, &ss);
1588
1589 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1590 msr_data >>= 32;
1591 cs.selector = (u16)(msr_data & 0xfffc);
1592 ss.selector = (u16)(msr_data + 8);
1593
1594 if (is_long_mode(ctxt->vcpu)) {
1595 cs.db = 0;
1596 cs.l = 1;
1597 }
1598 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1599 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1600
1601 c->regs[VCPU_REGS_RCX] = c->eip;
1602 if (is_long_mode(ctxt->vcpu)) {
1603#ifdef CONFIG_X86_64
1604 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1605
1606 kvm_x86_ops->get_msr(ctxt->vcpu,
1607 ctxt->mode == X86EMUL_MODE_PROT64 ?
1608 MSR_LSTAR : MSR_CSTAR, &msr_data);
1609 c->eip = msr_data;
1610
1611 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1612 ctxt->eflags &= ~(msr_data | EFLG_RF);
1613#endif
1614 } else {
1615 /* legacy mode */
1616 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1617 c->eip = (u32)msr_data;
1618
1619 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1620 }
1621
1622 return 0;
1623}
1624
8c604352
AP		 1625static int
1626emulate_sysenter(struct x86_emulate_ctxt *ctxt)
1627{
1628 struct decode_cache *c = &ctxt->decode;
1629 struct kvm_segment cs, ss;
1630 u64 msr_data;
1631
1632 /* inject #UD if LOCK prefix is used */
1633 if (c->lock_prefix)
1634 return -1;
1635
a0044755
GN		 1636 /* inject #GP if in real mode */
1637 if (ctxt->mode == X86EMUL_MODE_REAL) {
8c604352
AP		 1638 kvm_inject_gp(ctxt->vcpu, 0);
1639 return -1;
1640 }
1641
1642 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1643 * Therefore, we inject an #UD.
1644 */
1645 if (ctxt->mode == X86EMUL_MODE_PROT64)
1646 return -1;
1647
1648 setup_syscalls_segments(ctxt, &cs, &ss);
1649
1650 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1651 switch (ctxt->mode) {
1652 case X86EMUL_MODE_PROT32:
1653 if ((msr_data & 0xfffc) == 0x0) {
1654 kvm_inject_gp(ctxt->vcpu, 0);
1655 return -1;
1656 }
1657 break;
1658 case X86EMUL_MODE_PROT64:
1659 if (msr_data == 0x0) {
1660 kvm_inject_gp(ctxt->vcpu, 0);
1661 return -1;
1662 }
1663 break;
1664 }
1665
1666 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1667 cs.selector = (u16)msr_data;
1668 cs.selector &= ~SELECTOR_RPL_MASK;
1669 ss.selector = cs.selector + 8;
1670 ss.selector &= ~SELECTOR_RPL_MASK;
1671 if (ctxt->mode == X86EMUL_MODE_PROT64
1672 || is_long_mode(ctxt->vcpu)) {
1673 cs.db = 0;
1674 cs.l = 1;
1675 }
1676
1677 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1678 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1679
1680 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1681 c->eip = msr_data;
1682
1683 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1684 c->regs[VCPU_REGS_RSP] = msr_data;
1685
1686 return 0;
1687}
1688
4668f050
AP		 1689static int
1690emulate_sysexit(struct x86_emulate_ctxt *ctxt)
1691{
1692 struct decode_cache *c = &ctxt->decode;
1693 struct kvm_segment cs, ss;
1694 u64 msr_data;
1695 int usermode;
1696
1697 /* inject #UD if LOCK prefix is used */
1698 if (c->lock_prefix)
1699 return -1;
1700
a0044755
GN		 1701 /* inject #GP if in real mode or Virtual 8086 mode */
1702 if (ctxt->mode == X86EMUL_MODE_REAL ||
1703 ctxt->mode == X86EMUL_MODE_VM86) {
4668f050
AP		 1704 kvm_inject_gp(ctxt->vcpu, 0);
1705 return -1;
1706 }
1707
4668f050
AP		 1708 setup_syscalls_segments(ctxt, &cs, &ss);
1709
1710 if ((c->rex_prefix & 0x8) != 0x0)
1711 usermode = X86EMUL_MODE_PROT64;
1712 else
1713 usermode = X86EMUL_MODE_PROT32;
1714
1715 cs.dpl = 3;
1716 ss.dpl = 3;
1717 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1718 switch (usermode) {
1719 case X86EMUL_MODE_PROT32:
1720 cs.selector = (u16)(msr_data + 16);
1721 if ((msr_data & 0xfffc) == 0x0) {
1722 kvm_inject_gp(ctxt->vcpu, 0);
1723 return -1;
1724 }
1725 ss.selector = (u16)(msr_data + 24);
1726 break;
1727 case X86EMUL_MODE_PROT64:
1728 cs.selector = (u16)(msr_data + 32);
1729 if (msr_data == 0x0) {
1730 kvm_inject_gp(ctxt->vcpu, 0);
1731 return -1;
1732 }
1733 ss.selector = cs.selector + 8;
1734 cs.db = 0;
1735 cs.l = 1;
1736 break;
1737 }
1738 cs.selector |= SELECTOR_RPL_MASK;
1739 ss.selector |= SELECTOR_RPL_MASK;
1740
1741 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
1742 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
1743
1744 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
1745 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
1746
1747 return 0;
1748}
1749
f850e2e6
GN		 1750static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
1751{
1752 int iopl;
1753 if (ctxt->mode == X86EMUL_MODE_REAL)
1754 return false;
1755 if (ctxt->mode == X86EMUL_MODE_VM86)
1756 return true;
1757 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1758 return kvm_x86_ops->get_cpl(ctxt->vcpu) > iopl;
1759}
1760
1761static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1762 struct x86_emulate_ops *ops,
1763 u16 port, u16 len)
1764{
1765 struct kvm_segment tr_seg;
1766 int r;
1767 u16 io_bitmap_ptr;
1768 u8 perm, bit_idx = port & 0x7;
1769 unsigned mask = (1 << len) - 1;
1770
1771 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR);
1772 if (tr_seg.unusable)
1773 return false;
1774 if (tr_seg.limit < 103)
1775 return false;
1776 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu,
1777 NULL);
1778 if (r != X86EMUL_CONTINUE)
1779 return false;
1780 if (io_bitmap_ptr + port/8 > tr_seg.limit)
1781 return false;
1782 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1,
1783 ctxt->vcpu, NULL);
1784 if (r != X86EMUL_CONTINUE)
1785 return false;
1786 if ((perm >> bit_idx) & mask)
1787 return false;
1788 return true;
1789}
1790
1791static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1792 struct x86_emulate_ops *ops,
1793 u16 port, u16 len)
1794{
1795 if (emulator_bad_iopl(ctxt))
1796 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1797 return false;
1798 return true;
1799}
1800
8b4caf66 1801int
1be3aa47 1802x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1803{
e8d8d7fe 1804 unsigned long memop = 0;
8b4caf66 1805 u64 msr_data;
3427318f 1806 unsigned long saved_eip = 0;
8b4caf66 1807 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1808 unsigned int port;
1809 int io_dir_in;
1be3aa47 1810 int rc = 0;
8b4caf66 1811
310b5d30
GC		 1812 ctxt->interruptibility = 0;
1813
3427318f
LV		 1814 /* Shadow copy of register state. Committed on successful emulation.
1815 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1816 * modify them.
1817 */
1818
ad312c7c 1819 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1820 saved_eip = c->eip;
1821
e92805ac
GN		 1822 /* Privileged instruction can be executed only in CPL=0 */
1823 if ((c->d & Priv) && kvm_x86_ops->get_cpl(ctxt->vcpu)) {
1824 kvm_inject_gp(ctxt->vcpu, 0);
1825 goto done;
1826 }
1827
c7e75a3d 1828 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1829 memop = c->modrm_ea;
8b4caf66 1830
b9fa9d6b
AK		 1831 if (c->rep_prefix && (c->d & String)) {
1832 /* All REP prefixes have the same first termination condition */
1833 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1834 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1835 goto done;
1836 }
1837 /* The second termination condition only applies for REPE
1838 * and REPNE. Test if the repeat string operation prefix is
1839 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1840 * corresponding termination condition according to:
1841 * - if REPE/REPZ and ZF = 0 then done
1842 * - if REPNE/REPNZ and ZF = 1 then done
1843 */
1844 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1845 (c->b == 0xae) || (c->b == 0xaf)) {
1846 if ((c->rep_prefix == REPE_PREFIX) &&
1847 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1848 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1849 goto done;
1850 }
1851 if ((c->rep_prefix == REPNE_PREFIX) &&
1852 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1853 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1854 goto done;
1855 }
1856 }
1857 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1858 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1859 }
1860
8b4caf66 1861 if (c->src.type == OP_MEM) {
e8d8d7fe 1862 c->src.ptr = (unsigned long *)memop;
8b4caf66 1863 c->src.val = 0;
d77c26fc
MD		 1864 rc = ops->read_emulated((unsigned long)c->src.ptr,
1865 &c->src.val,
1866 c->src.bytes,
1867 ctxt->vcpu);
b60d513c 1868 if (rc != X86EMUL_CONTINUE)
8b4caf66
LV		 1869 goto done;
1870 c->src.orig_val = c->src.val;
1871 }
1872
1873 if ((c->d & DstMask) == ImplicitOps)
1874 goto special_insn;
1875
1876
1877 if (c->dst.type == OP_MEM) {
e8d8d7fe 1878 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1879 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1880 c->dst.val = 0;
e4e03ded
LV		 1881 if (c->d & BitOp) {
1882 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1883
e4e03ded
LV		 1884 c->dst.ptr = (void *)c->dst.ptr +
1885 (c->src.val & mask) / 8;
038e51de 1886 }
b60d513c
TY		 1887 if (!(c->d & Mov)) {
1888 /* optimisation - avoid slow emulated read */
1889 rc = ops->read_emulated((unsigned long)c->dst.ptr,
1890 &c->dst.val,
1891 c->dst.bytes,
1892 ctxt->vcpu);
1893 if (rc != X86EMUL_CONTINUE)
1894 goto done;
1895 }
038e51de 1896 }
e4e03ded 1897 c->dst.orig_val = c->dst.val;
038e51de 1898
018a98db
AK		 1899special_insn:
1900
e4e03ded 1901 if (c->twobyte)
6aa8b732
AK		 1902 goto twobyte_insn;
1903
e4e03ded 1904 switch (c->b) {
6aa8b732
AK		 1905 case 0x00 ... 0x05:
1906 add: /* add */
05f086f8 1907 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 1908 break;
0934ac9d 1909 case 0x06: /* push es */
0934ac9d
MG		 1910 emulate_push_sreg(ctxt, VCPU_SREG_ES);
1911 break;
1912 case 0x07: /* pop es */
0934ac9d
MG		 1913 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1914 if (rc != 0)
1915 goto done;
1916 break;
6aa8b732
AK		 1917 case 0x08 ... 0x0d:
1918 or: /* or */
05f086f8 1919 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 1920 break;
0934ac9d 1921 case 0x0e: /* push cs */
0934ac9d
MG		 1922 emulate_push_sreg(ctxt, VCPU_SREG_CS);
1923 break;
6aa8b732
AK		 1924 case 0x10 ... 0x15:
1925 adc: /* adc */
05f086f8 1926 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 1927 break;
0934ac9d 1928 case 0x16: /* push ss */
0934ac9d
MG		 1929 emulate_push_sreg(ctxt, VCPU_SREG_SS);
1930 break;
1931 case 0x17: /* pop ss */
0934ac9d
MG		 1932 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1933 if (rc != 0)
1934 goto done;
1935 break;
6aa8b732
AK		 1936 case 0x18 ... 0x1d:
1937 sbb: /* sbb */
05f086f8 1938 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1939 break;
0934ac9d 1940 case 0x1e: /* push ds */
0934ac9d
MG		 1941 emulate_push_sreg(ctxt, VCPU_SREG_DS);
1942 break;
1943 case 0x1f: /* pop ds */
0934ac9d
MG		 1944 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1945 if (rc != 0)
1946 goto done;
1947 break;
aa3a816b 1948 case 0x20 ... 0x25:
6aa8b732 1949 and: /* and */
05f086f8 1950 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1951 break;
1952 case 0x28 ... 0x2d:
1953 sub: /* sub */
05f086f8 1954 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1955 break;
1956 case 0x30 ... 0x35:
1957 xor: /* xor */
05f086f8 1958 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1959 break;
1960 case 0x38 ... 0x3d:
1961 cmp: /* cmp */
05f086f8 1962 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1963 break;
33615aa9
AK		 1964 case 0x40 ... 0x47: /* inc r16/r32 */
1965 emulate_1op("inc", c->dst, ctxt->eflags);
1966 break;
1967 case 0x48 ... 0x4f: /* dec r16/r32 */
1968 emulate_1op("dec", c->dst, ctxt->eflags);
1969 break;
1970 case 0x50 ... 0x57: /* push reg */
2786b014 1971 emulate_push(ctxt);
33615aa9
AK		 1972 break;
1973 case 0x58 ... 0x5f: /* pop reg */
1974 pop_instruction:
350f69dc 1975 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1976 if (rc != 0)
33615aa9 1977 goto done;
33615aa9 1978 break;
abcf14b5
MG		 1979 case 0x60: /* pusha */
1980 emulate_pusha(ctxt);
1981 break;
1982 case 0x61: /* popa */
1983 rc = emulate_popa(ctxt, ops);
1984 if (rc != 0)
1985 goto done;
1986 break;
6aa8b732 1987 case 0x63: /* movsxd */
8b4caf66 1988 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1989 goto cannot_emulate;
e4e03ded 1990 c->dst.val = (s32) c->src.val;
6aa8b732 1991 break;
91ed7a0e 1992 case 0x68: /* push imm */
018a98db 1993 case 0x6a: /* push imm8 */
018a98db
AK		 1994 emulate_push(ctxt);
1995 break;
1996 case 0x6c: /* insb */
1997 case 0x6d: /* insw/insd */
f850e2e6
GN		 1998 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
1999 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2000 kvm_inject_gp(ctxt->vcpu, 0);
2001 goto done;
2002 }
2003 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2004 1,
2005 (c->d & ByteOp) ? 1 : c->op_bytes,
2006 c->rep_prefix ?
e4706772 2007 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2008 (ctxt->eflags & EFLG_DF),
7a5b56df 2009 register_address(c, es_base(ctxt),
018a98db
AK		 2010 c->regs[VCPU_REGS_RDI]),
2011 c->rep_prefix,
2012 c->regs[VCPU_REGS_RDX]) == 0) {
2013 c->eip = saved_eip;
2014 return -1;
2015 }
2016 return 0;
2017 case 0x6e: /* outsb */
2018 case 0x6f: /* outsw/outsd */
f850e2e6
GN		 2019 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2020 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2021 kvm_inject_gp(ctxt->vcpu, 0);
2022 goto done;
2023 }
851ba692 2024 if (kvm_emulate_pio_string(ctxt->vcpu,
018a98db
AK		 2025 0,
2026 (c->d & ByteOp) ? 1 : c->op_bytes,
2027 c->rep_prefix ?
e4706772 2028 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 2029 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 2030 register_address(c,
2031 seg_override_base(ctxt, c),
018a98db
AK		 2032 c->regs[VCPU_REGS_RSI]),
2033 c->rep_prefix,
2034 c->regs[VCPU_REGS_RDX]) == 0) {
2035 c->eip = saved_eip;
2036 return -1;
2037 }
2038 return 0;
b2833e3c 2039 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2040 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2041 jmp_rel(c, c->src.val);
018a98db 2042 break;
6aa8b732 2043 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2044 switch (c->modrm_reg) {
6aa8b732
AK		 2045 case 0:
2046 goto add;
2047 case 1:
2048 goto or;
2049 case 2:
2050 goto adc;
2051 case 3:
2052 goto sbb;
2053 case 4:
2054 goto and;
2055 case 5:
2056 goto sub;
2057 case 6:
2058 goto xor;
2059 case 7:
2060 goto cmp;
2061 }
2062 break;
2063 case 0x84 ... 0x85:
05f086f8 2064 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2065 break;
2066 case 0x86 ... 0x87: /* xchg */
b13354f8 2067 xchg:
6aa8b732 2068 /* Write back the register source. */
e4e03ded 2069 switch (c->dst.bytes) {
6aa8b732 2070 case 1:
e4e03ded 2071 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2072 break;
2073 case 2:
e4e03ded 2074 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2075 break;
2076 case 4:
e4e03ded 2077 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2078 break; /* 64b reg: zero-extend */
2079 case 8:
e4e03ded 2080 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2081 break;
2082 }
2083 /*
2084 * Write back the memory destination with implicit LOCK
2085 * prefix.
2086 */
e4e03ded
LV		 2087 c->dst.val = c->src.val;
2088 c->lock_prefix = 1;
6aa8b732 2089 break;
6aa8b732 2090 case 0x88 ... 0x8b: /* mov */
7de75248 2091 goto mov;
38d5bc6d
GT		 2092 case 0x8c: { /* mov r/m, sreg */
2093 struct kvm_segment segreg;
2094
2095 if (c->modrm_reg <= 5)
2096 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
2097 else {
2098 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
2099 c->modrm);
2100 goto cannot_emulate;
2101 }
2102 c->dst.val = segreg.selector;
2103 break;
2104 }
7e0b54b1 2105 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2106 c->dst.val = c->modrm_ea;
7e0b54b1 2107 break;
4257198a
GT		 2108 case 0x8e: { /* mov seg, r/m16 */
2109 uint16_t sel;
2110 int type_bits;
2111 int err;
2112
2113 sel = c->src.val;
310b5d30
GC		 2114 if (c->modrm_reg == VCPU_SREG_SS)
2115 toggle_interruptibility(ctxt, X86_SHADOW_INT_MOV_SS);
2116
4257198a
GT		 2117 if (c->modrm_reg <= 5) {
2118 type_bits = (c->modrm_reg == 1) ? 9 : 1;
2119 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
2120 type_bits, c->modrm_reg);
2121 } else {
2122 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
2123 c->modrm);
2124 goto cannot_emulate;
2125 }
2126
2127 if (err < 0)
2128 goto cannot_emulate;
2129
2130 c->dst.type = OP_NONE; /* Disable writeback. */
2131 break;
2132 }
6aa8b732 2133 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 2134 rc = emulate_grp1a(ctxt, ops);
2135 if (rc != 0)
6aa8b732 2136 goto done;
6aa8b732 2137 break;
b13354f8
MG		 2138 case 0x90: /* nop / xchg r8,rax */
2139 if (!(c->rex_prefix & 1)) { /* nop */
2140 c->dst.type = OP_NONE;
2141 break;
2142 }
2143 case 0x91 ... 0x97: /* xchg reg,rax */
2144 c->src.type = c->dst.type = OP_REG;
2145 c->src.bytes = c->dst.bytes = c->op_bytes;
2146 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2147 c->src.val = *(c->src.ptr);
2148 goto xchg;
fd2a7608 2149 case 0x9c: /* pushf */
05f086f8 2150 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 2151 emulate_push(ctxt);
2152 break;
535eabcf 2153 case 0x9d: /* popf */
2b48cc75 2154 c->dst.type = OP_REG;
05f086f8 2155 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2156 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2157 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2158 if (rc != X86EMUL_CONTINUE)
2159 goto done;
2160 break;
018a98db
AK		 2161 case 0xa0 ... 0xa1: /* mov */
2162 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2163 c->dst.val = c->src.val;
2164 break;
2165 case 0xa2 ... 0xa3: /* mov */
2166 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
2167 break;
6aa8b732 2168 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 2169 c->dst.type = OP_MEM;
2170 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2171 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2172 es_base(ctxt),
e4e03ded 2173 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2174 rc = ops->read_emulated(register_address(c,
2175 seg_override_base(ctxt, c),
2176 c->regs[VCPU_REGS_RSI]),
e4e03ded 2177 &c->dst.val,
b60d513c
TY		 2178 c->dst.bytes, ctxt->vcpu);
2179 if (rc != X86EMUL_CONTINUE)
6aa8b732 2180 goto done;
7a957275 2181 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2182 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2183 : c->dst.bytes);
7a957275 2184 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2185 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2186 : c->dst.bytes);
6aa8b732
AK		 2187 break;
2188 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 2189 c->src.type = OP_NONE; /* Disable writeback. */
2190 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2191 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 2192 seg_override_base(ctxt, c),
d7e5117a 2193 c->regs[VCPU_REGS_RSI]);
b60d513c
TY		 2194 rc = ops->read_emulated((unsigned long)c->src.ptr,
2195 &c->src.val,
2196 c->src.bytes,
2197 ctxt->vcpu);
2198 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2199 goto done;
2200
2201 c->dst.type = OP_NONE; /* Disable writeback. */
2202 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2203 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2204 es_base(ctxt),
d7e5117a 2205 c->regs[VCPU_REGS_RDI]);
b60d513c
TY		 2206 rc = ops->read_emulated((unsigned long)c->dst.ptr,
2207 &c->dst.val,
2208 c->dst.bytes,
2209 ctxt->vcpu);
2210 if (rc != X86EMUL_CONTINUE)
d7e5117a
GT		 2211 goto done;
2212
2213 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2214
2215 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2216
7a957275 2217 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 2218 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
2219 : c->src.bytes);
7a957275 2220 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 2221 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
2222 : c->dst.bytes);
2223
2224 break;
6aa8b732 2225 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 2226 c->dst.type = OP_MEM;
2227 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 2228 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 2229 es_base(ctxt),
a7e6c88a 2230 c->regs[VCPU_REGS_RDI]);
e4e03ded 2231 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 2232 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 2233 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2234 : c->dst.bytes);
6aa8b732
AK		 2235 break;
2236 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 2237 c->dst.type = OP_REG;
2238 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2239 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
b60d513c
TY		 2240 rc = ops->read_emulated(register_address(c,
2241 seg_override_base(ctxt, c),
2242 c->regs[VCPU_REGS_RSI]),
2243 &c->dst.val,
2244 c->dst.bytes,
2245 ctxt->vcpu);
2246 if (rc != X86EMUL_CONTINUE)
6aa8b732 2247 goto done;
7a957275 2248 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 2249 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 2250 : c->dst.bytes);
6aa8b732
AK		 2251 break;
2252 case 0xae ... 0xaf: /* scas */
2253 DPRINTF("Urk! I don't handle SCAS.\n");
2254 goto cannot_emulate;
a5e2e82b 2255 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2256 goto mov;
018a98db
AK		 2257 case 0xc0 ... 0xc1:
2258 emulate_grp2(ctxt);
2259 break;
111de5d6 2260 case 0xc3: /* ret */
cf5de4f8 2261 c->dst.type = OP_REG;
111de5d6 2262 c->dst.ptr = &c->eip;
cf5de4f8 2263 c->dst.bytes = c->op_bytes;
111de5d6 2264 goto pop_instruction;
018a98db
AK		 2265 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2266 mov:
2267 c->dst.val = c->src.val;
2268 break;
a77ab5ea
AK		 2269 case 0xcb: /* ret far */
2270 rc = emulate_ret_far(ctxt, ops);
2271 if (rc)
2272 goto done;
2273 break;
018a98db
AK		 2274 case 0xd0 ... 0xd1: /* Grp2 */
2275 c->src.val = 1;
2276 emulate_grp2(ctxt);
2277 break;
2278 case 0xd2 ... 0xd3: /* Grp2 */
2279 c->src.val = c->regs[VCPU_REGS_RCX];
2280 emulate_grp2(ctxt);
2281 break;
a6a3034c
MG		 2282 case 0xe4: /* inb */
2283 case 0xe5: /* in */
84ce66a6 2284 port = c->src.val;
a6a3034c
MG		 2285 io_dir_in = 1;
2286 goto do_io;
2287 case 0xe6: /* outb */
2288 case 0xe7: /* out */
84ce66a6 2289 port = c->src.val;
a6a3034c
MG		 2290 io_dir_in = 0;
2291 goto do_io;
1a52e051 2292 case 0xe8: /* call (near) */ {
d53c4777 2293 long int rel = c->src.val;
e4e03ded 2294 c->src.val = (unsigned long) c->eip;
7a957275 2295 jmp_rel(c, rel);
8cdbd2c9
LV		 2296 emulate_push(ctxt);
2297 break;
1a52e051
NK		 2298 }
2299 case 0xe9: /* jmp rel */
954cd36f 2300 goto jmp;
782b877c
GN		 2301 case 0xea: /* jmp far */
2302 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
2303 VCPU_SREG_CS) < 0) {
954cd36f
GT		 2304 DPRINTF("jmp far: Failed to load CS descriptor\n");
2305 goto cannot_emulate;
2306 }
2307
782b877c 2308 c->eip = c->src.val;
954cd36f 2309 break;
954cd36f
GT		 2310 case 0xeb:
2311 jmp: /* jmp rel short */
7a957275 2312 jmp_rel(c, c->src.val);
a01af5ec 2313 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 2314 break;
a6a3034c
MG		 2315 case 0xec: /* in al,dx */
2316 case 0xed: /* in (e/r)ax,dx */
2317 port = c->regs[VCPU_REGS_RDX];
2318 io_dir_in = 1;
2319 goto do_io;
2320 case 0xee: /* out al,dx */
2321 case 0xef: /* out (e/r)ax,dx */
2322 port = c->regs[VCPU_REGS_RDX];
2323 io_dir_in = 0;
f850e2e6
GN		 2324 do_io:
2325 if (!emulator_io_permited(ctxt, ops, port,
2326 (c->d & ByteOp) ? 1 : c->op_bytes)) {
2327 kvm_inject_gp(ctxt->vcpu, 0);
2328 goto done;
2329 }
2330 if (kvm_emulate_pio(ctxt->vcpu, io_dir_in,
a6a3034c
MG		 2331 (c->d & ByteOp) ? 1 : c->op_bytes,
2332 port) != 0) {
2333 c->eip = saved_eip;
2334 goto cannot_emulate;
2335 }
e93f36bc 2336 break;
111de5d6 2337 case 0xf4: /* hlt */
ad312c7c 2338 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 2339 break;
111de5d6
AK		 2340 case 0xf5: /* cmc */
2341 /* complement carry flag from eflags reg */
2342 ctxt->eflags ^= EFLG_CF;
2343 c->dst.type = OP_NONE; /* Disable writeback. */
2344 break;
018a98db
AK		 2345 case 0xf6 ... 0xf7: /* Grp3 */
2346 rc = emulate_grp3(ctxt, ops);
2347 if (rc != 0)
2348 goto done;
2349 break;
111de5d6
AK		 2350 case 0xf8: /* clc */
2351 ctxt->eflags &= ~EFLG_CF;
2352 c->dst.type = OP_NONE; /* Disable writeback. */
2353 break;
2354 case 0xfa: /* cli */
f850e2e6
GN		 2355 if (emulator_bad_iopl(ctxt))
2356 kvm_inject_gp(ctxt->vcpu, 0);
2357 else {
2358 ctxt->eflags &= ~X86_EFLAGS_IF;
2359 c->dst.type = OP_NONE; /* Disable writeback. */
2360 }
111de5d6
AK		 2361 break;
2362 case 0xfb: /* sti */
f850e2e6
GN		 2363 if (emulator_bad_iopl(ctxt))
2364 kvm_inject_gp(ctxt->vcpu, 0);
2365 else {
2366 toggle_interruptibility(ctxt, X86_SHADOW_INT_STI);
2367 ctxt->eflags |= X86_EFLAGS_IF;
2368 c->dst.type = OP_NONE; /* Disable writeback. */
2369 }
111de5d6 2370 break;
fb4616f4
MG		 2371 case 0xfc: /* cld */
2372 ctxt->eflags &= ~EFLG_DF;
2373 c->dst.type = OP_NONE; /* Disable writeback. */
2374 break;
2375 case 0xfd: /* std */
2376 ctxt->eflags |= EFLG_DF;
2377 c->dst.type = OP_NONE; /* Disable writeback. */
2378 break;
018a98db
AK		 2379 case 0xfe ... 0xff: /* Grp4/Grp5 */
2380 rc = emulate_grp45(ctxt, ops);
2381 if (rc != 0)
2382 goto done;
2383 break;
6aa8b732 2384 }
018a98db
AK		 2385
2386writeback:
2387 rc = writeback(ctxt, ops);
2388 if (rc != 0)
2389 goto done;
2390
2391 /* Commit shadow register state. */
ad312c7c 2392 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 2393 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 2394
2395done:
2396 if (rc == X86EMUL_UNHANDLEABLE) {
2397 c->eip = saved_eip;
2398 return -1;
2399 }
2400 return 0;
6aa8b732
AK		 2401
2402twobyte_insn:
e4e03ded 2403 switch (c->b) {
6aa8b732 2404 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 2405 switch (c->modrm_reg) {
6aa8b732
AK		 2406 u16 size;
2407 unsigned long address;
2408
aca7f966 2409 case 0: /* vmcall */
e4e03ded 2410 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 2411 goto cannot_emulate;
2412
7aa81cc0
AL		 2413 rc = kvm_fix_hypercall(ctxt->vcpu);
2414 if (rc)
2415 goto done;
2416
33e3885d 2417 /* Let the processor re-execute the fixed hypercall */
5fdbf976 2418 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 2419 /* Disable writeback. */
2420 c->dst.type = OP_NONE;
aca7f966 2421 break;
6aa8b732 2422 case 2: /* lgdt */
e4e03ded
LV		 2423 rc = read_descriptor(ctxt, ops, c->src.ptr,
2424 &size, &address, c->op_bytes);
6aa8b732
AK		 2425 if (rc)
2426 goto done;
2427 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 2428 /* Disable writeback. */
2429 c->dst.type = OP_NONE;
6aa8b732 2430 break;
aca7f966 2431 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 2432 if (c->modrm_mod == 3) {
2433 switch (c->modrm_rm) {
2434 case 1:
2435 rc = kvm_fix_hypercall(ctxt->vcpu);
2436 if (rc)
2437 goto done;
2438 break;
2439 default:
2440 goto cannot_emulate;
2441 }
aca7f966 2442 } else {
e4e03ded 2443 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 2444 &size, &address,
e4e03ded 2445 c->op_bytes);
aca7f966
AL		 2446 if (rc)
2447 goto done;
2448 realmode_lidt(ctxt->vcpu, size, address);
2449 }
16286d08
AK		 2450 /* Disable writeback. */
2451 c->dst.type = OP_NONE;
6aa8b732
AK		 2452 break;
2453 case 4: /* smsw */
16286d08
AK		 2454 c->dst.bytes = 2;
2455 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 2456 break;
2457 case 6: /* lmsw */
16286d08
AK		 2458 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
2459 &ctxt->eflags);
dc7457ea 2460 c->dst.type = OP_NONE;
6aa8b732
AK		 2461 break;
2462 case 7: /* invlpg*/
e8d8d7fe 2463 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 2464 /* Disable writeback. */
2465 c->dst.type = OP_NONE;
6aa8b732
AK		 2466 break;
2467 default:
2468 goto cannot_emulate;
2469 }
2470 break;
e99f0507 2471 case 0x05: /* syscall */
e66bb2cc
AP		 2472 if (emulate_syscall(ctxt) == -1)
2473 goto cannot_emulate;
2474 else
2475 goto writeback;
e99f0507 2476 break;
018a98db
AK		 2477 case 0x06:
2478 emulate_clts(ctxt->vcpu);
2479 c->dst.type = OP_NONE;
2480 break;
2481 case 0x08: /* invd */
2482 case 0x09: /* wbinvd */
2483 case 0x0d: /* GrpP (prefetch) */
2484 case 0x18: /* Grp16 (prefetch/nop) */
2485 c->dst.type = OP_NONE;
2486 break;
2487 case 0x20: /* mov cr, reg */
2488 if (c->modrm_mod != 3)
2489 goto cannot_emulate;
2490 c->regs[c->modrm_rm] =
2491 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
2492 c->dst.type = OP_NONE; /* no writeback */
2493 break;
6aa8b732 2494 case 0x21: /* mov from dr to reg */
e4e03ded 2495 if (c->modrm_mod != 3)
6aa8b732 2496 goto cannot_emulate;
8cdbd2c9 2497 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 2498 if (rc)
2499 goto cannot_emulate;
2500 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2501 break;
018a98db
AK		 2502 case 0x22: /* mov reg, cr */
2503 if (c->modrm_mod != 3)
2504 goto cannot_emulate;
2505 realmode_set_cr(ctxt->vcpu,
2506 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2507 c->dst.type = OP_NONE;
2508 break;
6aa8b732 2509 case 0x23: /* mov from reg to dr */
e4e03ded 2510 if (c->modrm_mod != 3)
6aa8b732 2511 goto cannot_emulate;
e4e03ded
LV		 2512 rc = emulator_set_dr(ctxt, c->modrm_reg,
2513 c->regs[c->modrm_rm]);
a01af5ec
LV		 2514 if (rc)
2515 goto cannot_emulate;
2516 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2517 break;
018a98db
AK		 2518 case 0x30:
2519 /* wrmsr */
2520 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2521 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2522 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2523 if (rc) {
c1a5d4f9 2524 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2525 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2526 }
2527 rc = X86EMUL_CONTINUE;
2528 c->dst.type = OP_NONE;
2529 break;
2530 case 0x32:
2531 /* rdmsr */
2532 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2533 if (rc) {
c1a5d4f9 2534 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2535 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2536 } else {
2537 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2538 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2539 }
2540 rc = X86EMUL_CONTINUE;
2541 c->dst.type = OP_NONE;
2542 break;
e99f0507 2543 case 0x34: /* sysenter */
8c604352
AP		 2544 if (emulate_sysenter(ctxt) == -1)
2545 goto cannot_emulate;
2546 else
2547 goto writeback;
e99f0507
AP		 2548 break;
2549 case 0x35: /* sysexit */
4668f050
AP		 2550 if (emulate_sysexit(ctxt) == -1)
2551 goto cannot_emulate;
2552 else
2553 goto writeback;
e99f0507 2554 break;
6aa8b732 2555 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2556 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2557 if (!test_cc(c->b, ctxt->eflags))
2558 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2559 break;
b2833e3c 2560 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2561 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2562 jmp_rel(c, c->src.val);
018a98db
AK		 2563 c->dst.type = OP_NONE;
2564 break;
0934ac9d
MG		 2565 case 0xa0: /* push fs */
2566 emulate_push_sreg(ctxt, VCPU_SREG_FS);
2567 break;
2568 case 0xa1: /* pop fs */
2569 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
2570 if (rc != 0)
2571 goto done;
2572 break;
7de75248
NK		 2573 case 0xa3:
2574 bt: /* bt */
e4f8e039 2575 c->dst.type = OP_NONE;
e4e03ded
LV		 2576 /* only subword offset */
2577 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2578 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2579 break;
9bf8ea42
GT		 2580 case 0xa4: /* shld imm8, r, r/m */
2581 case 0xa5: /* shld cl, r, r/m */
2582 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2583 break;
0934ac9d
MG		 2584 case 0xa8: /* push gs */
2585 emulate_push_sreg(ctxt, VCPU_SREG_GS);
2586 break;
2587 case 0xa9: /* pop gs */
2588 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
2589 if (rc != 0)
2590 goto done;
2591 break;
7de75248
NK		 2592 case 0xab:
2593 bts: /* bts */
e4e03ded
LV		 2594 /* only subword offset */
2595 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2596 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2597 break;
9bf8ea42
GT		 2598 case 0xac: /* shrd imm8, r, r/m */
2599 case 0xad: /* shrd cl, r, r/m */
2600 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2601 break;
2a7c5b8b
GC		 2602 case 0xae: /* clflush */
2603 break;
6aa8b732
AK		 2604 case 0xb0 ... 0xb1: /* cmpxchg */
2605 /*
2606 * Save real source value, then compare EAX against
2607 * destination.
2608 */
e4e03ded
LV		 2609 c->src.orig_val = c->src.val;
2610 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2611 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2612 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2613 /* Success: write back to memory. */
e4e03ded 2614 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2615 } else {
2616 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2617 c->dst.type = OP_REG;
2618 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2619 }
2620 break;
6aa8b732
AK		 2621 case 0xb3:
2622 btr: /* btr */
e4e03ded
LV		 2623 /* only subword offset */
2624 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2625 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2626 break;
6aa8b732 2627 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2628 c->dst.bytes = c->op_bytes;
2629 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2630 : (u16) c->src.val;
6aa8b732 2631 break;
6aa8b732 2632 case 0xba: /* Grp8 */
e4e03ded 2633 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2634 case 0:
2635 goto bt;
2636 case 1:
2637 goto bts;
2638 case 2:
2639 goto btr;
2640 case 3:
2641 goto btc;
2642 }
2643 break;
7de75248
NK		 2644 case 0xbb:
2645 btc: /* btc */
e4e03ded
LV		 2646 /* only subword offset */
2647 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2648 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2649 break;
6aa8b732 2650 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2651 c->dst.bytes = c->op_bytes;
2652 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2653 (s16) c->src.val;
6aa8b732 2654 break;
a012e65a 2655 case 0xc3: /* movnti */
e4e03ded
LV		 2656 c->dst.bytes = c->op_bytes;
2657 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2658 (u64) c->src.val;
a012e65a 2659 break;
6aa8b732 2660 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2661 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2662 if (rc != 0)
2663 goto done;
018a98db 2664 c->dst.type = OP_NONE;
8cdbd2c9 2665 break;
6aa8b732
AK		 2666 }
2667 goto writeback;
2668
2669cannot_emulate:
e4e03ded 2670 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2671 c->eip = saved_eip;
6aa8b732
AK		 2672 return -1;
2673}
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